diff --git a/bsp/lm3s8962/Libraries/SConscript b/bsp/lm3s8962/Libraries/SConscript index ebf7b660c1..784d61658a 100644 --- a/bsp/lm3s8962/Libraries/SConscript +++ b/bsp/lm3s8962/Libraries/SConscript @@ -6,9 +6,13 @@ from building import * cwd = GetCurrentDir() src = Glob('driverlib/*.c') +# cortex-m3 no FPU. +if rtconfig.PART_TYPE.startswith('PART_LM4F') != True: + SrcRemove(src, 'fpu.c') + # add for startup script if rtconfig.CROSS_TOOL == 'gcc': - src += ['startup/gcc/startup_LPC17xx.s'] + src += ['startup/gcc/start_gcc.s'] elif rtconfig.CROSS_TOOL == 'keil': src += ['startup/arm/start_rvds.S'] elif rtconfig.CROSS_TOOL == 'iar': @@ -16,6 +20,7 @@ elif rtconfig.CROSS_TOOL == 'iar': CPPPATH = [cwd] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) +CPPDEFINES = [rtconfig.PART_TYPE] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/lm3s8962/Libraries/driverlib/adc.c b/bsp/lm3s8962/Libraries/driverlib/adc.c index d0729a8636..c306389a5b 100644 --- a/bsp/lm3s8962/Libraries/driverlib/adc.c +++ b/bsp/lm3s8962/Libraries/driverlib/adc.c @@ -2,7 +2,7 @@ // // adc.c - Driver for the ADC. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -33,6 +33,7 @@ #include "inc/hw_ints.h" #include "inc/hw_memmap.h" #include "inc/hw_types.h" +#include "inc/hw_sysctl.h" #include "driverlib/adc.h" #include "driverlib/debug.h" #include "driverlib/interrupt.h" @@ -46,6 +47,7 @@ #define ADC_SEQ (ADC_O_SSMUX0) #define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0) #define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0) +#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0) #define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0) #define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0) #define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0) @@ -70,10 +72,10 @@ static unsigned char g_pucOversampleFactor[3]; //! ADC sample sequence interrupt occurs. //! //! This function sets the handler to be called when a sample sequence -//! interrupt occurs. This will enable the global interrupt in the interrupt -//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It -//! is the interrupt handler's responsibility to clear the interrupt source via -//! ADCIntClear(). +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; the sequence interrupt must be enabled with +//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via ADCIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -117,9 +119,9 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This function unregisters the interrupt handler. This will disable the -//! global interrupt in the interrupt controller; the sequence interrupt must -//! be disabled via ADCIntDisable(). +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller; the sequence interrupt +//! must be disabled via ADCIntDisable(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -225,9 +227,9 @@ ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the specified sample sequence. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. +//! This function returns the interrupt status for the specified sample +//! sequence. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. //! //! \return The current raw or masked interrupt status. // @@ -257,7 +259,7 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum)); // - // If the digital comparator status bit is set, reflect it to the + // If the digital comparator status bit is set, reflect it to the // appropriate sequence bit. // if(ulTemp & 0x10000) @@ -281,17 +283,17 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulSequenceNum is the sample sequence number. //! //! The specified sample sequence interrupt is cleared, so that it no longer -//! asserts. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. +//! asserts. This function must be called in the interrupt handler to keep +//! the interrupt from being triggered again immediately upon exit. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -379,10 +381,10 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) //! respect to the other sample sequences. //! //! This function configures the initiation criteria for a sample sequence. -//! Valid sample sequences range from zero to three; sequence zero will capture -//! up to eight samples, sequences one and two will capture up to four samples, -//! and sequence three will capture a single sample. The trigger condition and -//! priority (with respect to other sample sequence execution) is set. +//! Valid sample sequencers range from zero to three; sequencer zero captures +//! up to eight samples, sequencers one and two capture up to four samples, +//! and sequencer three captures a single sample. The trigger condition and +//! priority (with respect to other sample sequencer execution) are set. //! //! The \e ulTrigger parameter can take on the following values: //! @@ -395,7 +397,9 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) //! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog //! comparator; configured with ComparatorConfigure(). //! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port -//! B4 pin. +//! B4 pin. Note that some microcontrollers can +//! select from any GPIO using the +//! GPIOADCTriggerEnable() function. //! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with //! TimerControlTrigger(). //! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; @@ -472,42 +476,40 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulSequenceNum is the sample sequence number. //! \param ulStep is the step to be configured. //! \param ulConfig is the configuration of this step; must be a logical OR of -//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the -//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts -//! with the digital comparator feature, the follow values may also be OR'd -//! into the \e ulConfig value to enable the digital comparater feature: -//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through -//! \b ADC_CTL_CMP7). +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of +//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). //! -//! This function will set the configuration of the ADC for one step of a -//! sample sequence. The ADC can be configured for single-ended or -//! differential operation (the \b ADC_CTL_D bit selects differential -//! operation when set), the channel to be sampled can be chosen (the -//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal -//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally, -//! this step can be defined as the last in the sequence (the \b ADC_CTL_END -//! bit) and it can be configured to cause an interrupt when the step is -//! complete (the \b ADC_CTL_IE bit). If the digital comparators are present -//! on the device, this step may also be configured send the ADC sample to -//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 -//! values) by using the \b ADC_CTL_CE bit. The configuration is used by the -//! ADC at the appropriate time when the trigger for this sequence occurs. +//! This function configures the ADC for one step of a sample sequence. The +//! ADC can be configured for single-ended or differential operation +//! (the \b ADC_CTL_D bit selects differential operation when set), the +//! channel to be sampled can be chosen (the \b ADC_CTL_CH0 through +//! \b ADC_CTL_CH23 values), and the internal temperature sensor can be +//! selected (the \b ADC_CTL_TS bit). Additionally, this step can be defined +//! as the last in the sequence (the \b ADC_CTL_END bit) and it can be +//! configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). If the digital comparators are present on the device, +//! this step may also be configured to send the ADC sample to the selected +//! comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration +//! is used by the ADC at the appropriate time when the trigger for +//! this sequence occurs. //! //! \note If the Digitial Comparator is present and enabled using the -//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC -//! sequence data FIFO. +//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT +//! written into the ADC sequence data FIFO. //! //! The \e ulStep parameter determines the order in which the samples are //! captured by the ADC when the trigger occurs. It can range from zero to -//! seven for the first sample sequence, from zero to three for the second and -//! third sample sequence, and can only be zero for the fourth sample sequence. +//! seven for the first sample sequencer, from zero to three for the second and +//! third sample sequencer, and can only be zero for the fourth sample +//! sequencer. //! //! Differential mode only works with adjacent channel pairs (for example, 0 //! and 1). The channel select must be the number of the channel pair to //! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 -//! and 3) or undefined results will be returned by the ADC. Additionally, if +//! and 3) or undefined results are returned by the ADC. Additionally, if //! differential mode is selected when the temperature sensor is being sampled, -//! undefined results will be returned by the ADC. +//! undefined results are returned by the ADC. //! //! It is the responsibility of the caller to ensure that a valid configuration //! is specified; this function does not check the validity of the specified @@ -549,6 +551,13 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, ~(0x0000000f << ulStep)) | ((ulConfig & 0x0f) << ulStep)); + // + // Set the upper bits of the analog mux value for this step. + // + HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf00) >> 8) << ulStep)); + // // Set the control value for this step. // @@ -595,9 +604,9 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This determines if a sample sequence overflow has occurred. This will -//! happen if the captured samples are not read from the FIFO before the next -//! trigger occurs. +//! This function determines if a sample sequence overflow has occurred. +//! Overflow happens if the captured samples are not read from the FIFO before +//! the next trigger occurs. //! //! \return Returns zero if there was not an overflow, and non-zero if there //! was. @@ -625,9 +634,9 @@ ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This will clear an overflow condition on one of the sample sequences. The -//! overflow condition must be cleared in order to detect a subsequent overflow -//! condition (it otherwise causes no harm). +//! This function clears an overflow condition on one of the sample sequences. +//! The overflow condition must be cleared in order to detect a subsequent +//! overflow condition (it otherwise causes no harm). //! //! \return None. // @@ -654,8 +663,8 @@ ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This determines if a sample sequence underflow has occurred. This will -//! happen if too many samples are read from the FIFO. +//! This function determines if a sample sequence underflow has occurred. +//! Underflow happens if too many samples are read from the FIFO. //! //! \return Returns zero if there was not an underflow, and non-zero if there //! was. @@ -683,8 +692,8 @@ ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This will clear an underflow condition on one of the sample sequences. The -//! underflow condition must be cleared in order to detect a subsequent +//! This function clears an underflow condition on one of the sample sequencers. +//! The underflow condition must be cleared in order to detect a subsequent //! underflow condition (it otherwise causes no harm). //! //! \return None. @@ -713,12 +722,12 @@ ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulSequenceNum is the sample sequence number. //! \param pulBuffer is the address where the data is stored. //! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer. The number of samples available in the hardware -//! FIFO are copied into the buffer, which is assumed to be large enough to -//! hold that many samples. This will only return the samples that are -//! presently available, which may not be the entire sample sequence if it is -//! in the process of being executed. +//! This function copies data from the specified sample sequencer output FIFO +//! to a memory resident buffer. The number of samples available in the +//! hardware FIFO are copied into the buffer, which is assumed to be large +//! enough to hold that many samples. This function only returns the samples +//! that are presently available, which may not be the entire sample sequence +//! if it is in the process of being executed. //! //! \return Returns the number of samples copied to the buffer. // @@ -794,8 +803,8 @@ ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) // // Generate a processor trigger for this sample sequence. // - HWREG(ulBase + ADC_O_PSSI) = ((ulSequenceNum & 0xffff0000) | - (1 << (ulSequenceNum & 0xf))); + HWREG(ulBase + ADC_O_PSSI) |= ((ulSequenceNum & 0xffff0000) | + (1 << (ulSequenceNum & 0xf))); } //***************************************************************************** @@ -905,6 +914,13 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase, ~(0x0000000f << ulStep)) | ((ulConfig & 0x0f) << ulStep)); + // + // Set the upper bits of the analog mux value for this step. + // + HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf00) >> 8) << ulStep)); + // // Set the control value for this step. // @@ -936,9 +952,9 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase, //! This function copies data from the specified sample sequence output FIFO to //! a memory resident buffer with software oversampling applied. The requested //! number of samples are copied into the data buffer; if there are not enough -//! samples in the hardware FIFO to satisfy this many oversampled data items -//! then incorrect results will be returned. It is the caller's responsibility -//! to read only the samples that are available and wait until enough data is +//! samples in the hardware FIFO to satisfy this many oversampled data items, +//! then incorrect results are returned. It is the caller's responsibility to +//! read only the samples that are available and wait until enough data is //! available, for example as a result of receiving an interrupt. //! //! \return None. @@ -999,21 +1015,18 @@ ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, //! be used to provide better resolution on the sampled data. Oversampling is //! accomplished by averaging multiple samples from the same analog input. Six //! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. -//! Specifying an oversampling factor of zero will disable hardware +//! Specifying an oversampling factor of zero disables hardware //! oversampling. //! //! Hardware oversampling applies uniformly to all sample sequencers. It does //! not reduce the depth of the sample sequencers like the software -//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! oversampling APIs; each sample written into the sample sequencer FIFO is a //! fully oversampled analog input reading. //! //! Enabling hardware averaging increases the precision of the ADC at the cost //! of throughput. For example, enabling 4x oversampling reduces the //! throughput of a 250 Ksps ADC to 62.5 Ksps. //! -//! \note Hardware oversampling is available beginning with Rev C0 of the -//! Stellaris microcontroller. -//! //! \return None. // //***************************************************************************** @@ -1051,7 +1064,7 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor) //! \param ulComp is the index of the comparator to configure. //! \param ulConfig is the configuration of the comparator. //! -//! This function will configure a comparator. The \e ulConfig parameter is +//! This function configures a comparator. The \e ulConfig parameter is //! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and //! \b ADC_COMP_INT_xxx values. //! @@ -1178,7 +1191,7 @@ ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp, //! \param bInterrupt is the flag to indicate reset of Interrupt conditions. //! //! Because the digital comparator uses current and previous ADC values, this -//! function is provide to allow the comparator to be reset to its initial +//! function allows the comparator to be reset to its initial //! value to prevent stale data from being used when a sequence is enabled. //! //! \return None. @@ -1272,8 +1285,8 @@ ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) //! //! \param ulBase is the base address of the ADC module. //! -//! This returns the digitial comparator interrupt status bits. This status -//! is sequence agnostic. +//! This function returns the digitial comparator interrupt status bits. This +//! status is sequence agnostic. //! //! \return The current comparator interrupt status. // @@ -1326,10 +1339,12 @@ ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus) //! \param ulRef is the reference to use. //! //! The ADC reference is set as specified by \e ulRef. It must be one of -//! \b ADC_REF_INT or \b ADC_REF_EXT_3V, for internal or external reference. -//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and -//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then a 3V -//! reference must be supplied to the AVREF pin. +//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or +//! external reference. If \b ADC_REF_INT is chosen, then an internal 3V +//! reference is used and no external reference is needed. If +//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the +//! AVREF pin. If \b ADC_REF_EXT_1V is chosen, then a 1V external referece +//! must be supplied to the AVREF pin. //! //! \note The ADC reference can only be selected on parts that have an external //! reference. Consult the data sheet for your part to determine if there is @@ -1345,12 +1360,13 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef) // Check the arguments. // ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); - ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V)); + ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V) || + (ulRef == ADC_REF_EXT_1V)); // // Set the reference. // - HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) | + HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ulRef; } @@ -1360,8 +1376,8 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef) //! //! \param ulBase is the base address of the ADC module. //! -//! Returns the value of the ADC reference setting. The returned value will be -//! one of \b ADC_REF_INT or \b ADC_REF_EXT_3V. +//! Returns the value of the ADC reference setting. The returned value is one +//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V. //! //! \note The value returned by this function is only meaningful if used on a //! part that is capable of using an external reference. Consult the data @@ -1381,7 +1397,71 @@ ADCReferenceGet(unsigned long ulBase) // // Return the value of the reference. // - return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF); + return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF_M); +} + +//***************************************************************************** +// +//! Selects the ADC resolution. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulResolution is the ADC bit resolution. +//! +//! The ADC resolution is set as specified by \e ulResolution. It must be one +//! of \b ADC_RES_12BIT or \b ADC_RES_10BIT. +//! +//! \note The ADC resolution can only be set on parts that are capable of +//! changing ADC resolution mode. Consult the data sheet for your part to +//! determine if it is capable of operating in more than one resolution mode. +//! +//! \return None. +// +//***************************************************************************** +void +ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT((ulResolution == ADC_RES_10BIT) || (ulResolution == ADC_RES_12BIT)); + + // + // Set the resolution. + // + HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) | + ulResolution; +} + +//***************************************************************************** +// +//! Gets the setting of ADC resolution. +//! +//! \param ulBase is the base address of the ADC module. +//! +//! The ADC resolution is returned as one of \b ADC_RES_12BIT or +//! \b ADC_RES_10BIT. +//! +//! \note The value returned by this function is only meaningful if used on a +//! part that is capable of changing ADC resolution mode. Consult the +//! data sheet for your part to determine if it is capable of operating in +//! more than one resolution mode. +//! +//! \return The current setting of the ADC resolution. +// +//***************************************************************************** +unsigned long +ADCResolutionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + + // + // Get the resolution and return it to the caller. + // + return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_RES); } //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/adc.h b/bsp/lm3s8962/Libraries/driverlib/adc.h index 4b70cf97d1..ea1a734e50 100644 --- a/bsp/lm3s8962/Libraries/driverlib/adc.h +++ b/bsp/lm3s8962/Libraries/driverlib/adc.h @@ -2,7 +2,7 @@ // // adc.h - ADC headers for using the ADC driver functions. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -80,6 +80,14 @@ extern "C" #define ADC_CTL_CH13 0x0000000D // Input channel 13 #define ADC_CTL_CH14 0x0000000E // Input channel 14 #define ADC_CTL_CH15 0x0000000F // Input channel 15 +#define ADC_CTL_CH16 0x00000100 // Input channel 16 +#define ADC_CTL_CH17 0x00000101 // Input channel 17 +#define ADC_CTL_CH18 0x00000102 // Input channel 18 +#define ADC_CTL_CH19 0x00000103 // Input channel 19 +#define ADC_CTL_CH20 0x00000104 // Input channel 20 +#define ADC_CTL_CH21 0x00000105 // Input channel 21 +#define ADC_CTL_CH22 0x00000106 // Input channel 22 +#define ADC_CTL_CH23 0x00000107 // Input channel 23 #define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 #define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 #define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 @@ -173,6 +181,15 @@ extern "C" //***************************************************************************** #define ADC_REF_INT 0x00000000 // Internal reference #define ADC_REF_EXT_3V 0x00000001 // External 3V reference +#define ADC_REF_EXT_1V 0x00000003 // External 1V reference + +//***************************************************************************** +// +// Values that can be passed to ADCResolutionSet as the ulResolution parameter. +// +//***************************************************************************** +#define ADC_RES_10BIT 0x00000000 // 10-bit resolution +#define ADC_RES_12BIT 0x00000010 // 12-bit resolution //***************************************************************************** // @@ -243,6 +260,8 @@ extern void ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus); extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef); extern unsigned long ADCReferenceGet(unsigned long ulBase); +extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution); +extern unsigned long ADCResolutionGet(unsigned long ulBase); extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase); extern unsigned long ADCPhaseDelayGet(unsigned long ulBase); diff --git a/bsp/lm3s8962/Libraries/driverlib/can.c b/bsp/lm3s8962/Libraries/driverlib/can.c index 6acb1193c7..e0f5f7ee18 100644 --- a/bsp/lm3s8962/Libraries/driverlib/can.c +++ b/bsp/lm3s8962/Libraries/driverlib/can.c @@ -2,7 +2,7 @@ // // can.c - Driver for the CAN module. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -151,8 +151,8 @@ CANBaseValid(unsigned long ulBase) //! //! \param ulBase is the base address of the selected CAN controller //! -//! Given a CAN controller base address, returns the corresponding interrupt -//! number. +//! Given a CAN controller base address, this function returns the +//! corresponding interrupt number. //! //! This function replaces the original CANGetIntNumber() API and performs the //! same actions. A macro is provided in can.h to map the original @@ -233,7 +233,7 @@ CANIntNumberGet(unsigned long ulBase) static unsigned long CANRegRead(unsigned long ulRegAddress) { - volatile int iDelay; + volatile unsigned long ulDelay; unsigned long ulRetVal; unsigned long ulIntNumber; unsigned long ulReenableInts; @@ -271,7 +271,7 @@ CANRegRead(unsigned long ulRegAddress) // // This delay is necessary for the CAN have the correct data on the bus. // - for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++) + for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++) { } @@ -317,7 +317,7 @@ CANRegRead(unsigned long ulRegAddress) static void CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue) { - volatile int iDelay; + volatile unsigned long ulDelay; // // Trigger the initial write to the CAN controller. The value will not make @@ -328,7 +328,7 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue) // // Delay to allow the CAN controller to receive the new data. // - for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++) + for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++) { } } @@ -360,29 +360,29 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue) // //***************************************************************************** static void -CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize) +CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, + unsigned long ulSize) { - int iIdx; - unsigned long ulValue; + unsigned long ulIdx, ulValue; // // Loop always copies 1 or 2 bytes per iteration. // - for(iIdx = 0; iIdx < iSize; ) + for(ulIdx = 0; ulIdx < ulSize; ) { // // Write out the data 16 bits at a time since this is how the registers // are aligned in memory. // - ulValue = pucData[iIdx++]; + ulValue = pucData[ulIdx++]; // // Only write the second byte if needed otherwise it will be zero. // - if(iIdx < iSize) + if(ulIdx < ulSize) { - ulValue |= (pucData[iIdx++] << 8); + ulValue |= (pucData[ulIdx++] << 8); } CANRegWrite((unsigned long)(pulRegister++), ulValue); } @@ -415,15 +415,15 @@ CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize) // //***************************************************************************** static void -CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize) +CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, + unsigned long ulSize) { - int iIdx; - unsigned long ulValue; + unsigned long ulIdx, ulValue; // // Loop always copies 1 or 2 bytes per iteration. // - for(iIdx = 0; iIdx < iSize; ) + for(ulIdx = 0; ulIdx < ulSize; ) { // // Read out the data 16 bits at a time since this is how the registers @@ -434,14 +434,14 @@ CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize) // // Store the first byte. // - pucData[iIdx++] = (unsigned char)ulValue; + pucData[ulIdx++] = (unsigned char)ulValue; // // Only read the second byte if needed. // - if(iIdx < iSize) + if(ulIdx < ulSize) { - pucData[iIdx++] = (unsigned char)(ulValue >> 8); + pucData[ulIdx++] = (unsigned char)(ulValue >> 8); } } } @@ -465,7 +465,7 @@ CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize) void CANInit(unsigned long ulBase) { - int iMsg; + unsigned long ulMsg; // // Check the arguments. @@ -499,7 +499,7 @@ CANInit(unsigned long ulBase) // // Loop through to program all 32 message objects // - for(iMsg = 1; iMsg <= 32; iMsg++) + for(ulMsg = 1; ulMsg <= 32; ulMsg++) { // // Wait for busy bit to clear @@ -511,7 +511,7 @@ CANInit(unsigned long ulBase) // // Initiate programming the message object // - CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg); + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg); } // @@ -524,7 +524,7 @@ CANInit(unsigned long ulBase) // // Loop through to program all 32 message objects // - for(iMsg = 1; iMsg <= 32; iMsg++) + for(ulMsg = 1; ulMsg <= 32; ulMsg++) { // // Wait for busy bit to clear. @@ -536,7 +536,7 @@ CANInit(unsigned long ulBase) // // Initiate programming the message object // - CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg); + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg); } // @@ -552,7 +552,7 @@ CANInit(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller to enable. //! //! Enables the CAN controller for message processing. Once enabled, the -//! controller will automatically transmit any pending frames, and process any +//! controller automatically transmits any pending frames, and processes any //! received frames. The controller can be stopped by calling CANDisable(). //! Prior to calling CANEnable(), CANInit() should have been called to //! initialize the controller and the CAN bus clock should be configured by @@ -583,7 +583,7 @@ CANEnable(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller to disable. //! //! Disables the CAN controller for message processing. When disabled, the -//! controller will no longer automatically process data on the CAN bus. The +//! controller no longer automatically processes data on the CAN bus. The //! controller can be restarted by calling CANEnable(). The state of the CAN //! controller and the message objects in the controller are left as they were //! before this call was made. @@ -614,7 +614,7 @@ CANDisable(unsigned long ulBase) //! \param pClkParms is a pointer to a structure to hold the timing parameters. //! //! This function reads the current configuration of the CAN controller bit -//! clock timing, and stores the resulting information in the structure +//! clock timing and stores the resulting information in the structure //! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the //! values that are returned in the structure pointed to by \e pClkParms. //! @@ -628,7 +628,7 @@ CANDisable(unsigned long ulBase) void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms) { - unsigned int uBitReg; + unsigned long ulBitReg; // // Check the arguments. @@ -639,53 +639,53 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms) // // Read out all the bit timing values from the CAN controller registers. // - uBitReg = CANRegRead(ulBase + CAN_O_BIT); + ulBitReg = CANRegRead(ulBase + CAN_O_BIT); // // Set the phase 2 segment. // - pClkParms->uPhase2Seg = - ((uBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1; + pClkParms->ulPhase2Seg = + ((ulBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1; // // Set the phase 1 segment. // - pClkParms->uSyncPropPhase1Seg = - ((uBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1; + pClkParms->ulSyncPropPhase1Seg = + ((ulBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1; // // Set the synchronous jump width. // - pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1; + pClkParms->ulSJW = ((ulBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1; // // Set the pre-divider for the CAN bus bit clock. // - pClkParms->uQuantumPrescaler = - ((uBitReg & CAN_BIT_BRP_M) | + pClkParms->ulQuantumPrescaler = + ((ulBitReg & CAN_BIT_BRP_M) | ((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1; } //***************************************************************************** // -//! This function is used to set the CAN bit timing values to a nominal setting -//! based on a desired bit rate. +//! Sets the CAN bit timing values to a nominal setting based on a desired +//! bit rate. //! //! \param ulBase is the base address of the CAN controller. //! \param ulSourceClock is the system clock for the device in Hz. //! \param ulBitRate is the desired bit rate. //! -//! This function will set the CAN bit timing for the bit rate passed in the -//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Since the -//! CAN clock is based off of the system clock the calling function should pass +//! This function sets the CAN bit timing for the bit rate passed in the +//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Because the +//! CAN clock is based off of the system clock, the calling function should pass //! in the source clock rate either by retrieving it from SysCtlClockGet() or //! using a specific value in Hz. The CAN bit timing is calculated assuming a -//! minimal amount of propagation delay, which will work for most cases where +//! minimal amount of propagation delay, which works for most cases where //! the network length is short. If tighter timing requirements or longer //! network lengths are needed, then the CANBitTimingSet() function is //! available for full customization of all of the CAN bit timing values. -//! Since not all bit rates can be matched exactly, the bit rate is set to the -//! value closest to the desired bit rate without being higher than the +//! Because not all bit rates can be matched exactly, the bit rate is set to +//! the value closest to the desired bit rate without being higher than the //! \e ulBitRate value. //! //! \note On some devices the source clock is fixed at 8MHz so the @@ -826,27 +826,27 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock, //! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and //! the Synchronization Jump Width. The values for Propagation and Phase //! Buffer 1 segments are derived from the combination -//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined -//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along -//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual -//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value, +//! \e pClkParms->ulSyncPropPhase1Seg parameter. Phase Buffer 2 is determined +//! from the \e pClkParms->ulPhase2Seg parameter. These two parameters, along +//! with \e pClkParms->ulSJW are based in units of bit time quanta. The actual +//! quantum time is determined by the \e pClkParms->ulQuantumPrescaler value, //! which specifies the divisor for the CAN module clock. //! -//! The total bit time, in quanta, will be the sum of the two Seg parameters, +//! The total bit time, in quanta, is the sum of the two Seg parameters, //! as follows: //! -//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1 +//! bit_time_q = ulSyncPropPhase1Seg + ulPhase2Seg + 1 //! -//! Note that the Sync_Seg is always one quantum in duration, and will be added +//! Note that the Sync_Seg is always one quantum in duration, and is added //! to derive the correct duration of Prop_Seg and Phase1_Seg. //! //! The equation to determine the actual bit rate is as follows: //! //! CAN Clock / -//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler)) +//! ((\e ulSyncPropPhase1Seg + \e ulPhase2Seg + 1) * (\e ulQuantumPrescaler)) //! -//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1, -//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be +//! Thus with \e ulSyncPropPhase1Seg = 4, \e ulPhase2Seg = 1, +//! \e ulQuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is //! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. //! //! This function replaces the original CANSetBitTiming() API and performs the @@ -859,8 +859,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock, void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms) { - unsigned int uBitReg; - unsigned int uSavedInit; + unsigned long ulBitReg, ulSavedInit; // // Check the arguments. @@ -871,63 +870,63 @@ CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms) // // The phase 1 segment must be in the range from 2 to 16. // - ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) && - (pClkParms->uSyncPropPhase1Seg <= 16)); + ASSERT((pClkParms->ulSyncPropPhase1Seg >= 2) && + (pClkParms->ulSyncPropPhase1Seg <= 16)); // // The phase 2 segment must be in the range from 1 to 8. // - ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8)); + ASSERT((pClkParms->ulPhase2Seg >= 1) && (pClkParms->ulPhase2Seg <= 8)); // // The synchronous jump windows must be in the range from 1 to 4. // - ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4)); + ASSERT((pClkParms->ulSJW >= 1) && (pClkParms->ulSJW <= 4)); // // The CAN clock pre-divider must be in the range from 1 to 1024. // - ASSERT((pClkParms->uQuantumPrescaler <= 1024) && - (pClkParms->uQuantumPrescaler >= 1)); + ASSERT((pClkParms->ulQuantumPrescaler <= 1024) && + (pClkParms->ulQuantumPrescaler >= 1)); // // To set the bit timing register, the controller must be placed in init // mode (if not already), and also configuration change bit enabled. State // of the init bit should be saved so it can be restored at the end. // - uSavedInit = CANRegRead(ulBase + CAN_O_CTL); - CANRegWrite(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE); + ulSavedInit = CANRegRead(ulBase + CAN_O_CTL); + CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit | CAN_CTL_INIT | CAN_CTL_CCE); // // Set the bit fields of the bit timing register according to the parms. // - uBitReg = (((pClkParms->uPhase2Seg - 1) << CAN_BIT_TSEG2_S) & - CAN_BIT_TSEG2_M); - uBitReg |= (((pClkParms->uSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) & - CAN_BIT_TSEG1_M); - uBitReg |= ((pClkParms->uSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M; - uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M; - CANRegWrite(ulBase + CAN_O_BIT, uBitReg); + ulBitReg = (((pClkParms->ulPhase2Seg - 1) << CAN_BIT_TSEG2_S) & + CAN_BIT_TSEG2_M); + ulBitReg |= (((pClkParms->ulSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) & + CAN_BIT_TSEG1_M); + ulBitReg |= ((pClkParms->ulSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M; + ulBitReg |= (pClkParms->ulQuantumPrescaler - 1) & CAN_BIT_BRP_M; + CANRegWrite(ulBase + CAN_O_BIT, ulBitReg); // // Set the divider upper bits in the extension register. // CANRegWrite(ulBase + CAN_O_BRPE, - ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M); + ((pClkParms->ulQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M); // // Clear the config change bit, and restore the init bit. // - uSavedInit &= ~CAN_CTL_CCE; + ulSavedInit &= ~CAN_CTL_CCE; // // If Init was not set before, then clear it. // - if(uSavedInit & CAN_CTL_INIT) + if(ulSavedInit & CAN_CTL_INIT) { - uSavedInit &= ~CAN_CTL_INIT; + ulSavedInit &= ~CAN_CTL_INIT; } - CANRegWrite(ulBase + CAN_O_CTL, uSavedInit); + CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit); } //***************************************************************************** @@ -988,7 +987,7 @@ CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! \param ulBase is the base address of the controller. //! //! This function unregisters the previously registered interrupt handler and -//! disables the interrupt on the interrupt controller. +//! disables the interrupt in the interrupt controller. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1011,15 +1010,15 @@ CANIntUnregister(unsigned long ulBase) // ulIntNumber = CANIntNumberGet(ulBase); - // - // Register the interrupt handler. - // - IntUnregister(ulIntNumber); - // // Disable the CAN interrupt. // IntDisable(ulIntNumber); + + // + // Register the interrupt handler. + // + IntUnregister(ulIntNumber); } //***************************************************************************** @@ -1029,8 +1028,8 @@ CANIntUnregister(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables specific interrupt sources of the CAN controller. Only enabled -//! sources will cause a processor interrupt. +//! This function enables specific interrupt sources of the CAN controller. +//! Only enabled sources cause a processor interrupt. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! @@ -1044,7 +1043,7 @@ CANIntUnregister(unsigned long ulBase) //! an interrupt, that message object must have interrupts enabled (see //! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the //! controller enters the ``bus off'' condition, or if the error counters reach -//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few +//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few //! status conditions and may provide more interrupts than the application //! needs to handle. When an interrupt occurs, use CANIntStatus() to determine //! the cause. @@ -1107,19 +1106,19 @@ CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase is the base address of the CAN controller. //! \param eIntStsReg indicates which interrupt status register to read //! -//! Returns the value of one of two interrupt status registers. The interrupt -//! status register read is determined by the \e eIntStsReg parameter, which -//! can have one of the following values: +//! This function returns the value of one of two interrupt status registers. +//! The interrupt status register read is determined by the \e eIntStsReg +//! parameter, which can have one of the following values: //! //! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt //! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message //! objects //! //! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register -//! and indicates the cause of the interrupt. It will be a value of +//! and indicates the cause of the interrupt. The value returned is //! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, //! the status register should be read with the CANStatusGet() function. -//! Calling this function to read the status will also clear the status +//! Calling this function to read the status also clears the status //! interrupt. If the value of the interrupt register is in the range 1-32, //! then this indicates the number of the highest priority message object that //! has an interrupt pending. The message object interrupt can be cleared by @@ -1129,9 +1128,9 @@ CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! cleared before returning from the interrupt. //! //! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects -//! have pending interrupts. This can be used to discover all of the pending -//! interrupts at once, as opposed to repeatedly reading the interrupt register -//! by using \b CAN_INT_STS_CAUSE. +//! have pending interrupts. This value can be used to discover all of the +//! pending interrupts at once, as opposed to repeatedly reading the interrupt +//! register by using \b CAN_INT_STS_CAUSE. //! //! \return Returns the value of one of the interrupt status registers. // @@ -1185,6 +1184,7 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg) break; } } + // // Return the interrupt status value // @@ -1205,21 +1205,21 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg) //! - 1-32 - Clears the specified message object interrupt //! //! It is not necessary to use this function to clear an interrupt. This -//! should only be used if the application wants to clear an interrupt source -//! without taking the normal interrupt action. +//! function should only be used if the application wants to clear an interrupt +//! source without taking the normal interrupt action. //! //! Normally, the status interrupt is cleared by reading the controller status //! using CANStatusGet(). A specific message object interrupt is normally //! cleared by reading the message object using CANMessageGet(). //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1277,9 +1277,9 @@ CANIntClear(unsigned long ulBase, unsigned long ulIntClr) //! \param ulBase is the base address of the CAN controller. //! \param bAutoRetry enables automatic retransmission. //! -//! Enables or disables automatic retransmission of messages with detected -//! errors. If \e bAutoRetry is \b true, then automatic retransmission is -//! enabled, otherwise it is disabled. +//! This function enables or disables automatic retransmission of messages with +//! detected errors. If \e bAutoRetry is \b true, then automatic retransmission +//! is enabled, otherwise it is disabled. //! //! \return None. // @@ -1326,7 +1326,7 @@ CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry) //! //! \param ulBase is the base address of the CAN controller. //! -//! Reads the current setting for the automatic retransmission in the CAN +//! This function reads the current setting for automatic retransmission in the CAN //! controller and returns it to the caller. //! //! \return Returns \b true if automatic retransmission is enabled, \b false @@ -1365,7 +1365,8 @@ CANRetryGet(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller. //! \param eStatusReg is the status register to read. //! -//! Reads a status register of the CAN controller and returns it to the caller. +//! This function reads a status register of the CAN controller and returns it +//! to the caller. //! The different status registers are: //! //! - \b CAN_STS_CONTROL - the main controller status @@ -1374,9 +1375,9 @@ CANRetryGet(unsigned long ulBase) //! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration //! //! When reading the main controller status register, a pending status -//! interrupt will be cleared. This should be used in the interrupt handler -//! for the CAN controller if the cause is a status interrupt. The controller -//! status register fields are as follows: +//! interrupt is cleared. This parameter should be used in the interrupt +//! handler for the CAN controller if the cause is a status interrupt. The +//! controller status register fields are as follows: //! //! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition //! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 @@ -1396,20 +1397,21 @@ CANRetryGet(unsigned long ulBase) //! dominant mode //! - \b CAN_STATUS_LEC_CRC - CRC error in received message //! -//! The remaining status registers are 32-bit bit maps to the message objects. -//! They can be used to quickly obtain information about the status of all the -//! message objects without needing to query each one. They contain the -//! following information: +//! The remaining status registers consist of 32-bit-wide bit maps to the +//! message objects. They can be used to quickly obtain information about the +//! status of all the message objects without needing to query each one. They +//! contain the following information: //! -//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that -//! means that a transmission is pending on that object. The application can -//! use this to determine which objects are still waiting to send a message. -//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means -//! that a new message has been received in that object, and has not yet been -//! picked up by the host application -//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means -//! it has a valid configuration programmed. The host application can use this -//! to determine which message objects are empty/unused. +//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a +//! transmission is pending on that object. The application can use this +//! information to determine which objects are still waiting to send a +//! message. +//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new +//! message has been received in that object, and has not yet been picked up +//! by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object +//! has a valid configuration programmed. The host application can use this +//! information to determine which message objects are empty/unused. //! //! \return Returns the value of the status register. // @@ -1488,14 +1490,14 @@ CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg) //! \param pulRxCount is a pointer to storage for the receive error counter. //! \param pulTxCount is a pointer to storage for the transmit error counter. //! -//! Reads the error counter register and returns the transmit and receive error -//! counts to the caller along with a flag indicating if the controller receive -//! counter has reached the error passive limit. The values of the receive and -//! transmit error counters are returned through the pointers provided as -//! parameters. +//! This function reads the error counter register and returns the transmit and +//! receive error counts to the caller along with a flag indicating if the +//! controller receive counter has reached the error passive limit. The values +//! of the receive and transmit error counters are returned through the pointers +//! provided as parameters. //! -//! After this call, \e *pulRxCount will hold the current receive error count -//! and \e *pulTxCount will hold the current transmit error count. +//! After this call, \e *pulRxCount holds the current receive error count +//! and \e *pulTxCount holds the current transmit error count. //! //! \return Returns \b true if the receive error count has reached the error //! passive limit, and \b false if the error count is below the error passive @@ -1542,10 +1544,10 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! \param eMsgType indicates the type of message for this object. //! //! This function is used to configure any one of the 32 message objects in the -//! CAN controller. A message object can be configured as any type of CAN -//! message object as well as several options for automatic transmission and -//! reception. This call also allows the message object to be configured to -//! generate interrupts on completion of message receipt or transmission. The +//! CAN controller. A message object can be configured to be any type of CAN +//! message object as well as to use automatic transmission and reception. +//! This call also allows the message object to be configured to generate +//! interrupts on completion of message receipt or transmission. The //! message object can also be configured with a filter/mask so that actions //! are only taken when a message that meets certain parameters is seen on the //! CAN bus. @@ -1570,13 +1572,13 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. //! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the //! identifier mask specified by \e ulMsgIDMask. -//! - \e ulMsgLen - the number of bytes in the message data. This should be -//! non-zero even for a remote frame; it should match the expected bytes of the -//! data responding data frame. +//! - \e ulMsgLen - the number of bytes in the message data. This parameter +//! should be non-zero even for a remote frame; it should match the expected +//! bytes of data in the responding data frame. //! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a //! data frame. //! -//! \b Example: To send a data frame or remote frame(in response to a remote +//! \b Example: To send a data frame or remote frame (in response to a remote //! request), take the following steps: //! //! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. @@ -1598,7 +1600,7 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! -# Set \e pMsgObject->ulFlags as follows: //! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data frame //! is received. -//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based filtering. //! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data //! frame. //! -# The buffer pointed to by \e pMsgObject->pucMsgData is not used by this @@ -1606,7 +1608,7 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! -# Call this function with \e ulObjID set to one of the 32 object buffers. //! //! If you specify a message object buffer that already contains a message -//! definition, it will be overwritten. +//! definition, it is overwritten. //! //! \return None. // @@ -1928,11 +1930,9 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID, CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl); // - // Transfer the message object to the message object specifiec by ulObjID. + // Transfer the message object to the message object specified by ulObjID. // CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); - - return; } //***************************************************************************** @@ -1946,27 +1946,27 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID, //! cleared. //! //! This function is used to read the contents of one of the 32 message objects -//! in the CAN controller, and return it to the caller. The data returned is +//! in the CAN controller and return it to the caller. The data returned is //! stored in the fields of the caller-supplied structure pointed to by //! \e pMsgObject. The data consists of all of the parts of a CAN message, //! plus some control and status information. //! -//! Normally this is used to read a message object that has received and stored -//! a CAN message with a certain identifier. However, this could also be used -//! to read the contents of a message object in order to load the fields of the -//! structure in case only part of the structure needs to be changed from a -//! previous setting. +//! Normally, this function is used to read a message object that has received +//! and stored a CAN message with a certain identifier. However, this function +//! could also be used to read the contents of a message object in order to +//! load the fields of the structure in case only part of the structure must +//! be changed from a previous setting. //! -//! When using CANMessageGet, all of the same fields of the structure are +//! When using CANMessageGet(), all of the same fields of the structure are //! populated in the same way as when the CANMessageSet() function is used, //! with the following exceptions: //! //! \e pMsgObject->ulFlags: //! -//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it +//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it //! was read //! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on -//! this message object, and not read by the host before being overwritten. +//! this message object and not read by the host before being overwritten. //! //! \return None. // @@ -2206,8 +2206,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID, //! \param ulObjID is the message object number to disable (1-32). //! //! This function frees the specified message object from use. Once a message -//! object has been ``cleared,'' it will no longer automatically send or -//! receive messages, or generate interrupts. +//! object has been ``cleared,'' it no longer automatically sends or +//! receives messages, nor does it generate interrupts. //! //! \return None. // diff --git a/bsp/lm3s8962/Libraries/driverlib/can.h b/bsp/lm3s8962/Libraries/driverlib/can.h index 4913c934ba..369a4f009a 100644 --- a/bsp/lm3s8962/Libraries/driverlib/can.h +++ b/bsp/lm3s8962/Libraries/driverlib/can.h @@ -2,7 +2,7 @@ // // can.h - Defines and Macros for the CAN controller. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -179,25 +179,25 @@ typedef struct //! Buffer 1 segments, measured in time quanta. The valid values for this //! setting range from 2 to 16. // - unsigned int uSyncPropPhase1Seg; + unsigned long ulSyncPropPhase1Seg; // //! This value holds the Phase Buffer 2 segment in time quanta. The valid //! values for this setting range from 1 to 8. // - unsigned int uPhase2Seg; + unsigned long ulPhase2Seg; // //! This value holds the Resynchronization Jump Width in time quanta. The //! valid values for this setting range from 1 to 4. // - unsigned int uSJW; + unsigned long ulSJW; // //! This value holds the CAN_CLK divider used to determine time quanta. //! The valid values for this setting range from 1 to 1023. // - unsigned int uQuantumPrescaler; + unsigned long ulQuantumPrescaler; } tCANBitClkParms; diff --git a/bsp/lm3s8962/Libraries/driverlib/comp.c b/bsp/lm3s8962/Libraries/driverlib/comp.c index 0872256dfe..0ed7d8377d 100644 --- a/bsp/lm3s8962/Libraries/driverlib/comp.c +++ b/bsp/lm3s8962/Libraries/driverlib/comp.c @@ -2,7 +2,7 @@ // // comp.c - Driver for the analog comparator. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -45,8 +45,8 @@ //! \param ulComp is the index of the comparator to configure. //! \param ulConfig is the configuration of the comparator. //! -//! This function will configure a comparator. The \e ulConfig parameter is -//! the result of a logical OR operation between the \b COMP_TRIG_xxx, +//! This function configures a comparator. The \e ulConfig parameter is the +//! result of a logical OR operation between the \b COMP_TRIG_xxx, //! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. //! //! The \b COMP_TRIG_xxx term can take on the following values: @@ -117,8 +117,8 @@ ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, //! \param ulBase is the base address of the comparator module. //! \param ulRef is the desired reference voltage. //! -//! This function will set the internal reference voltage value. The voltage -//! is specified as one of the following values: +//! This function sets the internal reference voltage value. The voltage is +//! specified as one of the following values: //! //! - \b COMP_REF_OFF to turn off the reference voltage //! - \b COMP_REF_0V to set the reference voltage to 0 V @@ -212,9 +212,9 @@ ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) //! \param pfnHandler is a pointer to the function to be called when the //! comparator interrupt occurs. //! -//! This sets the handler to be called when the comparator interrupt occurs. -//! This will enable the interrupt in the interrupt controller; it is the -//! interrupt-handler's responsibility to clear the interrupt source via +//! This function sets the handler to be called when the comparator interrupt occurs +//! and enables the interrupt in the interrupt controller. It is the interrupt +//! handler's responsibility to clear the interrupt source via //! ComparatorIntClear(). //! //! \sa IntRegister() for important information about registering interrupt @@ -256,9 +256,9 @@ ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, //! \param ulBase is the base address of the comparator module. //! \param ulComp is the index of the comparator. //! -//! This function will clear the handler to be called when a comparator -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. +//! This function clears the handler to be called when a comparator interrupt +//! occurs. This function also masks off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -299,7 +299,7 @@ ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) //! \param ulComp is the index of the comparator. //! //! This function enables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected +//! comparator. Only enabled comparator interrupts can be reflected //! to the processor. //! //! \return None. @@ -328,7 +328,7 @@ ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) //! \param ulComp is the index of the comparator. //! //! This function disables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected +//! comparator. Only enabled comparator interrupts can be reflected //! to the processor. //! //! \return None. @@ -358,7 +358,7 @@ ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) //! \param bMasked is \b false if the raw interrupt status is required and //! \b true if the masked interrupt status is required. //! -//! This returns the interrupt status for the comparator. Either the raw or +//! This function returns the interrupt status for the comparator. Either the raw or //! the masked interrupt status can be returned. //! //! \return \b true if the interrupt is asserted and \b false if it is not @@ -397,18 +397,18 @@ ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, //! \param ulComp is the index of the comparator. //! //! The comparator interrupt is cleared, so that it no longer asserts. This -//! must be done in the interrupt handler to keep it from being called again -//! immediately upon exit. Note that for a level triggered interrupt, the -//! interrupt cannot be cleared until it stops asserting. +//! fucntion must be called in the interrupt handler to keep the handler from +//! being called again immediately upon exit. Note that for a level-triggered +//! interrupt, the interrupt cannot be cleared until it stops asserting. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // diff --git a/bsp/lm3s8962/Libraries/driverlib/comp.h b/bsp/lm3s8962/Libraries/driverlib/comp.h index 728f458881..894295687a 100644 --- a/bsp/lm3s8962/Libraries/driverlib/comp.h +++ b/bsp/lm3s8962/Libraries/driverlib/comp.h @@ -2,7 +2,7 @@ // // comp.h - Prototypes for the analog comparator driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/cpu.c b/bsp/lm3s8962/Libraries/driverlib/cpu.c index e78e877020..80b74ab393 100644 --- a/bsp/lm3s8962/Libraries/driverlib/cpu.c +++ b/bsp/lm3s8962/Libraries/driverlib/cpu.c @@ -3,7 +3,7 @@ // cpu.c - Instruction wrappers for special CPU instructions needed by the // drivers. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -360,8 +360,7 @@ CPUbasepriSet(unsigned long ulNewBasepri) // // Set the BASEPRI register // - __asm(" msr BASEPRI, r0\n" - " bx lr\n"); + __asm(" msr BASEPRI, r0\n"); } #endif diff --git a/bsp/lm3s8962/Libraries/driverlib/cpu.h b/bsp/lm3s8962/Libraries/driverlib/cpu.h index 79da0b1e71..edb76b775b 100644 --- a/bsp/lm3s8962/Libraries/driverlib/cpu.h +++ b/bsp/lm3s8962/Libraries/driverlib/cpu.h @@ -2,7 +2,7 @@ // // cpu.h - Prototypes for the CPU instruction wrapper functions. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/debug.h b/bsp/lm3s8962/Libraries/driverlib/debug.h index 1d98ee0c7d..a0fa0f8100 100644 --- a/bsp/lm3s8962/Libraries/driverlib/debug.h +++ b/bsp/lm3s8962/Libraries/driverlib/debug.h @@ -2,7 +2,7 @@ // // debug.h - Macros for assisting debug of the driver library. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/eeprom.c b/bsp/lm3s8962/Libraries/driverlib/eeprom.c new file mode 100644 index 0000000000..8096899155 --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/eeprom.c @@ -0,0 +1,1110 @@ +//***************************************************************************** +// +// eeprom.c - Driver for programming the on-chip EEPROM. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "inc/hw_eeprom.h" +#include "inc/hw_flash.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "driverlib/eeprom.h" + +//***************************************************************************** +// +//! \addtogroup eeprom_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Useful macros to extract the number of EEPROM blocks available on the target +// device and the total EEPROM storage in bytes from the EESIZE register. +// +//***************************************************************************** +#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >> \ + EEPROM_EESIZE_BLKCNT_S) +#define SIZE_FROM_EESIZE(x) ((((x) & EEPROM_EESIZE_WORDCNT_M) >> \ + EEPROM_EESIZE_WORDCNT_S) * 4) + +//***************************************************************************** +// +// Useful macro to extract the offset from a linear address. +// +//***************************************************************************** +#define OFFSET_FROM_ADDR(x) (((x) >> 2) & 0x0F) + +//***************************************************************************** +// +// The key value required to initiate a mass erase. +// +//***************************************************************************** +#define EEPROM_MASS_ERASE_KEY ((unsigned long)0xE37B << EEPROM_EEDBGME_KEY_S) + +//***************************************************************************** +// +// This function implements a workaround for a bug in Blizzard rev A silicon. +// It ensures that only the 1KB flash sector containing a given EEPROM address +// is erased if an erase/copy operation is required as a result of a following +// EEPROM write. +// +//***************************************************************************** +static void +EEPROMSetSectorMask(unsigned long ulAddress) +{ + unsigned long ulMask; + + // + // Determine which page contains the passed EEPROM address. The 2KB EEPROM + // is implemented in 16KB of flash with each 1KB sector of flash holding + // values for 32 consecutive EEPROM words (or 128 bytes). + // + ulMask = ~(1 << (ulAddress >> 7)); + + SysCtlDelay(10); + HWREG(0x400FD0FC) = 3; + SysCtlDelay(10); + HWREG(0x400AE2C0) = ulMask; + SysCtlDelay(10); + HWREG(0x400FD0FC) = 0; + SysCtlDelay(10); +} + +//***************************************************************************** +// +// Clear the FSM sector erase mask to ensure that any following main array flash +// erase operations operate as expected. +// +//***************************************************************************** +static void +EEPROMClearSectorMask(void) +{ + SysCtlDelay(10); + HWREG(0x400FD0FC) = 3; + SysCtlDelay(10); + HWREG(0x400AE2C0) = 0; + SysCtlDelay(10); + HWREG(0x400FD0FC) = 0; + SysCtlDelay(10); +} + +//***************************************************************************** +// +// Block until the EEPROM peripheral is not busy. +// +//***************************************************************************** +static void +EEPROMWaitForDone(void) +{ + // + // Is the EEPROM still busy? + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Spin while EEPROM is busy. + // + } +} + +//***************************************************************************** +// +//! Performs any necessary recovery in case of power failures during write. +//! +//! This function must be called after SysCtlPeripheralEnable() and before +//! the EEPROM is accessed to check for errors resulting from power failure +//! during a previous write operation. The function detects these errors +//! and performs as much recovery as possible before returning information to +//! the caller on whether or not a previous data write was lost and must +//! be retried. +//! +//! In cases where \b EEPROM_INIT_RETRY is returned, the application is +//! responsible for determining which data write may have been lost and +//! rewriting this data. If \b EEPROM_INIT_ERROR is returned, the EEPROM was +//! unable to recover its state. This condition may or may not be resolved on +//! future resets depending upon the cause of the fault. For example, if the +//! supply voltage is unstable, retrying the operation once the voltage is +//! stabilized may clear the error. +//! +//! Failure to call this function after a reset may lead to permanent data loss +//! if the EEPROM is later written! +//! +//! \return Returns \b EEPROM_INIT_OK if no errors were detected, +//! \b EEPROM_INIT_RETRY if a previous write operation may have been +//! interrupted by a power or reset event or \b EEPROM_INIT_ERROR if the EEPROM +//! peripheral cannot currently recover from an interrupted write or erase +//! operation. +// +//***************************************************************************** +unsigned long +EEPROMInit(void) +{ + unsigned long ulStatus; + + // + // Insert a small delay (6 cycles + call overhead) to guard against the + // possibility that this function is called immediately after the EEPROM + // peripheral is enabled. Without this delay, there is a slight chance + // that the first EEPROM register read will fault if you are using a + // compiler with a ridiculously good optimizer! + // + SysCtlDelay(2); + + // + // Make sure the EEPROM has finished its reset processing. + // + EEPROMWaitForDone(); + + // + // Read the EESUPP register to see if any errors have been reported. + // + ulStatus = HWREG(EEPROM_EESUPP); + + // + // Did an error of some sort occur during a previous attempt to write to + // the EEPROM? + // + if(ulStatus & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) + { + // + // Perform a second reset to allow the EEPROM a chance to correct + // the errors. + // + SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); + + // + // Wait for the EEPROM to complete it's reset processing once again. + // + SysCtlDelay(2); + EEPROMWaitForDone(); + + // + // Read EESUPP once again to determine if the error conditions are + // cleared. + // + ulStatus = HWREG(EEPROM_EESUPP); + if(ulStatus & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) + { + return(EEPROM_INIT_ERROR); + } + else + { + return(EEPROM_INIT_RETRY); + } + } + + // + // The EEPROM does not indicate that any error occurred. + // + return(EEPROM_INIT_OK); +} + +//***************************************************************************** +// +//! Determines the size of the EEPROM. +//! +//! This function returns the size of the EEPROM in bytes. +//! +//! \return Returns the total number of bytes in the EEPROM. +// +//***************************************************************************** +unsigned long +EEPROMSizeGet(void) +{ + // + // Return the size of the EEPROM in bytes. + // + return(SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); +} + +//***************************************************************************** +// +//! Determines the number of blocks in the EEPROM. +//! +//! This function may be called to determine the number of blocks in the +//! EEPROM. Each block is the same size and the number of bytes of storage +//! contained in a block may be determined by dividing the size of the device, +//! obtained via a call to the EEPROMSizeGet() function, by the number of +//! blocks returned by this function. +//! +//! \return Returns the total number of bytes in the device EEPROM. +// +//***************************************************************************** +unsigned long +EEPROMBlockCountGet(void) +{ + // + // Extract the number of blocks and return it to the caller. + // + return(BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); +} + +//***************************************************************************** +// +//! Reads data from the EEPROM. +//! +//! \param pulData is a pointer to storage for the data read from the EEPROM. +//! This pointer must point to at least \e ulCount bytes of available memory. +//! \param ulAddress is the byte address within the EEPROM from which data is +//! to be read. This value must be a multiple of 4. +//! \param ulCount is the number of bytes of data to read from the EEPROM. +//! This value must be a multiple of 4. +//! +//! This function may be called to read a number of words of data from a +//! word-aligned address within the EEPROM. Data read is copied into the +//! buffer pointed to by the \e pulData parameter. +//! +//! \return None. +// +//***************************************************************************** +void +EEPROMRead(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check parameters in a debug build. + // + ASSERT(pulData); + ASSERT(ulAddress < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress + ulCount) <= SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress & 3) == 0); + ASSERT((ulCount & 3) == 0); + + // + // Set the block and offset appropriately to read the first word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ulAddress); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ulAddress); + + // + // Convert the byte count to a word count. + // + ulCount /= 4; + + // + // Read each word in turn. + // + while(ulCount) + { + // + // Read the next word through the autoincrementing register. + // + *pulData = HWREG(EEPROM_EERDWRINC); + + // + // Move on to the next word. + // + pulData++; + ulCount--; + + // + // Do we need to move to the next block? This is the case if the + // offset register has just wrapped back to 0. + // + if(HWREG(EEPROM_EEOFFSET) == 0) + { + HWREG(EEPROM_EEBLOCK) += 1; + } + } +} + +//***************************************************************************** +// +//! Writes data to the EEPROM. +//! +//! \param pulData points to the first word of data to write to the EEPROM. +//! \param ulAddress defines the byte address within the EEPROM that the data +//! is to be written to. This value must be a multiple of 4. +//! \param ulCount defines the number of bytes of data that is to be written. +//! This value must be a multiple of 4. +//! +//! This function may be called to write data into the EEPROM at a given +//! word-aligned address. The call is synchronous and returns only after +//! all data has been written or an error occurs. +//! +//! \return Returns 0 on success or non-zero values on failure. Failure codes +//! are logical OR combinations of \b EEPROM_RC_INVPL, \b EEPROM_RC_WRBUSY, +//! \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and +//! \b EEPROM_RC_WORKING. +// +//***************************************************************************** +unsigned long +EEPROMProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + unsigned long ulStatus; + + // + // Check parameters in a debug build. + // + ASSERT(pulData); + ASSERT(ulAddress < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress + ulCount) <= SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress & 3) == 0); + ASSERT((ulCount & 3) == 0); + + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMSetSectorMask(ulAddress); + } + + // + // Set the block and offset appropriately to program the first word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ulAddress); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ulAddress); + + // + // Convert the byte count to a word count. + // + ulCount /= 4; + + // + // Write each word in turn. + // + while(ulCount) + { + // + // Write the next word through the autoincrementing register. + // + HWREG(EEPROM_EERDWRINC) = *pulData; + + // + // Wait for the write to complete. + // + do + { + // + // Read the status. + // + ulStatus = HWREG(EEPROM_EEDONE); + } + while(ulStatus & EEPROM_EEDONE_WORKING); + + // + // Make sure we completed the write without errors. Note that we + // must check this per-word because write permission can be set per + // block resulting in only a section of the write not being performed. + // + if(ulStatus & (EEPROM_EEDONE_NOPERM | EEPROM_EEDONE_INVPL)) + { + // + // An error was reported that would prevent the values from + // being written correctly. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + return(ulStatus); + } + + // + // Move on to the next word. + // + pulData++; + ulCount--; + + // + // Do we need to move to the next block? This is the case if the + // offset register has just wrapped back to 0. + // + if(HWREG(EEPROM_EEOFFSET) == 0) + { + HWREG(EEPROM_EEBLOCK) += 1; + } + } + + // + // Clear the sector protection bits to prevent possible problems when + // programming the main flash array later. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + + // + // Return the current status to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Writes a word to the EEPROM. +//! +//! \param ulData is the word to write to the EEPROM. +//! \param ulAddress defines the byte address within the EEPROM to which the +//! data is to be written. This value must be a multiple of 4. +//! +//! This function is intended to allow EEPROM programming under interrupt +//! control. It may be called to start the process of writing a single word of +//! data into the EEPROM at a given word-aligned address. The call is +//! asynchronous and returna immediately without waiting for the write to +//! complete. Completion of the operation is signaled by means of an +//! interrupt from the EEPROM module. The EEPROM peripheral shares a single +//! interrupt vector with the flash memory subsystem, \e INT_FLASH. +//! +//! \return Returns status and error information in the form of a logical OR +//! combinations of \b EEPROM_RC_INVPL, \b EEPROM_RC_WRBUSY, +//! \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE and +//! \b EEPROM_RC_WORKING. Flags \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and +//! \b EEPROM_RC_WORKING are expected in normal operation and do not indicate +//! an error. +// +//***************************************************************************** +unsigned long +EEPROMProgramNonBlocking(unsigned long ulData, unsigned long ulAddress) +{ + // + // Check parameters in a debug build. + // + ASSERT(ulAddress < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT((ulAddress & 3) == 0); + + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMSetSectorMask(ulAddress); + } + + // + // Set the block and offset appropriately to program the desired word. + // + HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ulAddress); + HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ulAddress); + + // + // Write the new word using the auto-incrementing register just in case + // the caller wants to write follow-on words using direct register access + // + HWREG(EEPROM_EERDWRINC) = ulData; + + // + // Return the current status to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Erases the EEPROM and returns it to the factory default condition. +//! +//! This function completely erases the EEPROM and removes any and +//! all access protection on its blocks, leaving the device in the factory +//! default condition. After this operation, all EEPROM words contain the +//! value 0xFFFFFFFF and all blocks are accessible for both read and write +//! operations in all CPU modes. No passwords are active. +//! +//! The function is synchronous and does not return until the erase operation +//! has completed. +//! +//! \return Returns 0 on success or non-zero values on failure. Failure codes +//! are logical OR combinations of \b EEPROM_RC_INVPL, \b EEPROM_RC_WRBUSY, +//! \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and +//! \b EEPROM_RC_WORKING. +// +//***************************************************************************** +unsigned long +EEPROMMassErase(void) +{ + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + + // + // Start the mass erase processing + // + HWREG(EEPROM_EEDBGME) = EEPROM_MASS_ERASE_KEY | EEPROM_EEDBGME_ME; + + // + // Wait for completion. + // + EEPROMWaitForDone(); + + // + // Reset the peripheral. This is required so that all protection + // mechanisms and passwords are reset now that the EEPROM data has been + // scrubbed. + // + SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); + + // + // Wait for completion again. + // + SysCtlDelay(2); + EEPROMWaitForDone(); + + // + // Pass any error codes back to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Returns the current protection level for an EEPROM block. +//! +//! \param ulBlock is the block number for which the protection level is to be +//! queried. +//! +//! This function returns the current protection settings for a given +//! EEPROM block. If block 0 is currently locked, it must be unlocked prior +//! to calling this function to query the protection setting for other blocks. +//! +//! \return Returns one of \b EEPROM_PROT_RW_LRO_URW, \b EEPROM_PROT_NA_LNA_URW +//! or \b EEPROM_PROT_RO_LNA_URO optionally OR-ed with +//! \b EEPROM_PROT_SUPERVISOR_ONLY. +// +//***************************************************************************** +unsigned long +EEPROMBlockProtectGet(unsigned long ulBlock) +{ + // + // Parameter validity check. + // + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Set the current block. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Return the protection flags for this block. + // + return(HWREG(EEPROM_EEPROT)); +} + +//***************************************************************************** +// +//! Set the current protection options for an EEPROM block. +//! +//! \param ulBlock is the block number for which the protection options are to +//! be set. +//! \param ulProtect consists of one of the values \b EEPROM_PROT_RW_LRO_URW, +//! \b EEPROM_PROT_NA_LNA_URW or \b EEPROM_PROT_RO_LNA_URO optionally ORed with +//! \b EEPROM_PROT_SUPERVISOR_ONLY. +//! +//! This function sets the protection settings for a given EEPROM block +//! assuming no protection settings have previously been written. Note that +//! protection settings applied to block 0 have special meaning and control +//! access to the EEPROM peripheral as a whole. Protection settings applied to +//! blocks numbered 1 and above are layered above any protection set on block 0 +//! such that the effective protection on each block is the logical OR of the +//! protection flags set for block 0 and for the target block. This protocol +//! allows global protection options to be set for the whole device via block +//! 0 and more restrictive protection settings to be set on a block-by-block +//! basis. +//! +//! The protection flags indicate access permissions as follow: +//! +//! \b EEPROM_PROT_SUPERVISOR_ONLY restricts access to the block to threads +//! running in supervisor mode. If clear, both user and supervisor threads +//! can access the block. +//! +//! \b EEPROM_PROT_RW_LRO_URW provides read/write access to the block if no +//! password is set or if a password is set and the block is unlocked. If the +//! block is locked, only read access is permitted. +//! +//! \b EEPROM_PROT_NA_LNA_URW provides neither read nor write access unless +//! a password is set and the block is unlocked. If the block is unlocked, +//! both read and write access are permitted. +//! +//! \b EEPROM_PROT_RO_LNA_URO provides read access to the block if no password +//! is set or if a password is set and the block is unlocked. If the block is +//! password protected and locked, neither read nor write access is permitted. +//! +//! \return Returns a logical OR combination of \b EEPROM_RC_INVPL, +//! \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, +//! \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING to indicate status and error +//! conditions. +// +//***************************************************************************** +unsigned long +EEPROMBlockProtectSet(unsigned long ulBlock, unsigned long ulProtect) +{ + // + // Parameter validity check. + // + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Set the current block. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Set the protection options for this block. + // + HWREG(EEPROM_EEPROT) = ulProtect; + + // + // Wait for the write to complete. + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Still working. + // + } + + // + // Pass any error codes back to the caller. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Sets the password used to protect an EEPROM block. +//! +//! \param ulBlock is the EEPROM block number for which the password is to be +//! set. +//! \param pulPassword points to an array of unsigned long values comprising +//! the password to set. Each element may be any 32-bit value other than +//! 0xFFFFFFFF. This array must contain the number of elements given by the +//! \b ulCount parameter. +//! \param ulCount provides the number of unsigned longs in the \b ulPassword. +//! Valid values are 1, 2 and 3. +//! +//! This function allows the password used to unlock an EEPROM block to be +//! set. Valid passwords may be either 32, 64 or 96 bits comprising words +//! with any value other than 0xFFFFFFFF. The password may only be set once. +//! Any further attempts to set the password result in an error. Once the +//! password is set, the block remains unlocked until EEPROMBlockLock() is +//! called for that block or block 0, or a reset occurs. +//! +//! If a password is set on block 0, this affects locking of the peripheral as +//! a whole. When block 0 is locked, all other EEPROM blocks are inaccessible +//! until block 0 is unlocked. Once block 0 is unlocked, other blocks +//! become accessible according to any passwords set on those blocks and the +//! protection set for that block via a call to EEPROMBlockProtectSet(). +//! +//! \return Returns a logical OR combination of \b EEPROM_RC_INVPL, +//! \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, +//! \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING to indicate status and error +//! conditions. +// +//***************************************************************************** +unsigned long +EEPROMBlockPasswordSet(unsigned long ulBlock, unsigned long *pulPassword, + unsigned long ulCount) +{ + unsigned long ulReg; + + // + // Check parameters in a debug build. + // + ASSERT(pulPassword); + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT(ulCount <= 3); + + // + // Set the block number whose password we are about to write. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Start with the first password word. + // + ulReg = EEPROM_EEPASS0; + + // + // Write the password. + // + while(ulCount) + { + // + // Start the process of writing the password. + // + HWREG(ulReg) = *pulPassword; + + // + // Update values in preparation for writing the next word. + // + pulPassword++; + ulReg += 4; + ulCount--; + + // + // Wait for the last word write to complete or an error to be reported. + // + while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) + { + // + // Still working. + // + } + } + + // + // Return the final write status. + // + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +//! Locks a password-protected EEPROM block. +//! +//! \param ulBlock is the EEPROM block number which is to be locked. +//! +//! This function locks an EEPROM block that has previously been protected by +//! writing a password. Access to the block once it is locked is determined +//! by the protection settings applied via a previous call to the +//! EEPROMBlockProtectSet() function. If no password has previously been set +//! for the block, this function has no effect. +//! +//! Locking block 0 has the effect of making all other blocks in the EEPROM +//! inaccessible. +//! +//! \return Returns the lock state for the block on exit, 1 if unlocked (as +//! would be the case if no password was set) or 0 if locked. +//! +//***************************************************************************** +unsigned long +EEPROMBlockLock(unsigned long ulBlock) +{ + // + // Check parameters in a debug build. + // + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Select the block we are going to lock. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Lock the block. + // + HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; + + // + // Return the current lock state. + // + return(HWREG(EEPROM_EEUNLOCK)); +} + +//***************************************************************************** +// +//! Unlocks a password-protected EEPROM block. +//! +//! \param ulBlock is the EEPROM block number which is to be unlocked. +//! \param pulPassword points to an array of unsigned long values containing +//! the password for the blockt. Each element must match the password +//! originally set via a call to EEPROMBlockPasswordSet(). +//! \param ulCount provides the number of unsigned longs in the \b pulPassword +//! array and must match the value originally passed to +//! EEPROMBlockPasswordSet(). Valid values are 1, 2 and 3. +//! +//! This function unlocks an EEPROM block that has previously been protected by +//! writing a password. Access to the block once it is unlocked is determined +//! by the protection settings applied via a previous call to the +//! EEPROMBlockProtectSet() function. +//! +//! To successfully unlock an EEPROM block, the password provided must match +//! the password provided on the original call to EEPROMBlockPasswordSet(). If +//! an incorrect password is provided, the block remains locked. +//! +//! Unlocking block 0 has the effect of making all other blocks in the device +//! accessible according to their own access protection settings. When block +//! 0 is locked, all other EEPROM blocks are inaccessible. +//! +//! \return Returns the lock state for the block on exit, 1 if unlocked or 0 if +//! locked. +//! +//***************************************************************************** +unsigned long +EEPROMBlockUnlock(unsigned long ulBlock, unsigned long *pulPassword, + unsigned long ulCount) +{ + // + // Check parameters in a debug build. + // + ASSERT(pulPassword); + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + ASSERT(ulCount <= 3); + + // + // Set the block that we are trying to unlock. + // + HWREG(EEPROM_EEBLOCK) = ulBlock; + + // + // Write the unlock register with 0xFFFFFFFF to reset the unlock + // sequence just in case a short password was previously used to try to + // unlock the block. + // + HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; + + // + // We need to write the password words in the opposite order when unlocking + // compared to locking so start at the end of the array. + // + pulPassword += (ulCount - 1); + + // + // Write the supplied password to unlock the block. + // + while(ulCount) + { + HWREG(EEPROM_EEUNLOCK) = *pulPassword--; + ulCount--; + } + + // + // Let the caller know if their password worked. + // + return(HWREG(EEPROM_EEUNLOCK)); +} + +//***************************************************************************** +// +//! Hides an EEPROM block until the next reset. +//! +//! \param ulBlock is the EEPROM block number which is to be hidden. +//! +//! This function hides an EEPROM block other than block 0. Once hidden, a +//! block is completely inaccessible until the next reset. This mechanism +//! allows initialization code to have access to data which is to be hidden +//! from the rest of the application. Unlike applications using passwords, an +//! application making using of block hiding need not contain any embedded +//! passwords which could be found through disassembly. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMBlockHide(unsigned long ulBlock) +{ + // + // Check parameters in a debug build. + // + ASSERT(!ulBlock); + ASSERT(ulBlock < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); + + // + // Hide the requested block. + // + HWREG(EEPROM_EEHIDE) = (1 << ulBlock); +} + +//***************************************************************************** +// +//! Enables the EEPROM interrupt. +//! +//! \param ulIntFlags indicates which EEPROM interrupt source to enable. This +//! must be \b EEPROM_INT_PROGRAM currently. +//! +//! This function enables the EEPROM interrupt. When enabled, an interrupt +//! is generated when any EEPROM write or erase operation completes. The +//! EEPROM peripheral shares a single interrupt vector with the flash memory +//! subsystem, \b INT_FLASH. This function is provided as a convenience but +//! the EEPROM interrupt can also be enabled using a call to FlashIntEnable() +//! passing FLASH_INT_EEPROM in the \b ulIntFlags parameter. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntEnable(unsigned long ulIntFlags) +{ + // + // Look for valid interrupt sources. + // + ASSERT(ulIntFlags == EEPROM_INT_PROGRAM); + + // + // Enable interrupts from the EEPROM module. + // + HWREG(EEPROM_EEINT) |= EEPROM_EEINT_INT; + + // + // Enable the EEPROM interrupt in the flash controller module. + // + HWREG(FLASH_FCIM) |= FLASH_FCRIS_ERIS; +} + +//***************************************************************************** +// +//! Disables the EEPROM interrupt. +//! +//! \param ulIntFlags indicates which EEPROM interrupt source to disable. This +//! must be \b EEPROM_INT_PROGRAM currently. +//! +//! This function disables the EEPROM interrupt and prevents calls to the +//! interrupt vector when any EEPROM write or erase operation completes. The +//! EEPROM peripheral shares a single interrupt vector with the flash memory +//! subsystem, \e INT_FLASH. This function is provided as a convenience but +//! the EEPROM interrupt can also be disabled using a call to FlashIntDisable() +//! passing FLASH_INT_EEPROM in the \b ulIntFlags parameter. +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntDisable(unsigned long ulIntFlags) +{ + // + // Look for valid interrupt sources. + // + ASSERT(ulIntFlags == EEPROM_INT_PROGRAM); + + // + // Disable the EEPROM interrupt in the flash controller module. + // + HWREG(FLASH_FCIM) &= ~FLASH_FCIM_EMASK; + + // + // Disable interrupts from the EEPROM module. + // + HWREG(EEPROM_EEINT) &= ~EEPROM_EEINT_INT; +} + +//***************************************************************************** +// +//! Reports the state of the EEPROM interrupt. +//! +//! \param bMasked determines whether the masked or unmasked state of the +//! interrupt is to be returned. If bMasked is \e true, the masked state is +//! returned, otherwise the unmasked state is returned. +//! +//! This function allows an application to query the state of the EEPROM +//! interrupt. If active, the interrupt may be cleared by calling +//! EEPROMIntClear(). +//! +//! \return Returns \b EEPROM_INT_PROGRAM if an interrupt is being signaled or +//! 0 otherwise. +// +//***************************************************************************** +unsigned long +EEPROMIntStatus(tBoolean bMasked) +{ + if(bMasked) + { + // + // If asked for the masked interrupt status, we check to see if the + // relevant interrupt is pending in the flash controller then return + // the appropriate EEPROM flag if it is. + // + return((HWREG(FLASH_FCMISC) & FLASH_FCMISC_EMISC) ? + EEPROM_INT_PROGRAM : 0); + } + else + { + // + // If asked for the unmasked interrupt status, infer that an interrupt + // is pending if the WORKING bit of the EEDONE register is clear. The + // actual interrupt fires on the high to low transition of this bit + // but we don't have access to an unmasked interrupt status for the + // EEPROM because it's handled via the flash controller so we have to + // make do with this instead. + // + return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ? + 0 : EEPROM_INT_PROGRAM); + } +} + +//***************************************************************************** +// +//! Clears the EEPROM interrupt. +//! +//! \param ulIntFlags indicates which interrupt sources to clear. Currently, +//! the only valid value is \b EEPROM_INT_PROGRAM. +//! +//! This function allows an application to clear the EEPROM interrupt. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +//! +//***************************************************************************** +void +EEPROMIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_EMISC; + + // + // Clear the sector protection bits to prevent possible problems when + // programming the main flash array later. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } +} + +//***************************************************************************** +// +//! Returns status on the last EEPROM program or erase operation. +//! +//! This function returns the current status of the last program or erase +//! operation performed by the EEPROM. It is intended to provide error +//! information to applications programming or setting EEPROM protection +//! options under interrupt control. +//! +//! \return Returns 0 if the last program or erase operation completed without +//! any errors. If an operation is ongoing or an error occurred, the return +//! value is a logical OR combination of \b EEPROM_RC_INVPL, +//! \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, +//! \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. +//! +//***************************************************************************** +unsigned long +EEPROMStatusGet(void) +{ + return(HWREG(EEPROM_EEDONE)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/eeprom.h b/bsp/lm3s8962/Libraries/driverlib/eeprom.h new file mode 100644 index 0000000000..00ac97e883 --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/eeprom.h @@ -0,0 +1,264 @@ +//***************************************************************************** +// +// eeprom.h - Prototypes for the EEPROM driver. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __EEPROM_H__ +#define __EEPROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eeprom_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Values returned by EEPROMInit. +// +//***************************************************************************** + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that +//! no previous write operations were interrupted by a reset event and that the +//! EEPROM peripheral is ready for use. +// +#define EEPROM_INIT_OK 0 + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that +//! a previous data or protection write operation was interrupted by a reset +//! event. The EEPROM peripheral has recovered its state but the last write +//! operation may have been lost. The application must check the validity of +//! data it has written and retry any writes as required. +// +#define EEPROM_INIT_RETRY 1 + +// +//! This value may be returned from a call to EEPROMInit(). It indicates that a +//! previous data or protection write operation was interrupted by a reset +//! event and that the EEPROM peripheral was unable to clean up after the +//! problem. This situation may be resolved with another reset or may be fatal +//! depending upon the cause of the problem. For example, if the voltage to +//! the part is unstable, retrying once the voltage has stabilized may clear +//! the error. +// +#define EEPROM_INIT_ERROR 2 + +//***************************************************************************** +// +// Error indicators returned by various EEPROM API calls. These will be ORed +// together into the final return code. +// +//***************************************************************************** + +// +//! This return code bit indicates that the EEPROM programming state machine +//! failed to write a value due to the voltage level dropping below that +//! required for EEPROM programming. The operation may be retried once the +//! voltage stabilizes. +// +#define EEPROM_RC_INVPL 0x00000100 + +// +//! This return code bit indicates that an attempt was made to read from +//! the EEPROM while a write operation was in progress. +// +#define EEPROM_RC_WRBUSY 0x00000020 + +// +//! This return code bit indicates that an attempt was made to write a +//! value but the destination permissions disallow write operations. This +//! may be due to the destination block being locked, access protection set +//! to prohibit writes or an attempt to write a password when one is already +//! written. +// +#define EEPROM_RC_NOPERM 0x00000010 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently copying to or from the internal copy buffer to make room for +//! a newly written value. It is provided as a status indicator and does not +//! indicate an error. +// +#define EEPROM_RC_WKCOPY 0x00000008 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently erasing the internal copy buffer. It is provided as a +//! status indicator and does not indicate an error. +// +#define EEPROM_RC_WKERASE 0x00000004 + +// +//! This return code bit indicates that the EEPROM programming state machine +//! is currently working. No new write operations should be attempted until +//! this bit is clear. +// +#define EEPROM_RC_WORKING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EEPROMBlockProtectSet() in the ulProtect +// parameter, and returned by EEPROMBlockProtectGet(). +// +//***************************************************************************** + +// +//! This bit may be ORed with the protection option passed to +//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It +//! restricts EEPROM access to threads running in supervisor mode and prevents +//! access to an EEPROM block when the CPU is in user mode. +// +#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer +//! read/write access when no password is set or when a password is set and +//! the block is unlocked, and read-only access when a password is set but +//! the block is locked. +// +#define EEPROM_PROT_RW_LRO_URW 0x00000000 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer neither +//! read nor write access unless it is protected by a password and unlocked. +// +#define EEPROM_PROT_NA_LNA_URW 0x00000001 + +// +//! This value may be passed to EEPROMBlockProtectSet() or returned from +//! EEPROMBlockProtectGet(). It indicates that the block should offer +//! read-only access when no password is set or when a password is set and the +//! block is unlocked. When a password is set and the block is locked, neither +//! read nor write access is permitted. +// +#define EEPROM_PROT_RO_LNA_URO 0x00000002 + +//***************************************************************************** +// +//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is +//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being +//! signaled. +// +//***************************************************************************** +#define EEPROM_INT_PROGRAM 0x00000004 + +//***************************************************************************** +// +//! Returns the EEPROM block number containing a given offset address. +//! +//! \param ulAddr is the linear, byte address of the EEPROM location whose +//! block number is to be returned. This is a zero-based offset from the start +//! of the EEPROM storage. +//! +//! This macro may be used to translate an EEPROM address offset into a +//! block number suitable for use in any of the driver's block protection +//! functions. The address provided is expressed as a byte offset from the +//! base of the EEPROM. +//! +//! \return Returns the zero-based block number which contains the passed +//! address. +// +//***************************************************************************** +#define EEPROMBlockFromAddr(ulAddr) ((ulAddr) >> 6) + +//***************************************************************************** +// +//! Returns the offset address of the first word in an EEPROM block. +//! +//! \param ulBlock is the index of the EEPROM block whose first word address +//! is to be returned. +//! +//! This macro may be used to determine the address of the first word in a +//! given EEPROM block. The address returned is expressed as a byte offset +//! from the base of EEPROM storage. +//! +//! \return Returns the address of the first word in the given EEPROM block. +// +//***************************************************************************** +#define EEPROMAddrFromBlock(ulBlock) ((ulBlock) << 6) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long EEPROMInit(void); +extern unsigned long EEPROMSizeGet(void); +extern unsigned long EEPROMBlockCountGet(void); +extern void EEPROMRead(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern unsigned long EEPROMProgram(unsigned long *pulData, + unsigned long ulAddress, + unsigned long ulCount); +extern unsigned long EEPROMProgramNonBlocking(unsigned long ulData, + unsigned long ulAddress); +extern unsigned long EEPROMStatusGet(void); +extern unsigned long EEPROMMassErase(void); +extern unsigned long EEPROMBlockProtectGet(unsigned long ulBlock); +extern unsigned long EEPROMBlockProtectSet(unsigned long ulBlock, + unsigned long ulProtect); +extern unsigned long EEPROMBlockPasswordSet(unsigned long ulBlock, + unsigned long *pulPassword, + unsigned long ulCount); +extern unsigned long EEPROMBlockLock(unsigned long ulBlock); +extern unsigned long EEPROMBlockUnlock(unsigned long ulBlock, + unsigned long *pulPassword, + unsigned long ulCount); +extern void EEPROMBlockHide(unsigned long ulBlock); +extern void EEPROMIntEnable(unsigned long ulIntFlags); +extern void EEPROMIntDisable(unsigned long ulIntFlags); +extern unsigned long EEPROMIntStatus(tBoolean bMasked); +extern void EEPROMIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EEPROM_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/epi.c b/bsp/lm3s8962/Libraries/driverlib/epi.c index eef70f3310..9bb281f7b8 100644 --- a/bsp/lm3s8962/Libraries/driverlib/epi.c +++ b/bsp/lm3s8962/Libraries/driverlib/epi.c @@ -2,7 +2,7 @@ // // epi.c - Driver for the EPI module. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -50,9 +50,10 @@ //! - \b EPI_MODE_GENERAL - use for general-purpose mode operation //! - \b EPI_MODE_SDRAM - use with SDRAM device //! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface +//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface //! - \b EPI_MODE_DISABLE - disable the EPI module //! -//! Selection of any of the above modes will enable the EPI module, except +//! Selection of any of the above modes enables the EPI module, except //! for \b EPI_MODE_DISABLE which should be used to disable the module. //! //! \return None. @@ -68,6 +69,7 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode) ASSERT((ulMode == EPI_MODE_GENERAL) || (ulMode == EPI_MODE_SDRAM) || (ulMode == EPI_MODE_HB8) || + (ulMode == EPI_MODE_HB16) || (ulMode == EPI_MODE_DISABLE)); // @@ -84,15 +86,15 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode) //! \param ulDivider is the value of the clock divider to be applied to //! the external interface (0-65535). //! -//! This functions sets the clock divider(s) that will be used to determine the +//! This function sets the clock divider(s) that is used to determine the //! clock rate of the external interface. The \e ulDivider value is used to -//! derive the EPI clock rate from the system clock based upon the following +//! derive the EPI clock rate from the system clock based on the following //! formula. //! //! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) //! //! For example, a divider value of 1 results in an EPI clock rate of half -//! the system clock, value of 2 or 3 yield one quarter of the system clock and +//! the system clock, value of 2 or 3 yields one quarter of the system clock and //! a value of 4 results in one sixth of the system clock rate. //! //! In cases where a dual chip select mode is in use and different clock rates @@ -213,16 +215,15 @@ EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig, //! rate resulting from the divider in the lower 16 bits of the parameter passed //! to EPIDividerSet(). //! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE, -//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL. \b EPI_HB8_CSCFG_CS -//! sets EPI30 to operate as a Chip Select (CSn) signal. When using this mode, -//! \b EPI_HB8_MODE_ADMUX must not be specified. \b EPI_HB8_CSCFG_ALE sets -//! EPI30 to operate as an address latch (ALE). \b EPI_HB8_CSCFG_DUAL_CS sets -//! EPI30 to operate as CS0n and EPI27 as CS1n with the asserted chip select -//! determined from the most significant address bit for the respective external -//! address map. \b EPI_HB8_CSCFG_DUAL_ALE sets EPI30 as an address latch (ALE), -//! EPI27 as CS0n and EPI26 as CS1n with the asserted chip select determined -//! from the most significant address bit for the respective external address -//! map. +//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL_CS. +//! \b EPI_HB8_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal. +//! \b EPI_HB8_CSCFG_ALE sets EPI30 to operate as an address latch (ALE). +//! \b EPI_HB8_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n +//! with the asserted chip select determined from the most significant address +//! bit for the respective external address map. \b EPI_HB8_CSCFG_ALE_DUAL_CS +//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with +//! the asserted chip select determined from the most significant address bit +//! for the respective external address map. //! //! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a //! FIFO is used along with RXFULL or TXEMPTY ready signals, then this @@ -248,7 +249,9 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, // HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ? EPI_HB8CFG2_WORD : 0) | - ((ulConfig & EPI_HB8_CSBAUD_DUAL) ? EPI_HB8CFG2_CSBAUD : 0) | ((ulConfig & EPI_HB8_CSCFG_MASK) << 15)); + ((ulConfig & EPI_HB8_CSBAUD_DUAL) ? + EPI_HB8CFG2_CSBAUD : 0) | + ((ulConfig & EPI_HB8_CSCFG_MASK) << 15)); // // Fill in the max wait field of the configuration word. // @@ -261,6 +264,96 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, HWREG(ulBase + EPI_O_HB8CFG) = ulConfig; } +//***************************************************************************** +// +//! Configures the interface for Host-bus 16 operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the interface configuration. +//! \param ulMaxWait is the maximum number of external clocks to wait +//! if a FIFO ready signal is holding off the transaction. +//! +//! This function is used to configure the interface when used in Host-bus 16 +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ulConfig is the logical OR of any of the following: +//! +//! - one of \b EPI_HB16_MODE_ADMUX, \b EPI_HB16_MODE_ADDEMUX, +//! \b EPI_HB16_MODE_SRAM, or \b EPI_HB16_MODE_FIFO to select the HB16 mode +//! - \b EPI_HB16_USE_TXEMPTY - enable TXEMPTY signal with FIFO +//! - \b EPI_HB16_USE_RXFULL - enable RXFULL signal with FIFO +//! - \b EPI_HB16_WRHIGH - use active high write strobe, otherwise it is +//! active low +//! - \b EPI_HB16_RDHIGH - use active high read strobe, otherwise it is +//! active low +//! - one of \b EPI_HB16_WRWAIT_0, \b EPI_HB16_WRWAIT_1, \b EPI_HB16_WRWAIT_2, +//! or \b EPI_HB16_WRWAIT_3 to select the number of write wait states (default +//! is 0 wait states) +//! - one of \b EPI_HB16_RDWAIT_0, \b EPI_HB16_RDWAIT_1, \b EPI_HB16_RDWAIT_2, +//! or \b EPI_HB16_RDWAIT_3 to select the number of read wait states (default +//! is 0 wait states) +//! - \b EPI_HB16_WORD_ACCESS - use Word Access mode to route bytes to the +//! correct byte lanes allowing data to be stored in bits [31:16]. If absent, +//! all data transfers use bits [15:0]. +//! - \b EPI_HB16_BSEL - enables byte selects. In this mode, two EPI signals +//! operate as byte selects allowing 8-bit transfers. If this flag is not +//! specified, data must be read and written using only 16-bit transfers. +//! - \b EPI_HB16_CSBAUD_DUAL - use different baud rates when accessing devices +//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the +//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the +//! upper 16 bits. If this option is absent, both chip selects use the baud +//! rate resulting from the divider in the lower 16 bits of the parameter passed +//! to EPIDividerSet(). +//! - one of \b EPI_HB16_CSCFG_CS, \b EPI_HB16_CSCFG_ALE, +//! \b EPI_HB16_CSCFG_DUAL_CS or \b EPI_HB16_CSCFG_ALE_DUAL_CS. +//! \b EPI_HB16_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal. +//! \b EPI_HB16_CSCFG_ALE sets EPI30 to operate as an address latch (ALE). +//! \b EPI_HB16_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n +//! with the asserted chip select determined from the most significant address +//! bit for the respective external address map. \b EPI_HB16_CSCFG_ALE_DUAL_CS +//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with +//! the asserted chip select determined from the most significant address bit +//! for the respective external address map. +//! +//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a +//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this +//! parameter determines the maximum number of clocks to wait when the +//! transaction is being held off by by the FIFO using one of these ready +//! signals. A value of 0 means to wait forever. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulMaxWait < 256); + + // + // Determine the CS and word access modes. + // + HWREG(ulBase + EPI_O_HB16CFG2) = (((ulConfig & EPI_HB16_WORD_ACCESS) ? + EPI_HB16CFG2_WORD : 0) | + ((ulConfig & EPI_HB16_CSBAUD_DUAL) ? + EPI_HB16CFG2_CSBAUD : 0) | + ((ulConfig & EPI_HB16_CSCFG_MASK) << 15)); + + // + // Fill in the max wait field of the configuration word. + // + ulConfig &= ~EPI_HB16CFG_MAXWAIT_M; + ulConfig |= ulMaxWait << EPI_HB16CFG_MAXWAIT_S; + + // + // Write the main HostBus16 configuration register. + // + HWREG(ulBase + EPI_O_HB16CFG) = ulConfig; +} + //***************************************************************************** // //! Configures the interface for general-purpose mode operation. @@ -274,9 +367,8 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, //! //! This function is used to configure the interface when used in //! general-purpose operation as chosen with the function EPIModeSet(). The -//! parameter -//! \e ulConfig is the logical OR of any of the following: -//! +//! parameter \e ulConfig is the logical OR of any of the following: +//! //! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin //! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction, //! otherwise it is free-running @@ -288,13 +380,13 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, //! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it //! is a pulse //! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins -//! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a +//! - \b EPI_GPMODE_WRITE2CYCLE - a two-cycle write is used, otherwise a //! single-cycle write is used -//! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a +//! - \b EPI_GPMODE_READ2CYCLE - a two-cycle read is used, otherwise a //! single-cycle read is used //! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4, //! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address -//! bus, or and address bus size of 4, 12, or 20 bits +//! bus or an address bus size of 4, 12, or 20 bits //! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16, //! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus //! size of 8, 16, 24, or 32 bits @@ -313,7 +405,7 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, //! external clock enable is used, this parameter determines the maximum //! number of clocks to wait when the external clock enable signal is holding //! off a transaction. A value of 0 means to wait forever. If a non-zero -//! value is used and exceeded, an interrupt will occur and the transaction +//! value is used and exceeded, an interrupt occurs and the transaction //! aborted. //! //! \return None. @@ -422,7 +514,7 @@ EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap) //! Once configured, the non-blocking read is started by calling //! EPINonBlockingReadStart(). If the addresses to be read from the device //! are in a sequence, it is not necessary to call this function multiple -//! times. Until it is changed, the EPI module will remember the last address +//! times. Until it is changed, the EPI module stores the last address //! that was used for a non-blocking read (per channel). //! //! \return None. @@ -468,9 +560,9 @@ EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel, //! //! This function starts a non-blocking read that was previously configured //! with the function EPINonBlockingReadConfigure(). Once this function is -//! called, the EPI module will begin reading data from the external device -//! into the read FIFO. The EPI will stop reading when the FIFO fills up -//! and resume reading when the application drains the FIFO, until the +//! called, the EPI module begins reading data from the external device +//! into the read FIFO. The EPI stops reading when the FIFO fills up +//! and resumes reading when the application drains the FIFO, until the //! total specified count of data items has been read. //! //! Once a read transaction is completed and the FIFO drained, another @@ -534,7 +626,7 @@ EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel) ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); // - // Write a 0 to the read count register, which will cancel the transaction. + // Write a 0 to the read count register, which cancels the transaction. // HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0; } @@ -612,10 +704,10 @@ EPINonBlockingReadAvail(unsigned long ulBase) //! be stored. //! //! This function reads 32-bit data items from the read FIFO and stores -//! the values in a caller supplied buffer. The function will read and store +//! the values in a caller-supplied buffer. The function reads and stores //! data from the FIFO until there is no more data in the FIFO or the maximum //! count is reached as specified in the parameter \e ulCount. The actual -//! count of items will be returned. +//! count of items is returned. //! //! \return The number of items read from the FIFO. // @@ -634,8 +726,8 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount, ASSERT(pulBuf); // - // Read from the FIFO while there are any items to read, and - // the callers specified count is not exceeded. + // Read from the FIFO while there are any items to read and + // the caller's specified count is not exceeded. // while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) { @@ -663,14 +755,14 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount, //! //! \param ulBase is the EPI module base address. //! \param ulCount is the maximum count of items to read. -//! \param pusBuf is the caller supplied buffer where the read data should +//! \param pusBuf is the caller-supplied buffer where the read data should //! be stored. //! //! This function reads 16-bit data items from the read FIFO and stores -//! the values in a caller supplied buffer. The function will read and store +//! the values in a caller-supplied buffer. The function reads and stores //! data from the FIFO until there is no more data in the FIFO or the maximum //! count is reached as specified in the parameter \e ulCount. The actual -//! count of items will be returned. +//! count of items is returned. //! //! \return The number of items read from the FIFO. // @@ -690,12 +782,12 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount, // // Read from the FIFO while there are any items to read, and - // the callers specified count is not exceeded. + // the caller's specified count is not exceeded. // while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) { // - // Read from the FIFO and store in the caller supplied buffer. + // Read from the FIFO and store in the caller-supplied buffer. // *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO); @@ -718,14 +810,14 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount, //! //! \param ulBase is the EPI module base address. //! \param ulCount is the maximum count of items to read. -//! \param pucBuf is the caller supplied buffer where the read data should +//! \param pucBuf is the caller-supplied buffer where the read data should //! be stored. //! //! This function reads 8-bit data items from the read FIFO and stores -//! the values in a caller supplied buffer. The function will read and store +//! the values in a caller-supplied buffer. The function reads and stores //! data from the FIFO until there is no more data in the FIFO or the maximum //! count is reached as specified in the parameter \e ulCount. The actual -//! count of items will be returned. +//! count of items is returned. //! //! \return The number of items read from the FIFO. // @@ -745,7 +837,7 @@ EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount, // // Read from the FIFO while there are any items to read, and - // the callers specified count is not exceeded. + // the caller's specified count is not exceeded. // while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) { @@ -1047,7 +1139,7 @@ EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the EPI module base address. //! -//! This function will disable and clear the handler to be called when the +//! This function disables and clears the handler to be called when the //! EPI interrupt occurs. //! //! \sa IntRegister() for important information about registering interrupt diff --git a/bsp/lm3s8962/Libraries/driverlib/epi.h b/bsp/lm3s8962/Libraries/driverlib/epi.h index 3aa55e3384..54d8b1511c 100644 --- a/bsp/lm3s8962/Libraries/driverlib/epi.h +++ b/bsp/lm3s8962/Libraries/driverlib/epi.h @@ -2,7 +2,7 @@ // // epi.h - Prototypes and macros for the EPI module. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -44,6 +44,7 @@ extern "C" #define EPI_MODE_GENERAL 0x00000010 #define EPI_MODE_SDRAM 0x00000011 #define EPI_MODE_HB8 0x00000012 +#define EPI_MODE_HB16 0x00000013 #define EPI_MODE_DISABLE 0x00000000 //***************************************************************************** @@ -115,6 +116,37 @@ extern "C" #define EPI_HB8_CSCFG_MASK 0x00000600 +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB16ModeSet() +// +//***************************************************************************** +#define EPI_HB16_USE_TXEMPTY 0x00800000 +#define EPI_HB16_USE_RXFULL 0x00400000 +#define EPI_HB16_WRHIGH 0x00200000 +#define EPI_HB16_RDHIGH 0x00100000 +#define EPI_HB16_WRWAIT_0 0x00000000 +#define EPI_HB16_WRWAIT_1 0x00000040 +#define EPI_HB16_WRWAIT_2 0x00000080 +#define EPI_HB16_WRWAIT_3 0x000000C0 +#define EPI_HB16_RDWAIT_0 0x00000000 +#define EPI_HB16_RDWAIT_1 0x00000010 +#define EPI_HB16_RDWAIT_2 0x00000020 +#define EPI_HB16_RDWAIT_3 0x00000030 +#define EPI_HB16_MODE_ADMUX 0x00000000 +#define EPI_HB16_MODE_ADDEMUX 0x00000001 +#define EPI_HB16_MODE_SRAM 0x00000002 +#define EPI_HB16_MODE_FIFO 0x00000003 +#define EPI_HB16_BSEL 0x00000004 +#define EPI_HB16_WORD_ACCESS 0x00000100 +#define EPI_HB16_CSCFG_ALE 0x00000000 +#define EPI_HB16_CSCFG_CS 0x00000200 +#define EPI_HB16_CSCFG_DUAL_CS 0x00000400 +#define EPI_HB16_CSCFG_ALE_DUAL_CS 0x00000600 +#define EPI_HB16_CSBAUD_DUAL 0x00000800 + +#define EPI_HB16_CSCFG_MASK 0x00000600 + //***************************************************************************** // // Values that can be passed to EPIConfigSDRAMSet() @@ -196,6 +228,8 @@ extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig, unsigned long ulMaxWait); extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, unsigned long ulMaxWait); +extern void EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait); extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap); extern void EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel, diff --git a/bsp/lm3s8962/Libraries/driverlib/ethernet.c b/bsp/lm3s8962/Libraries/driverlib/ethernet.c index c341bbd1cf..9597ec99df 100644 --- a/bsp/lm3s8962/Libraries/driverlib/ethernet.c +++ b/bsp/lm3s8962/Libraries/driverlib/ethernet.c @@ -2,7 +2,7 @@ // // ethernet.c - Driver for the Integrated Ethernet Controller // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -44,14 +44,14 @@ //! \param ulBase is the base address of the controller. //! \param ulEthClk is the rate of the clock supplied to the Ethernet module. //! -//! This function will prepare the Ethernet controller for first time use in +//! This function prepares the Ethernet controller for first-time use in //! a given hardware/software configuration. This function should be called //! before any other Ethernet API functions are called. //! -//! The peripheral clock will be the same as the processor clock. This will be -//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded -//! if it is constant and known (to save the code/execution overhead of a call -//! to SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). //! //! This function replaces the original EthernetInit() API and performs the //! same actions. A macro is provided in ethernet.h to map the @@ -112,14 +112,16 @@ EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk) //! //! The Ethernet controller provides three control registers that are used //! to configure the controller's operation. The transmit control register -//! provides settings to enable full duplex operation, to auto-generate the +//! provides settings to enable full-duplex operation, to auto-generate the //! frame check sequence, and to pad the transmit packets to the minimum //! length as required by the IEEE standard. The receive control register //! provides settings to enable reception of packets with bad frame check //! sequence values and to enable multi-cast or promiscuous modes. The //! timestamp control register provides settings that enable support logic in //! the controller that allow the use of the General Purpose Timer 3 to capture -//! timestamps for the transmitted and received packets. +//! timestamps for the transmitted and received packets. Note that not all +//! devices support this functionality; see the data sheet to determine if +//! this feature is supported. //! //! The \e ulConfig parameter is the logical OR of the following values: //! @@ -183,11 +185,11 @@ EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig) //! //! \param ulBase is the base address of the controller. //! -//! This function will query the control registers of the Ethernet controller -//! and return a bit-mapped configuration value. +//! This function queries the control registers of the Ethernet controller +//! and returns a bit-mapped configuration value. //! //! \sa The description of the EthernetConfigSet() function provides detailed -//! information for the bit-mapped configuration values that will be returned. +//! information for the bit-mapped configuration values that are returned. //! //! \return Returns the bit-mapped Ethernet controller configuration value. // @@ -219,7 +221,7 @@ EthernetConfigGet(unsigned long ulBase) //! \param ulBase is the base address of the controller. //! \param pucMACAddr is the pointer to the array of MAC-48 address octets. //! -//! This function will program the IEEE-defined MAC-48 address specified in +//! This function programs the IEEE-defined MAC-48 address specified in //! \e pucMACAddr into the Ethernet controller. This address is used by the //! Ethernet controller for hardware-level filtering of incoming Ethernet //! packets (when promiscuous mode is not enabled). @@ -282,7 +284,7 @@ EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr) //! \param pucMACAddr is the pointer to the location in which to store the //! array of MAC-48 address octets. //! -//! This function will read the currently programmed MAC address into the +//! This function reads the currently programmed MAC address into the //! \e pucMACAddr buffer. //! //! \sa Refer to EthernetMACAddrSet() API description for more details about @@ -329,8 +331,8 @@ EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr) //! the EthernetMACAddrSet() function, this API function can be called to //! enable the controller for normal operation. //! -//! This function will enable the controller's transmitter and receiver, and -//! will reset the receive FIFO. +//! This function enables the controller's transmitter and receiver, and +//! resets the receive FIFO. //! //! \return None. // @@ -371,8 +373,8 @@ EthernetEnable(unsigned long ulBase) //! \param ulBase is the base address of the controller. //! //! When terminating operations on the Ethernet interface, this function should -//! be called. This function will disable the transmitter and receiver, and -//! will clear out the receive FIFO. +//! be called. This function disables the transmitter and receiver, and +//! clears out the receive FIFO. //! //! \return None. // @@ -416,8 +418,7 @@ EthernetDisable(unsigned long ulBase) //! packets available in the receive FIFO. When the last bytes of a packet are //! successfully received (that is, the frame check sequence bytes), the packet //! count is incremented. Once the packet has been fully read (including the -//! frame check sequence bytes) from the FIFO, the packet count will be -//! decremented. +//! frame check sequence bytes) from the FIFO, the packet count is decremented. //! //! \return Returns \b true if there are one or more packets available in the //! receive FIFO, including the current packet being read, and \b false @@ -448,7 +449,7 @@ EthernetPacketAvail(unsigned long ulBase) //! packet at a time. After the packet has been written into the FIFO, the //! transmit request bit must be set to enable the transmission of the packet. //! Only after the packet has been transmitted can a new packet be written -//! into the FIFO. This function will simply check to see if a packet is +//! into the FIFO. This function simply checks to see if a packet is //! in progress. If so, there is no space available in the transmit FIFO. //! //! \return Returns \b true if a space is available in the transmit FIFO, and @@ -609,20 +610,20 @@ EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf, //! \param lBufLen is the maximum number of bytes to be read into the buffer. //! //! This function reads a packet from the receive FIFO of the controller and -//! places it into \e pucBuf. If no packet is available the function will -//! return immediately. Otherwise, the function will read the entire packet -//! from the receive FIFO. If there are more bytes in the packet than will fit -//! into \e pucBuf (as specified by \e lBufLen), the function will return the -//! negated length of the packet and the buffer will contain \e lBufLen bytes -//! of the packet. Otherwise, the function will return the length of the -//! packet that was read and \e pucBuf will contain the entire packet +//! places it into \e pucBuf. If no packet is available the function +//! returns immediately. Otherwise, the function reads the entire packet +//! from the receive FIFO. If there are more bytes in the packet than can fit +//! into \e pucBuf (as specified by \e lBufLen), the function returns the +//! negated length of the packet and the buffer contains \e lBufLen bytes +//! of the packet. Otherwise, the function returns the length of the +//! packet that was read and \e pucBuf contains the entire packet //! (excluding the frame check sequence bytes). //! //! This function replaces the original EthernetPacketNonBlockingGet() API and //! performs the same actions. A macro is provided in ethernet.h to //! map the original API to this API. //! -//! \note This function will return immediately if no packet is available. +//! \note This function returns immediately if no packet is available. //! //! \return Returns \b 0 if no packet is available, the negated packet length //! \b -n if the packet is too large for \e pucBuf, and the packet length \b n @@ -663,16 +664,16 @@ EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf, //! \param lBufLen is the maximum number of bytes to be read into the buffer. //! //! This function reads a packet from the receive FIFO of the controller and -//! places it into \e pucBuf. The function will wait until a packet is -//! available in the FIFO. Then the function will read the entire packet -//! from the receive FIFO. If there are more bytes in the packet than will -//! fit into \e pucBuf (as specified by \e lBufLen), the function will return -//! the negated length of the packet and the buffer will contain \e lBufLen -//! bytes of the packet. Otherwise, the function will return the length of -//! the packet that was read and \e pucBuf will contain the entire packet +//! places it into \e pucBuf. The function waits until a packet is +//! available in the FIFO. Then the function reads the entire packet +//! from the receive FIFO. If there are more bytes in the packet than can +//! fit into \e pucBuf (as specified by \e lBufLen), the function returns +//! the negated length of the packet and the buffer contains \e lBufLen +//! bytes of the packet. Otherwise, the function returns the length of +//! the packet that was read and \e pucBuf contains the entire packet //! (excluding the frame check sequence bytes). //! -//! \note This function is blocking and will not return until a packet arrives. +//! \note This function is blocking and does not return until a packet arrives. //! //! \return Returns the negated packet length \b -n if the packet is too large //! for \e pucBuf, and returns the packet length \b n otherwise. @@ -832,10 +833,10 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf, //! This function writes \e lBufLen bytes of the packet contained in \e pucBuf //! into the transmit FIFO of the controller and then activates the //! transmitter for this packet. If no space is available in the FIFO, the -//! function will return immediately. If space is available, the -//! function will return once \e lBufLen bytes of the packet have been placed -//! into the FIFO and the transmitter has been started. The function will not -//! wait for the transmission to complete. The function will return the +//! function returns immediately. If space is available, the +//! function returns once \e lBufLen bytes of the packet have been placed +//! into the FIFO and the transmitter has been started. The function does not +//! wait for the transmission to complete. The function returns the //! negated \e lBufLen if the length is larger than the space available in //! the transmit FIFO. //! @@ -843,7 +844,7 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf, //! performs the same actions. A macro is provided in ethernet.h to //! map the original API to this API. //! -//! \note This function does not block and will return immediately if no space +//! \note This function does not block and returns immediately if no space //! is available for the transmit packet. //! //! \return Returns \b 0 if no space is available in the transmit FIFO, the @@ -886,14 +887,14 @@ EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf, //! //! This function writes \e lBufLen bytes of the packet contained in \e pucBuf //! into the transmit FIFO of the controller and then activates the transmitter -//! for this packet. This function will wait until the transmit FIFO is empty. -//! Once space is available, the function will return once \e lBufLen bytes of +//! for this packet. This function waits until the transmit FIFO is empty. +//! Once space is available, the function returns once \e lBufLen bytes of //! the packet have been placed into the FIFO and the transmitter has been -//! started. The function will not wait for the transmission to complete. The -//! function will return the negated \e lBufLen if the length is larger than +//! started. The function does not wait for the transmission to complete. The +//! function returns the negated \e lBufLen if the length is larger than //! the space available in the transmit FIFO. //! -//! \note This function blocks and will wait until space is available for the +//! \note This function blocks and waits until space is available for the //! transmit packet before returning. //! //! \return Returns the negated packet length \b -lBufLen if the packet is too @@ -933,9 +934,10 @@ EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, //! enabled Ethernet interrupts occur. //! //! This function sets the handler to be called when the Ethernet interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It -//! is the interrupt handler's responsibility to clear the interrupt source. +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific Ethernet interrupts must be enabled via +//! EthernetIntEnable(). It is the interrupt handler's responsibility to clear +//! the interrupt source. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -969,9 +971,9 @@ EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the base address of the controller. //! -//! This function unregisters the interrupt handler. This will disable the -//! global interrupt in the interrupt controller so that the interrupt handler -//! no longer is called. +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller so that the interrupt +//! handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1005,16 +1007,17 @@ EthernetIntUnregister(unsigned long ulBase) //! \param ulBase is the base address of the controller. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated Ethernet interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function enables the indicated Ethernet interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! //! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated -//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17, -//! must be read to determine which PHY interrupt has occurred. This register -//! can be read using the EthernetPHYRead() API function. +//! PHY supports a number of interrupt conditions. The appropriate PHY +//! register, PHY_MR17 or PHY_MR29 depending on the device class, must be read +//! to determine which PHY interrupt has occurred. This register can be read +//! using the EthernetPHYRead() API function. //! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the //! management interface has completed successfully. //! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred @@ -1093,9 +1096,9 @@ EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true //! if the masked interrupt status is required. //! -//! This returns the interrupt status for the Ethernet controller. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the Ethernet controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in EthernetIntEnable(). @@ -1138,20 +1141,20 @@ EthernetIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified Ethernet interrupt sources are cleared so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to EthernetIntEnable(). //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1173,6 +1176,42 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags) HWREG(ulBase + MAC_O_IACK) = ulIntFlags; } +//***************************************************************************** +// +//! Sets the PHY address. +//! +//! \param ulBase is the base address of the controller. +//! \param ucAddr is the address of the PHY. +//! +//! This function sets the address of the PHY that is accessed via +//! EthernetPHYRead() and EthernePHYWrite(). This configuration is only needed +//! when connecting to an external PHY via MII, and should not be used on +//! devices that have integrated PHYs. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Wait for any pending transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Set the PHY address. + // + HWREG(ulBase + MAC_O_MADD) = ucAddr; +} + //***************************************************************************** // //! Writes to the PHY register. @@ -1181,7 +1220,7 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags) //! \param ucRegAddr is the address of the PHY register to be accessed. //! \param ulData is the data to be written to the PHY register. //! -//! This function will write the \e ulData to the PHY register specified by +//! This function writes the \e ulData to the PHY register specified by //! \e ucRegAddr. //! //! \return None. @@ -1229,7 +1268,7 @@ EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, //! \param ulBase is the base address of the controller. //! \param ucRegAddr is the address of the PHY register to be accessed. //! -//! This function will return the contents of the PHY register specified by +//! This function returns the contents of the PHY register specified by //! \e ucRegAddr. //! //! \return Returns the 16-bit value read from the PHY. @@ -1269,6 +1308,56 @@ EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr) return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M); } +//***************************************************************************** +// +//! Powers off the Ethernet PHY. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function powers off the Ethernet PHY, reducing the current +//! consumption of the device. While in the powered off state, the Ethernet +//! controller is unable to connect to the Ethernet. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYPowerOff(unsigned long ulBase) +{ + // + // Set the PWRDN bit and clear the ANEGEN bit in the PHY, putting it into + // its low power mode. + // + EthernetPHYWrite(ulBase, PHY_MR0, + (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_ANEGEN) | + PHY_MR0_PWRDN); +} + +//***************************************************************************** +// +//! Powers on the Ethernet PHY. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function powers on the Ethernet PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function is only +//! called if EthernetPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYPowerOn(unsigned long ulBase) +{ + // + // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into + // normal operating mode. + // + EthernetPHYWrite(ulBase, PHY_MR0, + (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_PWRDN) | + PHY_MR0_ANEGEN); +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm3s8962/Libraries/driverlib/ethernet.h b/bsp/lm3s8962/Libraries/driverlib/ethernet.h index 2f03b39291..015d4b1981 100644 --- a/bsp/lm3s8962/Libraries/driverlib/ethernet.h +++ b/bsp/lm3s8962/Libraries/driverlib/ethernet.h @@ -2,7 +2,7 @@ // // ethernet.h - Defines and Macros for the ethernet module. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -136,10 +136,13 @@ extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr); extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, unsigned long ulData); extern unsigned long EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr); +extern void EthernetPHYPowerOff(unsigned long ulBase); +extern void EthernetPHYPowerOn(unsigned long ulBase); //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/fan.c b/bsp/lm3s8962/Libraries/driverlib/fan.c new file mode 100644 index 0000000000..eb1b887e5d --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/fan.c @@ -0,0 +1,633 @@ +//***************************************************************************** +// +// fan.c - Driver for the FAN controller. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_fan.h" +#include "inc/hw_ints.h" +#include "driverlib/fan.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! \addtogroup fan_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enables a FAN channel for operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to enable. +//! +//! This function enables the specified FAN channel for operation. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Enable the requested channel + // + HWREG(ulBase + FAN_O_CTL) |= 1 << ulChannel; +} + +//***************************************************************************** +// +//! Disables a FAN channel for operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to disable. +//! +//! This function disables the specified FAN channel for operation. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Disable the requested channel + // + HWREG(ulBase + FAN_O_CTL) &= ~(1 << ulChannel); +} + +//***************************************************************************** +// +//! Gets the status of a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to query for status. +//! +//! This function queries and returns the status of the specified channel. +//! The returned value is one of: +//! +//! - \b FAN_STATUS_STALLED if the cooling fan is stalled +//! - \b FAN_STATUS_CHANGING if the fan is changing to the commanded speed +//! - \b FAN_STATUS_LOCKED if the fan is locked at the commanded speed +//! - \b FAN_STATUS_NOATTAIN if the fan cannot achieve the commanded speed +//! +//! \return Returns the status of the specified FAN channel. +// +//***************************************************************************** +unsigned long +FanChannelStatus(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Read and return the status for the specified fan channel + // + return((HWREG(ulBase + FAN_O_STS) >> (ulChannel * 2)) & FAN_STS_ST0_M); +} + +//***************************************************************************** +// +//! Configures a FAN channel for manual operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to configure. +//! \param ulConfig is the logical OR of manual configuration flags. +//! +//! This function configures a specific FAN channel to operate in manual +//! mode. The \e ulConfig parameter is the logical OR of several choices of +//! configuration flags as follows: +//! +//! One of the following to select the number of tachometer pulses used for +//! speed averaging: +//! +//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging +//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging +//! +//! One of the following to select the tachometer pulses per revolution: +//! +//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution +//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution +//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution +//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Program the fan channel for manual mode with parameters. + // + HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = FAN_CH0_MAN | ulConfig; +} + +//***************************************************************************** +// +//! Configures a FAN channel for automatic operation. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to configure. +//! \param ulConfig is the logical OR of configuration flags. +//! +//! This function configures a specific FAN channel to operate in automatic +//! mode. The \e ulConfig parameter is the logical OR of several choices of +//! configuration flags as follows: +//! +//! One of the following to select the automatic restart mode: +//! +//! - \b FAN_CONFIG_RESTART to enable automatic restart after stall +//! - \b FAN_CONFIG_NORESTART to disable automatic restart after stall +//! +//! One of the following to select the acceleration rate when changing speed: +//! +//! - \b FAN_CONFIG_ACCEL_FAST to select fast acceleration +//! - \b FAN_CONFIG_ACCEL_SLOW to select slow acceleration +//! +//! One of the following to select the number of tachometer pulses to use +//! for the hysteresis count: +//! \b FAN_CONFIG_HYST_1, \b FAN_CONFIG_HYST_2, \b FAN_CONFIG_HYST_4, +//! \b FAN_CONFIG_HYST_8, \b FAN_CONFIG_HYST_16, \b FAN_CONFIG_HYST_32, +//! \b FAN_CONFIG_HYST_64, or \b FAN_CONFIG_HYST_128 +//! +//! One of the following to select the start period as the number of tachometer +//! pulses. The start period is the amount of time that a starting PWM duty +//! cycle is used after the FAN channel is commended to a certain speed: +//! \b FAN_CONFIG_START_2, \b FAN_CONFIG_START_4, \b FAN_CONFIG_START_8, +//! \b FAN_CONFIG_START_16, \b FAN_CONFIG_START_32, \b FAN_CONFIG_START_64, +//! \b FAN_CONFIG_START_128, or \b FAN_CONFIG_START_256 +//! +//! One of the following to specify the duty cycle that is used when the FAN +//! channel is starting, during the starting period (above): +//! +//! - \b FAN_CONFIG_START_DUTY_OFF to disable the use of startup duty cycle +//! - \b FAN_CONFIG_START_DUTY_50 to select 50% startup duty cycle +//! - \b FAN_CONFIG_START_DUTY_75 to select 75% startup duty cycle +//! - \b FAN_CONFIG_START_DUTY_100 to select 100% startup duty cycle +//! +//! One of the following to select the number of tachometer pulses used for +//! speed averaging: +//! +//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging +//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging +//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging +//! +//! One of the following to select the tachometer pulses per revolution: +//! +//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution +//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution +//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution +//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Program the fan channel for automatic mode with parameters. + // + HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = ~FAN_CH0_MAN & ulConfig; +} + +//***************************************************************************** +// +//! Sets the duty cycle of a FAN channel when in manual mode. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to program the duty cycle. +//! \param ulDuty is the duty cycle in clocks from 0-511. +//! +//! This function sets the duty cycle of a FAN channel if the channel is +//! configured for manual mode. The duty cycle is specified in clocks from +//! 0-511 out of a 512 clock PWM period. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDuty) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + ASSERT(ulDuty < 512); + + // + // Program the specified duty cycle for the specified channel + // + HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) = + (ulDuty << FAN_CMD0_DC_S) & FAN_CMD0_DC_M; +} + +//***************************************************************************** +// +//! Reads the duty cycle of a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to query for duty cycle. +//! +//! This function gets the duty cycle of a FAN channel. If the channel is in +//! manual mode, then this is the value that was programmed. If the FAN +//! channel is configured for automatic mode, then this is the value that is +//! calculated by the Fan Control peripheral. +//! +//! \return Returns the FAN channel duty cycle as a number of clocks from +//! 0-511, out of a 512 clock PWM period. +// +//***************************************************************************** +unsigned long +FanChannelDutyGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulDuty; + + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Read the duty cycle field from the command register and shift to + // lower bits for return value. + // + ulDuty = HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) & FAN_CMD0_DC_M; + ulDuty >>= FAN_CMD0_DC_S; + + // + // Return the duty cycle for the specified channel. + // + return(ulDuty); +} + +//***************************************************************************** +// +//! Sets the RPM of a FAN channel when in automatic mode. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to program the RPM. +//! \param ulRPM is the RPM as a value from 0-8191. +//! +//! This function sets the RPM of the fan channel if the fan channel is +//! configured for automatic mode. If configured for manual mode, then this +//! function has no effect. +//! +//! \return None. +// +//***************************************************************************** +void +FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulRPM) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + ASSERT(ulRPM < 8192); + + // + // Program the specified RPM for the specified channel + // + HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) = ulRPM; +} + +//***************************************************************************** +// +//! Reads the RPM of a FAN channel. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulChannel is the FAN channel to query for RPM. +//! +//! This function gets the RPM of a FAN channel. +//! +//! \return Returns the FAN channel RPM as a number from 0-4095. +// +//***************************************************************************** +unsigned long +FanChannelRPMGet(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(ulChannel <= 5); + + // + // Read and return the RPM for the specified channel. + // + return(HWREG(ulBase + FAN_O_CST0 + (ulChannel * 0x10)) & FAN_CST0_RPM_M); +} + +//***************************************************************************** +// +//! Enables FAN module interrupts. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulFlags is the logical OR of all the interrupts to be enabled. +//! +//! This function enables one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be enabled. For each channel, the following interrupt flags are +//! available: +//! +//! - \b FAN_CHn_INT_STALL means that a stall was detected (in either mode). +//! - \b FAN_CHn_INT_AUTO_SPEED_ERROR means that in automatic mode, the cooling +//! fan cannot attain the commanded speed. +//! - \b FAN_CHn_INT_AUTO_SPEED_OK means that in automatic mode, the cooling +//! fan has attained the commanded speed. +//! +//! In the above flag names, the \b CHn placeholder should be replaced with +//! the actual channel number, 0-5 (for example, CH1). +//! +//! The interrupt flags have a different meaning if the FAN channel is +//! configured for manual mode. The following alternate set of flag names is +//! available for convenience to use in manual mode: +//! +//! - \b FAN_CHn_INT_MANUAL_SPEED_UPDATE means that in manual mode, the speed +//! was calculated. +//! - \b FAN_CHn_INT_MANUAL_SPEED_CHANGE means that in manual mode, the speed +//! changed. +//! +//! Note that even though the names are different for manual mode, the values +//! are the same. For example \b _AUTO_SPEED_ERROR is the same value as +//! \b _MANUAL_SPEED_UPDATE. The different names are provided just to make it +//! easier to associate a meaning with each interrupt flag. +//! +//! \return None. +// +//***************************************************************************** +void +FanIntEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Enable the requested interrupt sources. + // + HWREG(ulBase + FAN_O_IM) |= ulFlags; +} + +//***************************************************************************** +// +//! Disables FAN module interrupts. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulFlags is the logical OR of all the interrupts to be disabled. +//! +//! This function disables one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be enabled. For a list of possible interrupt flags, refer to the +//! documentation for the function FanIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +FanIntDisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Disable the requested interrupt sources. + // + HWREG(ulBase + FAN_O_IM) &= ~ulFlags; +} + +//***************************************************************************** +// +//! Gets the FAN module interrupt status. +//! +//! \param ulBase is the base address of the FAN module. +//! \param bMasked is set \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the interrupt status of the FAN module. It can +//! return either the raw or masked interrupt status. +//! +//! \return Returns the masked or raw FAN interrupt status, as a bit field +//! of multiple FAN interrupt flags. For a list of all the possible interrupt +//! flags, refer to the documentation for the function FanIntEnable(). +// +//***************************************************************************** +unsigned long +FanIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + FAN_O_MIS)); + } + else + { + return(HWREG(ulBase + FAN_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears pending FAN module interrupts. +//! +//! \param ulBase is the base address of the FAN module. +//! \param ulFlags is the logical OR of all the interrupts to be cleared. +//! +//! This function clears one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be cleared. For a list of possible interrupt flags, refer to the +//! documentation for the function FanIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +FanIntClear(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Clear the requested pending interrupts + // + HWREG(ulBase + FAN_O_IC) = ulFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the FAN module. +//! +//! \param ulBase is the base address of the FAN module. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function sets and enables the handler to be called when the FAN module +//! generates an interrupt. Specific FAN interrupts must still be enabled +//! with the FanIntEnable() function. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_FAN0, pfnHandler); + + // + // Enable the FAN peripheral interrupt. + // + IntEnable(INT_FAN0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the FAN module. +//! +//! \param ulBase is the base address of the FAN module. +//! +//! This function disables and clears the handler to be called when the +//! FAN module interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FanIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Disable the FAN peripheral interrupt. + // + IntDisable(INT_FAN0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FAN0); +} + +//***************************************************************************** +// +//! Gets the number of supported FAN channels. +//! +//! \param ulBase is the base address of the FAN module. +//! +//! This function gets the number of FAN channels that are supported by the +//! Fan Control peripheral. +//! +//! \return Returns the number of FAN channels. +// +//***************************************************************************** +unsigned long +FanChannelsGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == FAN0_BASE); + + // + // Read and return the fan channel count + // + return(HWREG(ulBase + FAN_O_PP) & FAN_PP_CHAN_M); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/fan.h b/bsp/lm3s8962/Libraries/driverlib/fan.h new file mode 100644 index 0000000000..1b9fb94059 --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/fan.h @@ -0,0 +1,168 @@ +//***************************************************************************** +// +// fan.h - Prototypes and macros for the Fan controller. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FAN_H__ +#define __FAN_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Fan status values that can be returned from the FanChannelStatus() function. +// +//***************************************************************************** +#define FAN_STATUS_STALLED 0 +#define FAN_STATUS_CHANGING 1 +#define FAN_STATUS_LOCKED 2 +#define FAN_STATUS_NOATTAIN 3 + +//***************************************************************************** +// +// Configuration flags to be used with FanChannelConfigManual() and +// FanChannelConfigAuto(). +// +//***************************************************************************** +#define FAN_CONFIG_RESTART (1 << 15) +#define FAN_CONFIG_NORESTART (0 << 15) +#define FAN_CONFIG_ACCEL_FAST (1 << 14) +#define FAN_CONFIG_ACCEL_SLOW (0 << 14) +#define FAN_CONFIG_HYST_1 (0 << 11) +#define FAN_CONFIG_HYST_2 (1 << 11) +#define FAN_CONFIG_HYST_4 (2 << 11) +#define FAN_CONFIG_HYST_8 (3 << 11) +#define FAN_CONFIG_HYST_16 (4 << 11) +#define FAN_CONFIG_HYST_32 (5 << 11) +#define FAN_CONFIG_HYST_64 (6 << 11) +#define FAN_CONFIG_HYST_128 (7 << 11) +#define FAN_CONFIG_START_2 (0 << 8) +#define FAN_CONFIG_START_4 (1 << 8) +#define FAN_CONFIG_START_8 (2 << 8) +#define FAN_CONFIG_START_16 (3 << 8) +#define FAN_CONFIG_START_32 (4 << 8) +#define FAN_CONFIG_START_64 (5 << 8) +#define FAN_CONFIG_START_128 (6 << 8) +#define FAN_CONFIG_START_256 (7 << 8) +#define FAN_CONFIG_START_DUTY_OFF (0 << 6) +#define FAN_CONFIG_START_DUTY_50 (1 << 6) +#define FAN_CONFIG_START_DUTY_75 (2 << 6) +#define FAN_CONFIG_START_DUTY_100 (3 << 6) +#define FAN_CONFIG_AVG_NONE (0 << 4) +#define FAN_CONFIG_AVG_2 (1 << 4) +#define FAN_CONFIG_AVG_4 (2 << 4) +#define FAN_CONFIG_AVG_8 (3 << 4) +#define FAN_CONFIG_TACH_1 (0 << 2) +#define FAN_CONFIG_TACH_2 (1 << 2) +#define FAN_CONFIG_TACH_4 (2 << 2) +#define FAN_CONFIG_TACH_8 (3 << 2) + +//***************************************************************************** +// +// Interrupt configuration/status flags to be used with the following +// functions: FanIntEnable(), FanIntDisable(), FanIntStatus(), FanIntClear(). +// +//***************************************************************************** +#define FAN_CH5_INT_AUTO_SPEED_OK (1 << 22) +#define FAN_CH5_INT_MANUAL_SPEED_CHANGE (1 << 22) +#define FAN_CH5_INT_AUTO_SPEED_ERROR (1 << 21) +#define FAN_CH5_INT_MANUAL_SPEED_UPDATE (1 << 21) +#define FAN_CH5_INT_STALL (1 << 20) +#define FAN_CH4_INT_AUTO_SPEED_OK (1 << 18) +#define FAN_CH4_INT_MANUAL_SPEED_CHANGE (1 << 18) +#define FAN_CH4_INT_AUTO_SPEED_ERROR (1 << 17) +#define FAN_CH4_INT_MANUAL_SPEED_UPDATE (1 << 17) +#define FAN_CH4_INT_STALL (1 << 16) +#define FAN_CH3_INT_AUTO_SPEED_OK (1 << 14) +#define FAN_CH3_INT_MANUAL_SPEED_CHANGE (1 << 14) +#define FAN_CH3_INT_AUTO_SPEED_ERROR (1 << 13) +#define FAN_CH3_INT_MANUAL_SPEED_UPDATE (1 << 13) +#define FAN_CH3_INT_STALL (1 << 12) +#define FAN_CH2_INT_AUTO_SPEED_OK (1 << 10) +#define FAN_CH2_INT_MANUAL_SPEED_CHANGE (1 << 10) +#define FAN_CH2_INT_AUTO_SPEED_ERROR (1 << 9) +#define FAN_CH2_INT_MANUAL_SPEED_UPDATE (1 << 9) +#define FAN_CH2_INT_STALL (1 << 8) +#define FAN_CH1_INT_AUTO_SPEED_OK (1 << 6) +#define FAN_CH1_INT_MANUAL_SPEED_CHANGE (1 << 6) +#define FAN_CH1_INT_AUTO_SPEED_ERROR (1 << 5) +#define FAN_CH1_INT_MANUAL_SPEED_UPDATE (1 << 5) +#define FAN_CH1_INT_STALL (1 << 4) +#define FAN_CH0_INT_AUTO_SPEED_OK (1 << 2) +#define FAN_CH0_INT_MANUAL_SPEED_CHANGE (1 << 2) +#define FAN_CH0_INT_AUTO_SPEED_ERROR (1 << 1) +#define FAN_CH0_INT_MANUAL_SPEED_UPDATE (1 << 1) +#define FAN_CH0_INT_STALL (1 << 0) +#define FAN_CHx_INT_AUTO_SPEED_OK(x) (1 << (((x) * 4) + 2)) +#define FAN_CHx_INT_MANUAL_SPEED_CHANGE(x) (1 << (((x) * 4) + 2)) +#define FAN_CHx_INT_AUTO_SPEED_ERROR(x) (1 << (((x) * 4) + 1)) +#define FAN_CHx_INT_MANUAL_SPEED_UPDATE(x) (1 << (((x) * 4) + 1)) +#define FAN_CHx_INT_STALL(x) (1 << ((x) * 4)) + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void FanChannelEnable(unsigned long ulBase, unsigned long ulChannel); +extern void FanChannelDisable(unsigned long ulBase, unsigned long ulChannel); +extern unsigned long FanChannelStatus(unsigned long ulBase, + unsigned long ulChannel); +extern void FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig); +extern void FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig); +extern void FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDuty); +extern unsigned long FanChannelDutyGet(unsigned long ulBase, + unsigned long ulChannel); +extern void FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulRPM); +extern unsigned long FanChannelRPMGet(unsigned long ulBase, + unsigned long ulChannel); +extern void FanIntEnable(unsigned long ulBase, unsigned long ulFlags); +extern void FanIntDisable(unsigned long ulBase, unsigned long ulFlags); +extern unsigned long FanIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void FanIntClear(unsigned long ulBase, unsigned long ulFlags); +extern void FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void FanIntUnregister(unsigned long ulBase); +extern unsigned long FanChannelsGet(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FAN_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/flash.c b/bsp/lm3s8962/Libraries/driverlib/flash.c index 1b2e396575..48dcd7af29 100644 --- a/bsp/lm3s8962/Libraries/driverlib/flash.c +++ b/bsp/lm3s8962/Libraries/driverlib/flash.c @@ -2,7 +2,7 @@ // // flash.c - Driver for programming the on-chip flash. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -70,7 +70,8 @@ static const unsigned long g_pulFMPRERegs[] = //! Gets the number of processor clocks per micro-second. //! //! This function returns the number of clocks per micro-second, as presently -//! known by the flash controller. +//! known by the flash controller. This function is only valid on Sandstorm- +//! and Fury-class devices. //! //! \return Returns the number of processor clocks per micro-second. // @@ -93,7 +94,7 @@ FlashUsecGet(void) //! This function is used to tell the flash controller the number of processor //! clocks per micro-second. This value must be programmed correctly or the //! flash most likely will not program correctly; it has no affect on reading -//! flash. +//! flash. This function is only valid on Sandstorm- and Fury-class devices. //! //! \return None. // @@ -113,11 +114,11 @@ FlashUsecSet(unsigned long ulClocks) //! //! \param ulAddress is the start address of the flash block to be erased. //! -//! This function will erase a 1 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. +//! This function erases a 1-kB block of the on-chip flash. After erasing, +//! the block is filled with 0xFF bytes. Read-only and execute-only blocks +//! cannot be erased. //! -//! This function will not return until the block has been erased. +//! This function does not return until the block has been erased. //! //! \return Returns 0 on success, or -1 if an invalid block address was //! specified or the block is write-protected. @@ -132,9 +133,10 @@ FlashErase(unsigned long ulAddress) ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); // - // Clear the flash access interrupt. + // Clear the flash access and error interrupts. // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC; + HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_ERMISC); // // Erase the block. @@ -150,9 +152,10 @@ FlashErase(unsigned long ulAddress) } // - // Return an error if an access violation occurred. + // Return an error if an access violation or erase error occurred. // - if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS) + if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_ERRIS)) { return(-1); } @@ -173,19 +176,16 @@ FlashErase(unsigned long ulAddress) //! \param ulCount is the number of bytes to be programmed. Must be a multiple //! of four. //! -//! This function will program a sequence of words into the on-chip flash. -//! Programming each location consists of the result of an AND operation -//! of the new data and the existing data; in other words bits that contain -//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed -//! to 1. Therefore, a word can be programmed multiple times as long as these -//! rules are followed; if a program operation attempts to change a 0 bit to -//! a 1 bit, that bit will not have its value changed. +//! This function programs a sequence of words into the on-chip flash. +//! Each word in a page of flash can only be programmed one time between an +//! erase of that page; programming a word multiple times results in an +//! unpredictable value in that word of flash. //! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to +//! Because the flash is programmed one word at a time, the starting address +//! and byte count must both be multiples of four. It is up to the caller to //! verify the programmed contents, if such verification is required. //! -//! This function will not return until the data has been programmed. +//! This function does not return until the data has been programmed. //! //! \return Returns 0 on success, or -1 if a programming error is encountered. // @@ -201,9 +201,10 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress, ASSERT(!(ulCount & 3)); // - // Clear the flash access interrupt. + // Clear the flash access and error interrupts. // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC; + HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC); // // See if this device has a write buffer. @@ -280,7 +281,8 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress, // // Return an error if an access violation occurred. // - if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS) + if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)) { return(-1); } @@ -297,7 +299,7 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress, //! //! \param ulAddress is the start address of the flash block to be queried. //! -//! This function will get the current protection for the specified 2 kB block +//! This function gets the current protection for the specified 2-kB block //! of flash. Each block can be read/write, read-only, or execute-only. //! Read/write blocks can be read, executed, erased, and programmed. Read-only //! blocks can be read and executed. Execute-only blocks can only be executed; @@ -390,17 +392,17 @@ FlashProtectGet(unsigned long ulAddress) //! \param eProtect is the protection to be applied to the block. Can be one //! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. //! -//! This function will set the protection for the specified 2 kB block of -//! flash. Blocks which are read/write can be made read-only or execute-only. -//! Blocks which are read-only can be made execute-only. Blocks which are +//! This function sets the protection for the specified 2-kB block of +//! flash. Blocks that are read/write can be made read-only or execute-only. +//! Blocks that are read-only can be made execute-only. Blocks that are //! execute-only cannot have their protection modified. Attempts to make the -//! block protection less stringent (that is, read-only to read/write) will -//! result in a failure (and be prevented by the hardware). +//! block protection less stringent (that is, read-only to read/write) +//! result in a failure (and are prevented by the hardware). //! //! Changes to the flash protection are maintained only until the next reset. -//! This allows the application to be executed in the desired flash protection -//! environment to check for inappropriate flash access (via the flash -//! interrupt). To make the flash protection permanent, use the +//! This protocol allows the application to be executed in the desired flash +//! protection environment to check for inappropriate flash access (via the +//! flash interrupt). To make the flash protection permanent, use the //! FlashProtectSave() function. //! //! \return Returns 0 on success, or -1 if an invalid address or an invalid @@ -536,7 +538,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) { ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30); ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) & - (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30)); + (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30)); } // @@ -555,11 +557,11 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) // //! Saves the flash protection settings. //! -//! This function will make the currently programmed flash protection settings -//! permanent. This is a non-reversible operation; a chip reset or power cycle -//! will not change the flash protection. +//! This function makes the currently programmed flash protection settings +//! permanent. On some devices, this operation is non-reversible; a chip reset +//! or power cycle does not change the flash protection. //! -//! This function will not return until the protection has been saved. +//! This function does not return until the protection has been saved. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. // @@ -567,7 +569,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) long FlashProtectSave(void) { - int ulTemp, ulLimit; + unsigned long ulTemp, ulLimit; // // If running on a Sandstorm-class device, only trigger a save of the first @@ -604,8 +606,8 @@ FlashProtectSave(void) //! \param pulUser0 is a pointer to the location to store USER Register 0. //! \param pulUser1 is a pointer to the location to store USER Register 1. //! -//! This function will read the contents of user registers (0 and 1), and -//! store them in the specified locations. +//! This function reads the contents of user registers (0 and 1), and +//! stores them in the specified locations. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. // @@ -646,7 +648,7 @@ FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1) //! \param ulUser0 is the value to store in USER Register 0. //! \param ulUser1 is the value to store in USER Register 1. //! -//! This function will set the contents of the user registers (0 and 1) to +//! This function sets the contents of the user registers (0 and 1) to //! the specified values. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. @@ -679,11 +681,11 @@ FlashUserSet(unsigned long ulUser0, unsigned long ulUser1) // //! Saves the user registers. //! -//! This function will make the currently programmed user register settings -//! permanent. This is a non-reversible operation; a chip reset or power cycle -//! will not change this setting. +//! This function makes the currently programmed user register settings +//! permanent. On some devices, this operation is non-reversible; a chip reset +//! or power cycle does not change this setting. //! -//! This function will not return until the protection has been saved. +//! This function does not return until the protection has been saved. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. // @@ -739,12 +741,12 @@ FlashUserSave(void) //! \param pfnHandler is a pointer to the function to be called when the flash //! interrupt occurs. //! -//! This sets the handler to be called when the flash interrupt occurs. The -//! flash controller can generate an interrupt when an invalid flash access +//! This function sets the handler to be called when the flash interrupt occurs. +//! The flash controller can generate an interrupt when an invalid flash access //! occurs, such as trying to program or erase a read-only block, or trying to //! read from an execute-only block. It can also generate an interrupt when a -//! program or erase operation has completed. The interrupt will be -//! automatically enabled when the handler is registered. +//! program or erase operation has completed. The interrupt is automatically +//! enabled when the handler is registered. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -770,9 +772,9 @@ FlashIntRegister(void (*pfnHandler)(void)) // //! Unregisters the interrupt handler for the flash interrupt. //! -//! This function will clear the handler to be called when the flash interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler is no longer called. +//! This function clears the handler to be called when the flash interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -801,9 +803,9 @@ FlashIntUnregister(void) //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values. //! -//! Enables the indicated flash controller interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. +//! This function enables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -824,9 +826,9 @@ FlashIntEnable(unsigned long ulIntFlags) //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values. //! -//! Disables the indicated flash controller interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. +//! This function disables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -847,9 +849,9 @@ FlashIntDisable(unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the flash controller. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the flash controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return The current interrupt status, enumerated as a bit field of //! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS. @@ -880,17 +882,17 @@ FlashIntStatus(tBoolean bMasked) //! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values. //! //! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. This must be done in the interrupt handler to keep it -//! from being called again immediately upon exit. +//! no longer assert. This function must be called in the interrupt handler +//! to keep the interrupt from being triggered again immediately upon exit. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // diff --git a/bsp/lm3s8962/Libraries/driverlib/flash.h b/bsp/lm3s8962/Libraries/driverlib/flash.h index ad84a6c850..e089d43e7a 100644 --- a/bsp/lm3s8962/Libraries/driverlib/flash.h +++ b/bsp/lm3s8962/Libraries/driverlib/flash.h @@ -2,7 +2,7 @@ // // flash.h - Prototypes for the flash driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -56,8 +56,13 @@ tFlashProtection; // returned from FlashIntStatus(). // //***************************************************************************** -#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask -#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask +#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask +#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask +#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask +#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask +#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask +#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/fpu.c b/bsp/lm3s8962/Libraries/driverlib/fpu.c new file mode 100644 index 0000000000..a61be4c95e --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/fpu.c @@ -0,0 +1,284 @@ +//***************************************************************************** +// +// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M +// processor. +// +// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup fpu_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "fpu.h" + +//***************************************************************************** +// +//! Enables the floating-point unit. +//! +//! This function enables the floating-point unit, allowing the floating-point +//! instructions to be executed. This function must be called prior to +//! performing any hardware floating-point operations; failure to do so results +//! in a NOCP usage fault. +//! +//! \return None. +// +//***************************************************************************** +void +FPUEnable(void) +{ + // + // Enable the coprocessors used by the floating-point unit. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); +} + +//***************************************************************************** +// +//! Disables the floating-point unit. +//! +//! This function disables the floating-point unit, preventing floating-point +//! instructions from executing (generating a NOCP usage fault instead). +//! +//! \return None. +// +//***************************************************************************** +void +FPUDisable(void) +{ + // + // Disable the coprocessors used by the floating-point unit. + // + HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & + ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | + NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS); +} + +//***************************************************************************** +// +//! Enables the stacking of floating-point registers. +//! +//! This function enables the stacking of floating-point registers s0-s15 when +//! an interrupt is handled. When enabled, space is reserved on the stack for +//! the floating-point context and the floating-point state is saved into this +//! stack space. Upon return from the interrupt, the floating-point context is +//! restored. +//! +//! If the floating-point registers are not stacked, floating-point +//! instructions cannot be safely executed in an interrupt handler because the +//! values of s0-s15 are not likely to be preserved for the interrupted code. +//! On the other hand, stacking the floating-point registers increases the +//! stacking operation from 8 words to 26 words, also increasing the interrupt +//! response latency. +//! +//! \return None. +// +//***************************************************************************** +void +FPUStackingEnable(void) +{ + // + // Enable automatic state preservation for the floating-point unit, and + // disable lazy state preservation (meaning that the floating-point state + // is always stacked when floating-point instructions are used). + // + HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN; +} + +//***************************************************************************** +// +//! Enables the lazy stacking of floating-point registers. +//! +//! This function enables the lazy stacking of floating-point registers s0-s15 +//! when an interrupt is handled. When lazy stacking is enabled, space is +//! reserved on the stack for the floating-point context, but the +//! floating-point state is not saved. If a floating-point instruction is +//! executed from within the interrupt context, the floating-point context is +//! first saved into the space reserved on the stack. On completion of the +//! interrupt handler, the floating-point context is only restored if it was +//! saved (as the result of executing a floating-point instruction). +//! +//! This method provides a compromise between fast interrupt response (because +//! the floating-point state is not saved on interrupt entry) and the ability +//! to use floating-point in interrupt handlers (because the floating-point +//! state is saved if floating-point instructions are used). +//! +//! \return None. +// +//***************************************************************************** +void +FPULazyStackingEnable(void) +{ + // + // Enable automatic and lazy state preservation for the floating-point + // unit. + // + HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN; +} + +//***************************************************************************** +// +//! Disables the stacking of floating-point registers. +//! +//! This function disables the stacking of floating-point registers s0-s15 when +//! an interrupt is handled. When floating-point context stacking is disabled, +//! floating-point operations performed in an interrupt handler destroy the +//! floating-point context of the main thread of execution. +//! +//! \return None. +// +//***************************************************************************** +void +FPUStackingDisable(void) +{ + // + // Disable automatic and lazy state preservation for the floating-point + // unit. + // + HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN); +} + +//***************************************************************************** +// +//! Selects the format of half-precision floating-point values. +//! +//! \param ulMode is the format for half-precision floating-point value, which +//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. +//! +//! This function selects between the IEEE half-precision floating-point +//! representation and the Cortex-M processor alternative representation. The +//! alternative representation has a larger range but does not have a way to +//! encode infinity (positive or negative) or NaN (quiet or signaling). The +//! default setting is the IEEE format. +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUHalfPrecisionModeSet(unsigned long ulMode) +{ + // + // Set the half-precision floating-point format. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ulMode; +} + +//***************************************************************************** +// +//! Selects the NaN mode. +//! +//! \param ulMode is the mode for NaN results; which is either +//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT. +//! +//! This function selects the handling of NaN results during floating-point +//! computations. NaNs can either propagate (the default), or they can return +//! the default NaN. +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUNaNModeSet(unsigned long ulMode) +{ + // + // Set the NaN mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ulMode; +} + +//***************************************************************************** +// +//! Selects the flush-to-zero mode. +//! +//! \param ulMode is the flush-to-zero mode; which is either +//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN. +//! +//! This function enables or disables the flush-to-zero mode of the +//! floating-point unit. When disabled (the default), the floating-point unit +//! is fully IEEE compliant. When enabled, values close to zero are treated as +//! zero, greatly improving the execution speed at the expense of some accuracy +//! (as well as IEEE compliance). +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPUFlushToZeroModeSet(unsigned long ulMode) +{ + // + // Set the flush-to-zero mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ulMode; +} + +//***************************************************************************** +// +//! Selects the rounding mode for floating-point results. +//! +//! \param ulMode is the rounding mode. +//! +//! This function selects the rounding mode for floating-point results. After +//! a floating-point operation, the result is rounded toward the specified +//! value. The default mode is \b FPU_ROUND_NEAREST. +//! +//! The following rounding modes are available (as specified by \e ulMode): +//! +//! - \b FPU_ROUND_NEAREST - round toward the nearest value +//! - \b FPU_ROUND_POS_INF - round toward positive infinity +//! - \b FPU_ROUND_NEG_INF - round toward negative infinity +//! - \b FPU_ROUND_ZERO - round toward zero +//! +//! \note Unless this function is called prior to executing any floating-point +//! instructions, the default mode is used. +//! +//! \return None. +// +//***************************************************************************** +void +FPURoundingModeSet(unsigned long ulMode) +{ + // + // Set the rounding mode. + // + HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ulMode; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/fpu.h b/bsp/lm3s8962/Libraries/driverlib/fpu.h new file mode 100644 index 0000000000..30d25d5cff --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/fpu.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// fpu.h - Prototypes for the floatint point manipulation routines. +// +// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FPU_H__ +#define __FPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_HALF_IEEE 0x00000000 +#define FPU_HALF_ALTERNATE 0x04000000 + +//***************************************************************************** +// +// Values that can be passed to FPUNaNModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_NAN_PROPAGATE 0x00000000 +#define FPU_NAN_DEFAULT 0x02000000 + +//***************************************************************************** +// +// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 +#define FPU_FLUSH_TO_ZERO_EN 0x01000000 + +//***************************************************************************** +// +// Values that can be passed to FPURoundingModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_ROUND_NEAREST 0x00000000 +#define FPU_ROUND_POS_INF 0x00400000 +#define FPU_ROUND_NEG_INF 0x00800000 +#define FPU_ROUND_ZERO 0x00c00000 + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void FPUEnable(void); +extern void FPUDisable(void); +extern void FPUStackingEnable(void); +extern void FPULazyStackingEnable(void); +extern void FPUStackingDisable(void); +extern void FPUHalfPrecisionModeSet(unsigned long ulMode); +extern void FPUNaNModeSet(unsigned long ulMode); +extern void FPUFlushToZeroModeSet(unsigned long ulMode); +extern void FPURoundingModeSet(unsigned long ulMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FPU_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/gpio.c b/bsp/lm3s8962/Libraries/driverlib/gpio.c index 0e26723f90..0e88fdbe11 100644 --- a/bsp/lm3s8962/Libraries/driverlib/gpio.c +++ b/bsp/lm3s8962/Libraries/driverlib/gpio.c @@ -2,7 +2,7 @@ // // gpio.c - API for GPIO ports // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -55,6 +55,12 @@ static const unsigned long g_pulGPIOBaseAddrs[] = GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE, GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE, GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE, + GPIO_PORTK_BASE, GPIO_PORTK_BASE, + GPIO_PORTL_BASE, GPIO_PORTL_BASE, + GPIO_PORTM_BASE, GPIO_PORTM_BASE, + GPIO_PORTN_BASE, GPIO_PORTN_BASE, + GPIO_PORTP_BASE, GPIO_PORTP_BASE, + GPIO_PORTQ_BASE, GPIO_PORTQ_BASE, }; //***************************************************************************** @@ -82,7 +88,10 @@ GPIOBaseValid(unsigned long ulPort) (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) || (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) || (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) || - (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE)); + (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE) || + (ulPort == GPIO_PORTK_BASE) || (ulPort == GPIO_PORTL_BASE) || + (ulPort == GPIO_PORTM_BASE) || (ulPort == GPIO_PORTN_BASE) || + (ulPort == GPIO_PORTP_BASE) || (ulPort == GPIO_PORTQ_BASE)); } #endif @@ -93,7 +102,8 @@ GPIOBaseValid(unsigned long ulPort) //! //! \param ulPort is the base address of the GPIO port. //! -//! Given a GPIO base address, returns the corresponding interrupt number. +//! Given a GPIO base address, this function returns the corresponding +//! interrupt number. //! //! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. // @@ -101,7 +111,7 @@ GPIOBaseValid(unsigned long ulPort) static long GPIOGetIntNumber(unsigned long ulPort) { - unsigned int ulInt; + long lInt; // // Determine the GPIO interrupt number for the given module. @@ -111,63 +121,99 @@ GPIOGetIntNumber(unsigned long ulPort) case GPIO_PORTA_BASE: case GPIO_PORTA_AHB_BASE: { - ulInt = INT_GPIOA; + lInt = INT_GPIOA; break; } case GPIO_PORTB_BASE: case GPIO_PORTB_AHB_BASE: { - ulInt = INT_GPIOB; + lInt = INT_GPIOB; break; } case GPIO_PORTC_BASE: case GPIO_PORTC_AHB_BASE: { - ulInt = INT_GPIOC; + lInt = INT_GPIOC; break; } case GPIO_PORTD_BASE: case GPIO_PORTD_AHB_BASE: { - ulInt = INT_GPIOD; + lInt = INT_GPIOD; break; } case GPIO_PORTE_BASE: case GPIO_PORTE_AHB_BASE: { - ulInt = INT_GPIOE; + lInt = INT_GPIOE; break; } case GPIO_PORTF_BASE: case GPIO_PORTF_AHB_BASE: { - ulInt = INT_GPIOF; + lInt = INT_GPIOF; break; } case GPIO_PORTG_BASE: case GPIO_PORTG_AHB_BASE: { - ulInt = INT_GPIOG; + lInt = INT_GPIOG; break; } case GPIO_PORTH_BASE: case GPIO_PORTH_AHB_BASE: { - ulInt = INT_GPIOH; + lInt = INT_GPIOH; break; } case GPIO_PORTJ_BASE: case GPIO_PORTJ_AHB_BASE: { - ulInt = INT_GPIOJ; + lInt = INT_GPIOJ; + break; + } + + case GPIO_PORTK_BASE: + { + lInt = INT_GPIOK; + break; + } + + case GPIO_PORTL_BASE: + { + lInt = INT_GPIOL; + break; + } + + case GPIO_PORTM_BASE: + { + lInt = INT_GPIOM; + break; + } + + case GPIO_PORTN_BASE: + { + lInt = INT_GPION; + break; + } + + case GPIO_PORTP_BASE: + { + lInt = INT_GPIOP0; + break; + } + + case GPIO_PORTQ_BASE: + { + lInt = INT_GPIOQ0; break; } @@ -180,7 +226,7 @@ GPIOGetIntNumber(unsigned long ulPort) // // Return GPIO interrupt number. // - return(ulInt); + return(lInt); } //***************************************************************************** @@ -191,8 +237,8 @@ GPIOGetIntNumber(unsigned long ulPort) //! \param ucPins is the bit-packed representation of the pin(s). //! \param ulPinIO is the pin direction and/or mode. //! -//! This function will set the specified pin(s) on the selected GPIO port -//! as either an input or output under software control, or it will set the +//! This function configures the specified pin(s) on the selected GPIO port +//! as either input or output under software control, or it configures the //! pin to be under hardware control. //! //! The parameter \e ulPinIO is an enumerated data type that can be one of @@ -202,11 +248,10 @@ GPIOGetIntNumber(unsigned long ulPort) //! - \b GPIO_DIR_MODE_OUT //! - \b GPIO_DIR_MODE_HW //! -//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as -//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin -//! will be programmed as a software controlled output, and -//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under -//! hardware control. +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a +//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is +//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW +//! specifies that the pin is placed under hardware control. //! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte @@ -300,11 +345,19 @@ GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) //! - \b GPIO_BOTH_EDGES //! - \b GPIO_LOW_LEVEL //! - \b GPIO_HIGH_LEVEL +//! - \b GPIO_DISCRETE_INT //! //! where the different values describe the interrupt detection mechanism //! (edge or level) and the particular triggering event (falling, rising, //! or both edges for edge detect, low or high for level detect). //! +//! Some devices also support discrete interrupts for each pin on a GPIO port, +//! giving each pin a separate interrupt vector. To use this feature, the +//! \b GPIO_DISCRETE_INT can be included to enable an interrupt per pin. The +//! \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports, +//! consult the data sheet to ensure that the device and the GPIO port supports +//! discrete interrupts. +//! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. @@ -350,9 +403,9 @@ GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, //! \param ucPin is the pin number. //! //! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling edge, rising edge, or -//! both edge detected interrupt, or it can be configured as a low level or -//! high level detected interrupt. The type of interrupt detection mechanism +//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or +//! both-edges detected interrupt, or it can be configured as a low-level or +//! high-level detected interrupt. The type of interrupt detection mechanism //! is returned as an enumerated data type. //! //! \return Returns one of the enumerated data types described for @@ -423,7 +476,7 @@ GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) //! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* //! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD //! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an -//! analog input (for the comparators). +//! analog input. //! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte @@ -621,7 +674,7 @@ GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) //! returned. //! //! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. +//! returned; otherwise, the raw interrupt status is returned. //! //! \return Returns a bit-packed byte, where each bit that is set identifies //! an active masked or raw interrupt, and where bit 0 of the byte @@ -663,14 +716,14 @@ GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -697,9 +750,9 @@ GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) //! \param pfnIntHandler is a pointer to the GPIO port interrupt handling //! function. //! -//! This function will ensure that the interrupt handler specified by +//! This function ensures that the interrupt handler specified by //! \e pfnIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function will also enable the corresponding GPIO interrupt +//! GPIO port. This function also enables the corresponding GPIO interrupt //! in the interrupt controller; individual pin interrupts and interrupt //! sources must be enabled with GPIOPinIntEnable(). //! @@ -739,8 +792,8 @@ GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) //! //! \param ulPort is the base address of the GPIO port. //! -//! This function will unregister the interrupt handler for the specified -//! GPIO port. This function will also disable the corresponding +//! This function unregisters the interrupt handler for the specified +//! GPIO port. This function also disables the corresponding //! GPIO port interrupt in the interrupt controller; individual GPIO interrupts //! and interrupt sources must be disabled with GPIOPinIntDisable(). //! @@ -849,15 +902,16 @@ GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) //! \param ucPins is the bit-packed representation of the pin(s). //! //! The analog-to-digital converter input pins must be properly configured -//! to function correctly on DustDevil-class devices. This function provides -//! the proper configuration for those pin(s). +//! to function correctly on devices that are not Sandstorm- or Fury-class. +//! This function provides the proper configuration for those pin(s). //! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an ADC input; it only -//! configures an ADC input pin for proper operation. +//! \note This function cannot be used to turn any pin into an ADC input; it +//! only configures an ADC input pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -897,8 +951,9 @@ GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a CAN pin; it only -//! configures a CAN pin for proper operation. +//! \note This function cannot be used to turn any pin into a CAN pin; it only +//! configures a CAN pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -937,8 +992,10 @@ GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an analog comparator input; -//! it only configures an analog comparator pin for proper operation. +//! \note This function cannot be used to turn any pin into an analog comparator +//! input; it only configures an analog comparator pin for proper operation. +//! Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. //! //! \return None. // @@ -962,6 +1019,174 @@ GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); } +//***************************************************************************** +// +//! Configures pin(s) for use by the external peripheral interface. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The external peripheral interface pins must be properly configured for the +//! external peripheral interface to function correctly. This function +//! provides a typical configuration for those pin(s); other configurations may +//! work as well depending upon the board setup (for example, using the on-chip +//! pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an external +//! peripheral interface pin; it only configures an external peripheral +//! interface pin for proper operation. Devices with flexible pin muxing also +//! require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Ethernet peripheral as LED signals. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The Ethernet peripheral provides two signals that can be used to drive +//! an LED (e.g. for link status/activity). This function provides a typical +//! configuration for the pins. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an Ethernet LED pin; +//! it only configures an Ethernet LED pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Ethernet peripheral as MII signals. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The Ethernet peripheral on some parts provides a set of MII signals that +//! are used to connect to an external PHY. This function provides a typical +//! configuration for the pins. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into an Ethernet MII pin; +//! it only configures an Ethernet MII pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the fan module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The fan pins must be properly configured for the fan controller to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a fan pin; it only +//! configures a fan pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + //***************************************************************************** // //! Configures pin(s) for use as GPIO inputs. @@ -978,6 +1203,9 @@ GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! +//! \note Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! //! \return None. // //***************************************************************************** @@ -1016,6 +1244,9 @@ GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! +//! \note Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! //! \return None. // //***************************************************************************** @@ -1027,15 +1258,15 @@ GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins) // ASSERT(GPIOBaseValid(ulPort)); - // - // Make the pin(s) be outputs. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); - // // Set the pad(s) for standard push-pull operation. // GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); } //***************************************************************************** @@ -1054,6 +1285,9 @@ GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! +//! \note Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! //! \return None. // //***************************************************************************** @@ -1065,15 +1299,15 @@ GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins) // ASSERT(GPIOBaseValid(ulPort)); - // - // Make the pin(s) be outputs. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); - // // Set the pad(s) for standard push-pull operation. // GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); } //***************************************************************************** @@ -1091,8 +1325,9 @@ GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an I2C pin; it only -//! configures an I2C pin for proper operation. +//! \note This function cannot be used to turn any pin into an I2C pin; it +//! only configures an I2C pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1116,6 +1351,221 @@ GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); } +//***************************************************************************** +// +//! Configures pin(s) for use as SCL by the I2C peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for the SCL +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function should only be used for Blizzard-class devices. It +//! cannot be used to turn any pin into an I2C SCL pin; it only configures an +//! I2C SCL pin for proper operation. Devices with flexible pin muxing also +//! require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + if(CLASS_IS_BLIZZARD) + { + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + } + else + { + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); + } +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2S peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some I2S pins must be properly configured for the I2S peripheral to +//! function correctly. This function provides a typical configuration for +//! the digital I2S pin(s); other configurations may work as well depending +//! upon the board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a I2S pin; it only +//! configures a I2S pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the LPC module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The LPC pins must be properly configured for the LPC module to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a LPC pin; it only +//! configures a LPC pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures a pin for receive use by the PECI module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The PECI receive pin must be properly configured for the PECI module to +//! function correctly. This function provides a typical configuration for +//! that pin. +//! +//! The pin is specified using a bit-packed byte, where each bit that is set +//! identifies the pin to be accessed, and where bit 0 of the byte represents +//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a PECI receive pin; +//! it only configures a PECI receive pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures a pin for transmit use by the PECI module. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The PECI transmit pin must be properly configured for the PECI module to +//! function correctly. This function provides a typical configuration for +//! that pin. +//! +//! The pin is specified using a bit-packed byte, where each bit that is set +//! identifies the pin to be accessed, and where bit 0 of the byte represents +//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a PECI transmit pin; +//! it only configures a PECI transmit pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + //***************************************************************************** // //! Configures pin(s) for use by the PWM peripheral. @@ -1132,8 +1582,9 @@ GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a PWM pin; it only -//! configures a PWM pin for proper operation. +//! \note This function cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. Devices wtih flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1173,8 +1624,9 @@ GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a QEI pin; it only -//! configures a QEI pin for proper operation. +//! \note This function cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1214,8 +1666,9 @@ GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a SSI pin; it only -//! configures a SSI pin for proper operation. +//! \note This function cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1255,8 +1708,9 @@ GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a timer pin; it only -//! configures a timer pin for proper operation. +//! \note This function cannot be used to turn any pin into a timer pin; it +//! only configures a timer pin for proper operation. Devices with flexible +//! pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1296,8 +1750,9 @@ GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a UART pin; it only -//! configures a UART pin for proper operation. +//! \note This function cannot be used to turn any pin into a UART pin; it +//! only configures a UART pin for proper operation. Devices with flexible +//! pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1321,51 +1776,6 @@ GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); } -//***************************************************************************** -// -//! Configures pin(s) for use by the USB peripheral. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! -//! Some USB digital pins must be properly configured for the USB peripheral to -//! function correctly. This function provides a typical configuration for -//! the digital USB pin(s); other configurations may work as well depending -//! upon the board setup (for example, using the on-chip pull-ups). -//! -//! This function should only be used with EPEN and PFAULT pins as all other -//! USB pins are analog in nature or are not used in devices without OTG -//! functionality. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - //***************************************************************************** // //! Configures pin(s) for use by the USB peripheral. @@ -1382,8 +1792,9 @@ GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1409,28 +1820,33 @@ GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins) //***************************************************************************** // -//! Configures pin(s) for use by the I2S peripheral. +//! Configures pin(s) for use by the USB peripheral. //! //! \param ulPort is the base address of the GPIO port. //! \param ucPins is the bit-packed representation of the pin(s). //! -//! Some I2S pins must be properly configured for the I2S peripheral to +//! Some USB digital pins must be properly configured for the USB peripheral to //! function correctly. This function provides a typical configuration for -//! the digital I2S pin(s); other configurations may work as well depending +//! the digital USB pin(s); other configurations may work as well depending //! upon the board setup (for example, using the on-chip pull-ups). //! +//! This function should only be used with EPEN and PFAULT pins as all other +//! USB pins are analog in nature or are not used in devices without OTG +//! functionality. +//! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a I2S pin; it only -//! configures a I2S pin for proper operation. +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // //***************************************************************************** void -GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins) +GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins) { // // Check the arguments. @@ -1448,89 +1864,6 @@ GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins) GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); } -//***************************************************************************** -// -//! Configures pin(s) for use by the Ethernet peripheral as LED signals. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! -//! The Ethernet peripheral provides two signals that can be used to drive -//! an LED (e.g. for link status/activity). This function provides a typical -//! configuration for the pins. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This cannot be used to turn any pin into an Ethernet LED pin; it only -//! configures an Ethernet LED pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the external peripheral interface. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! -//! The external peripheral interface pins must be properly configured for the -//! external peripheral interface to function correctly. This function -//! provides a typica configuration for those pin(s); other configurations may -//! work as well depending upon the board setup (for exampe, using the on-chip -//! pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This cannot be used to turn any pin into an external peripheral -//! interface pin; it only configures an external peripheral interface pin for -//! proper operation. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - //***************************************************************************** // //! Configures the alternate function of a GPIO pin. @@ -1542,9 +1875,15 @@ GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins) //! associated with a particular GPIO pin. Only one peripheral function at a //! time can be associated with a GPIO pin, and each peripheral function should //! only be associated with a single GPIO pin at a time (despite the fact that -//! many of them can be associated with more than one GPIO pin). +//! many of them can be associated with more than one GPIO pin). To fully +//! configure a pin, a GPIOPinType*() function should also be called. //! -//! \note This function is only valid on Tempest-class devices. +//! The available mappings are supplied on a per-device basis in +//! pin_map.h. The \b PART_IS_ define enables the +//! appropriate set of defines for the device that is being used. +//! +//! \note This function is not valid on Sandstorm, Fury, and Dustdevil-class +//! devices. //! //! \return None. // @@ -1557,7 +1896,7 @@ GPIOPinConfigure(unsigned long ulPinConfig) // // Check the argument. // - ASSERT(((ulPinConfig >> 16) & 0xff) < 9); + ASSERT(((ulPinConfig >> 16) & 0xff) < 15); ASSERT(((ulPinConfig >> 8) & 0xe3) == 0); // @@ -1569,7 +1908,7 @@ GPIOPinConfigure(unsigned long ulPinConfig) // Get the base address of the GPIO module, selecting either the APB or the // AHB aperture as appropriate. // - if(HWREG(SYSCTL_GPIOHSCTL) & (1 << ulBase)) + if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ulBase)) { ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1]; } @@ -1592,6 +1931,134 @@ GPIOPinConfigure(unsigned long ulPinConfig) } +//***************************************************************************** +// +//! Enables a GPIO pin as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function enables a GPIO pin to be used as a trigger to start a uDMA +//! transaction. Any GPIO pin can be configured to be an external trigger for +//! the uDMA. The GPIO pin still generates interrupts if the interrupt is +//! enabled for the selected pin. +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO DMA Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_DMACTL) |= ucPins; +} + +//***************************************************************************** +// +//! Disables a GPIO pin as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function disables a GPIO pin from being used as a trigger to start a +//! uDMA transaction. This function can be used to disable this feature if it +//! was enabled via a call to GPIODMATriggerEnable(). +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO DMA Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_DMACTL) &= (~ucPins); +} + +//***************************************************************************** +// +//! Enables a GPIO pin as a trigger to start an ADC capture. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function enables a GPIO pin to be used as a trigger to start an ADC +//! sequence. Any GPIO pin can be configured to be an external trigger for +//! an ADC sequence. The GPIO pin still generates interrupts if the +//! interrupt is enabled for the selected pin. To enable the use of a GPIO pin +//! to trigger the ADC module, the ADCSequenceConfigure() function must be called +//! with the ADC_TRIGGER_EXTERNAL parameter. +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO ADC Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_ADCCTL) |= ucPins; +} + +//***************************************************************************** +// +//! Disable a GPIO pin as a trigger to start an ADC capture. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! This function disables a GPIO pin to be used as a trigger to start an ADC +//! sequence. This function can be used to disable this feature if it was +//! enabled via a call to GPIOADCTriggerEnable(). +//! +//! \note This function is not available on all devices, consult the data sheet +//! to ensure that the device you are using supports GPIO ADC Control. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + HWREG(ulPort + GPIO_O_ADCCTL) &= (~ucPins); +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm3s8962/Libraries/driverlib/gpio.h b/bsp/lm3s8962/Libraries/driverlib/gpio.h index cf1046d55e..5320682910 100644 --- a/bsp/lm3s8962/Libraries/driverlib/gpio.h +++ b/bsp/lm3s8962/Libraries/driverlib/gpio.h @@ -2,7 +2,7 @@ // // gpio.h - Defines and Macros for GPIO API. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -72,6 +72,7 @@ extern "C" #define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges #define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level #define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins //***************************************************************************** // @@ -98,616 +99,6 @@ extern "C" #define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down #define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator -//***************************************************************************** -// -// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter. -// -//***************************************************************************** -// -// GPIO pin A0 -// -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C1SCL 0x00000008 -#define GPIO_PA0_U1RX 0x00000009 - -// -// GPIO pin A1 -// -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C1SDA 0x00000408 -#define GPIO_PA1_U1TX 0x00000409 - -// -// GPIO pin A2 -// -#define GPIO_PA2_SSI0CLK 0x00000801 -#define GPIO_PA2_PWM4 0x00000804 -#define GPIO_PA2_I2S0RXSD 0x00000809 - -// -// GPIO pin A3 -// -#define GPIO_PA3_SSI0FSS 0x00000c01 -#define GPIO_PA3_PWM5 0x00000c04 -#define GPIO_PA3_I2S0RXMCLK 0x00000c09 - -// -// GPIO pin A4 -// -#define GPIO_PA4_SSI0RX 0x00001001 -#define GPIO_PA4_PWM6 0x00001004 -#define GPIO_PA4_CAN0RX 0x00001005 -#define GPIO_PA4_I2S0TXSCK 0x00001009 - -// -// GPIO pin A5 -// -#define GPIO_PA5_SSI0TX 0x00001401 -#define GPIO_PA5_PWM7 0x00001404 -#define GPIO_PA5_CAN0TX 0x00001405 -#define GPIO_PA5_I2S0TXWS 0x00001409 - -// -// GPIO pin A6 -// -#define GPIO_PA6_I2C1SCL 0x00001801 -#define GPIO_PA6_CCP1 0x00001802 -#define GPIO_PA6_PWM0 0x00001804 -#define GPIO_PA6_PWM4 0x00001805 -#define GPIO_PA6_CAN0RX 0x00001806 -#define GPIO_PA6_USB0EPEN 0x00001808 -#define GPIO_PA6_U1CTS 0x00001809 - -// -// GPIO pin A7 -// -#define GPIO_PA7_I2C1SDA 0x00001c01 -#define GPIO_PA7_CCP4 0x00001c02 -#define GPIO_PA7_PWM1 0x00001c04 -#define GPIO_PA7_PWM5 0x00001c05 -#define GPIO_PA7_CAN0TX 0x00001c06 -#define GPIO_PA7_CCP3 0x00001c07 -#define GPIO_PA7_USB0PFLT 0x00001c08 -#define GPIO_PA7_U1DCD 0x00001c09 - -// -// GPIO pin B0 -// -#define GPIO_PB0_CCP0 0x00010001 -#define GPIO_PB0_PWM2 0x00010002 -#define GPIO_PB0_U1RX 0x00010005 - -// -// GPIO pin B1 -// -#define GPIO_PB1_CCP2 0x00010401 -#define GPIO_PB1_PWM3 0x00010402 -#define GPIO_PB1_CCP1 0x00010404 -#define GPIO_PB1_U1TX 0x00010405 - -// -// GPIO pin B2 -// -#define GPIO_PB2_I2C0SCL 0x00010801 -#define GPIO_PB2_IDX0 0x00010802 -#define GPIO_PB2_CCP3 0x00010804 -#define GPIO_PB2_CCP0 0x00010805 -#define GPIO_PB2_USB0EPEN 0x00010808 - -// -// GPIO pin B3 -// -#define GPIO_PB3_I2C0SDA 0x00010c01 -#define GPIO_PB3_FAULT0 0x00010c02 -#define GPIO_PB3_FAULT3 0x00010c04 -#define GPIO_PB3_USB0PFLT 0x00010c08 - -// -// GPIO pin B4 -// -#define GPIO_PB4_U2RX 0x00011004 -#define GPIO_PB4_CAN0RX 0x00011005 -#define GPIO_PB4_IDX0 0x00011006 -#define GPIO_PB4_U1RX 0x00011007 -#define GPIO_PB4_EPI0S23 0x00011008 - -// -// GPIO pin B5 -// -#define GPIO_PB5_C0O 0x00011401 -#define GPIO_PB5_CCP5 0x00011402 -#define GPIO_PB5_CCP6 0x00011403 -#define GPIO_PB5_CCP0 0x00011404 -#define GPIO_PB5_CAN0TX 0x00011405 -#define GPIO_PB5_CCP2 0x00011406 -#define GPIO_PB5_U1TX 0x00011407 -#define GPIO_PB5_EPI0S22 0x00011408 - -// -// GPIO pin B6 -// -#define GPIO_PB6_CCP1 0x00011801 -#define GPIO_PB6_CCP7 0x00011802 -#define GPIO_PB6_C0O 0x00011803 -#define GPIO_PB6_FAULT1 0x00011804 -#define GPIO_PB6_IDX0 0x00011805 -#define GPIO_PB6_CCP5 0x00011806 -#define GPIO_PB6_I2S0TXSCK 0x00011809 - -// -// GPIO pin B7 -// -#define GPIO_PB7_NMI 0x00011c04 - -// -// GPIO pin C0 -// -#define GPIO_PC0_TCK 0x00020003 - -// -// GPIO pin C1 -// -#define GPIO_PC1_TMS 0x00020403 - -// -// GPIO pin C2 -// -#define GPIO_PC2_TDI 0x00020803 - -// -// GPIO pin C3 -// -#define GPIO_PC3_TDO 0x00020c03 - -// -// GPIO pin C4 -// -#define GPIO_PC4_CCP5 0x00021001 -#define GPIO_PC4_PHA0 0x00021002 -#define GPIO_PC4_PWM6 0x00021004 -#define GPIO_PC4_CCP2 0x00021005 -#define GPIO_PC4_CCP4 0x00021006 -#define GPIO_PC4_EPI0S2 0x00021008 -#define GPIO_PC4_CCP1 0x00021009 - -// -// GPIO pin C5 -// -#define GPIO_PC5_CCP1 0x00021401 -#define GPIO_PC5_C1O 0x00021402 -#define GPIO_PC5_C0O 0x00021403 -#define GPIO_PC5_FAULT2 0x00021404 -#define GPIO_PC5_CCP3 0x00021405 -#define GPIO_PC5_USB0EPEN 0x00021406 -#define GPIO_PC5_EPI0S3 0x00021408 - -// -// GPIO pin C6 -// -#define GPIO_PC6_CCP3 0x00021801 -#define GPIO_PC6_PHB0 0x00021802 -#define GPIO_PC6_C2O 0x00021803 -#define GPIO_PC6_PWM7 0x00021804 -#define GPIO_PC6_U1RX 0x00021805 -#define GPIO_PC6_CCP0 0x00021806 -#define GPIO_PC6_USB0PFLT 0x00021807 -#define GPIO_PC6_EPI0S4 0x00021808 - -// -// GPIO pin C7 -// -#define GPIO_PC7_CCP4 0x00021c01 -#define GPIO_PC7_PHB0 0x00021c02 -#define GPIO_PC7_CCP0 0x00021c04 -#define GPIO_PC7_U1TX 0x00021c05 -#define GPIO_PC7_USB0PFLT 0x00021c06 -#define GPIO_PC7_C1O 0x00021c07 -#define GPIO_PC7_EPI0S5 0x00021c08 - -// -// GPIO pin D0 -// -#define GPIO_PD0_PWM0 0x00030001 -#define GPIO_PD0_CAN0RX 0x00030002 -#define GPIO_PD0_IDX0 0x00030003 -#define GPIO_PD0_U2RX 0x00030004 -#define GPIO_PD0_U1RX 0x00030005 -#define GPIO_PD0_CCP6 0x00030006 -#define GPIO_PD0_I2S0RXSCK 0x00030008 -#define GPIO_PD0_U1CTS 0x00030009 - -// -// GPIO pin D1 -// -#define GPIO_PD1_PWM1 0x00030401 -#define GPIO_PD1_CAN0TX 0x00030402 -#define GPIO_PD1_PHA0 0x00030403 -#define GPIO_PD1_U2TX 0x00030404 -#define GPIO_PD1_U1TX 0x00030405 -#define GPIO_PD1_CCP7 0x00030406 -#define GPIO_PD1_I2S0RXWS 0x00030408 -#define GPIO_PD1_U1DCD 0x00030409 -#define GPIO_PD1_CCP2 0x0003040a -#define GPIO_PD1_PHB1 0x0003040b - -// -// GPIO pin D2 -// -#define GPIO_PD2_U1RX 0x00030801 -#define GPIO_PD2_CCP6 0x00030802 -#define GPIO_PD2_PWM2 0x00030803 -#define GPIO_PD2_CCP5 0x00030804 -#define GPIO_PD2_EPI0S20 0x00030808 - -// -// GPIO pin D3 -// -#define GPIO_PD3_U1TX 0x00030c01 -#define GPIO_PD3_CCP7 0x00030c02 -#define GPIO_PD3_PWM3 0x00030c03 -#define GPIO_PD3_CCP0 0x00030c04 -#define GPIO_PD3_EPI0S21 0x00030c08 - -// -// GPIO pin D4 -// -#define GPIO_PD4_CCP0 0x00031001 -#define GPIO_PD4_CCP3 0x00031002 -#define GPIO_PD4_I2S0RXSD 0x00031008 -#define GPIO_PD4_U1RI 0x00031009 -#define GPIO_PD4_EPI0S19 0x0003100a - -// -// GPIO pin D5 -// -#define GPIO_PD5_CCP2 0x00031401 -#define GPIO_PD5_CCP4 0x00031402 -#define GPIO_PD5_I2S0RXMCLK 0x00031408 -#define GPIO_PD5_U2RX 0x00031409 -#define GPIO_PD5_EPI0S28 0x0003140a - -// -// GPIO pin D6 -// -#define GPIO_PD6_FAULT0 0x00031801 -#define GPIO_PD6_I2S0TXSCK 0x00031808 -#define GPIO_PD6_U2TX 0x00031809 -#define GPIO_PD6_EPI0S29 0x0003180a - -// -// GPIO pin D7 -// -#define GPIO_PD7_IDX0 0x00031c01 -#define GPIO_PD7_C0O 0x00031c02 -#define GPIO_PD7_CCP1 0x00031c03 -#define GPIO_PD7_I2S0TXWS 0x00031c08 -#define GPIO_PD7_U1DTR 0x00031c09 -#define GPIO_PD7_EPI0S30 0x00031c0a - -// -// GPIO pin E0 -// -#define GPIO_PE0_PWM4 0x00040001 -#define GPIO_PE0_SSI1CLK 0x00040002 -#define GPIO_PE0_CCP3 0x00040003 -#define GPIO_PE0_EPI0S8 0x00040008 -#define GPIO_PE0_USB0PFLT 0x00040009 - -// -// GPIO pin E1 -// -#define GPIO_PE1_PWM5 0x00040401 -#define GPIO_PE1_SSI1FSS 0x00040402 -#define GPIO_PE1_FAULT0 0x00040403 -#define GPIO_PE1_CCP2 0x00040404 -#define GPIO_PE1_CCP6 0x00040405 -#define GPIO_PE1_EPI0S9 0x00040408 - -// -// GPIO pin E2 -// -#define GPIO_PE2_CCP4 0x00040801 -#define GPIO_PE2_SSI1RX 0x00040802 -#define GPIO_PE2_PHB1 0x00040803 -#define GPIO_PE2_PHA0 0x00040804 -#define GPIO_PE2_CCP2 0x00040805 -#define GPIO_PE2_EPI0S24 0x00040808 - -// -// GPIO pin E3 -// -#define GPIO_PE3_CCP1 0x00040c01 -#define GPIO_PE3_SSI1TX 0x00040c02 -#define GPIO_PE3_PHA1 0x00040c03 -#define GPIO_PE3_PHB0 0x00040c04 -#define GPIO_PE3_CCP7 0x00040c05 -#define GPIO_PE3_EPI0S25 0x00040c08 - -// -// GPIO pin E4 -// -#define GPIO_PE4_CCP3 0x00041001 -#define GPIO_PE4_FAULT0 0x00041004 -#define GPIO_PE4_U2TX 0x00041005 -#define GPIO_PE4_CCP2 0x00041006 -#define GPIO_PE4_I2S0TXWS 0x00041009 - -// -// GPIO pin E5 -// -#define GPIO_PE5_CCP5 0x00041401 -#define GPIO_PE5_I2S0TXSD 0x00041409 - -// -// GPIO pin E6 -// -#define GPIO_PE6_PWM4 0x00041801 -#define GPIO_PE6_C1O 0x00041802 -#define GPIO_PE6_U1CTS 0x00041809 - -// -// GPIO pin E7 -// -#define GPIO_PE7_PWM5 0x00041c01 -#define GPIO_PE7_C2O 0x00041c02 -#define GPIO_PE7_U1DCD 0x00041c09 - -// -// GPIO pin F0 -// -#define GPIO_PF0_CAN1RX 0x00050001 -#define GPIO_PF0_PHB0 0x00050002 -#define GPIO_PF0_PWM0 0x00050003 -#define GPIO_PF0_I2S0TXSD 0x00050008 -#define GPIO_PF0_U1DSR 0x00050009 - -// -// GPIO pin F1 -// -#define GPIO_PF1_CAN1TX 0x00050401 -#define GPIO_PF1_IDX1 0x00050402 -#define GPIO_PF1_PWM1 0x00050403 -#define GPIO_PF1_I2S0TXMCLK 0x00050408 -#define GPIO_PF1_U1RTS 0x00050409 -#define GPIO_PF1_CCP3 0x0005040a - -// -// GPIO pin F2 -// -#define GPIO_PF2_LED1 0x00050801 -#define GPIO_PF2_PWM4 0x00050802 -#define GPIO_PF2_PWM2 0x00050804 -#define GPIO_PF2_SSI1CLK 0x00050809 - -// -// GPIO pin F3 -// -#define GPIO_PF3_LED0 0x00050c01 -#define GPIO_PF3_PWM5 0x00050c02 -#define GPIO_PF3_PWM3 0x00050c04 -#define GPIO_PF3_SSI1FSS 0x00050c09 - -// -// GPIO pin F4 -// -#define GPIO_PF4_CCP0 0x00051001 -#define GPIO_PF4_C0O 0x00051002 -#define GPIO_PF4_FAULT0 0x00051004 -#define GPIO_PF4_EPI0S12 0x00051008 -#define GPIO_PF4_SSI1RX 0x00051009 - -// -// GPIO pin F5 -// -#define GPIO_PF5_CCP2 0x00051401 -#define GPIO_PF5_C1O 0x00051402 -#define GPIO_PF5_EPI0S15 0x00051408 -#define GPIO_PF5_SSI1TX 0x00051409 - -// -// GPIO pin F6 -// -#define GPIO_PF6_CCP1 0x00051801 -#define GPIO_PF6_C2O 0x00051802 -#define GPIO_PF6_PHA0 0x00051804 -#define GPIO_PF6_I2S0TXMCLK 0x00051809 -#define GPIO_PF6_U1RTS 0x0005180a - -// -// GPIO pin F7 -// -#define GPIO_PF7_CCP4 0x00051c01 -#define GPIO_PF7_PHB0 0x00051c04 -#define GPIO_PF7_EPI0S12 0x00051c08 -#define GPIO_PF7_FAULT1 0x00051c09 - -// -// GPIO pin G0 -// -#define GPIO_PG0_U2RX 0x00060001 -#define GPIO_PG0_PWM0 0x00060002 -#define GPIO_PG0_I2C1SCL 0x00060003 -#define GPIO_PG0_PWM4 0x00060004 -#define GPIO_PG0_USB0EPEN 0x00060007 -#define GPIO_PG0_EPI0S13 0x00060008 - -// -// GPIO pin G1 -// -#define GPIO_PG1_U2TX 0x00060401 -#define GPIO_PG1_PWM1 0x00060402 -#define GPIO_PG1_I2C1SDA 0x00060403 -#define GPIO_PG1_PWM5 0x00060404 -#define GPIO_PG1_EPI0S14 0x00060408 - -// -// GPIO pin G2 -// -#define GPIO_PG2_PWM0 0x00060801 -#define GPIO_PG2_FAULT0 0x00060804 -#define GPIO_PG2_IDX1 0x00060808 -#define GPIO_PG2_I2S0RXSD 0x00060809 - -// -// GPIO pin G3 -// -#define GPIO_PG3_PWM1 0x00060c01 -#define GPIO_PG3_FAULT2 0x00060c04 -#define GPIO_PG3_FAULT0 0x00060c08 -#define GPIO_PG3_I2S0RXMCLK 0x00060c09 - -// -// GPIO pin G4 -// -#define GPIO_PG4_CCP3 0x00061001 -#define GPIO_PG4_FAULT1 0x00061004 -#define GPIO_PG4_EPI0S15 0x00061008 -#define GPIO_PG4_PWM6 0x00061009 -#define GPIO_PG4_U1RI 0x0006100a - -// -// GPIO pin G5 -// -#define GPIO_PG5_CCP5 0x00061401 -#define GPIO_PG5_IDX0 0x00061404 -#define GPIO_PG5_FAULT1 0x00061405 -#define GPIO_PG5_PWM7 0x00061408 -#define GPIO_PG5_I2S0RXSCK 0x00061409 -#define GPIO_PG5_U1DTR 0x0006140a - -// -// GPIO pin G6 -// -#define GPIO_PG6_PHA1 0x00061801 -#define GPIO_PG6_PWM6 0x00061804 -#define GPIO_PG6_FAULT1 0x00061808 -#define GPIO_PG6_I2S0RXWS 0x00061809 -#define GPIO_PG6_U1RI 0x0006180a - -// -// GPIO pin G7 -// -#define GPIO_PG7_PHB1 0x00061c01 -#define GPIO_PG7_PWM7 0x00061c04 -#define GPIO_PG7_CCP5 0x00061c08 -#define GPIO_PG7_EPI0S31 0x00061c09 - -// -// GPIO pin H0 -// -#define GPIO_PH0_CCP6 0x00070001 -#define GPIO_PH0_PWM2 0x00070002 -#define GPIO_PH0_EPI0S6 0x00070008 -#define GPIO_PH0_PWM4 0x00070009 - -// -// GPIO pin H1 -// -#define GPIO_PH1_CCP7 0x00070401 -#define GPIO_PH1_PWM3 0x00070402 -#define GPIO_PH1_EPI0S7 0x00070408 -#define GPIO_PH1_PWM5 0x00070409 - -// -// GPIO pin H2 -// -#define GPIO_PH2_IDX1 0x00070801 -#define GPIO_PH2_C1O 0x00070802 -#define GPIO_PH2_FAULT3 0x00070804 -#define GPIO_PH2_EPI0S1 0x00070808 - -// -// GPIO pin H3 -// -#define GPIO_PH3_PHB0 0x00070c01 -#define GPIO_PH3_FAULT0 0x00070c02 -#define GPIO_PH3_USB0EPEN 0x00070c04 -#define GPIO_PH3_EPI0S0 0x00070c08 - -// -// GPIO pin H4 -// -#define GPIO_PH4_USB0PFLT 0x00071004 -#define GPIO_PH4_EPI0S10 0x00071008 -#define GPIO_PH4_SSI1CLK 0x0007100b - -// -// GPIO pin H5 -// -#define GPIO_PH5_EPI0S11 0x00071408 -#define GPIO_PH5_FAULT2 0x0007140a -#define GPIO_PH5_SSI1FSS 0x0007140b - -// -// GPIO pin H6 -// -#define GPIO_PH6_EPI0S26 0x00071808 -#define GPIO_PH6_PWM4 0x0007180a -#define GPIO_PH6_SSI1RX 0x0007180b - -// -// GPIO pin H7 -// -#define GPIO_PH7_EPI0S27 0x00071c08 -#define GPIO_PH7_PWM5 0x00071c0a -#define GPIO_PH7_SSI1TX 0x00071c0b - -// -// GPIO pin J0 -// -#define GPIO_PJ0_EPI0S16 0x00080008 -#define GPIO_PJ0_PWM0 0x0008000a -#define GPIO_PJ0_I2C1SCL 0x0008000b - -// -// GPIO pin J1 -// -#define GPIO_PJ1_EPI0S17 0x00080408 -#define GPIO_PJ1_USB0PFLT 0x00080409 -#define GPIO_PJ1_PWM1 0x0008040a -#define GPIO_PJ1_I2C1SDA 0x0008040b - -// -// GPIO pin J2 -// -#define GPIO_PJ2_EPI0S18 0x00080808 -#define GPIO_PJ2_CCP0 0x00080809 -#define GPIO_PJ2_FAULT0 0x0008080a - -// -// GPIO pin J3 -// -#define GPIO_PJ3_EPI0S19 0x00080c08 -#define GPIO_PJ3_U1CTS 0x00080c09 -#define GPIO_PJ3_CCP6 0x00080c0a - -// -// GPIO pin J4 -// -#define GPIO_PJ4_EPI0S28 0x00081008 -#define GPIO_PJ4_U1DCD 0x00081009 -#define GPIO_PJ4_CCP4 0x0008100a - -// -// GPIO pin J5 -// -#define GPIO_PJ5_EPI0S29 0x00081408 -#define GPIO_PJ5_U1DSR 0x00081409 -#define GPIO_PJ5_CCP2 0x0008140a - -// -// GPIO pin J6 -// -#define GPIO_PJ6_EPI0S30 0x00081808 -#define GPIO_PJ6_U1RTS 0x00081809 -#define GPIO_PJ6_CCP1 0x0008180a - -// -// GPIO pin J7 -// -#define GPIO_PJ7_U1DTR 0x00081c09 -#define GPIO_PJ7_CCP0 0x00081c0a - //***************************************************************************** // // Prototypes for the APIs. @@ -741,12 +132,18 @@ extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); @@ -754,6 +151,25 @@ extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins); extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins); +extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins); + +//**************************************************************************** +// +// The definitions for GPIOPinConfigure previously resided in this file but +// have been moved to pin_map.h and made part-specific (in other words, only +// those definitions that are valid based on the selected part, as defined by +// PART_, will be made available). For backwards compatibility, +// pin_map.h is included here so that the expected definitions will still be +// available (though part-specific now, so some that were previously available +// but inappropriate for the given part will not be available). +// +//***************************************************************************** +#ifndef DEPRECATED +#include "pin_map.h" +#endif //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/hibernate.c b/bsp/lm3s8962/Libraries/driverlib/hibernate.c index 6e4c051710..97d0d7fc48 100644 --- a/bsp/lm3s8962/Libraries/driverlib/hibernate.c +++ b/bsp/lm3s8962/Libraries/driverlib/hibernate.c @@ -2,7 +2,7 @@ // // hibernate.c - Driver for the Hibernation module // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -69,9 +69,9 @@ static unsigned long g_ulWriteDelay; //! \param None. //! //! On non-Fury-class devices, the hibernate module provides an indication when -//! any write is completed. This is used to pace writes to the module. This -//! function merely polls this bit and returns as soon as it is set. At this -//! point, it is safe to perform another write to the module. +//! any write is completed. This mechanism is used to pace writes to the +//! module. This function merely polls this bit and returns as soon as it is +//! set. At this point, it is safe to perform another write to the module. //! //! \return None. // @@ -80,10 +80,24 @@ void HibernateWriteComplete(void) { // - // Spin until the write complete bit is set. + // Add a delay here to enforce the required delay between write accesses to + // certain Hibernation module registers. // - while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) + if(CLASS_IS_FURY) { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Spin until the write complete bit is set, for later devices. + // + while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) + { + } } } @@ -94,13 +108,13 @@ HibernateWriteComplete(void) //! \param ulHibClk is the rate of the clock supplied to the Hibernation //! module. //! -//! Enables the Hibernation module for operation. This function should be -//! called before any of the Hibernation module features are used. +//! This function enables the Hibernation module for operation. This function +//! should be called before any of the Hibernation module features are used. //! -//! The peripheral clock will be the same as the processor clock. This will be -//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded -//! if it is constant and known (to save the code/execution overhead of a call -//! to SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). //! //! This function replaces the original HibernateEnable() API and performs the //! same actions. A macro is provided in hibernate.h to map the @@ -128,14 +142,22 @@ HibernateEnableExpClk(unsigned long ulHibClk) (1000L * LOOP_CYCLES)); g_ulWriteDelay++; } + else + { + // + // Non-fury parts must wait for write complete following register + // load (above). + // + HibernateWriteComplete(); + } } //***************************************************************************** // //! Disables the Hibernation module for operation. //! -//! Disables the Hibernation module for operation. After this function is -//! called, none of the Hibernation module features are available. +//! This function disables the Hibernation module for operation. After this +//! function is called, none of the Hibernation module features are available. //! //! \return None. // @@ -147,6 +169,11 @@ HibernateDisable(void) // Turn off the clock enable bit. // HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** @@ -155,15 +182,20 @@ HibernateDisable(void) //! //! \param ulClockInput specifies the clock input. //! -//! Configures the clock input for the Hibernation module. The configuration -//! option chosen depends entirely on hardware design. The clock input for the -//! module will either be a 32.768 kHz oscillator or a 4.194304 MHz crystal. -//! The \e ulClockFlags parameter must be one of the following: +//! This function configures the clock input for the Hibernation module. The +//! configuration option chosen depends entirely on hardware design. The clock +//! input for the module is either a 32.768 kHz oscillator or a 4.194304 MHz +//! crystal. The \e ulClockFlags parameter must be one of the following: //! //! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz //! oscillator. //! - \b HIBERNATE_CLOCK_SEL_DIV128 - use the crystal input, divided by 128. //! +//! \note The \b HIBERNATE_CLOCK_SEL_DIV128 setting is not available on all +//! Stellaris devices. Please consult the data sheet to determine if the +//! device that you are using supports the 4.194304 crystal as a source for the +//! Hibernation module. +//! //! \return None. // //***************************************************************************** @@ -180,16 +212,87 @@ HibernateClockSelect(unsigned long ulClockInput) // Set the clock selection bit according to the parameter. // HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL); + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Configures the clock input for the Hibernation module. +//! +//! \param ulConfig is one of the possible configuration options for the clock +//! input listed below. +//! +//! This function is used to configure the clock input for the Hibernation +//! module. The \e ulConfig parameter can be one of the following values: +//! +//! - \b HIBERNATE_OSC_DISABLE specifies that the internal oscillator +//! is powered off and either an externally supplied clock source or no clock +//! source is being used. +//! - \b HIBERNATE_OSC_HIGHDRIVE specifies a higher drive strength when a 24pF +//! filter capacitor is used with a crystal. +//! - \b HIBERNATE_OSC_LOWDRIVE specifies a lower drive strength when a 12pF +//! filter capacitor is used with a crystal. +//! +//! The \b HIBERNATE_OSC_DISABLE option is used to disable and power down the +//! internal oscillator if an external clock source or no clock source is used +//! instead of a 32.768 kHz crystal. In the case where an external crystal is +//! used, either the \b HIBERNATE_OSC_HIGHDRIVE or \b HIBERNATE_OSC_LOWDRIVE is +//! used. This optimizes the oscillator drive strength to match the size of +//! the filter capacitor that is used with the external crystal circuit. +//! +//! \note The ability to configure the clock input in the Hibernation +//! module is not available on all Stellaris devices. Please consult the data +//! sheet for the Stellaris device that you are using to determine if this +//! feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateClockConfig(unsigned long ulConfig) +{ + unsigned long ulHIBCtl; + + ASSERT((ulConfig & (HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE)) == 0); + + ulHIBCtl = HWREG(HIB_CTL); + + // + // Clear the current configuration bits. + // + ulHIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE); + + // + // Set the new configuration bits. + // + ulHIBCtl |= ulConfig & (HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | + HIBERNATE_OSC_DISABLE); + + // + // Set the hibernation clocking configuration. + // + HWREG(HIB_CTL) = ulHIBCtl; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** // //! Enables the RTC feature of the Hibernation module. //! -//! Enables the RTC in the Hibernation module. The RTC can be used to wake the -//! processor from hibernation at a certain time, or to generate interrupts at -//! certain times. This function must be called before using any of the RTC -//! features of the Hibernation module. +//! This function enables the RTC in the Hibernation module. The RTC can be +//! used to wake the processor from hibernation at a certain time, or to +//! generate interrupts at certain times. This function must be called before +//! using any of the RTC features of the Hibernation module. //! //! \return None. // @@ -201,14 +304,20 @@ HibernateRTCEnable(void) // Turn on the RTC enable bit. // HWREG(HIB_CTL) |= HIB_CTL_RTCEN; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** // //! Disables the RTC feature of the Hibernation module. //! -//! Disables the RTC in the Hibernation module. After calling this function -//! the RTC features of the Hibernation module will not be available. +//! This function disables the RTC in the Hibernation module. After calling +//! this function, the RTC features of the Hibernation module are not +//! available. //! //! \return None. // @@ -220,6 +329,72 @@ HibernateRTCDisable(void) // Turn off the RTC enable bit. // HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Forces the Hibernation module to initiate a check of the battery voltage. +//! +//! This function forces the Hibernation module to initiate a check of the +//! battery voltage immediately rather than waiting for the next check interval +//! to pass. After calling this function, the application should call the +//! () function and wait for the function to return a zero +//! value before calling the HibernateIntStatus() to check if the return code +//! has the \b HIBERNATE_INT_LOW_BAT set. If \b HIBERNATE_INT_LOW_BAT is set +//! this indicates that battery level is low. The application can also enable +//! the \b HIBERNATE_INT_LOW_BAT interrupt and wait for an interrupt to +//! indicate that the battery level is low. +//! +//! \note A hibernation request is held off if a battery check is in progress. +//! This function is only available on some Stellaris devices. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateBatCheckStart(void) +{ + // + // Initiated a forced battery check. + // + HWREG(HIB_CTL) |= HIB_CTL_BATCHK; + + // + // Wait for write completion + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns if a forced battery check has completed. +//! +//! This function returns if the forced battery check initiated by a call to +//! the HibernateBatCheckStart() function has completed. This function +//! returns a non-zero value until the battery level check has completed. Once +//! this function returns a value of zero, the hibernation module has completed +//! the battery check and the HibernateIntStatus() function can be used to +//! check if the battery was low by checking if the value returned has the +//! \b HIBERNATE_INT_LOW_BAT set. +//! +//! \note This function is only available on some Stellaris devices. +//! +//! \return The value is zero when the battery level check has completed or +//! non-zero if the check is still in process. +// +//***************************************************************************** +unsigned long +HibernateBatCheckDone(void) +{ + // + // Read the current state of the batter check. + // + return(HWREG(HIB_CTL) & HIB_CTL_BATCHK); } //***************************************************************************** @@ -228,12 +403,17 @@ HibernateRTCDisable(void) //! //! \param ulWakeFlags specifies which conditions should be used for waking. //! -//! Enables the conditions under which the Hibernation module will wake. The -//! \e ulWakeFlags parameter is the logical OR of any combination of the -//! following: +//! This function enables the conditions under which the Hibernation module +//! wakes. The \e ulWakeFlags parameter is the logical OR of any combination +//! of the following: //! //! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. //! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. +//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low battery +//! level being detected. +//! +//! \note The \b HIBERNATE_WAKE_LOW_BAT parameter is only available on some +//! Stellaris devices. //! //! \return None. // @@ -244,25 +424,38 @@ HibernateWakeSet(unsigned long ulWakeFlags) // // Check the arguments. // - ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC))); + ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT))); // // Set the specified wake flags in the control register. // HWREG(HIB_CTL) = (ulWakeFlags | - (HWREG(HIB_CTL) & - ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC))); + (HWREG(HIB_CTL) & ~(HIBERNATE_WAKE_PIN + | HIBERNATE_WAKE_RTC | + HIBERNATE_WAKE_LOW_BAT))); + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** // //! Gets the currently configured wake conditions for the Hibernation module. //! -//! Returns the flags representing the wake configuration for the Hibernation -//! module. The return value will be a combination of the following flags: +//! This function returns the flags representing the wake configuration for the +//! Hibernation module. The return value is a combination of the following +//! flags: //! //! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. //! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. +//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low battery +//! level being detected. +//! +//! \note The \b HIBERNATE_WAKE_LOW_BAT parameter is only available on some +//! Stellaris devices. //! //! \return Returns flags indicating the configured wake conditions. // @@ -274,7 +467,8 @@ HibernateWakeGet(void) // Read the wake bits from the control register and return // those bits to the caller. // - return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)); + return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC + | HIBERNATE_WAKE_LOW_BAT)); } //***************************************************************************** @@ -283,11 +477,11 @@ HibernateWakeGet(void) //! //! \param ulLowBatFlags specifies behavior of low battery detection. //! -//! Enables the low battery detection and whether hibernation is allowed if a -//! low battery is detected. If low battery detection is enabled, then a low -//! battery condition will be indicated in the raw interrupt status register, -//! and can also trigger an interrupt. Optionally, hibernation can be aborted -//! if a low battery is detected. +//! This function enables the low battery detection and whether hibernation is +//! allowed if a low battery is detected. If low battery detection is enabled, +//! then a low battery condition is indicated in the raw interrupt status +//! register, and can also trigger an interrupt. Optionally, hibernation can be +//! aborted if a low battery is detected. //! //! The \e ulLowBatFlags parameter is one of the following values: //! @@ -295,6 +489,23 @@ HibernateWakeGet(void) //! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort //! hibernation if low battery is detected. //! +//! The other setting in the \e ulLowBatFlags allows the caller to set one of +//! the following voltage level trigger values : +//! +//! - \b HIBERNATE_LOW_BAT_1_9V - voltage low level is 1.9V +//! - \b HIBERNATE_LOW_BAT_2_1V - voltage low level is 2.1V +//! - \b HIBERNATE_LOW_BAT_2_3V - voltage low level is 2.3V +//! - \b HIBERNATE_LOW_BAT_2_5V - voltage low level is 2.5V +//! +//! \b Example: Abort hibernate if the voltage level is below 2.1V. +//! +//! \verbatim +//! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V); +//! \endverbatim +//! +//! \note The parameters with the specific voltage levels are only available on +//! some Stellaris devices. +//! //! \return None. // //***************************************************************************** @@ -304,27 +515,31 @@ HibernateLowBatSet(unsigned long ulLowBatFlags) // // Check the arguments. // - ASSERT((ulLowBatFlags == HIBERNATE_LOW_BAT_DETECT) || - (ulLowBatFlags == HIBERNATE_LOW_BAT_ABORT)); + ASSERT(!(ulLowBatFlags & ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT))); // // Set the low battery detect and abort bits in the control register, // according to the parameter. // HWREG(HIB_CTL) = (ulLowBatFlags | - (HWREG(HIB_CTL) & ~HIBERNATE_LOW_BAT_ABORT)); + (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M + | HIBERNATE_LOW_BAT_ABORT))); + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** // //! Gets the currently configured low battery detection behavior. //! -//! Returns a value representing the currently configured low battery detection -//! behavior. The return value will be one of the following: +//! This function returns a value representing the currently configured low +//! battery detection behavior. //! -//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition. -//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort -//! hibernation if low battery is detected. +//! The return value is a combination of the values described in the +//! HibernateLowBatSet() function. //! //! \return Returns a value indicating the configured low battery detection. // @@ -333,10 +548,10 @@ unsigned long HibernateLowBatGet(void) { // - // Read the low bat bits from the control register and return those bits to - // the caller. + // Read the supported low bat bits from the control register and return + // those bits to the caller. // - return(HWREG(HIB_CTL) & HIBERNATE_LOW_BAT_ABORT); + return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)); } //***************************************************************************** @@ -345,8 +560,8 @@ HibernateLowBatGet(void) //! //! \param ulRTCValue is the new value for the RTC. //! -//! Sets the value of the RTC. The RTC will count seconds if the hardware is -//! configured correctly. The RTC must be enabled by calling +//! This function sets the value of the RTC. The RTC count seconds if the +//! hardware is configured correctly. The RTC must be enabled by calling //! HibernateRTCEnable() before calling this function. //! //! \return None. @@ -361,30 +576,16 @@ HibernateRTCSet(unsigned long ulRTCValue) HWREG(HIB_RTCLD) = ulRTCValue; // - // Add a delay here to enforce the required delay between write accesses to - // certain Hibernation module registers. + // Wait for write completion // - if(CLASS_IS_FURY) - { - // - // Delay a fixed time on Fury-class devices - // - SysCtlDelay(g_ulWriteDelay); - } - else - { - // - // Wait for write complete to be signaled on later devices. - // - HibernateWriteComplete(); - } + HibernateWriteComplete(); } //***************************************************************************** // //! Gets the value of the real time clock (RTC) counter. //! -//! Gets the value of the RTC and returns it to the caller. +//! This function gets the value of the RTC and returns it to the caller. //! //! \return Returns the value of the RTC. // @@ -404,9 +605,10 @@ HibernateRTCGet(void) //! //! \param ulMatch is the value for the match register. //! -//! Sets the match 0 register for the RTC. The Hibernation module can be -//! configured to wake from hibernation, and/or generate an interrupt when the -//! value of the RTC counter is the same as the match register. +//! This function sets the match 0 register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. //! //! \return None. // @@ -420,30 +622,16 @@ HibernateRTCMatch0Set(unsigned long ulMatch) HWREG(HIB_RTCM0) = ulMatch; // - // Add a delay here to enforce the required delay between write accesses to - // certain Hibernation module registers. + // Wait for write completion // - if(CLASS_IS_FURY) - { - // - // Delay a fixed time on Fury-class devices - // - SysCtlDelay(g_ulWriteDelay); - } - else - { - // - // Wait for write complete to be signaled on later devices. - // - HibernateWriteComplete(); - } + HibernateWriteComplete(); } //***************************************************************************** // //! Gets the value of the RTC match 0 register. //! -//! Gets the value of the match 0 register for the RTC. +//! This function gets the value of the match 0 register for the RTC. //! //! \return Returns the value of the match register. // @@ -463,9 +651,14 @@ HibernateRTCMatch0Get(void) //! //! \param ulMatch is the value for the match register. //! -//! Sets the match 1 register for the RTC. The Hibernation module can be -//! configured to wake from hibernation, and/or generate an interrupt when the -//! value of the RTC counter is the same as the match register. +//! This function sets the match 1 register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. +//! +//! \note The Hibernation RTC Match 1 feature is not available on all Stellaris +//! devices. Please consult the data sheet for the Stellaris device that you +//! are using to determine if this feature is available. //! //! \return None. // @@ -479,30 +672,20 @@ HibernateRTCMatch1Set(unsigned long ulMatch) HWREG(HIB_RTCM1) = ulMatch; // - // Add a delay here to enforce the required delay between write accesses to - // certain Hibernation module registers. + // Wait for write completion // - if(CLASS_IS_FURY) - { - // - // Delay a fixed time on Fury-class devices - // - SysCtlDelay(g_ulWriteDelay); - } - else - { - // - // Wait for write complete to be signaled on later devices. - // - HibernateWriteComplete(); - } + HibernateWriteComplete(); } //***************************************************************************** // //! Gets the value of the RTC match 1 register. //! -//! Gets the value of the match 1 register for the RTC. +//! This function gets the value of the match 1 register for the RTC. +//! +//! \note The Hibernation RTC Match 1 feature is not available on all Stellaris +//! devices. Please consult the data sheet for the Stellaris device that you +//! are using to determine if this feature is available. //! //! \return Returns the value of the match register. // @@ -516,20 +699,99 @@ HibernateRTCMatch1Get(void) return(HWREG(HIB_RTCM1)); } +//***************************************************************************** +// +//! Sets the value of the RTC sub second match 0 register. +//! +//! \param ulMatch is the value for the sub second match register. +//! +//! This function sets the sub second match 0 register for the RTC in 1/32768 +//! of a second increments. The Hibernation module can be configured to wake +//! from hibernation, and/or generate an interrupt when the value of the RTC +//! counter is the same as the match combined with the sub second match +//! register. +//! +//! \note The Hibernation sub second RTC Match 0 feature is not available on +//! all Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCSSMatch0Set(unsigned long ulMatch) +{ + // + // Write the new sub second match value to the sub second match register. + // + HWREG(HIB_RTCSS) = ulMatch << HIB_RTCSS_RTCSSM_S; + + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); +} + +//***************************************************************************** +// +//! Returns the value of the RTC sub second match 0 register. +//! +//! This function returns the current value of the sub second match 0 register +//! for the RTC. The value returned is in 1/32768 second increments. +//! +//! \note The Hibernation sub second RTC Match 0 feature is not available on +//! all Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine if this feature is available. +//! +//! \return Returns the value of the sub section match register. +// +//***************************************************************************** +unsigned long +HibernateRTCSSMatch0Get(void) +{ + // + // Read the current second RTC count. + // + return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S); +} + +//***************************************************************************** +// +//! Returns the current value of the RTC sub second count. +//! +//! This function returns the current value of the sub second count for the +//! for the RTC in 1/32768 of a second increments. +//! +//! \note The Hibernation sub second RTC Match 0 feature is not available on +//! all Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine if this feature is available. +//! +//! \return The current RTC sub second count in 1/32768 seconds. +// +//***************************************************************************** +unsigned long +HibernateRTCSSGet(void) +{ + // + // Read the current second RTC count. + // + return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M); +} + //***************************************************************************** // //! Sets the value of the RTC predivider trim register. //! //! \param ulTrim is the new value for the pre-divider trim register. //! -//! Sets the value of the pre-divider trim register. The input time source is -//! divided by the pre-divider to achieve a one-second clock rate. Once every -//! 64 seconds, the value of the pre-divider trim register is applied to the -//! predivider to allow fine-tuning of the RTC rate, in order to make -//! corrections to the rate. The software application can make adjustments to -//! the predivider trim register to account for variations in the accuracy of -//! the input time source. The nominal value is 0x7FFF, and it can be adjusted -//! up or down in order to fine-tune the RTC rate. +//! This function sets the value of the pre-divider trim register. The input +//! time source is divided by the pre-divider to achieve a one-second clock +//! rate. Once every 64 seconds, the value of the pre-divider trim register is +//! applied to the predivider to allow fine-tuning of the RTC rate, in order +//! to make corrections to the rate. The software application can make +//! adjustments to the predivider trim register to account for variations in +//! the accuracy of the input time source. The nominal value is 0x7FFF, and it +//! can be adjusted up or down in order to fine-tune the RTC rate. //! //! \return None. // @@ -548,32 +810,18 @@ HibernateRTCTrimSet(unsigned long ulTrim) HWREG(HIB_RTCT) = ulTrim; // - // Add a delay here to enforce the required delay between write accesses to - // certain Hibernation module registers. + // Wait for write completion // - if(CLASS_IS_FURY) - { - // - // Delay a fixed time on Fury-class devices - // - SysCtlDelay(g_ulWriteDelay); - } - else - { - // - // Wait for write complete to be signaled on later devices. - // - HibernateWriteComplete(); - } + HibernateWriteComplete(); } //***************************************************************************** // //! Gets the value of the RTC predivider trim register. //! -//! Gets the value of the pre-divider trim register. This function can be used -//! to get the current value of the trim register prior to making an adjustment -//! by using the HibernateRTCTrimSet() function. +//! This function gets the value of the pre-divider trim register. This +//! function can be used to get the current value of the trim register prior +//! to making an adjustment by using the HibernateRTCTrimSet() function. //! //! \return None. // @@ -589,26 +837,31 @@ HibernateRTCTrimGet(void) //***************************************************************************** // -//! Stores data in the non-volatile memory of the Hibernation module. +//! Stores data in the battery-backed memory of the Hibernation module. //! //! \param pulData points to the data that the caller wants to store in the //! memory of the Hibernation module. //! \param ulCount is the count of 32-bit words to store. //! -//! Stores a set of data in the Hibernation module non-volatile memory. This -//! memory will be preserved when the power to the processor is turned off, and -//! can be used to store application state information which will be available +//! Stores a set of data in the Hibernation module battery-backed memory. +//! This memory is preserved when the power to the processor is turned off, +//! and can be used to store application state information which is available //! when the processor wakes. Up to 64 32-bit words can be stored in the -//! non-volatile memory. The data can be restored by calling the +//! battery-backed memory. The data can be restored by calling the //! HibernateDataGet() function. //! +//! \note The amount of memory available in the Hibernation module varies +//! across Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine the amount of memory available in +//! the Hibernation module. +//! //! \return None. // //***************************************************************************** void HibernateDataSet(unsigned long *pulData, unsigned long ulCount) { - unsigned int uIdx; + unsigned long ulIdx; // // Check the arguments. @@ -619,45 +872,39 @@ HibernateDataSet(unsigned long *pulData, unsigned long ulCount) // // Loop through all the words to be stored, storing one at a time. // - for(uIdx = 0; uIdx < ulCount; uIdx++) + for(ulIdx = 0; ulIdx < ulCount; ulIdx++) { // - // Write a word to the non-volatile storage area. + // Write a word to the battery-backed storage area. // - HWREG(HIB_DATA + (uIdx * 4)) = pulData[uIdx]; + HWREG(HIB_DATA + (ulIdx * 4)) = pulData[ulIdx]; // - // Add a delay between writes to the data area. + // Wait for write completion // - if(CLASS_IS_FURY) - { - // - // Delay a fixed time on Fury-class devices - // - SysCtlDelay(g_ulWriteDelay); - } - else - { - // - // Wait for write complete to be signaled on later devices. - // - HibernateWriteComplete(); - } + HibernateWriteComplete(); } } //***************************************************************************** // -//! Reads a set of data from the non-volatile memory of the Hibernation module. +//! Reads a set of data from the battery-backed memory of the Hibernation +//! module. //! //! \param pulData points to a location where the data that is read from the -//! Hibernation module will be stored. +//! Hibernation module is stored. //! \param ulCount is the count of 32-bit words to read. //! -//! Retrieves a set of data from the Hibernation module non-volatile memory -//! that was previously stored with the HibernateDataSet() function. The -//! caller must ensure that \e pulData points to a large enough memory block to -//! hold all the data that is read from the non-volatile memory. +//! This function retrieves a set of data from the Hibernation module battery- +//! backed memory that was previously stored with the HibernateDataSet() +//! function. The caller must ensure that \e pulData points to a large enough +//! memory block to hold all the data that is read from the battery-backed +//! memory. +//! +//! \note The amount of memory available in the Hibernation module varies +//! across Stellaris devices. Please consult the data sheet for the Stellaris +//! device that you are using to determine the amount of memory available in +//! the Hibernation module. //! //! \return None. // @@ -665,7 +912,7 @@ HibernateDataSet(unsigned long *pulData, unsigned long ulCount) void HibernateDataGet(unsigned long *pulData, unsigned long ulCount) { - unsigned int uIdx; + unsigned long ulIdx; // // Check the arguments. @@ -676,13 +923,13 @@ HibernateDataGet(unsigned long *pulData, unsigned long ulCount) // // Loop through all the words to be restored, reading one at a time. // - for(uIdx = 0; uIdx < ulCount; uIdx++) + for(ulIdx = 0; ulIdx < ulCount; ulIdx++) { // - // Read a word from the non-volatile storage area. No delay is + // Read a word from the battery-backed storage area. No delay is // required between reads. // - pulData[uIdx] = HWREG(HIB_DATA + (uIdx * 4)); + pulData[ulIdx] = HWREG(HIB_DATA + (ulIdx * 4)); } } @@ -692,24 +939,25 @@ HibernateDataGet(unsigned long *pulData, unsigned long ulCount) //! //! This function requests the Hibernation module to disable the external //! regulator, thus removing power from the processor and all peripherals. The -//! Hibernation module will remain powered from the battery or auxiliary power +//! Hibernation module remains powered from the battery or auxiliary power //! supply. //! -//! The Hibernation module will re-enable the external regulator when one of +//! The Hibernation module re-enables the external regulator when one of //! the configured wake conditions occurs (such as RTC match or external -//! \b WAKE pin). When the power is restored the processor will go through a -//! normal power-on reset. The processor can retrieve saved state information -//! with the HibernateDataGet() function. Prior to calling the function to -//! request hibernation mode, the conditions for waking must have already been -//! set by using the HibernateWakeSet() function. +//! \b WAKE pin). When the power is restored the processor goes through a +//! power-on reset although the Hibernation module is not reset. The processor +//! can retrieve saved state information with the HibernateDataGet() function. +//! Prior to calling the function to request hibernation mode, the conditions +//! for waking must have already been set by using the HibernateWakeSet() +//! function. //! //! Note that this function may return because some time may elapse before the //! power is actually removed, or it may not be removed at all. For this -//! reason, the processor will continue to execute instructions for some time +//! reason, the processor continues to execute instructions for some time //! and the caller should be prepared for this function to return. There are //! various reasons why the power may not be removed. For example, if the //! HibernateLowBatSet() function was used to configure an abort if low -//! battery is detected, then the power will not be removed if the battery +//! battery is detected, then the power is not removed if the battery //! voltage is too low. There may be other reasons, related to the external //! circuit design, that a request for hibernation may not actually occur. //! @@ -727,6 +975,11 @@ HibernateRequest(void) // Set the bit in the control register to cut main power to the processor. // HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** @@ -735,16 +988,23 @@ HibernateRequest(void) //! //! \param ulIntFlags is the bit mask of the interrupts to be enabled. //! -//! Enables the specified interrupt sources from the Hibernation module. +//! This function enables the specified interrupt sources from the Hibernation +//! module. //! //! The \e ulIntFlags parameter must be the logical OR of any combination of //! the following: //! +//! - \b HIBERNATE_INT_WR_COMPLETE - write complete interrupt //! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt //! - \b HIBERNATE_INT_LOW_BAT - low battery interrupt //! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt //! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt //! +//! \note The \b HIBERNATE_INT_WR_COMPLETE and \b HIBERNATE_INT_RTC_MATCH_1 +//! settings are not available on all Stellaris devices. Please consult the +//! data sheet for the Stellaris device that you are using to determine if +//! these interrupt sources are available. +//! //! \return None. // //***************************************************************************** @@ -756,12 +1016,18 @@ HibernateIntEnable(unsigned long ulIntFlags) // ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_RTC_MATCH_1))); + HIBERNATE_INT_RTC_MATCH_1 | + HIBERNATE_INT_WR_COMPLETE))); // // Set the specified interrupt mask bits. // HWREG(HIB_IM) |= ulIntFlags; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** @@ -770,7 +1036,8 @@ HibernateIntEnable(unsigned long ulIntFlags) //! //! \param ulIntFlags is the bit mask of the interrupts to be disabled. //! -//! Disables the specified interrupt sources from the Hibernation module. +//! This function disables the specified interrupt sources from the +//! Hibernation module. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to the HibernateIntEnable() function. @@ -786,12 +1053,18 @@ HibernateIntDisable(unsigned long ulIntFlags) // ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_RTC_MATCH_1))); + HIBERNATE_INT_RTC_MATCH_1 | + HIBERNATE_INT_WR_COMPLETE))); // // Clear the specified interrupt mask bits. // HWREG(HIB_IM) &= ~ulIntFlags; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** @@ -801,9 +1074,10 @@ HibernateIntDisable(unsigned long ulIntFlags) //! \param pfnHandler points to the function to be called when a hibernation //! interrupt occurs. //! -//! Registers the interrupt handler in the system interrupt controller. The -//! interrupt is enabled at the global level, but individual interrupt sources -//! must still be enabled with a call to HibernateIntEnable(). +//! This function registers the interrupt handler in the system interrupt +//! controller. The interrupt is enabled at the global level, but individual +//! interrupt sources must still be enabled with a call to +//! HibernateIntEnable(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -829,9 +1103,9 @@ HibernateIntRegister(void (*pfnHandler)(void)) // //! Unregisters an interrupt handler for the Hibernation module interrupt. //! -//! Unregisters the interrupt handler in the system interrupt controller. The -//! interrupt is disabled at the global level, and the interrupt handler will -//! no longer be called. +//! This function unregisters the interrupt handler in the system interrupt +//! controller. The interrupt is disabled at the global level, and the +//! interrupt handler is longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -860,9 +1134,9 @@ HibernateIntUnregister(void) //! \param bMasked is false to retrieve the raw interrupt status, and true to //! retrieve the masked interrupt status. //! -//! Returns the interrupt status of the Hibernation module. The caller can use -//! this to determine the cause of a hibernation interrupt. Either the masked -//! or raw interrupt status can be returned. +//! This function returns the interrupt status of the Hibernation module. The +//! caller can use this function to determine the cause of a hibernation +//! interrupt. Either the masked or raw interrupt status can be returned. //! //! \return Returns the interrupt status as a bit field with the values as //! described in the HibernateIntEnable() function. @@ -890,20 +1164,21 @@ HibernateIntStatus(tBoolean bMasked) //! //! \param ulIntFlags is the bit mask of the interrupts to be cleared. //! -//! Clears the specified interrupt sources. This must be done from within the -//! interrupt handler or else the handler will be called again upon exit. +//! This function clears the specified interrupt sources. This function must +//! be called within the interrupt handler or else the handler is called again +//! upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to the HibernateIntEnable() function. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -922,6 +1197,11 @@ HibernateIntClear(unsigned long ulIntFlags) // Write the specified interrupt bits into the interrupt clear register. // HWREG(HIB_IC) |= ulIntFlags; + + // + // Wait for write completion + // + HibernateWriteComplete(); } //***************************************************************************** @@ -945,7 +1225,7 @@ HibernateIntClear(unsigned long ulIntFlags) //! not. // //***************************************************************************** -unsigned int +unsigned long HibernateIsActive(void) { // diff --git a/bsp/lm3s8962/Libraries/driverlib/hibernate.h b/bsp/lm3s8962/Libraries/driverlib/hibernate.h index 02f54a0f7b..87cdf3d558 100644 --- a/bsp/lm3s8962/Libraries/driverlib/hibernate.h +++ b/bsp/lm3s8962/Libraries/driverlib/hibernate.h @@ -2,7 +2,7 @@ // // hibernate.h - API definition for the Hibernation module. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -41,34 +41,50 @@ extern "C" // Macros needed for selecting the clock source for HibernateClockSelect() // //***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 +#define HIBERNATE_CLOCK_SEL_RAW 0x00000004 +#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000 //***************************************************************************** // // Macros need to configure wake events for HibernateWakeSet() // //***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 +#define HIBERNATE_WAKE_PIN 0x00000010 +#define HIBERNATE_WAKE_RTC 0x00000008 +#define HIBERNATE_WAKE_LOW_BAT 0x00000200 //***************************************************************************** // // Macros needed to configure low battery detect for HibernateLowBatSet() // //***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 +#define HIBERNATE_LOW_BAT_DETECT 0x00000020 +#define HIBERNATE_LOW_BAT_ABORT 0x000000A0 +#define HIBERNATE_LOW_BAT_1_9V 0x00000000 +#define HIBERNATE_LOW_BAT_2_1V 0x00002000 +#define HIBERNATE_LOW_BAT_2_3V 0x00004000 +#define HIBERNATE_LOW_BAT_2_5V 0x00006000 //***************************************************************************** // // Macros defining interrupt source bits for the interrupt functions. // //***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 +#define HIBERNATE_INT_WR_COMPLETE 0x00000010 +#define HIBERNATE_INT_PIN_WAKE 0x00000008 +#define HIBERNATE_INT_LOW_BAT 0x00000004 +#define HIBERNATE_INT_RTC_MATCH_0 0x00000001 +#define HIBERNATE_INT_RTC_MATCH_1 0x00000002 + +//***************************************************************************** +// +// Macros defining oscillator configuration options for the +// HibernateClockConfig() function. +// +//***************************************************************************** +#define HIBERNATE_OSC_LOWDRIVE 0x00040000 +#define HIBERNATE_OSC_HIGHDRIVE 0x00060000 +#define HIBERNATE_OSC_DISABLE 0x00010000 //***************************************************************************** // @@ -101,7 +117,13 @@ extern void HibernateIntRegister(void (*pfnHandler)(void)); extern void HibernateIntUnregister(void); extern unsigned long HibernateIntStatus(tBoolean bMasked); extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); +extern unsigned long HibernateIsActive(void); +extern void HibernateRTCSSMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCSSMatch0Get(void); +extern unsigned long HibernateRTCSSGet(void); +extern void HibernateClockConfig(unsigned long ulConfig); +extern void HibernateBatCheckStart(void); +extern unsigned long HibernateBatCheckDone(void); //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/i2c.c b/bsp/lm3s8962/Libraries/driverlib/i2c.c index b47148c34d..87d363e9f6 100644 --- a/bsp/lm3s8962/Libraries/driverlib/i2c.c +++ b/bsp/lm3s8962/Libraries/driverlib/i2c.c @@ -2,7 +2,7 @@ // // i2c.c - Driver for Inter-IC (I2C) bus block. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -38,6 +38,110 @@ #include "driverlib/i2c.h" #include "driverlib/interrupt.h" +//***************************************************************************** +// +// A mapping of I2C base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulI2CIntMap[][2] = +{ + { I2C0_MASTER_BASE, INT_I2C0 }, + { I2C1_MASTER_BASE, INT_I2C1 }, + { I2C2_MASTER_BASE, INT_I2C2 }, + { I2C3_MASTER_BASE, INT_I2C3 }, + { I2C4_MASTER_BASE, INT_I2C4 }, + { I2C5_MASTER_BASE, INT_I2C5 }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a I2C master base address. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function determines if a I2C master module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +I2CMasterBaseValid(unsigned long ulBase) +{ + return((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE) || + (ulBase == I2C2_MASTER_BASE) || (ulBase == I2C3_MASTER_BASE) || + (ulBase == I2C4_MASTER_BASE) || (ulBase == I2C5_MASTER_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a I2C slave base address. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function determines if a I2C slave module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +I2CSlaveBaseValid(unsigned long ulBase) +{ + return((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE) || + (ulBase == I2C2_SLAVE_BASE) || (ulBase == I2C3_SLAVE_BASE) || + (ulBase == I2C4_SLAVE_BASE) || (ulBase == I2C5_SLAVE_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the I2C interrupt number. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! Given a I2C base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns an I2C interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +I2CIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps I2C base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulI2CIntMap) / + sizeof(g_ppulI2CIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulI2CIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulI2CIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + //***************************************************************************** // //! Initializes the I2C Master block. @@ -46,18 +150,17 @@ //! \param ulI2CClk is the rate of the clock supplied to the I2C module. //! \param bFast set up for fast data transfers //! -//! This function initializes operation of the I2C Master block. Upon -//! successful initialization of the I2C block, this function will have set the -//! bus speed for the master, and will have enabled the I2C Master block. +//! This function initializes operation of the I2C Master block by configuring +//! the bus speed for the master and enabling the I2C Master block. //! -//! If the parameter \e bFast is \b true, then the master block will be set up -//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data -//! at 100 kbps. +//! If the parameter \e bFast is \b true, then the master block is set up to +//! transfer data at 400 kbps; otherwise, it is set up to transfer data at +//! 100 kbps. //! -//! The peripheral clock will be the same as the processor clock. This will be -//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded -//! if it is constant and known (to save the code/execution overhead of a call -//! to SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). //! //! This function replaces the original I2CMasterInit() API and performs the //! same actions. A macro is provided in i2c.h to map the original @@ -76,7 +179,7 @@ I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Must enable the device before doing anything else. @@ -112,11 +215,10 @@ I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, //! \param ulBase is the base address of the I2C Slave module. //! \param ucSlaveAddr 7-bit slave address //! -//! This function initializes operation of the I2C Slave block. Upon -//! successful initialization of the I2C blocks, this function will have set -//! the slave address and have enabled the I2C Slave block. +//! This function initializes operation of the I2C Slave block by configuring +//! the slave address and enabling the I2C Slave block. //! -//! The parameter \e ucSlaveAddr is the value that will be compared against the +//! The parameter \e ucSlaveAddr is the value that is compared against the //! slave address sent by an I2C master. //! //! \return None. @@ -128,7 +230,7 @@ I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); ASSERT(!(ucSlaveAddr & 0x80)); // @@ -142,13 +244,67 @@ I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; } +//***************************************************************************** +// +//! Sets the I2C slave address. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ucAddrNum determines which slave address is set. +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function writes the specified slave address. The \e ulAddrNum field +//! dictates which slave address is configured. For example, a value of 0 +//! configures the primary address and a value of 1, the secondary. +//! +//! \note Not all Stellaris devices support a secondary address. Please consult +//! the device data sheet to know if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum, + unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + ASSERT(!(ucAddrNum > 1)); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Determine which slave address is being set. + // + switch(ucAddrNum) + { + // + // Set up the primary slave address. + // + case 0: + { + HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; + break; + } + + // + // Set up and enable the secondary slave address. + // + case 1: + { + HWREG(ulBase + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ucSlaveAddr; + break; + } + } +} + //***************************************************************************** // //! Enables the I2C Master block. //! //! \param ulBase is the base address of the I2C Master module. //! -//! This will enable operation of the I2C Master block. +//! This function enables operation of the I2C Master block. //! //! \return None. // @@ -159,7 +315,7 @@ I2CMasterEnable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Enable the master block. @@ -173,7 +329,7 @@ I2CMasterEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! This will enable operation of the I2C Slave block. +//! This fucntion enables operation of the I2C Slave block. //! //! \return None. // @@ -184,7 +340,7 @@ I2CSlaveEnable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Enable the clock to the slave block. @@ -204,7 +360,7 @@ I2CSlaveEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Master module. //! -//! This will disable operation of the I2C master block. +//! This function disables operation of the I2C master block. //! //! \return None. // @@ -215,7 +371,7 @@ I2CMasterDisable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Disable the master block. @@ -229,7 +385,7 @@ I2CMasterDisable(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! This will disable operation of the I2C slave block. +//! This function disables operation of the I2C slave block. //! //! \return None. // @@ -240,7 +396,7 @@ I2CSlaveDisable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Disable the slave. @@ -262,9 +418,9 @@ I2CSlaveDisable(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! I2C interrupt occurs. //! -//! This sets the handler to be called when an I2C interrupt occurs. This will -//! enable the global interrupt in the interrupt controller; specific I2C -//! interrupts must be enabled via I2CMasterIntEnable() and +//! This function sets the handler to be called when an I2C interrupt occurs. +//! This function enables the global interrupt in the interrupt controller; +//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and //! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's //! responsibility to clear the interrupt source via I2CMasterIntClear() and //! I2CSlaveIntClear(). @@ -283,12 +439,12 @@ I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Determine the interrupt number based on the I2C port. // - ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1; + ulInt = I2CIntNumberGet(ulBase); // // Register the interrupt handler, returning an error if an error occurs. @@ -307,9 +463,9 @@ I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the base address of the I2C Master module. //! -//! This function will clear the handler to be called when an I2C interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. +//! This function clears the handler to be called when an I2C interrupt +//! occurs. This function also masks off the interrupt in the interrupt r +//! controlle so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -325,12 +481,12 @@ I2CIntUnregister(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Determine the interrupt number based on the I2C port. // - ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1; + ulInt = I2CIntNumberGet(ulBase); // // Disable the interrupt. @@ -349,7 +505,7 @@ I2CIntUnregister(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Master module. //! -//! Enables the I2C Master interrupt source. +//! This function enables the I2C Master interrupt source. //! //! \return None. // @@ -360,7 +516,7 @@ I2CMasterIntEnable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Enable the master interrupt. @@ -368,13 +524,50 @@ I2CMasterIntEnable(unsigned long ulBase) HWREG(ulBase + I2C_O_MIMR) = 1; } +//***************************************************************************** +// +//! Enables individual I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Master interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt +//! - \b I2C_MASTER_INT_DATA - Data interrupt +//! +//! \note Not all Stellaris devices support the Clock Timeout interrupt. +//! Please consult the device data sheet to know if this feature is +//! supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) |= ulIntFlags; +} + //***************************************************************************** // //! Enables the I2C Slave interrupt. //! //! \param ulBase is the base address of the I2C Slave module. //! -//! Enables the I2C Slave interrupt source. +//! This function enables the I2C Slave interrupt source. //! //! \return None. // @@ -385,7 +578,7 @@ I2CSlaveIntEnable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Enable the slave interrupt. @@ -400,9 +593,9 @@ I2CSlaveIntEnable(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated I2C Slave interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function enables the indicated I2C Slave interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! @@ -410,6 +603,10 @@ I2CSlaveIntEnable(unsigned long ulBase) //! - \b I2C_SLAVE_INT_START - Start condition detected interrupt //! - \b I2C_SLAVE_INT_DATA - Data interrupt //! +//! \note Not all Stellaris devices support the Stop and Start condition +//! interrupts. Please consult the device data sheet to know if these features +//! are supported. +//! //! \return None. // //***************************************************************************** @@ -419,7 +616,7 @@ I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Enable the slave interrupt. @@ -433,7 +630,7 @@ I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) //! //! \param ulBase is the base address of the I2C Master module. //! -//! Disables the I2C Master interrupt source. +//! This function disables the I2C Master interrupt source. //! //! \return None. // @@ -444,7 +641,7 @@ I2CMasterIntDisable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Disable the master interrupt. @@ -452,13 +649,44 @@ I2CMasterIntDisable(unsigned long ulBase) HWREG(ulBase + I2C_O_MIMR) = 0; } +//***************************************************************************** +// +//! Disables individual I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Master interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CMasterIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) &= ~ulIntFlags; +} + //***************************************************************************** // //! Disables the I2C Slave interrupt. //! //! \param ulBase is the base address of the I2C Slave module. //! -//! Disables the I2C Slave interrupt source. +//! This function disables the I2C Slave interrupt source. //! //! \return None. // @@ -469,7 +697,7 @@ I2CSlaveIntDisable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Disable the slave interrupt. @@ -484,9 +712,9 @@ I2CSlaveIntDisable(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated I2C Slave interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function disables the indicated I2C Slave interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to I2CSlaveIntEnableEx(). @@ -500,7 +728,7 @@ I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Disable the slave interrupt. @@ -516,8 +744,8 @@ I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Master module. Either the -//! raw interrupt status or the status of interrupts that are allowed to +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are allowed to //! reflect to the processor can be returned. //! //! \return The current interrupt status, returned as \b true if active @@ -530,7 +758,7 @@ I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Return either the interrupt status or the raw interrupt status as @@ -546,6 +774,44 @@ I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) } } +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CMasterIntEnableEx(). +// +//***************************************************************************** +unsigned long +I2CMasterIntStatusEx(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + I2C_O_MMIS)); + } + else + { + return(HWREG(ulBase + I2C_O_MRIS)); + } +} + //***************************************************************************** // //! Gets the current I2C Slave interrupt status. @@ -554,9 +820,9 @@ I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Slave module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return The current interrupt status, returned as \b true if active //! or \b false if not active. @@ -568,7 +834,7 @@ I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Return either the interrupt status or the raw interrupt status as @@ -592,9 +858,9 @@ I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Slave module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in I2CSlaveIntEnableEx(). @@ -608,7 +874,7 @@ I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Return either the interrupt status or the raw interrupt status as @@ -643,17 +909,17 @@ I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the base address of the I2C Master module. //! //! The I2C Master interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -664,7 +930,7 @@ I2CMasterIntClear(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Clear the I2C master interrupt source. @@ -679,6 +945,46 @@ I2CMasterIntClear(unsigned long ulBase) HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC; } +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Master interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CMasterIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_O_MICR) = ulIntFlags; +} + //***************************************************************************** // //! Clears I2C Slave interrupt sources. @@ -686,17 +992,17 @@ I2CMasterIntClear(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! //! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -707,7 +1013,7 @@ I2CSlaveIntClear(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Clear the I2C slave interrupt source. @@ -723,20 +1029,20 @@ I2CSlaveIntClear(unsigned long ulBase) //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to I2CSlaveIntEnableEx(). //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -747,7 +1053,7 @@ I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Clear the I2C slave interrupt source. @@ -757,16 +1063,16 @@ I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) //***************************************************************************** // -//! Sets the address that the I2C Master will place on the bus. +//! Sets the address that the I2C Master places on the bus. //! //! \param ulBase is the base address of the I2C Master module. //! \param ucSlaveAddr 7-bit slave address //! \param bReceive flag indicating the type of communication with the slave //! -//! This function will set the address that the I2C Master will place on the +//! This function configures the address that the I2C Master places on the //! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address will indicate that the I2C Master is initiating a -//! read from the slave; otherwise the address will indicate that the I2C +//! to \b true, the address indicates that the I2C Master is initiating a +//! read from the slave; otherwise the address indicates that the I2C //! Master is initiating a write to the slave. //! //! \return None. @@ -779,7 +1085,7 @@ I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); ASSERT(!(ucSlaveAddr & 0x80)); // @@ -788,6 +1094,36 @@ I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive; } +//***************************************************************************** +// +//! Reads the state of the SDA and SCL pins. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function returns the state of the I2C bus by providing the real time +//! values of the SDA and SCL pins. +//! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to know if this feature is supported. +//! +//! \return Returns the state of the bus with SDA in bit position 1 and SCL in +//! bit position 0. +// +//***************************************************************************** +unsigned long +I2CMasterLineStateGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Return the line state. + // + return(HWREG(ulBase + I2C_O_MBMON)); +} + //***************************************************************************** // //! Indicates whether or not the I2C Master is busy. @@ -807,7 +1143,7 @@ I2CMasterBusy(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Return the busy status. @@ -842,7 +1178,7 @@ I2CMasterBusBusy(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Return the bus busy status. @@ -862,7 +1198,7 @@ I2CMasterBusBusy(unsigned long ulBase) //! Controls the state of the I2C Master module. //! //! \param ulBase is the base address of the I2C Master module. -//! \param ulCmd command to be issued to the I2C Master module +//! \param ulCmd command to be issued to the I2C Master module. //! //! This function is used to control the state of the Master module send and //! receive operations. The \e ucCmd parameter can be one of the following @@ -888,7 +1224,7 @@ I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || @@ -928,7 +1264,7 @@ I2CMasterErr(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Get the raw error state @@ -962,9 +1298,9 @@ I2CMasterErr(unsigned long ulBase) //! Transmits a byte from the I2C Master. //! //! \param ulBase is the base address of the I2C Master module. -//! \param ucData data to be transmitted from the I2C Master +//! \param ucData data to be transmitted from the I2C Master. //! -//! This function will place the supplied data into I2C Master Data Register. +//! This function places the supplied data into I2C Master Data Register. //! //! \return None. // @@ -975,7 +1311,7 @@ I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Write the byte. @@ -1001,7 +1337,7 @@ I2CMasterDataGet(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(I2CMasterBaseValid(ulBase)); // // Read a byte. @@ -1009,27 +1345,141 @@ I2CMasterDataGet(unsigned long ulBase) return(HWREG(ulBase + I2C_O_MDR)); } +//***************************************************************************** +// +//! Sets the Master clock timeout value. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulValue is the number of I2C clocks before the timeout is asserted. +//! +//! This function enables and configures the clock low timeout feature in the +//! I2C peripheral. This feature is implemented as a 12-bit counter, with the +//! upper 8-bits being programmable. For example, to program a timeout of 20ms +//! with a 100kHz SCL frequency, \e ulValue would be 0x7d. +//! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to know if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(I2CMasterBaseValid(ulBase)); + + // + // Write the timeout value. + // + HWREG(ulBase + I2C_O_MCLKOCNT) = ulValue; +} + +//***************************************************************************** +// +//! Configures ACK override behavior of the I2C Slave. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bEnable enables or disables ACK override. +//! +//! This function enables or disables ACK override, allowing the user +//! application to drive the value on SDA during the ACK cycle. +//! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to know if this feature is supported. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // Enable or disable based on bEnable. + // + if(bEnable) + { + HWREG(ulBase + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; + } + else + { + HWREG(ulBase + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; + } +} + +//***************************************************************************** +// +//! Writes the ACK value. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. +//! +//! This function puts the desired ACK value on SDA during the ACK cycle. The +//! value written is only valid when ACK override is enabled using +//! I2CSlaveACKOverride(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK) +{ + // + // Check the arguments. + // + ASSERT(I2CSlaveBaseValid(ulBase)); + + // + // ACK or NACK based on the value of bACK. + // + if(bACK) + { + HWREG(ulBase + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; + } + else + { + HWREG(ulBase + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; + } +} + //***************************************************************************** // //! Gets the I2C Slave module status //! //! \param ulBase is the base address of the I2C Slave module. //! -//! This function will return the action requested from a master, if any. +//! This function returns the action requested from a master, if any. //! Possible values are: //! //! - \b I2C_SLAVE_ACT_NONE //! - \b I2C_SLAVE_ACT_RREQ //! - \b I2C_SLAVE_ACT_TREQ //! - \b I2C_SLAVE_ACT_RREQ_FBR +//! - \b I2C_SLAVE_ACT_OWN2SEL +//! - \b I2C_SLAVE_ACT_QCMD +//! - \b I2C_SLAVE_ACT_QCMD_DATA //! //! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been //! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that //! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ //! to indicate that an I2C master has requested that the I2C Slave module send -//! data, and \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent +//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent //! data to the I2C slave and the first byte following the slave's own address -//! has been received. +//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C +//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick +//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the +//! data bit was set when the quick command was received. +//! +//! \note Not all Stellaris devices support the second I2C slave's own address +//! or the quick command function. Please consult the device data sheet to +//! know if these features are supported. // //***************************************************************************** unsigned long @@ -1038,7 +1488,7 @@ I2CSlaveStatus(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Return the slave status. @@ -1053,7 +1503,7 @@ I2CSlaveStatus(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! \param ucData data to be transmitted from the I2C Slave //! -//! This function will place the supplied data into I2C Slave Data Register. +//! This function places the supplied data into I2C Slave Data Register. //! //! \return None. // @@ -1064,7 +1514,7 @@ I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Write the byte. @@ -1090,7 +1540,7 @@ I2CSlaveDataGet(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(I2CSlaveBaseValid(ulBase)); // // Read a byte. diff --git a/bsp/lm3s8962/Libraries/driverlib/i2c.h b/bsp/lm3s8962/Libraries/driverlib/i2c.h index cb93ded54d..e85a9cad40 100644 --- a/bsp/lm3s8962/Libraries/driverlib/i2c.h +++ b/bsp/lm3s8962/Libraries/driverlib/i2c.h @@ -2,7 +2,7 @@ // // i2c.h - Prototypes for the I2C Driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -65,6 +65,8 @@ extern "C" 0x00000001 #define I2C_MASTER_CMD_BURST_SEND_FINISH \ 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 #define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ 0x00000004 #define I2C_MASTER_CMD_BURST_RECEIVE_START \ @@ -75,6 +77,8 @@ extern "C" 0x00000005 #define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 //***************************************************************************** // @@ -95,6 +99,9 @@ extern "C" #define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data #define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data #define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value //***************************************************************************** // @@ -103,6 +110,14 @@ extern "C" //***************************************************************************** #define I2C_MASTER_MAX_RETRIES 1000 // Number of retries +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt. +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt. + //***************************************************************************** // // I2C Slave interrupts. @@ -133,6 +148,18 @@ extern void I2CMasterIntClear(unsigned long ulBase); extern void I2CMasterIntDisable(unsigned long ulBase); extern void I2CMasterIntEnable(unsigned long ulBase); extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterIntEnableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CMasterIntDisableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase, + tBoolean bMasked); +extern void I2CMasterIntClearEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue); +extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable); +extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK); +extern unsigned long I2CMasterLineStateGet(unsigned long ulBase); extern void I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, tBoolean bReceive); @@ -141,6 +168,8 @@ extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); extern void I2CSlaveDisable(unsigned long ulBase); extern void I2CSlaveEnable(unsigned long ulBase); extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum, + unsigned char ucSlaveAddr); extern void I2CSlaveIntClear(unsigned long ulBase); extern void I2CSlaveIntDisable(unsigned long ulBase); extern void I2CSlaveIntEnable(unsigned long ulBase); diff --git a/bsp/lm3s8962/Libraries/driverlib/i2s.c b/bsp/lm3s8962/Libraries/driverlib/i2s.c index 358d1a012e..3cd12ffb64 100644 --- a/bsp/lm3s8962/Libraries/driverlib/i2s.c +++ b/bsp/lm3s8962/Libraries/driverlib/i2s.c @@ -2,7 +2,7 @@ // // i2s.c - Driver for the I2S controller. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -45,7 +45,7 @@ //! //! This function enables the transmit module for operation. The module //! should be enabled after configuration. When the module is disabled, -//! no data or clocks will be generated on the I2S signals. +//! no data or clocks are generated on the I2S signals. //! //! \return None. // @@ -77,7 +77,7 @@ I2STxEnable(unsigned long ulBase) //! //! This function disables the transmit module for operation. The module //! should be disabled before configuration. When the module is disabled, -//! no data or clocks will be generated on the I2S signals. +//! no data or clocks are generated on the I2S signals. //! //! \return None. // @@ -101,18 +101,19 @@ I2STxDisable(unsigned long ulBase) //! Writes data samples to the I2S transmit FIFO with blocking. //! //! \param ulBase is the I2S module base address. -//! \param ulData is the single or dual channel I2S data. +//! \param ulData is the single- or dual-channel I2S data. //! -//! This function writes a single channel sample or combined left-right +//! This function writes a single-channel sample or combined left-right //! samples to the I2S transmit FIFO. The format of the sample is determined //! by the configuration that was used with the function I2STxConfigSet(). -//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter -//! contains either the left or right sample. The left and right sample -//! alternate with each write to the FIFO, left sample first. If the transmit -//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the -//! \e ulData parameter contains both the left and right samples. If the -//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter -//! contains the single channel sample. +//! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData +//! parameter contains either the left or right sample. The left and right +//! sample alternate with each write to the FIFO, left sample first. If the +//! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or +//! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both +//! the left and right samples. If the transmit mode is +//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single +//! channel sample. //! //! For the compact modes, both the left and right samples are written at //! the same time. If 16-bit compact mode is used, then the least significant @@ -121,7 +122,7 @@ I2STxDisable(unsigned long ulBase) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no room in the transmit FIFO, then this function will wait +//! If there is no room in the transmit FIFO, then this function waits //! in a polling loop until the data can be written. //! //! \return None. @@ -153,18 +154,19 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData) //! Writes data samples to the I2S transmit FIFO without blocking. //! //! \param ulBase is the I2S module base address. -//! \param ulData is the single or dual channel I2S data. +//! \param ulData is the single- or dual-channel I2S data. //! -//! This function writes a single channel sample or combined left-right +//! This function writes a single-channel sample or combined left-right //! samples to the I2S transmit FIFO. The format of the sample is determined //! by the configuration that was used with the function I2STxConfigSet(). -//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter -//! contains either the left or right sample. The left and right sample -//! alternate with each write to the FIFO, left sample first. If the transmit -//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the -//! \e ulData parameter contains both the left and right samples. If the -//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter -//! contains the single channel sample. +//! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData +//! parameter contains either the left or right sample. The left and right +//! sample alternate with each write to the FIFO, left sample first. If the +//! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or +//! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both +//! the left and right samples. If the transmit mode is +//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single- +//! channel sample. //! //! For the compact modes, both the left and right samples are written at //! the same time. If 16-bit compact mode is used, then the least significant @@ -173,7 +175,7 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no room in the transmit FIFO, then this function will return +//! If there is no room in the transmit FIFO, then this function returns //! immediately without writing any data to the FIFO. //! //! \return The number of elements written to the I2S transmit FIFO (1 or 0). @@ -213,23 +215,23 @@ I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) //! options: //! //! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, -//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or -//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. //! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. //! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, -//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, -//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or -//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. //! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether -//! the I2S transmitter is the clock master or slave. +//! the I2S transmitter is the clock master or slave. //! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 -//! to select the number of bits per sample. +//! to select the number of bits per sample. //! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 -//! to select the number of bits per word that are transferred on the data -//! line. +//! to select the number of bits per word that are transferred on the data +//! line. //! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether -//! the module transmits zeroes or repeats the last sample when the FIFO is -//! empty. +//! the module transmits zeroes or repeats the last sample when the FIFO is +//! empty. //! //! \return None. // @@ -254,7 +256,7 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) // // If compact 8 mode is used, then need to adjust some bits // before writing the config register. Also set the FIFO - // config register for 8 bit compact samples. + // config register for 8-bit compact samples. // ulConfig &= ~I2S_CONFIG_MODE_MONO; HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; @@ -263,14 +265,14 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) { // // If compact 8 mode is not used, then set the FIFO config - // register for 16 bit. This is okay if a compact mode is - // not used. + // register for 16 bit. This setting is okay if a compact + // mode is not used. // HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; } // - // Write the configuration register. Since all the fields are + // Write the configuration register. Because all the fields are // specified by the configuration parameter, it is not necessary // to do a read-modify-write. // @@ -284,22 +286,21 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! \param ulBase is the I2S module base address. //! \param ulLevel is the FIFO service request limit. //! -//! This function is used to set the transmit FIFO fullness level at which -//! a service request will occur. The service request is used to generate -//! an interrupt or a DMA transfer request. The transmit FIFO will -//! generate a service request when the number of items in the FIFO is -//! less than the level specified in the \e ulLevel parameter. For example, -//! if \e ulLevel is 8, then a service request will be generated when -//! there are less than 8 samples remaining in the transmit FIFO. +//! This function is used to set the transmit FIFO fullness level at which a +//! service request occurs. The service request is used to generate an +//! interrupt or a DMA transfer request. The transmit FIFO generates a +//! service request when the number of items in the FIFO is less than the level +//! specified in the \e ulLevel parameter. For example, if \e ulLevel is 8, +//! then a service request is generated when there are less than 8 samples +//! remaining in the transmit FIFO. //! //! For the purposes of counting the FIFO level, a left-right sample pair -//! counts as 2, whether the mode is dual or compact stereo. When mono -//! mode is used, internally the mono sample is still treated as a sample -//! pair, so a single mono sample counts as 2. Since the FIFO always deals -//! with sample pairs, the level must be an even number from 0 to 16. The -//! maximum value is 16, which will cause a service request when there -//! is any room in the FIFO. The minimum value is 0, which disables the -//! service request. +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, the level must be an even number from 0 to 16. The maximum value is +//! 16, which causes a service request when there is any room in the FIFO. +//! The minimum value is 0, which disables the service request. //! //! \return None. // @@ -352,19 +353,18 @@ I2STxFIFOLimitGet(unsigned long ulBase) //! //! \param ulBase is the I2S module base address. //! -//! This function is used to get the number of samples in the transmit -//! FIFO. For the purposes of measuring the FIFO level, a left-right sample -//! pair counts as 2, whether the mode is dual or compact stereo. When mono -//! mode is used, internally the mono sample is still treated as a sample -//! pair, so a single mono sample counts as 2. Since the FIFO always deals -//! with sample pairs, normally the level will be an even number from 0 to -//! 16. If dual stereo mode is used and only the left sample has been -//! written without the matching right sample, then the FIFO level will be an -//! odd value. If the FIFO level is odd, it indicates a left-right sample -//! mismatch. +//! This function is used to get the number of samples in the transmit FIFO. +//! For the purposes of measuring the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, normally the level is an even number from 0 to 16. If dual stereo +//! mode is used and only the left sample has been written without the matching +//! right sample, then the FIFO level is an odd value. If the FIFO level is +//! odd, it indicates a left-right sample mismatch. //! -//! \return Returns the number of samples in the transmit FIFO, which will -//! normally be an even number. +//! \return Returns the number of samples in the transmit FIFO, which is +//! normally an even number. // //***************************************************************************** unsigned long @@ -387,9 +387,9 @@ I2STxFIFOLevelGet(unsigned long ulBase) //! //! \param ulBase is the I2S module base address. //! -//! This function enables the receive module for operation. The module -//! should be enabled after configuration. When the module is disabled, -//! no data will be clocked in regardless of the signals on the I2S interface. +//! This function enables the receive module for operation. The module should +//! be enabled after configuration. When the module is disabled, no data is +//! clocked in regardless of the signals on the I2S interface. //! //! \return None. // @@ -419,9 +419,9 @@ I2SRxEnable(unsigned long ulBase) //! //! \param ulBase is the I2S module base address. //! -//! This function disables the receive module for operation. The module -//! should be disabled before configuration. When the module is disabled, -//! no data will be clocked in regardless of the signals on the I2S interface. +//! This function disables the receive module for operation. The module should +//! be disabled before configuration. When the module is disabled, no data is +//! clocked in regardless of the signals on the I2S interface. //! //! \return None. // @@ -450,12 +450,12 @@ I2SRxDisable(unsigned long ulBase) //! This function reads a single channel sample or combined left-right //! samples from the I2S receive FIFO. The format of the sample is determined //! by the configuration that was used with the function I2SRxConfigSet(). -//! If the receive mode is I2S_MODE_DUAL_STEREO then the returned value +//! If the receive mode is \b I2S_MODE_DUAL_STEREO then the returned value //! contains either the left or right sample. The left and right sample //! alternate with each read from the FIFO, left sample first. If the receive -//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the -//! returned data contains both the left and right samples. If the -//! receive mode is I2S_MODE_SINGLE_MONO then the returned data +//! mode is \b I2S_MODE_COMPACT_STEREO_16 or \b I2S_MODE_COMPACT_STEREO_8, then +//! the returned data contains both the left and right samples. If the +//! receive mode is \b I2S_MODE_SINGLE_MONO then the returned data //! contains the single channel sample. //! //! For the compact modes, both the left and right samples are read at @@ -465,7 +465,7 @@ I2SRxDisable(unsigned long ulBase) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no data in the receive FIFO, then this function will wait +//! If there is no data in the receive FIFO, then this function waits //! in a polling loop until data is available. //! //! \return None. @@ -502,12 +502,12 @@ I2SRxDataGet(unsigned long ulBase, unsigned long *pulData) //! This function reads a single channel sample or combined left-right //! samples from the I2S receive FIFO. The format of the sample is determined //! by the configuration that was used with the function I2SRxConfigSet(). -//! If the receive mode is I2S_MODE_DUAL_STEREO then the received data +//! If the receive mode is \b I2S_MODE_DUAL_STEREO then the received data //! contains either the left or right sample. The left and right sample //! alternate with each read from the FIFO, left sample first. If the receive -//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the -//! received data contains both the left and right samples. If the -//! receive mode is I2S_MODE_SINGLE_MONO then the received data +//! mode is \b I2S_MODE_COMPACT_STEREO_16 or \b I2S_MODE_COMPACT_STEREO_8, then +//! the received data contains both the left and right samples. If the +//! receive mode is \b I2S_MODE_SINGLE_MONO then the received data //! contains the single channel sample. //! //! For the compact modes, both the left and right samples are read at @@ -517,7 +517,7 @@ I2SRxDataGet(unsigned long ulBase, unsigned long *pulData) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no data in the receive FIFO, then this function will return +//! If there is no data in the receive FIFO, then this function returns //! immediately without reading any data from the FIFO. //! //! \return The number of elements read from the I2S receive FIFO (1 or 0). @@ -557,20 +557,20 @@ I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) //! options: //! //! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, -//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or -//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. //! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. //! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, -//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, -//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or -//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. //! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether -//! the I2S receiver is the clock master or slave. +//! the I2S receiver is the clock master or slave. //! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 -//! to select the number of bits per sample. +//! to select the number of bits per sample. //! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 -//! to select the number of bits per word that are transferred on the data -//! line. +//! to select the number of bits per word that are transferred on the data +//! line. //! //! \return None. // @@ -608,14 +608,14 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) } // - // The "mono" bits needs to be removed from the configuration word + // The "mono" bits must be removed from the configuration word // prior to writing to hardware, because the RX configuration register // does not actually use these bits. // ulConfig &= ~I2S_CONFIG_MODE_MONO; // - // Write the configuration register. Since all the fields are + // Write the configuration register. Because all the fields are // specified by the configuration parameter, it is not necessary // to do a read-modify-write. // @@ -629,23 +629,22 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! \param ulBase is the I2S module base address. //! \param ulLevel is the FIFO service request limit. //! -//! This function is used to set the receive FIFO fullness level at which -//! a service request will occur. The service request is used to generate -//! an interrupt or a DMA transfer request. The receive FIFO will -//! generate a service request when the number of items in the FIFO is -//! greater than the level specified in the \e ulLevel parameter. For example, -//! if \e ulLevel is 4, then a service request will be generated when -//! there are more than 4 samples available in the receive FIFO. +//! This function is used to set the receive FIFO fullness level at which a +//! service request occurs. The service request is used to generate an +//! interrupt or a DMA transfer request. The receive FIFO generates a +//! service request when the number of items in the FIFO is greater than the +//! level specified in the \e ulLevel parameter. For example, if \e ulLevel is +//! 4, then a service request is generated when there are more than 4 samples +//! available in the receive FIFO. //! //! For the purposes of counting the FIFO level, a left-right sample pair -//! counts as 2, whether the mode is dual or compact stereo. When mono -//! mode is used, internally the mono sample is still treated as a sample -//! pair, so a single mono sample counts as 2. Since the FIFO always deals -//! with sample pairs, the level must be an even number from 0 to 16. The -//! minimum value is 0, which will cause a service request when there -//! is any data available in the FIFO. The maximum value is 16, which -//! disables the service request (because there cannot be more than 16 -//! items in the FIFO). +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, the level must be an even number from 0 to 16. The minimum value is +//! 0, which causes a service request when there is any data available in +//! the FIFO. The maximum value is 16, which disables the service request +//! (because there cannot be more than 16 items in the FIFO). //! //! \return None. // @@ -688,7 +687,7 @@ I2SRxFIFOLimitGet(unsigned long ulBase) // // Read and return the FIFO limit. The lower bit is masked - // because it always reads as 1, and has no meaning. + // because it always reads as 1 and has no meaning. // return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); } @@ -699,19 +698,18 @@ I2SRxFIFOLimitGet(unsigned long ulBase) //! //! \param ulBase is the I2S module base address. //! -//! This function is used to get the number of samples in the receive -//! FIFO. For the purposes of measuring the FIFO level, a left-right sample -//! pair counts as 2, whether the mode is dual or compact stereo. When mono -//! mode is used, internally the mono sample is still treated as a sample -//! pair, so a single mono sample counts as 2. Since the FIFO always deals -//! with sample pairs, normally the level will be an even number from 0 to -//! 16. If dual stereo mode is used and only the left sample has been -//! read without reading the matching right sample, then the FIFO level will -//! be an odd value. If the FIFO level is odd, it indicates a left-right -//! sample mismatch. +//! This function is used to get the number of samples in the receive FIFO. +//! For the purposes of measuring the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono mode is +//! used, internally the mono sample is still treated as a sample pair, so a +//! single mono sample counts as 2. Because the FIFO always deals with sample +//! pairs, normally the level is an even number from 0 to 16. If dual stereo +//! mode is used and only the left sample has been read without reading the +//! matching right sample, then the FIFO level is an odd value. If the FIFO +//! level is odd, it indicates a left-right sample mismatch. //! -//! \return Returns the number of samples in the transmit FIFO, which will -//! normally be an even number. +//! \return Returns the number of samples in the transmit FIFO, which is +//! normally an even number. // //***************************************************************************** unsigned long @@ -737,7 +735,7 @@ I2SRxFIFOLevelGet(unsigned long ulBase) //! This function simultaneously enables the transmit and receive modules for //! operation, providing a synchronized SCLK and LRCLK. The module should be //! enabled after configuration. When the module is disabled, no data or -//! clocks will be generated on the I2S signals. +//! clocks are generated on the I2S signals. //! //! \return None. // @@ -773,7 +771,7 @@ I2STxRxEnable(unsigned long ulBase) //! \param ulBase is the I2S module base address. //! //! This function simultaneously disables the transmit and receive modules. -//! When the module is disabled, no data or clocks will be generated on the I2S +//! When the module is disabled, no data or clocks are generated on the I2S //! signals. //! //! \return None. @@ -805,23 +803,23 @@ I2STxRxDisable(unsigned long ulBase) //! the logical OR of the following options: //! //! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, -//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or -//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. //! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. -//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, -//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, -//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or -//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! - \b I2S_CONFIG_MODE_DUAL for dual-channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single-channel mono format. //! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether -//! the I2S transmitter is the clock master or slave. +//! the I2S transmitter is the clock master or slave. //! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 -//! to select the number of bits per sample. +//! to select the number of bits per sample. //! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 -//! to select the number of bits per word that are transferred on the data -//! line. +//! to select the number of bits per word that are transferred on the data +//! line. //! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether -//! the module transmits zeroes or repeats the last sample when the FIFO is -//! empty. +//! the module transmits zeroes or repeats the last sample when the FIFO is +//! empty. //! //! \return None. // @@ -863,8 +861,8 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) } // - // Write the configuration register. Since all the fields are specified by - // the configuration parameter, it is not necessary to do a + // Write the configuration register. Because all the fields are specified + // by the configuration parameter, it is not necessary to do a // read-modify-write. // HWREG(ulBase + I2S_O_TXCFG) = ulConfig; @@ -880,7 +878,7 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! choices. //! //! This function selects whether the master clock is sourced from the device -//! internal PLL, or comes from an external pin. The I2S serial bit clock +//! internal PLL or comes from an external pin. The I2S serial bit clock //! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master //! clock. The transmit and receive modules can be configured independently. //! The \e ulMClock parameter is chosen from the following: @@ -888,7 +886,7 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT //! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT //! -//! \return Returns None. +//! \return None. // //***************************************************************************** void @@ -926,7 +924,7 @@ I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock) //! - \b I2S_INT_TXERR for transmit errors //! - \b I2S_INT_TXREQ for transmit FIFO service requests //! -//! \return Returns None. +//! \return None. // //***************************************************************************** void @@ -957,7 +955,7 @@ I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ, //! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. //! -//! \return Returns None. +//! \return None. // //***************************************************************************** void @@ -1021,22 +1019,22 @@ I2SIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the I2S module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! This function clears the specified pending I2S interrupts. This must -//! be done in the interrupt handler to keep the handler from being called -//! again immediately upon exit. The \e ulIntFlags parameter can be the -//! logical OR of any of the following values: \b I2S_INT_RXERR, +//! This function clears the specified pending I2S interrupts. This function +//! must be called in the interrupt handler to keep the interrupt from being +//! triggered again immediately upon exit. The \e ulIntFlags parameter can be +//! the logical OR of any of the following values: \b I2S_INT_RXERR, //! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! -//! \return Returns None. +//! \return None. // //***************************************************************************** void @@ -1063,9 +1061,9 @@ I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags) //! \param pfnHandler is a pointer to the function to be called when the //! interrupt is activated. //! -//! This sets and enables the handler to be called when the I2S controller -//! generates an interrupt. Specific I2S interrupts must still be enabled -//! with the I2SIntEnable() function. It is the responsibility of the +//! This function sets and enables the handler to be called when the I2S +//! controller generates an interrupt. Specific I2S interrupts must still be +//! enabled with the I2SIntEnable() function. It is the responsibility of the //! interrupt handler to clear any pending interrupts with I2SIntClear(). //! //! \sa IntRegister() for important information about registering interrupt @@ -1100,7 +1098,7 @@ I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the I2S module base address. //! -//! This function will disable and clear the handler to be called when the +//! This function disables and clears the handler to be called when the //! I2S interrupt occurs. //! //! \sa IntRegister() for important information about registering interrupt diff --git a/bsp/lm3s8962/Libraries/driverlib/i2s.h b/bsp/lm3s8962/Libraries/driverlib/i2s.h index b86075a736..f7abacf8c6 100644 --- a/bsp/lm3s8962/Libraries/driverlib/i2s.h +++ b/bsp/lm3s8962/Libraries/driverlib/i2s.h @@ -2,7 +2,7 @@ // // i2s.h - Prototypes and macros for the I2S controller. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/interrupt.c b/bsp/lm3s8962/Libraries/driverlib/interrupt.c index 8bed6e81f4..7eed9758b0 100644 --- a/bsp/lm3s8962/Libraries/driverlib/interrupt.c +++ b/bsp/lm3s8962/Libraries/driverlib/interrupt.c @@ -2,7 +2,7 @@ // // interrupt.c - Driver for the NVIC Interrupt Controller. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -59,7 +59,58 @@ static const unsigned long g_pulRegs[] = { 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, + NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, + NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, + NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, + NVIC_PRI32 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulEnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt disable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulDisRegs[] = +{ + NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt pend for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulPendRegs[] = +{ + NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt unpend for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulUnpendRegs[] = +{ + NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4 }; //***************************************************************************** @@ -97,30 +148,32 @@ IntDefaultHandler(void) // //***************************************************************************** #if defined(ewarm) +#pragma data_alignment=1024 static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; #elif defined(sourcerygxx) static __attribute__((section(".cs3.region-head.ram"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#elif defined(ccs) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); +#elif defined(ccs) || defined(DOXYGEN) +#pragma DATA_ALIGN(g_pfnRAMVectors, 1024) #pragma DATA_SECTION(g_pfnRAMVectors, ".vtable") void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); #else static __attribute__((section("vtable"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); #endif //***************************************************************************** // //! Enables the processor interrupt. //! -//! Allows the processor to respond to interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. +//! This function allows the processor to respond to interrupts. This function +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the single interrupt from the controller to the processor. //! //! \note Previously, this function had no return value. As such, it was //! possible to include interrupt.h and call this function without //! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution +//! tBoolean, a compiler error occurs in this case. The solution //! is to include hw_types.h before including interrupt.h. //! //! \return Returns \b true if interrupts were disabled when the function was @@ -140,14 +193,15 @@ IntMasterEnable(void) // //! Disables the processor interrupt. //! -//! Prevents the processor from receiving interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. +//! This function prevents the processor from receiving interrupts. This +//! function does not affect the set of interrupts enabled in the interrupt +//! controller; it just gates the single interrupt from the controller to the +//! processor. //! //! \note Previously, this function had no return value. As such, it was //! possible to include interrupt.h and call this function without //! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution +//! tBoolean, a compiler error occurs in this case. The solution //! is to include hw_types.h before including interrupt.h. //! //! \return Returns \b true if interrupts were already disabled when the @@ -172,22 +226,20 @@ IntMasterDisable(void) //! //! This function is used to specify the handler function to be called when the //! given interrupt is asserted to the processor. When the interrupt occurs, -//! if it is enabled (via IntEnable()), the handler function will be called in -//! interrupt context. Since the handler function can preempt other code, care -//! must be taken to protect memory or peripherals that are accessed by the -//! handler and other non-handler code. +//! if it is enabled (via IntEnable()), the handler function is called in +//! interrupt context. Because the handler function can preempt other code, +//! care must be taken to protect memory or peripherals that are accessed by +//! the handler and other non-handler code. //! //! \note The use of this function (directly or indirectly via a peripheral //! driver interrupt register function) moves the interrupt vector table from //! flash to SRAM. Therefore, care must be taken when linking the application //! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise NVIC will not look in the correct portion of memory for the +//! otherwise the NVIC does not look in the correct portion of memory for the //! vector table (it requires the vector table be on a 1 kB memory alignment). -//! Normally, the SRAM vector table is so placed via the use of linker scripts; -//! some tool chains, such as the evaluation version of RV-MDK, do not support -//! linker scripts and therefore will not produce a valid executable. See the -//! discussion of compile-time versus run-time interrupt handler registration -//! in the introduction to this chapter. +//! Normally, the SRAM vector table is so placed via the use of linker scripts. +//! See the discussion of compile-time versus run-time interrupt handler +//! registration in the introduction to this chapter. //! //! \return None. // @@ -224,7 +276,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) } // - // Point NVIC at the RAM vector table. + // Point the NVIC at the RAM vector table. // HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; } @@ -242,7 +294,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) //! \param ulInterrupt specifies the interrupt in question. //! //! This function is used to indicate that no handler should be called when the -//! given interrupt is asserted to the processor. The interrupt source will be +//! given interrupt is asserted to the processor. The interrupt source is //! automatically disabled (via IntDisable()) if necessary. //! //! \sa IntRegister() for important information about registering interrupt @@ -348,7 +400,7 @@ IntPriorityGroupingGet(void) //! correspond to higher interrupt priorities; priority 0 is the highest //! interrupt priority. //! -//! The hardware priority mechanism will only look at the upper N bits of the +//! The hardware priority mechanism only looks at the upper N bits of the //! priority level (where N is 3 for the Stellaris family), so any //! prioritization must be performed in those bits. The remaining bits can be //! used to sub-prioritize the interrupt sources, and may be used by the @@ -458,19 +510,13 @@ IntEnable(unsigned long ulInterrupt) // HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; } - else if((ulInterrupt >= 16) && (ulInterrupt <= 47)) + else if(ulInterrupt >= 16) { // // Enable the general interrupt. // - HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16); - } - else if(ulInterrupt >= 48) - { - // - // Enable the general interrupt. - // - HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48); + HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); } } @@ -526,19 +572,13 @@ IntDisable(unsigned long ulInterrupt) // HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); } - else if((ulInterrupt >= 16) && (ulInterrupt <= 47)) + else if(ulInterrupt >= 16) { // // Disable the general interrupt. // - HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16); - } - else if(ulInterrupt >= 48) - { - // - // Disable the general interrupt. - // - HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48); + HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); } } @@ -548,13 +588,13 @@ IntDisable(unsigned long ulInterrupt) //! //! \param ulInterrupt specifies the interrupt to be pended. //! -//! The specified interrupt is pended in the interrupt controller. This will -//! cause the interrupt controller to execute the corresponding interrupt -//! handler at the next available time, based on the current interrupt state -//! priorities. For example, if called by a higher priority interrupt handler, -//! the specified interrupt handler will not be called until after the current -//! interrupt handler has completed execution. The interrupt must have been -//! enabled for it to be called. +//! The specified interrupt is pended in the interrupt controller. Pending an +//! interrupt causes the interrupt controller to execute the corresponding +//! interrupt handler at the next available time, based on the current +//! interrupt state priorities. For example, if called by a higher priority +//! interrupt handler, the specified interrupt handler is not called until +//! after the current interrupt handler has completed execution. The interrupt +//! must have been enabled for it to be called. //! //! \return None. // @@ -591,19 +631,13 @@ IntPendSet(unsigned long ulInterrupt) // HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; } - else if((ulInterrupt >= 16) && (ulInterrupt <= 47)) + else if(ulInterrupt >= 16) { // // Pend the general interrupt. // - HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16); - } - else if(ulInterrupt >= 48) - { - // - // Pend the general interrupt. - // - HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48); + HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); } } @@ -613,10 +647,10 @@ IntPendSet(unsigned long ulInterrupt) //! //! \param ulInterrupt specifies the interrupt to be unpended. //! -//! The specified interrupt is unpended in the interrupt controller. This will -//! cause any previously generated interrupts that have not been handled yet -//! (due to higher priority interrupts or the interrupt no having been enabled -//! yet) to be discarded. +//! The specified interrupt is unpended in the interrupt controller. Unpending +//! an interrupt causes any previously generated interrupts that have not been +//! handled yet (due to higher priority interrupts or the interrupt not having +//! been enabled yet) to be discarded. //! //! \return None. // @@ -646,19 +680,13 @@ IntPendClear(unsigned long ulInterrupt) // HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; } - else if((ulInterrupt >= 16) && (ulInterrupt <= 47)) + else if(ulInterrupt >= 16) { // // Unpend the general interrupt. // - HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16); - } - else if(ulInterrupt >= 48) - { - // - // Unpend the general interrupt. - // - HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48); + HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); } } @@ -666,19 +694,19 @@ IntPendClear(unsigned long ulInterrupt) // //! Sets the priority masking level //! -//! \param ulPriorityMask is the priority level that will be masked. +//! \param ulPriorityMask is the priority level that is masked. //! //! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level is masked. This -//! can be used to globally disable a set of interrupts with priority below -//! a predetermined threshold. A value of 0 disables priority +//! interrupts at the specified or lesser priority level are masked. Masking +//! interrupts can be used to globally disable a set of interrupts with +//! priority below a predetermined threshold. A value of 0 disables priority //! masking. //! //! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. //! -//! The hardware priority mechanism will only look at the upper N bits of the +//! The hardware priority mechanism only looks at the upper N bits of the //! priority level (where N is 3 for the Stellaris family), so any //! prioritization must be performed in those bits. //! @@ -701,10 +729,10 @@ IntPriorityMaskSet(unsigned long ulPriorityMask) //! masking is disabled. //! //! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. //! -//! The hardware priority mechanism will only look at the upper N bits of the +//! The hardware priority mechanism only looks at the upper N bits of the //! priority level (where N is 3 for the Stellaris family), so any //! prioritization must be performed in those bits. //! diff --git a/bsp/lm3s8962/Libraries/driverlib/interrupt.h b/bsp/lm3s8962/Libraries/driverlib/interrupt.h index c13f09b30a..5ab98d6431 100644 --- a/bsp/lm3s8962/Libraries/driverlib/interrupt.h +++ b/bsp/lm3s8962/Libraries/driverlib/interrupt.h @@ -2,7 +2,7 @@ // // interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/lpc.c b/bsp/lm3s8962/Libraries/driverlib/lpc.c new file mode 100644 index 0000000000..0e8cab7821 --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/lpc.c @@ -0,0 +1,1533 @@ +//***************************************************************************** +// +// lpc.c - Driver for the Low Pin Count (LPC) module. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup lpc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_lpc.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/lpc.h" + +//***************************************************************************** +// +//! \internal +//! Checks an LPC Channel. +//! +//! \param ulChannel is the LPC channel identifier. +//! +//! This function determines if a channel identifier is valid. This function +//! does not check for Channel 7 (COMx). +//! +//! \return Returns \b true if the channel identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +LPCChannelValid(unsigned long ulChannel) +{ + return((ulChannel == LPC_CHAN_CH0) || + (ulChannel == LPC_CHAN_CH1) || + (ulChannel == LPC_CHAN_CH2) || + (ulChannel == LPC_CHAN_CH3) || + (ulChannel == LPC_CHAN_CH4) || + (ulChannel == LPC_CHAN_CH5) || + (ulChannel == LPC_CHAN_CH6) || + (ulChannel == LPC_CHAN_CH7)); +} +#endif // #ifdef DEBUG + +//***************************************************************************** +// +//! Sets the configuration of the LPC module. +//! +//! \param ulBase is the base address of the LPC module. +//! \param ulConfig specifies the configuration of the LPC module. +//! +//! This function configures the LPC module for basic operation. The +//! configuration of individual channels is handled in a separate function. +//! +//! The \e ulConfig parameter is the logical OR of the following values: +//! - \b LPC_CFG_WAKE - Force assertion of the LPC0CLKRUN signal when the +//! LPC bus is powered down (LPC0PD is asserted). +//! +//! \return None. +// +//***************************************************************************** +void +LPCConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulConfig & ~(LPC_CFG_WAKE)) == 0); + + // + // Configure the appropriate LPC Control Register fields. + // + ulTemp = HWREG(ulBase + LPC_O_CTL); + ulTemp &= ~LPC_CTL_WAKE; + ulTemp |= (ulConfig & LPC_CTL_WAKE); + HWREG(ulBase + LPC_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the current configuration of the LPC module. +//! +//! \param ulBase is the base address of the LPC module. +//! +//! This function queries the control register of the LPC module and returns +//! a bit-mapped value. +//! +//! \sa The description of the LPCConfigSet() function provides detailed +//! information for the bit-mapped configuration values that are returned. +//! +//! \return Returns the bit-mapped LPC module configration value. +// +//***************************************************************************** +unsigned long +LPCConfigGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return the configuration value + // + return((HWREG(ulBase + LPC_O_CTL) & LPC_CTL_WAKE)); +} + +//***************************************************************************** +// +//! Sets the Status Block Address for the LPC peripheral. +//! +//! \param ulBase is the base address of the LPC module. +//! \param ulAddress is the host address to use for the block status. +//! \param bEnabled indicates whether the block address feature should +//! be enabled. +//! +//! This function sets the LPC block address register and optionally enables +//! it. +//! +//! \return None. +// +//***************************************************************************** +void +LPCStatusBlockAddressSet(unsigned long ulBase, unsigned long ulAddress, + tBoolean bEnabled) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulAddress & ~0xFFFFFFFE) == 0); + + // + // Set (and optionally enable) the Status Block Address + // + HWREG(ulBase + LPC_O_STSADDR) = (ulAddress | (bEnabled ? 1 : 0)); +} + +//***************************************************************************** +// +//! Gets the Status Block Address for the LPC peripheral. +//! +//! \param ulBase is the base address of the LPC module. +//! +//! This function returns the LPC block address register. The LSB is used +//! to indicate whether this feature has been enabled or not. +//! +//! \return None. +// +//***************************************************************************** +unsigned +LPCStatusBlockAddressGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return the Status Block Address, including the enable bit. + // + return(HWREG(ulBase + LPC_O_STSADDR)); +} + +//***************************************************************************** +// +//! Returns the status of the LPC module. +//! +//! \param ulBase is the base address of the LPC module. +//! \param pulCount is a pointer to storage for the channel count. +//! \param pulPoolSize is a pointer to storage for the register pool size. +//! +//! This function reads the value of the LPC Status register, calculates the +//! number of channels and buffer pool size, and then returns the raw status +//! value. +//! +//! \return Returns the contents of the LPC Status register. +// +//***************************************************************************** +unsigned long +LPCStatusGet(unsigned long ulBase, unsigned long *pulCount, + unsigned long *pulPoolSize) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get a snapshot of the status register. + // + ulStatus = HWREG(ulBase + LPC_O_STS); + + // + // Extract the channel count from the status, including COMx channel. + // + if(pulCount) + { + *pulCount = (((ulStatus & LPC_STS_CHCNT_M) >> LPC_STS_CHCNT_S) + 1); + } + + // + // Extract/Calculate the register pool size. + // + if(pulPoolSize) + { + *pulPoolSize = (((ulStatus & LPC_STS_POOLSZ_M) >> 16) * 256); + } + + // + // Return the raw status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Generates a pulse on the SCIn signal. +//! +//! \param ulBase is the base address of the LPC module. +//! \param ulCount is the number used to generate the pulse width value. +//! +//! This function generates a pulse on the SCIn interrupt pin. The width of +//! the pulse is (2 << \e ulCount) LPC Clock Periods, where \e ulCount can take +//! on the value of 0, 1, 2, or 3. So, the pulse width is 2, 4, 8, or 16 clock +//! periods. +//! +//! \return None. +// +//***************************************************************************** +void +LPCSCIAssert(unsigned long ulBase, unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(ulCount <= 3); + + // + // Wait for any previous pulse to be completed, by checking the SCI bit + // (which is a self-clearing bit that is used to generate the pulse). + // + while(HWREG(ulBase + LPC_O_CTL) & LPC_CTL_SCI) + { + } + + // + // Set the count value first, prior to enabling the pulse. + // + HWREG(ulBase + LPC_O_CTL) &= ~LPC_CTL_SCICNT_M; + HWREG(ulBase + LPC_O_CTL) |= (ulCount << 10); + + // + // Now, generate the pulse by setting the SCI bit. + // + HWREG(ulBase + LPC_O_CTL) |= LPC_CTL_SCI; +} + +//***************************************************************************** +// +//! Configure the LPC IRQ operation. +//! +//! \param ulBase is the base address of the LPC module. +//! \param bIRQPulse is a flag to indicate the manual IRQ bits should be +//! cleared after they have been sent (in an SIRQ frame). +//! \param bIRQOnChange is a flag to indicate that an SIRQ frame should be +//! sent whenever any IRQ bits (manual/auto) change status. +//! +//! This function configures the LPC IRQs. If the \e bIRQPulse parameter is +//! \b true, then manual IRQ values are cleared after they are sent. If the +//! \e bIRQOnChange parameter is true, then IRQ values (manual and/or +//! automatic) are sent when a change is detected. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse, tBoolean bIRQOnChange) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Setup IRQ pulse configuration. + // + if(bIRQPulse) + { + HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_PULSE; + } + else + { + HWREG(ulBase + LPC_O_IRQCTL) &= ~LPC_IRQCTL_PULSE; + } + + // + // Setup IRQ on-change configuration. + // + if(bIRQOnChange) + { + HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_ONCHG; + } + else + { + HWREG(ulBase + LPC_O_IRQCTL) &= ~LPC_IRQCTL_ONCHG; + } +} + +//***************************************************************************** +// +//! Set the manual LPC IRQ bits. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIRQ specifies the IRQ bits that should be set. +//! +//! This function sets the IRQ bits that are sent in the SERIRQ frame. The +//! value in the \e ulIRQ register is OR-ed into the existing manual IRQ +//! setting. The value for the \e ulIRQ parameter can be any combination of +//! the following values: \b LPC_IRQ15, \b LPC_IRQ14, \b LPC_IRQ13, +//! \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, \b LPC_IRQ8, +//! \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, \b LPC_IRQ3, +//! \b LPC_IRQ2, \b LPC_IRQ1, or \b LPC_IRQ0. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current IRQ configuration, mask off the bits that we are to + // be operating on, set/clear them as appropriate, then rewrite the + // register. + // + ulTemp = HWREG(ulBase + LPC_O_IRQCTL); + ulTemp |= (ulIRQ & 0xFFFF0000); + HWREG(ulBase + LPC_O_IRQCTL) = ulTemp; +} + +//***************************************************************************** +// +//! Clear the manual LPC IRQ bits. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIRQ specifies the IRQ bits that should be cleared. +//! +//! This function clears the IRQ bits that are sent in the SERIRQ frame. The +//! value in the \e ulIRQ register is OR-ed into the existing manual IRQ +//! setting. The value for the \e ulIRQ parameter can be any combination of +//! the following values: \b LPC_IRQ15, \b LPC_IRQ14, \b LPC_IRQ13, +//! \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, \b LPC_IRQ8, +//! \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, \b LPC_IRQ3, +//! \b LPC_IRQ2, \b LPC_IRQ1, or \b LPC_IRQ0. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current IRQ configuration, mask off the bits that we are to + // be operating on, set/clear them as appropriate, then rewrite the + // register. + // + ulTemp = HWREG(ulBase + LPC_O_IRQCTL); + ulTemp &= ~(ulIRQ & 0xFFFF0000); + HWREG(ulBase + LPC_O_IRQCTL) = ulTemp; +} + +//***************************************************************************** +// +//! Get the configuration and status of the IRQ signals +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function returns the LPC module's SERIRQ status. The value returned +//! is a combination of the following values: \b LPC_IRQ15, \b LPC_IRQ14, +//! \b LPC_IRQ13, \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, +//! \b LPC_IRQ8, \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, +//! \b LPC_IRQ3, \b LPC_IRQ2, \b LPC_IRQ1, \b LPC_IRQ0, \b LPC_IRQ_BUSY, or +//! \b LPC_IRQ_CONT. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +LPCIRQGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Simply read the registers and return the values. + // + return(HWREG(ulBase + LPC_O_IRQST)); +} + +//***************************************************************************** +// +//! Trigger a manual SIRQ frame. +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function forces the sending of an SIRQ frame using whatever values are +//! currently set (auto and/or manual). +//! +//! \return None. +// +//***************************************************************************** +void +LPCIRQSend(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Set the bit to force the sending of an SIRQ frame. + // + HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_SND; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the LPC module. +//! +//! \param ulBase specifies the LPC module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! LPC interrupt occurs. +//! +//! This function registers the handler to be called when an LPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific LPC interrupts must be enabled via LPCIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via LPCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_LPC0, pfnHandler); + + // + // Enable the LPC interrupt. + // + IntEnable(INT_LPC0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the LPC module. +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function unregisters the handler to be called when an LPC interrupt +//! occurs. This fucntion also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Disable the LPC interrupt. + // + IntDisable(INT_LPC0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_LPC0); +} + +//***************************************************************************** +// +//! Enables individual LPC interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated LPC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter can be any of the following values: +//! \b LPC_INT_RST, \b LPC_INT_SLEEP, \b LPC_INT_COMx, \b LPC_INT_SIRQ, +//! \b LPC_INT_CHx_EP_TO_HOST, \b LPC_INT_CHx_EP_FROM_DATA, +//! \b LPC_INT_CHx_EP_FROM_CMD, \b LPC_INT_CHx_MB_HOST_WON, +//! \b LPC_INT_CHx_MB_HOST_WRITE, \b LPC_INT_CHx_MB_HOST_READ, or +//! \b LPC_INT_CHx_MB_MCU_LOST, where \b CHx can be \b CH6, \b CH5, \b CH4, +//! \b CH3, \b CH2, \b CH1, or \b CH0. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current mask value. + // + HWREG(ulBase + LPC_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual LPC interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This funciton disables the indicated LPC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \sa The description of the LPCIntEnable() function provides detailed +//! information for the bit-mapped values in \e ulIntFlags. +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + LPC_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the LPC module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the LPC module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! The interpretation of the LPC_INT_CHx fields varies based on the type +//! value programed for the specific Channel. +//! +//! \sa The description of the LPCIntEnable() function provides detailed +//! information for the bit-mapped values returned by this function. +//! +//! \return The current interrupt status. +// +//***************************************************************************** +unsigned long +LPCIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + LPC_O_MIS)); + } + else + { + return(HWREG(ulBase + LPC_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears LPC interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified LPC interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \sa The description of the LPCIntEnable() function provides detailed +//! information for the bit-mapped values in \e ulIntFlags. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + LPC_O_IC) = ulIntFlags; +} + +//***************************************************************************** +// +//! Enables an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to enable. +//! +//! The specified LPC Channel is enabled. +//! +//! The value for the \e ulChannel parameter can be any one of the following +//! values: \b LPC_CHAN_CH0, \b LPC_CHAN_CH1, \b LPC_CHAN_CH2, +//! \b LPC_CHAN_CH3, \b LPC_CHAN_CH4, \b LPC_CHAN_CH5, \b LPC_CHAN_CH6 or +//! \b LPC_CHAN_CH7. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Enable the specified channel. + // + HWREG(ulBase + LPC_O_CTL) |= (1 << ulChannel); +} + +//***************************************************************************** +// +//! Disables an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to disable. +//! +//! This function disables the specified LPC Channel. +//! +//! \sa The description of the LPCChannelEnable() function provides detailed +//! information for the values that can be usd for the \e ulChannel parameter. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Disable the specified channel. + // + HWREG(ulBase + LPC_O_CTL) &= ~(1 << ulChannel); +} + +//***************************************************************************** +// +//! Sets the configuration of an LPC Channel as an endpoint. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param ulConfig specifies configuration options required for the endpoint. +//! \param ulOffset specifies the offset from the beginning of the buffer pool +//! for this endpoint's data. +//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this +//! channel. +//! +//! This function enables the specified LPC Channel as an endpoint. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelConfigEPSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig, unsigned long ulAddress, + unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulConfig & ~(LPC_CH0CTL_IRQSEL1_M | LPC_CH0CTL_IRQSEL0_M | + LPC_CH0CTL_IRQEN1 | LPC_CH0CTL_IRQEN0_M)) == 0); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256) - 4)); + + // + // Convert the byte offset address into a half-word + // offset address and add into the control word. + // + ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) & + LPC_CH0CTL_OFFSET_M); + + // + // Write the final control value into the control word for + // the channel. + // + HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig; + + // + // Setup the IO and/or MEM address to match for this channel. + // + HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress; +} + +//***************************************************************************** +// +//! Sets the configuration of an LPC Channel as a mailbox. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param ulConfig specifies configuration options required for the endpoint. +//! \param ulOffset specifies the offset from the beginning of the buffer pool +//! for this endpoint's data. +//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this +//! channel. +//! +//! This function enables the specified LPC Channel as a mailbox. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelConfigMBSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig, unsigned long ulAddress, + unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulConfig & ~(LPC_CH0CTL_IRQSEL1_M | LPC_CH0CTL_IRQSEL1_M | + LPC_CH0CTL_IRQSEL0_M | + LPC_CH0CTL_IRQEN2 | LPC_CH0CTL_IRQEN1 | + LPC_CH0CTL_IRQEN0_M | + LPC_CH0CTL_ARBDIS | LPC_CH0CTL_AMASK_M)) == 0); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256) - 4)); + + // + // Convert the byte offset address into a half-word + // offset address and add into the control word. + // + ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) & + LPC_CH0CTL_OFFSET_M); + + // + // Set the configuration bit that enables Mailbox mode. + // + ulConfig |= LPC_CH0CTL_TYPE; + + // + // Write the final control value into the control word for + // the channel. + // + HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig; + + // + // Setup the IO and/or MEM address to match for this channel. + // + HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress; +} + +//***************************************************************************** +// +//! Sets the configuration of an LPC Channel as a COMx. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param ulConfig specifies configuration options required for the endpoint. +//! \param ulOffset specifies the offset from the beginning of the buffer pool +//! for this endpoint's data. +//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this +//! channel. +//! \param ulCOMxMode specifies the COMx mode to be used. +//! +//! The specified LPC Channel is enabled as a COMx. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelConfigCOMxSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulConfig, unsigned long ulAddress, + unsigned long ulOffset, unsigned long ulCOMxMode) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT(ulChannel == LPC_CHAN_COMx); + ASSERT((ulConfig & ~(LPC_CH7CTL_IRQSEL1_M | LPC_CH7CTL_IRQSEL0_M | + LPC_CH7CTL_CX | LPC_CH7CTL_IRQEN1 | + LPC_CH7CTL_IRQEN0_M)) == 0); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256) - 4)); + ASSERT((ulCOMxMode & ~LPC_DMACX_CXACT_M) == 0); + + // + // Convert the byte offset address into a half-word + // offset address and add into the control word. + // + ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) & + LPC_CH0CTL_OFFSET_M); + + // + // Write the final control value into the control word for + // the channel. + // + HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig; + + // + // Setup the IO and/or MEM address to match for this channel. + // + HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress; + + // + // Configure the COMx Mode for this channel. + // + ulTemp = HWREG(ulBase + LPC_O_DMACX); + ulTemp &= ~LPC_DMACX_CXACT_M; + ulTemp |= ulCOMxMode; + ulTemp |= LPC_DMACX_COMX; + HWREG(ulBase + LPC_O_DMACX) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the configuration of an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! \param pulOffset is a pointer to storage for the channel pool offset. +//! \param pulAddress is a pointer to storage for the channel bus address. +//! \param pulCOMxMode is a pointer to storage for the channel COMx mode. +//! +//! This function determines and returns the configuration for the specified +//! channel. +//! +//! \return Returns the bit-mapped channel control register value. +// +//***************************************************************************** +unsigned long +LPCChannelConfigGet(unsigned long ulBase, unsigned long ulChannel, + unsigned long *pulAddress, unsigned long *pulOffset, + unsigned long *pulCOMxMode) +{ + unsigned long ulConfig; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Read the channel control register. + // + ulConfig = HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)); + + // + // Get the buffer pool offset value. + // + if(pulOffset) + { + *pulOffset = ((ulConfig & LPC_CH0CTL_OFFSET_M) >> + (LPC_CH0CTL_OFFSET_S - 1)); + } + + // + // Get the IO/Memory address that this endpoint responds to. + // + if(pulAddress) + { + *pulAddress = HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)); + } + + // + // Configure the COMx Mode for this channel. + // + if(pulCOMxMode && (ulChannel == LPC_CHAN_COMx)) + { + *pulCOMxMode = (HWREG(ulBase + LPC_O_DMACX) & 0x00070000); + } + + // + // Return the raw config value. + // + return(ulConfig); +} + +//***************************************************************************** +// +//! Gets the absolute base address of the channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC channel to configure. +//! +//! Thos function calculates the absolute address of the channel pool from the +//! channel configuration setting and returns it. +//! +//! \return Returns the absolute base address of the channel pool. +// +//***************************************************************************** +unsigned long +LPCChannelPoolAddressGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulAddress; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Read the channel control register. + // + ulAddress = HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)); + + // + // Mask off the channel offset portion and shift it into a byte + // offset (stored as half-word offset). + // + ulAddress = ((ulAddress & LPC_CH0CTL_OFFSET_M) >> + (LPC_CH0CTL_OFFSET_S - 1)); + + // + // Add the LPC and Buffer Pool base address to get the final + // address to return. + // + ulAddress += (ulBase + LPC_O_POOL); + + // + // Return the address to the calling routine. + // + return(ulAddress); +} + +//***************************************************************************** +// +//! Reads the status word from an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC Channel. +//! +//! This function reads the status word from an LPC channel and returns it to +//! the caller. +//! +//! \return content of the channel status register. +// +//***************************************************************************** +unsigned long +LPCChannelStatusGet(unsigned long ulBase, unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + + // + // Read the half-word status from the LPC Channel + // + return (HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10))); +} + +//***************************************************************************** +// +//! Sets the user bits in the status word (16-bits) of an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC Channel. +//! \param ulStatus is the user bit values to set. +//! +//! This function sets the selected user bits of the status word for an LPC +//! channel. +//! +//! \return None +// +//***************************************************************************** +void +LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulStatus) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0); + + // + // Read the status from the LPC Channel, and set new values for + // the user bits. + // + ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)); + ulTemp |= ulStatus; + HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)) = ulTemp; +} + +//***************************************************************************** +// +//! Clears the user bits in the status word (16-bits) of an LPC Channel. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulChannel specifies the LPC Channel. +//! \param ulStatus is the user bit values to clear. +//! +//! This function sets the selected user bits of the status word for an LPC +//! channel. +//! +//! \return None +// +//***************************************************************************** +void +LPCChannelStatusClear(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulStatus) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(LPCChannelValid(ulChannel)); + ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0); + + // + // Read the status from the LPC Channel, and set new values for + // the user bits. + // + ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)); + ulTemp &= ~ulStatus; + HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)) = ulTemp; +} + +//***************************************************************************** +// +//! Sets the configuration of DMA for LPC channels. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulConfig specifies the DMA channel configuration. +//! \param ulMask specifies the configuration mask to be used. +//! +//! This function sets the specified DMA channel operation based on the +//! \e ulConfig parameter. +//! +//! \return None. +// +//***************************************************************************** +void +LPCChannelDMAConfigSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMask) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulConfig & ~0x000000FF) == 0); + ASSERT((ulConfig & 0x00000003) != 0x00000003); + ASSERT((ulConfig & 0x0000000C) != 0x0000000C); + ASSERT((ulConfig & 0x00000030) != 0x00000030); + ASSERT((ulConfig & 0x000000C0) != 0x000000C0); + ASSERT((ulMask & ~0x000000FF) == 0); + + // + // Get the current mask value. + // + ulTemp = HWREG(ulBase + LPC_O_DMACX); + ulTemp &= ~ulMask; + ulTemp |= (ulConfig & ulMask); + HWREG(ulBase + LPC_O_DMACX) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the configuration of DMA for LPC channels. +//! +//! \param ulBase specifies the LPC module base address. +//! +//! This function returns the configuration of the LPC DMA channels. +//! +//! \return Returns the bit-mapped DMA channel configuration. +// +//***************************************************************************** +unsigned long +LPCChannelDMAConfigGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Get the current mask value. + // + return(HWREG(ulBase + LPC_O_DMACX) & 0x000000FF); +} + +//***************************************************************************** +// +//! Reads a byte from the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! +//! This function reads a byte from the channel pool. +//! +//! \return Returns the byte read from the pool memory. +// +//***************************************************************************** +unsigned char +LPCByteRead(unsigned long ulBase, unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Return the byte from the LPC Buffer Pool. + // + return(HWREGB(ulBase + LPC_O_POOL + ulOffset)); +} + +//***************************************************************************** +// +//! Writes a byte to the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! \param ucData specifies the byte to write. +//! +//! This function writes a byte to the channel pool. +//! +//! \return None +// +//***************************************************************************** +void +LPCByteWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Write the byte to the LPC Buffer Pool. + // + HWREGB(ulBase + LPC_O_POOL + ulOffset) = ucData; +} + +//***************************************************************************** +// +//! Reads a half-word from the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! +//! This function reads a half-word from the channel pool. The \e ulOffset +//! specified must be half-word aligned. +//! +//! \return Returns the half-word read from the pool memory. +// +//***************************************************************************** +unsigned short +LPCHalfWordRead(unsigned long ulBase, unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 1) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Return the half-word from the LPC Buffer Pool. + // + return(HWREGH(ulBase + LPC_O_POOL + ulOffset)); +} + +//***************************************************************************** +// +//! Writes a half-word to the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! \param usData specifies the byte to write. +//! +//! This function writes a half-word to the channel pool. The \e ulOffset +//! specified must be half-word aligned. +//! +//! \return None +// +//***************************************************************************** +void +LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned short usData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 1) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Write the half-word to the LPC Buffer Pool. + // + HWREGH(ulBase + LPC_O_POOL + ulOffset) = usData; +} + +//***************************************************************************** +// +//! Reads a word from the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! +//! This function reads a word from the channel pool. The \e ulOffset +//! specified must be word aligned. +//! +//! \return Returns the word read from the pool memory. +// +//***************************************************************************** +unsigned long +LPCWordRead(unsigned long ulBase, unsigned long ulOffset) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 3) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Return the word from the LPC Buffer Pool. + // + return(HWREG(ulBase + LPC_O_POOL + ulOffset)); +} + +//***************************************************************************** +// +//! Writes a word to the LPC channel pool. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulOffset specifies the offset from the beginning of the LPC channel +//! pool. +//! \param ulData specifies the word to write. +//! +//! This function writes a word to the channel pool. The \e ulOffset +//! specified must be word aligned. +//! +//! \return None +// +//***************************************************************************** +void +LPCWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulOffset & 1) == 0); + ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >> + 16) * 256)); + + // + // Write the word to the LPC Buffer Pool. + // + HWREG(ulBase + LPC_O_POOL + ulOffset) = ulData; +} + +//***************************************************************************** +// +//! Enables individual COMx interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated COMx interrupt sources to trigger the +//! COMx interrupt in the primary LPC interrupt registers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulIntFlags & ~(LPC_DMACX_CXEM | LPC_DMACX_CXTXEM | + LPC_DMACX_CXRXEM)) == 0); + + // + // Get the current mask value. + // + HWREG(ulBase + LPC_O_DMACX) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual COMx interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated COMx interrupt sources from triggering +//! the COMx interrupt in the primary LPC interrupt registers. +//! +//! \return None. +// +//***************************************************************************** +void +LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulIntFlags & ~(LPC_DMACX_CXEM | LPC_DMACX_CXTXEM | + LPC_DMACX_CXRXEM)) == 0); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + LPC_O_DMACX) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current COMx interrupt status. +//! +//! \param ulBase specifies the LPC module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the COMx module. +//! +//! \return The current interrupt status. +// +//***************************************************************************** +unsigned long +LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + ulStatus = HWREG(ulBase + LPC_O_DMACX); + if(bMasked) + { + ulStatus = ulStatus & (ulStatus << 4); + } + return(ulStatus & (LPC_DMACX_CXRES | LPC_DMACX_CXTXRES | + LPC_DMACX_CXRXRES)); +} + +//***************************************************************************** +// +//! Clears COMx interrupt sources. +//! +//! \param ulBase specifies the LPC module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified COMx interrupt sources so that they no +//! longer assert. +//! +//! \return None. +// +//***************************************************************************** +void +LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == LPC0_BASE); + ASSERT((ulIntFlags & ~(LPC_DMACX_CXRES | LPC_DMACX_CXTXRES | + LPC_DMACX_CXRXRES)) == 0); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + LPC_O_DMACX) |= ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/lpc.h b/bsp/lm3s8962/Libraries/driverlib/lpc.h new file mode 100644 index 0000000000..ec67c6578c --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/lpc.h @@ -0,0 +1,470 @@ +//***************************************************************************** +// +// lpc.h - Prototypes for the Low Pin Count (LPC) driver. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __LPC_H__ +#define __LPC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to LPCConfigSet as the ulConfig value, and +// returned from LPCConfigGet. +// +//***************************************************************************** +#define LPC_CFG_WAKE 0x00000100 // Restart the LPC Bus + +//***************************************************************************** +// +// Values that can be returned from LPCStatus. +// +//***************************************************************************** +#define LPC_STATUS_RST 0x00000400 // LPC is in Reset +#define LPC_STATUS_BUSY 0x00000200 // LPC is Busy +#define LPC_STATUS_SLEEP 0x00000100 // LPC is in Sleep Mode +#define LPC_STATUS_CA7 0x00000080 // Channel 7 Active +#define LPC_STATUS_CA6 0x00000040 // Channel 6 Active +#define LPC_STATUS_CA5 0x00000020 // Channel 5 Active +#define LPC_STATUS_CA4 0x00000010 // Channel 4 Active +#define LPC_STATUS_CA3 0x00000008 // Channel 3 Active +#define LPC_STATUS_CA2 0x00000004 // Channel 2 Active +#define LPC_STATUS_CA1 0x00000002 // Channel 1 Active +#define LPC_STATUS_CA0 0x00000001 // Channel 0 Active + +//***************************************************************************** +// +// Values that can be passed to LPCIRQSet and LPCIRQClear in the ulIRQ +// parameter and returned from LPCIRQGet. +// +//***************************************************************************** +#define LPC_IRQ15 0x80000000 // Serial IRQ15 +#define LPC_IRQ14 0x40000000 // Serial IRQ14 +#define LPC_IRQ13 0x20000000 // Serial IRQ13 +#define LPC_IRQ12 0x10000000 // Serial IRQ12 +#define LPC_IRQ11 0x08000000 // Serial IRQ11 +#define LPC_IRQ10 0x04000000 // Serial IRQ10 +#define LPC_IRQ9 0x02000000 // Serial IRQ9 +#define LPC_IRQ8 0x01000000 // Serial IRQ8 +#define LPC_IRQ7 0x00800000 // Serial IRQ7 +#define LPC_IRQ6 0x00400000 // Serial IRQ6 +#define LPC_IRQ5 0x00200000 // Serial IRQ5 +#define LPC_IRQ4 0x00100000 // Serial IRQ4 +#define LPC_IRQ3 0x00080000 // Serial IRQ3 +#define LPC_IRQ2 0x00040000 // Serial IRQ2 +#define LPC_IRQ1 0x00020000 // Serial IRQ1 +#define LPC_IRQ0 0x00010000 // Serial IRQ0 + +//***************************************************************************** +// +// Addition values that can be returned from LPCIRQGet. +// +//***************************************************************************** +#define LPC_IRQ_BUSY 0x00000004 // SERIRQ frame in progress +#define LPC_IRQ_CONT 0x00000001 // SERIRQ in Continuous Mode + +//***************************************************************************** +// +// Values that can be passed as the ulChannel parameter in LPCChannel... +// API calls. +// +//***************************************************************************** +#define LPC_CHAN_CH0 0 // LPC Channel 0 +#define LPC_CHAN_CH1 1 // LPC Channel 1 +#define LPC_CHAN_CH2 2 // LPC Channel 2 +#define LPC_CHAN_CH3 3 // LPC Channel 3 +#define LPC_CHAN_CH4 4 // LPC Channel 4 +#define LPC_CHAN_CH5 5 // LPC Channel 5 +#define LPC_CHAN_CH6 6 // LPC Channel 6 +#define LPC_CHAN_CH7 7 // LPC Channel 7 (COMx) +#define LPC_CHAN_COMx 7 // LPC Channel 7 (COMx) + +//***************************************************************************** +// +// Values that can be passed as part of the ulConfig parameter in the +// LPCChannelConfig... functions. +// +//***************************************************************************** +#define LPC_CHAN_IRQSEL2_NONE 0x00000000 // LPC Channel IRQSEL2 Disabled +#define LPC_CHAN_IRQSEL2_IRQ0 0x00080000 // LPC Channel IRQSEL2 IRQ0 +#define LPC_CHAN_IRQSEL2_IRQ1 0x10080000 // LPC Channel IRQSEL2 IRQ1 +#define LPC_CHAN_IRQSEL2_IRQ2 0x20080000 // LPC Channel IRQSEL2 IRQ2 +#define LPC_CHAN_IRQSEL2_IRQ3 0x30080000 // LPC Channel IRQSEL2 IRQ3 +#define LPC_CHAN_IRQSEL2_IRQ4 0x40080000 // LPC Channel IRQSEL2 IRQ4 +#define LPC_CHAN_IRQSEL2_IRQ5 0x50080000 // LPC Channel IRQSEL2 IRQ5 +#define LPC_CHAN_IRQSEL2_IRQ6 0x60080000 // LPC Channel IRQSEL2 IRQ6 +#define LPC_CHAN_IRQSEL2_IRQ7 0x70080000 // LPC Channel IRQSEL2 IRQ7 +#define LPC_CHAN_IRQSEL2_IRQ8 0x80080000 // LPC Channel IRQSEL2 IRQ8 +#define LPC_CHAN_IRQSEL2_IRQ9 0x90080000 // LPC Channel IRQSEL2 IRQ9 +#define LPC_CHAN_IRQSEL2_IRQ10 0xA0080000 // LPC Channel IRQSEL2 IRQ10 +#define LPC_CHAN_IRQSEL2_IRQ11 0xB0080000 // LPC Channel IRQSEL2 IRQ11 +#define LPC_CHAN_IRQSEL2_IRQ12 0xC0080000 // LPC Channel IRQSEL2 IRQ12 +#define LPC_CHAN_IRQSEL2_IRQ13 0xD0080000 // LPC Channel IRQSEL2 IRQ13 +#define LPC_CHAN_IRQSEL2_IRQ14 0xE0080000 // LPC Channel IRQSEL2 IRQ14 +#define LPC_CHAN_IRQSEL2_IRQ15 0xF0080000 // LPC Channel IRQSEL2 IRQ15 + +#define LPC_CHAN_COMxIRQ_DISABLE \ + 0x00000000 // LCP Channel COMx IRQ Disabled +#define LPC_CHAN_COMxIRQ_ENABLE 0x00080000 // LCP Channel COMx IRQ Enabled + +#define LPC_CHAN_IRQSEL1_NONE 0x00000000 // LPC Channel IRQSEL1 Disabled +#define LPC_CHAN_IRQSEL1_IRQ0 0x00040000 // LPC Channel IRQSEL1 IRQ0 +#define LPC_CHAN_IRQSEL1_IRQ1 0x01040000 // LPC Channel IRQSEL1 IRQ1 +#define LPC_CHAN_IRQSEL1_IRQ2 0x02040000 // LPC Channel IRQSEL1 IRQ2 +#define LPC_CHAN_IRQSEL1_IRQ3 0x03040000 // LPC Channel IRQSEL1 IRQ3 +#define LPC_CHAN_IRQSEL1_IRQ4 0x04040000 // LPC Channel IRQSEL1 IRQ4 +#define LPC_CHAN_IRQSEL1_IRQ5 0x05040000 // LPC Channel IRQSEL1 IRQ5 +#define LPC_CHAN_IRQSEL1_IRQ6 0x06040000 // LPC Channel IRQSEL1 IRQ6 +#define LPC_CHAN_IRQSEL1_IRQ7 0x07040000 // LPC Channel IRQSEL1 IRQ7 +#define LPC_CHAN_IRQSEL1_IRQ8 0x08040000 // LPC Channel IRQSEL1 IRQ8 +#define LPC_CHAN_IRQSEL1_IRQ9 0x09040000 // LPC Channel IRQSEL1 IRQ9 +#define LPC_CHAN_IRQSEL1_IRQ10 0x0A040000 // LPC Channel IRQSEL1 IRQ10 +#define LPC_CHAN_IRQSEL1_IRQ11 0x0B040000 // LPC Channel IRQSEL1 IRQ11 +#define LPC_CHAN_IRQSEL1_IRQ12 0x0C040000 // LPC Channel IRQSEL1 IRQ12 +#define LPC_CHAN_IRQSEL1_IRQ13 0x0D040000 // LPC Channel IRQSEL1 IRQ13 +#define LPC_CHAN_IRQSEL1_IRQ14 0x0E040000 // LPC Channel IRQSEL1 IRQ14 +#define LPC_CHAN_IRQSEL1_IRQ15 0x0F040000 // LPC Channel IRQSEL1 IRQ15 + +#define LPC_CHAN_IRQSEL0_NONE 0x00000000 // LPC Channel IRQSEL0 Disabled +#define LPC_CHAN_IRQSEL0_IRQ0 0x00000000 // LPC Channel IRQSEL0 IRQ0 +#define LPC_CHAN_IRQSEL0_IRQ1 0x00100000 // LPC Channel IRQSEL0 IRQ1 +#define LPC_CHAN_IRQSEL0_IRQ2 0x00200000 // LPC Channel IRQSEL0 IRQ2 +#define LPC_CHAN_IRQSEL0_IRQ3 0x00300000 // LPC Channel IRQSEL0 IRQ3 +#define LPC_CHAN_IRQSEL0_IRQ4 0x00400000 // LPC Channel IRQSEL0 IRQ4 +#define LPC_CHAN_IRQSEL0_IRQ5 0x00500000 // LPC Channel IRQSEL0 IRQ5 +#define LPC_CHAN_IRQSEL0_IRQ6 0x00600000 // LPC Channel IRQSEL0 IRQ6 +#define LPC_CHAN_IRQSEL0_IRQ7 0x00700000 // LPC Channel IRQSEL0 IRQ7 +#define LPC_CHAN_IRQSEL0_IRQ8 0x00800000 // LPC Channel IRQSEL0 IRQ8 +#define LPC_CHAN_IRQSEL0_IRQ9 0x00900000 // LPC Channel IRQSEL0 IRQ9 +#define LPC_CHAN_IRQSEL0_IRQ10 0x00A00000 // LPC Channel IRQSEL0 IRQ10 +#define LPC_CHAN_IRQSEL0_IRQ11 0x00B00000 // LPC Channel IRQSEL0 IRQ11 +#define LPC_CHAN_IRQSEL0_IRQ12 0x00C00000 // LPC Channel IRQSEL0 IRQ12 +#define LPC_CHAN_IRQSEL0_IRQ13 0x00D00000 // LPC Channel IRQSEL0 IRQ13 +#define LPC_CHAN_IRQSEL0_IRQ14 0x00E00000 // LPC Channel IRQSEL0 IRQ14 +#define LPC_CHAN_IRQSEL0_IRQ15 0x00F00000 // LPC Channel IRQSEL0 IRQ15 +#define LPC_CHAN_IRQEN0_OFF 0x00000000 // LPC Channel IRQEN0 Disabled +#define LPC_CHAN_IRQEN0_TRG1 0x00010000 // LPC Channel IRQEN0 Trigger 1 +#define LPC_CHAN_IRQEN0_TRG2 0x00020000 // LPC Channel IRQEN0 Trigger 2 +#define LPC_CHAN_IRQEN0_TRG3 0x00030000 // LPC Channel IRQEN0 Trigger 3 + +#define LPC_CHAN_MBARB_ENABLED 0x00000000 // LPC Channel Mailbox Arbritration + // enabled. +#define LPC_CHAN_MBARB_DISABLED 0x00008000 // LPC Channel Mailbox Arbritration + // disabled. + +#define LPC_CHAN_SIZE_4 0x00000000 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_8 0x00000004 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_16 0x00000008 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_32 0x0000000C // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_64 0x00000010 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_128 0x00000014 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_256 0x00000018 // Mailbox IO/Memory Window size + // is 4 Bytes. +#define LPC_CHAN_SIZE_512 0x0000001C // Mailbox IO/Memory Window size + // is 4 Bytes. + +//***************************************************************************** +// +// Values that can be passed to LCPChannelConfigCOMxSet as the ulCOMxMode +// parameter or returned from LPCChannelConfigGet in the pulCOMxMode +// parameter. +// +//***************************************************************************** +#define LPC_COMx_MODE_FRMHNML 0x00000000 // Normal From Host model. +#define LPC_COMx_MODE_FRMHIGN 0x00020000 // Ignore From Host data. +#define LPC_COMx_MODE_FRMHDMA 0x00040000 // COMx DMA on From Host data to + // memory +#define LPC_COMx_MODE_UARTDMA 0x00060000 // COMx DMA on From Host data to + // UART1 + +//***************************************************************************** +// +// Additinal values that can be returned from LPCChannelConfigGet in the +// pulCOMxMode parameter. +// +//***************************************************************************** +#define LPC_COMx_ENABLED 0x00010000 // COMx mode enabled. + +//***************************************************************************** +// +// Values that can be passed to LPCIntEnable, LPCIntDisable, and LPCIntClear +// as the ulIntFlags parameter and returned by LPCIntStatus. +// +//***************************************************************************** +#define LPC_INT_RST 0x80000000 // LPC Bus Enters or Exits + // Reset State. +#define LPC_INT_SLEEP 0x40000000 // LPC Bus Enters or Exits + // Sleep State. +#define LPC_INT_COMx 0x20000000 // COMx has read/written + // data. +#define LPC_INT_SIRQ 0x10000000 // SERIRQ frame has completed +#define LPC_INT_CH6_EP_TO_HOST (1 << 24) // To-Host has been read. +#define LPC_INT_CH6_EP_FROM_DATA \ + (2 << 24) // From-Host has been written as + // data. +#define LPC_INT_CH6_EP_FROM_CMD (4 << 24) // From-Host has been written as + // command. +#define LPC_INT_CH6_MB_HOST_WON (1 << 24) // Host Won (HW1ST) +#define LPC_INT_CH6_MB_HOST_WRITE \ + (2 << 24) // Host Wrote Last Byte. +#define LPC_INT_CH6_MB_HOST_READ \ + (4 << 24) // Host Read Last Byte +#define LPC_INT_CH6_MB_MCU_LOST (8 << 24) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH5_EP_TO_HOST (1 << 20) // To-Host has been read. +#define LPC_INT_CH5_EP_FROM_DATA \ + (2 << 20) // From-Host has been written as + // data. +#define LPC_INT_CH5_EP_FROM_CMD (4 << 20) // From-Host has been written as + // command. +#define LPC_INT_CH5_MB_HOST_WON (1 << 20) // Host Won (HW1ST) +#define LPC_INT_CH5_MB_HOST_WRITE \ + (2 << 20) // Host Wrote Last Byte. +#define LPC_INT_CH5_MB_HOST_READ \ + (4 << 20) // Host Read Last Byte +#define LPC_INT_CH5_MB_MCU_LOST (8 << 20) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH4_EP_TO_HOST (1 << 16) // To-Host has been read. +#define LPC_INT_CH4_EP_FROM_DATA \ + (2 << 16) // From-Host has been written as + // data. +#define LPC_INT_CH4_EP_FROM_CMD (4 << 16) // From-Host has been written as + // command. +#define LPC_INT_CH4_MB_HOST_WON (1 << 16) // Host Won (HW1ST) +#define LPC_INT_CH4_MB_HOST_WRITE \ + (2 << 16) // Host Wrote Last Byte. +#define LPC_INT_CH4_MB_HOST_READ \ + (4 << 16) // Host Read Last Byte +#define LPC_INT_CH4_MB_MCU_LOST (8 << 16) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH3_EP_TO_HOST (1 << 12) // To-Host has been read. +#define LPC_INT_CH3_EP_FROM_DATA \ + (2 << 12) // From-Host has been written as + // data. +#define LPC_INT_CH3_EP_FROM_CMD (4 << 12) // From-Host has been written as + // command. +#define LPC_INT_CH3_MB_HOST_WON (1 << 12) // Host Won (HW1ST) +#define LPC_INT_CH3_MB_HOST_WRITE \ + (2 << 12) // Host Wrote Last Byte. +#define LPC_INT_CH3_MB_HOST_READ \ + (4 << 12) // Host Read Last Byte +#define LPC_INT_CH3_MB_MCU_LOST (8 << 12) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH2_EP_TO_HOST (1 << 8) // To-Host has been read. +#define LPC_INT_CH2_EP_FROM_DATA \ + (2 << 8) // From-Host has been written as + // data. +#define LPC_INT_CH2_EP_FROM_CMD (4 << 8) // From-Host has been written as + // command. +#define LPC_INT_CH2_MB_HOST_WON (1 << 8) // Host Won (HW1ST) +#define LPC_INT_CH2_MB_HOST_WRITE \ + (2 << 8) // Host Wrote Last Byte. +#define LPC_INT_CH2_MB_HOST_READ \ + (4 << 8) // Host Read Last Byte +#define LPC_INT_CH2_MB_MCU_LOST (8 << 8) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH1_EP_TO_HOST (1 << 4) // To-Host has been read. +#define LPC_INT_CH1_EP_FROM_DATA \ + (2 << 4) // From-Host has been written as + // data. +#define LPC_INT_CH1_EP_FROM_CMD (4 << 4) // From-Host has been written as + // command. +#define LPC_INT_CH1_MB_HOST_WON (1 << 4) // Host Won (HW1ST) +#define LPC_INT_CH1_MB_HOST_WRITE \ + (2 << 4) // Host Wrote Last Byte. +#define LPC_INT_CH1_MB_HOST_READ \ + (4 << 4) // Host Read Last Byte +#define LPC_INT_CH1_MB_MCU_LOST (8 << 4) // MCU Lost (when host had HW1ST). +#define LPC_INT_CH0_EP_TO_HOST (1 << 0) // To-Host has been read. +#define LPC_INT_CH0_EP_FROM_DATA \ + (2 << 0) // From-Host has been written as + // data. +#define LPC_INT_CH0_EP_FROM_CMD (4 << 0) // From-Host has been written as + // command. +#define LPC_INT_CH0_MB_HOST_WON (1 << 0) // Host Won (HW1ST) +#define LPC_INT_CH0_MB_HOST_WRITE \ + (2 << 0) // Host Wrote Last Byte. +#define LPC_INT_CH0_MB_HOST_READ \ + (4 << 0) // Host Read Last Byte +#define LPC_INT_CH0_MB_MCU_LOST (8 << 0) // MCU Lost (when host had HW1ST). + +//***************************************************************************** +// +// Values that can be passed to LPCCOMxInt... functions as the ulIntFlags +// parameter and returned by LPCIntStatus. +// +//***************************************************************************** +#define LPC_COMx_INT_CX 0x02000000 // Raw Event State for COMx +#define LPC_COMx_INT_CXTX 0x01000000 // Raw Event State for COMx TX +#define LPC_COMx_INT_CXRX 0x00800000 // Raw Event State for COMx RX +#define LPC_COMx_MASK_CX 0x00200000 // Event Mask for COMx +#define LPC_COMx_MASK_CXTX 0x00100000 // Event Mask for COMx TX +#define LPC_COMx_MASK_CXRX 0x00080000 // Event Mask for COMx RX + +//***************************************************************************** +// +// Values that can be passed to the LPCChannelDMAConfigSet function as part +// of the ulConfig or ulMask parameter, or can be returned from the +// LPCChannelConfigGet function. +// +//***************************************************************************** +#define LPC_DMA_CH3_WEN 0x00000080 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH3_REN 0x00000040 // Trigger DMA when "From Host" + // data buffer is full. +#define LPC_DMA_CH2_WEN 0x00000020 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH2_REN 0x00000010 // Trigger DMA when "From Host" + // data buffer is full. +#define LPC_DMA_CH1_WEN 0x00000008 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH1_REN 0x00000004 // Trigger DMA when "From Host" + // data buffer is full. +#define LPC_DMA_CH0_WEN 0x00000002 // Trigger DMA for "To Host" data + // buffer is empty. +#define LPC_DMA_CH0_REN 0x00000001 // Trigger DMA when "From Host" + // data buffer is full. +//***************************************************************************** +// +// Values that can be passed to the LPCChannelStatusSet and +// LPCChannelStatusClear function, and returned by the LPCChannelStatusGet +// function. +// +//***************************************************************************** +#define LPC_CH_ST_USER0 0x00000100 // User Status Bit 0 +#define LPC_CH_ST_USER1 0x00000200 // User Status Bit 1 +#define LPC_CH_ST_USER2 0x00000400 // User Status Bit 2 +#define LPC_CH_ST_USER3 0x00000800 // User Status Bit 3 +#define LPC_CH_ST_USER4 0x00001000 // User Status Bit 4 + +//***************************************************************************** +// +// Additinoal values that can be returned by the LPCChannelStatusGet function. +// +//***************************************************************************** +#define LPC_CH_ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH_ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH_ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH_ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH_ST_CMD 0x00000008 // Command or Data +#define LPC_CH_ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH_ST_TOH 0x00000001 // To-Host Transaction + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void LPCConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long LPCConfigGet(unsigned long ulBase); +extern unsigned long LPCStatusGet(unsigned long ulBase, + unsigned long *pulCount, + unsigned long *pulPoolSize); +extern void LPCStatusBlockAddressSet(unsigned long ulBase, + unsigned long ulAddress, + tBoolean bEnabled); +extern unsigned LPCStatusBlockAddressGet(unsigned long ulBase); +extern void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount); +extern void LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse, + tBoolean bIRQOnChange); +extern void LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ); +extern void LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ); +extern unsigned long LPCIRQGet(unsigned long ulBase); +extern void LPCIRQSend(unsigned long ulBase); +extern void LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void LPCIntUnregister(unsigned long ulBase); +extern void LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long LPCIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel); +extern void LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel); +extern void LPCChannelConfigEPSet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig, + unsigned long ulAddress, + unsigned long ulOffset); +extern void LPCChannelConfigMBSet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig, + unsigned long ulAddress, + unsigned long ulOffset); +extern void LPCChannelConfigCOMxSet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulConfig, + unsigned long ulAddress, + unsigned long ulOffset, + unsigned long ulCOMxMode); +extern unsigned long LPCChannelConfigGet(unsigned long ulBase, + unsigned long ulChannel, + unsigned long *pulAddress, + unsigned long *pulOffset, + unsigned long *pulCOMxMode); +extern unsigned long LPCChannelPoolAddressGet(unsigned long ulBase, + unsigned long ulChannel); +extern unsigned long LPCChannelStatusGet(unsigned long ulBase, + unsigned long ulChannel); +extern void LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulStatus); +extern void LPCChannelStatusClear(unsigned long ulBase, + unsigned long ulChannel, + unsigned long ulStatus); +extern void LPCChannelDMAConfigSet(unsigned long ulBase, + unsigned long ulConfig, + unsigned long ulMask); +extern unsigned long LPCChannelDMAConfigGet(unsigned long ulBase); +extern unsigned char LPCByteRead(unsigned long ulBase, unsigned long ulOffset); +extern void LPCByteWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned char ucData); +extern unsigned short LPCHalfWordRead(unsigned long ulBase, + unsigned long ulOffset); +extern void LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned short usData); +extern unsigned long LPCWordRead(unsigned long ulBase, unsigned long ulOffset); +extern void LPCWordWrite(unsigned long ulBase, unsigned long ulOffset, + unsigned long ulData); +extern void LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __LPC_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/mpu.c b/bsp/lm3s8962/Libraries/driverlib/mpu.c index 143af02da2..a0bc0c404e 100644 --- a/bsp/lm3s8962/Libraries/driverlib/mpu.c +++ b/bsp/lm3s8962/Libraries/driverlib/mpu.c @@ -2,7 +2,7 @@ // // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -42,14 +42,13 @@ //! //! \param ulMPUConfig is the logical OR of the possible configurations. //! -//! This function enables the Cortex-M3 memory protection unit. It also -//! configures the default behavior when in privileged mode and while -//! handling a hard fault or NMI. Prior to enabling the MPU, at least one -//! region must be set by calling MPURegionSet() or else by enabling the -//! default region for privileged mode by passing the -//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable(). -//! Once the MPU is enabled, a memory management fault will be generated -//! for any memory access violations. +//! This function enables the Cortex-M memory protection unit. It also +//! configures the default behavior when in privileged mode and while handling +//! a hard fault or NMI. Prior to enabling the MPU, at least one region must +//! be set by calling MPURegionSet() or else by enabling the default region for +//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to +//! MPUEnable(). Once the MPU is enabled, a memory management fault is +//! generated for memory access violations. //! //! The \e ulMPUConfig parameter should be the logical OR of any of the //! following: @@ -63,8 +62,8 @@ //! disabled while in one of these exception handlers and the default //! memory map is applied. //! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, -//! no default memory map is provided in privileged mode, and the MPU will -//! not be enabled in the fault handlers. +//! no default memory map is provided in privileged mode, and the MPU isl +//! not enabled in the fault handlers. //! //! \return None. // @@ -89,7 +88,7 @@ MPUEnable(unsigned long ulMPUConfig) // //! Disables the MPU for use. //! -//! This function disables the Cortex-M3 memory protection unit. When the +//! This function disables the Cortex-M memory protection unit. When the //! MPU is disabled, the default memory map is used and memory management //! faults are not generated. //! @@ -109,9 +108,8 @@ MPUDisable(void) // //! Gets the count of regions supported by the MPU. //! -//! This function is used to get the number of regions that are supported by -//! the MPU. This is the total number that are supported, including regions -//! that are already programmed. +//! This function is used to get the total number of regions that are supported +//! by the MPU, including regions that are already programmed. //! //! \return The number of memory protection regions that are available //! for programming using MPURegionSet(). @@ -121,7 +119,7 @@ unsigned long MPURegionCountGet(void) { // - // Read the DREGION field of the MPU type register, and mask off + // Read the DREGION field of the MPU type register and mask off // the bits of interest to get the count of regions. // return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) @@ -135,9 +133,9 @@ MPURegionCountGet(void) //! \param ulRegion is the region number to enable. //! //! This function is used to enable a memory protection region. The region -//! should already be set up with the MPURegionSet() function. Once enabled, -//! the memory protection rules of the region will be applied and access -//! violations will cause a memory management fault. +//! should already be configured with the MPURegionSet() function. Once +//! enabled, the memory protection rules of the region are applied and access +//! violations cause a memory management fault. //! //! \return None. // @@ -168,7 +166,7 @@ MPURegionEnable(unsigned long ulRegion) //! \param ulRegion is the region number to disable. //! //! This function is used to disable a previously enabled memory protection -//! region. The region will remain configured if it is not overwritten with +//! region. The region remains configured if it is not overwritten with //! another call to MPURegionSet(), and can be enabled again by calling //! MPURegionEnable(). //! @@ -204,16 +202,16 @@ MPURegionDisable(unsigned long ulRegion) //! \param ulFlags is a set of flags to define the attributes of the region. //! //! This function sets up the protection rules for a region. The region has -//! a base address and a set of attributes including the size, which must -//! be a power of 2. The base address parameter, \e ulAddr, must be aligned -//! according to the size. +//! a base address and a set of attributes including the size. The base +//! address parameter, \e ulAddr, must be aligned according to the size, and +//! the size must be a power of 2. //! //! The \e ulFlags parameter is the logical OR of all of the attributes //! of the region. It is a combination of choices for region size, //! execute permission, read/write permissions, disabled sub-regions, //! and a flag to determine if the region is enabled. //! -//! The size flag determines the size of a region, and must be one of the +//! The size flag determines the size of a region and must be one of the //! following: //! //! - \b MPU_RGN_SIZE_32B @@ -263,8 +261,8 @@ MPURegionDisable(unsigned long ulRegion) //! //! The region is automatically divided into 8 equally-sized sub-regions by //! the MPU. Sub-regions can only be used in regions of size 256 bytes -//! or larger. Any of these 8 sub-regions can be disabled. This allows -//! for creation of ``holes'' in a region which can be left open, or overlaid +//! or larger. Any of these 8 sub-regions can be disabled, allowing for +//! creation of ``holes'' in a region which can be left open, or overlaid //! by another region with different attributes. Any of the 8 sub-regions //! can be disabled with a logical OR of any of the following flags: //! @@ -293,7 +291,7 @@ MPURegionDisable(unsigned long ulRegion) //! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) //! //! -//! \note This function will write to multiple registers and is not protected +//! \note This function writes to multiple registers and is not protected //! from interrupts. It is possible that an interrupt which accesses a //! region may occur while that region is in the process of being changed. //! The safest way to handle this is to disable a region before changing it. @@ -342,9 +340,9 @@ MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, //! meanings and format of the parameters is the same as that of the //! MPURegionSet() function. //! -//! This function can be used to save the configuration of a region for -//! later use with the MPURegionSet() function. The region's enable state -//! will be preserved in the attributes that are saved. +//! This function can be used to save the configuration of a region for later +//! use with the MPURegionSet() function. The region's enable state is +//! preserved in the attributes that are saved. //! //! \return None. // @@ -383,8 +381,9 @@ MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, //! \param pfnHandler is a pointer to the function to be called when the //! memory management fault occurs. //! -//! This sets and enables the handler to be called when the MPU generates -//! a memory management fault due to a protection region access violation. +//! This function sets and enables the handler to be called when the MPU +//! generates a memory management fault due to a protection region access +//! violation. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -415,7 +414,7 @@ MPUIntRegister(void (*pfnHandler)(void)) // //! Unregisters an interrupt handler for the memory management fault. //! -//! This function will disable and clear the handler to be called when a +//! This function disables and clears the handler to be called when a //! memory management fault occurs. //! //! \sa IntRegister() for important information about registering interrupt diff --git a/bsp/lm3s8962/Libraries/driverlib/mpu.h b/bsp/lm3s8962/Libraries/driverlib/mpu.h index 4e05529883..655228da60 100644 --- a/bsp/lm3s8962/Libraries/driverlib/mpu.h +++ b/bsp/lm3s8962/Libraries/driverlib/mpu.h @@ -2,7 +2,7 @@ // // mpu.h - Defines and Macros for the memory protection unit. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/peci.c b/bsp/lm3s8962/Libraries/driverlib/peci.c new file mode 100644 index 0000000000..e07cfc54af --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/peci.c @@ -0,0 +1,971 @@ +//***************************************************************************** +// +// peci.c - Driver for the Platform Environment Control Interface (PECI) +// module. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup peci_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_peci.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/peci.h" + +//***************************************************************************** +// +// The following defines provide characteristics of the PECI module that are +// important to the driver but which can not be gleaned from the register +// definitions. +// +//***************************************************************************** +#define PECI_MAX_BAUD 2000000 // Maximum baud rate +#define PECI_MIN_BAUD 2000 // Minimum baud rate +#define PECI_MIN_RATIO 8 // Minimum baud rate divider +#define PECI_MAX_RATIO 65535 // Maximum baud rate divider +#define PECI_POLL_PRESCALE 4096 // Polling timer prescaler +#define PECI_MIN_POLL 2 // Minimum polling interval (ms) +#define PECI_MAX_POLL 1000 // Maximum polling interval (ms) + +//***************************************************************************** +// +//! \internal +//! Checks a PECI domain. +//! +//! \param ulDomain is the PECI domain identifier. +//! +//! This function determines if a domain identifier is valid. +//! +//! \return Returns \b true if the domain identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +PECIDomainValid(unsigned long ulDomain) +{ + return((ulDomain == PECI_DOMAIN_M0D0) || + (ulDomain == PECI_DOMAIN_M0D1) || + (ulDomain == PECI_DOMAIN_M1D0) || + (ulDomain == PECI_DOMAIN_M1D1)); +} +#endif + +//***************************************************************************** +// +//! Sets the configuration of the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulPECIClk is the rate of the clock supplied to the PECI module. +//! \param ulBaud is the bit rate that should be used for the PECI transfers. +//! \param ulPoll is the polling rate, in ms, that should be used for the +//! time between PECI polls. +//! \param ulOffset is the offset to be applied to all temperature values to +//! convert from relative to absolute. +//! \param ulRetry is the number of retry attempts for a PECI transaction. +//! +//! This function initializes operation of the PECI block. It programs the bit +//! rate, polling rate and retry counts for PECI transactions. It also +//! programs the offset value to be used to translate relative temperature +//! values from PECI transactions to absolute values. At the end of this +//! function, no host/domain combinations are enabled. Each desired +//! host/domain combination can be configured/enabled with a call to +//! PECIDomainEnable(). +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! The \e ulBaud parameter defines the bit rate for the PECI transactions. +//! This value is used to calculate a divisor value based on the specified +//! \e ulPECIClk. If the exact baud rate cannot be achieved (due to rounding), +//! the baud rate is programmed to the nearest value that is less than the +//! specified value. +//! +//! The \e ulPoll parameter defines the polling rate, in milliseconds, used +//! for PECI transactions. For generation of the polling rate, the \e +//! ulPECIClk is pre-divided by \b 4096. A value of 0 disables the polling +//! feature. If the exact polling rate cannot be achieved (due to rounding), +//! the polling rate is programmed to the nearest value that is greater than +//! the specified value. +//! +//! The \e ulRetry parameter defines the number of PECI transactions that are +//! attempted before indicating an error condition. +//! +//! \return None. +// +//***************************************************************************** +void +PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long ulBaud, unsigned long ulPoll, + unsigned long ulOffset, unsigned long ulRetry) +{ + unsigned long ulTemp, ulDiv; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(ulPECIClk != 0); + ASSERT((ulBaud != 0) && (ulBaud <= PECI_MAX_BAUD) && + (ulBaud >= PECI_MIN_BAUD) && + ((ulBaud * 4 * PECI_MIN_RATIO) < ulPECIClk)); + ASSERT((ulPoll == 0) || + ((ulPoll >= PECI_MIN_POLL) && (ulPoll <= PECI_MAX_POLL))); + + // + // Generate value for the PECI Control Register. + // + ulTemp = ((ulOffset << PECI_CTL_OFFSET_S) & PECI_CTL_OFFSET_M); + ulTemp |= ((ulRetry << PECI_CTL_CRETRY_S) & PECI_CTL_CRETRY_M); + HWREG(ulBase + PECI_O_CTL) = ulTemp; + + // + // Compute the divisor for the PECI baud rate clock. + // Round up, to ensure programmed baud rate is <= specified rate. + // Ensure that proper ratio is maintained for clock:baud. + // + ulDiv = (ulPECIClk + (4 * ulBaud) - 1) / (4 * ulBaud); + ulDiv = (ulDiv < PECI_MIN_RATIO) ? PECI_MIN_RATIO : ulDiv; + ulDiv = (ulDiv > PECI_MAX_RATIO) ? PECI_MAX_RATIO : ulDiv; + ulTemp = ((ulDiv << PECI_DIV_BAUD_S) & PECI_DIV_BAUD_M); + + // + // Compute the divisor for the PECI polling rate. + // Round up, to ensure programmed polling rate is >= specified rate. + // + ulDiv = ((ulPoll == 0) ? 0 : ((((ulPECIClk * ulPoll) / 1000) + + (PECI_POLL_PRESCALE - 1)) / + PECI_POLL_PRESCALE)); + ulTemp |= ((ulDiv << PECI_DIV_POLL_S) & PECI_DIV_POLL_M);; + HWREG(ulBase + PECI_O_DIV) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the current configuration of the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulPECIClk is the rate of the clock supplied to the PECI module. +//! \param pulBaud is a pointer to storage for the bit rate. +//! \param pulPoll is a pointer to storage for the polling rate. +//! \param pulOffset is a pointer to stoarage for the offset. +//! \param pulRetry is a pointer to storage for the retry count. +//! +//! The baud rate and poll rate for the PECI module are determined, given an +//! explicitly provided peripheral clock. The returned rates are the actual +//! rates being used; they may not be the same as the requested rates, due to +//! rounding in the calculations. +//! +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). +//! +//! \return None. +// +//***************************************************************************** +void +PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long *pulBaud, unsigned long *pulPoll, + unsigned long *pulOffset, unsigned long *pulRetry) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(ulPECIClk != 0); + ASSERT(*pulBaud != 0); + ASSERT(*pulPoll != 0); + ASSERT(*pulOffset != 0); + ASSERT(*pulRetry != 0); + + // + // Retrieve the Offset and Retry values + // + ulTemp = HWREG(ulBase + PECI_O_CTL); + *pulOffset = ((ulTemp & PECI_CTL_OFFSET_M) >> PECI_CTL_OFFSET_S); + *pulRetry = ((ulTemp & PECI_CTL_CRETRY_M) >> PECI_CTL_CRETRY_S); + + // + // Calculate the baud rate. + // + ulTemp = HWREG(ulBase + PECI_O_DIV); + *pulBaud = ulPECIClk / ((ulTemp & PECI_DIV_BAUD_M) >> PECI_DIV_BAUD_S); + + // + // Compute the divisor for the PECI polling rate. + // Round up, to ensure programmed polling rate is >= specified rate. + // + *pulPoll = ((((ulTemp & PECI_DIV_POLL_M) >> PECI_DIV_POLL_S) * 1000) / + (ulPECIClk / PECI_POLL_PRESCALE)); +} + +//***************************************************************************** +// +//! Enables bypassing of negotiation errors. +//! +//! \param ulBase is the base address of the PECI module. +//! +//! This function enables bypassing of negotiation errors that might occur +//! during a PECI transaction. When enabled, negotiation errors are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +PECIBypassEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Enable bypass. + // + HWREG(ulBase + PECI_O_CTL) |= PECI_CTL_BYERR; +} + +//***************************************************************************** +// +//! Disables bypassing of negotiation errors. +//! +//! \param ulBase is the base address of the PECI module. +//! +//! This function disables bypassing of negotiation errors that might occur +//! during a PECI transaction. When disabled, negotiation errors are reported +//! and the remainder of the transaction is aborted. +//! +//! \return None. +// +//***************************************************************************** +void +PECIBypassDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Disable bypass. + // + HWREG(ulBase + PECI_O_CTL) &= ~PECI_CTL_BYERR; +} + +//***************************************************************************** +// +//! Sets the configuration of the specified PECI domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be configured. +//! \param ulHigh is the high temperature threshold value. +//! \param ulLow is the low temperature threshold value. +//! +//! This function configures the specified PECI domain for temperature +//! monitoring operations. The values for \e ulHigh and \e ulLow can be +//! specified as values relative to the maximum temperature allowed, or they +//! can be specified as absolute temperatures if an offset was programmed +//! in the PECIConfigSet() function. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain, + unsigned long ulHigh, unsigned long ulLow) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + ASSERT(ulHigh <= 0xFFFF); + ASSERT(ulLow <= 0xFFFF); + ASSERT(ulHigh > ulLow); + + // + // Set the HTHRESH and LTHRESH fields in the domain control/status + // register. + // + HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4)) = + (((ulHigh << PECI_M0D0C_HITHR_S) & PECI_M0D0C_HITHR_M) | + ((ulLow << PECI_M0D0C_LOTHR_S) & PECI_M0D0C_LOTHR_M)); +} + +//***************************************************************************** +// +//! Gets the configuration of the specified PECI domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be configured. +//! \param pulHigh is a pointer to storage for the high threshold. +//! \param pulLow is a pointer to storage for the low threshold. +//! +//! This function configures the specified PECI domain for temperature +//! monitoring operations. The values for \e ulHigh and \e ulLow can be +//! specified as values relative to the maximum temperature allowed, or they +//! can be specified as absolute temperatures if an offset was programmed +//! in the PECIConfigSet() function. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain, + unsigned long *pulHigh, unsigned long *pulLow) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + ASSERT(pulHigh != 0); + ASSERT(pulLow != 0); + + // + // Get the HTHRESH and LTHRESH fields in the domain control/status + // register. + // + ulTemp = HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4)); + *pulHigh = ((ulTemp && PECI_M0D0C_HITHR_M) >> PECI_M0D0C_HITHR_S); + *pulLow = ((ulTemp && PECI_M0D0C_LOTHR_M) >> PECI_M0D0C_LOTHR_S); +} + +//***************************************************************************** +// +//! Enables a domain within the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be enabled. +//! +//! This function enables the specified PECI domain for temperature monitoring +//! operations. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Enable the specified domain. + // + HWREG(ulBase + PECI_O_CTL) |= (1 << ulDomain); +} + +//***************************************************************************** +// +//! Disables a domain within the PECI module. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function disables the specified PECI domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Disable the specified domain. + // + HWREG(ulBase + PECI_O_CTL) &= ~(1 << ulDomain); +} + +//***************************************************************************** +// +//! Reads the current temperature value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function returns the most recently read temperature value from the +//! specified domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +PECIDomainValueGet(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Return the most recently polled temperature value + // + return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) & + PECI_M0D0_VALUE_M))); +} + +//***************************************************************************** +// +//! Reads the maximum/error value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function returns the maximum temperature value for the specified +//! domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +PECIDomainMaxReadGet(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Return the most recently polled temperature value + // + return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) & + PECI_M0D0_MAXREAD_M) >> PECI_M0D0_MAXREAD_S)); +} + +//***************************************************************************** +// +//! Clears the current temperature value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function clears the current and maximum values for the specified +//! domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Clear the temperature value. + // + HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_VALUE_M; +} + +//***************************************************************************** +// +//! Clears the maximum/error value for the specified domain. +//! +//! \param ulBase is the base address of the PECI module. +//! \param ulDomain is the PECI domain that should be disabled. +//! +//! This function clears the current and maximum values for the specified +//! domain. +//! +//! The \e ulDomain parameter can be one of the following values: +//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or +//! \b PECI_DOMAIN_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIDomainMaxReadClear(unsigned long ulBase, unsigned long ulDomain) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(PECIDomainValid(ulDomain)); + + // + // Clear the maximum/error value. + // + HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_MAXREAD_M; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the PECI module. +//! +//! \param ulBase specifies the PECI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! PECI interrupt occurs. +//! +//! This function registers the handler to be called when an PECI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific PECI interrupts must be enabled via PECIIntEnable(). +//! If necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via PECIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_PECI0, pfnHandler); + + // + // Enable the PECI interrupt. + // + IntEnable(INT_PECI0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the PECI module. +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function unregisters the handler to be called when a PECI interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Disable the PECI interrupt. + // + IntDisable(INT_PECI0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_PECI0); +} + +//***************************************************************************** +// +//! Enables individual PECI interrupt sources. +//! +//! \param ulBase specifies the PECI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! \param ulIntMode is the mode for the PECI domain interrupts. +//! +//! This function enables the indicated PECI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter can be any of the following values: +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1. +//! +//! The \e ulIntMode parameter is used to configure the interrupt mode for +//! the corresponding \b PECI_DOMAIN_MnDm field, and can be any of the +//! following values: \b PECI_M0D0_MODE1, \b PECI_M0D0_MODE2, +//! \b PECI_M0D0_MODE3, \b PECI_M0D1_MODE1, \b PECI_M0D1_MODE2, +//! \b PECI_M0D1_MODE3. \b PECI_M1D0_MODE1, \b PECI_M1D0_MODE2, +//! \b PECI_M1D0_MODE3, \b PECI_M1D1_MODE1, \b PECI_M1D1_MODE2, or +//! \b PECI_M1D1_MODE3. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags, + unsigned long ulIntMode) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Get the current mask value. + // + ulTemp = HWREG(ulBase + PECI_O_IM); + + // + // Clear the bit/bit-fields that are configured, based on the value + // in the flags parameter. + // + ulTemp &= ~ulIntFlags; + + // + // Set/Enable the bit/bit-fields based on the value in the flags and mode + // parameter. The flags parameter alters the bits in the lower half + // of the mask, while the mode alters the bit fields in the upper + // half of the mask. + // + ulTemp |= (0x0000FFFF & ulIntFlags); + ulTemp |= (0xFFFF0000 & ulIntMode); + HWREG(ulBase + PECI_O_IM) = ulTemp; +} + +//***************************************************************************** +// +//! Disables individual PECI interrupt sources. +//! +//! \param ulBase specifies the PECI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated PECI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter can be any of the following values: +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1. +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + PECI_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the PECI module base address. +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the PECI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! The interpretation of the PECI_DOMAIN_MnDm fields vary based on the mode +//! value programed using the PECIIntEnable() function for the field. Each +//! field may take on one of the following values: +//! \b PECI_MnDm_MODE1_HIGH, \b PECI_MnDm_MODE2_MID, \b PECI_MnDm_MODE2_HIGH, +//! \b PECI_MnDm_MODE3_LOW, \b PECI_MnDm_MODE3_MID, or \b PECI_MnDm_MODE3_HIGH. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1. +// +//***************************************************************************** +unsigned long +PECIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + PECI_O_MIS)); + } + else + { + return(HWREG(ulBase + PECI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears PECI interrupt sources. +//! +//! \param ulBase specifies the PECI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified PECI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being recognized again immediately upon exit. +//! The \e ulIntFlags parameter can consist of any combination of the +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1 values. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + PECI_O_IC) = ulIntFlags; +} + +//***************************************************************************** +// +//! Sends a PECI Advanced Command. +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function sends a PECI Advanced Command. If the interface is not IDLE, +//! it waits for the interface to become IDLE then sends the command. The +//! function parameters are used to populate the message control fields before +//! activating the command. +//! +//! \return None. +// +//***************************************************************************** +void +PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd, + unsigned char ucHidRe, unsigned char ucDomain, + unsigned char ucProcAdd, unsigned long ulArg, + unsigned char ucSize, unsigned long ulData0, + unsigned long ulData1) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Wait for the interface to be idle. + // + while(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF) + { + } + + // + // Fill in the registers for the advanced command. + // + HWREG(ulBase + PECI_O_ACARG) = ulArg; + HWREG(ulBase + PECI_O_ACRDWR0) = ulData0; + HWREG(ulBase + PECI_O_ACRDWR1) = ulData1; + HWREG(ulBase + PECI_O_ACADDR) = (ucHidRe << 24) | + (ucSize << 16) | + (ucDomain << 8) | + (ucProcAdd << 0); + + // + // Now, issue the command. + // + HWREG(ulBase + PECI_O_ACCMD) = ucCmd; +} + +//***************************************************************************** +// +//! Sends a PECI Advanced Command (non blocking). +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function sends a PECI Advanced Command. If the interface is not IDLE, +//! it returns immediately. Otherwise, it sends the the command. The function +//! paramters are used to populate the message control fields before activating +//! the command. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +PECIAdvCmdSendNonBlocking(unsigned long ulBase, unsigned char ucCmd, + unsigned char ucHidRe, unsigned char ucDomain, + unsigned char ucProcAdd, unsigned long ulArg, + unsigned char ucSize, unsigned long ulData0, + unsigned long ulData1) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // Check for the interface to be idle. + // If not, return immediately. + // + if(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF) + { + return(0); + } + + // + // Send the command. + // + PECIAdvCmdSend(ulBase, ucCmd, ucHidRe, ucDomain, ucProcAdd, ulArg, + ucSize, ulData0, ulData1); + + // + // Return, indicating that the command has been issued. + // + return(1); +} + +//***************************************************************************** +// +//! Obtains status of previous PECI Advanced Command. +//! +//! \param ulBase specifies the PECI module base address. +//! +//! This function gets the status of a previously issued PECI Advanced Command. +//! If the command has completed, and the data pointers are non-zero, the data +//! registers are read and saved. +//! +//! \return -1 if command has not yet been completed, otherwise, the return +//! code associated with the Advanced Command. +// +//***************************************************************************** +unsigned long +PECIAdvCmdStatusGet(unsigned long ulBase, unsigned long *pulData0, + unsigned long *pulData1) +{ + unsigned long ulCode; + + // + // Check the arguments. + // + ASSERT(ulBase == PECI0_BASE); + + // + // If the command has completed, optionally read and save the data + // registers. + // + ulCode = HWREG(ulBase + PECI_O_ACCODE); + if(ulCode != 0xFFFFFFFF) + { + if(pulData0 != (void *)0) + { + *pulData0 = HWREG(ulBase + PECI_O_ACRDWR0); + } + if(pulData1 != (void *)0) + { + *pulData1 = HWREG(ulBase + PECI_O_ACRDWR1); + } + } + + // + // Return the command code from the most recently completed command. + // + return(ulCode); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/peci.h b/bsp/lm3s8962/Libraries/driverlib/peci.h new file mode 100644 index 0000000000..e1b0b9016b --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/peci.h @@ -0,0 +1,226 @@ +//***************************************************************************** +// +// peci.h - Prototypes for Platform Environment Control Interface (PECI) +// driver. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PECI_H__ +#define __PECI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to PECIConfigDomain, PECIEnableDomain, +// PECIDisableDomain, PECIReadDomainValue, PECIReadDomainMax, and +// PECIClearDomain as the ulDomain parameter. +// +//***************************************************************************** +#define PECI_DOMAIN_M0D0 0 // Microprocessor 0 / Domain 0 +#define PECI_DOMAIN_M0D1 1 // Microprocessor 0 / Domain 1 +#define PECI_DOMAIN_M1D0 2 // Microprocessor 1 / Domain 0 +#define PECI_DOMAIN_M1D1 3 // Microprocessor 1 / Domain 1 + +//***************************************************************************** +// +// Values that can be passed to PECIIntEnable, PECIIntDisable, and PECIIntClear +// as the ulIntFlags parameter and returned by PECIIntStatus. +// +//***************************************************************************** +#define PECI_READ 0x00000001 // End of PECI Poll +#define PECI_ERR 0x00000002 // Error on PECI Poll +#define PECI_AC 0x00000004 // Advanced Command Complete +#define PECI_M0D0 0x00030000 // Microprocessor 0 / Domain 0 +#define PECI_M0D1 0x000C0000 // Microprocessor 0 / Domain 1 +#define PECI_M1D0 0x00300000 // Microprocessor 1 / Domain 0 +#define PECI_M1D1 0x00C00000 // Microprocessor 1 / Domain 1 + +//***************************************************************************** +// +// Additional values that can be returned by PECIIntStatus. +// +//***************************************************************************** +#define PECI_M0D0_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 0 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M0D0_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 0 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M0D0_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 0 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M0D0_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 0 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M0D0_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 0 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M0D0_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 0 + // Mode 3 + // Temperature CROSSED above HIGH +#define PECI_M0D1_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 1 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M0D1_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 1 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M0D1_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 1 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M0D1_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 1 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M0D1_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 1 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M0D1_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 1 + // Mode 3 + // Temperature CROSSED above HIGH +#define PECI_M1D0_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 0 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M1D0_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 0 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M1D0_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 0 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M1D0_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 0 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M1D0_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 0 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M1D0_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 0 + // Mode 3 + // Temperature CROSSED above HIGH +#define PECI_M1D1_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 1 + // Mode 1 + // Temperature IS above HIGH +#define PECI_M1D1_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 1 + // Mode 2 + // Temperature CROSSED above LOW +#define PECI_M1D1_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 1 + // Mode 2 + // Temperature CROSSED above HIGH +#define PECI_M1D1_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 1 + // Mode 3 + // Temperature CROSSED below LOW +#define PECI_M1D1_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 1 + // Mode 3 + // Temperature CROSSED above LOW or + // Temperature CROSSED below HIGH +#define PECI_M1D1_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 1 + // Mode 3 + // Temperature CROSSED above HIGH + +//***************************************************************************** +// +// Values that can be passed to PECIIntEnable as the ulIntMode parameter. +// +//***************************************************************************** +#define PECI_M0D0_MODE1 0x00010000 // Domain Interrupt Mode 1 +#define PECI_M0D0_MODE2 0x00020000 // Domain Interrupt Mode 2 +#define PECI_M0D0_MODE3 0x00030000 // Domain Interrupt Mode 3 +#define PECI_M0D1_MODE1 0x00040000 // Domain Interrupt Mode 1 +#define PECI_M0D1_MODE2 0x00080000 // Domain Interrupt Mode 2 +#define PECI_M0D1_MODE3 0x000C0000 // Domain Interrupt Mode 3 +#define PECI_M1D0_MODE1 0x00100000 // Domain Interrupt Mode 1 +#define PECI_M1D0_MODE2 0x00200000 // Domain Interrupt Mode 2 +#define PECI_M1D0_MODE3 0x00300000 // Domain Interrupt Mode 3 +#define PECI_M1D1_MODE1 0x00400000 // Domain Interrupt Mode 1 +#define PECI_M1D1_MODE2 0x00800000 // Domain Interrupt Mode 2 +#define PECI_M1D1_MODE3 0x00C00000 // Domain Interrupt Mode 3 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long ulBaud, unsigned long ulPoll, + unsigned long ulOffset, unsigned long ulRetry); +extern void PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk, + unsigned long *pulBaud, unsigned long *pulPoll, + unsigned long *pulOffset, unsigned long *pulRetry); +extern void PECIBypassEnable(unsigned long ulBase); +extern void PECIBypassDisable(unsigned long ulBase); +extern void PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain, + unsigned long ulHigh, unsigned long ulLow); +extern void PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain, + unsigned long *pulHigh, unsigned long *pulLow); +extern void PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain); +extern void PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain); +extern unsigned long PECIDomainValueGet(unsigned long ulBase, + unsigned long ulDomain); +extern unsigned long PECIDomainMaxReadGet(unsigned long ulBase, + unsigned long ulDomain); +extern void PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain); +extern void PECIDomainMaxReadClear(unsigned long ulBase, + unsigned long ulDomain); +extern void PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void PECIIntUnregister(unsigned long ulBase); +extern void PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags, + unsigned long ulIntMode); +extern void PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long PECIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd, + unsigned char ucHidRe, unsigned char ucDomain, + unsigned char ucProcAdd, unsigned long ulArg, + unsigned char ucSize, unsigned long ulData0, + unsigned long ulData1); +extern unsigned long PECIAdvCmdSendNonBlocking(unsigned long ulBase, + unsigned char ucCmd, + unsigned char ucHidRe, + unsigned char ucDomain, + unsigned char ucProcAdd, + unsigned long ulArg, + unsigned char ucSize, + unsigned long ulData0, + unsigned long ulData1); +extern unsigned long PECIAdvCmdStatusGet(unsigned long ulBase, + unsigned long *pulData0, + unsigned long *pulData1); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PECI_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/pin_map.h b/bsp/lm3s8962/Libraries/driverlib/pin_map.h index ad75a86e4f..51c4a2e342 100644 --- a/bsp/lm3s8962/Libraries/driverlib/pin_map.h +++ b/bsp/lm3s8962/Libraries/driverlib/pin_map.h @@ -2,7 +2,7 @@ // // pin_map.h - Mapping of peripherals to pins for all parts. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -32,85 +32,85 @@ //***************************************************************************** #ifdef PART_LM3S101 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB) -#define 32KHZ_PORT (GPIO_PORTB_BASE) -#define 32KHZ_PIN (GPIO_PIN_1) +#define 32KHZ_PERIPH SYSCTL_PERIPH_GPIOB +#define 32KHZ_PORT GPIO_PORTB_BASE +#define 32KHZ_PIN GPIO_PIN_1 #endif // PART_LM3S101 @@ -121,93 +121,93 @@ //***************************************************************************** #ifdef PART_LM3S102 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB) -#define 32KHZ_PORT (GPIO_PORTB_BASE) -#define 32KHZ_PIN (GPIO_PIN_1) +#define 32KHZ_PERIPH SYSCTL_PERIPH_GPIOB +#define 32KHZ_PORT GPIO_PORTB_BASE +#define 32KHZ_PIN GPIO_PIN_1 #endif // PART_LM3S102 @@ -218,137 +218,137 @@ //***************************************************************************** #ifdef PART_LM3S300 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S300 @@ -359,105 +359,105 @@ //***************************************************************************** #ifdef PART_LM3S301 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S301 @@ -468,109 +468,109 @@ //***************************************************************************** #ifdef PART_LM3S308 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S308 @@ -581,157 +581,157 @@ //***************************************************************************** #ifdef PART_LM3S310 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S310 @@ -742,117 +742,117 @@ //***************************************************************************** #ifdef PART_LM3S315 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S315 @@ -863,133 +863,133 @@ //***************************************************************************** #ifdef PART_LM3S316 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S316 @@ -1000,125 +1000,125 @@ //***************************************************************************** #ifdef PART_LM3S317 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S317 @@ -1129,101 +1129,101 @@ //***************************************************************************** #ifdef PART_LM3S328 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S328 @@ -1234,137 +1234,137 @@ //***************************************************************************** #ifdef PART_LM3S600 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S600 @@ -1375,169 +1375,169 @@ //***************************************************************************** #ifdef PART_LM3S601 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX_PORT (GPIO_PORTD_BASE) -#define IDX_PIN (GPIO_PIN_7) +#define IDX_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX_PORT GPIO_PORTD_BASE +#define IDX_PIN GPIO_PIN_7 -#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA_PORT (GPIO_PORTC_BASE) -#define PHA_PIN (GPIO_PIN_4) +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 -#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB_PORT (GPIO_PORTC_BASE) -#define PHB_PIN (GPIO_PIN_6) +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S601 @@ -1548,109 +1548,109 @@ //***************************************************************************** #ifdef PART_LM3S608 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S608 @@ -1661,129 +1661,129 @@ //***************************************************************************** #ifdef PART_LM3S610 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S610 @@ -1794,129 +1794,129 @@ //***************************************************************************** #ifdef PART_LM3S611 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S611 @@ -1927,125 +1927,125 @@ //***************************************************************************** #ifdef PART_LM3S612 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S612 @@ -2056,133 +2056,133 @@ //***************************************************************************** #ifdef PART_LM3S613 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S613 @@ -2193,161 +2193,161 @@ //***************************************************************************** #ifdef PART_LM3S615 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S615 @@ -2358,133 +2358,133 @@ //***************************************************************************** #ifdef PART_LM3S617 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S617 @@ -2495,137 +2495,137 @@ //***************************************************************************** #ifdef PART_LM3S618 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define IDX_PORT (GPIO_PORTB_BASE) -#define IDX_PIN (GPIO_PIN_2) +#define IDX_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX_PORT GPIO_PORTB_BASE +#define IDX_PIN GPIO_PIN_2 -#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA_PORT (GPIO_PORTC_BASE) -#define PHA_PIN (GPIO_PIN_4) +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 -#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB_PORT (GPIO_PORTC_BASE) -#define PHB_PIN (GPIO_PIN_6) +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S618 @@ -2636,93 +2636,93 @@ //***************************************************************************** #ifdef PART_LM3S628 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S628 @@ -2733,137 +2733,137 @@ //***************************************************************************** #ifdef PART_LM3S800 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S800 @@ -2874,169 +2874,169 @@ //***************************************************************************** #ifdef PART_LM3S801 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX_PORT (GPIO_PORTD_BASE) -#define IDX_PIN (GPIO_PIN_7) +#define IDX_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX_PORT GPIO_PORTD_BASE +#define IDX_PIN GPIO_PIN_7 -#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA_PORT (GPIO_PORTC_BASE) -#define PHA_PIN (GPIO_PIN_4) +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 -#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB_PORT (GPIO_PORTC_BASE) -#define PHB_PIN (GPIO_PIN_6) +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S801 @@ -3047,109 +3047,109 @@ //***************************************************************************** #ifdef PART_LM3S808 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S808 @@ -3160,141 +3160,141 @@ //***************************************************************************** #ifdef PART_LM3S811 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S811 @@ -3305,125 +3305,125 @@ //***************************************************************************** #ifdef PART_LM3S812 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S812 @@ -3434,161 +3434,161 @@ //***************************************************************************** #ifdef PART_LM3S815 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S815 @@ -3599,133 +3599,133 @@ //***************************************************************************** #ifdef PART_LM3S817 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S817 @@ -3736,137 +3736,137 @@ //***************************************************************************** #ifdef PART_LM3S818 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define IDX_PORT (GPIO_PORTB_BASE) -#define IDX_PIN (GPIO_PIN_2) +#define IDX_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX_PORT GPIO_PORTB_BASE +#define IDX_PIN GPIO_PIN_2 -#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA_PORT (GPIO_PORTC_BASE) -#define PHA_PIN (GPIO_PIN_4) +#define PHA_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA_PORT GPIO_PORTC_BASE +#define PHA_PIN GPIO_PIN_4 -#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB_PORT (GPIO_PORTC_BASE) -#define PHB_PIN (GPIO_PIN_6) +#define PHB_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB_PORT GPIO_PORTC_BASE +#define PHB_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S818 @@ -3877,101 +3877,101 @@ //***************************************************************************** #ifdef PART_LM3S828 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSCL_PORT (GPIO_PORTB_BASE) -#define I2CSCL_PIN (GPIO_PIN_2) +#define I2CSCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSCL_PORT GPIO_PORTB_BASE +#define I2CSCL_PIN GPIO_PIN_2 -#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2CSDA_PORT (GPIO_PORTB_BASE) -#define I2CSDA_PIN (GPIO_PIN_3) +#define I2CSDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2CSDA_PORT GPIO_PORTB_BASE +#define I2CSDA_PIN GPIO_PIN_3 -#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSICLK_PORT (GPIO_PORTA_BASE) -#define SSICLK_PIN (GPIO_PIN_2) +#define SSICLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSICLK_PORT GPIO_PORTA_BASE +#define SSICLK_PIN GPIO_PIN_2 -#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIFSS_PORT (GPIO_PORTA_BASE) -#define SSIFSS_PIN (GPIO_PIN_3) +#define SSIFSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIFSS_PORT GPIO_PORTA_BASE +#define SSIFSS_PIN GPIO_PIN_3 -#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSIRX_PORT (GPIO_PORTA_BASE) -#define SSIRX_PIN (GPIO_PIN_4) +#define SSIRX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSIRX_PORT GPIO_PORTA_BASE +#define SSIRX_PIN GPIO_PIN_4 -#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSITX_PORT (GPIO_PORTA_BASE) -#define SSITX_PIN (GPIO_PIN_5) +#define SSITX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSITX_PORT GPIO_PORTA_BASE +#define SSITX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S828 @@ -3982,101 +3982,101 @@ //***************************************************************************** #ifdef PART_LM3S1110 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1110 @@ -4087,157 +4087,157 @@ //***************************************************************************** #ifdef PART_LM3S1133 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1133 @@ -4248,169 +4248,169 @@ //***************************************************************************** #ifdef PART_LM3S1138 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP3_PORT (GPIO_PORTG_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP4_PORT (GPIO_PORTF_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP4_PORT GPIO_PORTF_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1138 @@ -4421,197 +4421,197 @@ //***************************************************************************** #ifdef PART_LM3S1150 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1150 @@ -4622,185 +4622,185 @@ //***************************************************************************** #ifdef PART_LM3S1162 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1162 @@ -4811,173 +4811,173 @@ //***************************************************************************** #ifdef PART_LM3S1165 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP6_PORT (GPIO_PORTB_BASE) -#define CCP6_PIN (GPIO_PIN_5) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP6_PORT GPIO_PORTB_BASE +#define CCP6_PIN GPIO_PIN_5 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1165 @@ -4988,129 +4988,129 @@ //***************************************************************************** #ifdef PART_LM3S1332 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1332 @@ -5121,117 +5121,117 @@ //***************************************************************************** #ifdef PART_LM3S1435 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1435 @@ -5242,169 +5242,169 @@ //***************************************************************************** #ifdef PART_LM3S1439 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1439 @@ -5415,189 +5415,189 @@ //***************************************************************************** #ifdef PART_LM3S1512 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C2O_PORT (GPIO_PORTF_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOF +#define C2O_PORT GPIO_PORTF_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP4_PORT (GPIO_PORTD_BASE) -#define CCP4_PIN (GPIO_PIN_5) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP4_PORT GPIO_PORTD_BASE +#define CCP4_PIN GPIO_PIN_5 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1512 @@ -5608,153 +5608,153 @@ //***************************************************************************** #ifdef PART_LM3S1538 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1538 @@ -5765,165 +5765,165 @@ //***************************************************************************** #ifdef PART_LM3S1601 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1601 @@ -5934,149 +5934,149 @@ //***************************************************************************** #ifdef PART_LM3S1607 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_1) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_1 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_0) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_0 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_5) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_6) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U2RX_PORT (GPIO_PORTB_BASE) -#define U2RX_PIN (GPIO_PIN_4) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U2RX_PORT GPIO_PORTB_BASE +#define U2RX_PIN GPIO_PIN_4 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define U2TX_PORT (GPIO_PORTE_BASE) -#define U2TX_PIN (GPIO_PIN_4) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOE +#define U2TX_PORT GPIO_PORTE_BASE +#define U2TX_PIN GPIO_PIN_4 #endif // PART_LM3S1607 @@ -6087,157 +6087,157 @@ //***************************************************************************** #ifdef PART_LM3S1608 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1608 @@ -6248,184 +6248,430 @@ //***************************************************************************** #ifdef PART_LM3S1620 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1620 +//***************************************************************************** +// +// LM3S1621 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1621 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1621 + //***************************************************************************** // // LM3S1625 Port/Pin Mapping Definitions @@ -6433,149 +6679,149 @@ //***************************************************************************** #ifdef PART_LM3S1625 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_7) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S1625 @@ -6586,149 +6832,149 @@ //***************************************************************************** #ifdef PART_LM3S1626 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_6) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_5) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_5 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM0_PORT (GPIO_PORTA_BASE) -#define PWM0_PIN (GPIO_PIN_6) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM1_PORT (GPIO_PORTA_BASE) -#define PWM1_PIN (GPIO_PIN_7) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_4) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_4 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_5) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_5 #endif // PART_LM3S1626 @@ -6739,149 +6985,149 @@ //***************************************************************************** #ifdef PART_LM3S1627 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_6) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_5) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_5 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define IDX0_PORT (GPIO_PORTB_BASE) -#define IDX0_PIN (GPIO_PIN_4) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX0_PORT GPIO_PORTB_BASE +#define IDX0_PIN GPIO_PIN_4 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM2_PORT (GPIO_PORTD_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM3_PORT (GPIO_PORTD_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 #endif // PART_LM3S1627 @@ -6892,193 +7138,193 @@ //***************************************************************************** #ifdef PART_LM3S1635 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1635 @@ -7089,164 +7335,477 @@ //***************************************************************************** #ifdef PART_LM3S1637 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1637 +//***************************************************************************** +// +// LM3S1651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1651 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S1651 + //***************************************************************************** // // LM3S1751 Port/Pin Mapping Definitions @@ -7254,157 +7813,157 @@ //***************************************************************************** #ifdef PART_LM3S1751 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1751 @@ -7415,148 +7974,522 @@ //***************************************************************************** #ifdef PART_LM3S1776 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_7) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_5 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT1_PORT (GPIO_PORTB_BASE) -#define FAULT1_PIN (GPIO_PIN_6) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 -#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define FAULT2_PORT (GPIO_PORTC_BASE) -#define FAULT2_PIN (GPIO_PIN_5) +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOC +#define FAULT2_PORT GPIO_PORTC_BASE +#define FAULT2_PIN GPIO_PIN_5 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 -#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PWM6_PORT (GPIO_PORTC_BASE) -#define PWM6_PIN (GPIO_PIN_4) +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM6_PORT GPIO_PORTC_BASE +#define PWM6_PIN GPIO_PIN_4 -#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PWM7_PORT (GPIO_PORTC_BASE) -#define PWM7_PIN (GPIO_PIN_6) +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM7_PORT GPIO_PORTC_BASE +#define PWM7_PIN GPIO_PIN_6 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S1776 +//***************************************************************************** +// +// LM3S1811 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1811 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1811 + +//***************************************************************************** +// +// LM3S1816 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1816 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1816 + //***************************************************************************** // // LM3S1850 Port/Pin Mapping Definitions @@ -7564,173 +8497,173 @@ //***************************************************************************** #ifdef PART_LM3S1850 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1850 @@ -7741,165 +8674,165 @@ //***************************************************************************** #ifdef PART_LM3S1911 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1911 @@ -7910,157 +8843,157 @@ //***************************************************************************** #ifdef PART_LM3S1918 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1918 @@ -8071,133 +9004,133 @@ //***************************************************************************** #ifdef PART_LM3S1937 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S1937 @@ -8208,141 +9141,141 @@ //***************************************************************************** #ifdef PART_LM3S1958 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1958 @@ -8353,229 +9286,229 @@ //***************************************************************************** #ifdef PART_LM3S1960 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C2O_PORT (GPIO_PORTF_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOF +#define C2O_PORT GPIO_PORTF_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP4_PORT (GPIO_PORTF_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP4_PORT GPIO_PORTF_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH) -#define IDX1_PORT (GPIO_PORTH_BASE) -#define IDX1_PIN (GPIO_PIN_2) +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOH +#define IDX1_PORT GPIO_PORTH_BASE +#define IDX1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PHA1_PORT (GPIO_PORTG_BASE) -#define PHA1_PIN (GPIO_PIN_6) +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHA1_PORT GPIO_PORTG_BASE +#define PHA1_PIN GPIO_PIN_6 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PHB0_PORT (GPIO_PORTH_BASE) -#define PHB0_PIN (GPIO_PIN_3) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 -#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PHB1_PORT (GPIO_PORTG_BASE) -#define PHB1_PIN (GPIO_PIN_7) +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHB1_PORT GPIO_PORTG_BASE +#define PHB1_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1960 @@ -8586,208 +9519,4101 @@ //***************************************************************************** #ifdef PART_LM3S1968 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP3_PORT (GPIO_PORTG_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOH) -#define FAULT_PORT (GPIO_PORTH_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT_PORT GPIO_PORTH_BASE +#define FAULT_PIN GPIO_PIN_3 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define IDX1_PORT (GPIO_PORTF_BASE) -#define IDX1_PIN (GPIO_PIN_1) +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOF +#define IDX1_PORT GPIO_PORTF_BASE +#define IDX1_PIN GPIO_PIN_1 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PHA1_PORT (GPIO_PORTG_BASE) -#define PHA1_PIN (GPIO_PIN_6) +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHA1_PORT GPIO_PORTG_BASE +#define PHA1_PIN GPIO_PIN_6 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PHB1_PORT (GPIO_PORTG_BASE) -#define PHB1_PIN (GPIO_PIN_7) +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHB1_PORT GPIO_PORTG_BASE +#define PHB1_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM0_PORT (GPIO_PORTG_BASE) -#define PWM0_PIN (GPIO_PIN_2) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_2 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S1968 +//***************************************************************************** +// +// LM3S1B21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1B21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1B21 + +//***************************************************************************** +// +// LM3S1C21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1C21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1C21 + +//***************************************************************************** +// +// LM3S1C26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1C26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1C26 + +//***************************************************************************** +// +// LM3S1C58 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1C58 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 + +#define GPIO_PG5_CCP5 0x00061401 + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 + +#define GPIO_PH1_CCP7 0x00070401 + +#endif // PART_LM3S1C58 + +//***************************************************************************** +// +// LM3S1D21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1D21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1D21 + +//***************************************************************************** +// +// LM3S1D26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1D26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1D26 + +//***************************************************************************** +// +// LM3S1F11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1F11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1F11 + +//***************************************************************************** +// +// LM3S1F16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1F16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1F16 + +//***************************************************************************** +// +// LM3S1G21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1G21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1G21 + +//***************************************************************************** +// +// LM3S1G58 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1G58 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 + +#define GPIO_PG5_CCP5 0x00061401 + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 + +#define GPIO_PH1_CCP7 0x00070401 + +#endif // PART_LM3S1G58 + +//***************************************************************************** +// +// LM3S1H11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1H11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1H11 + +//***************************************************************************** +// +// LM3S1H16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1H16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1H16 + +//***************************************************************************** +// +// LM3S1J11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1J11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH2_C1O 0x00070802 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1J11 + +//***************************************************************************** +// +// LM3S1J16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1J16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1J16 + +//***************************************************************************** +// +// LM3S1N11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1N11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH2_C1O 0x00070802 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1N11 + +//***************************************************************************** +// +// LM3S1N16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1N16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1N16 + +//***************************************************************************** +// +// LM3S1P51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1P51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S1P51 + +//***************************************************************************** +// +// LM3S1R21 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1R21 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_EPI0S12 0x00051C08 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S1R21 + +//***************************************************************************** +// +// LM3S1R26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1R26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1R26 + +//***************************************************************************** +// +// LM3S1W16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1W16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1W16 + +//***************************************************************************** +// +// LM3S1Z16 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1Z16 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S1Z16 + //***************************************************************************** // // LM3S2016 Port/Pin Mapping Definitions @@ -8795,101 +13621,101 @@ //***************************************************************************** #ifdef PART_LM3S2016 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2016 @@ -8900,133 +13726,133 @@ //***************************************************************************** #ifdef PART_LM3S2110 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2110 @@ -9037,137 +13863,137 @@ //***************************************************************************** #ifdef PART_LM3S2139 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2139 @@ -9178,149 +14004,149 @@ //***************************************************************************** #ifdef PART_LM3S2276 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0RX_PORT (GPIO_PORTB_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0TX_PORT (GPIO_PORTB_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_7) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT1_PORT (GPIO_PORTB_BASE) -#define FAULT1_PIN (GPIO_PIN_6) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 -#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define FAULT2_PORT (GPIO_PORTC_BASE) -#define FAULT2_PIN (GPIO_PIN_5) +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOC +#define FAULT2_PORT GPIO_PORTC_BASE +#define FAULT2_PIN GPIO_PIN_5 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 -#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PWM6_PORT (GPIO_PORTC_BASE) -#define PWM6_PIN (GPIO_PIN_4) +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM6_PORT GPIO_PORTC_BASE +#define PWM6_PIN GPIO_PIN_4 -#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PWM7_PORT (GPIO_PORTC_BASE) -#define PWM7_PIN (GPIO_PIN_6) +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM7_PORT GPIO_PORTC_BASE +#define PWM7_PIN GPIO_PIN_6 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2276 @@ -9331,109 +14157,109 @@ //***************************************************************************** #ifdef PART_LM3S2410 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2410 @@ -9444,133 +14270,133 @@ //***************************************************************************** #ifdef PART_LM3S2412 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2412 @@ -9581,133 +14407,133 @@ //***************************************************************************** #ifdef PART_LM3S2432 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2432 @@ -9718,165 +14544,165 @@ //***************************************************************************** #ifdef PART_LM3S2533 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2533 @@ -9887,173 +14713,173 @@ //***************************************************************************** #ifdef PART_LM3S2601 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2601 @@ -10064,165 +14890,165 @@ //***************************************************************************** #ifdef PART_LM3S2608 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2608 @@ -10233,149 +15059,149 @@ //***************************************************************************** #ifdef PART_LM3S2616 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_7) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_7 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_7) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_7 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CAN0RX_PORT (GPIO_PORTA_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0RX_PORT GPIO_PORTA_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CAN0TX_PORT (GPIO_PORTA_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0TX_PORT GPIO_PORTA_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_6) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM0_PORT (GPIO_PORTA_BASE) -#define PWM0_PIN (GPIO_PIN_6) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM1_PORT (GPIO_PORTA_BASE) -#define PWM1_PIN (GPIO_PIN_7) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2616 @@ -10386,177 +15212,177 @@ //***************************************************************************** #ifdef PART_LM3S2620 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C2O_PORT (GPIO_PORTE_BASE) -#define C2O_PIN (GPIO_PIN_7) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOE +#define C2O_PORT GPIO_PORTE_BASE +#define C2O_PIN GPIO_PIN_7 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PHB0_PORT (GPIO_PORTH_BASE) -#define PHB0_PIN (GPIO_PIN_3) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM0_PORT (GPIO_PORTG_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM1_PORT (GPIO_PORTG_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM2_PORT (GPIO_PORTD_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM3_PORT (GPIO_PORTD_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2620 @@ -10567,141 +15393,141 @@ //***************************************************************************** #ifdef PART_LM3S2637 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2637 @@ -10712,165 +15538,165 @@ //***************************************************************************** #ifdef PART_LM3S2651 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2651 @@ -10881,149 +15707,149 @@ //***************************************************************************** #ifdef PART_LM3S2671 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_7) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_7 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_7) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_7 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_5) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_5 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_1) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_1 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM0_PORT (GPIO_PORTA_BASE) -#define PWM0_PIN (GPIO_PIN_6) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM1_PORT (GPIO_PORTA_BASE) -#define PWM1_PIN (GPIO_PIN_7) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2671 @@ -11034,145 +15860,145 @@ //***************************************************************************** #ifdef PART_LM3S2678 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_1) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_1 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_0) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_0 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0RX_PORT (GPIO_PORTB_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0TX_PORT (GPIO_PORTB_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_6) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP1_PORT (GPIO_PORTC_BASE) -#define CCP1_PIN (GPIO_PIN_5) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP1_PORT GPIO_PORTC_BASE +#define CCP1_PIN GPIO_PIN_5 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT0_PORT (GPIO_PORTB_BASE) -#define FAULT0_PIN (GPIO_PIN_3) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT0_PORT GPIO_PORTB_BASE +#define FAULT0_PIN GPIO_PIN_3 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT1_PORT (GPIO_PORTB_BASE) -#define FAULT1_PIN (GPIO_PIN_6) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define IDX0_PORT (GPIO_PORTB_BASE) -#define IDX0_PIN (GPIO_PIN_2) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX0_PORT GPIO_PORTB_BASE +#define IDX0_PIN GPIO_PIN_2 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM0_PORT (GPIO_PORTA_BASE) -#define PWM0_PIN (GPIO_PIN_6) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM0_PORT GPIO_PORTA_BASE +#define PWM0_PIN GPIO_PIN_6 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM1_PORT (GPIO_PORTA_BASE) -#define PWM1_PIN (GPIO_PIN_7) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM1_PORT GPIO_PORTA_BASE +#define PWM1_PIN GPIO_PIN_7 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2678 @@ -11183,109 +16009,109 @@ //***************************************************************************** #ifdef PART_LM3S2730 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2730 @@ -11296,161 +16122,161 @@ //***************************************************************************** #ifdef PART_LM3S2739 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2739 @@ -11461,152 +16287,520 @@ //***************************************************************************** #ifdef PART_LM3S2776 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0RX_PORT (GPIO_PORTB_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0TX_PORT (GPIO_PORTB_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_7) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_7 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT1_PORT (GPIO_PORTB_BASE) -#define FAULT1_PIN (GPIO_PIN_6) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT1_PORT GPIO_PORTB_BASE +#define FAULT1_PIN GPIO_PIN_6 -#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define FAULT2_PORT (GPIO_PORTC_BASE) -#define FAULT2_PIN (GPIO_PIN_5) +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOC +#define FAULT2_PORT GPIO_PORTC_BASE +#define FAULT2_PIN GPIO_PIN_5 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 -#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PWM6_PORT (GPIO_PORTC_BASE) -#define PWM6_PIN (GPIO_PIN_4) +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM6_PORT GPIO_PORTC_BASE +#define PWM6_PIN GPIO_PIN_4 -#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PWM7_PORT (GPIO_PORTC_BASE) -#define PWM7_PIN (GPIO_PIN_6) +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOC +#define PWM7_PORT GPIO_PORTC_BASE +#define PWM7_PIN GPIO_PIN_6 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S2776 +//***************************************************************************** +// +// LM3S2793 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2793 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2793 + //***************************************************************************** // // LM3S2911 Port/Pin Mapping Definitions @@ -11614,173 +16808,173 @@ //***************************************************************************** #ifdef PART_LM3S2911 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2911 @@ -11791,165 +16985,165 @@ //***************************************************************************** #ifdef PART_LM3S2918 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S2918 @@ -11960,173 +17154,173 @@ //***************************************************************************** #ifdef PART_LM3S2939 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PHB0_PORT (GPIO_PORTH_BASE) -#define PHB0_PIN (GPIO_PIN_3) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2939 @@ -12137,177 +17331,177 @@ //***************************************************************************** #ifdef PART_LM3S2948 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP3_PORT (GPIO_PORTG_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2948 @@ -12318,217 +17512,217 @@ //***************************************************************************** #ifdef PART_LM3S2950 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C2O_PORT (GPIO_PORTF_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOF +#define C2O_PORT GPIO_PORTF_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP5_PORT (GPIO_PORTE_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP5_PORT GPIO_PORTE_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PHB0_PORT (GPIO_PORTH_BASE) -#define PHB0_PIN (GPIO_PIN_3) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM0_PORT (GPIO_PORTG_BASE) -#define PWM0_PIN (GPIO_PIN_2) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_2 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM1_PORT (GPIO_PORTG_BASE) -#define PWM1_PIN (GPIO_PIN_3) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_3 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2950 @@ -12539,232 +17733,1485 @@ //***************************************************************************** #ifdef PART_LM3S2965 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP4_PORT (GPIO_PORTD_BASE) -#define CCP4_PIN (GPIO_PIN_5) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP4_PORT GPIO_PORTD_BASE +#define CCP4_PIN GPIO_PIN_5 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP5_PORT (GPIO_PORTG_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP5_PORT GPIO_PORTG_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH) -#define IDX1_PORT (GPIO_PORTH_BASE) -#define IDX1_PIN (GPIO_PIN_2) +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOH +#define IDX1_PORT GPIO_PORTH_BASE +#define IDX1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PHA1_PORT (GPIO_PORTG_BASE) -#define PHA1_PIN (GPIO_PIN_6) +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHA1_PORT GPIO_PORTG_BASE +#define PHA1_PIN GPIO_PIN_6 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PHB0_PORT (GPIO_PORTH_BASE) -#define PHB0_PIN (GPIO_PIN_3) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOH +#define PHB0_PORT GPIO_PORTH_BASE +#define PHB0_PIN GPIO_PIN_3 -#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PHB1_PORT (GPIO_PORTG_BASE) -#define PHB1_PIN (GPIO_PIN_7) +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOG +#define PHB1_PORT GPIO_PORTG_BASE +#define PHB1_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM0_PORT (GPIO_PORTG_BASE) -#define PWM0_PIN (GPIO_PIN_2) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_2 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM1_PORT (GPIO_PORTG_BASE) -#define PWM1_PIN (GPIO_PIN_3) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_3 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S2965 +//***************************************************************************** +// +// LM3S2B93 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2B93 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2B93 + +//***************************************************************************** +// +// LM3S2D93 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2D93 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2D93 + +//***************************************************************************** +// +// LM3S2U93 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2U93 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S2U93 + +//***************************************************************************** +// +// LM3S3634 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3634 + +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 + +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 + +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 + +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 + +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 + +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 + +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_1 + +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_0 + +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 + +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 + +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 + +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 + +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 + +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 + +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 + +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 + +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 + +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 + +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 + +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 + +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 + +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 + +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 + +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 + +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 + +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 + +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 + +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 + +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 + +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 + +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 + +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 + +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 + +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 + +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 + +#endif // PART_LM3S3634 + //***************************************************************************** // // LM3S3651 Port/Pin Mapping Definitions @@ -12772,156 +19219,267 @@ //***************************************************************************** #ifdef PART_LM3S3651 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_7) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_7 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_3) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_3 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP5_PORT (GPIO_PORTD_BASE) -#define CCP5_PIN (GPIO_PIN_2) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP6_PORT (GPIO_PORTD_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP6_PORT GPIO_PORTD_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP7_PORT (GPIO_PORTD_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP7_PORT GPIO_PORTD_BASE +#define CCP7_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0ID_PORT (GPIO_PORTB_BASE) -#define USB0ID_PIN (GPIO_PIN_0) +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 -#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0VBUS_PORT (GPIO_PORTB_BASE) -#define USB0VBUS_PIN (GPIO_PIN_1) +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 #endif // PART_LM3S3651 +//***************************************************************************** +// +// LM3S3654 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3654 + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3654 + //***************************************************************************** // // LM3S3739 Port/Pin Mapping Definitions @@ -12929,205 +19487,205 @@ //***************************************************************************** #ifdef PART_LM3S3739 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_6) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP3_PORT (GPIO_PORTG_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP5_PORT (GPIO_PORTD_BASE) -#define CCP5_PIN (GPIO_PIN_2) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP7_PORT (GPIO_PORTD_BASE) -#define CCP7_PIN (GPIO_PIN_3) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP7_PORT GPIO_PORTD_BASE +#define CCP7_PIN GPIO_PIN_3 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U2RX_PORT (GPIO_PORTD_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2RX_PORT GPIO_PORTD_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U2TX_PORT (GPIO_PORTD_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2TX_PORT GPIO_PORTD_BASE +#define U2TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0EPEN_PORT (GPIO_PORTH_BASE) -#define USB0EPEN_PIN (GPIO_PIN_3) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0PFLT_PORT (GPIO_PORTH_BASE) -#define USB0PFLT_PIN (GPIO_PIN_4) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 #endif // PART_LM3S3739 @@ -13138,249 +19696,249 @@ //***************************************************************************** #ifdef PART_LM3S3748 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_3) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_3 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP2_PORT (GPIO_PORTF_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP2_PORT GPIO_PORTF_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP3_PORT (GPIO_PORTG_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_4) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_4 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP5_PORT (GPIO_PORTD_BASE) -#define CCP5_PIN (GPIO_PIN_2) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP7_PORT (GPIO_PORTH_BASE) -#define CCP7_PIN (GPIO_PIN_1) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP7_PORT GPIO_PORTH_BASE +#define CCP7_PIN GPIO_PIN_1 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define FAULT0_PORT (GPIO_PORTF_BASE) -#define FAULT0_PIN (GPIO_PIN_4) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOF +#define FAULT0_PORT GPIO_PORTF_BASE +#define FAULT0_PIN GPIO_PIN_4 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT1_PORT (GPIO_PORTG_BASE) -#define FAULT1_PIN (GPIO_PIN_5) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT1_PORT GPIO_PORTG_BASE +#define FAULT1_PIN GPIO_PIN_5 -#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT2_PORT (GPIO_PORTG_BASE) -#define FAULT2_PIN (GPIO_PIN_3) +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT2_PORT GPIO_PORTG_BASE +#define FAULT2_PIN GPIO_PIN_3 -#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define FAULT3_PORT (GPIO_PORTH_BASE) -#define FAULT3_PIN (GPIO_PIN_2) +#define FAULT3_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT3_PORT GPIO_PORTH_BASE +#define FAULT3_PIN GPIO_PIN_2 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM2_PORT (GPIO_PORTF_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM2_PORT GPIO_PORTF_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM3_PORT (GPIO_PORTF_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM3_PORT GPIO_PORTF_BASE +#define PWM3_PIN GPIO_PIN_3 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM4_PORT (GPIO_PORTG_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM4_PORT GPIO_PORTG_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM5_PORT (GPIO_PORTG_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM5_PORT GPIO_PORTG_BASE +#define PWM5_PIN GPIO_PIN_1 -#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM6_PORT (GPIO_PORTG_BASE) -#define PWM6_PIN (GPIO_PIN_6) +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM6_PORT GPIO_PORTG_BASE +#define PWM6_PIN GPIO_PIN_6 -#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM7_PORT (GPIO_PORTG_BASE) -#define PWM7_PIN (GPIO_PIN_7) +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM7_PORT GPIO_PORTG_BASE +#define PWM7_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOC) -#define U1RX_PORT (GPIO_PORTC_BASE) -#define U1RX_PIN (GPIO_PIN_6) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOC +#define U1RX_PORT GPIO_PORTC_BASE +#define U1RX_PIN GPIO_PIN_6 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOC) -#define U1TX_PORT (GPIO_PORTC_BASE) -#define U1TX_PIN (GPIO_PIN_7) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOC +#define U1TX_PORT GPIO_PORTC_BASE +#define U1TX_PIN GPIO_PIN_7 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0EPEN_PORT (GPIO_PORTH_BASE) -#define USB0EPEN_PIN (GPIO_PIN_3) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0PFLT_PORT (GPIO_PORTH_BASE) -#define USB0PFLT_PIN (GPIO_PIN_4) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 #endif // PART_LM3S3748 @@ -13391,264 +19949,864 @@ //***************************************************************************** #ifdef PART_LM3S3749 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_7) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_7 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_3) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_3 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP2_PORT (GPIO_PORTF_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP2_PORT GPIO_PORTF_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP3_PORT (GPIO_PORTA_BASE) -#define CCP3_PIN (GPIO_PIN_7) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP3_PORT GPIO_PORTA_BASE +#define CCP3_PIN GPIO_PIN_7 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP4_PORT (GPIO_PORTF_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP4_PORT GPIO_PORTF_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP6_PORT (GPIO_PORTD_BASE) -#define CCP6_PIN (GPIO_PIN_2) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP6_PORT GPIO_PORTD_BASE +#define CCP6_PIN GPIO_PIN_2 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT0_PORT (GPIO_PORTG_BASE) -#define FAULT0_PIN (GPIO_PIN_2) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT0_PORT GPIO_PORTG_BASE +#define FAULT0_PIN GPIO_PIN_2 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT1_PORT (GPIO_PORTG_BASE) -#define FAULT1_PIN (GPIO_PIN_4) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT1_PORT GPIO_PORTG_BASE +#define FAULT1_PIN GPIO_PIN_4 -#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT2_PORT (GPIO_PORTG_BASE) -#define FAULT2_PIN (GPIO_PIN_3) +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT2_PORT GPIO_PORTG_BASE +#define FAULT2_PIN GPIO_PIN_3 -#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define FAULT3_PORT (GPIO_PORTH_BASE) -#define FAULT3_PIN (GPIO_PIN_2) +#define FAULT3_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT3_PORT GPIO_PORTH_BASE +#define FAULT3_PIN GPIO_PIN_2 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) -#define I2C1SCL_PORT (GPIO_PORTG_BASE) -#define I2C1SCL_PIN (GPIO_PIN_0) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG) -#define I2C1SDA_PORT (GPIO_PORTG_BASE) -#define I2C1SDA_PIN (GPIO_PIN_1) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SDA_PORT GPIO_PORTG_BASE +#define I2C1SDA_PIN GPIO_PIN_1 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define IDX0_PORT (GPIO_PORTG_BASE) -#define IDX0_PIN (GPIO_PIN_5) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOG +#define IDX0_PORT GPIO_PORTG_BASE +#define IDX0_PIN GPIO_PIN_5 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHA0_PORT (GPIO_PORTF_BASE) -#define PHA0_PIN (GPIO_PIN_6) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHA0_PORT GPIO_PORTF_BASE +#define PHA0_PIN GPIO_PIN_6 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_6) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_6 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM6_PORT (GPIO_PORTG_BASE) -#define PWM6_PIN (GPIO_PIN_6) +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM6_PORT GPIO_PORTG_BASE +#define PWM6_PIN GPIO_PIN_6 -#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM7_PORT (GPIO_PORTG_BASE) -#define PWM7_PIN (GPIO_PIN_7) +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM7_PORT GPIO_PORTG_BASE +#define PWM7_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U2RX_PORT (GPIO_PORTD_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2RX_PORT GPIO_PORTD_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U2TX_PORT (GPIO_PORTD_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2TX_PORT GPIO_PORTD_BASE +#define U2TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0EPEN_PORT (GPIO_PORTH_BASE) -#define USB0EPEN_PIN (GPIO_PIN_3) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0PFLT_PORT (GPIO_PORTH_BASE) -#define USB0PFLT_PIN (GPIO_PIN_4) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 #endif // PART_LM3S3749 +//***************************************************************************** +// +// LM3S3826 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3826 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3826 + +//***************************************************************************** +// +// LM3S3J26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3J26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3J26 + +//***************************************************************************** +// +// LM3S3N26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3N26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3N26 + +//***************************************************************************** +// +// LM3S3W26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3W26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3W26 + +//***************************************************************************** +// +// LM3S3Z26 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3Z26 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S3Z26 + //***************************************************************************** // // LM3S5632 Port/Pin Mapping Definitions @@ -13656,148 +20814,483 @@ //***************************************************************************** #ifdef PART_LM3S5632 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_5) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 #endif // PART_LM3S5632 +//***************************************************************************** +// +// LM3S5651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5651 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5651 + //***************************************************************************** // // LM3S5652 Port/Pin Mapping Definitions @@ -13805,152 +21298,326 @@ //***************************************************************************** #ifdef PART_LM3S5652 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_5) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP2_PORT (GPIO_PORTE_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP2_PORT GPIO_PORTE_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP3_PORT (GPIO_PORTA_BASE) -#define CCP3_PIN (GPIO_PIN_7) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP3_PORT GPIO_PORTA_BASE +#define CCP3_PIN GPIO_PIN_7 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0ID_PORT (GPIO_PORTB_BASE) -#define USB0ID_PIN (GPIO_PIN_0) +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 -#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0VBUS_PORT (GPIO_PORTB_BASE) -#define USB0VBUS_PIN (GPIO_PIN_1) +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 #endif // PART_LM3S5652 +//***************************************************************************** +// +// LM3S5656 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5656 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5656 + //***************************************************************************** // // LM3S5662 Port/Pin Mapping Definitions @@ -13958,149 +21625,149 @@ //***************************************************************************** #ifdef PART_LM3S5662 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0RX_PORT (GPIO_PORTB_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0TX_PORT (GPIO_PORTB_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_2) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_2 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT0_PORT (GPIO_PORTB_BASE) -#define FAULT0_PIN (GPIO_PIN_3) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT0_PORT GPIO_PORTB_BASE +#define FAULT0_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM2_PORT (GPIO_PORTD_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM3_PORT (GPIO_PORTD_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0ID_PORT (GPIO_PORTB_BASE) -#define USB0ID_PIN (GPIO_PIN_0) +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 -#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0VBUS_PORT (GPIO_PORTB_BASE) -#define USB0VBUS_PIN (GPIO_PIN_1) +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 #endif // PART_LM3S5662 @@ -14111,145 +21778,145 @@ //***************************************************************************** #ifdef PART_LM3S5732 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_5) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 #endif // PART_LM3S5732 @@ -14260,153 +21927,153 @@ //***************************************************************************** #ifdef PART_LM3S5737 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_1) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_1 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_5 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 #endif // PART_LM3S5737 @@ -14417,213 +22084,213 @@ //***************************************************************************** #ifdef PART_LM3S5739 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CAN0RX_PORT (GPIO_PORTA_BASE) -#define CAN0RX_PIN (GPIO_PIN_6) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0RX_PORT GPIO_PORTA_BASE +#define CAN0RX_PIN GPIO_PIN_6 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CAN0TX_PORT (GPIO_PORTA_BASE) -#define CAN0TX_PIN (GPIO_PIN_7) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define CAN0TX_PORT GPIO_PORTA_BASE +#define CAN0TX_PIN GPIO_PIN_7 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP0_PORT (GPIO_PORTC_BASE) -#define CCP0_PIN (GPIO_PIN_6) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP0_PORT GPIO_PORTC_BASE +#define CCP0_PIN GPIO_PIN_6 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CCP1_PORT (GPIO_PORTF_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOF +#define CCP1_PORT GPIO_PORTF_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) -#define CCP3_PORT (GPIO_PORTG_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOG +#define CCP3_PORT GPIO_PORTG_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP5_PORT (GPIO_PORTD_BASE) -#define CCP5_PIN (GPIO_PIN_2) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP5_PORT GPIO_PORTD_BASE +#define CCP5_PIN GPIO_PIN_2 -#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) -#define CCP6_PORT (GPIO_PORTH_BASE) -#define CCP6_PIN (GPIO_PIN_0) +#define CCP6_PERIPH SYSCTL_PERIPH_GPIOH +#define CCP6_PORT GPIO_PORTH_BASE +#define CCP6_PIN GPIO_PIN_0 -#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP7_PORT (GPIO_PORTD_BASE) -#define CCP7_PIN (GPIO_PIN_3) +#define CCP7_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP7_PORT GPIO_PORTD_BASE +#define CCP7_PIN GPIO_PIN_3 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) -#define I2C1SCL_PORT (GPIO_PORTG_BASE) -#define I2C1SCL_PIN (GPIO_PIN_0) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG) -#define I2C1SDA_PORT (GPIO_PORTG_BASE) -#define I2C1SDA_PIN (GPIO_PIN_1) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SDA_PORT GPIO_PORTG_BASE +#define I2C1SDA_PIN GPIO_PIN_1 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1RX_PORT (GPIO_PORTB_BASE) -#define U1RX_PIN (GPIO_PIN_0) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1RX_PORT GPIO_PORTB_BASE +#define U1RX_PIN GPIO_PIN_0 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define U1TX_PORT (GPIO_PORTB_BASE) -#define U1TX_PIN (GPIO_PIN_1) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOB +#define U1TX_PORT GPIO_PORTB_BASE +#define U1TX_PIN GPIO_PIN_1 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U2RX_PORT (GPIO_PORTD_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2RX_PORT GPIO_PORTD_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U2TX_PORT (GPIO_PORTD_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U2TX_PORT GPIO_PORTD_BASE +#define U2TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0EPEN_PORT (GPIO_PORTH_BASE) -#define USB0EPEN_PIN (GPIO_PIN_3) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0PFLT_PORT (GPIO_PORTH_BASE) -#define USB0PFLT_PIN (GPIO_PIN_4) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 #endif // PART_LM3S5739 @@ -14634,153 +22301,153 @@ //***************************************************************************** #ifdef PART_LM3S5747 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0RX_PORT (GPIO_PORTB_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0TX_PORT (GPIO_PORTB_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT0_PORT (GPIO_PORTE_BASE) -#define FAULT0_PIN (GPIO_PIN_1) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT0_PORT GPIO_PORTE_BASE +#define FAULT0_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM2_PORT (GPIO_PORTD_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM3_PORT (GPIO_PORTD_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 #endif // PART_LM3S5747 @@ -14791,261 +22458,261 @@ //***************************************************************************** #ifdef PART_LM3S5749 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_7) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_7 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_6) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_6 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_5) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_5 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_4) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_4 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_7) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_7 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_6) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_6 -#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC6_PORT (GPIO_PORTD_BASE) -#define ADC6_PIN (GPIO_PIN_5) +#define ADC6_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC6_PORT GPIO_PORTD_BASE +#define ADC6_PIN GPIO_PIN_5 -#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC7_PORT (GPIO_PORTD_BASE) -#define ADC7_PIN (GPIO_PIN_4) +#define ADC7_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC7_PORT GPIO_PORTD_BASE +#define ADC7_PIN GPIO_PIN_4 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C0O_PORT (GPIO_PORTF_BASE) -#define C0O_PIN (GPIO_PIN_4) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOF +#define C0O_PORT GPIO_PORTF_BASE +#define C0O_PIN GPIO_PIN_4 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) -#define C1O_PORT (GPIO_PORTF_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOF +#define C1O_PORT GPIO_PORTF_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_1) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_1 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT0_PORT (GPIO_PORTG_BASE) -#define FAULT0_PIN (GPIO_PIN_2) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT0_PORT GPIO_PORTG_BASE +#define FAULT0_PIN GPIO_PIN_2 -#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT1_PORT (GPIO_PORTG_BASE) -#define FAULT1_PIN (GPIO_PIN_4) +#define FAULT1_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT1_PORT GPIO_PORTG_BASE +#define FAULT1_PIN GPIO_PIN_4 -#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG) -#define FAULT2_PORT (GPIO_PORTG_BASE) -#define FAULT2_PIN (GPIO_PIN_3) +#define FAULT2_PERIPH SYSCTL_PERIPH_GPIOG +#define FAULT2_PORT GPIO_PORTG_BASE +#define FAULT2_PIN GPIO_PIN_3 -#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define FAULT3_PORT (GPIO_PORTH_BASE) -#define FAULT3_PIN (GPIO_PIN_2) +#define FAULT3_PERIPH SYSCTL_PERIPH_GPIOH +#define FAULT3_PORT GPIO_PORTH_BASE +#define FAULT3_PIN GPIO_PIN_2 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define IDX0_PORT (GPIO_PORTG_BASE) -#define IDX0_PIN (GPIO_PIN_5) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOG +#define IDX0_PORT GPIO_PORTG_BASE +#define IDX0_PIN GPIO_PIN_5 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHA0_PORT (GPIO_PORTF_BASE) -#define PHA0_PIN (GPIO_PIN_6) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHA0_PORT GPIO_PORTF_BASE +#define PHA0_PIN GPIO_PIN_6 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM0_PORT (GPIO_PORTG_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM0_PORT GPIO_PORTG_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM1_PORT (GPIO_PORTG_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM2_PORT (GPIO_PORTH_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM2_PORT GPIO_PORTH_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) -#define PWM3_PORT (GPIO_PORTH_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOH +#define PWM3_PORT GPIO_PORTH_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM4_PORT (GPIO_PORTF_BASE) -#define PWM4_PIN (GPIO_PIN_2) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM4_PORT GPIO_PORTF_BASE +#define PWM4_PIN GPIO_PIN_2 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM5_PORT (GPIO_PORTF_BASE) -#define PWM5_PIN (GPIO_PIN_3) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM5_PORT GPIO_PORTF_BASE +#define PWM5_PIN GPIO_PIN_3 -#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM6_PORT (GPIO_PORTG_BASE) -#define PWM6_PIN (GPIO_PIN_6) +#define PWM6_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM6_PORT GPIO_PORTG_BASE +#define PWM6_PIN GPIO_PIN_6 -#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM7_PORT (GPIO_PORTG_BASE) -#define PWM7_PIN (GPIO_PIN_7) +#define PWM7_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM7_PORT GPIO_PORTG_BASE +#define PWM7_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0EPEN_PORT (GPIO_PORTH_BASE) -#define USB0EPEN_PIN (GPIO_PIN_3) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0EPEN_PORT GPIO_PORTH_BASE +#define USB0EPEN_PIN GPIO_PIN_3 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) -#define USB0PFLT_PORT (GPIO_PORTH_BASE) -#define USB0PFLT_PIN (GPIO_PIN_4) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOH +#define USB0PFLT_PORT GPIO_PORTH_BASE +#define USB0PFLT_PIN GPIO_PIN_4 #endif // PART_LM3S5749 @@ -15056,149 +22723,149 @@ //***************************************************************************** #ifdef PART_LM3S5752 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC4_PORT (GPIO_PORTD_BASE) -#define ADC4_PIN (GPIO_PIN_3) +#define ADC4_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC4_PORT GPIO_PORTD_BASE +#define ADC4_PIN GPIO_PIN_3 -#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) -#define ADC5_PORT (GPIO_PORTD_BASE) -#define ADC5_PIN (GPIO_PIN_2) +#define ADC5_PERIPH SYSCTL_PERIPH_GPIOD +#define ADC5_PORT GPIO_PORTD_BASE +#define ADC5_PIN GPIO_PIN_2 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_5) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_5 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP2_PORT (GPIO_PORTE_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP2_PORT GPIO_PORTE_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP3_PORT (GPIO_PORTA_BASE) -#define CCP3_PIN (GPIO_PIN_7) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP3_PORT GPIO_PORTA_BASE +#define CCP3_PIN GPIO_PIN_7 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0ID_PORT (GPIO_PORTB_BASE) -#define USB0ID_PIN (GPIO_PIN_0) +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 -#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0VBUS_PORT (GPIO_PORTB_BASE) -#define USB0VBUS_PIN (GPIO_PIN_1) +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 #endif // PART_LM3S5752 @@ -15209,152 +22876,7341 @@ //***************************************************************************** #ifdef PART_LM3S5762 -#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC0_PORT (GPIO_PORTE_BASE) -#define ADC0_PIN (GPIO_PIN_3) +#define ADC0_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC0_PORT GPIO_PORTE_BASE +#define ADC0_PIN GPIO_PIN_3 -#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC1_PORT (GPIO_PORTE_BASE) -#define ADC1_PIN (GPIO_PIN_2) +#define ADC1_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC1_PORT GPIO_PORTE_BASE +#define ADC1_PIN GPIO_PIN_2 -#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC2_PORT (GPIO_PORTE_BASE) -#define ADC2_PIN (GPIO_PIN_1) +#define ADC2_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC2_PORT GPIO_PORTE_BASE +#define ADC2_PIN GPIO_PIN_1 -#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define ADC3_PORT (GPIO_PORTE_BASE) -#define ADC3_PIN (GPIO_PIN_0) +#define ADC3_PERIPH SYSCTL_PERIPH_GPIOE +#define ADC3_PORT GPIO_PORTE_BASE +#define ADC3_PIN GPIO_PIN_0 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0RX_PORT (GPIO_PORTB_BASE) -#define CAN0RX_PIN (GPIO_PIN_4) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0RX_PORT GPIO_PORTB_BASE +#define CAN0RX_PIN GPIO_PIN_4 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CAN0TX_PORT (GPIO_PORTB_BASE) -#define CAN0TX_PIN (GPIO_PIN_5) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOB +#define CAN0TX_PORT GPIO_PORTB_BASE +#define CAN0TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_2) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_2 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP1_PORT (GPIO_PORTB_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP1_PORT GPIO_PORTB_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP2_PORT (GPIO_PORTC_BASE) -#define CCP2_PIN (GPIO_PIN_4) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP2_PORT GPIO_PORTC_BASE +#define CCP2_PIN GPIO_PIN_4 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT0_PORT (GPIO_PORTB_BASE) -#define FAULT0_PIN (GPIO_PIN_3) +#define FAULT0_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT0_PORT GPIO_PORTB_BASE +#define FAULT0_PIN GPIO_PIN_3 -#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) -#define NMI_PORT (GPIO_PORTB_BASE) -#define NMI_PIN (GPIO_PIN_7) +#define NMI_PERIPH SYSCTL_PERIPH_GPIOB +#define NMI_PORT GPIO_PORTB_BASE +#define NMI_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM2_PORT (GPIO_PORTD_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM3_PORT (GPIO_PORTD_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM4_PORT (GPIO_PORTA_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM4_PORT GPIO_PORTA_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) -#define PWM5_PORT (GPIO_PORTA_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOA +#define PWM5_PORT GPIO_PORTA_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0EPEN_PORT (GPIO_PORTC_BASE) -#define USB0EPEN_PIN (GPIO_PIN_5) +#define USB0EPEN_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0EPEN_PORT GPIO_PORTC_BASE +#define USB0EPEN_PIN GPIO_PIN_5 -#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0ID_PORT (GPIO_PORTB_BASE) -#define USB0ID_PIN (GPIO_PIN_0) +#define USB0ID_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0ID_PORT GPIO_PORTB_BASE +#define USB0ID_PIN GPIO_PIN_0 -#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) -#define USB0PFLT_PORT (GPIO_PORTC_BASE) -#define USB0PFLT_PIN (GPIO_PIN_6) +#define USB0PFLT_PERIPH SYSCTL_PERIPH_GPIOC +#define USB0PFLT_PORT GPIO_PORTC_BASE +#define USB0PFLT_PIN GPIO_PIN_6 -#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define USB0VBUS_PORT (GPIO_PORTB_BASE) -#define USB0VBUS_PIN (GPIO_PIN_1) +#define USB0VBUS_PERIPH SYSCTL_PERIPH_GPIOB +#define USB0VBUS_PORT GPIO_PORTB_BASE +#define USB0VBUS_PIN GPIO_PIN_1 #endif // PART_LM3S5762 +//***************************************************************************** +// +// LM3S5791 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5791 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5791 + +//***************************************************************************** +// +// LM3S5951 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5951 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5951 + +//***************************************************************************** +// +// LM3S5956 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5956 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5956 + +//***************************************************************************** +// +// LM3S5B91 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5B91 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5B91 + +//***************************************************************************** +// +// LM3S5C31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5C31 + +//***************************************************************************** +// +// LM3S5C36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5C36 + +//***************************************************************************** +// +// LM3S5C51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5C51 + +//***************************************************************************** +// +// LM3S5C56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5C56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5C56 + +//***************************************************************************** +// +// LM3S5D51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5D51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5D51 + +//***************************************************************************** +// +// LM3S5D56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5D56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5D56 + +//***************************************************************************** +// +// LM3S5D91 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5D91 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5D91 + +//***************************************************************************** +// +// LM3S5G31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5G31 + +//***************************************************************************** +// +// LM3S5G36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5G36 + +//***************************************************************************** +// +// LM3S5G51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5G51 + +//***************************************************************************** +// +// LM3S5G56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5G56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5G56 + +//***************************************************************************** +// +// LM3S5K31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5K31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5K31 + +//***************************************************************************** +// +// LM3S5K36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5K36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5K36 + +//***************************************************************************** +// +// LM3S5P31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5P31 + +//***************************************************************************** +// +// LM3S5P36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5P36 + +//***************************************************************************** +// +// LM3S5P3B Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P3B + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 + +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5P3B + +//***************************************************************************** +// +// LM3S5P51 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P51 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5P51 + +//***************************************************************************** +// +// LM3S5P56 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5P56 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5P56 + +//***************************************************************************** +// +// LM3S5R31 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5R31 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S5R31 + +//***************************************************************************** +// +// LM3S5R36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5R36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5R36 + +//***************************************************************************** +// +// LM3S5T36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5T36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5T36 + +//***************************************************************************** +// +// LM3S5U91 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5U91 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S5U91 + +//***************************************************************************** +// +// LM3S5Y36 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5Y36 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHB0 0x00040C04 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#endif // PART_LM3S5Y36 + //***************************************************************************** // // LM3S6100 Port/Pin Mapping Definitions @@ -15362,97 +30218,97 @@ //***************************************************************************** #ifdef PART_LM3S6100 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S6100 @@ -15463,125 +30319,125 @@ //***************************************************************************** #ifdef PART_LM3S6110 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S6110 @@ -15592,109 +30448,109 @@ //***************************************************************************** #ifdef PART_LM3S6420 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S6420 @@ -15705,109 +30561,109 @@ //***************************************************************************** #ifdef PART_LM3S6422 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S6422 @@ -15818,133 +30674,133 @@ //***************************************************************************** #ifdef PART_LM3S6432 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6432 @@ -15955,157 +30811,157 @@ //***************************************************************************** #ifdef PART_LM3S6537 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6537 @@ -16116,185 +30972,185 @@ //***************************************************************************** #ifdef PART_LM3S6610 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C2O_PORT (GPIO_PORTE_BASE) -#define C2O_PIN (GPIO_PIN_7) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOE +#define C2O_PORT GPIO_PORTE_BASE +#define C2O_PIN GPIO_PIN_7 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_0) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6610 @@ -16305,165 +31161,165 @@ //***************************************************************************** #ifdef PART_LM3S6611 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6611 @@ -16474,153 +31330,153 @@ //***************************************************************************** #ifdef PART_LM3S6618 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) -#define I2C1SCL_PORT (GPIO_PORTG_BASE) -#define I2C1SCL_PIN (GPIO_PIN_0) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6618 @@ -16631,121 +31487,121 @@ //***************************************************************************** #ifdef PART_LM3S6633 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6633 @@ -16756,145 +31612,145 @@ //***************************************************************************** #ifdef PART_LM3S6637 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6637 @@ -16905,109 +31761,109 @@ //***************************************************************************** #ifdef PART_LM3S6730 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S6730 @@ -17018,161 +31874,161 @@ //***************************************************************************** #ifdef PART_LM3S6753 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6753 @@ -17183,129 +32039,129 @@ //***************************************************************************** #ifdef PART_LM3S6816 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT_PORT (GPIO_PORTE_BASE) -#define FAULT_PIN (GPIO_PIN_1) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT_PORT GPIO_PORTE_BASE +#define FAULT_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6816 @@ -17316,165 +32172,165 @@ //***************************************************************************** #ifdef PART_LM3S6911 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) -#define C1O_PORT (GPIO_PORTE_BASE) -#define C1O_PIN (GPIO_PIN_6) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOE +#define C1O_PORT GPIO_PORTE_BASE +#define C1O_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6911 @@ -17485,129 +32341,129 @@ //***************************************************************************** #ifdef PART_LM3S6916 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE) -#define FAULT_PORT (GPIO_PORTE_BASE) -#define FAULT_PIN (GPIO_PIN_1) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOE +#define FAULT_PORT GPIO_PORTE_BASE +#define FAULT_PIN GPIO_PIN_1 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6916 @@ -17618,153 +32474,153 @@ //***************************************************************************** #ifdef PART_LM3S6918 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP4_PORT (GPIO_PORTC_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP4_PORT GPIO_PORTC_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) -#define I2C1SCL_PORT (GPIO_PORTG_BASE) -#define I2C1SCL_PIN (GPIO_PIN_0) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOG +#define I2C1SCL_PORT GPIO_PORTG_BASE +#define I2C1SCL_PIN GPIO_PIN_0 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S6918 @@ -17775,149 +32631,149 @@ //***************************************************************************** #ifdef PART_LM3S6938 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_0) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6938 @@ -17928,209 +32784,209 @@ //***************************************************************************** #ifdef PART_LM3S6950 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_4 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PHA0_PORT (GPIO_PORTD_BASE) -#define PHA0_PIN (GPIO_PIN_1) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOD +#define PHA0_PORT GPIO_PORTD_BASE +#define PHA0_PIN GPIO_PIN_1 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_6) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_6 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_7) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_7 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6950 @@ -18141,173 +32997,173 @@ //***************************************************************************** #ifdef PART_LM3S6952 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_0) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PHB0_PORT (GPIO_PORTF_BASE) -#define PHB0_PIN (GPIO_PIN_0) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOF +#define PHB0_PORT GPIO_PORTF_BASE +#define PHB0_PIN GPIO_PIN_0 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM0_PORT (GPIO_PORTD_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM0_PORT GPIO_PORTD_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6952 @@ -18318,192 +33174,920 @@ //***************************************************************************** #ifdef PART_LM3S6965 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP1_PORT (GPIO_PORTD_BASE) -#define CCP1_PIN (GPIO_PIN_7) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP1_PORT GPIO_PORTD_BASE +#define CCP1_PIN GPIO_PIN_7 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP2_PORT (GPIO_PORTD_BASE) -#define CCP2_PIN (GPIO_PIN_5) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP2_PORT GPIO_PORTD_BASE +#define CCP2_PIN GPIO_PIN_5 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_0) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_0 -#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define IDX1_PORT (GPIO_PORTF_BASE) -#define IDX1_PIN (GPIO_PIN_1) +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOF +#define IDX1_PORT GPIO_PORTF_BASE +#define IDX1_PIN GPIO_PIN_1 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PHA1_PORT (GPIO_PORTE_BASE) -#define PHA1_PIN (GPIO_PIN_3) +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHA1_PORT GPIO_PORTE_BASE +#define PHA1_PIN GPIO_PIN_3 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PHB1_PORT (GPIO_PORTE_BASE) -#define PHB1_PIN (GPIO_PIN_2) +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHB1_PORT GPIO_PORTE_BASE +#define PHB1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM1_PORT (GPIO_PORTD_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM1_PORT GPIO_PORTD_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S6965 +//***************************************************************************** +// +// LM3S6C11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6C11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#endif // PART_LM3S6C11 + +//***************************************************************************** +// +// LM3S6C65 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6C65 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S6C65 + +//***************************************************************************** +// +// LM3S6G11 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6G11 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 + +#define GPIO_PA3_SSI0FSS 0x00000C01 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 + +#endif // PART_LM3S6G11 + +//***************************************************************************** +// +// LM3S6G65 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6G65 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 + +#define GPIO_PA5_SSI0TX 0x00001401 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S6G65 + //***************************************************************************** // // LM3S8530 Port/Pin Mapping Definitions @@ -18511,125 +34095,125 @@ //***************************************************************************** #ifdef PART_LM3S8530 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CAN2RX_PORT (GPIO_PORTE_BASE) -#define CAN2RX_PIN (GPIO_PIN_4) +#define CAN2RX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2RX_PORT GPIO_PORTE_BASE +#define CAN2RX_PIN GPIO_PIN_4 -#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CAN2TX_PORT (GPIO_PORTE_BASE) -#define CAN2TX_PIN (GPIO_PIN_5) +#define CAN2TX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2TX_PORT GPIO_PORTE_BASE +#define CAN2TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S8530 @@ -18640,141 +34224,141 @@ //***************************************************************************** #ifdef PART_LM3S8538 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_0) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8538 @@ -18785,101 +34369,101 @@ //***************************************************************************** #ifdef PART_LM3S8630 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8630 @@ -18890,101 +34474,101 @@ //***************************************************************************** #ifdef PART_LM3S8730 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8730 @@ -18995,141 +34579,141 @@ //***************************************************************************** #ifdef PART_LM3S8733 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8733 @@ -19140,153 +34724,153 @@ //***************************************************************************** #ifdef PART_LM3S8738 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S8738 @@ -19297,101 +34881,101 @@ //***************************************************************************** #ifdef PART_LM3S8930 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S8930 @@ -19402,141 +34986,141 @@ //***************************************************************************** #ifdef PART_LM3S8933 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) -#define C0O_PORT (GPIO_PORTD_BASE) -#define C0O_PIN (GPIO_PIN_7) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOD +#define C0O_PORT GPIO_PORTD_BASE +#define C0O_PIN GPIO_PIN_7 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP3_PORT (GPIO_PORTD_BASE) -#define CCP3_PIN (GPIO_PIN_4) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP3_PORT GPIO_PORTD_BASE +#define CCP3_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8933 @@ -19547,169 +35131,169 @@ //***************************************************************************** #ifdef PART_LM3S8938 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_6) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_6 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1O_PORT (GPIO_PORTC_BASE) -#define C1O_PIN (GPIO_PIN_5) +#define C1O_PERIPH SYSCTL_PERIPH_GPIOC +#define C1O_PORT GPIO_PORTC_BASE +#define C1O_PIN GPIO_PIN_5 -#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C1_MINUS_PORT (GPIO_PORTB_BASE) -#define C1_MINUS_PIN (GPIO_PIN_5) +#define C1_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C1_MINUS_PORT GPIO_PORTB_BASE +#define C1_MINUS_PIN GPIO_PIN_5 -#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C1_PLUS_PORT (GPIO_PORTC_BASE) -#define C1_PLUS_PIN (GPIO_PIN_5) +#define C1_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C1_PLUS_PORT GPIO_PORTC_BASE +#define C1_PLUS_PIN GPIO_PIN_5 -#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2O_PORT (GPIO_PORTC_BASE) -#define C2O_PIN (GPIO_PIN_6) +#define C2O_PERIPH SYSCTL_PERIPH_GPIOC +#define C2O_PORT GPIO_PORTC_BASE +#define C2O_PIN GPIO_PIN_6 -#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_MINUS_PORT (GPIO_PORTC_BASE) -#define C2_MINUS_PIN (GPIO_PIN_7) +#define C2_MINUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_MINUS_PORT GPIO_PORTC_BASE +#define C2_MINUS_PIN GPIO_PIN_7 -#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C2_PLUS_PORT (GPIO_PORTC_BASE) -#define C2_PLUS_PIN (GPIO_PIN_6) +#define C2_PLUS_PERIPH SYSCTL_PERIPH_GPIOC +#define C2_PLUS_PORT GPIO_PORTC_BASE +#define C2_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP1_PORT (GPIO_PORTE_BASE) -#define CCP1_PIN (GPIO_PIN_3) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP1_PORT GPIO_PORTE_BASE +#define CCP1_PIN GPIO_PIN_3 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP3_PORT (GPIO_PORTE_BASE) -#define CCP3_PIN (GPIO_PIN_0) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP3_PORT GPIO_PORTE_BASE +#define CCP3_PIN GPIO_PIN_0 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CCP4_PORT (GPIO_PORTE_BASE) -#define CCP4_PIN (GPIO_PIN_2) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOE +#define CCP4_PORT GPIO_PORTE_BASE +#define CCP4_PIN GPIO_PIN_2 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP5_PORT (GPIO_PORTC_BASE) -#define CCP5_PIN (GPIO_PIN_4) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP5_PORT GPIO_PORTC_BASE +#define CCP5_PIN GPIO_PIN_4 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SCL_PORT (GPIO_PORTA_BASE) -#define I2C1SCL_PIN (GPIO_PIN_6) +#define I2C1SCL_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SCL_PORT GPIO_PORTA_BASE +#define I2C1SCL_PIN GPIO_PIN_6 -#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) -#define I2C1SDA_PORT (GPIO_PORTA_BASE) -#define I2C1SDA_PIN (GPIO_PIN_7) +#define I2C1SDA_PERIPH SYSCTL_PERIPH_GPIOA +#define I2C1SDA_PORT GPIO_PORTA_BASE +#define I2C1SDA_PIN GPIO_PIN_7 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 -#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2RX_PORT (GPIO_PORTG_BASE) -#define U2RX_PIN (GPIO_PIN_0) +#define U2RX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2RX_PORT GPIO_PORTG_BASE +#define U2RX_PIN GPIO_PIN_0 -#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) -#define U2TX_PORT (GPIO_PORTG_BASE) -#define U2TX_PIN (GPIO_PIN_1) +#define U2TX_PERIPH SYSCTL_PERIPH_GPIOG +#define U2TX_PORT GPIO_PORTG_BASE +#define U2TX_PIN GPIO_PIN_1 #endif // PART_LM3S8938 @@ -19720,165 +35304,165 @@ //***************************************************************************** #ifdef PART_LM3S8962 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0O_PORT (GPIO_PORTB_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOB +#define C0O_PORT GPIO_PORTB_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CCP0_PORT (GPIO_PORTD_BASE) -#define CCP0_PIN (GPIO_PIN_4) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOD +#define CCP0_PORT GPIO_PORTD_BASE +#define CCP0_PIN GPIO_PIN_4 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) -#define FAULT_PORT (GPIO_PORTD_BASE) -#define FAULT_PIN (GPIO_PIN_6) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOD +#define FAULT_PORT GPIO_PORTD_BASE +#define FAULT_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) -#define IDX0_PORT (GPIO_PORTD_BASE) -#define IDX0_PIN (GPIO_PIN_7) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOD +#define IDX0_PORT GPIO_PORTD_BASE +#define IDX0_PIN GPIO_PIN_7 -#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define IDX1_PORT (GPIO_PORTF_BASE) -#define IDX1_PIN (GPIO_PIN_1) +#define IDX1_PERIPH SYSCTL_PERIPH_GPIOF +#define IDX1_PORT GPIO_PORTF_BASE +#define IDX1_PIN GPIO_PIN_1 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PHA1_PORT (GPIO_PORTE_BASE) -#define PHA1_PIN (GPIO_PIN_3) +#define PHA1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHA1_PORT GPIO_PORTE_BASE +#define PHA1_PIN GPIO_PIN_3 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_6) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_6 -#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PHB1_PORT (GPIO_PORTE_BASE) -#define PHB1_PIN (GPIO_PIN_2) +#define PHB1_PERIPH SYSCTL_PERIPH_GPIOE +#define PHB1_PORT GPIO_PORTE_BASE +#define PHB1_PIN GPIO_PIN_2 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) -#define PWM1_PORT (GPIO_PORTG_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOG +#define PWM1_PORT GPIO_PORTG_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM2_PORT (GPIO_PORTB_BASE) -#define PWM2_PIN (GPIO_PIN_0) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM2_PORT GPIO_PORTB_BASE +#define PWM2_PIN GPIO_PIN_0 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) -#define PWM3_PORT (GPIO_PORTB_BASE) -#define PWM3_PIN (GPIO_PIN_1) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOB +#define PWM3_PORT GPIO_PORTB_BASE +#define PWM3_PIN GPIO_PIN_1 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8962 @@ -19889,133 +35473,133 @@ //***************************************************************************** #ifdef PART_LM3S8970 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1RX_PORT (GPIO_PORTF_BASE) -#define CAN1RX_PIN (GPIO_PIN_0) +#define CAN1RX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1RX_PORT GPIO_PORTF_BASE +#define CAN1RX_PIN GPIO_PIN_0 -#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) -#define CAN1TX_PORT (GPIO_PORTF_BASE) -#define CAN1TX_PIN (GPIO_PIN_1) +#define CAN1TX_PERIPH SYSCTL_PERIPH_GPIOF +#define CAN1TX_PORT GPIO_PORTF_BASE +#define CAN1TX_PIN GPIO_PIN_1 -#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CAN2RX_PORT (GPIO_PORTE_BASE) -#define CAN2RX_PIN (GPIO_PIN_4) +#define CAN2RX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2RX_PORT GPIO_PORTE_BASE +#define CAN2RX_PIN GPIO_PIN_4 -#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define CAN2TX_PORT (GPIO_PORTE_BASE) -#define CAN2TX_PIN (GPIO_PIN_5) +#define CAN2TX_PERIPH SYSCTL_PERIPH_GPIOE +#define CAN2TX_PORT GPIO_PORTE_BASE +#define CAN2TX_PIN GPIO_PIN_5 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SCL_PORT (GPIO_PORTB_BASE) -#define I2C0SCL_PIN (GPIO_PIN_2) +#define I2C0SCL_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SCL_PORT GPIO_PORTB_BASE +#define I2C0SCL_PIN GPIO_PIN_2 -#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) -#define I2C0SDA_PORT (GPIO_PORTB_BASE) -#define I2C0SDA_PIN (GPIO_PIN_3) +#define I2C0SDA_PERIPH SYSCTL_PERIPH_GPIOB +#define I2C0SDA_PORT GPIO_PORTB_BASE +#define I2C0SDA_PIN GPIO_PIN_3 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1CLK_PORT (GPIO_PORTE_BASE) -#define SSI1CLK_PIN (GPIO_PIN_0) +#define SSI1CLK_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1CLK_PORT GPIO_PORTE_BASE +#define SSI1CLK_PIN GPIO_PIN_0 -#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1FSS_PORT (GPIO_PORTE_BASE) -#define SSI1FSS_PIN (GPIO_PIN_1) +#define SSI1FSS_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1FSS_PORT GPIO_PORTE_BASE +#define SSI1FSS_PIN GPIO_PIN_1 -#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1RX_PORT (GPIO_PORTE_BASE) -#define SSI1RX_PIN (GPIO_PIN_2) +#define SSI1RX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1RX_PORT GPIO_PORTE_BASE +#define SSI1RX_PIN GPIO_PIN_2 -#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) -#define SSI1TX_PORT (GPIO_PORTE_BASE) -#define SSI1TX_PIN (GPIO_PIN_3) +#define SSI1TX_PERIPH SYSCTL_PERIPH_GPIOE +#define SSI1TX_PORT GPIO_PORTE_BASE +#define SSI1TX_PIN GPIO_PIN_3 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 -#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1RX_PORT (GPIO_PORTD_BASE) -#define U1RX_PIN (GPIO_PIN_2) +#define U1RX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1RX_PORT GPIO_PORTD_BASE +#define U1RX_PIN GPIO_PIN_2 -#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define U1TX_PORT (GPIO_PORTD_BASE) -#define U1TX_PIN (GPIO_PIN_3) +#define U1TX_PERIPH SYSCTL_PERIPH_GPIOD +#define U1TX_PORT GPIO_PORTD_BASE +#define U1TX_PIN GPIO_PIN_3 #endif // PART_LM3S8970 @@ -20026,156 +35610,21518 @@ //***************************************************************************** #ifdef PART_LM3S8971 -#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) -#define C0O_PORT (GPIO_PORTC_BASE) -#define C0O_PIN (GPIO_PIN_5) +#define C0O_PERIPH SYSCTL_PERIPH_GPIOC +#define C0O_PORT GPIO_PORTC_BASE +#define C0O_PIN GPIO_PIN_5 -#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_MINUS_PORT (GPIO_PORTB_BASE) -#define C0_MINUS_PIN (GPIO_PIN_4) +#define C0_MINUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_MINUS_PORT GPIO_PORTB_BASE +#define C0_MINUS_PIN GPIO_PIN_4 -#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) -#define C0_PLUS_PORT (GPIO_PORTB_BASE) -#define C0_PLUS_PIN (GPIO_PIN_6) +#define C0_PLUS_PERIPH SYSCTL_PERIPH_GPIOB +#define C0_PLUS_PORT GPIO_PORTB_BASE +#define C0_PLUS_PIN GPIO_PIN_6 -#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0RX_PORT (GPIO_PORTD_BASE) -#define CAN0RX_PIN (GPIO_PIN_0) +#define CAN0RX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0RX_PORT GPIO_PORTD_BASE +#define CAN0RX_PIN GPIO_PIN_0 -#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) -#define CAN0TX_PORT (GPIO_PORTD_BASE) -#define CAN0TX_PIN (GPIO_PIN_1) +#define CAN0TX_PERIPH SYSCTL_PERIPH_GPIOD +#define CAN0TX_PORT GPIO_PORTD_BASE +#define CAN0TX_PIN GPIO_PIN_1 -#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP0_PORT (GPIO_PORTB_BASE) -#define CCP0_PIN (GPIO_PIN_0) +#define CCP0_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP0_PORT GPIO_PORTB_BASE +#define CCP0_PIN GPIO_PIN_0 -#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP1_PORT (GPIO_PORTA_BASE) -#define CCP1_PIN (GPIO_PIN_6) +#define CCP1_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP1_PORT GPIO_PORTA_BASE +#define CCP1_PIN GPIO_PIN_6 -#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP2_PORT (GPIO_PORTB_BASE) -#define CCP2_PIN (GPIO_PIN_1) +#define CCP2_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP2_PORT GPIO_PORTB_BASE +#define CCP2_PIN GPIO_PIN_1 -#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) -#define CCP3_PORT (GPIO_PORTC_BASE) -#define CCP3_PIN (GPIO_PIN_6) +#define CCP3_PERIPH SYSCTL_PERIPH_GPIOC +#define CCP3_PORT GPIO_PORTC_BASE +#define CCP3_PIN GPIO_PIN_6 -#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) -#define CCP4_PORT (GPIO_PORTA_BASE) -#define CCP4_PIN (GPIO_PIN_7) +#define CCP4_PERIPH SYSCTL_PERIPH_GPIOA +#define CCP4_PORT GPIO_PORTA_BASE +#define CCP4_PIN GPIO_PIN_7 -#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) -#define CCP5_PORT (GPIO_PORTB_BASE) -#define CCP5_PIN (GPIO_PIN_5) +#define CCP5_PERIPH SYSCTL_PERIPH_GPIOB +#define CCP5_PORT GPIO_PORTB_BASE +#define CCP5_PIN GPIO_PIN_5 -#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) -#define FAULT_PORT (GPIO_PORTB_BASE) -#define FAULT_PIN (GPIO_PIN_3) +#define FAULT_PERIPH SYSCTL_PERIPH_GPIOB +#define FAULT_PORT GPIO_PORTB_BASE +#define FAULT_PIN GPIO_PIN_3 -#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB) -#define IDX0_PORT (GPIO_PORTB_BASE) -#define IDX0_PIN (GPIO_PIN_2) +#define IDX0_PERIPH SYSCTL_PERIPH_GPIOB +#define IDX0_PORT GPIO_PORTB_BASE +#define IDX0_PIN GPIO_PIN_2 -#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED0_PORT (GPIO_PORTF_BASE) -#define LED0_PIN (GPIO_PIN_3) +#define LED0_PERIPH SYSCTL_PERIPH_GPIOF +#define LED0_PORT GPIO_PORTF_BASE +#define LED0_PIN GPIO_PIN_3 -#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define LED1_PORT (GPIO_PORTF_BASE) -#define LED1_PIN (GPIO_PIN_2) +#define LED1_PERIPH SYSCTL_PERIPH_GPIOF +#define LED1_PORT GPIO_PORTF_BASE +#define LED1_PIN GPIO_PIN_2 -#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHA0_PORT (GPIO_PORTC_BASE) -#define PHA0_PIN (GPIO_PIN_4) +#define PHA0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHA0_PORT GPIO_PORTC_BASE +#define PHA0_PIN GPIO_PIN_4 -#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) -#define PHB0_PORT (GPIO_PORTC_BASE) -#define PHB0_PIN (GPIO_PIN_7) +#define PHB0_PERIPH SYSCTL_PERIPH_GPIOC +#define PHB0_PORT GPIO_PORTC_BASE +#define PHB0_PIN GPIO_PIN_7 -#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM0_PORT (GPIO_PORTF_BASE) -#define PWM0_PIN (GPIO_PIN_0) +#define PWM0_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM0_PORT GPIO_PORTF_BASE +#define PWM0_PIN GPIO_PIN_0 -#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) -#define PWM1_PORT (GPIO_PORTF_BASE) -#define PWM1_PIN (GPIO_PIN_1) +#define PWM1_PERIPH SYSCTL_PERIPH_GPIOF +#define PWM1_PORT GPIO_PORTF_BASE +#define PWM1_PIN GPIO_PIN_1 -#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM2_PORT (GPIO_PORTD_BASE) -#define PWM2_PIN (GPIO_PIN_2) +#define PWM2_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM2_PORT GPIO_PORTD_BASE +#define PWM2_PIN GPIO_PIN_2 -#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) -#define PWM3_PORT (GPIO_PORTD_BASE) -#define PWM3_PIN (GPIO_PIN_3) +#define PWM3_PERIPH SYSCTL_PERIPH_GPIOD +#define PWM3_PORT GPIO_PORTD_BASE +#define PWM3_PIN GPIO_PIN_3 -#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM4_PORT (GPIO_PORTE_BASE) -#define PWM4_PIN (GPIO_PIN_0) +#define PWM4_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM4_PORT GPIO_PORTE_BASE +#define PWM4_PIN GPIO_PIN_0 -#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) -#define PWM5_PORT (GPIO_PORTE_BASE) -#define PWM5_PIN (GPIO_PIN_1) +#define PWM5_PERIPH SYSCTL_PERIPH_GPIOE +#define PWM5_PORT GPIO_PORTE_BASE +#define PWM5_PIN GPIO_PIN_1 -#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0CLK_PORT (GPIO_PORTA_BASE) -#define SSI0CLK_PIN (GPIO_PIN_2) +#define SSI0CLK_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0CLK_PORT GPIO_PORTA_BASE +#define SSI0CLK_PIN GPIO_PIN_2 -#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0FSS_PORT (GPIO_PORTA_BASE) -#define SSI0FSS_PIN (GPIO_PIN_3) +#define SSI0FSS_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0FSS_PORT GPIO_PORTA_BASE +#define SSI0FSS_PIN GPIO_PIN_3 -#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0RX_PORT (GPIO_PORTA_BASE) -#define SSI0RX_PIN (GPIO_PIN_4) +#define SSI0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0RX_PORT GPIO_PORTA_BASE +#define SSI0RX_PIN GPIO_PIN_4 -#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define SSI0TX_PORT (GPIO_PORTA_BASE) -#define SSI0TX_PIN (GPIO_PIN_5) +#define SSI0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define SSI0TX_PORT GPIO_PORTA_BASE +#define SSI0TX_PIN GPIO_PIN_5 -#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWCLK_PORT (GPIO_PORTC_BASE) -#define SWCLK_PIN (GPIO_PIN_0) +#define SWCLK_PERIPH SYSCTL_PERIPH_GPIOC +#define SWCLK_PORT GPIO_PORTC_BASE +#define SWCLK_PIN GPIO_PIN_0 -#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWDIO_PORT (GPIO_PORTC_BASE) -#define SWDIO_PIN (GPIO_PIN_1) +#define SWDIO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWDIO_PORT GPIO_PORTC_BASE +#define SWDIO_PIN GPIO_PIN_1 -#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define SWO_PORT (GPIO_PORTC_BASE) -#define SWO_PIN (GPIO_PIN_3) +#define SWO_PERIPH SYSCTL_PERIPH_GPIOC +#define SWO_PORT GPIO_PORTC_BASE +#define SWO_PIN GPIO_PIN_3 -#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TCK_PORT (GPIO_PORTC_BASE) -#define TCK_PIN (GPIO_PIN_0) +#define TCK_PERIPH SYSCTL_PERIPH_GPIOC +#define TCK_PORT GPIO_PORTC_BASE +#define TCK_PIN GPIO_PIN_0 -#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDI_PORT (GPIO_PORTC_BASE) -#define TDI_PIN (GPIO_PIN_2) +#define TDI_PERIPH SYSCTL_PERIPH_GPIOC +#define TDI_PORT GPIO_PORTC_BASE +#define TDI_PIN GPIO_PIN_2 -#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TDO_PORT (GPIO_PORTC_BASE) -#define TDO_PIN (GPIO_PIN_3) +#define TDO_PERIPH SYSCTL_PERIPH_GPIOC +#define TDO_PORT GPIO_PORTC_BASE +#define TDO_PIN GPIO_PIN_3 -#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) -#define TMS_PORT (GPIO_PORTC_BASE) -#define TMS_PIN (GPIO_PIN_1) +#define TMS_PERIPH SYSCTL_PERIPH_GPIOC +#define TMS_PORT GPIO_PORTC_BASE +#define TMS_PIN GPIO_PIN_1 -#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) -#define TRST_PORT (GPIO_PORTB_BASE) -#define TRST_PIN (GPIO_PIN_7) +#define TRST_PERIPH SYSCTL_PERIPH_GPIOB +#define TRST_PORT GPIO_PORTB_BASE +#define TRST_PIN GPIO_PIN_7 -#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0RX_PORT (GPIO_PORTA_BASE) -#define U0RX_PIN (GPIO_PIN_0) +#define U0RX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0RX_PORT GPIO_PORTA_BASE +#define U0RX_PIN GPIO_PIN_0 -#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) -#define U0TX_PORT (GPIO_PORTA_BASE) -#define U0TX_PIN (GPIO_PIN_1) +#define U0TX_PERIPH SYSCTL_PERIPH_GPIOA +#define U0TX_PORT GPIO_PORTA_BASE +#define U0TX_PIN GPIO_PIN_1 #endif // PART_LM3S8971 +//***************************************************************************** +// +// LM3S8C62 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8C62 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 + +#define GPIO_PD6_FAULT0 0x00031801 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S8C62 + +//***************************************************************************** +// +// LM3S8G62 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8G62 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 + +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 + +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 + +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 + +#define GPIO_PD6_FAULT0 0x00031801 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_CCP3 0x00040003 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_CCP2 0x00041006 + +#define GPIO_PE5_CCP5 0x00041401 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 + +#define GPIO_PE7_PWM5 0x00041C01 + +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 + +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_PWM4 0x00060004 + +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_PWM5 0x00060404 + +#endif // PART_LM3S8G62 + +//***************************************************************************** +// +// LM3S9781 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9781 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9781 + +//***************************************************************************** +// +// LM3S9790 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9790 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9790 + +//***************************************************************************** +// +// LM3S9792 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9792 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9792 + +//***************************************************************************** +// +// LM3S9971 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9971 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9971 + +//***************************************************************************** +// +// LM3S9997 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9997 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9997 + +//***************************************************************************** +// +// LM3S9B81 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B81 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B81 + +//***************************************************************************** +// +// LM3S9B90 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B90 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9B90 + +//***************************************************************************** +// +// LM3S9B92 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B92 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B92 + +//***************************************************************************** +// +// LM3S9B95 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B95 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B95 + +//***************************************************************************** +// +// LM3S9B96 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9B96 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9B96 + +//***************************************************************************** +// +// LM3S9BN2 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9BN2 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9BN2 + +//***************************************************************************** +// +// LM3S9BN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9BN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9BN5 + +//***************************************************************************** +// +// LM3S9BN6 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9BN6 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9BN6 + +//***************************************************************************** +// +// LM3S9C97 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9C97 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9C97 + +//***************************************************************************** +// +// LM3S9CN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9CN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9CN5 + +//***************************************************************************** +// +// LM3S9D81 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D81 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D81 + +//***************************************************************************** +// +// LM3S9D90 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D90 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9D90 + +//***************************************************************************** +// +// LM3S9D92 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D92 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D92 + +//***************************************************************************** +// +// LM3S9D95 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D95 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D95 + +//***************************************************************************** +// +// LM3S9D96 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9D96 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9D96 + +//***************************************************************************** +// +// LM3S9DN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9DN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9DN5 + +//***************************************************************************** +// +// LM3S9DN6 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9DN6 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9DN6 + +//***************************************************************************** +// +// LM3S9G97 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9G97 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9G97 + +//***************************************************************************** +// +// LM3S9GN5 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9GN5 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_EPI0S12 0x00051C08 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9GN5 + +//***************************************************************************** +// +// LM3S9L71 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9L71 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_TXD2 0x00000803 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_TXD1 0x00000C03 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_TXD0 0x00001003 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_RXDV 0x00001403 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_RXCK 0x00001803 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_RXER 0x00001C03 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 +#define GPIO_PB7_RXD1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_TXD3 0x00021003 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_RXDV 0x00030007 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_TXER 0x00030407 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_TXD3 0x00031004 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_TXD2 0x00031404 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_TXD1 0x00031804 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_TXD0 0x00031C04 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_RXD0 0x00041007 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_RXCK 0x00050004 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_RXER 0x00050404 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PHYINT 0x00050803 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_MDC 0x00050C03 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_MDIO 0x00051003 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_RXD3 0x00051403 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_RXD2 0x00051803 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180A + +#define GPIO_PF7_CCP4 0x00051C01 +#define GPIO_PF7_RXD1 0x00051C03 +#define GPIO_PF7_PHB0 0x00051C04 +#define GPIO_PF7_FAULT1 0x00051C09 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_COL 0x00060803 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +#define GPIO_PG3_PWM1 0x00060C01 +#define GPIO_PG3_CRS 0x00060C03 +#define GPIO_PG3_FAULT2 0x00060C04 +#define GPIO_PG3_FAULT0 0x00060C08 +#define GPIO_PG3_I2S0RXMCLK 0x00060C09 + +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_RXD0 0x00061003 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_U1RI 0x0006100A + +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_TXEN 0x00061403 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140A + +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_TXCK 0x00061803 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180A + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_TXER 0x00061C03 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_TXD3 0x00070809 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_TXD2 0x00070C09 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_TXD1 0x00071009 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_TXD0 0x00071409 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_RXDV 0x00071809 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_RXCK 0x00071C03 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_RXER 0x00080003 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9L71 + +//***************************************************************************** +// +// LM3S9L97 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9L97 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_CCP5 0x00061C08 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#endif // PART_LM3S9L97 + +//***************************************************************************** +// +// LM3S9U81 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U81 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_CAN2RX 0x00041002 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_CAN2TX 0x00041402 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U81 + +//***************************************************************************** +// +// LM3S9U90 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U90 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_EPI0S6 0x00070008 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_EPI0S7 0x00070408 + +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 + +#endif // PART_LM3S9U90 + +//***************************************************************************** +// +// LM3S9U92 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U92 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U92 + +//***************************************************************************** +// +// LM3S9U95 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U95 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U95 + +//***************************************************************************** +// +// LM3S9U96 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S9U96 + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +#define GPIO_PA3_SSI0FSS 0x00000C01 +#define GPIO_PA3_PWM5 0x00000C04 +#define GPIO_PA3_I2S0RXMCLK 0x00000C09 + +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +#define GPIO_PA7_I2C1SDA 0x00001C01 +#define GPIO_PA7_CCP4 0x00001C02 +#define GPIO_PA7_PWM1 0x00001C04 +#define GPIO_PA7_PWM5 0x00001C05 +#define GPIO_PA7_CAN0TX 0x00001C06 +#define GPIO_PA7_CCP3 0x00001C07 +#define GPIO_PA7_USB0PFLT 0x00001C08 +#define GPIO_PA7_U1DCD 0x00001C09 + +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +#define GPIO_PB3_I2C0SDA 0x00010C01 +#define GPIO_PB3_FAULT0 0x00010C02 +#define GPIO_PB3_FAULT3 0x00010C04 +#define GPIO_PB3_USB0PFLT 0x00010C08 + +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +#define GPIO_PB7_NMI 0x00011C04 + +#define GPIO_PC0_TCK 0x00020003 +#define GPIO_PC0_SWCLK 0x00020003 + +#define GPIO_PC1_TMS 0x00020403 +#define GPIO_PC1_SWDIO 0x00020403 + +#define GPIO_PC2_TDI 0x00020803 + +#define GPIO_PC3_SWO 0x00020C03 +#define GPIO_PC3_TDO 0x00020C03 + +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +#define GPIO_PC7_CCP4 0x00021C01 +#define GPIO_PC7_PHB0 0x00021C02 +#define GPIO_PC7_CCP0 0x00021C04 +#define GPIO_PC7_U1TX 0x00021C05 +#define GPIO_PC7_USB0PFLT 0x00021C06 +#define GPIO_PC7_C1O 0x00021C07 +#define GPIO_PC7_EPI0S5 0x00021C08 + +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040A +#define GPIO_PD1_PHB1 0x0003040B + +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +#define GPIO_PD3_U1TX 0x00030C01 +#define GPIO_PD3_CCP7 0x00030C02 +#define GPIO_PD3_PWM3 0x00030C03 +#define GPIO_PD3_CCP0 0x00030C04 +#define GPIO_PD3_EPI0S21 0x00030C08 + +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100A + +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140A + +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180A + +#define GPIO_PD7_IDX0 0x00031C01 +#define GPIO_PD7_C0O 0x00031C02 +#define GPIO_PD7_CCP1 0x00031C03 +#define GPIO_PD7_I2S0TXWS 0x00031C08 +#define GPIO_PD7_U1DTR 0x00031C09 +#define GPIO_PD7_EPI0S30 0x00031C0A + +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +#define GPIO_PE3_CCP1 0x00040C01 +#define GPIO_PE3_SSI1TX 0x00040C02 +#define GPIO_PE3_PHA1 0x00040C03 +#define GPIO_PE3_PHB0 0x00040C04 +#define GPIO_PE3_CCP7 0x00040C05 +#define GPIO_PE3_EPI0S25 0x00040C08 + +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +#define GPIO_PE7_PWM5 0x00041C01 +#define GPIO_PE7_C2O 0x00041C02 +#define GPIO_PE7_U1DCD 0x00041C09 + +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040A + +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +#define GPIO_PF3_LED0 0x00050C01 +#define GPIO_PF3_PWM5 0x00050C02 +#define GPIO_PF3_PWM3 0x00050C04 +#define GPIO_PF3_SSI1FSS 0x00050C09 + +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +#define GPIO_PG7_PHB1 0x00061C01 +#define GPIO_PG7_PWM7 0x00061C04 +#define GPIO_PG7_CCP5 0x00061C08 +#define GPIO_PG7_EPI0S31 0x00061C09 + +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +#define GPIO_PH3_PHB0 0x00070C01 +#define GPIO_PH3_FAULT0 0x00070C02 +#define GPIO_PH3_USB0EPEN 0x00070C04 +#define GPIO_PH3_EPI0S0 0x00070C08 + +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100B + +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140A +#define GPIO_PH5_SSI1FSS 0x0007140B + +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180A +#define GPIO_PH6_SSI1RX 0x0007180B + +#define GPIO_PH7_EPI0S27 0x00071C08 +#define GPIO_PH7_PWM5 0x00071C0A +#define GPIO_PH7_SSI1TX 0x00071C0B + +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000A +#define GPIO_PJ0_I2C1SCL 0x0008000B + +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040A +#define GPIO_PJ1_I2C1SDA 0x0008040B + +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080A + +#define GPIO_PJ3_EPI0S19 0x00080C08 +#define GPIO_PJ3_U1CTS 0x00080C09 +#define GPIO_PJ3_CCP6 0x00080C0A + +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100A + +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140A + +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180A + +#define GPIO_PJ7_U1DTR 0x00081C09 +#define GPIO_PJ7_CCP0 0x00081C0A + +#endif // PART_LM3S9U96 + +//***************************************************************************** +// +// LM4F110B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110B2QR + +//***************************************************************************** +// +// LM4F110C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110C4QR + +//***************************************************************************** +// +// LM4F110E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110E5QR + +//***************************************************************************** +// +// LM4F110H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F110H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F110H5QR + +//***************************************************************************** +// +// LM4F111B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111B2QR + +//***************************************************************************** +// +// LM4F111C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111C4QR + +//***************************************************************************** +// +// LM4F111E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111E5QR + +//***************************************************************************** +// +// LM4F111H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F111H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F111H5QR + +//***************************************************************************** +// +// LM4F112C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112C4QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F112C4QC + +//***************************************************************************** +// +// LM4F112E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112E5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F112E5QC + +//***************************************************************************** +// +// LM4F112H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112H5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F112H5QC + +//***************************************************************************** +// +// LM4F112H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F112H5QD + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F112H5QD + +//***************************************************************************** +// +// LM4F120B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120B2QR + +//***************************************************************************** +// +// LM4F120C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120C4QR + +//***************************************************************************** +// +// LM4F120E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120E5QR + +//***************************************************************************** +// +// LM4F120H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120H5QR + +//***************************************************************************** +// +// LM4F121B2QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121B2QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121B2QR + +//***************************************************************************** +// +// LM4F121C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121C4QR + +//***************************************************************************** +// +// LM4F121E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121E5QR + +//***************************************************************************** +// +// LM4F121H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F121H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_LM4F121H5QR + +//***************************************************************************** +// +// LM4F122C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122C4QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F122C4QC + +//***************************************************************************** +// +// LM4F122E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122E5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F122E5QC + +//***************************************************************************** +// +// LM4F122H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122H5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F122H5QC + +//***************************************************************************** +// +// LM4F122H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F122H5QD + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F122H5QD + +//***************************************************************************** +// +// LM4F130C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F130C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F130C4QR + +//***************************************************************************** +// +// LM4F130E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F130E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F130E5QR + +//***************************************************************************** +// +// LM4F130H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F130H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F130H5QR + +//***************************************************************************** +// +// LM4F131C4QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F131C4QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F131C4QR + +//***************************************************************************** +// +// LM4F131E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F131E5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F131E5QR + +//***************************************************************************** +// +// LM4F131H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F131H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F131H5QR + +//***************************************************************************** +// +// LM4F132C4QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132C4QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F132C4QC + +//***************************************************************************** +// +// LM4F132E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132E5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F132E5QC + +//***************************************************************************** +// +// LM4F132H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132H5QC + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_LM4F132H5QC + +//***************************************************************************** +// +// LM4F132H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F132H5QD + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F132H5QD + +//***************************************************************************** +// +// LM4F230E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F230E5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F230E5QR + +//***************************************************************************** +// +// LM4F230H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F230H5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_LM4F230H5QR + +//***************************************************************************** +// +// LM4F231E5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F231E5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F231E5QR + +//***************************************************************************** +// +// LM4F231H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F231H5QR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_LM4F231H5QR + +//***************************************************************************** +// +// LM4F232E5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232E5QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F232E5QC + +//***************************************************************************** +// +// LM4F232H5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232H5BB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4F232H5BB + +//***************************************************************************** +// +// LM4F232H5QC Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232H5QC + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 +#define GPIO_PG0_LPC0PD_N 0x0006000F + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 +#define GPIO_PG1_LPC0SCI_N 0x0006040F + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 +#define GPIO_PG2_LPC0CLKRUN_N 0x0006080F + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_LM4F232H5QC + +//***************************************************************************** +// +// LM4F232H5QD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F232H5QD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_LM4F232H5QD + +//***************************************************************************** +// +// LM4FS1AH5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FS1AH5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FS1AH5BB + +//***************************************************************************** +// +// LM4FS99H5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FS99H5BB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_USB0PFLT 0x00021C08 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_FAN0PWM7 0x00080802 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_FAN0TACH7 0x00080C02 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_FAN0PWM6 0x00091002 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_FAN0TACH6 0x00091402 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FS99H5BB + +//***************************************************************************** +// +// LM4FSXAH5BB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4FSXAH5BB + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 + +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 + +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE4_I2C2SCL 0x00041003 + +#define GPIO_PE5_I2C2SDA 0x00041403 + +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_FAN0PWM5 0x00070801 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_FAN0TACH5 0x00070C01 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PJ6_PECI0TX 0x00081801 + +#define GPIO_PK4_RTCCLK 0x00091007 + +#define GPIO_PK6_FAN0PWM1 0x00091801 +#define GPIO_PK6_WT1CCP0 0x00091807 + +#define GPIO_PK7_FAN0TACH1 0x00091C01 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 +#define GPIO_PL0_LPC0AD3 0x000A000F + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 +#define GPIO_PL1_LPC0AD2 0x000A040F + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 +#define GPIO_PL2_LPC0AD1 0x000A080F + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 +#define GPIO_PL3_LPC0AD0 0x000A0C0F + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 +#define GPIO_PL4_LPC0FRAME_N 0x000A100F + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 +#define GPIO_PL5_LPC0RESET_N 0x000A140F + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 +#define GPIO_PM0_LPC0PD_N 0x000B000F + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 +#define GPIO_PM1_LPC0SCI_N 0x000B040F + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 +#define GPIO_PM2_LPC0CLKRUN_N 0x000B080F + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM4_LPC0SERIRQ 0x000B100F + +#define GPIO_PM5_LPC0CLK 0x000B140F + +#define GPIO_PM6_FAN0PWM0 0x000B1801 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_FAN0TACH0 0x000B1C01 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN2_FAN0PWM2 0x000C0801 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_FAN0TACH2 0x000C0C01 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_FAN0PWM3 0x000C1001 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_FAN0TACH3 0x000C1401 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_FAN0PWM4 0x000C1801 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_FAN0TACH4 0x000C1C01 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_LM4FSXAH5BB + //***************************************************************************** // // Pin Mapping Functions @@ -20272,6 +57218,28 @@ //***************************************************************************** #define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN) +//***************************************************************************** +// +// Configures the specified Ethernet LED to function as an Ethernet LED pin. +// +// \param ulName is one of the valid names for the Ethernet LED pins. +// +// This function takes one of the valid names for an Ethernet LED pin and +// configures the pin for its Ethernet LED functionality depending on the part +// that is defined. +// +// The valid names for the pins are as follows: \b LED0 or \b LED1. +// +// sa GPIOPinTypeEthernetLED() in order to configure multiple Ethernet LED +// pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeEthernetLED(ulName) \ + GPIOPinTypeEthernetLED(ulName##_PORT, \ + ulName##_PIN) + //***************************************************************************** // // Configures the specified PWM pin to function as a PWM pin. diff --git a/bsp/lm3s8962/Libraries/driverlib/pwm.c b/bsp/lm3s8962/Libraries/driverlib/pwm.c index 3694a362fd..c6432735d1 100644 --- a/bsp/lm3s8962/Libraries/driverlib/pwm.c +++ b/bsp/lm3s8962/Libraries/driverlib/pwm.c @@ -2,7 +2,7 @@ // // pwm.c - API for the PWM modules // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -105,8 +105,8 @@ PWMOutValid(unsigned long ulPWMOut) //! Configures a PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to configure. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to configure. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulConfig is the configuration for the PWM generator. //! //! This function is used to set the mode of operation for a PWM generator. @@ -115,31 +115,31 @@ PWMOutValid(unsigned long ulPWMOut) //! state. //! //! A PWM generator can count in two different modes: count down mode or count -//! up/down mode. In count down mode, it will count from a value down to zero, -//! and then reset to the preset value. This will produce left-aligned PWM -//! signals (that is the rising edge of the two PWM signals produced by the -//! generator will occur at the same time). In count up/down mode, it will -//! count up from zero to the preset value, count back down to zero, and then -//! repeat the process. This will produce center-aligned PWM signals (that is, +//! up/down mode. In count down mode, it counts from a value down to zero, +//! and then resets to the preset value, producing left-aligned PWM +//! signals (that is, the rising edge of the two PWM signals produced by the +//! generator occur at the same time). In count up/down mode, it counts up +//! from zero to the preset value, counts back down to zero, and then repeats +//! the process, producing center-aligned PWM signals (that is, //! the middle of the high/low period of the PWM signals produced by the -//! generator will occur at the same time). +//! generator occurs at the same time). //! //! When the PWM generator parameters (period and pulse width) are modified, -//! their affect on the output PWM signals can be delayed. In synchronous +//! their effect on the output PWM signals can be delayed. In synchronous //! mode, the parameter updates are not applied until a synchronization event -//! occurs. This allows multiple parameters to be modified and take affect -//! simultaneously, instead of one at a time. Additionally, parameters to -//! multiple PWM generators in synchronous mode can be updated simultaneously, -//! allowing them to be treated as if they were a unified generator. In -//! non-synchronous mode, the parameter updates are not delayed until a -//! synchronization event. In either mode, the parameter updates only occur -//! when the counter is at zero to help prevent oddly formed PWM signals during -//! the update (that is, a PWM pulse that is too short or too long). +//! occurs. This mode allows multiple parameters to be modified and take +//! effect simultaneously, instead of one at a time. Additionally, parameters +//! to multiple PWM generators in synchronous mode can be updated +//! simultaneously, allowing them to be treated as if they were a unified +//! generator. In non-synchronous mode, the parameter updates are not delayed +//! until a synchronization event. In either mode, the parameter updates only +//! occur when the counter is at zero to help prevent oddly formed PWM signals +//! during the update (that is, a PWM pulse that is too short or too long). //! //! The PWM generator can either pause or continue running when the processor -//! is stopped via the debugger. If configured to pause, it will continue to -//! count until it reaches zero, at which point it will pause until the -//! processor is restarted. If configured to continue running, it will keep +//! is stopped via the debugger. If configured to pause, it continues to +//! count until it reaches zero, at which point it pauses until the +//! processor is restarted. If configured to continue running, it keeps //! counting as if nothing had happened. //! //! The \e ulConfig parameter contains the desired configuration. It is the @@ -165,14 +165,14 @@ PWMOutValid(unsigned long ulPWMOut) //! whether extended fault source selection support is enabled or not //! //! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the -//! minimum duration of a PWM fault signal. Fault will be signaled for at +//! minimum duration of a PWM fault signal. Faults are signaled for at //! least this time even if the external fault pin deasserts earlier. Care -//! should be taken when using this mode since during the fault signal period, -//! the fault interrupt from the PWM generator will remain asserted. The fault -//! interrupt handler may, therefore, reenter immediately if it exits prior to -//! expiration of the fault timer. +//! should be taken when using this mode because during the fault signal +//! period, the fault interrupt from the PWM generator remains asserted. The +//! fault interrupt handler may, therefore, reenter immediately if it exits +//! prior to expiration of the fault timer. //! -//! \note Changes to the counter mode will affect the period of the PWM signals +//! \note Changes to the counter mode affect the period of the PWM signals //! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after //! any changes to the counter mode of a generator. //! @@ -186,7 +186,7 @@ PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -238,11 +238,11 @@ PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, //***************************************************************************** // -//! Set the period of a PWM generator. +//! Sets the period of a PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be modified. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to be modified. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulPeriod specifies the period of PWM generator output, measured //! in clock ticks. //! @@ -251,7 +251,7 @@ PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, //! ticks between pulses on the generator block zero signal. //! //! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. +//! cause the previous values to be overwritten. //! //! \return None. // @@ -263,7 +263,7 @@ PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -299,7 +299,7 @@ PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, //! Gets the period of a PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of +//! \param ulGen is the PWM generator to query. This parameter must be one of //! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function gets the period of the specified PWM generator block. The @@ -320,7 +320,7 @@ PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -352,8 +352,8 @@ PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) //! Enables the timer/counter for a PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be enabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to be enabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function allows the PWM clock to drive the timer/counter for the //! specified generator block. @@ -367,7 +367,7 @@ PWMGenEnable(unsigned long ulBase, unsigned long ulGen) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -381,8 +381,8 @@ PWMGenEnable(unsigned long ulBase, unsigned long ulGen) //! Disables the timer/counter for a PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be disabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to be disabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function blocks the PWM clock from driving the timer/counter for the //! specified generator block. @@ -396,7 +396,7 @@ PWMGenDisable(unsigned long ulBase, unsigned long ulGen) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -410,16 +410,16 @@ PWMGenDisable(unsigned long ulBase, unsigned long ulGen) //! Sets the pulse width for the specified PWM output. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5, -//! \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ulPWMOut is the PWM output to modify. This parameter must be one +//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. //! \param ulWidth specifies the width of the positive portion of the pulse. //! //! This function sets the pulse width for the specified PWM output, where the //! pulse width is defined as the number of PWM clock ticks. //! //! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. +//! cause the previous values to be overwritten. //! //! \return None. // @@ -433,7 +433,7 @@ PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMOutValid(ulPWMOut)); // @@ -482,9 +482,9 @@ PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, //! Gets the pulse width of a PWM output. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5, -//! \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ulPWMOut is the PWM output to query. This parameter must be one of +//! \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. //! //! This function gets the currently programmed pulse width for the specified //! PWM output. If the update of the comparator for the specified output has @@ -503,7 +503,7 @@ PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMOutValid(ulPWMOut)); // @@ -542,11 +542,11 @@ PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) //***************************************************************************** // -//! Enables the PWM dead band output, and sets the dead band delays. +//! Enables the PWM dead band output and sets the dead band delays. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to modify. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param usRise specifies the width of delay from the rising edge. //! \param usFall specifies the width of delay from the falling edge. //! @@ -557,7 +557,7 @@ PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) //! //! \return None. // -//***************************************************************************** +//**************************************************************************** void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, unsigned short usRise, unsigned short usFall) @@ -565,7 +565,7 @@ PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT(usRise < 4096); ASSERT(usFall < 4096); @@ -592,7 +592,7 @@ PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, //! Disables the PWM dead band output. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of +//! \param ulGen is the PWM generator to modify. This parameter must be one of //! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function disables the dead band mode for the specified PWM generator. @@ -607,7 +607,7 @@ PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -622,9 +622,9 @@ PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) //! Synchronizes all pending updates. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be updated. Must be the -//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, -//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! \param ulGenBits are the PWM generator blocks to be updated. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. //! //! For the selected PWM generators, this function causes all queued updates to //! the period or pulse width to be applied the next time the corresponding @@ -639,7 +639,7 @@ PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | PWM_GEN_3_BIT))); @@ -654,9 +654,9 @@ PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) //! Synchronizes the counters in one or multiple PWM generator blocks. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be -//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, -//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! \param ulGenBits are the PWM generator blocks to be synchronized. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. //! //! For the selected PWM module, this function synchronizes the time base //! of the generator blocks by causing the specified generator counters to be @@ -671,7 +671,7 @@ PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | PWM_GEN_3_BIT))); @@ -687,17 +687,17 @@ PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) //! Enables or disables PWM outputs. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, -//! or \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bEnable determines if the signal is enabled or disabled. //! -//! This function is used to enable or disable the selected PWM outputs. The +//! This function enables or disables the selected PWM outputs. The //! outputs are selected using the parameter \e ulPWMOutBits. The parameter //! \e bEnable determines the state of the selected outputs. If \e bEnable is //! \b true, then the selected PWM outputs are enabled, or placed in the active -//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! state. If \e bEnable is \b false, then the selected outputs are disabled //! or placed in the inactive state. //! //! \return None. @@ -710,13 +710,13 @@ PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's ENABLE output control register, and set or clear the + // Read the module's ENABLE output control register and set or clear the // requested bits. // if(bEnable == true) @@ -734,19 +734,19 @@ PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, //! Selects the inversion mode for PWM outputs. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or -//! \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bInvert determines if the signal is inverted or passed through. //! //! This function is used to select the inversion mode for the selected PWM //! outputs. The outputs are selected using the parameter \e ulPWMOutBits. //! The parameter \e bInvert determines the inversion mode for the selected -//! outputs. If \e bInvert is \b true, this function will cause the specified -//! PWM output signals to be inverted, or made active low. If \e bInvert is -//! \b false, the specified output will be passed through as is, or be made -//! active high. +//! outputs. If \e bInvert is \b true, this function causes the specified +//! PWM output signals to be inverted or made active low. If \e bInvert is +//! \b false, the specified outputs are passed through as is or made active +//! high. //! //! \return None. // @@ -758,13 +758,13 @@ PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's INVERT output control register, and set or clear the + // Read the module's INVERT output control register and set or clear the // requested bits. // if(bInvert == true) @@ -783,20 +783,20 @@ PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, //! condition. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or -//! \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bDriveHigh determines if the signal is driven high or low during an //! active fault condition. //! //! This function determines whether a PWM output pin that is suppressed in -//! response to a fault condition will be driven high or low. The affected -//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! response to a fault condition is driven high or low. The affected outputs +//! are selected using the parameter \e ulPWMOutBits. The parameter //! \e bDriveHigh determines the output level for the pins identified by -//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs -//! will be driven high when a fault is detected. If it is \e false, the pins -//! will be driven low. +//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs are +//! driven high when a fault is detected. If it is \e false, the pins are +//! driven low. //! //! In a fault condition, pins which have not been configured to be suppressed //! via a call to PWMOutputFault() are unaffected by this function. @@ -814,14 +814,13 @@ PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, // // Check the arguments. // - ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's FAULT output control register, and set or clear the + // Read the module's FAULT output control register and set or clear the // requested bits. // if(bDriveHigh == true) @@ -839,10 +838,10 @@ PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, //! Specifies the state of PWM outputs in response to a fault condition. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or -//! \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bFaultSuppress determines if the signal is suppressed or passed //! through during an active fault condition. //! @@ -850,13 +849,13 @@ PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, //! outputs. The outputs are selected using the parameter \e ulPWMOutBits. //! The parameter \e bFaultSuppress determines the fault handling //! characteristics for the selected outputs. If \e bFaultSuppress is \b true, -//! then the selected outputs will be made inactive. If \e bFaultSuppress is +//! then the selected outputs are made inactive. If \e bFaultSuppress is //! \b false, then the selected outputs are unaffected by the detected fault. //! //! On devices supporting extended PWM fault handling, the state the affected //! output pins are driven to can be configured with PWMOutputFaultLevel(). If //! not configured, or if the device does not support extended PWM fault -//! handling, affected outputs will be driven low on a fault condition. +//! handling, affected outputs are driven low on a fault condition. //! //! \return None. // @@ -868,13 +867,13 @@ PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's FAULT output control register, and set or clear the + // Read the module's FAULT output control register and set or clear the // requested bits. // if(bFaultSuppress == true) @@ -887,19 +886,115 @@ PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, } } +//***************************************************************************** +// +//! Gets the PWM generator interrupt number. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function returns the interrupt number of the corresponding PWM +//! generator. +//! +//! \return Returns the interrupt number. +// +//***************************************************************************** +static unsigned long +PWMGenIntGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Determine the generator and PWM module in question. + // + switch(ulBase + ulGen) + { + // + // The first PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_0: + { + return(INT_PWM0_0); + } + + // + // The second PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_1: + { + return(INT_PWM0_1); + } + + // + // The third PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_2: + { + return(INT_PWM0_2); + } + + // + // The fourth PWM generator in the first PWM module. + // + case PWM0_BASE + PWM_GEN_3: + { + return(INT_PWM0_3); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_0: + { + return(INT_PWM1_0); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_1: + { + return(INT_PWM1_1); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_2: + { + return(INT_PWM1_2); + } + + // + // The first PWM generator in the second PWM module. + // + case PWM1_BASE + PWM_GEN_3: + { + return(INT_PWM1_3); + } + + // + // An unknown PWM module/generator was specified. + // + default: + { + return(0); + } + } +} + //***************************************************************************** // //! Registers an interrupt handler for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param pfnIntHandler is a pointer to the function to be called when the PWM //! generator interrupt occurs. //! -//! This function will ensure that the interrupt handler specified by +//! This function ensures that the interrupt handler specified by //! \e pfnIntHandler is called when an interrupt is detected for the specified -//! PWM generator block. This function will also enable the corresponding +//! PWM generator block. This function also enables the corresponding //! PWM generator interrupt in the interrupt controller; individual generator //! interrupts and interrupt sources must be enabled with PWMIntEnable() and //! PWMGenIntTrigEnable(). @@ -919,20 +1014,13 @@ PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // // Get the interrupt number associated with the specified generator. // - if(ulGen == PWM_GEN_3) - { - ulInt = INT_PWM3; - } - else - { - ulInt = INT_PWM0 + (ulGen >> 6) - 1; - } + ulInt = PWMGenIntGet(ulBase, ulGen); // // Register the interrupt handler. @@ -950,11 +1038,11 @@ PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, //! Removes an interrupt handler for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! -//! This function will unregister the interrupt handler for the specified -//! PWM generator block. This function will also disable the corresponding +//! This function unregisters the interrupt handler for the specified +//! PWM generator block. This function also disables the corresponding //! PWM generator interrupt in the interrupt controller; individual generator //! interrupts and interrupt sources must be disabled with PWMIntDisable() and //! PWMGenIntTrigDisable(). @@ -973,20 +1061,13 @@ PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // // Get the interrupt number associated with the specified generator. // - if(ulGen == PWM_GEN_3) - { - ulInt = INT_PWM3; - } - else - { - ulInt = INT_PWM0 + (ulGen >> 6) - 1; - } + ulInt = PWMGenIntGet(ulBase, ulGen); // // Disable the PWMx interrupt. @@ -999,6 +1080,27 @@ PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) IntUnregister(ulInt); } +//***************************************************************************** +// +//! Gets the PWM fault interrupt number. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function returns the fault interrupt number of the corresponding +//! PWM module. +//! +//! \return Returns the interrupt number. +// +//***************************************************************************** +static unsigned long +PWMFaultIntGet(unsigned long ulBase) +{ + // + // Return the fault interrupt number. + // + return((ulBase == PWM0_BASE) ? INT_PWM0_FAULT : INT_PWM1_FAULT); +} + //***************************************************************************** // //! Registers an interrupt handler for a fault condition detected in a PWM @@ -1008,9 +1110,9 @@ PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) //! \param pfnIntHandler is a pointer to the function to be called when the PWM //! fault interrupt occurs. //! -//! This function will ensure that the interrupt handler specified by +//! This function ensures that the interrupt handler specified by //! \e pfnIntHandler is called when a fault interrupt is detected for the -//! selected PWM module. This function will also enable the PWM fault +//! selected PWM module. This function also enables the PWM fault //! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the //! module level using PWMIntEnable(). //! @@ -1023,20 +1125,27 @@ PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) void PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) { + unsigned long ulInt; + // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + + // + // Get the interrupt number associated with the specified module. + // + ulInt = PWMFaultIntGet(ulBase); // // Register the interrupt handler, returning an error if one occurs. // - IntRegister(INT_PWM_FAULT, pfnIntHandler); + IntRegister(ulInt, pfnIntHandler); // // Enable the PWM fault interrupt. // - IntEnable(INT_PWM_FAULT); + IntEnable(ulInt); } //***************************************************************************** @@ -1045,8 +1154,8 @@ PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) //! //! \param ulBase is the base address of the PWM module. //! -//! This function will remove the interrupt handler for a PWM fault interrupt -//! from the selected PWM module. This function will also disable the PWM +//! This function removes the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function also disables the PWM //! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled //! at the module level using PWMIntDisable(). //! @@ -1059,20 +1168,27 @@ PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) void PWMFaultIntUnregister(unsigned long ulBase) { + unsigned long ulInt; + // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); + + // + // Get the interrupt number associated with the specified module. + // + ulInt = PWMFaultIntGet(ulBase); // // Disable the PWM fault interrupt. // - IntDisable(INT_PWM_FAULT); + IntDisable(ulInt); // // Unregister the interrupt handler, returning an error if one occurs. // - IntUnregister(INT_PWM_FAULT); + IntUnregister(ulInt); } //***************************************************************************** @@ -1081,12 +1197,13 @@ PWMFaultIntUnregister(unsigned long ulBase) //! //! \param ulBase is the base address of the PWM module. //! \param ulGen is the PWM generator to have interrupts and triggers enabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. //! \param ulIntTrig specifies the interrupts and triggers to be enabled. //! -//! Unmasks the specified interrupt(s) and trigger(s) by setting the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The \e ulIntTrig parameter is the logical OR of +//! This function unmasks the specified interrupt(s) and trigger(s) by setting +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ulIntTrig parameter is the logical OR of //! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, //! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, //! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, @@ -1102,7 +1219,7 @@ PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | @@ -1122,12 +1239,13 @@ PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, //! //! \param ulBase is the base address of the PWM module. //! \param ulGen is the PWM generator to have interrupts and triggers disabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. //! \param ulIntTrig specifies the interrupts and triggers to be disabled. //! -//! Masks the specified interrupt(s) and trigger(s) by clearing the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The \e ulIntTrig parameter is the logical OR of +//! This function masks the specified interrupt(s) and trigger(s) by clearing +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ulIntTrig parameter is the logical OR of //! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, //! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, //! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, @@ -1143,7 +1261,7 @@ PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | @@ -1162,16 +1280,16 @@ PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, //! Gets interrupt status for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param bMasked specifies whether masked or raw interrupt status is //! returned. //! //! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. +//! returned; otherwise, the raw interrupt status is returned. //! -//! \return Returns the contents of the interrupt status register, or the -//! contents of the raw interrupt status register, for the specified +//! \return Returns the contents of the interrupt status register or the +//! contents of the raw interrupt status register for the specified //! PWM generator. // //***************************************************************************** @@ -1181,7 +1299,7 @@ PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); // @@ -1208,24 +1326,24 @@ PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) //! Clears the specified interrupt(s) for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulInts specifies the interrupts to be cleared. //! -//! Clears the specified interrupt(s) by writing a 1 to the specified bits -//! of the interrupt status register for the specified PWM generator. The -//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO, -//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD, -//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. +//! This funciton clears the specified interrupt(s) by writing a 1 to the +//! specified bits of the interrupt status register for the specified PWM +//! generator. The \e ulInts parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1236,7 +1354,7 @@ PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == @@ -1254,13 +1372,13 @@ PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) //! Enables generator and fault interrupts for a PWM module. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be enabled. Must be a logical -//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, -//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, -//! or \b PWM_INT_FAULT3. +//! \param ulGenFault contains the interrupts to be enabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! -//! Unmasks the specified interrupt(s) by setting the specified bits of -//! the interrupt enable register for the selected PWM module. +//! This function unmasks the specified interrupt(s) by setting the specified +//! bits of the interrupt enable register for the selected PWM module. //! //! \return None. // @@ -1271,13 +1389,13 @@ PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); // - // Read the module's interrupt enable register, and enable interrupts + // Read the module's interrupt enable register and enable interrupts // for the specified PWM generators. // HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; @@ -1288,13 +1406,13 @@ PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) //! Disables generator and fault interrupts for a PWM module. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be disabled. Must be a -//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, -//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, -//! or \b PWM_INT_FAULT3. +//! \param ulGenFault contains the interrupts to be disabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! -//! Masks the specified interrupt(s) by clearing the specified bits of -//! the interrupt enable register for the selected PWM module. +//! This function masks the specified interrupt(s) by clearing the specified +//! bits of the interrupt enable register for the selected PWM module. //! //! \return None. // @@ -1305,13 +1423,13 @@ PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); // - // Read the module's interrupt enable register, and disable interrupts + // Read the module's interrupt enable register and disable interrupts // for the specified PWM generators. // HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); @@ -1323,22 +1441,22 @@ PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) //! //! \param ulBase is the base address of the PWM module. //! -//! Clears the fault interrupt by writing to the appropriate bit of the -//! interrupt status register for the selected PWM module. +//! This function clears the fault interrupt by writing to the appropriate bit +//! of the interrupt status register for the selected PWM module. //! //! This function clears only the FAULT0 interrupt and is retained for //! backwards compatibility. It is recommended that PWMFaultIntClearExt() be -//! used instead since it supports all fault interrupts supported on devices +//! used instead because it supports all fault interrupts supported on devices //! with and without extended PWM fault handling support. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1349,7 +1467,7 @@ PWMFaultIntClear(unsigned long ulBase) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); // // Write the only writeable bit in the module's interrupt register. @@ -1366,7 +1484,7 @@ PWMFaultIntClear(unsigned long ulBase) //! returned. //! //! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. +//! returned; otherwise, the raw interrupt status is returned. //! //! \return The current interrupt status, enumerated as a bit field of //! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, @@ -1380,7 +1498,7 @@ PWMIntStatus(unsigned long ulBase, tBoolean bMasked) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); // // Read and return either the module's raw or enabled interrupt status. @@ -1402,10 +1520,10 @@ PWMIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the base address of the PWM module. //! \param ulFaultInts specifies the fault interrupts to clear. //! -//! Clears one or more fault interrupts by writing to the appropriate bit of -//! the PWM interrupt status register. The parameter \e ulFaultInts must be -//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, -//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! This function clears one or more fault interrupts by writing to the +//! appropriate bit of the PWM interrupt status register. The parameter +//! \e ulFaultInts must be the logical OR of any of \b PWM_INT_FAULT0, +//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! //! When running on a device supporting extended PWM fault handling, the fault //! interrupts are derived by performing a logical OR of each of the configured @@ -1415,13 +1533,14 @@ PWMIntStatus(unsigned long ulBase, tBoolean bMasked) //! generators. On a device without extended PWM fault handling, the interrupt //! is directly related to the state of the single FAULT pin. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several cycles before the interrupt source is actually cleared. Therefore, -//! it is recommended that the interrupt source be cleared early in the -//! interrupt handler (as opposed to the very last action) to avoid returning -//! from the interrupt handler before the interrupt source is actually cleared. -//! Failure to do so may result in the interrupt handler being immediately -//! reentered (since NVIC still sees the interrupt source asserted). +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1432,7 +1551,7 @@ PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts) // // Check the arguments. // - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 | PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); @@ -1448,17 +1567,18 @@ PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts) //! PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault configuration is being set. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault configuration is being +//! set. This function must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, +//! or \b PWM_GEN_3. //! \param ulMinFaultPeriod is the minimum fault active period expressed in //! PWM clock cycles. //! \param ulFaultSenses indicates which sense of each FAULT input should be //! considered the ``asserted'' state. Valid values are logical OR //! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. //! -//! This function sets the minimum fault period for a given generator along -//! with the sense of each of the 4 possible fault inputs. The minimum fault -//! period is expressed in PWM clock cycles and takes effect only if +//! This function configures the minimum fault period for a given generator +//! along with the sense of each of the 4 possible fault inputs. The minimum +//! fault period is expressed in PWM clock cycles and takes effect only if //! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the //! \e ulConfig parameter. When a fault input is asserted, the minimum fault //! period timer ensures that it remains asserted for at least the number of @@ -1478,8 +1598,7 @@ PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, // // Check the arguments. // - ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M); ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW | @@ -1504,30 +1623,32 @@ PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, //! Configures the set of fault triggers for a given PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault triggers are being set. Must -//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault triggers are being set. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. //! \param ulGroup indicates the subset of possible faults that are to be -//! configured. This must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! configured. This parameter must be \b PWM_FAULT_GROUP_0 or +//! \b PWM_FAULT_GROUP_1. //! \param ulFaultTriggers defines the set of inputs that are to contribute //! towards generation of the fault signal to the given PWM generator. For -//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0, +//! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0, //! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. For -//! \b PWM_FAULT_GROUP_1, this will be the logical OR of \b PWM_FAULT_DCMP0, -//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b -//! PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b -//! PWM_FAULT_DCMP7. +//! \b PWM_FAULT_GROUP_1, this is the logical OR of \b PWM_FAULT_DCMP0, +//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, +//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or +//! \b PWM_FAULT_DCMP7. //! -//! This function allows selection of the set of fault inputs that will be -//! combined to generate a fault condition to a given PWM generator. By -//! default, all generators use only FAULT0 (for backwards compatibility) but -//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the +//! This function allows selection of the set of fault inputs that is combined +//! to generate a fault condition to a given PWM generator. By default, all +//! generators use only FAULT0 (for backwards compatibility) but if +//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the //! \e ulConfig parameter, extended fault handling is enabled and this function //! must be called to configure the fault triggers. //! //! The fault signal to the PWM generator is generated by ORing together each -//! of the signals whose inputs are specified in the \e ulFaultTriggers -//! parameter after having adjusted the sense of each FAULTn input based on the -//! configuration previously set using a call to PWMGenFaultConfigure(). +//! of the signals specified in the \e ulFaultTriggers parameter after having +//! adjusted the sense of each FAULTn input based on the configuration +//! previously set using a call to PWMGenFaultConfigure(). //! //! \note This function is only available on devices supporting extended PWM //! fault handling. @@ -1542,8 +1663,7 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, // // Check for valid parameters. // - ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); ASSERT((ulGroup == PWM_FAULT_GROUP_0) && @@ -1576,25 +1696,25 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, //! generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault triggers are being queried. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault triggers are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulGroup indicates the subset of faults that are being queried. This -//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. //! //! This function allows an application to query the current set of inputs that -//! contribute towards the generation of a fault condition to a given PWM -//! generator. -//! +//! contribute to the generation of a fault condition to a given PWM generator. +//! //! \note This function is only available on devices supporting extended PWM //! fault handling. //! //! \return Returns the current fault triggers configured for the fault group -//! provided. For \b PWM_FAULT_GROUP_0, the returned value will be a logical -//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or -//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value will be -//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, \b -//! PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, -//! \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. +//! provided. For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of +//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the +//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, +//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, +//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. // //***************************************************************************** unsigned long @@ -1604,8 +1724,7 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen, // // Check for valid parameters. // - ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); @@ -1627,17 +1746,17 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen, //! Returns the current state of the fault triggers for a given PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault trigger states are being -//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or -//! \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault trigger states are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulGroup indicates the subset of faults that are being queried. This -//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. //! //! This function allows an application to query the current state of each of //! the fault trigger inputs to a given PWM generator. The current state of //! each fault trigger input is returned unless PWMGenConfigure() has //! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the -//! \e ulConfig parameter in which case the returned status is the latched +//! \e ulConfig parameter, in which case the returned status is the latched //! fault trigger status. //! //! If latched faults are configured, the application must call @@ -1648,12 +1767,12 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen, //! //! \return Returns the current state of the fault triggers for the given PWM //! generator. A set bit indicates that the associated trigger is active. For -//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of +//! \b PWM_FAULT_GROUP_0, the returned value is a logical OR of //! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or -//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value will be -//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, \b -//! PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, -//! \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. +//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the +//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, +//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, +//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. // //***************************************************************************** unsigned long @@ -1663,8 +1782,7 @@ PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen, // // Check for valid parameters. // - ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); @@ -1686,17 +1804,18 @@ PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen, //! Clears one or more latched fault triggers for a given PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault trigger states are being -//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or -//! \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault trigger states are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulGroup indicates the subset of faults that are being queried. This -//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. //! \param ulFaultTriggers is the set of fault triggers which are to be //! cleared. //! //! This function allows an application to clear the fault triggers for a given -//! PWM generator. This is only required if PWMGenConfigure() has previously -//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig. +//! PWM generator. This function is only required if PWMGenConfigure() has +//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter +//! \e ulConfig. //! //! \note This function is only available on devices supporting extended PWM //! fault handling. @@ -1711,8 +1830,7 @@ PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, // // Check for valid parameters. // - ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); - ASSERT(ulBase == PWM_BASE); + ASSERT((ulBase == PWM0_BASE) || (ulBase == PWM1_BASE)); ASSERT(PWMGenValid(ulGen)); ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); ASSERT((ulGroup == PWM_FAULT_GROUP_0) && diff --git a/bsp/lm3s8962/Libraries/driverlib/pwm.h b/bsp/lm3s8962/Libraries/driverlib/pwm.h index 9714bff935..520adbc072 100644 --- a/bsp/lm3s8962/Libraries/driverlib/pwm.h +++ b/bsp/lm3s8962/Libraries/driverlib/pwm.h @@ -2,7 +2,7 @@ // // pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/qei.c b/bsp/lm3s8962/Libraries/driverlib/qei.c index 956fce3283..4c701a88a9 100644 --- a/bsp/lm3s8962/Libraries/driverlib/qei.c +++ b/bsp/lm3s8962/Libraries/driverlib/qei.c @@ -2,7 +2,7 @@ // // qei.c - Driver for the Quadrature Encoder with Index. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -43,8 +43,8 @@ //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will enable operation of the quadrature encoder module. It must be -//! configured before it is enabled. +//! This function enables operation of the quadrature encoder module. The +//! module must be configured before it is enabled. //! //! \sa QEIConfigure() //! @@ -71,7 +71,7 @@ QEIEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will disable operation of the quadrature encoder module. +//! This function disables operation of the quadrature encoder module. //! //! \return None. // @@ -99,22 +99,22 @@ QEIDisable(unsigned long ulBase) //! for a description of this parameter. //! \param ulMaxPosition specifies the maximum position value. //! -//! This will configure the operation of the quadrature encoder. The +//! This function configures the operation of the quadrature encoder. The //! \e ulConfig parameter provides the configuration of the encoder and is the //! logical OR of several values: //! -//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges //! on channel A or on both channels A and B should be counted by the //! position integrator and velocity accumulator. -//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the //! position integrator should be reset when the index pulse is detected. -//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if //! quadrature signals are being provided on ChA and ChB, or if a direction //! signal and a clock are being provided instead. //! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals //! provided on ChA and ChB should be swapped before being processed. //! -//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! \e ulMaxPosition is the maximum value of the position integrator and is //! the value used to reset the position capture when in index reset mode and //! moving in the reverse (negative) direction. //! @@ -150,11 +150,11 @@ QEIConfigure(unsigned long ulBase, unsigned long ulConfig, //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the current position of the encoder. Depending upon the -//! configuration of the encoder, and the incident of an index pulse, this +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this //! value may or may not contain the expected data (that is, if in reset on //! index mode, if an index pulse has not been encountered, the position -//! counter will not be aligned with the index pulse yet). +//! counter is not yet aligned with the index pulse). //! //! \return The current position of the encoder. // @@ -180,8 +180,8 @@ QEIPositionGet(unsigned long ulBase) //! \param ulBase is the base address of the quadrature encoder module. //! \param ulPosition is the new position for the encoder. //! -//! This sets the current position of the encoder; the encoder position will -//! then be measured relative to this value. +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. //! //! \return None. // @@ -206,9 +206,10 @@ QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the current direction of rotation. In this case, current -//! means the most recently detected direction of the encoder; it may not be -//! presently moving but this is the direction it last moved before it stopped. +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. //! //! \return Returns 1 if moving in the forward direction or -1 if moving in the //! reverse direction. @@ -234,9 +235,9 @@ QEIDirectionGet(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the error indicator for the quadrature encoder. It is an -//! error for both of the signals of the quadrature input to change at the same -//! time. +//! This function returns the error indicator for the quadrature encoder. It +//! is an error for both of the signals of the quadrature input to change at +//! the same time. //! //! \return Returns \b true if an error has occurred and \b false otherwise. // @@ -261,9 +262,9 @@ QEIErrorGet(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will enable operation of the velocity capture in the quadrature -//! encoder module. It must be configured before it is enabled. Velocity -//! capture will not occur if the quadrature encoder is not enabled. +//! This function enables operation of the velocity capture in the quadrature +//! encoder module. The module must be configured before velocity capture is +//! enabled. //! //! \sa QEIVelocityConfigure() and QEIEnable() //! @@ -290,7 +291,7 @@ QEIVelocityEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will disable operation of the velocity capture in the quadrature +//! This function disables operation of the velocity capture in the quadrature //! encoder module. //! //! \return None. @@ -322,8 +323,8 @@ QEIVelocityDisable(unsigned long ulBase) //! \param ulPeriod specifies the number of clock ticks over which to measure //! the velocity; must be non-zero. //! -//! This will configure the operation of the velocity capture portion of the -//! quadrature encoder. The position increment signal is predivided as +//! This function configures the operation of the velocity capture portion of +//! the quadrature encoder. The position increment signal is predivided as //! specified by \e ulPreDiv before being accumulated by the velocity capture. //! The divided signal is accumulated over \e ulPeriod system clock before //! being saved and resetting the accumulator. @@ -360,10 +361,10 @@ QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the current speed of the encoder. The value returned is the -//! number of pulses detected in the specified time period; this number can be -//! multiplied by the number of time periods per second and divided by the -//! number of pulses per revolution to obtain the number of revolutions per +//! This function returns the current speed of the encoder. The value returned +//! is the number of pulses detected in the specified time period; this number +//! can be multiplied by the number of time periods per second and divided by +//! the number of pulses per revolution to obtain the number of revolutions per //! second. //! //! \return Returns the number of pulses captured in the given time period. @@ -391,11 +392,11 @@ QEIVelocityGet(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! quadrature encoder interrupt occurs. //! -//! This sets the handler to be called when a quadrature encoder interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via QEIIntClear(). +//! This function registers the handler to be called when a quadrature encoder +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific quadrature encoder interrupts must be +//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via QEIIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -435,9 +436,9 @@ QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This function will clear the handler to be called when a quadrature encoder -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when a quadrature +//! encoder interrupt occurs. This function also masks off the interrupt in +//! the interrupt controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -480,9 +481,9 @@ QEIIntUnregister(unsigned long ulBase) //! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or //! \b QEI_INTINDEX values. //! -//! Enables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. +//! This function enables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -507,12 +508,12 @@ QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! //! \param ulBase is the base address of the quadrature encoder module. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or -//! \b QEI_INTINDEX values. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. //! -//! Disables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. +//! This function disables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -539,9 +540,9 @@ QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the quadrature encoder module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. +//! This function returns the interrupt status for the quadrature encoder +//! module. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. @@ -575,21 +576,22 @@ QEIIntStatus(unsigned long ulBase, tBoolean bMasked) //! //! \param ulBase is the base address of the quadrature encoder module. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or -//! \b QEI_INTINDEX values. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. //! //! The specified quadrature encoder interrupt sources are cleared, so that -//! they no longer assert. This must be done in the interrupt handler to keep -//! it from being called again immediately upon exit. +//! they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being triggered again immediately upon +//! exit. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // diff --git a/bsp/lm3s8962/Libraries/driverlib/qei.h b/bsp/lm3s8962/Libraries/driverlib/qei.h index 3f20a6a6fa..30c0858a51 100644 --- a/bsp/lm3s8962/Libraries/driverlib/qei.h +++ b/bsp/lm3s8962/Libraries/driverlib/qei.h @@ -2,7 +2,7 @@ // // qei.h - Prototypes for the Quadrature Encoder Driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/rom.h b/bsp/lm3s8962/Libraries/driverlib/rom.h index 8a9928a66f..0f1a029eef 100644 --- a/bsp/lm3s8962/Libraries/driverlib/rom.h +++ b/bsp/lm3s8962/Libraries/driverlib/rom.h @@ -2,7 +2,7 @@ // // rom.h - Macros to facilitate calling functions in the ROM. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -55,6 +55,12 @@ #define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21])) #define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[22])) #define ROM_EPITABLE ((unsigned long *)(ROM_APITABLE[23])) +#define ROM_FANTABLE ((unsigned long *)(ROM_APITABLE[25])) +#define ROM_FPUTABLE ((unsigned long *)(ROM_APITABLE[26])) +#define ROM_LPCTABLE ((unsigned long *)(ROM_APITABLE[27])) +#define ROM_PECITABLE ((unsigned long *)(ROM_APITABLE[28])) +#define ROM_SMBUSTABLE ((unsigned long *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((unsigned long *)(ROM_APITABLE[30])) //***************************************************************************** // @@ -63,7 +69,11 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceDataGet \ ((long (*)(unsigned long ulBase, \ unsigned long ulSequenceNum, \ @@ -71,21 +81,33 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulSequenceNum, \ @@ -93,28 +115,44 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum, \ @@ -123,7 +161,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceStepConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum, \ @@ -132,85 +174,178 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceOverflow \ ((long (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceOverflowClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceUnderflow \ ((long (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCSequenceUnderflowClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCProcessorTrigger \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCHardwareOversampleConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulFactor))ROM_ADCTABLE[14]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp, \ unsigned long ulConfig))ROM_ADCTABLE[15]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorRegionSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp, \ unsigned long ulLowRef, \ unsigned long ulHighRef))ROM_ADCTABLE[16]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorReset \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp, \ tBoolean bTrigger, \ tBoolean bInterrupt))ROM_ADCTABLE[17]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[18]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulSequenceNum))ROM_ADCTABLE[19]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorIntStatus \ ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[20]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ADCComparatorIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulStatus))ROM_ADCTABLE[21]) #endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_ADCReferenceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_ADCReferenceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPhase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_ADCPhaseDelayGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_ADCResolutionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulResolution))ROM_ADCTABLE[26]) +#endif +#if defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_ADCResolutionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[27]) +#endif //***************************************************************************** // @@ -218,40 +353,68 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntClr))ROM_CANTABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANInit \ ((void (*)(unsigned long ulBase))ROM_CANTABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANEnable \ ((void (*)(unsigned long ulBase))ROM_CANTABLE[2]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANDisable \ ((void (*)(unsigned long ulBase))ROM_CANTABLE[3]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANBitTimingSet \ ((void (*)(unsigned long ulBase, \ tCANBitClkParms *pClkParms))ROM_CANTABLE[4]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANBitTimingGet \ ((void (*)(unsigned long ulBase, \ tCANBitClkParms *pClkParms))ROM_CANTABLE[5]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANMessageSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulObjID, \ @@ -259,7 +422,11 @@ tMsgObjType eMsgType))ROM_CANTABLE[6]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANMessageGet \ ((void (*)(unsigned long ulBase, \ unsigned long ulObjID, \ @@ -267,54 +434,90 @@ tBoolean bClrPendingInt))ROM_CANTABLE[7]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANStatusGet \ ((unsigned long (*)(unsigned long ulBase, \ tCANStsReg eStatusReg))ROM_CANTABLE[8]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANMessageClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulObjID))ROM_CANTABLE[9]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_CANTABLE[10]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_CANTABLE[11]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANRetryGet \ ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANRetrySet \ ((void (*)(unsigned long ulBase, \ tBoolean bAutoRetry))ROM_CANTABLE[14]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANErrCntrGet \ ((tBoolean (*)(unsigned long ulBase, \ unsigned long *pulRxCount, \ unsigned long *pulTxCount))ROM_CANTABLE[15]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_CANBitRateSet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulSourceClock, \ @@ -328,14 +531,22 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp))ROM_COMPARATORTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp, \ @@ -343,35 +554,55 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorRefSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulRef))ROM_COMPARATORTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorValueGet \ ((tBoolean (*)(unsigned long ulBase, \ unsigned long ulComp))ROM_COMPARATORTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp))ROM_COMPARATORTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulComp))ROM_COMPARATORTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_ComparatorIntStatus \ ((tBoolean (*)(unsigned long ulBase, \ unsigned long ulComp, \ @@ -380,123 +611,189 @@ //***************************************************************************** // -// Macros for calling ROM functions in the Ethernet API. +// Macros for calling ROM functions in the EPI API. // //***************************************************************************** -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_EPITABLE[0]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIModeSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulMode))ROM_EPITABLE[1]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIDividerSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulDivider))ROM_EPITABLE[2]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIConfigSDRAMSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig, \ unsigned long ulRefresh))ROM_EPITABLE[3]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIConfigGPModeSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig, \ unsigned long ulFrameCount, \ unsigned long ulMaxWait))ROM_EPITABLE[4]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIConfigHB8Set \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig, \ unsigned long ulMaxWait))ROM_EPITABLE[5]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIConfigHB16Set \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig, \ unsigned long ulMaxWait))ROM_EPITABLE[6]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIAddressMapSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulMap))ROM_EPITABLE[7]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulChannel, \ unsigned long ulDataSize, \ unsigned long ulAddress))ROM_EPITABLE[8]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadStart \ ((void (*)(unsigned long ulBase, \ unsigned long ulChannel, \ unsigned long ulCount))ROM_EPITABLE[9]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadStop \ ((void (*)(unsigned long ulBase, \ unsigned long ulChannel))ROM_EPITABLE[10]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadCount \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulChannel))ROM_EPITABLE[11]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadAvail \ ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[12]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadGet32 \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulCount, \ unsigned long *pulBuf))ROM_EPITABLE[13]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadGet16 \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulCount, \ unsigned short *pusBuf))ROM_EPITABLE[14]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPINonBlockingReadGet8 \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulCount, \ unsigned char *pucBuf))ROM_EPITABLE[15]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIFIFOConfig \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig))ROM_EPITABLE[16]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIWriteFIFOCountGet \ ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[17]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_EPITABLE[18]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_EPITABLE[19]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIIntErrorStatus \ ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[20]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EPIIntErrorClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulErrFlags))ROM_EPITABLE[21]) @@ -508,124 +805,279 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_ETHERNETTABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetInitExpClk \ ((void (*)(unsigned long ulBase, \ unsigned long ulEthClk))ROM_ETHERNETTABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetConfigSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig))ROM_ETHERNETTABLE[2]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetConfigGet \ ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetMACAddrSet \ ((void (*)(unsigned long ulBase, \ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetMACAddrGet \ ((void (*)(unsigned long ulBase, \ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetEnable \ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetDisable \ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPacketAvail \ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetSpaceAvail \ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPacketGetNonBlocking \ ((long (*)(unsigned long ulBase, \ unsigned char *pucBuf, \ long lBufLen))ROM_ETHERNETTABLE[10]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPacketGet \ ((long (*)(unsigned long ulBase, \ unsigned char *pucBuf, \ long lBufLen))ROM_ETHERNETTABLE[11]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPacketPutNonBlocking \ ((long (*)(unsigned long ulBase, \ unsigned char *pucBuf, \ long lBufLen))ROM_ETHERNETTABLE[12]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPacketPut \ ((long (*)(unsigned long ulBase, \ unsigned char *pucBuf, \ long lBufLen))ROM_ETHERNETTABLE[13]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_ETHERNETTABLE[14]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_ETHERNETTABLE[15]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_ETHERNETTABLE[16]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPHYWrite \ ((void (*)(unsigned long ulBase, \ unsigned char ucRegAddr, \ unsigned long ulData))ROM_ETHERNETTABLE[17]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_EthernetPHYRead \ ((unsigned long (*)(unsigned long ulBase, \ unsigned char ucRegAddr))ROM_ETHERNETTABLE[18]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_UpdateEthernet \ ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19]) #endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr))ROM_ETHERNETTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYPowerOff \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYPowerOn \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Fan API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelConfigAuto \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig))ROM_FANTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelConfigManual \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig))ROM_FANTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelDutyGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelDutySet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulDuty))ROM_FANTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelRPMGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelRPMSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulRPM))ROM_FANTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanChannelsGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_FANTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FanIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_FANTABLE[13]) +#endif //***************************************************************************** // @@ -634,7 +1086,11 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashProgram \ ((long (*)(unsigned long *pulData, \ unsigned long ulAddress, \ @@ -642,86 +1098,180 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashUsecGet \ ((unsigned long (*)(void))ROM_FLASHTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashUsecSet \ ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashErase \ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashProtectGet \ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashProtectSet \ ((long (*)(unsigned long ulAddress, \ tFlashProtection eProtect))ROM_FLASHTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashProtectSave \ ((long (*)(void))ROM_FLASHTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashUserGet \ ((long (*)(unsigned long *pulUser0, \ unsigned long *pulUser1))ROM_FLASHTABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashUserSet \ ((long (*)(unsigned long ulUser0, \ unsigned long ulUser1))ROM_FLASHTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashUserSave \ ((long (*)(void))ROM_FLASHTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashIntEnable \ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashIntDisable \ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashIntStatus \ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_FlashIntClear \ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13]) #endif +//***************************************************************************** +// +// Macros for calling ROM functions in the FPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUNaNModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPURoundingModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + //***************************************************************************** // // Macros for calling ROM functions in the GPIO API. @@ -729,7 +1279,11 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinWrite \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins, \ @@ -737,7 +1291,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIODirModeSet \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins, \ @@ -745,14 +1303,22 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIODirModeGet \ ((unsigned long (*)(unsigned long ulPort, \ unsigned char ucPin))ROM_GPIOTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOIntTypeSet \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins, \ @@ -760,14 +1326,22 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOIntTypeGet \ ((unsigned long (*)(unsigned long ulPort, \ unsigned char ucPin))ROM_GPIOTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPadConfigSet \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins, \ @@ -776,7 +1350,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPadConfigGet \ ((void (*)(unsigned long ulPort, \ unsigned char ucPin, \ @@ -785,147 +1363,287 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinIntEnable \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinIntDisable \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinIntStatus \ ((long (*)(unsigned long ulPort, \ tBoolean bMasked))ROM_GPIOTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinIntClear \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinRead \ ((long (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeCAN \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeComparator \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeGPIOInput \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[14]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeGPIOOutput \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[15]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeI2C \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[16]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypePWM \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[17]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeQEI \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[18]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeSSI \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[19]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeTimer \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[20]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeUART \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[21]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeGPIOOutputOD \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[22]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeADC \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[23]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeUSBDigital \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[24]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_GPIOPinTypeI2S \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[25]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinConfigure \ ((void (*)(unsigned long ulPinConfig))ROM_GPIOTABLE[26]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_GPIOPinTypeEthernetLED \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[27]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_GPIOPinTypeUSBAnalog \ ((void (*)(unsigned long ulPort, \ unsigned char ucPins))ROM_GPIOTABLE[28]) #endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEPI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEthernetMII \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIOPinTypeFan \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIOPinTypeLPC \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIOPinTypePECIRx \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_GPIOPinTypePECITx \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[38]) +#endif //***************************************************************************** // @@ -933,131 +1651,253 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateIntClear \ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateEnableExpClk \ ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateDisable \ ((void (*)(void))ROM_HIBERNATETABLE[2]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateClockSelect \ ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCEnable \ ((void (*)(void))ROM_HIBERNATETABLE[4]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCDisable \ ((void (*)(void))ROM_HIBERNATETABLE[5]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateWakeSet \ ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateWakeGet \ ((unsigned long (*)(void))ROM_HIBERNATETABLE[7]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateLowBatSet \ ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateLowBatGet \ ((unsigned long (*)(void))ROM_HIBERNATETABLE[9]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCSet \ ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCGet \ ((unsigned long (*)(void))ROM_HIBERNATETABLE[11]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCMatch0Set \ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCMatch0Get \ ((unsigned long (*)(void))ROM_HIBERNATETABLE[13]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_HibernateRTCMatch1Set \ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_HibernateRTCMatch1Get \ ((unsigned long (*)(void))ROM_HIBERNATETABLE[15]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCTrimSet \ ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRTCTrimGet \ ((unsigned long (*)(void))ROM_HIBERNATETABLE[17]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateDataSet \ ((void (*)(unsigned long *pulData, \ unsigned long ulCount))ROM_HIBERNATETABLE[18]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateDataGet \ ((void (*)(unsigned long *pulData, \ unsigned long ulCount))ROM_HIBERNATETABLE[19]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateRequest \ ((void (*)(void))ROM_HIBERNATETABLE[20]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateIntEnable \ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateIntDisable \ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateIntStatus \ ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_HibernateIsActive \ - ((unsigned int (*)(void))ROM_HIBERNATETABLE[24]) + ((unsigned long (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_HibernateRTCSSMatch0Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_HibernateRTCSSMatch0Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_HibernateRTCSSGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_HibernateClockConfig \ + ((void (*)(unsigned long ulConfig))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_HibernateBatCheckDone \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[30]) #endif //***************************************************************************** @@ -1067,14 +1907,22 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterDataPut \ ((void (*)(unsigned long ulBase, \ unsigned char ucData))ROM_I2CTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterInitExpClk \ ((void (*)(unsigned long ulBase, \ unsigned long ulI2CClk, \ @@ -1082,88 +1930,144 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveInit \ ((void (*)(unsigned long ulBase, \ unsigned char ucSlaveAddr))ROM_I2CTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterEnable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveEnable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterDisable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveDisable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterIntEnable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntEnable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterIntDisable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntDisable \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterIntStatus \ ((tBoolean (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_I2CTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntStatus \ ((tBoolean (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_I2CTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterIntClear \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntClear \ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterSlaveAddrSet \ ((void (*)(unsigned long ulBase, \ unsigned char ucSlaveAddr, \ @@ -1171,192 +2075,361 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterBusy \ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterBusBusy \ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterControl \ ((void (*)(unsigned long ulBase, \ unsigned long ulCmd))ROM_I2CTABLE[18]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterErr \ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CMasterDataGet \ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveStatus \ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveDataPut \ ((void (*)(unsigned long ulBase, \ unsigned char ucData))ROM_I2CTABLE[22]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveDataGet \ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UpdateI2C \ ((void (*)(void))ROM_I2CTABLE[24]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntEnableEx \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_I2CTABLE[25]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntDisableEx \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_I2CTABLE[26]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntStatusEx \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_I2CTABLE[27]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_I2CSlaveIntClearEx \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_I2CTABLE[28]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CMasterIntStatusEx \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulValue))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(unsigned long ulBase, \ + tBoolean bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(unsigned long ulBase, \ + tBoolean bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddrNum, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_I2CMasterLineStateGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[38]) +#endif //***************************************************************************** // // Macros for calling ROM functions in the I2S API. // //***************************************************************************** -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_I2STABLE[0]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxEnable \ ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxDisable \ ((void (*)(unsigned long ulBase))ROM_I2STABLE[2]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxDataPut \ ((void (*)(unsigned long ulBase, \ unsigned long ulData))ROM_I2STABLE[3]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxDataPutNonBlocking \ ((long (*)(unsigned long ulBase, \ unsigned long ulData))ROM_I2STABLE[4]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxConfigSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig))ROM_I2STABLE[5]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxFIFOLimitSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulLevel))ROM_I2STABLE[6]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxFIFOLimitGet \ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[7]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxFIFOLevelGet \ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[8]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxEnable \ ((void (*)(unsigned long ulBase))ROM_I2STABLE[9]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxDisable \ ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxDataGet \ ((void (*)(unsigned long ulBase, \ unsigned long *pulData))ROM_I2STABLE[11]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxDataGetNonBlocking \ ((long (*)(unsigned long ulBase, \ unsigned long *pulData))ROM_I2STABLE[12]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxConfigSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig))ROM_I2STABLE[13]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxFIFOLimitSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulLevel))ROM_I2STABLE[14]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxFIFOLimitGet \ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[15]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SRxFIFOLevelGet \ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxRxEnable \ ((void (*)(unsigned long ulBase))ROM_I2STABLE[17]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxRxDisable \ ((void (*)(unsigned long ulBase))ROM_I2STABLE[18]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2STxRxConfigSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig))ROM_I2STABLE[19]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SMasterClockSelect \ ((void (*)(unsigned long ulBase, \ unsigned long ulMClock))ROM_I2STABLE[20]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_I2STABLE[21]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_I2STABLE[22]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_I2SIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_I2STABLE[23]) @@ -1369,59 +2442,319 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntEnable \ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntMasterEnable \ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntMasterDisable \ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntDisable \ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntPriorityGroupingSet \ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntPriorityGroupingGet \ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntPrioritySet \ ((void (*)(unsigned long ulInterrupt, \ unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntPriorityGet \ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntPendSet \ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_IntPendClear \ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) #endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_IntPriorityMaskSet \ + ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_IntPriorityMaskGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the LPC API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCByteRead \ + ((unsigned char (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCByteWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned char ucData))ROM_LPCTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelConfigCOMxSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset, \ + unsigned long ulCOMxMode))ROM_LPCTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelConfigGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long *pulAddress, \ + unsigned long *pulOffset, \ + unsigned long *pulCOMxMode))ROM_LPCTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelConfigEPSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset))ROM_LPCTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelConfigMBSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset))ROM_LPCTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelDMAConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelDMAConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMask))ROM_LPCTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulStatus))ROM_LPCTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelStatusSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulStatus))ROM_LPCTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCCOMxIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCCOMxIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCCOMxIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCCOMxIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_LPCTABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_LPCTABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCHalfWordRead \ + ((unsigned short (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[20]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCHalfWordWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned short usData))ROM_LPCTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIRQClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIRQ))ROM_LPCTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIRQConfig \ + ((void (*)(unsigned long ulBase, \ + tBoolean bIRQPulse, \ + tBoolean bIRQOnChange))ROM_LPCTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIRQGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIRQSend \ + ((void (*)(unsigned long ulBase))ROM_LPCTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIRQSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIRQ))ROM_LPCTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_LPCTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCSCIAssert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCount))ROM_LPCTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long *pulCount, \ + unsigned long *pulPoolSize))ROM_LPCTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCWordRead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCWordWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned long ulData))ROM_LPCTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCChannelPoolAddressGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCStatusBlockAddressGet \ + ((unsigned (*)(unsigned long ulBase))ROM_LPCTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_LPCStatusBlockAddressSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulAddress, \ + tBoolean bEnabled))ROM_LPCTABLE[36]) +#endif //***************************************************************************** // @@ -1429,45 +2762,200 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPUEnable \ ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPUDisable \ ((void (*)(void))ROM_MPUTABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPURegionCountGet \ ((unsigned long (*)(void))ROM_MPUTABLE[2]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPURegionEnable \ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPURegionDisable \ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPURegionSet \ ((void (*)(unsigned long ulRegion, \ unsigned long ulAddr, \ unsigned long ulFlags))ROM_MPUTABLE[5]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_MPURegionGet \ ((void (*)(unsigned long ulRegion, \ unsigned long *pulAddr, \ unsigned long *pulFlags))ROM_MPUTABLE[6]) #endif +//***************************************************************************** +// +// Macros for calling ROM functions in the PECI API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_PECITABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIAdvCmdSend \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucCmd, \ + unsigned char ucHidRe, \ + unsigned char ucDomain, \ + unsigned char ucProcAdd, \ + unsigned long ulArg, \ + unsigned char ucSize, \ + unsigned long ulData0, \ + unsigned long ulData1))ROM_PECITABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIAdvCmdSendNonBlocking \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned char ucCmd, \ + unsigned char ucHidRe, \ + unsigned char ucDomain, \ + unsigned char ucProcAdd, \ + unsigned long ulArg, \ + unsigned char ucSize, \ + unsigned long ulData0, \ + unsigned long ulData1))ROM_PECITABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIAdvCmdStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long *pulData0, \ + unsigned long *pulData1))ROM_PECITABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPECIClk, \ + unsigned long *pulBaud, \ + unsigned long *pulPoll, \ + unsigned long *pulOffset, \ + unsigned long *pulRetry))ROM_PECITABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPECIClk, \ + unsigned long ulBaud, \ + unsigned long ulPoll, \ + unsigned long ulOffset, \ + unsigned long ulRetry))ROM_PECITABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainMaxReadClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainValueClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain, \ + unsigned long *pulHigh, \ + unsigned long *pulLow))ROM_PECITABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain, \ + unsigned long ulHigh, \ + unsigned long ulLow))ROM_PECITABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainMaxReadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIDomainValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_PECITABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags, \ + unsigned long ulIntMode))ROM_PECITABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PECITABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIBypassEnable \ + ((void (*)(unsigned long ulBase))ROM_PECITABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_PECIBypassDisable \ + ((void (*)(unsigned long ulBase))ROM_PECITABLE[18]) +#endif + //***************************************************************************** // // Macros for calling ROM functions in the PWM API. @@ -1475,7 +2963,11 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMPulseWidthSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulPWMOut, \ @@ -1483,7 +2975,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1491,7 +2987,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenPeriodSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1499,35 +2999,55 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenPeriodGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulGen))ROM_PWMTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen))ROM_PWMTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen))ROM_PWMTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMPulseWidthGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulPWMOut))ROM_PWMTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMDeadBandEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1536,28 +3056,44 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMDeadBandDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen))ROM_PWMTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMSyncUpdate \ ((void (*)(unsigned long ulBase, \ unsigned long ulGenBits))ROM_PWMTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMSyncTimeBase \ ((void (*)(unsigned long ulBase, \ unsigned long ulGenBits))ROM_PWMTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMOutputState \ ((void (*)(unsigned long ulBase, \ unsigned long ulPWMOutBits, \ @@ -1565,7 +3101,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMOutputInvert \ ((void (*)(unsigned long ulBase, \ unsigned long ulPWMOutBits, \ @@ -1573,7 +3113,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMOutputFault \ ((void (*)(unsigned long ulBase, \ unsigned long ulPWMOutBits, \ @@ -1581,7 +3125,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenIntTrigEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1589,7 +3137,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenIntTrigDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1597,7 +3149,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1605,7 +3161,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1613,46 +3173,74 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGenFault))ROM_PWMTABLE[18]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulGenFault))ROM_PWMTABLE[19]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMFaultIntClear \ ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_PWMTABLE[21]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMOutputFaultLevel \ ((void (*)(unsigned long ulBase, \ unsigned long ulPWMOutBits, \ tBoolean bDriveHigh))ROM_PWMTABLE[22]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMFaultIntClearExt \ ((void (*)(unsigned long ulBase, \ unsigned long ulFaultInts))ROM_PWMTABLE[23]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenFaultConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1660,7 +3248,11 @@ unsigned long ulFaultSenses))ROM_PWMTABLE[24]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenFaultTriggerSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1668,21 +3260,33 @@ unsigned long ulFaultTriggers))ROM_PWMTABLE[25]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenFaultTriggerGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulGen, \ unsigned long ulGroup))ROM_PWMTABLE[26]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenFaultStatus \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulGen, \ unsigned long ulGroup))ROM_PWMTABLE[27]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_PWMGenFaultClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulGen, \ @@ -1697,25 +3301,41 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIPositionGet \ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIEnable \ ((void (*)(unsigned long ulBase))ROM_QEITABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIDisable \ ((void (*)(unsigned long ulBase))ROM_QEITABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig, \ @@ -1723,38 +3343,62 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIPositionSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulPosition))ROM_QEITABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIDirectionGet \ ((long (*)(unsigned long ulBase))ROM_QEITABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIErrorGet \ ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIVelocityEnable \ ((void (*)(unsigned long ulBase))ROM_QEITABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIVelocityDisable \ ((void (*)(unsigned long ulBase))ROM_QEITABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIVelocityConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulPreDiv, \ @@ -1762,39 +3406,344 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIVelocityGet \ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_QEITABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_QEITABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_QEITABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_QEIIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_QEITABLE[14]) #endif +//***************************************************************************** +// +// Macros for calling ROM functions in the SMBus API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + unsigned char *pucAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + unsigned char ucAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucTxData, \ + unsigned char ucTxSize, \ + unsigned char *pucRxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucData))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucOwnSlaveAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucTxData, \ + unsigned char ucTxSize, \ + unsigned char *pucRxData, \ + unsigned char ucRxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *pSMBus, \ + unsigned long ulI2CBase, \ + unsigned long ulSMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucTxData, \ + unsigned char *pucRxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + tBoolean bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusRxPacketSizeGet \ + ((unsigned char (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char ucAddressNum, \ + unsigned char ucSlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveARPFlagARGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveCommandGet \ + ((unsigned char (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *pSMBus, \ + unsigned long ulI2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *pSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[54]) +#endif + //***************************************************************************** // // Macros for calling ROM functions in the SSI API. @@ -1802,14 +3751,22 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDataPut \ ((void (*)(unsigned long ulBase, \ unsigned long ulData))ROM_SSITABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIConfigSetExpClk \ ((void (*)(unsigned long ulBase, \ unsigned long ulSSIClk, \ @@ -1820,87 +3777,148 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIEnable \ ((void (*)(unsigned long ulBase))ROM_SSITABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDisable \ ((void (*)(unsigned long ulBase))ROM_SSITABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_SSITABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_SSITABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_SSITABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_SSITABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDataPutNonBlocking \ ((long (*)(unsigned long ulBase, \ unsigned long ulData))ROM_SSITABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDataGet \ ((void (*)(unsigned long ulBase, \ unsigned long *pulData))ROM_SSITABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDataGetNonBlocking \ ((long (*)(unsigned long ulBase, \ unsigned long *pulData))ROM_SSITABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UpdateSSI \ ((void (*)(void))ROM_SSITABLE[11]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDMAEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulDMAFlags))ROM_SSITABLE[12]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIDMADisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulDMAFlags))ROM_SSITABLE[13]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SSIBusy \ ((tBoolean (*)(unsigned long ulBase))ROM_SSITABLE[14]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SSIClockSourceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SSIClockSourceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSource))ROM_SSITABLE[16]) +#endif //***************************************************************************** // @@ -1909,209 +3927,392 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlSleep \ ((void (*)(void))ROM_SYSCTLTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlSRAMSizeGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlFlashSizeGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPinPresent \ ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralPresent \ ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralReset \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralEnable \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralDisable \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralSleepEnable \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralSleepDisable \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralDeepSleepEnable \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralDeepSleepDisable \ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPeripheralClockGating \ ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlIntEnable \ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlIntDisable \ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlIntClear \ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlIntStatus \ ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_SysCtlLDOSet \ ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_SysCtlLDOGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[18]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlReset \ ((void (*)(void))ROM_SYSCTLTABLE[19]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlDeepSleep \ ((void (*)(void))ROM_SYSCTLTABLE[20]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlResetCauseGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[21]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlResetCauseClear \ ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlClockSet \ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlClockGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[24]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPWMClockSet \ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlPWMClockGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[26]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlADCSpeedSet \ ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlADCSpeedGet \ ((unsigned long (*)(void))ROM_SYSCTLTABLE[28]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlGPIOAHBEnable \ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlGPIOAHBDisable \ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlUSBPLLEnable \ ((void (*)(void))ROM_SYSCTLTABLE[31]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlUSBPLLDisable \ ((void (*)(void))ROM_SYSCTLTABLE[32]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) #define ROM_SysCtlI2SMClkSet \ ((unsigned long (*)(unsigned long ulInputClock, \ unsigned long ulMClk))ROM_SYSCTLTABLE[33]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysCtlDelay \ ((void (*)(unsigned long ulCount))ROM_SYSCTLTABLE[34]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysCtlPeripheralReady \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysCtlPIOSCCalibrate \ + ((unsigned long (*)(unsigned long ulType))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[46]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysExc API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysExcIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysExcIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysExcIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_SysExcIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[3]) +#endif //***************************************************************************** // @@ -2120,43 +4321,71 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickValueGet \ ((unsigned long (*)(void))ROM_SYSTICKTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickEnable \ ((void (*)(void))ROM_SYSTICKTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickDisable \ ((void (*)(void))ROM_SYSTICKTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickIntEnable \ ((void (*)(void))ROM_SYSTICKTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickIntDisable \ ((void (*)(void))ROM_SYSTICKTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickPeriodSet \ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_SysTickPeriodGet \ ((unsigned long (*)(void))ROM_SYSTICKTABLE[6]) #endif @@ -2168,35 +4397,55 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_TIMERTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer))ROM_TIMERTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer))ROM_TIMERTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerConfigure \ ((void (*)(unsigned long ulBase, \ unsigned long ulConfig))ROM_TIMERTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerControlLevel \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ @@ -2204,15 +4453,17 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerControlTrigger \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ tBoolean bEnable))ROM_TIMERTABLE[5]) #endif -#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ - defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerControlEvent \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ @@ -2220,7 +4471,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerControlStall \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ @@ -2228,19 +4483,31 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerRTCEnable \ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerRTCDisable \ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerPrescaleSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ @@ -2248,14 +4515,39 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerPrescaleGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulTimer))ROM_TIMERTABLE[11]) #endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerPrescaleMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[13]) +#endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerLoadSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ @@ -2263,21 +4555,33 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerLoadGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulTimer))ROM_TIMERTABLE[15]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerValueGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulTimer))ROM_TIMERTABLE[16]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerMatchSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulTimer, \ @@ -2285,32 +4589,79 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerMatchGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulTimer))ROM_TIMERTABLE[18]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_TIMERTABLE[19]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_TIMERTABLE[20]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_TimerIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_TIMERTABLE[21]) #endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerLoadSet64 \ + ((void (*)(unsigned long ulBase, \ + unsigned long long ullValue))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerLoadGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerValueGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerMatchSet64 \ + ((void (*)(unsigned long ulBase, \ + unsigned long long ullValue))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_TimerMatchGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[27]) +#endif //***************************************************************************** // @@ -2319,27 +4670,43 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTCharPut \ ((void (*)(unsigned long ulBase, \ unsigned char ucData))ROM_UARTTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTParityModeSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulParity))ROM_UARTTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTParityModeGet \ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTFIFOLevelSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulTxLevel, \ @@ -2347,7 +4714,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTFIFOLevelGet \ ((void (*)(unsigned long ulBase, \ unsigned long *pulTxLevel, \ @@ -2355,7 +4726,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTConfigSetExpClk \ ((void (*)(unsigned long ulBase, \ unsigned long ulUARTClk, \ @@ -2364,7 +4739,11 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTConfigGetExpClk \ ((void (*)(unsigned long ulBase, \ unsigned long ulUARTClk, \ @@ -2373,142 +4752,266 @@ #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTEnable \ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTDisable \ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTEnableSIR \ ((void (*)(unsigned long ulBase, \ tBoolean bLowPower))ROM_UARTTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTDisableSIR \ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTCharsAvail \ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTSpaceAvail \ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTCharGetNonBlocking \ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTCharGet \ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTCharPutNonBlocking \ ((tBoolean (*)(unsigned long ulBase, \ unsigned char ucData))ROM_UARTTABLE[15]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTBreakCtl \ ((void (*)(unsigned long ulBase, \ tBoolean bBreakState))ROM_UARTTABLE[16]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_UARTTABLE[17]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_UARTTABLE[18]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_UARTTABLE[19]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTIntClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_UARTTABLE[20]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UpdateUART \ ((void (*)(void))ROM_UARTTABLE[21]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTDMAEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulDMAFlags))ROM_UARTTABLE[22]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTDMADisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulDMAFlags))ROM_UARTTABLE[23]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTFIFOEnable \ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[24]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTFIFODisable \ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[25]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTBusy \ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[26]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTTxIntModeSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulMode))ROM_UARTTABLE[27]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTTxIntModeGet \ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[28]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTRxErrorGet \ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[29]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_UARTRxErrorClear \ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[30]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_UARTClockSourceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSource))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_UARTClockSourceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_UART9BitEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_UART9BitDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_UART9BitAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr, \ + unsigned char ucMask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_UART9BitAddrSend \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr))ROM_UARTTABLE[36]) +#endif //***************************************************************************** // @@ -2516,105 +5019,206 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelTransferSet \ - ((void (*)(unsigned long ulChannel, \ + ((void (*)(unsigned long ulChannelStructIndex, \ unsigned long ulMode, \ void *pvSrcAddr, \ void *pvDstAddr, \ unsigned long ulTransferSize))ROM_UDMATABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAEnable \ ((void (*)(void))ROM_UDMATABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMADisable \ ((void (*)(void))ROM_UDMATABLE[2]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAErrorStatusGet \ ((unsigned long (*)(void))ROM_UDMATABLE[3]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAErrorStatusClear \ ((void (*)(void))ROM_UDMATABLE[4]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelEnable \ - ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[5]) + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelDisable \ - ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[6]) + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelIsEnabled \ - ((tBoolean (*)(unsigned long ulChannel))ROM_UDMATABLE[7]) + ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAControlBaseSet \ ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAControlBaseGet \ ((void * (*)(void))ROM_UDMATABLE[9]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelRequest \ - ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[10]) + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelAttributeEnable \ - ((void (*)(unsigned long ulChannel, \ + ((void (*)(unsigned long ulChannelNum, \ unsigned long ulAttr))ROM_UDMATABLE[11]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelAttributeDisable \ - ((void (*)(unsigned long ulChannel, \ + ((void (*)(unsigned long ulChannelNum, \ unsigned long ulAttr))ROM_UDMATABLE[12]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelAttributeGet \ - ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[13]) + ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelControlSet \ - ((void (*)(unsigned long ulChannel, \ + ((void (*)(unsigned long ulChannelStructIndex, \ unsigned long ulControl))ROM_UDMATABLE[14]) #endif -#if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelSizeGet \ - ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[15]) + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelModeGet \ - ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[16]) + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelSelectSecondary \ ((void (*)(unsigned long ulSecPeriphs))ROM_UDMATABLE[17]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_uDMAChannelSelectDefault \ ((void (*)(unsigned long ulDefPeriphs))ROM_UDMATABLE[18]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_uDMAIntStatus \ + ((unsigned long (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_uDMAIntClear \ + ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned ulTaskCount, \ + void *pvTaskList, \ + unsigned long ulIsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_uDMAChannelAssign \ + ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[23]) +#endif //***************************************************************************** // @@ -2622,33 +5226,57 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntStatus \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevAddrGet \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevAddrSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulAddress))ROM_USBTABLE[2]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevConnect \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[3]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevDisconnect \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[4]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevEndpointConfigSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2656,35 +5284,52 @@ unsigned long ulFlags))ROM_USBTABLE[5]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevEndpointDataAck \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ tBoolean bIsLastPacket))ROM_USBTABLE[6]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevEndpointStall \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[7]) #endif -#if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevEndpointStallClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[8]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevEndpointStatusClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[9]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDataGet \ ((long (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2692,7 +5337,11 @@ unsigned long *pulSize))ROM_USBTABLE[10]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDataPut \ ((long (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2700,33 +5349,53 @@ unsigned long ulSize))ROM_USBTABLE[11]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDataSend \ ((long (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulTransType))ROM_USBTABLE[12]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDataToggleClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[13]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointStatus \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulEndpoint))ROM_USBTABLE[14]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBFIFOAddrGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulEndpoint))ROM_USBTABLE[15]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBFIFOConfigGet \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2735,7 +5404,11 @@ unsigned long ulFlags))ROM_USBTABLE[16]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBFIFOConfigSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2743,26 +5416,40 @@ unsigned long ulFIFOSize, \ unsigned long ulFlags))ROM_USBTABLE[17]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBFIFOFlush \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[18]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBFrameNumberGet \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostAddrGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[20]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostAddrSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2770,23 +5457,21 @@ unsigned long ulFlags))ROM_USBTABLE[21]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) -#define ROM_USBHostEndpointConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulEndpoint, \ - unsigned long ulMaxPacketSize, \ - unsigned long ulNAKPollInterval, \ - unsigned long ulTargetEndpoint, \ - unsigned long ulFlags))ROM_USBTABLE[22]) -#endif -#if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostEndpointDataAck \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint))ROM_USBTABLE[23]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostEndpointDataToggle \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2794,21 +5479,33 @@ unsigned long ulFlags))ROM_USBTABLE[24]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostEndpointStatusClear \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[25]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostHubAddrGet \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[26]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostHubAddrSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ @@ -2816,147 +5513,271 @@ unsigned long ulFlags))ROM_USBTABLE[27]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostPwrDisable \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[28]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostPwrEnable \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[29]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostPwrConfig \ ((void (*)(unsigned long ulBase, \ unsigned long ulFlags))ROM_USBTABLE[30]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostPwrFaultDisable \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[31]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostPwrFaultEnable \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[32]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostRequestIN \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint))ROM_USBTABLE[33]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostRequestStatus \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[34]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostReset \ ((void (*)(unsigned long ulBase, \ tBoolean bStart))ROM_USBTABLE[35]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostResume \ ((void (*)(unsigned long ulBase, \ tBoolean bStart))ROM_USBTABLE[36]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostSpeedGet \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostSuspend \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[38]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntDisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_USBTABLE[39]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_USBTABLE[40]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBDevEndpointConfigGet \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long *pulMaxPacketSize, \ unsigned long *pulFlags))ROM_USBTABLE[41]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDMAEnable \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[42]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDMADisable \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulFlags))ROM_USBTABLE[43]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDataAvail \ ((unsigned long (*)(unsigned long ulBase, \ unsigned long ulEndpoint))ROM_USBTABLE[44]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBOTGHostRequest \ ((void (*)(unsigned long ulBase, \ tBoolean bHNP))ROM_USBTABLE[45]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBModeGet \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[46]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBEndpointDMAChannel \ ((void (*)(unsigned long ulBase, \ unsigned long ulEndpoint, \ unsigned long ulChannel))ROM_USBTABLE[47]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntDisableControl \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_USBTABLE[48]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntEnableControl \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_USBTABLE[49]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntStatusControl \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[50]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntDisableEndpoint \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_USBTABLE[51]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntEnableEndpoint \ ((void (*)(unsigned long ulBase, \ unsigned long ulIntFlags))ROM_USBTABLE[52]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBIntStatusEndpoint \ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[53]) #endif -#if defined(TARGET_IS_TEMPEST_RC1) +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_USBHostMode \ ((void (*)(unsigned long ulBase))ROM_USBTABLE[54]) #endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_USBDevMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_USBPHYPowerOff \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_USBPHYPowerOn \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_USBOTGMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[59]) +#endif //***************************************************************************** // @@ -2965,96 +5786,161 @@ //***************************************************************************** #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogIntClear \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogRunning \ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogEnable \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogResetEnable \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogResetDisable \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogLock \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogUnlock \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogLockState \ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogReloadSet \ ((void (*)(unsigned long ulBase, \ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogReloadGet \ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogValueGet \ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogIntEnable \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogIntStatus \ ((unsigned long (*)(unsigned long ulBase, \ tBoolean bMasked))ROM_WATCHDOGTABLE[12]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogStallEnable \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13]) #endif #if defined(TARGET_IS_DUSTDEVIL_RA0) || \ defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_WatchdogStallDisable \ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulType))ROM_WATCHDOGTABLE[15]) +#endif //***************************************************************************** // @@ -3062,20 +5948,44 @@ // //***************************************************************************** #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_Crc16Array \ ((unsigned short (*)(unsigned long ulWordLen, \ - unsigned long *pulData))ROM_SOFTWARETABLE[1]) + const unsigned long *pulData))ROM_SOFTWARETABLE[1]) #endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_Crc16Array3 \ ((void (*)(unsigned long ulWordLen, \ - unsigned long *pulData, \ + const unsigned long *pulData, \ unsigned short *pusCrc3))ROM_SOFTWARETABLE[2]) #endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_Crc16 \ + ((unsigned short (*)(unsigned short usCrc, \ + const unsigned char *pucData, \ + unsigned long ulCount))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) +#define ROM_Crc8CCITT \ + ((unsigned char (*)(unsigned char ucCrc, \ + const unsigned char *pucData, \ + unsigned long ulCount))ROM_SOFTWARETABLE[4]) +#endif #if defined(TARGET_IS_TEMPEST_RB1) || \ - defined(TARGET_IS_TEMPEST_RC1) + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) #define ROM_pvAESTable \ ((void *)&(ROM_SOFTWARETABLE[7])) #endif diff --git a/bsp/lm3s8962/Libraries/driverlib/rom_map.h b/bsp/lm3s8962/Libraries/driverlib/rom_map.h index 816292c4e0..f2c88ec67f 100644 --- a/bsp/lm3s8962/Libraries/driverlib/rom_map.h +++ b/bsp/lm3s8962/Libraries/driverlib/rom_map.h @@ -3,7 +3,7 @@ // rom_map.h - Macros to facilitate calling functions in the ROM when they are // available and in flash otherwise. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -185,6 +185,48 @@ #define MAP_ADCComparatorIntClear \ ADCComparatorIntClear #endif +#ifdef ROM_ADCReferenceSet +#define MAP_ADCReferenceSet \ + ROM_ADCReferenceSet +#else +#define MAP_ADCReferenceSet \ + ADCReferenceSet +#endif +#ifdef ROM_ADCReferenceGet +#define MAP_ADCReferenceGet \ + ROM_ADCReferenceGet +#else +#define MAP_ADCReferenceGet \ + ADCReferenceGet +#endif +#ifdef ROM_ADCPhaseDelaySet +#define MAP_ADCPhaseDelaySet \ + ROM_ADCPhaseDelaySet +#else +#define MAP_ADCPhaseDelaySet \ + ADCPhaseDelaySet +#endif +#ifdef ROM_ADCPhaseDelayGet +#define MAP_ADCPhaseDelayGet \ + ROM_ADCPhaseDelayGet +#else +#define MAP_ADCPhaseDelayGet \ + ADCPhaseDelayGet +#endif +#ifdef ROM_ADCResolutionSet +#define MAP_ADCResolutionSet \ + ROM_ADCResolutionSet +#else +#define MAP_ADCResolutionSet \ + ADCResolutionSet +#endif +#ifdef ROM_ADCResolutionGet +#define MAP_ADCResolutionGet \ + ROM_ADCResolutionGet +#else +#define MAP_ADCResolutionGet \ + ADCResolutionGet +#endif //***************************************************************************** // @@ -368,7 +410,7 @@ //***************************************************************************** // -// Macros for the Ethernet API. +// Macros for the EPI API. // //***************************************************************************** #ifdef ROM_EPIIntStatus @@ -664,6 +706,131 @@ #define MAP_EthernetPHYRead \ EthernetPHYRead #endif +#ifdef ROM_EthernetPHYAddrSet +#define MAP_EthernetPHYAddrSet \ + ROM_EthernetPHYAddrSet +#else +#define MAP_EthernetPHYAddrSet \ + EthernetPHYAddrSet +#endif +#ifdef ROM_EthernetPHYPowerOff +#define MAP_EthernetPHYPowerOff \ + ROM_EthernetPHYPowerOff +#else +#define MAP_EthernetPHYPowerOff \ + EthernetPHYPowerOff +#endif +#ifdef ROM_EthernetPHYPowerOn +#define MAP_EthernetPHYPowerOn \ + ROM_EthernetPHYPowerOn +#else +#define MAP_EthernetPHYPowerOn \ + EthernetPHYPowerOn +#endif + +//***************************************************************************** +// +// Macros for the Fan API. +// +//***************************************************************************** +#ifdef ROM_FanIntClear +#define MAP_FanIntClear \ + ROM_FanIntClear +#else +#define MAP_FanIntClear \ + FanIntClear +#endif +#ifdef ROM_FanChannelConfigAuto +#define MAP_FanChannelConfigAuto \ + ROM_FanChannelConfigAuto +#else +#define MAP_FanChannelConfigAuto \ + FanChannelConfigAuto +#endif +#ifdef ROM_FanChannelConfigManual +#define MAP_FanChannelConfigManual \ + ROM_FanChannelConfigManual +#else +#define MAP_FanChannelConfigManual \ + FanChannelConfigManual +#endif +#ifdef ROM_FanChannelDisable +#define MAP_FanChannelDisable \ + ROM_FanChannelDisable +#else +#define MAP_FanChannelDisable \ + FanChannelDisable +#endif +#ifdef ROM_FanChannelDutyGet +#define MAP_FanChannelDutyGet \ + ROM_FanChannelDutyGet +#else +#define MAP_FanChannelDutyGet \ + FanChannelDutyGet +#endif +#ifdef ROM_FanChannelDutySet +#define MAP_FanChannelDutySet \ + ROM_FanChannelDutySet +#else +#define MAP_FanChannelDutySet \ + FanChannelDutySet +#endif +#ifdef ROM_FanChannelEnable +#define MAP_FanChannelEnable \ + ROM_FanChannelEnable +#else +#define MAP_FanChannelEnable \ + FanChannelEnable +#endif +#ifdef ROM_FanChannelRPMGet +#define MAP_FanChannelRPMGet \ + ROM_FanChannelRPMGet +#else +#define MAP_FanChannelRPMGet \ + FanChannelRPMGet +#endif +#ifdef ROM_FanChannelRPMSet +#define MAP_FanChannelRPMSet \ + ROM_FanChannelRPMSet +#else +#define MAP_FanChannelRPMSet \ + FanChannelRPMSet +#endif +#ifdef ROM_FanChannelStatus +#define MAP_FanChannelStatus \ + ROM_FanChannelStatus +#else +#define MAP_FanChannelStatus \ + FanChannelStatus +#endif +#ifdef ROM_FanChannelsGet +#define MAP_FanChannelsGet \ + ROM_FanChannelsGet +#else +#define MAP_FanChannelsGet \ + FanChannelsGet +#endif +#ifdef ROM_FanIntDisable +#define MAP_FanIntDisable \ + ROM_FanIntDisable +#else +#define MAP_FanIntDisable \ + FanIntDisable +#endif +#ifdef ROM_FanIntEnable +#define MAP_FanIntEnable \ + ROM_FanIntEnable +#else +#define MAP_FanIntEnable \ + FanIntEnable +#endif +#ifdef ROM_FanIntStatus +#define MAP_FanIntStatus \ + ROM_FanIntStatus +#else +#define MAP_FanIntStatus \ + FanIntStatus +#endif //***************************************************************************** // @@ -769,6 +936,75 @@ FlashIntClear #endif +//***************************************************************************** +// +// Macros for the FPU API. +// +//***************************************************************************** +#ifdef ROM_FPUEnable +#define MAP_FPUEnable \ + ROM_FPUEnable +#else +#define MAP_FPUEnable \ + FPUEnable +#endif +#ifdef ROM_FPUDisable +#define MAP_FPUDisable \ + ROM_FPUDisable +#else +#define MAP_FPUDisable \ + FPUDisable +#endif +#ifdef ROM_FPUFlushToZeroModeSet +#define MAP_FPUFlushToZeroModeSet \ + ROM_FPUFlushToZeroModeSet +#else +#define MAP_FPUFlushToZeroModeSet \ + FPUFlushToZeroModeSet +#endif +#ifdef ROM_FPUHalfPrecisionModeSet +#define MAP_FPUHalfPrecisionModeSet \ + ROM_FPUHalfPrecisionModeSet +#else +#define MAP_FPUHalfPrecisionModeSet \ + FPUHalfPrecisionModeSet +#endif +#ifdef ROM_FPULazyStackingEnable +#define MAP_FPULazyStackingEnable \ + ROM_FPULazyStackingEnable +#else +#define MAP_FPULazyStackingEnable \ + FPULazyStackingEnable +#endif +#ifdef ROM_FPUNaNModeSet +#define MAP_FPUNaNModeSet \ + ROM_FPUNaNModeSet +#else +#define MAP_FPUNaNModeSet \ + FPUNaNModeSet +#endif +#ifdef ROM_FPURoundingModeSet +#define MAP_FPURoundingModeSet \ + ROM_FPURoundingModeSet +#else +#define MAP_FPURoundingModeSet \ + FPURoundingModeSet +#endif +#ifdef ROM_FPUStackingDisable +#define MAP_FPUStackingDisable \ + ROM_FPUStackingDisable +#else +#define MAP_FPUStackingDisable \ + FPUStackingDisable +#endif +#ifdef ROM_FPUStackingEnable +#define MAP_FPUStackingEnable \ + ROM_FPUStackingEnable +#else +#define MAP_FPUStackingEnable \ + FPUStackingEnable +#endif + //***************************************************************************** // // Macros for the GPIO API. @@ -977,6 +1213,76 @@ #define MAP_GPIOPinTypeUSBAnalog \ GPIOPinTypeUSBAnalog #endif +#ifdef ROM_GPIOPinTypeEPI +#define MAP_GPIOPinTypeEPI \ + ROM_GPIOPinTypeEPI +#else +#define MAP_GPIOPinTypeEPI \ + GPIOPinTypeEPI +#endif +#ifdef ROM_GPIOPinTypeEthernetMII +#define MAP_GPIOPinTypeEthernetMII \ + ROM_GPIOPinTypeEthernetMII +#else +#define MAP_GPIOPinTypeEthernetMII \ + GPIOPinTypeEthernetMII +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOADCTriggerEnable +#define MAP_GPIOADCTriggerEnable \ + ROM_GPIOADCTriggerEnable +#else +#define MAP_GPIOADCTriggerEnable \ + GPIOADCTriggerEnable +#endif +#ifdef ROM_GPIOADCTriggerDisable +#define MAP_GPIOADCTriggerDisable \ + ROM_GPIOADCTriggerDisable +#else +#define MAP_GPIOADCTriggerDisable \ + GPIOADCTriggerDisable +#endif +#ifdef ROM_GPIOPinTypeFan +#define MAP_GPIOPinTypeFan \ + ROM_GPIOPinTypeFan +#else +#define MAP_GPIOPinTypeFan \ + GPIOPinTypeFan +#endif +#ifdef ROM_GPIOPinTypeLPC +#define MAP_GPIOPinTypeLPC \ + ROM_GPIOPinTypeLPC +#else +#define MAP_GPIOPinTypeLPC \ + GPIOPinTypeLPC +#endif +#ifdef ROM_GPIOPinTypePECIRx +#define MAP_GPIOPinTypePECIRx \ + ROM_GPIOPinTypePECIRx +#else +#define MAP_GPIOPinTypePECIRx \ + GPIOPinTypePECIRx +#endif +#ifdef ROM_GPIOPinTypePECITx +#define MAP_GPIOPinTypePECITx \ + ROM_GPIOPinTypePECITx +#else +#define MAP_GPIOPinTypePECITx \ + GPIOPinTypePECITx +#endif //***************************************************************************** // @@ -1158,6 +1464,48 @@ #define MAP_HibernateIsActive \ HibernateIsActive #endif +#ifdef ROM_HibernateRTCSSMatch0Set +#define MAP_HibernateRTCSSMatch0Set \ + ROM_HibernateRTCSSMatch0Set +#else +#define MAP_HibernateRTCSSMatch0Set \ + HibernateRTCSSMatch0Set +#endif +#ifdef ROM_HibernateRTCSSMatch0Get +#define MAP_HibernateRTCSSMatch0Get \ + ROM_HibernateRTCSSMatch0Get +#else +#define MAP_HibernateRTCSSMatch0Get \ + HibernateRTCSSMatch0Get +#endif +#ifdef ROM_HibernateRTCSSGet +#define MAP_HibernateRTCSSGet \ + ROM_HibernateRTCSSGet +#else +#define MAP_HibernateRTCSSGet \ + HibernateRTCSSGet +#endif +#ifdef ROM_HibernateClockConfig +#define MAP_HibernateClockConfig \ + ROM_HibernateClockConfig +#else +#define MAP_HibernateClockConfig \ + HibernateClockConfig +#endif +#ifdef ROM_HibernateBatCheckStart +#define MAP_HibernateBatCheckStart \ + ROM_HibernateBatCheckStart +#else +#define MAP_HibernateBatCheckStart \ + HibernateBatCheckStart +#endif +#ifdef ROM_HibernateBatCheckDone +#define MAP_HibernateBatCheckDone \ + ROM_HibernateBatCheckDone +#else +#define MAP_HibernateBatCheckDone \ + HibernateBatCheckDone +#endif //***************************************************************************** // @@ -1360,6 +1708,69 @@ #define MAP_I2CSlaveIntClearEx \ I2CSlaveIntClearEx #endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif //***************************************************************************** // @@ -1610,6 +2021,285 @@ #define MAP_IntPendClear \ IntPendClear #endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif + +//***************************************************************************** +// +// Macros for the LPC API. +// +//***************************************************************************** +#ifdef ROM_LPCIntClear +#define MAP_LPCIntClear \ + ROM_LPCIntClear +#else +#define MAP_LPCIntClear \ + LPCIntClear +#endif +#ifdef ROM_LPCByteRead +#define MAP_LPCByteRead \ + ROM_LPCByteRead +#else +#define MAP_LPCByteRead \ + LPCByteRead +#endif +#ifdef ROM_LPCByteWrite +#define MAP_LPCByteWrite \ + ROM_LPCByteWrite +#else +#define MAP_LPCByteWrite \ + LPCByteWrite +#endif +#ifdef ROM_LPCChannelConfigCOMxSet +#define MAP_LPCChannelConfigCOMxSet \ + ROM_LPCChannelConfigCOMxSet +#else +#define MAP_LPCChannelConfigCOMxSet \ + LPCChannelConfigCOMxSet +#endif +#ifdef ROM_LPCChannelConfigGet +#define MAP_LPCChannelConfigGet \ + ROM_LPCChannelConfigGet +#else +#define MAP_LPCChannelConfigGet \ + LPCChannelConfigGet +#endif +#ifdef ROM_LPCChannelConfigEPSet +#define MAP_LPCChannelConfigEPSet \ + ROM_LPCChannelConfigEPSet +#else +#define MAP_LPCChannelConfigEPSet \ + LPCChannelConfigEPSet +#endif +#ifdef ROM_LPCChannelConfigMBSet +#define MAP_LPCChannelConfigMBSet \ + ROM_LPCChannelConfigMBSet +#else +#define MAP_LPCChannelConfigMBSet \ + LPCChannelConfigMBSet +#endif +#ifdef ROM_LPCChannelDMAConfigGet +#define MAP_LPCChannelDMAConfigGet \ + ROM_LPCChannelDMAConfigGet +#else +#define MAP_LPCChannelDMAConfigGet \ + LPCChannelDMAConfigGet +#endif +#ifdef ROM_LPCChannelDMAConfigSet +#define MAP_LPCChannelDMAConfigSet \ + ROM_LPCChannelDMAConfigSet +#else +#define MAP_LPCChannelDMAConfigSet \ + LPCChannelDMAConfigSet +#endif +#ifdef ROM_LPCChannelDisable +#define MAP_LPCChannelDisable \ + ROM_LPCChannelDisable +#else +#define MAP_LPCChannelDisable \ + LPCChannelDisable +#endif +#ifdef ROM_LPCChannelEnable +#define MAP_LPCChannelEnable \ + ROM_LPCChannelEnable +#else +#define MAP_LPCChannelEnable \ + LPCChannelEnable +#endif +#ifdef ROM_LPCChannelStatusClear +#define MAP_LPCChannelStatusClear \ + ROM_LPCChannelStatusClear +#else +#define MAP_LPCChannelStatusClear \ + LPCChannelStatusClear +#endif +#ifdef ROM_LPCChannelStatusGet +#define MAP_LPCChannelStatusGet \ + ROM_LPCChannelStatusGet +#else +#define MAP_LPCChannelStatusGet \ + LPCChannelStatusGet +#endif +#ifdef ROM_LPCChannelStatusSet +#define MAP_LPCChannelStatusSet \ + ROM_LPCChannelStatusSet +#else +#define MAP_LPCChannelStatusSet \ + LPCChannelStatusSet +#endif +#ifdef ROM_LPCCOMxIntClear +#define MAP_LPCCOMxIntClear \ + ROM_LPCCOMxIntClear +#else +#define MAP_LPCCOMxIntClear \ + LPCCOMxIntClear +#endif +#ifdef ROM_LPCCOMxIntDisable +#define MAP_LPCCOMxIntDisable \ + ROM_LPCCOMxIntDisable +#else +#define MAP_LPCCOMxIntDisable \ + LPCCOMxIntDisable +#endif +#ifdef ROM_LPCCOMxIntEnable +#define MAP_LPCCOMxIntEnable \ + ROM_LPCCOMxIntEnable +#else +#define MAP_LPCCOMxIntEnable \ + LPCCOMxIntEnable +#endif +#ifdef ROM_LPCCOMxIntStatus +#define MAP_LPCCOMxIntStatus \ + ROM_LPCCOMxIntStatus +#else +#define MAP_LPCCOMxIntStatus \ + LPCCOMxIntStatus +#endif +#ifdef ROM_LPCConfigGet +#define MAP_LPCConfigGet \ + ROM_LPCConfigGet +#else +#define MAP_LPCConfigGet \ + LPCConfigGet +#endif +#ifdef ROM_LPCConfigSet +#define MAP_LPCConfigSet \ + ROM_LPCConfigSet +#else +#define MAP_LPCConfigSet \ + LPCConfigSet +#endif +#ifdef ROM_LPCHalfWordRead +#define MAP_LPCHalfWordRead \ + ROM_LPCHalfWordRead +#else +#define MAP_LPCHalfWordRead \ + LPCHalfWordRead +#endif +#ifdef ROM_LPCHalfWordWrite +#define MAP_LPCHalfWordWrite \ + ROM_LPCHalfWordWrite +#else +#define MAP_LPCHalfWordWrite \ + LPCHalfWordWrite +#endif +#ifdef ROM_LPCIRQClear +#define MAP_LPCIRQClear \ + ROM_LPCIRQClear +#else +#define MAP_LPCIRQClear \ + LPCIRQClear +#endif +#ifdef ROM_LPCIRQConfig +#define MAP_LPCIRQConfig \ + ROM_LPCIRQConfig +#else +#define MAP_LPCIRQConfig \ + LPCIRQConfig +#endif +#ifdef ROM_LPCIRQGet +#define MAP_LPCIRQGet \ + ROM_LPCIRQGet +#else +#define MAP_LPCIRQGet \ + LPCIRQGet +#endif +#ifdef ROM_LPCIRQSend +#define MAP_LPCIRQSend \ + ROM_LPCIRQSend +#else +#define MAP_LPCIRQSend \ + LPCIRQSend +#endif +#ifdef ROM_LPCIRQSet +#define MAP_LPCIRQSet \ + ROM_LPCIRQSet +#else +#define MAP_LPCIRQSet \ + LPCIRQSet +#endif +#ifdef ROM_LPCIntDisable +#define MAP_LPCIntDisable \ + ROM_LPCIntDisable +#else +#define MAP_LPCIntDisable \ + LPCIntDisable +#endif +#ifdef ROM_LPCIntEnable +#define MAP_LPCIntEnable \ + ROM_LPCIntEnable +#else +#define MAP_LPCIntEnable \ + LPCIntEnable +#endif +#ifdef ROM_LPCIntStatus +#define MAP_LPCIntStatus \ + ROM_LPCIntStatus +#else +#define MAP_LPCIntStatus \ + LPCIntStatus +#endif +#ifdef ROM_LPCSCIAssert +#define MAP_LPCSCIAssert \ + ROM_LPCSCIAssert +#else +#define MAP_LPCSCIAssert \ + LPCSCIAssert +#endif +#ifdef ROM_LPCStatusGet +#define MAP_LPCStatusGet \ + ROM_LPCStatusGet +#else +#define MAP_LPCStatusGet \ + LPCStatusGet +#endif +#ifdef ROM_LPCWordRead +#define MAP_LPCWordRead \ + ROM_LPCWordRead +#else +#define MAP_LPCWordRead \ + LPCWordRead +#endif +#ifdef ROM_LPCWordWrite +#define MAP_LPCWordWrite \ + ROM_LPCWordWrite +#else +#define MAP_LPCWordWrite \ + LPCWordWrite +#endif +#ifdef ROM_LPCChannelPoolAddressGet +#define MAP_LPCChannelPoolAddressGet \ + ROM_LPCChannelPoolAddressGet +#else +#define MAP_LPCChannelPoolAddressGet \ + LPCChannelPoolAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressGet +#define MAP_LPCStatusBlockAddressGet \ + ROM_LPCStatusBlockAddressGet +#else +#define MAP_LPCStatusBlockAddressGet \ + LPCStatusBlockAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressSet +#define MAP_LPCStatusBlockAddressSet \ + ROM_LPCStatusBlockAddressSet +#else +#define MAP_LPCStatusBlockAddressSet \ + LPCStatusBlockAddressSet +#endif //***************************************************************************** // @@ -1666,6 +2356,145 @@ MPURegionGet #endif +//***************************************************************************** +// +// Macros for the PECI API. +// +//***************************************************************************** +#ifdef ROM_PECIIntClear +#define MAP_PECIIntClear \ + ROM_PECIIntClear +#else +#define MAP_PECIIntClear \ + PECIIntClear +#endif +#ifdef ROM_PECIAdvCmdSend +#define MAP_PECIAdvCmdSend \ + ROM_PECIAdvCmdSend +#else +#define MAP_PECIAdvCmdSend \ + PECIAdvCmdSend +#endif +#ifdef ROM_PECIAdvCmdSendNonBlocking +#define MAP_PECIAdvCmdSendNonBlocking \ + ROM_PECIAdvCmdSendNonBlocking +#else +#define MAP_PECIAdvCmdSendNonBlocking \ + PECIAdvCmdSendNonBlocking +#endif +#ifdef ROM_PECIAdvCmdStatusGet +#define MAP_PECIAdvCmdStatusGet \ + ROM_PECIAdvCmdStatusGet +#else +#define MAP_PECIAdvCmdStatusGet \ + PECIAdvCmdStatusGet +#endif +#ifdef ROM_PECIConfigGet +#define MAP_PECIConfigGet \ + ROM_PECIConfigGet +#else +#define MAP_PECIConfigGet \ + PECIConfigGet +#endif +#ifdef ROM_PECIConfigSet +#define MAP_PECIConfigSet \ + ROM_PECIConfigSet +#else +#define MAP_PECIConfigSet \ + PECIConfigSet +#endif +#ifdef ROM_PECIDomainMaxReadClear +#define MAP_PECIDomainMaxReadClear \ + ROM_PECIDomainMaxReadClear +#else +#define MAP_PECIDomainMaxReadClear \ + PECIDomainMaxReadClear +#endif +#ifdef ROM_PECIDomainValueClear +#define MAP_PECIDomainValueClear \ + ROM_PECIDomainValueClear +#else +#define MAP_PECIDomainValueClear \ + PECIDomainValueClear +#endif +#ifdef ROM_PECIDomainConfigGet +#define MAP_PECIDomainConfigGet \ + ROM_PECIDomainConfigGet +#else +#define MAP_PECIDomainConfigGet \ + PECIDomainConfigGet +#endif +#ifdef ROM_PECIDomainConfigSet +#define MAP_PECIDomainConfigSet \ + ROM_PECIDomainConfigSet +#else +#define MAP_PECIDomainConfigSet \ + PECIDomainConfigSet +#endif +#ifdef ROM_PECIDomainDisable +#define MAP_PECIDomainDisable \ + ROM_PECIDomainDisable +#else +#define MAP_PECIDomainDisable \ + PECIDomainDisable +#endif +#ifdef ROM_PECIDomainEnable +#define MAP_PECIDomainEnable \ + ROM_PECIDomainEnable +#else +#define MAP_PECIDomainEnable \ + PECIDomainEnable +#endif +#ifdef ROM_PECIDomainMaxReadGet +#define MAP_PECIDomainMaxReadGet \ + ROM_PECIDomainMaxReadGet +#else +#define MAP_PECIDomainMaxReadGet \ + PECIDomainMaxReadGet +#endif +#ifdef ROM_PECIDomainValueGet +#define MAP_PECIDomainValueGet \ + ROM_PECIDomainValueGet +#else +#define MAP_PECIDomainValueGet \ + PECIDomainValueGet +#endif +#ifdef ROM_PECIIntDisable +#define MAP_PECIIntDisable \ + ROM_PECIIntDisable +#else +#define MAP_PECIIntDisable \ + PECIIntDisable +#endif +#ifdef ROM_PECIIntEnable +#define MAP_PECIIntEnable \ + ROM_PECIIntEnable +#else +#define MAP_PECIIntEnable \ + PECIIntEnable +#endif +#ifdef ROM_PECIIntStatus +#define MAP_PECIIntStatus \ + ROM_PECIIntStatus +#else +#define MAP_PECIIntStatus \ + PECIIntStatus +#endif +#ifdef ROM_PECIBypassEnable +#define MAP_PECIBypassEnable \ + ROM_PECIBypassEnable +#else +#define MAP_PECIBypassEnable \ + PECIBypassEnable +#endif +#ifdef ROM_PECIBypassDisable +#define MAP_PECIBypassDisable \ + ROM_PECIBypassDisable +#else +#define MAP_PECIBypassDisable \ + PECIBypassDisable +#endif + //***************************************************************************** // // Macros for the PWM API. @@ -1986,6 +2815,390 @@ QEIIntClear #endif +//***************************************************************************** +// +// Macros for the SMBus API. +// +//***************************************************************************** +#ifdef ROM_SMBusMasterIntProcess +#define MAP_SMBusMasterIntProcess \ + ROM_SMBusMasterIntProcess +#else +#define MAP_SMBusMasterIntProcess \ + SMBusMasterIntProcess +#endif +#ifdef ROM_SMBusARPDisable +#define MAP_SMBusARPDisable \ + ROM_SMBusARPDisable +#else +#define MAP_SMBusARPDisable \ + SMBusARPDisable +#endif +#ifdef ROM_SMBusARPEnable +#define MAP_SMBusARPEnable \ + ROM_SMBusARPEnable +#else +#define MAP_SMBusARPEnable \ + SMBusARPEnable +#endif +#ifdef ROM_SMBusARPUDIDPacketDecode +#define MAP_SMBusARPUDIDPacketDecode \ + ROM_SMBusARPUDIDPacketDecode +#else +#define MAP_SMBusARPUDIDPacketDecode \ + SMBusARPUDIDPacketDecode +#endif +#ifdef ROM_SMBusARPUDIDPacketEncode +#define MAP_SMBusARPUDIDPacketEncode \ + ROM_SMBusARPUDIDPacketEncode +#else +#define MAP_SMBusARPUDIDPacketEncode \ + SMBusARPUDIDPacketEncode +#endif +#ifdef ROM_SMBusMasterARPAssignAddress +#define MAP_SMBusMasterARPAssignAddress \ + ROM_SMBusMasterARPAssignAddress +#else +#define MAP_SMBusMasterARPAssignAddress \ + SMBusMasterARPAssignAddress +#endif +#ifdef ROM_SMBusMasterARPGetUDIDDir +#define MAP_SMBusMasterARPGetUDIDDir \ + ROM_SMBusMasterARPGetUDIDDir +#else +#define MAP_SMBusMasterARPGetUDIDDir \ + SMBusMasterARPGetUDIDDir +#endif +#ifdef ROM_SMBusMasterARPGetUDIDGen +#define MAP_SMBusMasterARPGetUDIDGen \ + ROM_SMBusMasterARPGetUDIDGen +#else +#define MAP_SMBusMasterARPGetUDIDGen \ + SMBusMasterARPGetUDIDGen +#endif +#ifdef ROM_SMBusMasterARPNotifyMaster +#define MAP_SMBusMasterARPNotifyMaster \ + ROM_SMBusMasterARPNotifyMaster +#else +#define MAP_SMBusMasterARPNotifyMaster \ + SMBusMasterARPNotifyMaster +#endif +#ifdef ROM_SMBusMasterARPPrepareToARP +#define MAP_SMBusMasterARPPrepareToARP \ + ROM_SMBusMasterARPPrepareToARP +#else +#define MAP_SMBusMasterARPPrepareToARP \ + SMBusMasterARPPrepareToARP +#endif +#ifdef ROM_SMBusMasterARPResetDeviceDir +#define MAP_SMBusMasterARPResetDeviceDir \ + ROM_SMBusMasterARPResetDeviceDir +#else +#define MAP_SMBusMasterARPResetDeviceDir \ + SMBusMasterARPResetDeviceDir +#endif +#ifdef ROM_SMBusMasterARPResetDeviceGen +#define MAP_SMBusMasterARPResetDeviceGen \ + ROM_SMBusMasterARPResetDeviceGen +#else +#define MAP_SMBusMasterARPResetDeviceGen \ + SMBusMasterARPResetDeviceGen +#endif +#ifdef ROM_SMBusMasterBlockProcessCall +#define MAP_SMBusMasterBlockProcessCall \ + ROM_SMBusMasterBlockProcessCall +#else +#define MAP_SMBusMasterBlockProcessCall \ + SMBusMasterBlockProcessCall +#endif +#ifdef ROM_SMBusMasterBlockWrite +#define MAP_SMBusMasterBlockWrite \ + ROM_SMBusMasterBlockWrite +#else +#define MAP_SMBusMasterBlockWrite \ + SMBusMasterBlockWrite +#endif +#ifdef ROM_SMBusMasterByteReceive +#define MAP_SMBusMasterByteReceive \ + ROM_SMBusMasterByteReceive +#else +#define MAP_SMBusMasterByteReceive \ + SMBusMasterByteReceive +#endif +#ifdef ROM_SMBusMasterByteSend +#define MAP_SMBusMasterByteSend \ + ROM_SMBusMasterByteSend +#else +#define MAP_SMBusMasterByteSend \ + SMBusMasterByteSend +#endif +#ifdef ROM_SMBusMasterByteWordRead +#define MAP_SMBusMasterByteWordRead \ + ROM_SMBusMasterByteWordRead +#else +#define MAP_SMBusMasterByteWordRead \ + SMBusMasterByteWordRead +#endif +#ifdef ROM_SMBusMasterByteWordWrite +#define MAP_SMBusMasterByteWordWrite \ + ROM_SMBusMasterByteWordWrite +#else +#define MAP_SMBusMasterByteWordWrite \ + SMBusMasterByteWordWrite +#endif +#ifdef ROM_SMBusMasterHostNotify +#define MAP_SMBusMasterHostNotify \ + ROM_SMBusMasterHostNotify +#else +#define MAP_SMBusMasterHostNotify \ + SMBusMasterHostNotify +#endif +#ifdef ROM_SMBusMasterI2CRead +#define MAP_SMBusMasterI2CRead \ + ROM_SMBusMasterI2CRead +#else +#define MAP_SMBusMasterI2CRead \ + SMBusMasterI2CRead +#endif +#ifdef ROM_SMBusMasterI2CWrite +#define MAP_SMBusMasterI2CWrite \ + ROM_SMBusMasterI2CWrite +#else +#define MAP_SMBusMasterI2CWrite \ + SMBusMasterI2CWrite +#endif +#ifdef ROM_SMBusMasterI2CWriteRead +#define MAP_SMBusMasterI2CWriteRead \ + ROM_SMBusMasterI2CWriteRead +#else +#define MAP_SMBusMasterI2CWriteRead \ + SMBusMasterI2CWriteRead +#endif +#ifdef ROM_SMBusMasterInit +#define MAP_SMBusMasterInit \ + ROM_SMBusMasterInit +#else +#define MAP_SMBusMasterInit \ + SMBusMasterInit +#endif +#ifdef ROM_SMBusMasterIntEnable +#define MAP_SMBusMasterIntEnable \ + ROM_SMBusMasterIntEnable +#else +#define MAP_SMBusMasterIntEnable \ + SMBusMasterIntEnable +#endif +#ifdef ROM_SMBusMasterProcessCall +#define MAP_SMBusMasterProcessCall \ + ROM_SMBusMasterProcessCall +#else +#define MAP_SMBusMasterProcessCall \ + SMBusMasterProcessCall +#endif +#ifdef ROM_SMBusMasterQuickCommand +#define MAP_SMBusMasterQuickCommand \ + ROM_SMBusMasterQuickCommand +#else +#define MAP_SMBusMasterQuickCommand \ + SMBusMasterQuickCommand +#endif +#ifdef ROM_SMBusPECDisable +#define MAP_SMBusPECDisable \ + ROM_SMBusPECDisable +#else +#define MAP_SMBusPECDisable \ + SMBusPECDisable +#endif +#ifdef ROM_SMBusPECEnable +#define MAP_SMBusPECEnable \ + ROM_SMBusPECEnable +#else +#define MAP_SMBusPECEnable \ + SMBusPECEnable +#endif +#ifdef ROM_SMBusRxPacketSizeGet +#define MAP_SMBusRxPacketSizeGet \ + ROM_SMBusRxPacketSizeGet +#else +#define MAP_SMBusRxPacketSizeGet \ + SMBusRxPacketSizeGet +#endif +#ifdef ROM_SMBusSlaveACKSend +#define MAP_SMBusSlaveACKSend \ + ROM_SMBusSlaveACKSend +#else +#define MAP_SMBusSlaveACKSend \ + SMBusSlaveACKSend +#endif +#ifdef ROM_SMBusSlaveAddressSet +#define MAP_SMBusSlaveAddressSet \ + ROM_SMBusSlaveAddressSet +#else +#define MAP_SMBusSlaveAddressSet \ + SMBusSlaveAddressSet +#endif +#ifdef ROM_SMBusSlaveARPFlagARGet +#define MAP_SMBusSlaveARPFlagARGet \ + ROM_SMBusSlaveARPFlagARGet +#else +#define MAP_SMBusSlaveARPFlagARGet \ + SMBusSlaveARPFlagARGet +#endif +#ifdef ROM_SMBusSlaveARPFlagARSet +#define MAP_SMBusSlaveARPFlagARSet \ + ROM_SMBusSlaveARPFlagARSet +#else +#define MAP_SMBusSlaveARPFlagARSet \ + SMBusSlaveARPFlagARSet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVGet +#define MAP_SMBusSlaveARPFlagAVGet \ + ROM_SMBusSlaveARPFlagAVGet +#else +#define MAP_SMBusSlaveARPFlagAVGet \ + SMBusSlaveARPFlagAVGet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVSet +#define MAP_SMBusSlaveARPFlagAVSet \ + ROM_SMBusSlaveARPFlagAVSet +#else +#define MAP_SMBusSlaveARPFlagAVSet \ + SMBusSlaveARPFlagAVSet +#endif +#ifdef ROM_SMBusSlaveBlockTransferDisable +#define MAP_SMBusSlaveBlockTransferDisable \ + ROM_SMBusSlaveBlockTransferDisable +#else +#define MAP_SMBusSlaveBlockTransferDisable \ + SMBusSlaveBlockTransferDisable +#endif +#ifdef ROM_SMBusSlaveBlockTransferEnable +#define MAP_SMBusSlaveBlockTransferEnable \ + ROM_SMBusSlaveBlockTransferEnable +#else +#define MAP_SMBusSlaveBlockTransferEnable \ + SMBusSlaveBlockTransferEnable +#endif +#ifdef ROM_SMBusSlaveCommandGet +#define MAP_SMBusSlaveCommandGet \ + ROM_SMBusSlaveCommandGet +#else +#define MAP_SMBusSlaveCommandGet \ + SMBusSlaveCommandGet +#endif +#ifdef ROM_SMBusSlaveI2CDisable +#define MAP_SMBusSlaveI2CDisable \ + ROM_SMBusSlaveI2CDisable +#else +#define MAP_SMBusSlaveI2CDisable \ + SMBusSlaveI2CDisable +#endif +#ifdef ROM_SMBusSlaveI2CEnable +#define MAP_SMBusSlaveI2CEnable \ + ROM_SMBusSlaveI2CEnable +#else +#define MAP_SMBusSlaveI2CEnable \ + SMBusSlaveI2CEnable +#endif +#ifdef ROM_SMBusSlaveInit +#define MAP_SMBusSlaveInit \ + ROM_SMBusSlaveInit +#else +#define MAP_SMBusSlaveInit \ + SMBusSlaveInit +#endif +#ifdef ROM_SMBusSlaveIntAddressGet +#define MAP_SMBusSlaveIntAddressGet \ + ROM_SMBusSlaveIntAddressGet +#else +#define MAP_SMBusSlaveIntAddressGet \ + SMBusSlaveIntAddressGet +#endif +#ifdef ROM_SMBusSlaveIntEnable +#define MAP_SMBusSlaveIntEnable \ + ROM_SMBusSlaveIntEnable +#else +#define MAP_SMBusSlaveIntEnable \ + SMBusSlaveIntEnable +#endif +#ifdef ROM_SMBusSlaveIntProcess +#define MAP_SMBusSlaveIntProcess \ + ROM_SMBusSlaveIntProcess +#else +#define MAP_SMBusSlaveIntProcess \ + SMBusSlaveIntProcess +#endif +#ifdef ROM_SMBusSlaveManualACKDisable +#define MAP_SMBusSlaveManualACKDisable \ + ROM_SMBusSlaveManualACKDisable +#else +#define MAP_SMBusSlaveManualACKDisable \ + SMBusSlaveManualACKDisable +#endif +#ifdef ROM_SMBusSlaveManualACKEnable +#define MAP_SMBusSlaveManualACKEnable \ + ROM_SMBusSlaveManualACKEnable +#else +#define MAP_SMBusSlaveManualACKEnable \ + SMBusSlaveManualACKEnable +#endif +#ifdef ROM_SMBusSlaveManualACKStatusGet +#define MAP_SMBusSlaveManualACKStatusGet \ + ROM_SMBusSlaveManualACKStatusGet +#else +#define MAP_SMBusSlaveManualACKStatusGet \ + SMBusSlaveManualACKStatusGet +#endif +#ifdef ROM_SMBusSlaveProcessCallDisable +#define MAP_SMBusSlaveProcessCallDisable \ + ROM_SMBusSlaveProcessCallDisable +#else +#define MAP_SMBusSlaveProcessCallDisable \ + SMBusSlaveProcessCallDisable +#endif +#ifdef ROM_SMBusSlaveProcessCallEnable +#define MAP_SMBusSlaveProcessCallEnable \ + ROM_SMBusSlaveProcessCallEnable +#else +#define MAP_SMBusSlaveProcessCallEnable \ + SMBusSlaveProcessCallEnable +#endif +#ifdef ROM_SMBusSlaveRxBufferSet +#define MAP_SMBusSlaveRxBufferSet \ + ROM_SMBusSlaveRxBufferSet +#else +#define MAP_SMBusSlaveRxBufferSet \ + SMBusSlaveRxBufferSet +#endif +#ifdef ROM_SMBusSlaveTransferInit +#define MAP_SMBusSlaveTransferInit \ + ROM_SMBusSlaveTransferInit +#else +#define MAP_SMBusSlaveTransferInit \ + SMBusSlaveTransferInit +#endif +#ifdef ROM_SMBusSlaveTxBufferSet +#define MAP_SMBusSlaveTxBufferSet \ + ROM_SMBusSlaveTxBufferSet +#else +#define MAP_SMBusSlaveTxBufferSet \ + SMBusSlaveTxBufferSet +#endif +#ifdef ROM_SMBusSlaveUDIDSet +#define MAP_SMBusSlaveUDIDSet \ + ROM_SMBusSlaveUDIDSet +#else +#define MAP_SMBusSlaveUDIDSet \ + SMBusSlaveUDIDSet +#endif +#ifdef ROM_SMBusStatusGet +#define MAP_SMBusStatusGet \ + ROM_SMBusStatusGet +#else +#define MAP_SMBusStatusGet \ + SMBusStatusGet +#endif + //***************************************************************************** // // Macros for the SSI API. @@ -2089,6 +3302,20 @@ #define MAP_SSIBusy \ SSIBusy #endif +#ifdef ROM_SSIClockSourceGet +#define MAP_SSIClockSourceGet \ + ROM_SSIClockSourceGet +#else +#define MAP_SSIClockSourceGet \ + SSIClockSourceGet +#endif +#ifdef ROM_SSIClockSourceSet +#define MAP_SSIClockSourceSet \ + ROM_SSIClockSourceSet +#else +#define MAP_SSIClockSourceSet \ + SSIClockSourceSet +#endif //***************************************************************************** // @@ -2340,6 +3567,82 @@ #define MAP_SysCtlDelay \ SysCtlDelay #endif +#ifdef ROM_SysCtlPeripheralReady +#define MAP_SysCtlPeripheralReady \ + ROM_SysCtlPeripheralReady +#else +#define MAP_SysCtlPeripheralReady \ + SysCtlPeripheralReady +#endif +#ifdef ROM_SysCtlPeripheralPowerOn +#define MAP_SysCtlPeripheralPowerOn \ + ROM_SysCtlPeripheralPowerOn +#else +#define MAP_SysCtlPeripheralPowerOn \ + SysCtlPeripheralPowerOn +#endif +#ifdef ROM_SysCtlPeripheralPowerOff +#define MAP_SysCtlPeripheralPowerOff \ + ROM_SysCtlPeripheralPowerOff +#else +#define MAP_SysCtlPeripheralPowerOff \ + SysCtlPeripheralPowerOff +#endif +#ifdef ROM_SysCtlMOSCConfigSet +#define MAP_SysCtlMOSCConfigSet \ + ROM_SysCtlMOSCConfigSet +#else +#define MAP_SysCtlMOSCConfigSet \ + SysCtlMOSCConfigSet +#endif +#ifdef ROM_SysCtlPIOSCCalibrate +#define MAP_SysCtlPIOSCCalibrate \ + ROM_SysCtlPIOSCCalibrate +#else +#define MAP_SysCtlPIOSCCalibrate \ + SysCtlPIOSCCalibrate +#endif +#ifdef ROM_SysCtlDeepSleepClockSet +#define MAP_SysCtlDeepSleepClockSet \ + ROM_SysCtlDeepSleepClockSet +#else +#define MAP_SysCtlDeepSleepClockSet \ + SysCtlDeepSleepClockSet +#endif + +//***************************************************************************** +// +// Macros for the SysExc API. +// +//***************************************************************************** +#ifdef ROM_SysExcIntStatus +#define MAP_SysExcIntStatus \ + ROM_SysExcIntStatus +#else +#define MAP_SysExcIntStatus \ + SysExcIntStatus +#endif +#ifdef ROM_SysExcIntClear +#define MAP_SysExcIntClear \ + ROM_SysExcIntClear +#else +#define MAP_SysExcIntClear \ + SysExcIntClear +#endif +#ifdef ROM_SysExcIntDisable +#define MAP_SysExcIntDisable \ + ROM_SysExcIntDisable +#else +#define MAP_SysExcIntDisable \ + SysExcIntDisable +#endif +#ifdef ROM_SysExcIntEnable +#define MAP_SysExcIntEnable \ + ROM_SysExcIntEnable +#else +#define MAP_SysExcIntEnable \ + SysExcIntEnable +#endif //***************************************************************************** // @@ -2485,6 +3788,20 @@ #define MAP_TimerPrescaleGet \ TimerPrescaleGet #endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif #ifdef ROM_TimerLoadSet #define MAP_TimerLoadSet \ ROM_TimerLoadSet @@ -2541,6 +3858,48 @@ #define MAP_TimerIntStatus \ TimerIntStatus #endif +#ifdef ROM_TimerControlWaitOnTrigger +#define MAP_TimerControlWaitOnTrigger \ + ROM_TimerControlWaitOnTrigger +#else +#define MAP_TimerControlWaitOnTrigger \ + TimerControlWaitOnTrigger +#endif +#ifdef ROM_TimerLoadSet64 +#define MAP_TimerLoadSet64 \ + ROM_TimerLoadSet64 +#else +#define MAP_TimerLoadSet64 \ + TimerLoadSet64 +#endif +#ifdef ROM_TimerLoadGet64 +#define MAP_TimerLoadGet64 \ + ROM_TimerLoadGet64 +#else +#define MAP_TimerLoadGet64 \ + TimerLoadGet64 +#endif +#ifdef ROM_TimerValueGet64 +#define MAP_TimerValueGet64 \ + ROM_TimerValueGet64 +#else +#define MAP_TimerValueGet64 \ + TimerValueGet64 +#endif +#ifdef ROM_TimerMatchSet64 +#define MAP_TimerMatchSet64 \ + ROM_TimerMatchSet64 +#else +#define MAP_TimerMatchSet64 \ + TimerMatchSet64 +#endif +#ifdef ROM_TimerMatchGet64 +#define MAP_TimerMatchGet64 \ + ROM_TimerMatchGet64 +#else +#define MAP_TimerMatchGet64 \ + TimerMatchGet64 +#endif //***************************************************************************** // @@ -2757,6 +4116,48 @@ #define MAP_UARTRxErrorClear \ UARTRxErrorClear #endif +#ifdef ROM_UARTClockSourceSet +#define MAP_UARTClockSourceSet \ + ROM_UARTClockSourceSet +#else +#define MAP_UARTClockSourceSet \ + UARTClockSourceSet +#endif +#ifdef ROM_UARTClockSourceGet +#define MAP_UARTClockSourceGet \ + ROM_UARTClockSourceGet +#else +#define MAP_UARTClockSourceGet \ + UARTClockSourceGet +#endif +#ifdef ROM_UART9BitEnable +#define MAP_UART9BitEnable \ + ROM_UART9BitEnable +#else +#define MAP_UART9BitEnable \ + UART9BitEnable +#endif +#ifdef ROM_UART9BitDisable +#define MAP_UART9BitDisable \ + ROM_UART9BitDisable +#else +#define MAP_UART9BitDisable \ + UART9BitDisable +#endif +#ifdef ROM_UART9BitAddrSet +#define MAP_UART9BitAddrSet \ + ROM_UART9BitAddrSet +#else +#define MAP_UART9BitAddrSet \ + UART9BitAddrSet +#endif +#ifdef ROM_UART9BitAddrSend +#define MAP_UART9BitAddrSend \ + ROM_UART9BitAddrSend +#else +#define MAP_UART9BitAddrSend \ + UART9BitAddrSend +#endif //***************************************************************************** // @@ -2896,6 +4297,41 @@ #define MAP_uDMAChannelSelectDefault \ uDMAChannelSelectDefault #endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif //***************************************************************************** // @@ -3056,13 +4492,6 @@ #define MAP_USBHostAddrSet \ USBHostAddrSet #endif -#ifdef ROM_USBHostEndpointConfig -#define MAP_USBHostEndpointConfig \ - ROM_USBHostEndpointConfig -#else -#define MAP_USBHostEndpointConfig \ - USBHostEndpointConfig -#endif #ifdef ROM_USBHostEndpointDataAck #define MAP_USBHostEndpointDataAck \ ROM_USBHostEndpointDataAck @@ -3287,6 +4716,34 @@ #define MAP_USBHostMode \ USBHostMode #endif +#ifdef ROM_USBDevMode +#define MAP_USBDevMode \ + ROM_USBDevMode +#else +#define MAP_USBDevMode \ + USBDevMode +#endif +#ifdef ROM_USBPHYPowerOff +#define MAP_USBPHYPowerOff \ + ROM_USBPHYPowerOff +#else +#define MAP_USBPHYPowerOff \ + USBPHYPowerOff +#endif +#ifdef ROM_USBPHYPowerOn +#define MAP_USBPHYPowerOn \ + ROM_USBPHYPowerOn +#else +#define MAP_USBPHYPowerOn \ + USBPHYPowerOn +#endif +#ifdef ROM_USBOTGMode +#define MAP_USBOTGMode \ + ROM_USBOTGMode +#else +#define MAP_USBOTGMode \ + USBOTGMode +#endif //***************************************************************************** // @@ -3398,6 +4855,13 @@ #define MAP_WatchdogStallDisable \ WatchdogStallDisable #endif +#ifdef ROM_WatchdogIntTypeSet +#define MAP_WatchdogIntTypeSet \ + ROM_WatchdogIntTypeSet +#else +#define MAP_WatchdogIntTypeSet \ + WatchdogIntTypeSet +#endif //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/rvmdk/driverlib.lib b/bsp/lm3s8962/Libraries/driverlib/rvmdk/driverlib.lib deleted file mode 100644 index 0b6f9f04c1..0000000000 Binary files a/bsp/lm3s8962/Libraries/driverlib/rvmdk/driverlib.lib and /dev/null differ diff --git a/bsp/lm3s8962/Libraries/driverlib/ssi.c b/bsp/lm3s8962/Libraries/driverlib/ssi.c index 8ee31e52e9..d46b29b474 100644 --- a/bsp/lm3s8962/Libraries/driverlib/ssi.c +++ b/bsp/lm3s8962/Libraries/driverlib/ssi.c @@ -2,7 +2,7 @@ // // ssi.c - Driver for Synchronous Serial Interface. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -37,6 +37,83 @@ #include "driverlib/interrupt.h" #include "driverlib/ssi.h" +//***************************************************************************** +// +// A mapping of timer base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulSSIIntMap[][2] = +{ + { SSI0_BASE, INT_SSI0 }, + { SSI1_BASE, INT_SSI1 }, + { SSI2_BASE, INT_SSI2 }, + { SSI3_BASE, INT_SSI3 }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks an SSI base address. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function determines if a SSI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +SSIBaseValid(unsigned long ulBase) +{ + return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) || + (ulBase == SSI2_BASE) || (ulBase == SSI3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the SSI interrupt number. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! Given a SSI base address, returns the corresponding interrupt number. +//! +//! \return Returns an SSI interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +SSIIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps SSI base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulSSIIntMap) / + sizeof(g_ppulSSIIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulSSIIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulSSIIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + //***************************************************************************** // //! Configures the synchronous serial interface. @@ -55,7 +132,7 @@ //! \e ulProtocol parameter can be one of the following values: //! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, //! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola -//! frame formats imply the following polarity and phase configurations: +//! frame formats encode the following polarity and phase configurations: //! //! 
 //! Polarity Phase       Mode
@@ -66,26 +143,27 @@
 //!
//! //! The \e ulMode parameter defines the operating mode of the SSI module. The -//! SSI module can operate as a master or slave; if a slave, the SSI can be -//! configured to disable output on its serial output line. The \e ulMode +//! SSI module can operate as a master or slave; if it is a slave, the SSI can +//! be configured to disable output on its serial output line. The \e ulMode //! parameter can be one of the following values: \b SSI_MODE_MASTER, //! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. //! //! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate //! must satisfy the following clock ratio criteria: //! -//! - FSSI >= 2 * bit rate (master mode) -//! - FSSI >= 12 * bit rate (slave modes) +//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz. +//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the +//! capability of the specific microcontroller //! //! where FSSI is the frequency of the clock supplied to the SSI module. //! -//! The \e ulDataWidth parameter defines the width of the data transfers, and +//! The \e ulDataWidth parameter defines the width of the data transfers and //! can be a value between 4 and 16, inclusive. //! -//! The peripheral clock will be the same as the processor clock. This will be -//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded -//! if it is constant and known (to save the code/execution overhead of a call -//! to SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. This value is +//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtlClockGet()). //! //! This function replaces the original SSIConfig() API and performs the same //! actions. A macro is provided in ssi.h to map the original API to @@ -108,7 +186,7 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || (ulProtocol == SSI_FRF_MOTO_MODE_1) || (ulProtocol == SSI_FRF_MOTO_MODE_2) || @@ -170,7 +248,7 @@ SSIEnable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Read-modify-write the enable bit. @@ -195,7 +273,7 @@ SSIDisable(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Read-modify-write the enable bit. @@ -211,11 +289,11 @@ SSIDisable(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! synchronous serial interface interrupt occurs. //! -//! This sets the handler to be called when an SSI interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, -//! it is the interrupt handler's responsibility to clear the interrupt source -//! via SSIIntClear(). +//! This function registers the handler to be called when an SSI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via SSIIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -231,12 +309,12 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Determine the interrupt number based on the SSI port. // - ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1; + ulInt = SSIIntNumberGet(ulBase); // // Register the interrupt handler, returning an error if an error occurs. @@ -255,8 +333,8 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase specifies the SSI module base address. //! -//! This function will clear the handler to be called when a SSI -//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! This function clears the handler to be called when an SSI interrupt +//! occurs. This function also masks off the interrupt in the interrupt //! controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt @@ -273,12 +351,12 @@ SSIIntUnregister(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Determine the interrupt number based on the SSI port. // - ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1; + ulInt = SSIIntNumberGet(ulBase); // // Disable the interrupt. @@ -298,10 +376,11 @@ SSIIntUnregister(unsigned long ulBase) //! \param ulBase specifies the SSI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated SSI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. The \e ulIntFlags parameter can be any of the -//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values. +//! This function enables the indicated SSI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. The \e ulIntFlags +//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or +//! \b SSI_RXOR values. //! //! \return None. // @@ -312,7 +391,7 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Enable the specified interrupts. @@ -327,9 +406,9 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase specifies the SSI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter -//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR -//! values. +//! This function disables the indicated SSI interrupt sources. The +//! \e ulIntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, +//! \b SSI_RXTO, or \b SSI_RXOR values. //! //! \return None. // @@ -340,7 +419,7 @@ SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Disable the specified interrupts. @@ -370,7 +449,7 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Return either the interrupt status or the raw interrupt status as @@ -393,20 +472,20 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase specifies the SSI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! The specified SSI interrupt sources are cleared so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupts from being recognized again immediately upon exit. The +//! This function clears the specified SSI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The //! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and //! \b SSI_RXOR values. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -417,7 +496,7 @@ SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Clear the requested interrupt sources. @@ -449,7 +528,7 @@ SSIDataPut(unsigned long ulBase, unsigned long ulData) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & SSI_CR0_DSS_M))) == 0); @@ -495,7 +574,7 @@ SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & SSI_CR0_DSS_M))) == 0); @@ -540,7 +619,7 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Wait until there is data to be read. @@ -565,7 +644,7 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData) //! //! This function gets received data from the receive FIFO of the specified SSI //! module and places that data into the location specified by the \e ulData -//! parameter. If there is no data in the FIFO, then this function returns a +//! parameter. If there is no data in the FIFO, then this function returns a //! zero. //! //! This function replaces the original SSIDataNonBlockingGet() API and @@ -587,7 +666,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Check for data to read. @@ -610,7 +689,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) //! \param ulBase is the base address of the SSI port. //! \param ulDMAFlags is a bit mask of the DMA features to enable. //! -//! The specified SSI DMA features are enabled. The SSI can be +//! This function enables the specified SSI DMA features. The SSI can be //! configured to use DMA for transmit and/or receive data transfers. //! The \e ulDMAFlags parameter is the logical OR of any of the following //! values: @@ -630,10 +709,10 @@ SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // - // Set the requested bits in the UART DMA control register. + // Set the requested bits in the SSI DMA control register. // HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags; } @@ -661,10 +740,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // - // Clear the requested bits in the UART DMA control register. + // Clear the requested bits in the SSI DMA control register. // HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags; } @@ -675,10 +754,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) //! //! \param ulBase is the base address of the SSI port. //! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \b false is returned, then the transmit FIFO -//! is empty and all bits of the last transmitted word have left the hardware -//! shift register. +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. //! //! \return Returns \b true if the SSI is transmitting or \b false if all //! transmissions are complete. @@ -690,7 +769,7 @@ SSIBusy(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT(SSIBaseValid(ulBase)); // // Determine if the SSI is busy. @@ -698,6 +777,74 @@ SSIBusy(unsigned long ulBase) return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false); } +//***************************************************************************** +// +//! Sets the data clock source for the specified SSI peripheral. +//! +//! \param ulBase is the base address of the SSI port. +//! \param ulSource is the baud clock source for the SSI. +//! +//! This function allows the baud clock source for the SSI to be selected. +//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). +//! +//! Changing the baud clock source changes the data rate generated by the +//! SSI. Therefore, the data rate should be reconfigured after any change to +//! the SSI clock source. +//! +//! \note The ability to specify the SSI baud clock source varies with the +//! Stellaris part and SSI in use. Please consult the data sheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + ASSERT((ulSource == SSI_CLOCK_SYSTEM) || (ulSource == SSI_CLOCK_PIOSC)); + + // + // Set the SSI clock source. + // + HWREG(ulBase + SSI_O_CC) = ulSource; +} + +//***************************************************************************** +// +//! Gets the data clock source for the specified SSI peripheral. +//! +//! \param ulBase is the base address of the SSI port. +//! +//! This function returns the data clock source for the specified SSI. The +//! possible data clock source are the system clock (\b SSI_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). +//! +//! \note The ability to specify the SSI data clock source varies with the +//! Stellaris part and SSI in use. Please consult the data sheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +SSIClockSourceGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ulBase)); + + // + // Return the SSI clock source. + // + return(HWREG(ulBase + SSI_O_CC)); +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm3s8962/Libraries/driverlib/ssi.h b/bsp/lm3s8962/Libraries/driverlib/ssi.h index 6f409224cd..b0cfd1ec5b 100644 --- a/bsp/lm3s8962/Libraries/driverlib/ssi.h +++ b/bsp/lm3s8962/Libraries/driverlib/ssi.h @@ -2,7 +2,7 @@ // // ssi.h - Prototypes for the Synchronous Serial Interface Driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -71,6 +71,15 @@ extern "C" #define SSI_DMA_TX 0x00000002 // Enable DMA for transmit #define SSI_DMA_RX 0x00000001 // Enable DMA for receive +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +#define SSI_CLOCK_SYSTEM 0x00000000 +#define SSI_CLOCK_PIOSC 0x00000001 + //***************************************************************************** // // Prototypes for the APIs. @@ -96,6 +105,8 @@ extern void SSIIntUnregister(unsigned long ulBase); extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); extern tBoolean SSIBusy(unsigned long ulBase); +extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource); +extern unsigned long SSIClockSourceGet(unsigned long ulBase); //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/sysctl.c b/bsp/lm3s8962/Libraries/driverlib/sysctl.c index a0d37d1eb9..43755758e4 100644 --- a/bsp/lm3s8962/Libraries/driverlib/sysctl.c +++ b/bsp/lm3s8962/Libraries/driverlib/sysctl.c @@ -2,7 +2,7 @@ // // sysctl.c - Driver for the system controller. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -152,9 +152,26 @@ static const unsigned long g_pulXtals[] = 13560000, 14318180, 16000000, - 16384000 + 16384000, + 18000000, + 20000000, + 24000000, + 25000000 }; +//***************************************************************************** +// +// The base addresses of the various peripheral control registers. +// +//***************************************************************************** +#define SYSCTL_PPBASE 0x400fe300 +#define SYSCTL_SRBASE 0x400fe500 +#define SYSCTL_RCGCBASE 0x400fe600 +#define SYSCTL_SCGCBASE 0x400fe700 +#define SYSCTL_DCGCBASE 0x400fe800 +#define SYSCTL_PCBASE 0x400fe900 +#define SYSCTL_PRBASE 0x400fea00 + //***************************************************************************** // //! \internal @@ -180,8 +197,10 @@ SysCtlPeripheralValid(unsigned long ulPeripheral) (ulPeripheral == SYSCTL_PERIPH_COMP0) || (ulPeripheral == SYSCTL_PERIPH_COMP1) || (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_EEPROM0) || (ulPeripheral == SYSCTL_PERIPH_EPI0) || (ulPeripheral == SYSCTL_PERIPH_ETH) || + (ulPeripheral == SYSCTL_PERIPH_FAN0) || (ulPeripheral == SYSCTL_PERIPH_GPIOA) || (ulPeripheral == SYSCTL_PERIPH_GPIOB) || (ulPeripheral == SYSCTL_PERIPH_GPIOC) || @@ -191,33 +210,143 @@ SysCtlPeripheralValid(unsigned long ulPeripheral) (ulPeripheral == SYSCTL_PERIPH_GPIOG) || (ulPeripheral == SYSCTL_PERIPH_GPIOH) || (ulPeripheral == SYSCTL_PERIPH_GPIOJ) || + (ulPeripheral == SYSCTL_PERIPH_GPIOK) || + (ulPeripheral == SYSCTL_PERIPH_GPIOL) || + (ulPeripheral == SYSCTL_PERIPH_GPIOM) || + (ulPeripheral == SYSCTL_PERIPH_GPION) || + (ulPeripheral == SYSCTL_PERIPH_GPIOP) || + (ulPeripheral == SYSCTL_PERIPH_GPIOQ) || (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) || (ulPeripheral == SYSCTL_PERIPH_I2C0) || (ulPeripheral == SYSCTL_PERIPH_I2C1) || + (ulPeripheral == SYSCTL_PERIPH_I2C2) || + (ulPeripheral == SYSCTL_PERIPH_I2C3) || + (ulPeripheral == SYSCTL_PERIPH_I2C4) || + (ulPeripheral == SYSCTL_PERIPH_I2C5) || (ulPeripheral == SYSCTL_PERIPH_I2S0) || (ulPeripheral == SYSCTL_PERIPH_IEEE1588) || + (ulPeripheral == SYSCTL_PERIPH_LPC0) || (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_PECI0) || (ulPeripheral == SYSCTL_PERIPH_PLL) || - (ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_PWM0) || + (ulPeripheral == SYSCTL_PERIPH_PWM1) || (ulPeripheral == SYSCTL_PERIPH_QEI0) || (ulPeripheral == SYSCTL_PERIPH_QEI1) || (ulPeripheral == SYSCTL_PERIPH_SSI0) || (ulPeripheral == SYSCTL_PERIPH_SSI1) || + (ulPeripheral == SYSCTL_PERIPH_SSI2) || + (ulPeripheral == SYSCTL_PERIPH_SSI3) || (ulPeripheral == SYSCTL_PERIPH_TEMP) || (ulPeripheral == SYSCTL_PERIPH_TIMER0) || (ulPeripheral == SYSCTL_PERIPH_TIMER1) || (ulPeripheral == SYSCTL_PERIPH_TIMER2) || (ulPeripheral == SYSCTL_PERIPH_TIMER3) || + (ulPeripheral == SYSCTL_PERIPH_TIMER4) || + (ulPeripheral == SYSCTL_PERIPH_TIMER5) || (ulPeripheral == SYSCTL_PERIPH_UART0) || (ulPeripheral == SYSCTL_PERIPH_UART1) || (ulPeripheral == SYSCTL_PERIPH_UART2) || + (ulPeripheral == SYSCTL_PERIPH_UART3) || + (ulPeripheral == SYSCTL_PERIPH_UART4) || + (ulPeripheral == SYSCTL_PERIPH_UART5) || + (ulPeripheral == SYSCTL_PERIPH_UART6) || + (ulPeripheral == SYSCTL_PERIPH_UART7) || (ulPeripheral == SYSCTL_PERIPH_UDMA) || (ulPeripheral == SYSCTL_PERIPH_USB0) || (ulPeripheral == SYSCTL_PERIPH_WDOG0) || - (ulPeripheral == SYSCTL_PERIPH_WDOG1)); + (ulPeripheral == SYSCTL_PERIPH_WDOG1) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER0) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER1) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER2) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER3) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER4) || + (ulPeripheral == SYSCTL_PERIPH_WTIMER5)); } #endif +//***************************************************************************** +// +// A map of old peripheral defines to new peripheral defines. Note that the +// new peripheral defines will not work on parts that precede Blizzard class. +// +//***************************************************************************** +static const unsigned long g_ppulPeripheralMap[][2] = +{ + { SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH2_ADC0 }, + { SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH2_ADC1 }, + { SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH2_CAN0 }, + { SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH2_CAN1 }, + { SYSCTL_PERIPH_CAN2, SYSCTL_PERIPH2_CAN2 }, + { SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH2_COMP0 }, + { SYSCTL_PERIPH_COMP1, SYSCTL_PERIPH2_COMP0 }, + { SYSCTL_PERIPH_COMP2, SYSCTL_PERIPH2_COMP0 }, + { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH2_GPIOA }, + { SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH2_GPIOB }, + { SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH2_GPIOC }, + { SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH2_GPIOD }, + { SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH2_GPIOE }, + { SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH2_GPIOF }, + { SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH2_GPIOG }, + { SYSCTL_PERIPH_GPIOH, SYSCTL_PERIPH2_GPIOH }, + { SYSCTL_PERIPH_GPIOJ, SYSCTL_PERIPH2_GPIOJ }, + { SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH2_I2C0 }, + { SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH2_I2C1 }, + { SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH2_PWM0 }, + { SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH2_QEI0 }, + { SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH2_QEI1 }, + { SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH2_SSI0 }, + { SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH2_SSI1 }, + { SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH2_TIMER0 }, + { SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH2_TIMER1 }, + { SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH2_TIMER2 }, + { SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH2_TIMER3 }, + { SYSCTL_PERIPH_UART0, SYSCTL_PERIPH2_UART0 }, + { SYSCTL_PERIPH_UART1, SYSCTL_PERIPH2_UART1 }, + { SYSCTL_PERIPH_UART2, SYSCTL_PERIPH2_UART2 }, + { SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH2_UDMA }, + { SYSCTL_PERIPH_USB0, SYSCTL_PERIPH2_USB0 }, + { SYSCTL_PERIPH_WDOG0, SYSCTL_PERIPH2_WDOG0 }, + { SYSCTL_PERIPH_WDOG1, SYSCTL_PERIPH2_WDOG1 }, +}; + +//***************************************************************************** +// +// Maps a SYSCTL_PERIPH_foo identifier into its new-style SYSCTL_PERIPH2_foo +// identifier. +// +//***************************************************************************** +static unsigned long +SysCtlPeripheralMapToNew(unsigned long ulPeripheral) +{ + unsigned long ulIndex; + + // + // Loop throug the table of old-style identifiers. + // + for(ulIndex = 0; ulIndex < (sizeof(g_ppulPeripheralMap) / + sizeof(g_ppulPeripheralMap[0])); ulIndex++) + { + // + // See if this peripheral matches the old-style identifer. + // + if(g_ppulPeripheralMap[ulIndex][0] == ulPeripheral) + { + // + // Return the new-style identifier that corresponds to this + // peripheral. + // + return(g_ppulPeripheralMap[ulIndex][1]); + } + } + + // + // No old-style identifier was found, so return the identifier unchanged + // (on the assumption that it is already a new-style identifier). + // + return(ulPeripheral); +} + //***************************************************************************** // //! Gets the size of the SRAM. @@ -260,10 +389,10 @@ SysCtlFlashSizeGet(void) //! //! \param ulPin is the pin in question. //! -//! Determines if a particular pin is present in the device. The PWM, analog -//! comparators, ADC, and timers have a varying number of pins across members -//! of the Stellaris family; this will determine which are present on this -//! device. +//! This function determines if a particular pin is present in the device. The +//! PWM, analog comparators, ADC, and timers have a varying number of pins +//! across members of the Stellaris family; this function determines which pins +//! are present on this device. //! //! The \e ulPin argument must be only one of the following values: //! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, @@ -339,26 +468,36 @@ SysCtlPinPresent(unsigned long ulPin) //! //! \param ulPeripheral is the peripheral in question. //! -//! Determines if a particular peripheral is present in the device. Each -//! member of the Stellaris family has a different peripheral set; this will -//! determine which are present on this device. +//! This function determines if a particular peripheral is present in the +//! device. Each member of the Stellaris family has a different peripheral +//! set; this function determines which peripherals are present on this device. //! //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_IEEE1588, -//! \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, -//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_GPIOK, +//! \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, \b SYSCTL_PERIPH_GPION, +//! \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, \b SYSCTL_PERIPH_HIBERNATE, +//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, +//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, +//! \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PLL, +//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5, //! //! \return Returns \b true if the specified peripheral is present and \b false //! if it is not. @@ -373,12 +512,21 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Read the correct DC register and determine if this peripheral exists. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_PPperiph registers. // - if(ulPeripheral == SYSCTL_PERIPH_USB0) + if((ulPeripheral & 0xf0000000) == 0xf0000000) { // - // USB is a special case since the DC bit is missing for USB0. + // See if this peripheral is present. + // + return(HWREGBITW(SYSCTL_PPBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff)); + } + else if(ulPeripheral == SYSCTL_PERIPH_USB0) + { + // + // USB is a special case because the DC bit is missing for USB0. // if(HWREG(SYSCTL_DC6) & SYSCTL_DC6_USB0_M) { @@ -400,6 +548,199 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral) } } +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! The \e ulPeripheral paramter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note The ability to check for a peripheral being ready varies based on the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine if this feature is available. +//! +//! \return Returns \b true if the specified peripheral is ready and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +SysCtlPeripheralReady(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Map the peripheral identifier to the new style identifiers. If it is + // already a new style identifier, this is a NOP. + // + ulPeripheral = SysCtlPeripheralMapToNew(ulPeripheral); + + // + // See if this peripheral is ready. + // + return(HWREGBITW(SYSCTL_PRBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff)); +} + +//***************************************************************************** +// +//! Powers on a peripheral. +//! +//! \param ulPeripheral is the peripheral to be powered on. +//! +//! This function turns on the power to a peripheral. The peripheral continues +//! to receive power even when its clock is not enabled. +//! +//! The \e ulPeripheral paramter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note The ability to power off a peripheral varies based on the Stellaris +//! part in use. Please consult the data sheet for the part you are using to +//! determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralPowerOn(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Map the peripheral identifier to the new style identifiers. If it is + // already a new style identifier, this is a NOP. + // + ulPeripheral = SysCtlPeripheralMapToNew(ulPeripheral); + + // + // Power on this peripheral. + // + HWREGBITW(SYSCTL_PCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; +} + +//***************************************************************************** +// +//! Powers off a peripheral. +//! +//! \param ulPeripheral is the peripheral to be powered off. +//! +//! This function allows the power to a peripheral to be turned off. The +//! peripheral continues to receive power when its clock is enabled, but +//! the power is removed when its clock is disabled. +//! +//! The \e ulPeripheral paramter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, +//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, +//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. +//! +//! \note The ability to power off a peripheral varies based on the Stellaris +//! part in use. Please consult the data sheet for the part you are using to +//! determine if this feature is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralPowerOff(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Map the peripheral identifier to the new style identifiers. If it is + // already a new style identifier, this is a NOP. + // + ulPeripheral = SysCtlPeripheralMapToNew(ulPeripheral); + + // + // Power off this peripheral. + // + HWREGBITW(SYSCTL_PCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; +} + //***************************************************************************** // //! Performs a software reset of a peripheral. @@ -414,18 +755,28 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral) //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \return None. // @@ -441,23 +792,51 @@ SysCtlPeripheralReset(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Put the peripheral into the reset state. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_SRperiph registers. // - HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= - SYSCTL_PERIPH_MASK(ulPeripheral); - - // - // Delay for a little bit. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) + if((ulPeripheral & 0xf0000000) == 0xf0000000) { - } + // + // Put the peripheral into the reset state. + // + HWREGBITW(SYSCTL_SRBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; - // - // Take the peripheral out of the reset state. - // - HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= - ~SYSCTL_PERIPH_MASK(ulPeripheral); + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREGBITW(SYSCTL_SRBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -466,29 +845,39 @@ SysCtlPeripheralReset(unsigned long ulPeripheral) //! //! \param ulPeripheral is the peripheral to enable. //! -//! Peripherals are enabled with this function. At power-up, all peripherals +//! This function enables peripherals. At power-up, all peripherals //! are disabled; they must be enabled in order to operate or respond to //! register reads/writes. //! //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \note It takes five clock cycles after the write to enable a peripheral //! before the the peripheral is actually enabled. During this time, attempts -//! to access the peripheral will result in a bus fault. Care should be taken +//! to access the peripheral result in a bus fault. Care should be taken //! to ensure that the peripheral is not accessed during this brief time //! period. //! @@ -504,10 +893,25 @@ SysCtlPeripheralEnable(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Enable this peripheral. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_RCGCperiph registers. // - HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= - SYSCTL_PERIPH_MASK(ulPeripheral); + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Enable this peripheral. + // + HWREGBITW(SYSCTL_RCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + } + else + { + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -516,24 +920,34 @@ SysCtlPeripheralEnable(unsigned long ulPeripheral) //! //! \param ulPeripheral is the peripheral to disable. //! -//! Peripherals are disabled with this function. Once disabled, they will not -//! operate or respond to register reads/writes. +//! This function disables peripherals are disabled with this function. Once +//! disabled, they do not operate or respond to register reads/writes. //! //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \return None. // @@ -547,10 +961,25 @@ SysCtlPeripheralDisable(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Disable this peripheral. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_RCGCperiph registers. // - HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= - ~SYSCTL_PERIPH_MASK(ulPeripheral); + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Disable this peripheral. + // + HWREGBITW(SYSCTL_RCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -560,9 +989,9 @@ SysCtlPeripheralDisable(unsigned long ulPeripheral) //! \param ulPeripheral is the peripheral to enable in sleep mode. //! //! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Since the clocking configuration of the device does -//! not change, any peripheral can safely continue operating while the -//! processor is in sleep mode, and can therefore wake the processor from sleep +//! goes into sleep mode. Because the clocking configuration of the device +//! does not change, any peripheral can safely continue operating while the +//! processor is in sleep mode and can therefore wake the processor from sleep //! mode. //! //! Sleep mode clocking of peripherals must be enabled via @@ -572,18 +1001,28 @@ SysCtlPeripheralDisable(unsigned long ulPeripheral) //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \return None. // @@ -597,10 +1036,25 @@ SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Enable this peripheral in sleep mode. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_SCGCperiph registers. // - HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= - SYSCTL_PERIPH_MASK(ulPeripheral); + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Enable this peripheral in sleep mode. + // + HWREGBITW(SYSCTL_SCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + } + else + { + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -612,7 +1066,7 @@ SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) //! This function causes a peripheral to stop operating when the processor goes //! into sleep mode. Disabling peripherals while in sleep mode helps to lower //! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), -//! the peripheral will automatically resume operation when the processor +//! the peripheral automatically resumes operation when the processor //! leaves sleep mode, maintaining its entire state from before sleep mode was //! entered. //! @@ -623,18 +1077,28 @@ SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \return None. // @@ -648,10 +1112,25 @@ SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Disable this peripheral in sleep mode. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_SCGCperiph registers. // - HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= - ~SYSCTL_PERIPH_MASK(ulPeripheral); + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Disable this peripheral in sleep mode. + // + HWREGBITW(SYSCTL_SCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -661,11 +1140,11 @@ SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) //! \param ulPeripheral is the peripheral to enable in deep-sleep mode. //! //! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Since the clocking configuration of the device -//! may change, not all peripherals can safely continue operating while the -//! processor is in sleep mode. Those that must run at a particular frequency -//! (such as a UART) will not work as expected if the clock changes. It is the -//! responsibility of the caller to make sensible choices. +//! goes into deep-sleep mode. Because the clocking configuration of the +//! device may change, not all peripherals can safely continue operating while +//! the processor is in sleep mode. Those that must run at a particular +//! frequency (such as a UART) do not work as expected if the clock changes. +//! It is the responsibility of the caller to make sensible choices. //! //! Deep-sleep mode clocking of peripherals must be enabled via //! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode @@ -675,18 +1154,28 @@ SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \return None. // @@ -700,10 +1189,25 @@ SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Enable this peripheral in deep-sleep mode. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_DCGCperiph registers. // - HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= - SYSCTL_PERIPH_MASK(ulPeripheral); + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Enable this peripheral in deep-sleep mode. + // + HWREGBITW(SYSCTL_DCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 1; + } + else + { + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -717,7 +1221,7 @@ SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) //! to lower the current draw of the device, and can keep peripherals that //! require a particular clock frequency from operating when the clock changes //! as a result of entering deep-sleep mode. If enabled (via -//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! SysCtlPeripheralEnable()), the peripheral automatically resumes //! operation when the processor leaves deep-sleep mode, maintaining its entire //! state from before deep-sleep mode was entered. //! @@ -729,18 +1233,28 @@ SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, -//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, -//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, -//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, -//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0, +//! \b SYSCTL_PERIPH_EPI0, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_FAN0, +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, +//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, +//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, +//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, +//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, +//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_LPC0, +//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, //! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, -//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, -//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP, +//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or -//! \b SYSCTL_PERIPH_WDOG1. +//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5, +//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1, +//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, +//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, +//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \return None. // @@ -754,10 +1268,25 @@ SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) ASSERT(SysCtlPeripheralValid(ulPeripheral)); // - // Disable this peripheral in deep-sleep mode. + // See if the peripheral index is 15, indicating a peripheral that is + // accessed via the SYSCTL_DCGCperiph registers. // - HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= - ~SYSCTL_PERIPH_MASK(ulPeripheral); + if((ulPeripheral & 0xf0000000) == 0xf0000000) + { + // + // Disable this peripheral in deep-sleep mode. + // + HWREGBITW(SYSCTL_DCGCBASE + ((ulPeripheral & 0xff00) >> 8), + ulPeripheral & 0xff) = 0; + } + else + { + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); + } } //***************************************************************************** @@ -769,10 +1298,10 @@ SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) //! //! This function controls how peripherals are clocked when the processor goes //! into sleep or deep-sleep mode. By default, the peripherals are clocked the -//! same as in run mode; if peripheral clock gating is enabled they are clocked -//! according to the configuration set by SysCtlPeripheralSleepEnable(), -//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and -//! SysCtlPeripheralDeepSleepDisable(). +//! same as in run mode; if peripheral clock gating is enabled, they are +//! clocked according to the configuration set by +//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), +//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable(). //! //! \return None. // @@ -800,20 +1329,24 @@ SysCtlPeripheralClockGating(tBoolean bEnable) //! \param pfnHandler is a pointer to the function to be called when the system //! control interrupt occurs. //! -//! This sets the handler to be called when a system control interrupt occurs. -//! This will enable the global interrupt in the interrupt controller; specific -//! system control interrupts must be enabled via SysCtlIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! SysCtlIntClear(). +//! This function registers the handler to be called when a system control +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific system control interrupts must be enabled +//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via SysCtlIntClear(). //! //! System control can generate interrupts when the PLL achieves lock, if the //! internal LDO current limit is exceeded, if the internal oscillator fails, //! if the main oscillator fails, if the internal LDO output voltage droops too -//! much, if the external voltage droops too much, or if the PLL fails. +//! much, if the external voltage droops too much, or if the PLL fails. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. //! +//! \note The events that cause system control interrupts vary based on the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine which interrupt sources are available. +//! //! \return None. // //***************************************************************************** @@ -835,9 +1368,9 @@ SysCtlIntRegister(void (*pfnHandler)(void)) // //! Unregisters the interrupt handler for the system control interrupt. //! -//! This function will clear the handler to be called when a system control -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when a system control +//! interrupt occurs. This function also masks off the interrupt in the +//! interrupt controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -868,9 +1401,13 @@ SysCtlIntUnregister(void) //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. //! -//! Enables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. +//! This function enables the indicated system control interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. //! //! \return None. // @@ -893,9 +1430,13 @@ SysCtlIntEnable(unsigned long ulInts) //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. //! -//! Disables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. +//! This function disables the indicated system control interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. //! //! \return None. // @@ -919,17 +1460,21 @@ SysCtlIntDisable(unsigned long ulInts) //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. //! //! The specified system control interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. +//! longer assert. This function must be called in the interrupt handler to +//! keep it from being called again immediately upon exit. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. //! //! \return None. // @@ -950,14 +1495,18 @@ SysCtlIntClear(unsigned long ulInts) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the system controller. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the system controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return The current interrupt status, enumerated as a bit field of //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, //! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and //! \b SYSCTL_INT_PLL_FAIL. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. // //***************************************************************************** unsigned long @@ -987,8 +1536,11 @@ SysCtlIntStatus(tBoolean bMasked) //! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, //! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. //! -//! This function sets the output voltage of the LDO. The default voltage is -//! 2.5 V; it can be adjusted +/- 10%. +//! This function sets the output voltage of the LDO. +//! +//! \note The default LDO voltage and the adjustment range varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine the default voltage and range available. //! //! \return None. // @@ -1024,7 +1576,7 @@ SysCtlLDOSet(unsigned long ulVoltage) //! This function determines the output voltage of the LDO, as specified by the //! control register. //! -//! \return Returns the current voltage of the LDO; will be one of +//! \return Returns the current voltage of the LDO; is one of //! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, //! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, //! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, @@ -1074,10 +1626,10 @@ SysCtlLDOConfigSet(unsigned long ulConfig) // //! Resets the device. //! -//! This function will perform a software reset of the entire device. The -//! processor and all peripherals will be reset and all device registers will -//! return to their default values (with the exception of the reset cause -//! register, which will maintain its current value but have the software reset +//! This function performs a software reset of the entire device. The +//! processor and all peripherals are reset and all device registers are +//! returned to their default values (with the exception of the reset cause +//! register, which maintains its current value but has the software reset //! bit set as well). //! //! \return This function does not return. @@ -1087,8 +1639,8 @@ void SysCtlReset(void) { // - // Perform a software reset request. This will cause the device to reset, - // no further code will be executed. + // Perform a software reset request. This request causes the device to + // reset, no further code is executed. // HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; @@ -1105,7 +1657,7 @@ SysCtlReset(void) // //! Puts the processor into sleep mode. //! -//! This function places the processor into sleep mode; it will not return +//! This function places the processor into sleep mode; it does not return //! until the processor returns to run mode. The peripherals that are enabled //! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the //! processor (if automatic clock gating is enabled with @@ -1128,7 +1680,7 @@ SysCtlSleep(void) // //! Puts the processor into deep-sleep mode. //! -//! This function places the processor into deep-sleep mode; it will not return +//! This function places the processor into deep-sleep mode; it does not return //! until the processor returns to run mode. The peripherals that are enabled //! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up //! the processor (if automatic clock gating is enabled with @@ -1161,10 +1713,11 @@ SysCtlDeepSleep(void) // //! Gets the reason for a reset. //! -//! This function will return the reason(s) for a reset. Since the reset -//! reasons are sticky until either cleared by software or an external reset, +//! This function returns the reason(s) for a reset. Because the reset +//! reasons are sticky until either cleared by software or an external reset +//! (for Sandstorm-class devices) or a power-on reset (for all other classes), //! multiple reset reasons may be returned if multiple resets have occurred. -//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, +//! The reset reason is a logical OR of \b SYSCTL_CAUSE_LDO, //! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, //! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. //! @@ -1223,6 +1776,10 @@ SysCtlResetCauseClear(unsigned long ulCauses) //! When it detects a brown-out condition, it can either reset the device or //! generate a processor interrupt. //! +//! \note The availability of the resample feature is only available on +//! Sandstorm-class devices. Please consult the datasheet for the part you +//! are using to determine whether this feature is available. +//! //! \return None. // //***************************************************************************** @@ -1283,21 +1840,126 @@ SysCtlDelay(unsigned long ulCount) bx lr; } #endif +// +// For CCS implement this function in pure assembly. This prevents the TI +// compiler from doing funny things with the optimizer. +// #if defined(ccs) -volatile unsigned long g_ulInlineCCSWorkaround; -void -SysCtlDelay(unsigned long ulCount) -{ - __asm("delay?: subs r0, #1\n" - " bne.n delay?\n" + __asm(" .sect \".text:SysCtlDelay\"\n" + " .clink\n" + " .thumbfunc SysCtlDelay\n" + " .thumb\n" + " .global SysCtlDelay\n" + "SysCtlDelay:\n" + " subs r0, #1\n" + " bne.n SysCtlDelay\n" " bx lr\n"); +#endif + +//***************************************************************************** +// +//! Sets the configuration of the main oscillator (MOSC) control. +//! +//! \param ulConfig is the required configuration of the MOSC control. +//! +//! This function configures the control of the main oscillator. The +//! \e ulConfig is specified as follows: +//! +//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that +//! detects a failure of the main oscillator (such as a loss of the clock). +//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an +//! interrupt instead of resetting the processor. +//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal connected to +//! the OSC0/OSC1 pins, allowing power consumption to be reduced. +//! +//! \note The availability of MOSC control varies based on the Stellaris part +//! in use. Please consult the data sheet for the part you are using to +//! determine whether this support is available. In addition, the capability +//! of MOSC control varies based on the Stellaris part in use. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlMOSCConfigSet(unsigned long ulConfig) +{ + // + // Configure the MOSC control. + // + HWREG(SYSCTL_MOSCCTL) = ulConfig; +} + +//***************************************************************************** +// +//! Calibrates the precision internal oscillator. +//! +//! \param ulType is the type of calibration to perform. +//! +//! This function performs a calibration of the PIOSC. There are three types +//! of calibration available; the desired calibration type as specified in +//! \e ulType is one of: +//! +//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the +//! 32-kHz clock from the hibernate module as a reference. This type is +//! only possible on parts that have a hibernate module, and then only if +//! it is enabled and the hibernate module's RTC is also enabled. +//! +//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory +//! provided calibration. +//! +//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied +//! value. The value to be used is ORed into the lower 7-bits of this value, +//! with 0x40 being the ``nominal'' value (in other words, if everything were +//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 +//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +SysCtlPIOSCCalibrate(unsigned long ulType) +{ + // + // Perform the requested calibration. If performing user calibration, the + // UTEN bit must be set with one write, then the UT field in a second + // write, and the UPDATE bit in a final write. For other calibration + // types, a single write to set UPDATE or CAL is all that is required. + // + if(ulType & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE)) + { + HWREG(SYSCTL_PIOSCCAL) = ulType & SYSCTL_PIOSCCAL_UTEN; + HWREG(SYSCTL_PIOSCCAL) = + ulType & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M); + } + HWREG(SYSCTL_PIOSCCAL) = ulType; // - // This is needed to keep TI compiler from optimizing away this code. + // See if an automatic calibration was requested. // - g_ulInlineCCSWorkaround += ulCount; + if(ulType & SYSCTL_PIOSCCAL_CAL) + { + // + // Wait for the automatic calibration to complete. + // + while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0) + { + } + + // + // If the automatic calibration failed, return an error. + // + if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) != + SYSCTL_PIOSCSTAT_CRPASS) + { + return(0); + } + } + + // + // The calibration was successful. + // + return(1); } -#endif //***************************************************************************** // @@ -1315,7 +1977,9 @@ SysCtlDelay(unsigned long ulCount) //! The system clock divider is chosen with one of the following values: //! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... //! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16 -//! are valid on Sandstorm-class devices. +//! are valid on Sandstorm-class devices. Half-dividers, such as +//! \b SYSCTL_SYSDIV_2_5 and \b SYSCTL_SYSDIV_3_5. are available on Tempest-, +//! Firestorm-, and Blizzard-class devices. //! //! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or //! \b SYSCTL_USE_OSC. @@ -1328,10 +1992,16 @@ SysCtlDelay(unsigned long ulCount) //! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, //! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, //! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, -//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below -//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On -//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are -//! not valid. +//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, +//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. +//! Values below \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in +//! operation on Sandstorm-, Fury-, Dustdevil-, Tempest-, and Firestorm-class. +//! devices. Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in +//! operation on Blizzard-class devices. Values below \b SYSCTL_XTAL_4MHZ +//! are never valid on Blizzard-class devices. On Sandstorm- and Fury-class +//! devices, values above \b SYSCTL_XTAL_8_19MHZ are not valid. On Dustdevil-, +//! Tempest-, and Firestorm-class devices, values above \b SYSCTL_XTAL_16_3MHZ +//! are not valid. //! //! The oscillator source is chosen with one of the following values: //! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, @@ -1344,7 +2014,7 @@ SysCtlDelay(unsigned long ulCount) //! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. //! The external oscillator must be enabled in order to use an external clock //! source. Note that attempts to disable the oscillator used to clock the -//! device will be prevented by the hardware. +//! device is prevented by the hardware. //! //! To clock the system from an external source (such as an external crystal //! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the @@ -1354,10 +2024,10 @@ SysCtlDelay(unsigned long ulCount) //! crystal with one of the \b SYSCTL_XTAL_xxx values. //! //! \note If selecting the PLL as the system clock source (that is, via -//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to //! determine when the PLL has locked. If an interrupt handler for the //! system control interrupt is in place, and it responds to and clears the -//! PLL lock interrupt, this function will delay until its timeout has occurred +//! PLL lock interrupt, this function delays until its timeout has occurred //! instead of completing as soon as PLL lock is achieved. //! //! \return None. @@ -1375,7 +2045,7 @@ SysCtlClockSet(unsigned long ulConfig) if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2)) { // - // Return without changing the clocking since the requested + // Return without changing the clocking because the requested // configuration can not be achieved. // return; @@ -1383,8 +2053,8 @@ SysCtlClockSet(unsigned long ulConfig) // // Get the current value of the RCC and RCC2 registers. If using a - // Sandstorm-class device, the RCC2 register will read back as zero and the - // writes to it from within this function will be ignored. + // Sandstorm-class device, the RCC2 register reads back as zero and the + // writes to it from within this function are ignored. // ulRCC = HWREG(SYSCTL_RCC); ulRCC2 = HWREG(SYSCTL_RCC2); @@ -1447,21 +2117,36 @@ SysCtlClockSet(unsigned long ulConfig) } // - // Set the new crystal value, oscillator source, and PLL configuration. - // Since the OSCSRC2 field in RCC2 overlaps the XTAL field in RCC, the - // OSCSRC field has a special encoding within ulConfig to avoid the - // overlap. + // Set the new crystal value and oscillator source. Because the OSCSRC2 + // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a + // special encoding within ulConfig to avoid the overlap. // - ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | - SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); - ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | - SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); - ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M | - SYSCTL_RCC2_PWRDN2); - ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M | - SYSCTL_RCC2_PWRDN2); + ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); + ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M); + ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M); ulRCC2 |= (ulConfig & 0x00000008) << 3; + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. + // + SysCtlDelay(16); + + // + // Set the PLL configuration. + // + ulRCC &= ~(SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); + ulRCC |= ulConfig & (SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); + ulRCC2 &= ~(SYSCTL_RCC2_PWRDN2); + ulRCC2 |= ulConfig & SYSCTL_RCC2_PWRDN2; + // // Clear the PLL lock interrupt. // @@ -1481,15 +2166,9 @@ SysCtlClockSet(unsigned long ulConfig) HWREG(SYSCTL_RCC2) = ulRCC2; } - // - // Wait for a bit so that new crystal value and oscillator source can take - // effect. - // - SysCtlDelay(16); - // // Set the requested system divider and disable the appropriate - // oscillators. This will not get written immediately. + // oscillators. This value is not written immediately. // ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); @@ -1547,14 +2226,15 @@ SysCtlClockSet(unsigned long ulConfig) // //! Gets the processor clock rate. //! -//! This function determines the clock rate of the processor clock. This is -//! also the clock rate of all the peripheral modules (with the exception of -//! PWM, which has its own clock divider). +//! This function determines the clock rate of the processor clock, which is +//! also the clock rate of the peripheral modules (with the exception of +//! PWM, which has its own clock divider; other peripherals may have different +//! clocking, see the device data sheet for details). //! -//! \note This will not return accurate results if SysCtlClockSet() has not +//! \note This cannot return accurate results if SysCtlClockSet() has not //! been called to configure the clocking of the device, or if the device is //! directly clocked from a crystal (or a clock source) that is not one of the -//! supported crystal frequencies. In the later case, this function should be +//! supported crystal frequencies. In the latter case, this function should be //! modified to directly return the correct system clock rate. //! //! \return The processor clock rate. @@ -1564,11 +2244,12 @@ unsigned long SysCtlClockGet(void) { unsigned long ulRCC, ulRCC2, ulPLL, ulClk; + unsigned long ulPLL1; // // Read RCC and RCC2. For Sandstorm-class devices (which do not have - // RCC2), the RCC2 read will return 0, which indicates that RCC2 is - // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear). + // RCC2), the RCC2 read returns 0, indicating that RCC2 is + // disabled (because the SYSCTL_RCC2_USERCC2 bit is clear). // ulRCC = HWREG(SYSCTL_RCC); ulRCC2 = HWREG(SYSCTL_RCC2); @@ -1612,7 +2293,7 @@ SysCtlClockGet(void) { // // The internal oscillator on a rev A2 Fury-class device and a - // rev A0 Dustdevil-class device is 12 MHz +/- 30%. + // Dustdevil-class device is 12 MHz +/- 30%. // ulClk = 12000000; } @@ -1647,7 +2328,7 @@ SysCtlClockGet(void) { // // The internal oscillator on a rev A2 Fury-class device and a - // rev A0 Dustdevil-class device is 12 MHz +/- 30%. + // Dustdevil-class device is 12 MHz +/- 30%. // ulClk = 12000000 / 4; } @@ -1662,19 +2343,19 @@ SysCtlClockGet(void) } // - // The internal 30 KHz oscillator is the source clock. + // The internal 30-KHz oscillator is the source clock. // case SYSCTL_RCC_OSCSRC_30: { // - // The internal 30 KHz oscillator has an accuracy of +/- 30%. + // The internal 30-KHz oscillator has an accuracy of +/- 30%. // ulClk = 30000; break; } // - // The 4.19 MHz clock from the hibernate module is the clock source. + // The 4.194304-MHz clock from the hibernate module is the clock source. // case SYSCTL_RCC2_OSCSRC2_419: { @@ -1683,7 +2364,7 @@ SysCtlClockGet(void) } // - // The 32 KHz clock from the hibernate module is the source clock. + // The 32.768-KHz clock from the hibernate module is the source clock. // case SYSCTL_RCC2_OSCSRC2_32: { @@ -1708,57 +2389,93 @@ SysCtlClockGet(void) (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS))) { // - // Get the PLL configuration. + // See if this is a Blizzard-class device. // - ulPLL = HWREG(SYSCTL_PLLCFG); - - // - // See if this is a Sandstorm-class or Fury-class device. - // - if(CLASS_IS_SANDSTORM) + if(CLASS_IS_BLIZZARD) { // - // Compute the PLL output frequency based on its input frequency. - // The formula for a Sandstorm-class devices is - // "(xtal * (f + 2)) / (r + 2)". + // Read the two PLL frequency registers. The formula for a + // Blizzard-class device is "(xtal * m) / ((q + 1) * (n + 1))". // - ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >> - SYSCTL_PLLCFG_F_S) + 2)) / - (((ulPLL & SYSCTL_PLLCFG_R_M) >> - SYSCTL_PLLCFG_R_S) + 2)); + ulPLL = HWREG(SYSCTL_PLLFREQ0); + ulPLL1 = HWREG(SYSCTL_PLLFREQ1); + + // + // Divide the input clock by the dividers. + // + ulClk /= ((((ulPLL1 & SYSCTL_PLLFREQ1_Q_M) >> + SYSCTL_PLLFREQ1_Q_S) + 1) * + (((ulPLL1 & SYSCTL_PLLFREQ1_N_M) >> + SYSCTL_PLLFREQ1_N_S) + 1) * 2); + + // + // Multiply the clock by the multiplier, which is split into an + // integer part and a fractional part. + // + ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLFREQ0_MINT_M) >> + SYSCTL_PLLFREQ0_MINT_S)) + + ((ulClk * ((ulPLL & SYSCTL_PLLFREQ0_MFRAC_M) >> + SYSCTL_PLLFREQ0_MFRAC_S)) >> 10)); } + + // + // Older device classes used a different PLL. + // else { // - // Compute the PLL output frequency based on its input frequency. - // The formula for a Fury-class device is - // "(xtal * f) / ((r + 1) * 2)". + // Get the PLL configuration. // - ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >> - SYSCTL_PLLCFG_F_S)) / - ((((ulPLL & SYSCTL_PLLCFG_R_M) >> - SYSCTL_PLLCFG_R_S) + 1) * 2)); - } + ulPLL = HWREG(SYSCTL_PLLCFG); - // - // See if the optional output divide by 2 is being used. - // - if(ulPLL & SYSCTL_PLLCFG_OD_2) - { - ulClk /= 2; - } + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // Compute the PLL output frequency based on its input + // frequency. The formula for a Sandstorm-class devices is + // "(xtal * (f + 2)) / (r + 2)". + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 2)); + } + else + { + // + // Compute the PLL output frequency based on its input + // frequency. The formula for a Fury-class device is + // "(xtal * f) / ((r + 1) * 2)". + // + ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S)) / + ((((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 1) * 2)); + } - // - // See if the optional output divide by 4 is being used. - // - if(ulPLL & SYSCTL_PLLCFG_OD_4) - { - ulClk /= 4; + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } } // // Force the system divider to be enabled. It is always used when - // using the PLL, but in some cases it will not read as being enabled. + // using the PLL, but in some cases it does not read as being enabled. // ulRCC |= SYSCTL_RCC_USESYSDIV; } @@ -1803,6 +2520,50 @@ SysCtlClockGet(void) return(ulClk); } +//***************************************************************************** +// +//! Sets the clocking of the device while in deep-sleep mode. +//! +//! \param ulConfig is the required configuration of the device clocking while +//! in deep-sleep mode. +//! +//! This function configures the clocking of the device while in deep-sleep +//! mode. The oscillator to be used and the system clock divider are +//! configured with this function. +//! +//! The \e ulConfig parameter is the logical OR of the following values: +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ... +//! \b SYSCTL_DSLP_DIV_64. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, +//! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on +//! devices with the hibernate module, and then only when the hibernate module +//! has been enabled. +//! +//! The precision internal oscillator can be powered down in deep-sleep mode by +//! specifying \b SYSCTL_DSLP_PIOSC_PD. If it is required for operation while +//! in deep-sleep (based on other configuration settings), it will not be +//! powered down. +//! +//! \note The availability of deep-sleep clocking configuration varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleepClockSet(unsigned long ulConfig) +{ + // + // Set the deep-sleep clock configuration. + // + HWREG(SYSCTL_DSLPCLKCFG) = ulConfig; +} + //***************************************************************************** // //! Sets the PWM clock configuration. @@ -1812,8 +2573,8 @@ SysCtlClockGet(void) //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or //! \b SYSCTL_PWMDIV_64. //! -//! This function sets the rate of the clock provided to the PWM module as a -//! ratio of the processor clock. This clock is used by the PWM module to +//! This function configures the rate of the clock provided to the PWM module +//! as a ratio of the processor clock. This clock is used by the PWM module to //! generate PWM signals; its rate forms the basis for all PWM signals. //! //! \note The clocking of the PWM is dependent upon the system clock rate as @@ -1839,7 +2600,7 @@ SysCtlPWMClockSet(unsigned long ulConfig) // // Check that there is a PWM block on this part. // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM0); // // Set the PWM clock configuration into the run-mode clock configuration @@ -1856,7 +2617,7 @@ SysCtlPWMClockSet(unsigned long ulConfig) //! //! This function returns the current PWM clock configuration. //! -//! \return Returns the current PWM clock configuration; will be one of +//! \return Returns the current PWM clock configuration; is one of //! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or //! \b SYSCTL_PWMDIV_64. @@ -1868,7 +2629,7 @@ SysCtlPWMClockGet(void) // // Check that there is a PWM block on this part. // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM0); // // Return the current PWM clock configuration. Make sure that @@ -1899,10 +2660,10 @@ SysCtlPWMClockGet(void) //! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, //! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. //! -//! This function sets the rate at which the ADC samples are captured by the -//! ADC block. The sampling speed may be limited by the hardware, so the +//! This function configures the rate at which the ADC samples are captured by +//! the ADC block. The sampling speed may be limited by the hardware, so the //! sample rate may end up being slower than requested. SysCtlADCSpeedGet() -//! will return the actual speed in use. +//! returns the actual speed in use. //! //! \return None. // @@ -1924,7 +2685,7 @@ SysCtlADCSpeedSet(unsigned long ulSpeed) ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0); // - // Set the ADC speed in run, sleep, and deep-sleep mode. + // Set the ADC speed in run and sleep mode. // HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) | ulSpeed); @@ -1938,7 +2699,7 @@ SysCtlADCSpeedSet(unsigned long ulSpeed) //! //! This function gets the current sample rate of the ADC. //! -//! \return Returns the current ADC sample rate; will be one of +//! \return Returns the current ADC sample rate; is one of //! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, //! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. // @@ -1965,14 +2726,14 @@ SysCtlADCSpeedGet(void) //! verification timer should be enabled. //! //! This function allows the internal oscillator verification timer to be -//! enabled or disabled. When enabled, an interrupt will be generated if the +//! enabled or disabled. When enabled, an interrupt is generated if the //! internal oscillator ceases to operate. //! //! The internal oscillator verification timer is only available on //! Sandstorm-class devices. //! //! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the main oscillator will verify the +//! verification timer to operate as the main oscillator verifies the //! internal oscillator. //! //! \return None. @@ -2003,14 +2764,14 @@ SysCtlIOSCVerificationSet(tBoolean bEnable) //! verification timer should be enabled. //! //! This function allows the main oscillator verification timer to be enabled -//! or disabled. When enabled, an interrupt will be generated if the main +//! or disabled. When enabled, an interrupt is generated if the main //! oscillator ceases to operate. //! //! The main oscillator verification timer is only available on //! Sandstorm-class devices. //! //! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the internal oscillator will verify the +//! verification timer to operate as the internal oscillator verifies the //! main oscillator. //! //! \return None. @@ -2040,7 +2801,7 @@ SysCtlMOSCVerificationSet(tBoolean bEnable) //! should be enabled. //! //! This function allows the PLL verification timer to be enabled or disabled. -//! When enabled, an interrupt will be generated if the PLL ceases to operate. +//! When enabled, an interrupt is generated if the PLL ceases to operate. //! //! The PLL verification timer is only available on Sandstorm-class devices. //! @@ -2111,7 +2872,7 @@ SysCtlClkVerificationClear(void) //! The \e ulGPIOPeripheral argument must be only one of the following values: //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH. +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. //! //! \return None. // @@ -2135,7 +2896,7 @@ SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral) // // Enable this GPIO for AHB access. // - HWREG(SYSCTL_GPIOHSCTL) |= ulGPIOPeripheral & 0xFFFF; + HWREG(SYSCTL_GPIOHBCTL) |= ulGPIOPeripheral & 0xFFFF; } //***************************************************************************** @@ -2146,12 +2907,12 @@ SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral) //! //! This function disables the specified GPIO peripheral for access from the //! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed -//! from the legacy Advanced Peripheral Bus (AHB). +//! from the legacy Advanced Peripheral Bus (APB). //! //! The \b ulGPIOPeripheral argument must be only one of the following values: //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH. +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. //! //! \return None. // @@ -2175,14 +2936,14 @@ SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral) // // Disable this GPIO for AHB access. // - HWREG(SYSCTL_GPIOHSCTL) &= ~(ulGPIOPeripheral & 0xFFFF); + HWREG(SYSCTL_GPIOHBCTL) &= ~(ulGPIOPeripheral & 0xFFFF); } //***************************************************************************** // //! Powers up the USB PLL. //! -//! This function will enable the USB controller's PLL which is used by it's +//! This function enables the USB controller's PLL, which is used by it's //! physical layer. This call is necessary before connecting to any external //! devices. //! @@ -2202,9 +2963,9 @@ SysCtlUSBPLLEnable(void) // //! Powers down the USB PLL. //! -//! This function will disable the USB controller's PLL which is used by it's +//! This function disables the USB controller's PLL, which is used by it's //! physical layer. The USB registers are still accessible, but the physical -//! layer will no longer function. +//! layer no longer functions. //! //! \return None. // @@ -2213,7 +2974,7 @@ void SysCtlUSBPLLDisable(void) { // - // Turn of USB PLL. + // Turn off the USB PLL. // HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; } @@ -2222,20 +2983,20 @@ SysCtlUSBPLLDisable(void) // //! Sets the MCLK frequency provided to the I2S module. //! -//! \param ulInputClock is the input clock to the MCLK divider. If this is -//! zero, the value is computed from the current PLL configuration. -//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output -//! is disabled. +//! \param ulInputClock is the input clock to the MCLK divider. If this value +//! is zero, the value is computed from the current PLL configuration. +//! \param ulMClk is the desired MCLK frequency. If this value is zero, MCLK +//! output is disabled. //! -//! This function sets the dividers to provide MCLK to the I2S module. A MCLK -//! divider will be chosen that produces the MCLK frequency that is the closest +//! This function confgiures the dividers to provide MCLK to the I2S module. A +//! MCLK divider is chosen that produces the MCLK frequency that is the closest //! possible to the requested frequency, which may be above or below the //! requested frequency. //! -//! The actual MCLK frequency will be returned. It is the responsibility of -//! the application to determine if the selected MCLK is acceptable; in general -//! the human ear can not discern the frequency difference if it is within 0.3% -//! of the desired frequency (though there is a very small percentage of the +//! The actual MCLK frequency is returned. It is the responsibility of the +//! application to determine if the selected MCLK is acceptable; in general the +//! human ear can not discern the frequency difference if it is within 0.3% of +//! the desired frequency (although there is a very small percentage of the //! population that can discern lower frequency deviations). //! //! \return Returns the actual MCLK frequency. diff --git a/bsp/lm3s8962/Libraries/driverlib/sysctl.h b/bsp/lm3s8962/Libraries/driverlib/sysctl.h index cc24395ec6..a718c67b25 100644 --- a/bsp/lm3s8962/Libraries/driverlib/sysctl.h +++ b/bsp/lm3s8962/Libraries/driverlib/sysctl.h @@ -2,7 +2,7 @@ // // sysctl.h - Prototypes for the system control driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -55,7 +55,10 @@ extern "C" #endif #define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0 #define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1 +#ifndef DEPRECATED #define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#endif +#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM #define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 #define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 #define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 @@ -103,6 +106,72 @@ extern "C" #define SYSCTL_PERIPH_PLL 0x30000010 // PLL #define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor #define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2 +#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0 +#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0 +#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 +#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1 //***************************************************************************** // @@ -194,6 +263,7 @@ extern "C" // //***************************************************************************** #define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog1 reset #define SYSCTL_CAUSE_SW 0x00000010 // Software reset #define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset #define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset @@ -393,16 +463,115 @@ extern "C" #define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz #define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz #define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz #define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc #define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc #define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 #define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz #define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz #define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz -#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc. #define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator #define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPIOSCCalibrate() +// API as the ulType parameter. +// +//***************************************************************************** +#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration +#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration +#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlMOSCConfigSet() API +// as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation +#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail +#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC + //***************************************************************************** // // Prototypes for the APIs. @@ -412,6 +581,9 @@ extern unsigned long SysCtlSRAMSizeGet(void); extern unsigned long SysCtlFlashSizeGet(void); extern tBoolean SysCtlPinPresent(unsigned long ulPin); extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral); extern void SysCtlPeripheralReset(unsigned long ulPeripheral); extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); @@ -437,8 +609,11 @@ extern void SysCtlResetCauseClear(unsigned long ulCauses); extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay); extern void SysCtlDelay(unsigned long ulCount); +extern void SysCtlMOSCConfigSet(unsigned long ulConfig); +extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType); extern void SysCtlClockSet(unsigned long ulConfig); extern unsigned long SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(unsigned long ulConfig); extern void SysCtlPWMClockSet(unsigned long ulConfig); extern unsigned long SysCtlPWMClockGet(void); extern void SysCtlADCSpeedSet(unsigned long ulSpeed); diff --git a/bsp/lm3s8962/Libraries/driverlib/sysexc.c b/bsp/lm3s8962/Libraries/driverlib/sysexc.c new file mode 100644 index 0000000000..c3129e4c53 --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/sysexc.c @@ -0,0 +1,241 @@ +//***************************************************************************** +// +// sysexc.c - Routines for the System Exception Module. +// +// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysexc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_sysexc.h" +#include "inc/hw_types.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Registers an interrupt handler for the system exception interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! exception interrupt occurs. +//! +//! This function places the address of the system exception interrupt handler +//! into the interrupt vector table in SRAM. This function also enables the +//! global interrupt in the interrupt controller; specific system exception +//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_SYSEXC, pfnHandler); + + // + // Enable the system exception interrupt. + // + IntEnable(INT_SYSEXC); +} + +//***************************************************************************** +// +//! Unregisters the system exception interrupt handler. +//! +//! This function removes the system exception interrupt handler from the +//! vector table in SRAM. This function also masks off the system exception +//! interrupt in the interrupt controller so that the interrupt handler is no +//! longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntUnregister(void) +{ + // + // Disable the system exception interrupt. + // + IntDisable(INT_SYSEXC); + + // + // Unregister the system exception interrupt handler. + // + IntUnregister(INT_SYSEXC); +} + +//***************************************************************************** +// +//! Enables individual system exception interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated system exception interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSEXC_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual system exception interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated system exception interrupt sources. +//! Only sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSEXC_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current system exception interrupt status. +//! +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the system exception interrupt status. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current system exception interrupt status, enumerated +//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC, +//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and +//! \b SYSEXC_INT_FP_IDC. +// +//***************************************************************************** +unsigned long +SysExcIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSEXC_MIS)); + } + else + { + return(HWREG(SYSEXC_RIS)); + } +} + +//***************************************************************************** +// +//! Clears system exception interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified system exception interrupt sources, so +//! that they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being recognized again immediately upon +//! exit. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt +//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt +//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt +//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt +//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt +//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SysExcIntClear(unsigned long ulIntFlags) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSEXC_IC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/sysexc.h b/bsp/lm3s8962/Libraries/driverlib/sysexc.h new file mode 100644 index 0000000000..78088cb05a --- /dev/null +++ b/bsp/lm3s8962/Libraries/driverlib/sysexc.h @@ -0,0 +1,74 @@ +//***************************************************************************** +// +// sysexc.h - Prototypes for the System Exception Module routines. +// +// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSEXC_H__ +#define __SYSEXC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and +// SysExcIntClear as the ulIntFlags parameter, and returned from +// SysExcIntStatus. +// +//***************************************************************************** +#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt +#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt +#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt +#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt +#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int +#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void SysExcIntRegister(void (*pfnHandler)(void)); +extern void SysExcIntUnregister(void); +extern void SysExcIntEnable(unsigned long ulIntFlags); +extern void SysExcIntDisable(unsigned long ulIntFlags); +extern unsigned long SysExcIntStatus(tBoolean bMasked); +extern void SysExcIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSEXC_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/systick.c b/bsp/lm3s8962/Libraries/driverlib/systick.c index c2251b06aa..1fb10993c9 100644 --- a/bsp/lm3s8962/Libraries/driverlib/systick.c +++ b/bsp/lm3s8962/Libraries/driverlib/systick.c @@ -2,7 +2,7 @@ // // systick.c - Driver for the SysTick timer in NVIC. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -40,15 +40,15 @@ // //! Enables the SysTick counter. //! -//! This will start the SysTick counter. If an interrupt handler has been -//! registered, it will be called when the SysTick counter rolls over. +//! This function starts the SysTick counter. If an interrupt handler has been +//! registered, it is called when the SysTick counter rolls over. //! -//! \note Calling this function will cause the SysTick counter to (re)commence +//! \note Calling this function causes the SysTick counter to (re)commence //! counting from its current value. The counter is not automatically reloaded //! with the period as specified in a previous call to SysTickPeriodSet(). If //! an immediate reload is required, the \b NVIC_ST_CURRENT register must be -//! written to force this. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the supplied period on the next +//! written to force the reload. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the supplied period on the next //! clock. //! //! \return None. @@ -67,8 +67,8 @@ SysTickEnable(void) // //! Disables the SysTick counter. //! -//! This will stop the SysTick counter. If an interrupt handler has been -//! registered, it will no longer be called until SysTick is restarted. +//! This function stops the SysTick counter. If an interrupt handler has been +//! registered, it is not called until SysTick is restarted. //! //! \return None. // @@ -89,7 +89,8 @@ SysTickDisable(void) //! \param pfnHandler is a pointer to the function to be called when the //! SysTick interrupt occurs. //! -//! This sets the handler to be called when a SysTick interrupt occurs. +//! This function registers the handler to be called when a SysTick interrupt +//! occurs. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -115,7 +116,7 @@ SysTickIntRegister(void (*pfnHandler)(void)) // //! Unregisters the interrupt handler for the SysTick interrupt. //! -//! This function will clear the handler to be called when a SysTick interrupt +//! This function unregisters the handler to be called when a SysTick interrupt //! occurs. //! //! \sa IntRegister() for important information about registering interrupt @@ -142,12 +143,12 @@ SysTickIntUnregister(void) // //! Enables the SysTick interrupt. //! -//! This function will enable the SysTick interrupt, allowing it to be +//! This function enables the SysTick interrupt, allowing it to be //! reflected to the processor. //! -//! \note The SysTick interrupt handler does not need to clear the SysTick -//! interrupt source as this is done automatically by NVIC when the interrupt -//! handler is called. +//! \note The SysTick interrupt handler is not required to clear the SysTick +//! interrupt source because it is cleared automatically by the NVIC when the +//! interrupt handler is called. //! //! \return None. // @@ -165,7 +166,7 @@ SysTickIntEnable(void) // //! Disables the SysTick interrupt. //! -//! This function will disable the SysTick interrupt, preventing it from being +//! This function disables the SysTick interrupt, preventing it from being //! reflected to the processor. //! //! \return None. @@ -185,16 +186,16 @@ SysTickIntDisable(void) //! Sets the period of the SysTick counter. //! //! \param ulPeriod is the number of clock ticks in each period of the SysTick -//! counter; must be between 1 and 16,777,216, inclusive. +//! counter and must be between 1 and 16,777,216, inclusive. //! -//! This function sets the rate at which the SysTick counter wraps; this +//! This function sets the rate at which the SysTick counter wraps, which //! equates to the number of processor clocks between interrupts. //! //! \note Calling this function does not cause the SysTick counter to reload //! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT //! register must be written. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on -//! the next clock after the SysTick is enabled. +//! counter to 0 and causes a reload with the \e ulPeriod supplied here on +//! the next clock after SysTick is enabled. //! //! \return None. // @@ -217,7 +218,7 @@ SysTickPeriodSet(unsigned long ulPeriod) // //! Gets the period of the SysTick counter. //! -//! This function returns the rate at which the SysTick counter wraps; this +//! This function returns the rate at which the SysTick counter wraps, which //! equates to the number of processor clocks between interrupts. //! //! \return Returns the period of the SysTick counter. @@ -236,8 +237,8 @@ SysTickPeriodGet(void) // //! Gets the current value of the SysTick counter. //! -//! This function returns the current value of the SysTick counter; this will -//! be a value between the period - 1 and zero, inclusive. +//! This function returns the current value of the SysTick counter, which is +//! a value between the period - 1 and zero, inclusive. //! //! \return Returns the current value of the SysTick counter. // diff --git a/bsp/lm3s8962/Libraries/driverlib/systick.h b/bsp/lm3s8962/Libraries/driverlib/systick.h index 94251df94b..fc33f25eef 100644 --- a/bsp/lm3s8962/Libraries/driverlib/systick.h +++ b/bsp/lm3s8962/Libraries/driverlib/systick.h @@ -2,7 +2,7 @@ // // systick.h - Prototypes for the SysTick driver. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/driverlib/timer.c b/bsp/lm3s8962/Libraries/driverlib/timer.c index c103148868..ae255e058b 100644 --- a/bsp/lm3s8962/Libraries/driverlib/timer.c +++ b/bsp/lm3s8962/Libraries/driverlib/timer.c @@ -2,7 +2,7 @@ // // timer.c - Driver for the timer module. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -37,6 +37,27 @@ #include "driverlib/interrupt.h" #include "driverlib/timer.h" +//***************************************************************************** +// +// A mapping of timer base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulTimerIntMap[][2] = +{ + { TIMER0_BASE, INT_TIMER0A }, + { TIMER1_BASE, INT_TIMER1A }, + { TIMER2_BASE, INT_TIMER2A }, + { TIMER3_BASE, INT_TIMER3A }, + { TIMER4_BASE, INT_TIMER4A }, + { TIMER5_BASE, INT_TIMER5A }, + { WTIMER0_BASE, INT_WTIMER0A }, + { WTIMER1_BASE, INT_WTIMER1A }, + { WTIMER2_BASE, INT_WTIMER2A }, + { WTIMER3_BASE, INT_WTIMER3A }, + { WTIMER4_BASE, INT_WTIMER4A }, + { WTIMER5_BASE, INT_WTIMER5A }, +}; + //***************************************************************************** // //! \internal @@ -55,10 +76,57 @@ static tBoolean TimerBaseValid(unsigned long ulBase) { return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE)); + (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE) || + (ulBase == TIMER4_BASE) || (ulBase == TIMER5_BASE) || + (ulBase == WTIMER0_BASE) || (ulBase == WTIMER1_BASE) || + (ulBase == WTIMER2_BASE) || (ulBase == WTIMER3_BASE) || + (ulBase == WTIMER4_BASE) || (ulBase == WTIMER5_BASE)); } #endif +//***************************************************************************** +// +//! \internal +//! Gets the timer interrupt number. +//! +//! \param ulBase is the base address of the timer module. +//! +//! Given a timer base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a timer interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +TimerIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps timer base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulTimerIntMap) / + sizeof(g_ppulTimerIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulTimerIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulTimerIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + //***************************************************************************** // //! Enables the timer(s). @@ -67,7 +135,7 @@ TimerBaseValid(unsigned long ulBase) //! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. //! -//! This will enable operation of the timer module. The timer must be +//! This function enables operation of the timer module. The timer must be //! configured before it is enabled. //! //! \return None. @@ -97,7 +165,7 @@ TimerEnable(unsigned long ulBase, unsigned long ulTimer) //! \param ulTimer specifies the timer(s) to disable; must be one of //! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. //! -//! This will disable operation of the timer module. +//! This function disables operation of the timer module. //! //! \return None. // @@ -127,33 +195,43 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer) //! \param ulConfig is the configuration for the timer. //! //! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured, and is left in the disabled -//! state. The configuration is specified in \e ulConfig as one of the -//! following values: +//! module is disabled before being configured and is left in the disabled +//! state. There are two types of timers; a 16/32-bit variety and a 32/64-bit +//! variety. The 16/32-bit variety is comprised of two 16-bit timers that can +//! operate independently or be concatenated to form a 32-bit timer. +//! Similarly, the 32/64-bit variety is comprised of two 32-bit timers that can +//! operate independently or be concatenated to form a 64-bit timer. //! -//! - \b TIMER_CFG_32_BIT_OS - 32-bit one-shot timer -//! - \b TIMER_CFG_32_BIT_OS_UP - 32-bit one-shot timer that counts up instead -//! of down (not available on all parts) -//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer -//! - \b TIMER_CFG_32_BIT_PER_UP - 32-bit periodic timer that counts up instead -//! of down (not available on all parts) -//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer -//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers +//! The configuration is specified in \e ulConfig as one of the following +//! values: //! -//! When configured for a pair of 16-bit timers, each timer is separately +//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer +//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer +//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_RTC - Full-width real time clock timer +//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers +//! +//! When configured for a pair of half-width timers, each timer is separately //! configured. The first timer is configured by setting \e ulConfig to //! the result of a logical OR operation between one of the following values //! and \e ulConfig: //! -//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one-shot timer -//! - \b TIMER_CFG_A_ONE_SHOT_UP - 16-bit one-shot timer that counts up instead -//! of down (not available on all parts) -//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer -//! - \b TIMER_CFG_A_PERIODIC_UP - 16-bit periodic timer that counts up instead -//! of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture -//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture -//! - \b TIMER_CFG_A_PWM - 16-bit PWM output +//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer +//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer +//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture +//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts +//! up instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture +//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PWM - Half-width PWM output //! //! Similarly, the second timer is configured by setting \e ulConfig to //! the result of a logical OR operation between one of the corresponding @@ -169,13 +247,13 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig) // Check the arguments. // ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || - (ulConfig == TIMER_CFG_32_BIT_OS_UP) || - (ulConfig == TIMER_CFG_32_BIT_PER) || - (ulConfig == TIMER_CFG_32_BIT_PER_UP) || - (ulConfig == TIMER_CFG_32_RTC) || - ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); - ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || + ASSERT((ulConfig == TIMER_CFG_ONE_SHOT) || + (ulConfig == TIMER_CFG_ONE_SHOT_UP) || + (ulConfig == TIMER_CFG_PERIODIC) || + (ulConfig == TIMER_CFG_PERIODIC_UP) || + (ulConfig == TIMER_CFG_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_SPLIT_PAIR) || ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || @@ -188,7 +266,9 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig) ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) || ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) || ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); // @@ -205,8 +285,9 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig) // Set the configuration of the A and B timers. Note that the B timer // configuration is ignored by the hardware in 32-bit modes. // - HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; - HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; + HWREG(ulBase + TIMER_O_TAMR) = (ulConfig & 255) | TIMER_TAMR_TAPWMIE; + HWREG(ulBase + TIMER_O_TBMR) = + ((ulConfig >> 8) & 255) | TIMER_TBMR_TBPWMIE; } //***************************************************************************** @@ -218,9 +299,9 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig) //! \b TIMER_B, or \b TIMER_BOTH. //! \param bInvert specifies the output level. //! -//! This function sets the PWM output level for the specified timer. If the -//! \e bInvert parameter is \b true, then the timer's output will be made -//! active low; otherwise, it will be made active high. +//! This function configures the PWM output level for the specified timer. If +//! the \e bInvert parameter is \b true, then the timer's output is made active +//! low; otherwise, it is made active high. //! //! \return None. // @@ -247,15 +328,15 @@ TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, //***************************************************************************** // -//! Enables or disables the trigger output. +//! Enables or disables the ADC trigger output. //! //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. -//! \param bEnable specifies the desired trigger state. +//! \param bEnable specifies the desired ADC trigger state. //! -//! This function controls the trigger output for the specified timer. If the -//! \e bEnable parameter is \b true, then the timer's output trigger is +//! This function controls the ADC trigger output for the specified timer. If +//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is //! enabled; otherwise it is disabled. //! //! \return None. @@ -274,6 +355,7 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, // // Set the trigger output as requested. + // Set the ADC trigger output as requested. // ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; HWREG(ulBase + TIMER_O_CTL) = (bEnable ? @@ -292,8 +374,8 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, //! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or //! \b TIMER_EVENT_BOTH_EDGES. //! -//! This function sets the signal edge(s) that will trigger the timer when in -//! capture mode. +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. //! //! \return None. // @@ -312,10 +394,9 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, // // Set the event type. // - ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M); - HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & - ~(TIMER_CTL_TAEVENT_M | - TIMER_CTL_TBEVENT_M)) | ulEvent); + ulTimer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M; + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) | + (ulEvent & ulTimer)); } //***************************************************************************** @@ -328,8 +409,8 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, //! \param bStall specifies the response to a stall signal. //! //! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer will stop counting if the -//! processor enters debug mode; otherwise the timer will keep running while in +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in //! debug mode. //! //! \return None. @@ -337,7 +418,7 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, //***************************************************************************** void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall) + tBoolean bStall) { // // Check the arguments. @@ -369,7 +450,8 @@ TimerControlStall(unsigned long ulBase, unsigned long ulTimer, //! count to its timeout in order for this timer to start counting. Refer to //! the part's data sheet for a description of the trigger chain. //! -//! \note This functionality is not available on all parts. +//! \note This functionality is not available on all parts. This function +//! should not be used for Timer 0A or Wide Timer 0A. //! //! \return None. // @@ -401,7 +483,7 @@ TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer, } // - // Set the wait on trigger mode for timer A. + // Set the wait on trigger mode for timer B. // if((ulTimer & TIMER_B) != 0) { @@ -423,7 +505,7 @@ TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer, //! \param ulBase is the base address of the timer module. //! //! This function causes the timer to start counting when in RTC mode. If not -//! configured for RTC mode, this will do nothing. +//! configured for RTC mode, this function does nothing. //! //! \return None. // @@ -474,12 +556,19 @@ TimerRTCDisable(unsigned long ulBase) //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale value; must be between 0 and 255, -//! inclusive. +//! \param ulValue is the timer prescale value which must be between 0 and 255 +//! (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) for +//! 32/64-bit timers. //! -//! This function sets the value of the input clock prescaler. The prescaler -//! is only operational when in 16-bit mode and is used to extend the range of -//! the 16-bit timer modes. +//! This function configures the value of the input clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. The prescaler provides the least +//! significant bits when counting down in periodic and one-shot modes; in all +//! other modes, the prescaler provides the most significant bits. +//! +//! \note The availability of the prescaler varies with the Stellaris part and +//! timer mode in use. Please consult the datasheet for the part you are using +//! to determine whether this support is available. //! //! \return None. // @@ -522,8 +611,14 @@ TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, //! \b TIMER_B. //! //! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in 16-bit mode and is used to extend the range of -//! the 16-bit timer modes. +//! is only operational when in half-width mode and is used to extend the range +//! of the half-width timer modes. The prescaler provides the least significant +//! bits when counting down in periodic and one-shot modes; in all other modes, +//! the prescaler provides the most significant bits. +//! +//! \note The availability of the prescaler varies with the Stellaris part and +//! timer mode in use. Please consult the datasheet for the part you are using +//! to determine whether this support is available. //! //! \return The value of the timer prescaler. // @@ -552,14 +647,20 @@ TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale match value; must be between 0 and -//! 255, inclusive. +//! \param ulValue is the timer prescale match value which must be between 0 +//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 +//! (inclusive) for 32/64-bit timers. //! -//! This function sets the value of the input clock prescaler match value. -//! When in a 16-bit mode that uses the counter match and the prescaler, the -//! prescale match effectively extends the range of the counter to 24-bits. +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. //! -//! \note This functionality is not available on all parts. +//! \note The availability of the prescaler match varies with the Stellaris +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. //! //! \return None. // @@ -602,10 +703,15 @@ TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, //! \b TIMER_B. //! //! This function gets the value of the input clock prescaler match value. -//! When in a 16-bit mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the counter to 24-bits. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. //! -//! \note This functionality is not available on all parts. +//! \note The availability of the prescaler match varies with the Stellaris +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. //! //! \return The value of the timer prescale match. // @@ -634,11 +740,15 @@ TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. +//! timer is configured for full-width operation. //! \param ulValue is the load value. //! -//! This function sets the timer load value; if the timer is running then the -//! value will be immediately loaded into the timer. +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerLoadSet64() for full-width modes of 32/64-bit timers. //! //! \return None. // @@ -678,11 +788,15 @@ TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer; must be one of \b TIMER_A or //! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. +//! for full-width operation. //! //! This function gets the currently programmed interval load value for the //! specified timer. //! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerLoadGet64() for full-width modes of 32/64-bit timers. +//! //! \return Returns the load value for the timer. // //***************************************************************************** @@ -702,6 +816,79 @@ TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) HWREG(ulBase + TIMER_O_TBILR)); } +//***************************************************************************** +// +//! Sets the timer load value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! \param ullValue is the load value. +//! +//! This function configures the timer load value for a 64-bit timer; if the +//! timer is running, then the value is immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Set the timer load value. The upper 32-bits must be written before the + // lower 32-bits in order to adhere to the hardware interlocks on the + // 64-bit value. + // + HWREG(ulBase + TIMER_O_TBILR) = ullValue >> 32; + HWREG(ulBase + TIMER_O_TAILR) = ullValue & 0xffffffff; +} + +//***************************************************************************** +// +//! Gets the timer load value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function gets the currently programmed interval load value for the +//! specified 64-bit timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +unsigned long long +TimerLoadGet64(unsigned long ulBase) +{ + unsigned long ulHigh1, ulHigh2, ulLow; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Read the 64-bit load value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ulHigh1 = HWREG(ulBase + TIMER_O_TBILR); + ulLow = HWREG(ulBase + TIMER_O_TAILR); + ulHigh2 = HWREG(ulBase + TIMER_O_TBILR); + } + while(ulHigh1 != ulHigh2); + + // + // Return the load value. + // + return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow); +} + //***************************************************************************** // //! Gets the current timer value. @@ -709,10 +896,14 @@ TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer; must be one of \b TIMER_A or //! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. +//! for full-width operation. //! //! This function reads the current value of the specified timer. //! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerValueGet64() for full-width modes of 32/64-bit timers. +//! //! \return Returns the current value of the timer. // //***************************************************************************** @@ -732,6 +923,48 @@ TimerValueGet(unsigned long ulBase, unsigned long ulTimer) HWREG(ulBase + TIMER_O_TBR)); } +//***************************************************************************** +// +//! Gets the current 64-bit timer value. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +unsigned long long +TimerValueGet64(unsigned long ulBase) +{ + unsigned long ulHigh1, ulHigh2, ulLow; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Read the 64-bit timer value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ulHigh1 = HWREG(ulBase + TIMER_O_TBR); + ulLow = HWREG(ulBase + TIMER_O_TAR); + ulHigh2 = HWREG(ulBase + TIMER_O_TBR); + } + while(ulHigh1 != ulHigh2); + + // + // Return the timer value. + // + return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow); +} + //***************************************************************************** // //! Sets the timer match value. @@ -739,12 +972,18 @@ TimerValueGet(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. +//! timer is configured for full-width operation. //! \param ulValue is the match value. //! -//! This function sets the match value for a timer. This is used in capture -//! count mode to determine when to interrupt the processor and in PWM mode to -//! determine the duty cycle of the output signal. +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. On some +//! Stellaris devices, match interrupts can also be generated in periodic and +//! one-shot modes. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerMatchSet64() for full-width modes of 32/64-bit timers. //! //! \return None. // @@ -784,10 +1023,14 @@ TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer; must be one of \b TIMER_A or //! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. +//! for full-width operation. //! //! This function gets the match value for the specified timer. //! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use +//! TimerMatchGet64() for full-width modes of 32/64-bit timers. +//! //! \return Returns the match value for the timer. // //***************************************************************************** @@ -807,6 +1050,79 @@ TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) HWREG(ulBase + TIMER_O_TBMATCHR)); } +//***************************************************************************** +// +//! Sets the timer match value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! \param ullValue is the match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Set the timer match value. The upper 32-bits must be written before the + // lower 32-bits in order to adhere to the hardware interlocks on the + // 64-bit value. + // + HWREG(ulBase + TIMER_O_TBMATCHR) = ullValue >> 32; + HWREG(ulBase + TIMER_O_TAMATCHR) = ullValue & 0xffffffff; +} + +//***************************************************************************** +// +//! Gets the timer match value for a 64-bit timer. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +unsigned long long +TimerMatchGet64(unsigned long ulBase) +{ + unsigned long ulHigh1, ulHigh2, ulLow; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Read the 64-bit match value. A read of the low 32-bits is performed + // between two reads of the upper 32-bits; if the upper 32-bit values match + // then the 64-bit value is consistent. If they do not match, then the + // read is performed again until they do match (it should never execute the + // loop body more than twice). + // + do + { + ulHigh1 = HWREG(ulBase + TIMER_O_TBMATCHR); + ulLow = HWREG(ulBase + TIMER_O_TAMATCHR); + ulHigh2 = HWREG(ulBase + TIMER_O_TBMATCHR); + } + while(ulHigh1 != ulHigh2); + + // + // Return the match value. + // + return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow); +} + //***************************************************************************** // //! Registers an interrupt handler for the timer interrupt. @@ -817,10 +1133,11 @@ TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) //! \param pfnHandler is a pointer to the function to be called when the timer //! interrupt occurs. //! -//! This sets the handler to be called when a timer interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific -//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via TimerIntClear(). +//! This function registers the handler to be called when a timer interrupt +//! occurs. In addition, this function enables the global interrupt in the +//! interrupt controller; specific timer interrupts must be enabled via +//! TimerIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via TimerIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -842,9 +1159,7 @@ TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, // // Get the interrupt number for this timer module. // - ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : - ((ulBase == TIMER1_BASE) ? INT_TIMER1A : - ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A))); + ulBase = TimerIntNumberGet(ulBase); // // Register an interrupt handler for timer A if requested. @@ -887,9 +1202,9 @@ TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, //! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. //! -//! This function will clear the handler to be called when a timer interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -910,9 +1225,7 @@ TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) // // Get the interrupt number for this timer module. // - ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : - ((ulBase == TIMER1_BASE) ? INT_TIMER1A : - ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A))); + ulBase = TimerIntNumberGet(ulBase); // // Unregister the interrupt handler for timer A if requested. @@ -954,9 +1267,9 @@ TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter must be the logical OR of any combination of //! the following: @@ -993,9 +1306,9 @@ TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase is the base address of the timer module. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to TimerIntEnable(). @@ -1025,9 +1338,9 @@ TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the timer module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. //! //! \return The current interrupt status, enumerated as a bit field of //! values described in TimerIntEnable(). @@ -1057,20 +1370,20 @@ TimerIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to TimerIntEnable(). //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1089,15 +1402,76 @@ TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; } +//***************************************************************************** +// +//! Synchronizes the counters in a set of timers. +//! +//! \param ulBase is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b TIMER0_BASE). +//! \param ulTimers is the set of timers to synchronize. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! The \e ulTimers parameter is the logical OR of any of the following +//! defines: +//! +//! - \b TIMER_0A_SYNC +//! - \b TIMER_0B_SYNC +//! - \b TIMER_1A_SYNC +//! - \b TIMER_1B_SYNC +//! - \b TIMER_2A_SYNC +//! - \b TIMER_2B_SYNC +//! - \b TIMER_3A_SYNC +//! - \b TIMER_3B_SYNC +//! - \b TIMER_4A_SYNC +//! - \b TIMER_4B_SYNC +//! - \b TIMER_5A_SYNC +//! - \b TIMER_5B_SYNC +//! - \b WTIMER_0A_SYNC +//! - \b WTIMER_0B_SYNC +//! - \b WTIMER_1A_SYNC +//! - \b WTIMER_1B_SYNC +//! - \b WTIMER_2A_SYNC +//! - \b WTIMER_2B_SYNC +//! - \b WTIMER_3A_SYNC +//! - \b WTIMER_3B_SYNC +//! - \b WTIMER_4A_SYNC +//! - \b WTIMER_4B_SYNC +//! - \b WTIMER_5A_SYNC +//! - \b WTIMER_5B_SYNC +//! +//! \note This functionality is not available on all parts. +//! +//! \return None. +// +//***************************************************************************** +void +TimerSynchronize(unsigned long ulBase, unsigned long ulTimers) +{ + // + // Check the arguments. + // + ASSERT(ulBase == TIMER0_BASE); + + // + // Synchronize the specified timers. + // + HWREG(ulBase + TIMER_O_SYNC) = ulTimers; +} + //***************************************************************************** // // Puts the timer into its reset state. // // \param ulBase is the base address of the timer module. // -// The specified timer is disabled, and all its interrupts are disabled, -// cleared, and unregistered. Then the timer registers are set to their reset -// value. +// This function disables the specified timer, and all its interrupts are +// disabled, cleared, and unregistered. Then the timer registers are set to +// their reset value. // // \return None. // @@ -1127,7 +1501,7 @@ TimerQuiesce(unsigned long ulBase) HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; // - // Unregister the interrupt handler. This also disables interrupts to the + // Unregister the interrupt handler, which also disables interrupts to the // core. // TimerIntUnregister(ulBase, TIMER_BOTH); diff --git a/bsp/lm3s8962/Libraries/driverlib/timer.h b/bsp/lm3s8962/Libraries/driverlib/timer.h index eb76f42094..c27ac8d18e 100644 --- a/bsp/lm3s8962/Libraries/driverlib/timer.h +++ b/bsp/lm3s8962/Libraries/driverlib/timer.h @@ -2,7 +2,7 @@ // // timer.h - Prototypes for the timer module // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -41,26 +41,32 @@ extern "C" // Values that can be passed to TimerConfigure as the ulConfig parameter. // //***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_OS_UP 0x00000011 // 32-bit one-shot up-count timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_BIT_PER_UP 0x00000012 // 32-bit periodic up-count timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000011 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000012 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00001100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00001200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output //***************************************************************************** // @@ -97,6 +103,36 @@ extern "C" #define TIMER_B 0x0000ff00 // Timer B #define TIMER_BOTH 0x0000ffff // Timer Both +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ulTimers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A +#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B +#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A +#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B +#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A +#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B +#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A +#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B +#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A +#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B +#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A +#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B +#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A +#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B +#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A +#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B + //***************************************************************************** // // Prototypes for the APIs. @@ -129,12 +165,17 @@ extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, unsigned long ulValue); extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue); +extern unsigned long long TimerLoadGet64(unsigned long ulBase); extern unsigned long TimerValueGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long long TimerValueGet64(unsigned long ulBase); extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, unsigned long ulValue); extern unsigned long TimerMatchGet(unsigned long ulBase, unsigned long ulTimer); +extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue); +extern unsigned long long TimerMatchGet64(unsigned long ulBase); extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, void (*pfnHandler)(void)); extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); @@ -142,6 +183,7 @@ extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers); //***************************************************************************** // @@ -153,6 +195,20 @@ extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); extern void TimerQuiesce(unsigned long ulBase); #endif +//***************************************************************************** +// +// These values for TimerConfigure have been deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED +#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer +#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer +#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#endif + //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. diff --git a/bsp/lm3s8962/Libraries/driverlib/uart.c b/bsp/lm3s8962/Libraries/driverlib/uart.c index b03e4d6a06..5323cb86d5 100644 --- a/bsp/lm3s8962/Libraries/driverlib/uart.c +++ b/bsp/lm3s8962/Libraries/driverlib/uart.c @@ -2,7 +2,7 @@ // // uart.c - Driver for the UART. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -49,6 +49,23 @@ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \ 16 : 8) +//***************************************************************************** +// +// A mapping of UART base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulUARTIntMap[][2] = +{ + { UART0_BASE, INT_UART0 }, + { UART1_BASE, INT_UART1 }, + { UART2_BASE, INT_UART2 }, + { UART3_BASE, INT_UART3 }, + { UART4_BASE, INT_UART4 }, + { UART5_BASE, INT_UART5 }, + { UART6_BASE, INT_UART6 }, + { UART7_BASE, INT_UART7 }, +}; + //***************************************************************************** // //! \internal @@ -67,10 +84,55 @@ static tBoolean UARTBaseValid(unsigned long ulBase) { return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + (ulBase == UART2_BASE) || (ulBase == UART3_BASE) || + (ulBase == UART4_BASE) || (ulBase == UART5_BASE) || + (ulBase == UART6_BASE) || (ulBase == UART7_BASE)); } #endif +//***************************************************************************** +// +//! \internal +//! Gets the UART interrupt number. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Given a UART base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +UARTIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps UART base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) / + sizeof(g_ppulUARTIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulUARTIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulUARTIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + //***************************************************************************** // //! Sets the type of parity. @@ -78,11 +140,12 @@ UARTBaseValid(unsigned long ulBase) //! \param ulBase is the base address of the UART port. //! \param ulParity specifies the type of parity to use. //! -//! Sets the type of parity to use for transmitting and expect when receiving. -//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, -//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, -//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the -//! parity bit; it is always either one or zero based on the mode. +//! This function configures the type of parity to use for transmitting and +//! expect when receiving. The \e ulParity parameter must be one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two +//! parameters allow direct control of the parity bit; it is always either one +//! or zero based on the mode. //! //! \return None. // @@ -149,8 +212,8 @@ UARTParityModeGet(unsigned long ulBase) //! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, //! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. //! -//! This function sets the FIFO level at which transmit and receive interrupts -//! are generated. +//! This function configures the FIFO level at which transmit and receive +//! interrupts are generated. //! //! \return None. // @@ -193,7 +256,7 @@ UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, //! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. //! //! This function gets the FIFO level at which transmit and receive interrupts -//! are xogenerated. +//! are generated. //! //! \return None. // @@ -245,10 +308,15 @@ UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, //! select the parity mode (no parity bit, even parity bit, odd parity bit, //! parity bit always one, and parity bit always zero, respectively). //! -//! The peripheral clock will be the same as the processor clock. This will be -//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded -//! if it is constant and known (to save the code/execution overhead of a call -//! to SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet(), or it can be +//! explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet()). +//! +//! For Stellaris parts that have the ability to specify the UART baud clock +//! source (via UARTClockSourceSet()), the peripheral clock can be changed to +//! PIOSC. In this case, the peripheral clock should be specified as +//! 16,000,000 (the nominal rate of PIOSC). //! //! This function replaces the original UARTConfigSet() API and performs the //! same actions. A macro is provided in uart.h to map the original @@ -336,17 +404,22 @@ UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, //! \param pulBaud is a pointer to storage for the baud rate. //! \param pulConfig is a pointer to storage for the data format. //! -//! The baud rate and data format for the UART is determined, given an -//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! This function determines the baud rate and data format for the UART, given +//! an explicitly provided peripheral clock (hence the ExpClk suffix). The //! returned baud rate is the actual baud rate; it may not be the exact baud //! rate requested or an ``official'' baud rate. The data format returned in //! \e pulConfig is enumerated the same as the \e ulConfig parameter of //! UARTConfigSetExpClk(). //! -//! The peripheral clock will be the same as the processor clock. This will be -//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded -//! if it is constant and known (to save the code/execution overhead of a call -//! to SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet(), or it can be +//! explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet()). +//! +//! For Stellaris parts that have the ability to specify the UART baud clock +//! source (via UARTClockSourceSet()), the peripheral clock can be changed to +//! PIOSC. In this case, the peripheral clock should be specified as +//! 16,000,000 (the nominal rate of PIOSC). //! //! This function replaces the original UARTConfigGet() API and performs the //! same actions. A macro is provided in uart.h to map the original @@ -399,8 +472,8 @@ UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, //! //! \param ulBase is the base address of the UART port. //! -//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive -//! FIFOs. +//! This function sets the UARTEN, TXE, and RXE bits and enables the transmit +//! and receive FIFOs. //! //! \return None. // @@ -431,7 +504,7 @@ UARTEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of //! transmission of the current character, and flushes the transmit FIFO. //! //! \return None. @@ -495,7 +568,7 @@ UARTFIFOEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! This functions disables the transmit and receive FIFOs in the UART. +//! This function disables the transmit and receive FIFOs in the UART. //! //! \return None. // @@ -521,10 +594,18 @@ UARTFIFODisable(unsigned long ulBase) //! \param ulBase is the base address of the UART port. //! \param bLowPower indicates if SIR Low Power Mode is to be used. //! -//! Enables the SIREN control bit for IrDA mode on the UART. If the -//! \e bLowPower flag is set, then SIRLP bit will also be set. +//! This function enables the SIREN control bit for IrDA mode on the UART. If +//! the \e bLowPower flag is set, then SIRLP bit is also set. This +//! function only has an effect if the UART has not been enabled +//! by a call to UARTEnable(). The call UARTEnableSIR() must be made before +//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function +//! calls the UARTEnable() function. Another option is to call UARTDisable() +//! followed by UARTEnableSIR() and then enable the UART by calling +//! UARTEnable(). //! -//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices. +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. //! //! \return None. // @@ -556,9 +637,17 @@ UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower) //! //! \param ulBase is the base address of the UART port. //! -//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits. +//! This function clears the SIREN (IrDA) and SIRLP (Low Power) bits. This +//! function only has an effect if the UART has not been enabled by a +//! call to UARTEnable(). The call UARTEnableSIR() must be made before +//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function +//! calls the UARTEnable() function. Another option is to call UARTDisable() +//! followed by UARTEnableSIR() and then enable the UART by calling +//! UARTEnable(). //! -//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices. +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. //! //! \return None. // @@ -579,17 +668,17 @@ UARTDisableSIR(unsigned long ulBase) //***************************************************************************** // -//! Enables ISO 7816 smart card mode on the specified UART. +//! Enables ISO7816 smart card mode on the specified UART. //! //! \param ulBase is the base address of the UART port. //! -//! Enables the SMART control bit for ISO 7816 smart card mode on the UART. -//! This call also sets 8 bit word length and even parity as required by ISO -//! 7816. +//! This function enables the SMART control bit for the ISO7816 smart card mode +//! on the UART. This call also sets 8-bit word length and even parity as +//! required by ISO7816. //! -//! \note The availability of ISO 7816 smart card mode varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. //! //! \return None. // @@ -603,13 +692,12 @@ UARTSmartCardEnable(unsigned long ulBase) // Check the arguments. // ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + ASSERT(UARTBaseValid(ulBase)); // - // Set 8 bit word length, even parity, 2 stop bits (even though the STP2 - // bit is ignored when in smartcard mode, this lets the caller read back - // the actual setting in use). + // Set 8-bit word length, even parity, 2 stop bits (note that although the + // STP2 bit is ignored when in smartcard mode, this code lets the caller + // read back the actual setting in use). // ulVal = HWREG(ulBase + UART_O_LCRH); ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | @@ -625,15 +713,16 @@ UARTSmartCardEnable(unsigned long ulBase) //***************************************************************************** // -//! Disables ISO 7816 smart card mode on the specified UART. +//! Disables ISO7816 smart card mode on the specified UART. //! //! \param ulBase is the base address of the UART port. //! -//! Clears the SMART (ISO 7816 smart card) bits in the UART control register. +//! This function clears the SMART (ISO7816 smart card) bit in the UART +//! control register. //! -//! \note The availability of ISO 7816 smart card mode varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! \note The availability of ISO7816 smart card mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. //! //! \return None. // @@ -645,8 +734,7 @@ UARTSmartCardDisable(unsigned long ulBase) // Check the arguments. // ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + ASSERT(UARTBaseValid(ulBase)); // // Disable the SMART bit. @@ -662,16 +750,17 @@ UARTSmartCardDisable(unsigned long ulBase) //! \param ulControl is a bit-mapped flag indicating which modem control bits //! should be set. //! -//! Sets the states of the DTR or RTS modem handshake outputs from the UART. +//! This function configures the states of the DTR or RTS modem handshake +//! outputs from the UART. //! //! The \e ulControl parameter is the logical OR of any of the following: //! //! - \b UART_OUTPUT_DTR - The Modem Control DTR signal //! - \b UART_OUTPUT_RTS - The Modem Control RTS signal //! -//! \note The availability of hardware modem handshake signals varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! \note The availability of ISO7816 smart card mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. //! //! \return None. // @@ -704,7 +793,8 @@ UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) //! \param ulControl is a bit-mapped flag indicating which modem control bits //! should be set. //! -//! Clears the states of the DTR or RTS modem handshake outputs from the UART. +//! This function clears the states of the DTR or RTS modem handshake outputs +//! from the UART. //! //! The \e ulControl parameter is the logical OR of any of the following: //! @@ -744,15 +834,15 @@ UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) //! //! \param ulBase is the base address of the UART port. //! -//! Returns the current states of each of the two UART modem control signals, -//! DTR and RTS. +//! This function returns the current states of each of the two UART modem +//! control signals, DTR and RTS. //! //! \note The availability of hardware modem handshake signals varies with the //! Stellaris part and UART in use. Please consult the datasheet for the part //! you are using to determine whether this support is available. //! -//! \return Returns the states of the handshake output signals. This will be a -//! logical logical OR combination of values \b UART_OUTPUT_RTS and +//! \return Returns the states of the handshake output signals. This value is +//! a logical OR combination of values \b UART_OUTPUT_RTS and //! \b UART_OUTPUT_DTR where the presence of each flag indicates that the //! associated signal is asserted. // @@ -775,16 +865,16 @@ UARTModemControlGet(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! Returns the current states of each of the four UART modem status signals, -//! RI, DCD, DSR and CTS. +//! This function returns the current states of each of the four UART modem +//! status signals, RI, DCD, DSR and CTS. //! //! \note The availability of hardware modem handshake signals varies with the //! Stellaris part and UART in use. Please consult the datasheet for the part //! you are using to determine whether this support is available. //! -//! \return Returns the states of the handshake output signals. This will be a -//! logical logical OR combination of values \b UART_INPUT_RI, \b -//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the +//! \return Returns the states of the handshake output signals. This value +//! is a logical OR combination of values \b UART_INPUT_RI, +//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the //! presence of each flag indicates that the associated signal is asserted. // //***************************************************************************** @@ -806,17 +896,18 @@ UARTModemStatusGet(unsigned long ulBase) //! Sets the UART hardware flow control mode to be used. //! //! \param ulBase is the base address of the UART port. -//! \param ulMode indicates the flow control modes to be used. This is a -//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b -//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) +//! \param ulMode indicates the flow control modes to be used. This parameter +//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and +//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) //! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. //! -//! Sets the required hardware flow control modes. If \e ulMode contains -//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS -//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX, -//! the RTS output is controlled by the hardware and is asserted only when -//! there is space available in the receive FIFO. If no hardware flow control -//! is required, UART_FLOWCONTROL_NONE should be passed. +//! This function configures the required hardware flow control modes. If +//! \e ulMode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted +//! if the incoming CTS signal is asserted. If \e ulMode contains flag +//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is +//! asserted only when there is space available in the receive FIFO. If no +//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be +//! passed. //! //! \note The availability of hardware flow control varies with the Stellaris //! part and UART in use. Please consult the datasheet for the part you are @@ -832,8 +923,7 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) // Check the arguments. // ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + ASSERT(UARTBaseValid(ulBase)); ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); // @@ -850,17 +940,17 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) //! //! \param ulBase is the base address of the UART port. //! -//! Returns the current hardware flow control mode. +//! This function returns the current hardware flow control mode. //! //! \note The availability of hardware flow control varies with the Stellaris //! part and UART in use. Please consult the datasheet for the part you are //! using to determine whether this support is available. //! -//! \return Returns the current flow control mode in use. This is a +//! \return Returns the current flow control mode in use. This value is a //! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit //! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) -//! flow control is in use. If hardware flow control is disabled, \b -//! UART_FLOWCONTROL_NONE will be returned. +//! flow control is in use. If hardware flow control is disabled, +//! \b UART_FLOWCONTROL_NONE is returned. // //***************************************************************************** unsigned long @@ -870,8 +960,7 @@ UARTFlowControlGet(unsigned long ulBase) // Check the arguments. // ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + ASSERT(UARTBaseValid(ulBase)); return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)); @@ -891,9 +980,9 @@ UARTFlowControlGet(unsigned long ulBase) //! default, the transmit interrupt is asserted when the FIFO level falls past //! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this //! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the -//! transmit interrupt will only be asserted once the transmitter is completely -//! idle - the transmit FIFO is empty and all bits, including any stop bits, -//! have cleared the transmitter. +//! transmit interrupt is asserted once the transmitter is completely idle - +//! the transmit FIFO is empty and all bits, including any stop bits, have +//! cleared the transmitter. //! //! \note The availability of end-of-transmission mode varies with the //! Stellaris part in use. Please consult the datasheet for the part you are @@ -908,8 +997,7 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) // // Check the arguments. // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + ASSERT(UARTBaseValid(ulBase)); ASSERT((ulMode == UART_TXINT_MODE_EOT) || (ulMode == UART_TXINT_MODE_FIFO)); @@ -928,12 +1016,12 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) //! \param ulBase is the base address of the UART port. //! //! This function returns the current operating mode for the UART transmit -//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the -//! transmit interrupt is currently set to be asserted once the transmitter is +//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit +//! interrupt is currently configured to be asserted once the transmitter is //! completely idle - the transmit FIFO is empty and all bits, including any -//! stop bits, have cleared the transmitter. The return value will be \b -//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the -//! level of the transmit FIFO. +//! stop bits, have cleared the transmitter. The return value is +//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based +//! on the level of the transmit FIFO. //! //! \note The availability of end-of-transmission mode varies with the //! Stellaris part in use. Please consult the datasheet for the part you are @@ -948,8 +1036,7 @@ UARTTxIntModeGet(unsigned long ulBase) // // Check the arguments. // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || - (ulBase == UART2_BASE)); + ASSERT(UARTBaseValid(ulBase)); // // Return the current transmit interrupt mode. @@ -1018,7 +1105,8 @@ UARTSpaceAvail(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! Gets a character from the receive FIFO for the specified port. +//! This function gets a character from the receive FIFO for the specified +//! port. //! //! This function replaces the original UARTCharNonBlockingGet() API and //! performs the same actions. A macro is provided in uart.h to map @@ -1063,9 +1151,9 @@ UARTCharGetNonBlocking(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! Gets a character from the receive FIFO for the specified port. If there -//! are no characters available, this function waits until a character is -//! received before returning. +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. //! //! \return Returns the character read from the specified port, cast as a //! \e long. @@ -1099,9 +1187,10 @@ UARTCharGet(unsigned long ulBase) //! \param ulBase is the base address of the UART port. //! \param ucData is the character to be transmitted. //! -//! Writes the character \e ucData to the transmit FIFO for the specified port. -//! This function does not block, so if there is no space available, then a -//! \b false is returned, and the application must retry the function later. +//! This function writes the character \e ucData to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \b false is returned and the application must retry the +//! function later. //! //! This function replaces the original UARTCharNonBlockingPut() API and //! performs the same actions. A macro is provided in uart.h to map @@ -1151,9 +1240,9 @@ UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) //! \param ulBase is the base address of the UART port. //! \param ucData is the character to be transmitted. //! -//! Sends the character \e ucData to the transmit FIFO for the specified port. -//! If there is no space available in the transmit FIFO, this function waits -//! until there is space available before returning. +//! This function sends the character \e ucData to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. //! //! \return None. // @@ -1217,10 +1306,10 @@ UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) //! //! \param ulBase is the base address of the UART port. //! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \b false is returned, the transmit FIFO is -//! empty and all bits of the last transmitted character, including all stop -//! bits, have left the hardware shift register. +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, the +//! transmit FIFO is empty and all bits of the last transmitted character, +//! including all stop bits, have left the hardware shift register. //! //! \return Returns \b true if the UART is transmitting or \b false if all //! transmissions are complete. @@ -1249,8 +1338,8 @@ UARTBusy(unsigned long ulBase) //! UART interrupt occurs. //! //! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; specific UART -//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! function enables the global interrupt in the interrupt controller; specific +//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt //! handler's responsibility to clear the interrupt source. //! //! \sa IntRegister() for important information about registering interrupt @@ -1272,8 +1361,7 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) // // Determine the interrupt number based on the UART port. // - ulInt = ((ulBase == UART0_BASE) ? INT_UART0 : - ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2)); + ulInt = UARTIntNumberGet(ulBase); // // Register the interrupt handler. @@ -1293,9 +1381,9 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! \param ulBase is the base address of the UART port. //! //! This function does the actual unregistering of the interrupt handler. It -//! will clear the handler to be called when a UART interrupt occurs. This -//! will also mask off the interrupt in the interrupt controller so that the -//! interrupt handler no longer is called. +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1316,8 +1404,7 @@ UARTIntUnregister(unsigned long ulBase) // // Determine the interrupt number based on the UART port. // - ulInt = ((ulBase == UART0_BASE) ? INT_UART0 : - ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2)); + ulInt = UARTIntNumberGet(ulBase); // // Disable the interrupt. @@ -1337,12 +1424,13 @@ UARTIntUnregister(unsigned long ulBase) //! \param ulBase is the base address of the UART port. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated UART interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! +//! - \b UART_INT_9BIT - 9-bit Address Match interrupt //! - \b UART_INT_OE - Overrun Error interrupt //! - \b UART_INT_BE - Break Error interrupt //! - \b UART_INT_PE - Parity Error interrupt @@ -1379,9 +1467,9 @@ UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase is the base address of the UART port. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated UART interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to UARTIntEnable(). @@ -1411,9 +1499,9 @@ UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is \b false if the raw interrupt status is required and //! \b true if the masked interrupt status is required. //! -//! This returns the interrupt status for the specified UART. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in UARTIntEnable(). @@ -1450,19 +1538,19 @@ UARTIntStatus(unsigned long ulBase, tBoolean bMasked) //! //! The specified UART interrupt sources are cleared, so that they no longer //! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. +//! interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to UARTIntEnable(). //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -1489,7 +1577,7 @@ UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulDMAFlags is a bit mask of the DMA features to enable. //! //! The specified UART DMA features are enabled. The UART can be -//! configured to use DMA for transmit or receive, and to disable +//! configured to use DMA for transmit or receive and to disable //! receive if an error occurs. The \e ulDMAFlags parameter is the //! logical OR of any of the following values: //! @@ -1558,8 +1646,8 @@ UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) //! This function returns the current state of each of the 4 receiver error //! sources. The returned errors are equivalent to the four error bits //! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately the overrun -//! occurs rather than when a character is next read. +//! with the exception that the overrun error is set immediately when the +//! overrun occurs rather than when a character is next read. //! //! \return Returns a logical OR combination of the receiver error flags, //! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK @@ -1603,12 +1691,240 @@ UARTRxErrorClear(unsigned long ulBase) ASSERT(UARTBaseValid(ulBase)); // - // Any write to the Error Clear Register will clear all bits which are + // Any write to the Error Clear Register clears all bits which are // currently set. // HWREG(ulBase + UART_O_ECR) = 0; } +//***************************************************************************** +// +//! Sets the baud clock source for the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulSource is the baud clock source for the UART. +//! +//! This function allows the baud clock source for the UART to be selected. +//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b UART_CLOCK_PIOSC). +//! +//! Changing the baud clock source changes the baud rate generated by the +//! UART. Therefore, the baud rate should be reconfigured after any change to +//! the baud clock source. +//! +//! \note The ability to specify the UART baud clock source varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulSource == UART_CLOCK_SYSTEM) || (ulSource == UART_CLOCK_PIOSC)); + + // + // Set the UART clock source. + // + HWREG(ulBase + UART_O_CC) = ulSource; +} + +//***************************************************************************** +// +//! Gets the baud clock source for the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the baud clock source for the specified UART. The +//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or +//! the precision internal oscillator (\b UART_CLOCK_PIOSC). +//! +//! \note The ability to specify the UART baud clock source varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +UARTClockSourceGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the UART clock source. + // + return(HWREG(ulBase + UART_O_CC)); +} + +//***************************************************************************** +// +//! Enables 9-bit mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function enables the 9-bit operational mode of the UART. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable 9-bit mode. + // + HWREG(ulBase + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; +} + +//***************************************************************************** +// +//! Disables 9-bit mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function disables the 9-bit operational mode of the UART. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable 9-bit mode. + // + HWREG(ulBase + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; +} + +//***************************************************************************** +// +//! Sets the device address(es) for 9-bit mode. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucAddr is the device address. +//! \param ucMask is the device address mask. +//! +//! This function configures the device address or range of device addresses +//! that respond to requests on the 9-bit UART port. The received address is +//! masked with the mask and then compared against the given address, allowing +//! either a single address (if \b ucMask is 0xff) or a set of addresses to be +//! matched. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, + unsigned char ucMask) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the address and mask. + // + HWREG(ulBase + UART_O_9BITADDR) = ucAddr << UART_9BITADDR_ADDR_S; + HWREG(ulBase + UART_O_9BITAMASK) = ucMask << UART_9BITAMASK_MASK_S; +} + +//***************************************************************************** +// +//! Sends an address character from the specified port when operating in 9-bit +//! mode. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucAddr is the address to be transmitted. +//! +//! This function waits until all data has been sent from the specified port +//! and then sends the given address as an address byte. It then waits until +//! the address byte has been transmitted before returning. +//! +//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(), +//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive +//! data characters in 9-bit mode. +//! +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr) +{ + unsigned long ulLCRH; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until the FIFO is empty and the UART is not busy. + // + while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) + { + } + + // + // Force the address/data bit to 1 to indicate this is an address byte. + // + ulLCRH = HWREG(ulBase + UART_O_LCRH); + HWREG(ulBase + UART_O_LCRH) = ((ulLCRH & ~UART_LCRH_EPS) | UART_LCRH_SPS | + UART_LCRH_PEN); + + // + // Send the address. + // + HWREG(ulBase + UART_O_DR) = ucAddr; + + // + // Wait until the address has been sent. + // + while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) + { + } + + // + // Restore the address/data setting. + // + HWREG(ulBase + UART_O_LCRH) = ulLCRH; +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm3s8962/Libraries/driverlib/uart.h b/bsp/lm3s8962/Libraries/driverlib/uart.h index 735a83f64b..7a91483769 100644 --- a/bsp/lm3s8962/Libraries/driverlib/uart.h +++ b/bsp/lm3s8962/Libraries/driverlib/uart.h @@ -2,7 +2,7 @@ // // uart.h - Defines and Macros for the UART. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -42,6 +42,7 @@ extern "C" // as the ulIntFlags parameter, and returned from UARTIntStatus. // //***************************************************************************** +#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt #define UART_INT_OE 0x400 // Overrun Error Interrupt Mask #define UART_INT_BE 0x200 // Break Error Interrupt Mask #define UART_INT_PE 0x100 // Parity Error Interrupt Mask @@ -159,6 +160,15 @@ extern "C" #define UART_TXINT_MODE_FIFO 0x00000000 #define UART_TXINT_MODE_EOT 0x00000010 +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +#define UART_CLOCK_SYSTEM 0x00000000 +#define UART_CLOCK_PIOSC 0x00000001 + //***************************************************************************** // // API Function prototypes @@ -212,6 +222,13 @@ extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); extern unsigned long UARTFlowControlGet(unsigned long ulBase); extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); extern unsigned long UARTTxIntModeGet(unsigned long ulBase); +extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource); +extern unsigned long UARTClockSourceGet(unsigned long ulBase); +extern void UART9BitEnable(unsigned long ulBase); +extern void UART9BitDisable(unsigned long ulBase); +extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, + unsigned char ucMask); +extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr); //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/udma.c b/bsp/lm3s8962/Libraries/driverlib/udma.c index 9924d9d3dc..4124b52312 100644 --- a/bsp/lm3s8962/Libraries/driverlib/udma.c +++ b/bsp/lm3s8962/Libraries/driverlib/udma.c @@ -2,7 +2,7 @@ // // udma.c - Driver for the micro-DMA controller. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -29,6 +29,7 @@ // //***************************************************************************** +#include "inc/hw_sysctl.h" #include "inc/hw_types.h" #include "inc/hw_udma.h" #include "driverlib/debug.h" @@ -59,7 +60,7 @@ uDMAEnable(void) //! Disables the uDMA controller for use. //! //! This function disables the uDMA controller. Once disabled, the uDMA -//! controller will not operate until re-enabled with uDMAEnable(). +//! controller cannot operate until re-enabled with uDMAEnable(). //! //! \return None. // @@ -97,8 +98,9 @@ uDMAErrorStatusGet(void) // //! Clears the uDMA error interrupt. //! -//! This function clears a pending uDMA error interrupt. It should be called -//! from within the uDMA error interrupt handler to clear the interrupt. +//! This function clears a pending uDMA error interrupt. This function should +//! be called from within the uDMA error interrupt handler to clear the +//! interrupt. //! //! \return None. // @@ -116,165 +118,102 @@ uDMAErrorStatusClear(void) // //! Enables a uDMA channel for operation. //! -//! \param ulChannel is the channel number to enable. +//! \param ulChannelNum is the channel number to enable. //! //! This function enables a specific uDMA channel for use. This function must //! be used to enable a channel before it can be used to perform a uDMA //! transfer. //! -//! When a uDMA transfer is completed, the channel will be automatically -//! disabled by the uDMA controller. Therefore, this function should be called -//! prior to starting up any new transfer. -//! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! When a uDMA transfer is completed, the channel is automatically disabled by +//! the uDMA controller. Therefore, this function should be called prior to +//! starting up any new transfer. //! //! \return None. // //***************************************************************************** void -uDMAChannelEnable(unsigned long ulChannel) +uDMAChannelEnable(unsigned long ulChannelNum) { // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); // // Set the bit for this channel in the enable set register. // - HWREG(UDMA_ENASET) = 1 << ulChannel; + HWREG(UDMA_ENASET) = 1 << (ulChannelNum & 0x1f); } //***************************************************************************** // //! Disables a uDMA channel for operation. //! -//! \param ulChannel is the channel number to disable. +//! \param ulChannelNum is the channel number to disable. //! //! This function disables a specific uDMA channel. Once disabled, a channel -//! will not respond to uDMA transfer requests until re-enabled via +//! cannot respond to uDMA transfer requests until re-enabled via //! uDMAChannelEnable(). //! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit -//! //! \return None. // //***************************************************************************** void -uDMAChannelDisable(unsigned long ulChannel) +uDMAChannelDisable(unsigned long ulChannelNum) { // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); // // Set the bit for this channel in the enable clear register. // - HWREG(UDMA_ENACLR) = 1 << ulChannel; + HWREG(UDMA_ENACLR) = 1 << (ulChannelNum & 0x1f); } //***************************************************************************** // //! Checks if a uDMA channel is enabled for operation. //! -//! \param ulChannel is the channel number to check. +//! \param ulChannelNum is the channel number to check. //! //! This function checks to see if a specific uDMA channel is enabled. This -//! can be used to check the status of a transfer, since the channel will -//! be automatically disabled at the end of a transfer. -//! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! function can be used to check the status of a transfer, as the channel is +//! automatically disabled at the end of a transfer. //! //! \return Returns \b true if the channel is enabled, \b false if disabled. // //***************************************************************************** tBoolean -uDMAChannelIsEnabled(unsigned long ulChannel) +uDMAChannelIsEnabled(unsigned long ulChannelNum) { // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); // - // AND the specified channel bit with the enable register, and return the + // AND the specified channel bit with the enable register and return the // result. // - return((HWREG(UDMA_ENASET) & (1 << ulChannel)) ? true : false); + return((HWREG(UDMA_ENASET) & (1 << (ulChannelNum & 0x1f))) ? true : false); } //***************************************************************************** // //! Sets the base address for the channel control table. //! -//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! \param pControlTable is a pointer to the 1024-byte-aligned base address //! of the uDMA channel control table. //! -//! This function sets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. The table must be aligned on a 1024 byte boundary. The base -//! address must be set before any of the channel functions can be used. +//! This function configures the base address of the channel control table. +//! This table resides in system memory and holds control information for each +//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base +//! address must be configured before any of the channel functions can be used. //! //! The size of the channel control table depends on the number of uDMA -//! channels, and which transfer modes are used. Refer to the introductory +//! channels and the transfer modes that are used. Refer to the introductory //! text and the microcontroller datasheet for more information about the //! channel control table. //! @@ -312,100 +251,82 @@ void * uDMAControlBaseGet(void) { // - // Read the current value of the control base register, and return it to + // Read the current value of the control base register and return it to // the caller. // return((void *)HWREG(UDMA_CTLBASE)); } +//***************************************************************************** +// +//! Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +void * +uDMAControlAlternateBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_ALTBASE)); +} + //***************************************************************************** // //! Requests a uDMA channel to start a transfer. //! -//! \param ulChannel is the channel number on which to request a uDMA transfer. +//! \param ulChannelNum is the channel number on which to request a uDMA +//! transfer. //! //! This function allows software to request a uDMA channel to begin a -//! transfer. This could be used for performing a memory to memory transfer, -//! or if for some reason a transfer needs to be initiated by software instead -//! of the peripheral associated with that channel. -//! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! transfer. This function could be used for performing a memory-to-memory +//! transfer or if for some reason, a transfer needs to be initiated by software +//! instead of the peripheral associated with that channel. //! //! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then -//! the completion will be signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion will be signaled on the +//! the completion is signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion is signaled on the //! peripheral's interrupt. //! //! \return None. // //***************************************************************************** void -uDMAChannelRequest(unsigned long ulChannel) +uDMAChannelRequest(unsigned long ulChannelNum) { // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); // // Set the bit for this channel in the software uDMA request register. // - HWREG(UDMA_SWREQ) = 1 << ulChannel; + HWREG(UDMA_SWREQ) = 1 << (ulChannelNum & 0x1f); } //***************************************************************************** // //! Enables attributes of a uDMA channel. //! -//! \param ulChannel is the channel to configure. +//! \param ulChannelNum is the channel to configure. //! \param ulAttr is a combination of attributes for the channel. //! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! This function is used to enable attributes of a uDMA channel. //! //! The \e ulAttr parameter is the logical OR of any of the following: //! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst //! mode. //! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. +//! for this channel (it is very unlikely that this flag should be used). //! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. //! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the //! peripheral for this channel. @@ -414,21 +335,28 @@ uDMAChannelRequest(unsigned long ulChannel) // //***************************************************************************** void -uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) +uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) { // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + // // Set the useburst bit for this channel if set in ulConfig. // if(ulAttr & UDMA_ATTR_USEBURST) { - HWREG(UDMA_USEBURSTSET) = 1 << ulChannel; + HWREG(UDMA_USEBURSTSET) = 1 << ulChannelNum; } // @@ -437,7 +365,7 @@ uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) // if(ulAttr & UDMA_ATTR_ALTSELECT) { - HWREG(UDMA_ALTSET) = 1 << ulChannel; + HWREG(UDMA_ALTSET) = 1 << ulChannelNum; } // @@ -445,7 +373,7 @@ uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) // if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) { - HWREG(UDMA_PRIOSET) = 1 << ulChannel; + HWREG(UDMA_PRIOSET) = 1 << ulChannelNum; } // @@ -453,7 +381,7 @@ uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) // if(ulAttr & UDMA_ATTR_REQMASK) { - HWREG(UDMA_REQMASKSET) = 1 << ulChannel; + HWREG(UDMA_REQMASKSET) = 1 << ulChannelNum; } } @@ -461,35 +389,14 @@ uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) // //! Disables attributes of a uDMA channel. //! -//! \param ulChannel is the channel to configure. +//! \param ulChannelNum is the channel to configure. //! \param ulAttr is a combination of attributes for the channel. //! //! This function is used to disable attributes of a uDMA channel. //! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit -//! //! The \e ulAttr parameter is the logical OR of any of the following: //! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst //! mode. //! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure //! for this channel. @@ -501,21 +408,28 @@ uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) // //***************************************************************************** void -uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) +uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) { // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + // // Clear the useburst bit for this channel if set in ulConfig. // if(ulAttr & UDMA_ATTR_USEBURST) { - HWREG(UDMA_USEBURSTCLR) = 1 << ulChannel; + HWREG(UDMA_USEBURSTCLR) = 1 << ulChannelNum; } // @@ -524,7 +438,7 @@ uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) // if(ulAttr & UDMA_ATTR_ALTSELECT) { - HWREG(UDMA_ALTCLR) = 1 << ulChannel; + HWREG(UDMA_ALTCLR) = 1 << ulChannelNum; } // @@ -532,7 +446,7 @@ uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) // if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) { - HWREG(UDMA_PRIOCLR) = 1 << ulChannel; + HWREG(UDMA_PRIOCLR) = 1 << ulChannelNum; } // @@ -540,7 +454,7 @@ uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) // if(ulAttr & UDMA_ATTR_REQMASK) { - HWREG(UDMA_REQMASKCLR) = 1 << ulChannel; + HWREG(UDMA_REQMASKCLR) = 1 << ulChannelNum; } } @@ -548,35 +462,14 @@ uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) // //! Gets the enabled attributes of a uDMA channel. //! -//! \param ulChannel is the channel to configure. +//! \param ulChannelNum is the channel to configure. //! //! This function returns a combination of flags representing the attributes of //! the uDMA channel. //! -//! The \e ulChannel parameter must be one of the following: -//! -//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel -//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel -//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel -//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel -//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel -//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel -//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel -//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel -//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel -//! -//! And for microcontrollers that have a USB peripheral: -//! -//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive -//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit -//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive -//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit -//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive -//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit -//! //! \return Returns the logical OR of the attributes of the uDMA channel, which //! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst //! mode. //! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure //! for this channel. @@ -586,19 +479,26 @@ uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) // //***************************************************************************** unsigned long -uDMAChannelAttributeGet(unsigned long ulChannel) +uDMAChannelAttributeGet(unsigned long ulChannelNum) { unsigned long ulAttr = 0; // // Check the arguments. // - ASSERT(ulChannel < 32); + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; // // Check to see if useburst bit is set for this channel. // - if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannel)) + if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannelNum)) { ulAttr |= UDMA_ATTR_USEBURST; } @@ -606,7 +506,7 @@ uDMAChannelAttributeGet(unsigned long ulChannel) // // Check to see if the alternate control bit is set for this channel. // - if(HWREG(UDMA_ALTSET) & (1 << ulChannel)) + if(HWREG(UDMA_ALTSET) & (1 << ulChannelNum)) { ulAttr |= UDMA_ATTR_ALTSELECT; } @@ -614,7 +514,7 @@ uDMAChannelAttributeGet(unsigned long ulChannel) // // Check to see if the high priority bit is set for this channel. // - if(HWREG(UDMA_PRIOSET) & (1 << ulChannel)) + if(HWREG(UDMA_PRIOSET) & (1 << ulChannelNum)) { ulAttr |= UDMA_ATTR_HIGH_PRIORITY; } @@ -622,7 +522,7 @@ uDMAChannelAttributeGet(unsigned long ulChannel) // // Check to see if the request mask bit is set for this channel. // - if(HWREG(UDMA_REQMASKSET) & (1 << ulChannel)) + if(HWREG(UDMA_REQMASKSET) & (1 << ulChannelNum)) { ulAttr |= UDMA_ATTR_REQMASK; } @@ -635,20 +535,19 @@ uDMAChannelAttributeGet(unsigned long ulChannel) //***************************************************************************** // -//! Sets the control parameters for a uDMA channel. +//! Sets the control parameters for a uDMA channel control structure. //! -//! \param ulChannel is the logical OR of the uDMA channel number with -//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. //! \param ulControl is logical OR of several control values to set the control //! parameters for the channel. //! //! This function is used to set control parameters for a uDMA transfer. These -//! are typically parameters that are not changed often. +//! parameters are typically not changed often. //! -//! The \e ulChannel parameter is one of the choices documented in the -//! uDMAChannelEnable() function. It should be the logical OR of the channel -//! with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether -//! the primary or alternate data structure is used. +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. //! //! The \e ulControl parameter is the logical OR of five values: the data size, //! the source address increment, the destination address increment, the @@ -683,16 +582,24 @@ uDMAChannelAttributeGet(unsigned long ulChannel) // //***************************************************************************** void -uDMAChannelControlSet(unsigned long ulChannel, unsigned long ulControl) +uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl) { tDMAControlTable *pCtl; // // Check the arguments. // - ASSERT(ulChannel < 64); + ASSERT((ulChannelStructIndex & 0xffff) < 64); ASSERT(HWREG(UDMA_CTLBASE) != 0); + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + // // Get the base address of the control table. // @@ -702,47 +609,47 @@ uDMAChannelControlSet(unsigned long ulChannel, unsigned long ulControl) // Get the current control word value and mask off the fields to be // changed, then OR in the new settings. // - pCtl[ulChannel].ulControl = ((pCtl[ulChannel].ulControl & - ~(UDMA_CHCTL_DSTINC_M | - UDMA_CHCTL_DSTSIZE_M | - UDMA_CHCTL_SRCINC_M | - UDMA_CHCTL_SRCSIZE_M | - UDMA_CHCTL_ARBSIZE_M | - UDMA_CHCTL_NXTUSEBURST)) | - ulControl); + pCtl[ulChannelStructIndex].ulControl = + ((pCtl[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_DSTINC_M | + UDMA_CHCTL_DSTSIZE_M | + UDMA_CHCTL_SRCINC_M | + UDMA_CHCTL_SRCSIZE_M | + UDMA_CHCTL_ARBSIZE_M | + UDMA_CHCTL_NXTUSEBURST)) | + ulControl); } //***************************************************************************** // -//! Sets the transfer parameters for a uDMA channel. +//! Sets the transfer parameters for a uDMA channel control structure. //! -//! \param ulChannel is the logical or of the uDMA channel number with either -//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. //! \param ulMode is the type of uDMA transfer. //! \param pvSrcAddr is the source address for the transfer. //! \param pvDstAddr is the destination address for the transfer. //! \param ulTransferSize is the number of data items to transfer. //! -//! This function is used to set the parameters for a uDMA transfer. These are -//! typically parameters that are changed often. The function +//! This function is used to configure the parameters for a uDMA transfer. +//! These parameters are typically changed often. The function //! uDMAChannelControlSet() MUST be called at least once for this channel prior //! to calling this function. //! -//! The \e ulChannel parameter is one of the choices documented in the -//! uDMAChannelEnable() function. It should be the logical OR of the channel -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether the -//! primary or alternate data structure is used. +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. //! //! The \e ulMode parameter should be one of the following values: //! //! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode //! to this value at the end of a transfer. //! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that will always complete once -//! started even if request is removed. +//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once +//! started even if the request is removed. //! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This allows -//! use of ping-pong buffering for uDMA transfers. +//! primary and alternate control structures for the channel. This mode +//! allows use of ping-pong buffering for uDMA transfers. //! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather //! transfer. //! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather @@ -750,58 +657,65 @@ uDMAChannelControlSet(unsigned long ulChannel, unsigned long ulControl) //! //! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first //! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler will take care of this if the -//! pointers are pointing to storage of the appropriate data type. +//! according to the item size. The compiler takes care of this alignment if +//! the pointers are pointing to storage of the appropriate data type. //! //! The \e ulTransferSize parameter is the number of data items, not the number //! of bytes. //! -//! The two scatter/gather modes, memory and peripheral, are actually different +//! The two scatter-gather modes, memory and peripheral, are actually different //! depending on whether the primary or alternate control structure is -//! selected. This function will look for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and will set the -//! scatter/gather mode as appropriate for the primary or alternate control +//! selected. This function looks for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and sets the +//! scatter-gather mode as appropriate for the primary or alternate control //! structure. //! //! The channel must also be enabled using uDMAChannelEnable() after calling -//! this function. The transfer will not begin until the channel has been set -//! up and enabled. Note that the channel is automatically disabled after the -//! transfer is completed, meaning that uDMAChannelEnable() must be called -//! again after setting up the next transfer. +//! this function. The transfer does not begin until the channel has been +//! configured and enabled. Note that the channel is automatically disabled +//! after the transfer is completed, meaning that uDMAChannelEnable() must be +//! called again after setting up the next transfer. //! //! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results will be unpredictable, including the +//! that is in use or else the results are unpredictable, including the //! possibility of undesired data transfers to or from memory or peripherals. //! For BASIC and AUTO modes, it is safe to make changes when the channel is //! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For //! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the //! primary or alternate control structure only when the other is being used. -//! The uDMAChannelModeGet() function will return \b UDMA_MODE_STOP when a +//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a //! channel control structure is inactive and safe to modify. //! //! \return None. // //***************************************************************************** void -uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode, - void *pvSrcAddr, void *pvDstAddr, +uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, unsigned long ulTransferSize) { tDMAControlTable *pControlTable; unsigned long ulControl; - unsigned long ulSize; unsigned long ulInc; + unsigned long ulBufferBytes; // // Check the arguments. // - ASSERT(ulChannel < 64); + ASSERT((ulChannelStructIndex & 0xffff) < 64); ASSERT(HWREG(UDMA_CTLBASE) != 0); ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); ASSERT((unsigned long)pvSrcAddr >= 0x20000000); ASSERT((unsigned long)pvDstAddr >= 0x20000000); ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + // // Get the base address of the control table. // @@ -811,13 +725,13 @@ uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode, // Get the current control word value and mask off the mode and size // fields. // - ulControl = (pControlTable[ulChannel].ulControl & + ulControl = (pControlTable[ulChannelStructIndex].ulControl & ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); // // Adjust the mode if the alt control structure is selected. // - if(ulChannel & UDMA_ALT_SELECT) + if(ulChannelStructIndex & UDMA_ALT_SELECT) { if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) @@ -827,22 +741,11 @@ uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode, } // - // Set the transfer size and mode in the control word (but dont write the + // Set the transfer size and mode in the control word (but don't write the // control word yet as it could kick off a transfer). // ulControl |= ulMode | ((ulTransferSize - 1) << 4); - // - // Get the data item size from the control word (set previously). - // - ulSize = (ulControl & UDMA_CHCTL_DSTSIZE_M) >> 28; - - // - // Convert the transfer size to be in units of bytes. Shift (multiply) to - // get the value in bytes, based on the data item size. - // - ulTransferSize = ulTransferSize << ulSize; - // // Get the address increment value for the source, from the control word. // @@ -855,19 +758,21 @@ uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode, // if(ulInc != UDMA_SRC_INC_NONE) { - pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulTransferSize - 1); + ulInc = ulInc >> 26; + ulBufferBytes = ulTransferSize << ulInc; + pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1); } // // Load the source ending address into the control block. // - pControlTable[ulChannel].pvSrcEndAddr = pvSrcAddr; + pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr; // // Get the address increment value for the destination, from the control // word. // - ulInc = (ulControl & UDMA_CHCTL_DSTINC_M); + ulInc = ulControl & UDMA_CHCTL_DSTINC_M; // // Compute the ending destination address of the transfer. If the @@ -876,43 +781,145 @@ uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode, // if(ulInc != UDMA_DST_INC_NONE) { - pvDstAddr = (void *)((unsigned long)pvDstAddr + ulTransferSize - 1); + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer must point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ulChannelStructIndex | + UDMA_ALT_SELECT].ulSpare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ulInc = ulInc >> 30; + ulBufferBytes = ulTransferSize << ulInc; + pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1); + } } // // Load the destination ending address into the control block. // - pControlTable[ulChannel].pvDstEndAddr = pvDstAddr; + pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr; // // Write the new control word value. // - pControlTable[ulChannel].ulControl = ulControl; + pControlTable[ulChannelStructIndex].ulControl = ulControl; } //***************************************************************************** // -//! Gets the current transfer size for a uDMA channel. +//! Configures a uDMA channel for scatter-gather mode. //! -//! \param ulChannel is the logical or of the uDMA channel number with either -//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulChannelNum is the uDMA channel number. +//! \param ulTaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather +//! transfer (else it is memory scatter-gather transfer) +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list and must pass a pointer to +//! the start of the task list as the \e pvTaskList parameter. The +//! \e ulTaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. The flag \e bIsPeriphSG should be used to indicate +//! if scatter-gather should be configured for peripheral or memory +//! operation. +//! +//! \sa uDMATaskStructEntry +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, + void *pvTaskList, unsigned long ulIsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // + // Check the parameters + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ulTaskCount <= 1024); + ASSERT(ulTaskCount != 0); + + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get a handy pointer to the task list + // + pTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This address is the + // last element of the last task in the task table + // + pControlTable[ulChannelNum].pvSrcEndAddr = + &pTaskTable[ulTaskCount - 1].ulSpare; + + // + // Compute the ending address for the destination pointer. This address + // is the end of the alternate structure for this channel. + // + pControlTable[ulChannelNum].pvDstEndAddr = + &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + pControlTable[ulChannelNum].ulControl = + (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | + UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | + UDMA_CHCTL_ARBSIZE_4 | + (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | + (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : + UDMA_CHCTL_XFERMODE_MEM_SG)); +} + +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. //! //! This function is used to get the uDMA transfer size for a channel. The //! transfer size is the number of items to transfer, where the size of an item //! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items will be returned. If the transfer is -//! complete, then 0 will be returned. -//! -//! The \e ulChannel parameter is one of the choices documented in the -//! uDMAChannelEnable() function. It should be the logical OR of the channel -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether -//! the primary or alternate data structure is used. +//! then the number of remaining items is returned. If the transfer is +//! complete, then 0 is returned. //! //! \return Returns the number of items remaining to transfer. // //***************************************************************************** unsigned long -uDMAChannelSizeGet(unsigned long ulChannel) +uDMAChannelSizeGet(unsigned long ulChannelStructIndex) { tDMAControlTable *pControlTable; unsigned long ulControl; @@ -920,9 +927,16 @@ uDMAChannelSizeGet(unsigned long ulChannel) // // Check the arguments. // - ASSERT(ulChannel < 64); + ASSERT((ulChannelStructIndex & 0xffff) < 64); ASSERT(HWREG(UDMA_CTLBASE) != 0); + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + // // Get the base address of the control table. // @@ -932,8 +946,8 @@ uDMAChannelSizeGet(unsigned long ulChannel) // Get the current control word value and mask off all but the size field // and the mode field. // - ulControl = pControlTable[ulChannel].ulControl & - (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M); + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); // // If the size field and mode field are 0 then the transfer is finished @@ -959,28 +973,23 @@ uDMAChannelSizeGet(unsigned long ulChannel) //***************************************************************************** // -//! Gets the transfer mode for a uDMA channel. +//! Gets the transfer mode for a uDMA channel control structure. //! -//! \param ulChannel is the logical or of the uDMA channel number with either -//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. //! -//! This function is used to get the transfer mode for the uDMA channel. It -//! can be used to query the status of a transfer on a channel. When the -//! transfer is complete the mode will be \b UDMA_MODE_STOP. -//! -//! The \e ulChannel parameter is one of the choices documented in the -//! uDMAChannelEnable() function. It should be the logical OR of the channel -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether the -//! primary or alternate data structure is used. +//! This function is used to get the transfer mode for the uDMA channel and +//! to query the status of a transfer on a channel. When the transfer is +//! complete the mode is \b UDMA_MODE_STOP. //! //! \return Returns the transfer mode of the specified channel and control -//! structure, which will be one of the following values: \b UDMA_MODE_STOP, +//! structure, which is one of the following values: \b UDMA_MODE_STOP, //! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, //! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. // //***************************************************************************** unsigned long -uDMAChannelModeGet(unsigned long ulChannel) +uDMAChannelModeGet(unsigned long ulChannelStructIndex) { tDMAControlTable *pControlTable; unsigned long ulControl; @@ -988,9 +997,16 @@ uDMAChannelModeGet(unsigned long ulChannel) // // Check the arguments. // - ASSERT(ulChannel < 64); + ASSERT((ulChannelStructIndex & 0xffff) < 64); ASSERT(HWREG(UDMA_CTLBASE) != 0); + // + // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + // // Get the base address of the control table. // @@ -999,7 +1015,8 @@ uDMAChannelModeGet(unsigned long ulChannel) // // Get the current control word value and mask off all but the mode field. // - ulControl = pControlTable[ulChannel].ulControl & UDMA_CHCTL_XFERMODE_M; + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + UDMA_CHCTL_XFERMODE_M); // // Check if scatter/gather mode, and if so, mask off the alt bit. @@ -1020,18 +1037,17 @@ uDMAChannelModeGet(unsigned long ulChannel) // //! Selects the secondary peripheral for a set of uDMA channels. //! -//! \param ulSecPeriphs is the logical or of the uDMA channels for which to -//! use the secondary peripheral, instead of the default peripheral. +//! \param ulSecPeriphs is the logical OR of the uDMA channels for which to use +//! the secondary peripheral, instead of the default peripheral. //! -//! This function is used to select the secondary peripheral assignment for -//! a set of uDMA channels. By selecting the secondary peripheral assignment -//! for a channel, the default peripheral assignment is no longer available -//! for that channel. +//! This function is used to select the secondary peripheral assignment for a +//! set of uDMA channels. By selecting the secondary peripheral assignment for +//! a channel, the default peripheral assignment is no longer available for +//! that channel. //! -//! The parameter \e ulSecPeriphs can be the logical OR of any of the -//! following macros. If one of the macros below is in the list passed -//! to this function, then the secondary peripheral (marked as \b _SEC_) -//! will be selected. +//! The parameter \e ulSecPeriphs can be the logical OR of any of the following +//! macros. If one of the macros below is in the list passed to this function, +//! then the secondary peripheral (marked as \b _SEC_) is selected. //! //! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX //! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX @@ -1073,23 +1089,22 @@ uDMAChannelSelectSecondary(unsigned long ulSecPeriphs) // // Select the secondary peripheral for the specified channels. // - HWREG(UDMA_CHALT) |= ulSecPeriphs; + HWREG(UDMA_CHASGN) |= ulSecPeriphs; } //***************************************************************************** // //! Selects the default peripheral for a set of uDMA channels. //! -//! \param ulDefPeriphs is the logical or of the uDMA channels for which to -//! use the default peripheral, instead of the secondary peripheral. +//! \param ulDefPeriphs is the logical OR of the uDMA channels for which to use +//! the default peripheral, instead of the secondary peripheral. //! -//! This function is used to select the default peripheral assignment for -//! a set of uDMA channels. +//! This function is used to select the default peripheral assignment for a set +//! of uDMA channels. //! -//! The parameter \e ulDefPeriphs can be the logical OR of any of the -//! following macros. If one of the macros below is in the list passed -//! to this function, then the default peripheral (marked as \b _DEF_) -//! will be selected. +//! The parameter \e ulDefPeriphs can be the logical OR of any of the following +//! macros. If one of the macros below is in the list passed to this function, +//! then the default peripheral (marked as \b _DEF_) is selected. //! //! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX //! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX @@ -1131,7 +1146,7 @@ uDMAChannelSelectDefault(unsigned long ulDefPeriphs) // // Select the default peripheral for the specified channels. // - HWREG(UDMA_CHALT) &= ~ulDefPeriphs; + HWREG(UDMA_CHASGN) &= ~ulDefPeriphs; } //***************************************************************************** @@ -1142,9 +1157,9 @@ uDMAChannelSelectDefault(unsigned long ulDefPeriphs) //! \param pfnHandler is a pointer to the function to be called when the //! interrupt is activated. //! -//! This sets and enables the handler to be called when the uDMA controller -//! generates an interrupt. The \e ulIntChannel parameter should be one of the -//! following: +//! This function registers and enables the handler to be called when the uDMA +//! controller generates an interrupt. The \e ulIntChannel parameter should be +//! one of the following: //! //! - \b UDMA_INT_SW to register an interrupt handler to process interrupts //! from the uDMA software channel (UDMA_CHANNEL_SW) @@ -1154,8 +1169,8 @@ uDMAChannelSelectDefault(unsigned long ulDefPeriphs) //! \sa IntRegister() for important information about registering interrupt //! handlers. //! -//! \note The interrupt handler for uDMA is for transfer completion when the -//! channel UDMA_CHANNEL_SW is used, and for error interrupts. The +//! \note The interrupt handler for the uDMA is for transfer completion when +//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The //! interrupts for each peripheral channel are handled through the individual //! peripheral interrupt handlers. //! @@ -1188,7 +1203,7 @@ uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) //! //! \param ulIntChannel identifies which uDMA interrupt to unregister. //! -//! This function will disable and clear the handler to be called for the +//! This function disables and unregisters the handler to be called for the //! specified uDMA interrupt. The \e ulIntChannel parameter should be one of //! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function //! uDMAIntRegister(). @@ -1213,6 +1228,138 @@ uDMAIntUnregister(unsigned long ulIntChannel) IntUnregister(ulIntChannel); } +//***************************************************************************** +// +//! Gets the uDMA controller channel interrupt status. +//! +//! This function is used to get the interrupt status of the uDMA controller. +//! The returned value is a 32-bit bit mask that indicates which channels are +//! requesting an interrupt. This function can be used from within an +//! interrupt handler to determine or confirm which uDMA channel has requested +//! an interrupt. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return Returns a 32-bit mask which indicates requesting uDMA channels. +//! There is a bit for each channel and a 1 indicates that the channel +//! is requesting an interrupt. Multiple bits can be set. +// +//***************************************************************************** +unsigned long +uDMAIntStatus(void) +{ + // + // Check feature availability + // + ASSERT(!CLASS_IS_SANDSTORM); + ASSERT(!CLASS_IS_FURY); + ASSERT(!CLASS_IS_DUSTDEVIL); + ASSERT(!CLASS_IS_TEMPEST); + + // + // Return the value of the uDMA interrupt status register + // + return(HWREG(UDMA_CHIS)); +} + +//***************************************************************************** +// +//! Clears uDMA interrupt status. +//! +//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! This function clears bits in the uDMA interrupt status register according +//! to which bits are set in \e ulChanMask. There is one bit for each channel. +//! If a a bit is set in \e ulChanMask, then that corresponding channel's +//! interrupt status is cleared (if it was set). +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntClear(unsigned long ulChanMask) +{ + // + // Check feature availability + // + ASSERT(!CLASS_IS_SANDSTORM); + ASSERT(!CLASS_IS_FURY); + ASSERT(!CLASS_IS_DUSTDEVIL); + ASSERT(!CLASS_IS_TEMPEST); + + // + // Clear the requested bits in the uDMA interrupt status register + // + HWREG(UDMA_CHIS) = ulChanMask; +} + +//***************************************************************************** +// +//! Assigns a peripheral mapping for a uDMA channel. +//! +//! \param ulMapping is a macro specifying the peripheral assignment for +//! a channel. +//! +//! This function assigns a peripheral mapping to a uDMA channel. It is +//! used to select which peripheral is used for a uDMA channel. The parameter +//! \e ulMapping should be one of the macros named \b UDMA_CHn_tttt from the +//! header file \e udma.h. For example, to assign uDMA channel 0 to the +//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX. +//! +//! Please consult the Stellaris data sheet for a table showing all the +//! possible peripheral assignments for the uDMA channels for a particular +//! device. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAssign(unsigned long ulMapping) +{ + unsigned long ulMapReg; + unsigned long ulMapShift; + unsigned long ulChannelNum; + + // + // Check the parameters + // + ASSERT((ulMapping & 0xffffff00) < 0x00050000); + ASSERT(!CLASS_IS_SANDSTORM); + ASSERT(!CLASS_IS_FURY); + ASSERT(!CLASS_IS_DUSTDEVIL); + ASSERT(!CLASS_IS_TEMPEST); + ASSERT(!CLASS_IS_FIRESTORM); + + // + // Extract the channel number and map encoding value from the parameter. + // + ulChannelNum = ulMapping & 0xff; + ulMapping = ulMapping >> 16; + + // + // Find the uDMA channel mapping register and shift value to use for this + // channel + // + ulMapReg = UDMA_CHMAP0 + ((ulChannelNum / 8) * 4); + ulMapShift = (ulChannelNum % 8) * 4; + + // + // Set the channel map encoding for this channel + // + HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | + ulMapping << ulMapShift; +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm3s8962/Libraries/driverlib/udma.h b/bsp/lm3s8962/Libraries/driverlib/udma.h index 8f3fdf540e..a217ae5048 100644 --- a/bsp/lm3s8962/Libraries/driverlib/udma.h +++ b/bsp/lm3s8962/Libraries/driverlib/udma.h @@ -2,7 +2,7 @@ // // udma.h - Prototypes and macros for the uDMA controller. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -36,6 +36,13 @@ extern "C" { #endif +//***************************************************************************** +// +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + //***************************************************************************** // // A structure that defines an entry in the channel control table. These @@ -67,6 +74,104 @@ typedef struct } tDMAControlTable; +//***************************************************************************** +// +//! A helper macro for building scatter-gather task table entries. +//! +//! \param ulTransferCount is the count of items to transfer for this task. +//! \param ulItemSize is the bit size of the items to transfer for this task. +//! \param ulSrcIncrement is the bit size increment for source data. +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ulDstIncrement is the bit size increment for destination data. +//! \param pvDstAddr is the starting address of the destination data. +//! \param ulArbSize is the arbitration size to use for the transfer task. +//! \param ulMode is the transfer mode for this task. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! The \e ulTransferCount parameter is the number of items that will be +//! transferred by this task. It must be in the range 1-1024. +//! +//! The \e ulItemSize parameter is the bit size of the transfer data. It must +//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. +//! +//! The \e ulSrcIncrement parameter is the increment size for the source data. +//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, +//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. +//! +//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source +//! data. +//! +//! The \e ulDstIncrement parameter is the increment size for the destination +//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, +//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. +//! +//! The \e pvDstAddr parameter is a void pointer to the beginning of the +//! location where the data will be transferred. +//! +//! The \e ulArbSize parameter is the arbitration size for the transfer, and +//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on +//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in +//! powers of 2, from 1 to 1024. +//! +//! The \e ulMode parameter is the mode to use for this transfer task. It +//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note +//! that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +//! \verbatim +//! tDMAControlTable MyTaskList[] = +//! { +//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, +//! UDMA_SRC_INC_8, MySourceBuf, +//! UDMA_DST_INC_8, MyDestBuf, +//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), +//! uDMATaskStructEntry(Task2Count, ... ), +//! } +//! \endverbatim +//! +//! \return Nothing; this is not a function. +// +//***************************************************************************** +#define uDMATaskStructEntry(ulTransferCount, \ + ulItemSize, \ + ulSrcIncrement, \ + pvSrcAddr, \ + ulDstIncrement, \ + pvDstAddr, \ + ulArbSize, \ + ulMode) \ + { \ + (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ + ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ + ((ulSrcIncrement) >> 26)) - 1]))), \ + (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ + ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ + ((ulDstIncrement) >> 30)) - 1]))), \ + (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ + (((ulTransferCount) - 1) << 4) | \ + ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ + } + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + //***************************************************************************** // // Flags that can be passed to uDMAChannelAttributeEnable(), @@ -287,6 +392,301 @@ tDMAControlTable; #define UDMA_DEF_I2S0TX_SEC_RESERVED \ 0x20000000 +//***************************************************************************** +// +// Values that can be passed to uDMAChannelMapConfigure() to select peripheral +// mapping for each channel. The channels named RESERVED may be assigned +// to a peripheral in future parts. +// +//***************************************************************************** +// +// Channel 0 +// +#define UDMA_CH0_USB0EP1RX 0x00000000 +#define UDMA_CH0_UART2RX 0x00010000 +#define UDMA_CH0_RESERVED2 0x00020000 +#define UDMA_CH0_TIMER4A 0x00030000 +#define UDMA_CH0_RESERVED4 0x00040000 + +// +// Channel 1 +// +#define UDMA_CH1_USB0EP1TX 0x00000001 +#define UDMA_CH1_UART2TX 0x00010001 +#define UDMA_CH1_RESERVED2 0x00020001 +#define UDMA_CH1_TIMER4B 0x00030001 +#define UDMA_CH1_RESERVED4 0x00040001 + +// +// Channel 2 +// +#define UDMA_CH2_USB0EP2RX 0x00000002 +#define UDMA_CH2_TIMER3A 0x00010002 +#define UDMA_CH2_RESERVED2 0x00020002 +#define UDMA_CH2_RESERVED3 0x00030002 +#define UDMA_CH2_RESERVED4 0x00040002 + +// +// Channel 3 +// +#define UDMA_CH3_USB0EP2TX 0x00000003 +#define UDMA_CH3_TIMER3B 0x00010003 +#define UDMA_CH3_RESERVED2 0x00020003 +#define UDMA_CH3_LPC0_3 0x00030003 +#define UDMA_CH3_RESERVED4 0x00040003 + +// +// Channel 4 +// +#define UDMA_CH4_USB0EP3RX 0x00000004 +#define UDMA_CH4_TIMER2A 0x00010004 +#define UDMA_CH4_RESERVED2 0x00020004 +#define UDMA_CH4_GPIOA 0x00030004 +#define UDMA_CH4_RESERVED4 0x00040004 + +// +// Channel 5 +// +#define UDMA_CH5_USB0EP3TX 0x00000005 +#define UDMA_CH5_TIMER2B 0x00010005 +#define UDMA_CH5_RESERVED2 0x00020005 +#define UDMA_CH5_GPIOB 0x00030005 +#define UDMA_CH5_RESERVED4 0x00040005 + +// +// Channel 6 +// +#define UDMA_CH6_RESERVED0 0x00000006 +#define UDMA_CH6_TIMER2A 0x00010006 +#define UDMA_CH6_UART5RX 0x00020006 +#define UDMA_CH6_GPIOC 0x00030006 +#define UDMA_CH6_I2C0RX 0x00040006 + +// +// Channel 7 +// +#define UDMA_CH7_RESERVED0 0x00000007 +#define UDMA_CH7_TIMER2B 0x00010007 +#define UDMA_CH7_UART5TX 0x00020007 +#define UDMA_CH7_GPIOD 0x00030007 +#define UDMA_CH7_I2C0TX 0x00040007 + +// +// Channel 8 +// +#define UDMA_CH8_UART0RX 0x00000008 +#define UDMA_CH8_UART1RX 0x00010008 +#define UDMA_CH8_RESERVED2 0x00020008 +#define UDMA_CH8_TIMER5A 0x00030008 +#define UDMA_CH8_I2C1RX 0x00040008 + +// +// Channel 9 +// +#define UDMA_CH9_UART0TX 0x00000009 +#define UDMA_CH9_UART1TX 0x00010009 +#define UDMA_CH9_RESERVED2 0x00020009 +#define UDMA_CH9_TIMER5B 0x00030009 +#define UDMA_CH9_I2C1TX 0x00040009 + +// +// Channel 10 +// +#define UDMA_CH10_SSI0RX 0x0000000A +#define UDMA_CH10_SSI1RX 0x0001000A +#define UDMA_CH10_UART6RX 0x0002000A +#define UDMA_CH10_WTIMER0A 0x0003000A +#define UDMA_CH10_I2C2RX 0x0004000A + +// +// Channel 11 +// +#define UDMA_CH11_SSI0TX 0x0000000B +#define UDMA_CH11_SSI1TX 0x0001000B +#define UDMA_CH11_UART6TX 0x0002000B +#define UDMA_CH11_WTIMER0B 0x0003000B +#define UDMA_CH11_I2C2TX 0x0004000B + +// +// Channel 12 +// +#define UDMA_CH12_RESERVED0 0x0000000C +#define UDMA_CH12_UART2RX 0x0001000C +#define UDMA_CH12_SSI2RX 0x0002000C +#define UDMA_CH12_WTIMER1A 0x0003000C +#define UDMA_CH12_GPIOK 0x0004000C + +// +// Channel 13 +// +#define UDMA_CH13_RESERVED0 0x0000000D +#define UDMA_CH13_UART2TX 0x0001000D +#define UDMA_CH13_SSI2TX 0x0002000D +#define UDMA_CH13_WTIMER1B 0x0003000D +#define UDMA_CH13_GPIOL 0x0004000D + +// +// Channel 14 +// +#define UDMA_CH14_ADC0_0 0x0000000E +#define UDMA_CH14_TIMER2A 0x0001000E +#define UDMA_CH14_SSI3RX 0x0002000E +#define UDMA_CH14_GPIOE 0x0003000E +#define UDMA_CH14_GPIOM 0x0004000E + +// +// Channel 15 +// +#define UDMA_CH15_ADC0_1 0x0000000F +#define UDMA_CH15_TIMER2B 0x0001000F +#define UDMA_CH15_SSI3TX 0x0002000F +#define UDMA_CH15_GPIOF 0x0003000F +#define UDMA_CH15_GPION 0x0004000F + +// +// Channel 16 +// +#define UDMA_CH16_ADC0_2 0x00000010 +#define UDMA_CH16_RESERVED1 0x00010010 +#define UDMA_CH16_UART3RX 0x00020010 +#define UDMA_CH16_WTIMER2A 0x00030010 +#define UDMA_CH16_GPIOP 0x00040010 + +// +// Channel 17 +// +#define UDMA_CH17_ADC0_3 0x00000011 +#define UDMA_CH17_RESERVED1 0x00010011 +#define UDMA_CH17_UART3TX 0x00020011 +#define UDMA_CH17_WTIMER2B 0x00030011 +#define UDMA_CH17_RESERVED4 0x00040011 + +// +// Channel 18 +// +#define UDMA_CH18_TIMER0A 0x00000012 +#define UDMA_CH18_TIMER1A 0x00010012 +#define UDMA_CH18_UART4RX 0x00020012 +#define UDMA_CH18_GPIOB 0x00030012 +#define UDMA_CH18_I2C3RX 0x00040012 + +// +// Channel 19 +// +#define UDMA_CH19_TIMER0B 0x00000013 +#define UDMA_CH19_TIMER1B 0x00010013 +#define UDMA_CH19_UART4TX 0x00020013 +#define UDMA_CH19_GPIOG 0x00030013 +#define UDMA_CH19_I2C3TX 0x00040013 + +// +// Channel 20 +// +#define UDMA_CH20_TIMER1A 0x00000014 +#define UDMA_CH20_RESERVED1 0x00010014 +#define UDMA_CH20_UART7RX 0x00020014 +#define UDMA_CH20_GPIOH 0x00030014 +#define UDMA_CH20_I2C4RX 0x00040014 + +// +// Channel 21 +// +#define UDMA_CH21_TIMER1B 0x00000015 +#define UDMA_CH21_RESERVED1 0x00010015 +#define UDMA_CH21_UART7TX 0x00020015 +#define UDMA_CH21_GPIOJ 0x00030015 +#define UDMA_CH21_I2C4TX 0x00040015 + +// +// Channel 22 +// +#define UDMA_CH22_UART1RX 0x00000016 +#define UDMA_CH22_RESERVED1 0x00010016 +#define UDMA_CH22_RESERVED2 0x00020016 +#define UDMA_CH22_LPC0_2 0x00030016 +#define UDMA_CH22_I2C5RX 0x00040016 + +// +// Channel 23 +// +#define UDMA_CH23_UART1TX 0x00000017 +#define UDMA_CH23_RESERVED1 0x00010017 +#define UDMA_CH23_RESERVED2 0x00020017 +#define UDMA_CH23_LPC0_1 0x00030017 +#define UDMA_CH23_I2C5TX 0x00040017 + +// +// Channel 24 +// +#define UDMA_CH24_SSI1RX 0x00000018 +#define UDMA_CH24_ADC1_0 0x00010018 +#define UDMA_CH24_RESERVED2 0x00020018 +#define UDMA_CH24_WTIMER3A 0x00030018 +#define UDMA_CH24_GPIOQ 0x00040018 + +// +// Channel 25 +// +#define UDMA_CH25_SSI1TX 0x00000019 +#define UDMA_CH25_ADC1_1 0x00010019 +#define UDMA_CH25_RESERVED2 0x00020019 +#define UDMA_CH25_WTIMER3B 0x00030019 +#define UDMA_CH25_RESERVED4 0x00040019 + +// +// Channel 26 +// +#define UDMA_CH26_RESERVED0 0x0000001A +#define UDMA_CH26_ADC1_2 0x0001001A +#define UDMA_CH26_RESERVED2 0x0002001A +#define UDMA_CH26_WTIMER4A 0x0003001A +#define UDMA_CH26_RESERVED4 0x0004001A + +// +// Channel 27 +// +#define UDMA_CH27_RESERVED0 0x0000001B +#define UDMA_CH27_ADC1_3 0x0001001B +#define UDMA_CH27_RESERVED2 0x0002001B +#define UDMA_CH27_WTIMER4B 0x0003001B +#define UDMA_CH27_RESERVED4 0x0004001B + +// +// Channel 28 +// +#define UDMA_CH28_RESERVED0 0x0000001C +#define UDMA_CH28_RESERVED1 0x0001001C +#define UDMA_CH28_RESERVED2 0x0002001C +#define UDMA_CH28_WTIMER5A 0x0003001C +#define UDMA_CH28_RESERVED4 0x0004001C + +// +// Channel 29 +// +#define UDMA_CH29_RESERVED0 0x0000001D +#define UDMA_CH29_RESERVED1 0x0001001D +#define UDMA_CH29_RESERVED2 0x0002001D +#define UDMA_CH29_WTIMER5B 0x0003001D +#define UDMA_CH29_RESERVED4 0x0004001D + +// +// Channel 30 +// +#define UDMA_CH30_SW 0x0000001E +#define UDMA_CH30_RESERVED1 0x0001001E +#define UDMA_CH30_RESERVED2 0x0002001E +#define UDMA_CH30_RESERVED3 0x0003001E +#define UDMA_CH30_RESERVED4 0x0004001E + +// +// Channel 31 +// +#define UDMA_CH31_RESERVED0 0x0000001F +#define UDMA_CH31_RESERVED1 0x0001001F +#define UDMA_CH31_RESERVED2 0x0002001F +#define UDMA_CH31_LPC0_0 0x0003001F +#define UDMA_CH31_RESERVED4 0x0004001F + //***************************************************************************** // // API Function prototypes @@ -296,30 +696,37 @@ extern void uDMAEnable(void); extern void uDMADisable(void); extern unsigned long uDMAErrorStatusGet(void); extern void uDMAErrorStatusClear(void); -extern void uDMAChannelEnable(unsigned long ulChannel); -extern void uDMAChannelDisable(unsigned long ulChannel); -extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannel); +extern void uDMAChannelEnable(unsigned long ulChannelNum); +extern void uDMAChannelDisable(unsigned long ulChannelNum); +extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); extern void uDMAControlBaseSet(void *pControlTable); extern void *uDMAControlBaseGet(void); -extern void uDMAChannelRequest(unsigned long ulChannel); -extern void uDMAChannelAttributeEnable(unsigned long ulChannel, +extern void *uDMAControlAlternateBaseGet(void); +extern void uDMAChannelRequest(unsigned long ulChannelNum); +extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr); -extern void uDMAChannelAttributeDisable(unsigned long ulChannel, +extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr); -extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannel); -extern void uDMAChannelControlSet(unsigned long ulChannel, +extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); +extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, unsigned long ulControl); -extern void uDMAChannelTransferSet(unsigned long ulChannel, +extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, unsigned long ulTransferSize); -extern unsigned long uDMAChannelSizeGet(unsigned long ulChannel); -extern unsigned long uDMAChannelModeGet(unsigned long ulChannel); +extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, + unsigned ulTaskCount, void *pvTaskList, + unsigned long ulIsPeriphSG); +extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); +extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); extern void uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)); extern void uDMAIntUnregister(unsigned long ulIntChannel); extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs); extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs); +extern unsigned long uDMAIntStatus(void); +extern void uDMAIntClear(unsigned long ulChanMask); +extern void uDMAChannelAssign(unsigned long ulMapping); //***************************************************************************** // @@ -330,4 +737,4 @@ extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs); } #endif -#endif // __UDMA_H__ +#endif // __UDMA_H__ diff --git a/bsp/lm3s8962/Libraries/driverlib/usb.c b/bsp/lm3s8962/Libraries/driverlib/usb.c index 9df7d83f15..654948d014 100644 --- a/bsp/lm3s8962/Libraries/driverlib/usb.c +++ b/bsp/lm3s8962/Libraries/driverlib/usb.c @@ -2,7 +2,7 @@ // // usb.c - Driver for the USB Interface. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -85,7 +85,7 @@ // \param ucValue is the value to write to the register. // // This function is used to access the indexed registers for each endpoint. -// The only registers that are indexed are the FIFO configuration registers +// The only registers that are indexed are the FIFO configuration registers, // which are not used after configuration. // // \return None. @@ -150,7 +150,7 @@ USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint, // // This function is used internally to access the indexed registers for each // endpoint. The only registers that are indexed are the FIFO configuration -// registers which are not used after configuration. +// registers, which are not used after configuration. // // \return The value in the register requested. // @@ -215,7 +215,7 @@ USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! -//! When used in host mode, this function will put the USB bus in the suspended +//! When used in host mode, this function puts the USB bus in the suspended //! state. //! //! \note This function should only be called in host mode. @@ -246,7 +246,7 @@ USBHostSuspend(unsigned long ulBase) //! bus. //! //! When this function is called with the \e bStart parameter set to \b true, -//! this function will cause the start of a reset condition on the USB bus. +//! this function causes the start of a reset condition on the USB bus. //! The caller should then delay at least 20ms before calling this function //! again with the \e bStart parameter set to \b false. //! @@ -284,17 +284,17 @@ USBHostReset(unsigned long ulBase, tBoolean bStart) //! \param bStart specifies if the USB controller is entering or leaving the //! resume signaling state. //! -//! When in device mode this function will bring the USB controller out of the +//! When in device mode, this function brings the USB controller out of the //! suspend state. This call should first be made with the \e bStart parameter //! set to \b true to start resume signaling. The device application should //! then delay at least 10ms but not more than 15ms before calling this //! function with the \e bStart parameter set to \b false. //! -//! When in host mode this function will signal devices to leave the suspend +//! When in host mode, this function signals devices to leave the suspend //! state. This call should first be made with the \e bStart parameter set to //! \b true to start resume signaling. The host application should then delay //! at least 20ms before calling this function with the \e bStart parameter set -//! to \b false. This will cause the controller to complete the resume +//! to \b false. This action causes the controller to complete the resume //! signaling on the USB bus. //! //! \return None. @@ -327,7 +327,7 @@ USBHostResume(unsigned long ulBase, tBoolean bStart) //! //! \param ulBase specifies the USB module base address. //! -//! This function will return the current speed of the USB bus. +//! This function returns the current speed of the USB bus. //! //! \note This function should only be called in host mode. //! @@ -371,16 +371,15 @@ USBHostSpeedGet(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function will read the source of the interrupt for the USB controller. +//! This function reads the source of the interrupt for the USB controller. //! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints, -//! and general status changes. This call will return the current status for +//! and general status changes. This call returns the current status for //! all of these interrupts. The bit values returned should be compared //! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0, //! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values. //! -//! \note This call will clear the source of all of the general status -//! interrupts. -//! +//! \note This call clears the source of all of the general status interrupts. +//! //! \note WARNING: This API cannot be used on endpoint numbers greater than //! endpoint 3 so USBIntStatusControl() or USBIntStatusEndpoint() should be //! used instead. @@ -436,7 +435,7 @@ USBIntStatus(unsigned long ulBase) if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) { // - // Indicate a id detection was detected. + // Indicate an id detection was detected. // ulStatus |= USB_INT_MODE_DETECT; @@ -460,12 +459,12 @@ USBIntStatus(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which interrupts to disable. //! -//! This function will disable the USB controller from generating the +//! This function disables the USB controller from generating the //! interrupts indicated by the \e ulFlags parameter. There are three groups //! of interrupt sources, IN Endpoints, OUT Endpoints, and general status //! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT, //! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS. If -//! \b USB_INT_ALL is specified then all interrupts will be disabled. +//! \b USB_INT_ALL is specified, then all interrupts are disabled. //! //! \note WARNING: This API cannot be used on endpoint numbers greater than //! endpoint 3 so USBIntDisableControl() or USBIntDisableEndpoint() should be @@ -485,7 +484,7 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) ASSERT((ulFlags & ~(USB_INT_ALL)) == 0); // - // If any transmit interrupts were disabled then write the transmit + // If any transmit interrupts were disabled, then write the transmit // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) @@ -495,8 +494,8 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) } // - // If any receive interrupts were disabled then write the receive interrupt - // settings out to the hardware. + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) { @@ -506,8 +505,8 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) } // - // If any general interrupts were disabled then write the general interrupt - // settings out to the hardware. + // If any general interrupts were disabled, then write the general + // interrupt settings out to the hardware. // if(ulFlags & USB_INT_STATUS) { @@ -540,19 +539,19 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which interrupts to enable. //! -//! This function will enable the USB controller's ability to generate the +//! This function enables the USB controller's ability to generate the //! interrupts indicated by the \e ulFlags parameter. There are three //! groups of interrupt sources, IN Endpoints, OUT Endpoints, and //! general status changes, specified by \b USB_INT_HOST_IN, //! \b USB_INT_HOST_OUT, \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and -//! \b USB_STATUS. If \b USB_INT_ALL is specified then all interrupts will be +//! \b USB_STATUS. If \b USB_INT_ALL is specified then all interrupts are //! enabled. //! //! \note A call must be made to enable the interrupt in the main interrupt //! controller to receive interrupts. The USBIntRegister() API performs this -//! controller level interrupt enable. However if static interrupt handlers -//! are used then then a call to IntEnable() must be made in order to allow any -//! USB interrupts to occur. +//! controller-level interrupt enable. However if static interrupt handlers +//! are used, then then a call to IntEnable() must be made in order to allow +//! any USB interrupts to occur. //! //! \note WARNING: This API cannot be used on endpoint numbers greater than //! endpoint 3 so USBIntEnableControl() or USBIntEnableEndpoint() should be @@ -572,7 +571,7 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) ASSERT((ulFlags & (~USB_INT_ALL)) == 0); // - // If any transmit interrupts were enabled then write the transmit + // If any transmit interrupts were enabled, then write the transmit // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) @@ -582,8 +581,8 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) } // - // If any receive interrupts were enabled then write the receive interrupt - // settings out to the hardware. + // If any receive interrupts were enabled, then write the receive + // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) { @@ -593,8 +592,8 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) } // - // If any general interrupts were enabled then write the general interrupt - // settings out to the hardware. + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. // if(ulFlags & USB_INT_STATUS) { @@ -622,12 +621,12 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) //***************************************************************************** // -//! Disable control interrupts on a given USB controller. +//! Disables control interrupts on a given USB controller. //! //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which control interrupts to disable. //! -//! This function will disable the control interrupts for the USB controller +//! This function disables the control interrupts for the USB controller //! specified by the \e ulBase parameter. The \e ulFlags parameter specifies //! which control interrupts to disable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTCTRL_* and @@ -673,12 +672,12 @@ USBIntDisableControl(unsigned long ulBase, unsigned long ulFlags) //***************************************************************************** // -//! Enable control interrupts on a given USB controller. +//! Enables control interrupts on a given USB controller. //! //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which control interrupts to enable. //! -//! This function will enable the control interrupts for the USB controller +//! This function enables the control interrupts for the USB controller //! specified by the \e ulBase parameter. The \e ulFlags parameter specifies //! which control interrupts to enable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTCTRL_* and @@ -697,8 +696,8 @@ USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) ASSERT((ulFlags & (~USB_INTCTRL_ALL)) == 0); // - // If any general interrupts were enabled then write the general interrupt - // settings out to the hardware. + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. // if(ulFlags & USB_INTCTRL_STATUS) { @@ -728,17 +727,17 @@ USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) //! //! \param ulBase specifies the USB module base address. //! -//! This function will read control interrupt status for a USB controller. -//! This call will return the current status for control interrupts only, the -//! endpoint interrupt status is retrieved by calling USBIntStatusEndpoint(). -//! The bit values returned should be compared against the \b USB_INTCTRL_* +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned should be compared against the \b USB_INTCTRL_* //! values. //! //! The following are the meanings of all \b USB_INCTRL_ flags and the modes //! for which they are valid. These values apply to any calls to -//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableConrol(). +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). //! Some of these flags are only valid in the following modes as indicated in -//! the parenthesis: Host, Device, and OTG. +//! the parentheses: Host, Device, and OTG. //! //! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. //! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). @@ -758,9 +757,8 @@ USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) //! (OTG Only) //! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected. (Host Only) //! -//! \note This call will clear the source of all of the control status -//! interrupts. -//! +//! \note This call clears the source of all of the control status interrupts. +//! //! \return Returns the status of the control interrupts for a USB controller. // //***************************************************************************** @@ -799,7 +797,7 @@ USBIntStatusControl(unsigned long ulBase) if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) { // - // Indicate a id detection was detected. + // Indicate an id detection. // ulStatus |= USB_INTCTRL_MODE_DETECT; @@ -817,14 +815,14 @@ USBIntStatusControl(unsigned long ulBase) //***************************************************************************** // -//! Disable endpoint interrupts on a given USB controller. +//! Disables endpoint interrupts on a given USB controller. //! //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which endpoint interrupts to disable. //! -//! This function will disable endpoint interrupts for the USB controller -//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies -//! which endpoint interrupts to disable. The flags passed in the \e ulFlags +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ulBase parameter. The \e ulFlags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTEP_* and not //! any other \b USB_INT flags. //! @@ -840,14 +838,14 @@ USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags) ASSERT(ulBase == USB0_BASE); // - // If any transmit interrupts were disabled then write the transmit + // If any transmit interrupts were disabled, then write the transmit // interrupt settings out to the hardware. // HWREGH(ulBase + USB_O_TXIE) &= ~(ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); // - // If any receive interrupts were disabled then write the receive interrupt + // If any receive interrupts were disabled, then write the receive interrupt // settings out to the hardware. // HWREGH(ulBase + USB_O_RXIE) &= @@ -857,14 +855,14 @@ USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags) //***************************************************************************** // -//! Enable endpoint interrupts on a given USB controller. +//! Enables endpoint interrupts on a given USB controller. //! //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which endpoint interrupts to enable. //! -//! This function will enable endpoint interrupts for the USB controller -//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies -//! which endpoint interrupts to enable. The flags passed in the \e ulFlags +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ulBase parameter. The \e ulFlags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTEP_* and not //! any other \b USB_INT flags. //! @@ -899,15 +897,15 @@ USBIntEnableEndpoint(unsigned long ulBase, unsigned long ulFlags) //! //! \param ulBase specifies the USB module base address. //! -//! This function will read endpoint interrupt status for a USB controller. -//! This call will return the current status for endpoint interrupts only, the -//! control interrupt status is retrieved by calling USBIntStatusControl(). -//! The bit values returned should be compared against the \b USB_INTEP_* -//! values. These are grouped into classes for \b USB_INTEP_HOST_* and +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned should be compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and //! \b USB_INTEP_DEV_* values to handle both host and device modes with all //! endpoints. //! -//! \note This call will clear the source of all of the endpoint interrupts. +//! \note This call clears the source of all of the endpoint interrupts. //! //! \return Returns the status of the endpoint interrupts for a USB controller. // @@ -943,11 +941,11 @@ USBIntStatusEndpoint(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when a USB //! interrupt occurs. //! -//! This sets the handler to be called when a USB interrupt occurs. This will -//! also enable the global USB interrupt in the interrupt controller. The -//! specific desired USB interrupts must be enabled via a separate call to +//! This function registers the handler to be called when a USB interrupt +//! occurs and enables the global USB interrupt in the interrupt controller. +//! The specific desired USB interrupts must be enabled via a separate call to //! USBIntEnable(). It is the interrupt handler's responsibility to clear the -//! interrupt sources via a calls to USBIntStatusControl() and +//! interrupt sources via calls to USBIntStatusControl() and //! USBIntStatusEndpoint(). //! //! \sa IntRegister() for important information about registering interrupt @@ -981,8 +979,8 @@ USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) //! //! \param ulBase specifies the USB module base address. //! -//! This function unregister the interrupt handler. This function will also -//! disable the USB interrupt in the interrupt controller. +//! This function unregisters the interrupt handler. This function also +//! disables the USB interrupt in the interrupt controller. //! //! \sa IntRegister() for important information about registering or //! unregistering interrupt handlers. @@ -998,15 +996,15 @@ USBIntUnregister(unsigned long ulBase) // ASSERT(ulBase == USB0_BASE); + // + // Disable the USB interrupt. + // + IntDisable(INT_USB0); + // // Unregister the interrupt handler. // IntUnregister(INT_USB0); - - // - // Disable the CAN interrupt. - // - IntDisable(INT_USB0); } //***************************************************************************** @@ -1016,11 +1014,10 @@ USBIntUnregister(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will return the status of a given endpoint. If any of these -//! status bits need to be cleared, then these these values must be cleared by -//! calling the USBDevEndpointStatusClear() or USBHostEndpointStatusClear() -//! functions. -//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions should be called. +//! //! The following are the status flags for host mode: //! //! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. @@ -1121,9 +1118,9 @@ USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint) //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. -//! \param ulFlags are the status bits that will be cleared. +//! \param ulFlags are the status bits that should be cleared. //! -//! This function will clear the status of any bits that are passed in the +//! This function clears the status of any bits that are passed in the //! \e ulFlags parameter. The \e ulFlags parameter can take the value returned //! from the USBEndpointStatus() call. //! @@ -1170,9 +1167,9 @@ USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. -//! \param ulFlags are the status bits that will be cleared. +//! \param ulFlags are the status bits that should be cleared. //! -//! This function will clear the status of any bits that are passed in the +//! This function clears the status of any bits that are passed in the //! \e ulFlags parameter. The \e ulFlags parameter can take the value returned //! from the USBEndpointStatus() call. //! @@ -1199,8 +1196,8 @@ USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); // - // If this is endpoint 0 then the bits have different meaning and map into - // the TX memory location. + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. // if(ulEndpoint == USB_EP_0) { @@ -1259,9 +1256,9 @@ USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, //! //! This function is used to force the state of the data toggle in host mode. //! If the value passed in the \e bDataToggle parameter is \b false, then the -//! data toggle will be set to the DATA0 state, and if it is \b true it will be -//! set to the DATA1 state. The \e ulFlags parameter can be \b USB_EP_HOST_IN -//! or \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ulFlags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The //! \e ulFlags parameter is ignored for endpoint zero. //! //! \note This function should only be called in host mode. @@ -1352,13 +1349,13 @@ USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint, //***************************************************************************** // -//! Sets the Data toggle on an endpoint to zero. +//! Sets the data toggle on an endpoint to zero. //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint specifies the endpoint to reset the data toggle. //! \param ulFlags specifies whether to access the IN or OUT endpoint. //! -//! This function will cause the controller to clear the data toggle for an +//! This function causes the USB controller to clear the data toggle for an //! endpoint. This call is not valid for endpoint zero and can be made with //! host or device controllers. //! @@ -1408,11 +1405,11 @@ USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint specifies the endpoint to stall. //! \param ulFlags specifies whether to stall the IN or OUT endpoint. //! -//! This function will cause to endpoint number passed in to go into a stall -//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall -//! will be issued on the IN portion of this endpoint. If the \e ulFlags -//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT -//! portion of this endpoint. +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN, then the stall +//! is issued on the IN portion of this endpoint. If the \e ulFlags parameter +//! is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion of this +//! endpoint. //! //! \note This function should only be called in device mode. //! @@ -1475,11 +1472,11 @@ USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies whether to remove the stall condition from the IN //! or the OUT portion of this endpoint. //! -//! This function will cause the endpoint number passed in to exit the stall -//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall -//! will be cleared on the IN portion of this endpoint. If the \e ulFlags -//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT -//! portion of this endpoint. +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN, then the stall +//! is cleared on the IN portion of this endpoint. If the \e ulFlags parameter +//! is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT portion of this +//! endpoint. //! //! \note This function should only be called in device mode. //! @@ -1550,8 +1547,8 @@ USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! -//! This function will cause the soft connect feature of the USB controller to -//! be enabled. Call USBDisconnect() to remove the USB device from the bus. +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. //! //! \note This function should only be called in device mode. //! @@ -1578,7 +1575,7 @@ USBDevConnect(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function will cause the soft connect feature of the USB controller to +//! This function causes the soft connect feature of the USB controller to //! remove the device from the USB bus. A call to USBDevConnect() is needed to //! reconnect to the bus. //! @@ -1608,8 +1605,8 @@ USBDevDisconnect(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulAddress is the address to use for a device. //! -//! This function will set the device address on the USB bus. This address was -//! likely received via a SET ADDRESS command from the host controller. +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. //! //! \note This function should only be called in device mode. //! @@ -1636,7 +1633,7 @@ USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress) //! //! \param ulBase specifies the USB module base address. //! -//! This function will return the current device address. This address was set +//! This function returns the current device address. This address was set //! by a call to USBDevAddrSet(). //! //! \note This function should only be called in device mode. @@ -1666,18 +1663,19 @@ USBDevAddrGet(unsigned long ulBase) //! \param ulEndpoint is the endpoint to access. //! \param ulMaxPayload is the maximum payload for this endpoint. //! \param ulNAKPollInterval is the either the NAK timeout limit or the polling -//! interval depending on the type of endpoint. +//! interval, depending on the type of endpoint. //! \param ulTargetEndpoint is the endpoint that the host endpoint is //! targeting. //! \param ulFlags are used to configure other endpoint settings. //! -//! This function will set the basic configuration for the transmit or receive +//! This function sets the basic configuration for the transmit or receive //! portion of an endpoint in host mode. The \e ulFlags parameter determines //! some of the configuration while the other parameters provide the rest. The //! \e ulFlags parameter determines whether this is an IN endpoint -//! (USB_EP_HOST_IN or USB_EP_DEV_IN) or an OUT endpoint (USB_EP_HOST_OUT or -//! USB_EP_DEV_OUT), whether this is a Full speed endpoint (USB_EP_SPEED_FULL) -//! or a Low speed endpoint (USB_EP_SPEED_LOW). +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). //! //! The \b USB_EP_MODE_ flags control the type of the endpoint. //! - \b USB_EP_MODE_CTRL is a control endpoint. @@ -1693,18 +1691,18 @@ USBDevAddrGet(unsigned long ulBase) //! isochronous or interrupt endpoint, this value is the polling interval for //! this endpoint. //! -//! For interrupt endpoints the polling interval is simply the number of +//! For interrupt endpoints, the polling interval is simply the number of //! frames between polling an interrupt endpoint. For isochronous endpoints //! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1) //! frames. When used as a NAK timeout, the \e ulNAKPollInterval value //! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out. //! There are two special time out values that can be specified when setting -//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT which is the -//! maximum value that can be passed in this variable. The other is -//! \b DISABLE_NAK_LIMIT which indicates that there should be no limit on the +//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is +//! the maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT, which indicates that there should be no limit on the //! number of NAKs. //! -//! The \b USB_EP_DMA_MODE_ flags enables the type of DMA used to access the +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the //! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA //! controller is configured and how it is being used. See the ``Using USB //! with the uDMA Controller'' section for more information on DMA @@ -1712,15 +1710,15 @@ USBDevAddrGet(unsigned long ulBase) //! //! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit //! is specified to cause the transmission of data on the USB bus to start -//! as soon as the number of bytes specified by \e ulMaxPayload have been +//! as soon as the number of bytes specified by \e ulMaxPayload has been //! written into the OUT FIFO for this endpoint. //! //! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST //! bit can be specified to trigger the request for more data once the FIFO has //! been drained enough to fit \e ulMaxPayload bytes. The \b USB_EP_AUTO_CLEAR //! bit can be used to clear the data packet ready flag automatically once the -//! data has been read from the FIFO. If this is not used, this flag must be -//! manually cleared via a call to USBDevEndpointStatusClear() or +//! data has been read from the FIFO. If this option is not used, this flag +//! must be manually cleared via a call to USBDevEndpointStatusClear() or //! USBHostEndpointStatusClear(). //! //! \note This function should only be called in host mode. @@ -1764,7 +1762,7 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, // // Set the transfer type information. // - HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) = + HWREGB(ulBase + USB_O_TYPE0) = ((ulFlags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : USB_TYPE0_SPEED_LOW); } @@ -1942,9 +1940,9 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulMaxPacketSize is the maximum packet size for this endpoint. //! \param ulFlags are used to configure other endpoint settings. //! -//! This function will set the basic configuration for an endpoint in device -//! mode. Endpoint zero does not have a dynamic configuration, so this -//! function should not be called for endpoint zero. The \e ulFlags parameter +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! should not be called for endpoint zero. The \e ulFlags parameter //! determines some of the configuration while the other parameters provide the //! rest. //! @@ -1955,7 +1953,7 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! - \b USB_EP_MODE_BULK is a bulk endpoint. //! - \b USB_EP_MODE_INT is an interrupt endpoint. //! -//! The \b USB_EP_DMA_MODE_ flags determines the type of DMA access to the +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the //! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA //! controller is configured and how it is being used. See the ``Using USB //! with the uDMA Controller'' section for more information on DMA @@ -1964,7 +1962,7 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be //! specified to cause the automatic transmission of data on the USB bus as //! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for -//! this endpoint. This is commonly used with DMA as no interaction is +//! this endpoint. This option is commonly used with DMA as no interaction is //! required to start the transmission of data. //! //! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is @@ -1972,9 +1970,9 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! drained enough to receive \e ulMaxPacketSize more bytes of data. Also for //! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data //! packet ready flag automatically once the data has been read from the FIFO. -//! If this is not used, this flag must be manually cleared via a call to -//! USBDevEndpointStatusClear(). Both of these settings can be used to remove -//! the need for extra calls when using the controller in DMA mode. +//! If this option is not used, this flag must be manually cleared via a call +//! to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. //! //! \note This function should only be called in device mode. //! @@ -2119,14 +2117,14 @@ USBDevEndpointConfigSet(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. -//! \param pulMaxPacketSize is a pointer which will be written with the -//! maximum packet size for this endpoint. -//! \param pulFlags is a pointer which will be written with the current -//! endpoint settings. On entry to the function, this pointer must contain -//! either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or -//! OUT endpoint is to be queried. +//! \param pulMaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pulFlags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. //! -//! This function will return the basic configuration for an endpoint in device +//! This function returns the basic configuration for an endpoint in device //! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are //! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to //! USBDevEndpointConfigSet() for this endpoint. @@ -2216,9 +2214,9 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, // // The hardware doesn't differentiate between bulk, interrupt // and control mode for the endpoint so we just set something - // that isn't isochronous. This ensures that anyone modifying - // the returned flags in preparation for a call to - // USBDevEndpointConfigSet will not see an unexpected mode change. + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. // If they decode the returned mode, however, they may be in for // a surprise. // @@ -2281,9 +2279,9 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, // // The hardware doesn't differentiate between bulk, interrupt // and control mode for the endpoint so we just set something - // that isn't isochronous. This ensures that anyone modifying - // the returned flags in preparation for a call to - // USBDevEndpointConfigSet will not see an unexpected mode change. + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. // If they decode the returned mode, however, they may be in for // a surprise. // @@ -2299,27 +2297,28 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! \param ulFIFOAddress is the starting address for the FIFO. -//! \param ulFIFOSize is the size of the FIFO in bytes. +//! \param ulFIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. //! \param ulFlags specifies what information to set in the FIFO configuration. //! -//! This function will set the starting FIFO RAM address and size of the FIFO +//! This function configures the starting FIFO RAM address and size of the FIFO //! for a given endpoint. Endpoint zero does not have a dynamically -//! configurable FIFO so this function should not be called for endpoint zero. +//! configurable FIFO, so this function should not be called for endpoint zero. //! The \e ulFIFOSize parameter should be one of the values in the -//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering +//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering, //! it should use the values with the \b _DB at the end of the value. For -//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16 -//! byte double buffered FIFO. If a double buffered FIFO is used, then the -//! actual size of the FIFO will be twice the size indicated by the -//! \e ulFIFOSize parameter. This means that the \b USB_FIFO_SZ_16_DB value -//! will use 32 bytes of the USB controller's FIFO memory. +//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16- +//! byte, double-buffered FIFO. If a double-buffered FIFO is used, then the +//! actual size of the FIFO is twice the size indicated by the \e ulFIFOSize +//! parameter. For example, the \b USB_FIFO_SZ_16_DB value uses 32 bytes of +//! the USB controller's FIFO memory. //! //! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly //! indicates the starting address in the USB controller's FIFO RAM. For //! example, a value of 64 indicates that the FIFO should start 64 bytes into //! the USB controller's FIFO memory. The \e ulFlags value specifies whether //! the endpoint's OUT or IN FIFO should be configured. If in host mode, use -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use //! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. //! //! \return None. @@ -2373,16 +2372,17 @@ USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! \param pulFIFOAddress is the starting address for the FIFO. -//! \param pulFIFOSize is the size of the FIFO in bytes. +//! \param pulFIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. //! \param ulFlags specifies what information to retrieve from the FIFO //! configuration. //! -//! This function will return the starting address and size of the FIFO for a +//! This function returns the starting address and size of the FIFO for a //! given endpoint. Endpoint zero does not have a dynamically configurable -//! FIFO so this function should not be called for endpoint zero. The +//! FIFO, so this function should not be called for endpoint zero. The //! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should //! be read. If in host mode, the \e ulFlags parameter should be -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode the +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the //! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or //! \b USB_EP_DEV_IN. //! @@ -2444,9 +2444,9 @@ USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies which direction and what mode to use when enabling //! DMA. //! -//! This function will enable DMA on a given endpoint and set the mode according -//! to the values in the \e ulFlags parameter. The \e ulFlags parameter should -//! have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ulFlags parameter. The \e ulFlags +//! parameter should have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. //! //! \return None. // @@ -2461,7 +2461,7 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, if(ulFlags & USB_EP_DEV_IN) { // - // Enable DMA on the transmit end point. + // Enable DMA on the transmit endpoint. // HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |= USB_TXCSRH1_DMAEN; @@ -2469,7 +2469,7 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, else { // - // Enable DMA on the receive end point. + // Enable DMA on the receive endpoint. // HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |= USB_RXCSRH1_DMAEN; @@ -2484,9 +2484,9 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulFlags specifies which direction to disable. //! -//! This function will disable DMA on a given end point to allow non-DMA -//! USB transactions to generate interrupts normally. The ulFlags should be -//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT all other bits are ignored. +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The ulFlags should be +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. //! //! \return None. // @@ -2496,7 +2496,7 @@ USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint, unsigned long ulFlags) { // - // If this was a request to disable DMA on the IN portion of the end point + // If this was a request to disable DMA on the IN portion of the endpoint // then handle it. // if(ulFlags & USB_EP_DEV_IN) @@ -2524,13 +2524,13 @@ USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will return the number of bytes of data currently available -//! in the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to //! calling USBEndpointDataGet() to determine the size of buffer required to //! hold the newly-received packet. //! -//! \return This call will return the number of bytes available in a given -//! endpoint FIFO. +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. // //***************************************************************************** unsigned long @@ -2587,18 +2587,18 @@ USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint) //! \param pucData is a pointer to the data area used to return the data from //! the FIFO. //! \param pulSize is initially the size of the buffer passed into this call -//! via the \e pucData parameter. It will be set to the amount of data -//! returned in the buffer. +//! via the \e pucData parameter. It is set to the amount of data returned in +//! the buffer. //! -//! This function will return the data from the FIFO for the given endpoint. +//! This function returns the data from the FIFO for the given endpoint. //! The \e pulSize parameter should indicate the size of the buffer passed in -//! the \e pulData parameter. The data in the \e pulSize parameter will be -//! changed to match the amount of data returned in the \e pucData parameter. -//! If a zero byte packet was received this call will not return a error but -//! will instead just return a zero in the \e pulSize parameter. The only -//! error case occurs when there is no data packet available. +//! the \e pulData parameter. The data in the \e pulSize parameter is changed +//! to match the amount of data returned in the \e pucData parameter. If a +//! zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pulSize parameter. The only error +//! case occurs when there is no data packet available. //! -//! \return This call will return 0, or -1 if no packet was received. +//! \return This call returns 0, or -1 if no packet was received. // //***************************************************************************** long @@ -2693,7 +2693,7 @@ USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. -//! \param bIsLastPacket indicates if this is the last packet. +//! \param bIsLastPacket indicates if this packet is the last one. //! //! This function acknowledges that the data was read from the endpoint's FIFO. //! The \e bIsLastPacket parameter is set to a \b true value if this is the @@ -2802,13 +2802,13 @@ USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint) //! data to put into the FIFO. //! \param ulSize is the amount of data to put into the FIFO. //! -//! This function will put the data from the \e pucData parameter into the FIFO -//! for this endpoint. If a packet is already pending for transmission then -//! this call will not put any of the data into the FIFO and will return -1. -//! Care should be taken to not write more data than can fit into the FIFO -//! allocated by the call to USBFIFOConfig(). +//! This function puts the data from the \e pucData parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! should be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). //! -//! \return This call will return 0 on success, or -1 to indicate that the FIFO +//! \return This call returns 0 on success, or -1 to indicate that the FIFO //! is in use and cannot be written. // //***************************************************************************** @@ -2879,21 +2879,21 @@ USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulTransType is set to indicate what type of data is being sent. //! -//! This function will start the transfer of data from the FIFO for a given -//! endpoint. This is necessary if the \b USB_EP_AUTO_SET bit was not enabled -//! for the endpoint. Setting the \e ulTransType parameter will allow the -//! appropriate signaling on the USB bus for the type of transaction being +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function should be called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ulTransType parameter allows +//! the appropriate signaling on the USB bus for the type of transaction being //! requested. The \e ulTransType parameter should be one of the following: //! -//! - USB_TRANS_OUT for OUT transaction on any endpoint in host mode. -//! - USB_TRANS_IN for IN transaction on any endpoint in device mode. -//! - USB_TRANS_IN_LAST for the last IN transactions on endpoint zero in a +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a //! sequence of IN transactions. -//! - USB_TRANS_SETUP for setup transactions on endpoint zero. -//! - USB_TRANS_STATUS for status results on endpoint zero. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. //! -//! \return This call will return 0 on success, or -1 if a transmission is -//! already in progress. +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. // //***************************************************************************** long @@ -2903,7 +2903,7 @@ USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, unsigned long ulTxPktRdy; // - // CHeck the arguments. + // Check the arguments. // ASSERT(ulBase == USB0_BASE); ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || @@ -2954,7 +2954,7 @@ USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulFlags specifies if the IN or OUT endpoint should be accessed. //! -//! This function will force the controller to flush out the data in the FIFO. +//! This function forces the USB controller to flush out the data in the FIFO. //! The function can be called with either host or device controllers and //! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT, //! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. @@ -3041,11 +3041,12 @@ USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will schedule a request for an IN transaction. When the USB -//! device being communicated with responds the data, the data can be retrieved -//! by calling USBEndpointDataGet() or via a DMA transfer. +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. //! -//! \note This function should only be called in host mode. +//! \note This function should only be called in host mode and only for IN +//! endpoints. //! //! \return None. // @@ -3086,17 +3087,72 @@ USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint) HWREGB(ulBase + ulRegister) = USB_RXCSRL1_REQPKT; } +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is +//! still pending. This function should be used to safely disable any +//! scheduled IN transactions if the endpoint specified by \e ulEndpoint +//! is reconfigured for communications with other devices. +//! +//! \note This function should only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ulBase + ulRegister) &= ~USB_RXCSRL1_REQPKT; +} + //***************************************************************************** // //! Issues a request for a status IN transaction on endpoint zero. //! //! \param ulBase specifies the USB module base address. //! -//! This function is used to cause a request for an status IN transaction from +//! This function is used to cause a request for a status IN transaction from //! a device on endpoint zero. This function can only be used with endpoint //! zero as that is the only control endpoint that supports this ability. This -//! is used to complete the last phase of a control transaction to a device and -//! an interrupt will be signaled when the status packet has been received. +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. //! //! \return None. // @@ -3126,10 +3182,10 @@ USBHostRequestStatus(unsigned long ulBase) //! endpoint. //! \param ulFlags determines if this is an IN or an OUT endpoint. //! -//! This function will set the functional address for a device that is using +//! This function configures the functional address for a device that is using //! this endpoint for communication. This \e ulAddr parameter is the address -//! of the target device that this endpoint will be used to communicate with. -//! The \e ulFlags parameter indicates if the IN or OUT endpoint should be set. +//! of the target device that this endpoint is communicating with. The +//! \e ulFlags parameter indicates if the IN or OUT endpoint should be set. //! //! \note This function should only be called in host mode. //! @@ -3227,16 +3283,21 @@ USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //***************************************************************************** // -//! Set the hub address for the device that is connected to an endpoint. +//! Sets the hub address for the device that is connected to an endpoint. //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. -//! \param ulAddr is the hub address for the device using this endpoint. +//! \param ulAddr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 8 through 15 with the +//! port number in bits 0 through 6. //! \param ulFlags determines if this is an IN or an OUT endpoint. //! -//! This function will set the hub address for a device that is using this +//! This function configures the hub address for a device that is using this //! endpoint for communication. The \e ulFlags parameter determines if the -//! device address for the IN or the OUT endpoint is set by this call. +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of \b +//! USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with \b +//! USB_EP_SPEED_LOW. //! //! \note This function should only be called in host mode. //! @@ -3266,28 +3327,45 @@ USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, if(ulFlags & USB_EP_HOST_OUT) { // - // Set the hub transmit address for this endpoint. + // Set the hub transmit address and port number for this endpoint. // - HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr; + HWREGH(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr; } else { // - // Set the hub receive address for this endpoint. + // Set the hub receive address and port number for this endpoint. // - HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr; + HWREGH(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ulEndpoint == USB_EP_0) + { + if(ulFlags & USB_EP_SPEED_FULL) + { + HWREGB(ulBase + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ulBase + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } } } //***************************************************************************** // -//! Get the current device hub address for this endpoint. +//! Gets the current device hub address for this endpoint. //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! \param ulFlags determines if this is an IN or an OUT endpoint. //! -//! This function will return the current hub address that an endpoint is using +//! This function returns the current hub address that an endpoint is using //! to communicate with a device. The \e ulFlags parameter determines if the //! device address for the IN or OUT endpoint is returned. //! @@ -3341,12 +3419,11 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies the configuration of the power fault. //! //! This function controls how the USB controller uses its external power -//! control pins(USBnPFTL and USBnEPEN). The flags specify the power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power //! fault level sensitivity, the power fault action, and the power enable level //! and source. //! -//! One of the following can be selected as the power fault level -//! sensitivity: +//! One of the following can be selected as the power fault level sensitivity: //! //! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin //! being driven low. @@ -3357,7 +3434,7 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! //! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault //! detected. -//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBnEPEN pin on a +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a //! power fault. //! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a //! power fault. @@ -3366,21 +3443,23 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! //! One of the following can be selected as the power enable level and source: //! -//! - \b USB_HOST_PWREN_MAN_LOW - USBEPEN is driven low by the USB controller +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller //! when USBHostPwrEnable() is called. -//! - \b USB_HOST_PWREN_MAN_HIGH - USBEPEN is driven high by the USB controller -//! when USBHostPwrEnable() is called. -//! - \b USB_HOST_PWREN_AUTOLOW - USBEPEN is driven low by the USB controller +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller //! automatically if USBOTGSessionRequest() has //! enabled a session. -//! - \b USB_HOST_PWREN_AUTOHIGH - USBEPEN is driven high by the USB controller -//! automatically if USBOTGSessionRequest() has -//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. //! //! On devices that support the VBUS glitch filter, the -//! \b USB_HOST_PWREN_FILTER can be added to ignore small short drops in VBUS -//! level caused by high power consumption. This is mainly used to avoid -//! causing VBUS errors caused by devices with high in-rush current. +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. //! //! \note The following values have been deprecated and should no longer be //! used. @@ -3390,8 +3469,8 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! enabled. //! - \b USB_HOST_PWREN_VBLOW - Automatically drive USBnEPEN low when power is //! enabled. -//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power is -//! enabled. +//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power +//! is enabled. //! //! \note This function should only be called on microcontrollers that support //! host mode or OTG operation. @@ -3406,8 +3485,9 @@ USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags) // Check the arguments. // ASSERT(ulBase == USB0_BASE); - ASSERT((ulFlags & ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | - USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)) == 0); + ASSERT((ulFlags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0); // // If requested, enable VBUS droop detection on parts that support this @@ -3416,8 +3496,8 @@ USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags) HWREG(ulBase + USB_O_VDC) = ulFlags >> 16; // - // Set the power fault configuration as specified. This will not change - // whether fault detection is enabled or not. + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. // HWREGH(ulBase + USB_O_EPC) = (ulFlags | (HWREGH(ulBase + USB_O_EPC) & @@ -3432,7 +3512,7 @@ USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! //! This function enables power fault detection in the USB controller. If the -//! USBPFLT pin is not in use this function should not be used. +//! USBnPFLT pin is not in use, this function should not be used. //! //! \note This function should only be called in host mode. //! @@ -3486,8 +3566,8 @@ USBHostPwrFaultDisable(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function enables the USBEPEN signal to enable an external power supply -//! in host mode operation. +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. //! //! \note This function should only be called in host mode. //! @@ -3514,8 +3594,8 @@ USBHostPwrEnable(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function disables the USBEPEN signal to disable an external power -//! supply in host mode operation. +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. //! //! \note This function should only be called in host mode. //! @@ -3570,7 +3650,7 @@ USBFrameNumberGet(unsigned long ulBase) //! //! This function is used in OTG mode to start a session request or end a //! session. If the \e bStart parameter is set to \b true, then this function -//! start a session and if it is \b false it will end a session. +//! starts a session and if it is \b false it ends a session. //! //! \return None. // @@ -3603,10 +3683,10 @@ USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart) //! \param ulBase specifies the USB module base address. //! \param ulEndpoint specifies which endpoint's FIFO address to return. //! -//! This function returns the actual physical address of the FIFO. This is -//! needed when the USB is going to be used with the uDMA controller and the -//! source or destination address needs to be set to the physical FIFO address -//! for a given endpoint. +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. //! //! \return None. // @@ -3631,7 +3711,7 @@ USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint) //! //! For OTG controllers: //! -//! The function will return on of the following values on OTG controllers: +//! The function returns one of the following values on OTG controllers: //! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, //! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, //! \b USB_OTG_MODE_NONE. @@ -3646,15 +3726,15 @@ USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint) //! on the B-side of the cable. //! //! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode -//! on the B-side of the cable. If and OTG session request is started with no -//! cable in place this is the default mode for the controller. +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. //! //! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to //! determine its role in the system. //! //! For Dual Mode controllers: //! -//! The function will return on of the following values: +//! The function returns one of the following values: //! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or //! \b USB_DUAL_MODE_NONE. //! @@ -3705,14 +3785,14 @@ USBModeGet(unsigned long ulBase) //! //! This function is used to configure which DMA channel to use with a given //! endpoint. Receive DMA channels can only be used with receive endpoints -//! and transmit DMA channels can only be used with transmit endpoints. This -//! allows the 3 receive and 3 transmit DMA channels to be mapped to any -//! endpoint other than 0. The values that should be passed into the \e -//! ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that should be passed into the +//! \e ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. //! //! \note This function only has an effect on microcontrollers that have the //! ability to change the DMA channel for an endpoint. Calling this function -//! on other devices will have no effect. +//! on other devices has no effect. //! //! \return None. //! @@ -3738,7 +3818,7 @@ USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX); // - // The input select mask needs to be shifted into the correct position + // The input select mask must be shifted into the correct position // based on the channel. // ulMask = 0xf << (ulChannel * 4); @@ -3766,9 +3846,10 @@ USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! -//! This function changes the mode of the USB controller to host mode. This -//! is only valid on microcontrollers that have the host and device -//! capabilities and not the OTG capabilities. +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function should only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. //! //! \return None. // @@ -3796,9 +3877,10 @@ USBHostMode(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function changes the mode of the USB controller to device mode. This -//! is only valid on microcontrollers that have the host and device -//! capabilities and not the OTG capabilities. +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function should only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. //! //! \return None. // @@ -3817,6 +3899,79 @@ USBDevMode(unsigned long ulBase) HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; } +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ulBase + USB_O_GPCS) = 0; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(unsigned long ulBase) +{ + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function should +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(unsigned long ulBase) +{ + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm3s8962/Libraries/driverlib/usb.h b/bsp/lm3s8962/Libraries/driverlib/usb.h index 5c5b8638eb..66a94d0876 100644 --- a/bsp/lm3s8962/Libraries/driverlib/usb.h +++ b/bsp/lm3s8962/Libraries/driverlib/usb.h @@ -2,7 +2,7 @@ // // usb.h - Prototypes for the USB Interface Driver. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -152,6 +152,7 @@ extern "C" // USB_DEV_* values are used when the USB controller is in device mode. // //***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts #define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received #define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond #define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received @@ -163,6 +164,7 @@ extern "C" // device #define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full #define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts #define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the // specified timeout period #define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device @@ -474,6 +476,8 @@ extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags); extern void USBHostPwrFaultDisable(unsigned long ulBase); extern void USBHostPwrFaultEnable(unsigned long ulBase); extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint); +extern void USBHostRequestINClear(unsigned long ulBase, + unsigned long ulEndpoint); extern void USBHostRequestStatus(unsigned long ulBase); extern void USBHostReset(unsigned long ulBase, tBoolean bStart); extern void USBHostResume(unsigned long ulBase, tBoolean bStart); @@ -497,8 +501,10 @@ extern void USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, unsigned long ulChannel); extern void USBHostMode(unsigned long ulBase); -extern void USBHostMode(unsigned long ulBase); extern void USBDevMode(unsigned long ulBase); +extern void USBOTGMode(unsigned long ulBase); +extern void USBPHYPowerOff(unsigned long ulBase); +extern void USBPHYPowerOn(unsigned long ulBase); //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/driverlib/watchdog.c b/bsp/lm3s8962/Libraries/driverlib/watchdog.c index 6e33ea52fd..b3961c9494 100644 --- a/bsp/lm3s8962/Libraries/driverlib/watchdog.c +++ b/bsp/lm3s8962/Libraries/driverlib/watchdog.c @@ -2,7 +2,7 @@ // // watchdog.c - Driver for the Watchdog Timer Module. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -43,9 +43,9 @@ //! //! \param ulBase is the base address of the watchdog timer module. //! -//! This will check to see if the watchdog timer is enabled. +//! This function checks to see if the watchdog timer is enabled. //! -//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! \return Returns \b true if the watchdog timer is enabled and \b false //! if it is not. // //***************************************************************************** @@ -69,10 +69,9 @@ WatchdogRunning(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! This will enable the watchdog timer counter and interrupt. +//! This function enables the watchdog timer counter and interrupt. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock() //! @@ -99,12 +98,11 @@ WatchdogEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Enables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. //! +//! \note This function has no effect if the watchdog timer has been locked. +//! //! \sa WatchdogLock(), WatchdogUnlock() //! //! \return None. @@ -130,11 +128,10 @@ WatchdogResetEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Disables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock() //! @@ -161,7 +158,8 @@ WatchdogResetDisable(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Locks out write access to the watchdog timer configuration registers. +//! This function locks out write access to the watchdog timer configuration +//! registers. //! //! \return None. // @@ -187,7 +185,8 @@ WatchdogLock(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Enables write access to the watchdog timer configuration registers. +//! This function enables write access to the watchdog timer configuration +//! registers. //! //! \return None. // @@ -212,7 +211,7 @@ WatchdogUnlock(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Returns the lock state of the watchdog timer registers. +//! This function returns the lock state of the watchdog timer registers. //! //! \return Returns \b true if the watchdog timer registers are locked, and //! \b false if they are not locked. @@ -239,14 +238,13 @@ WatchdogLockState(unsigned long ulBase) //! \param ulBase is the base address of the watchdog timer module. //! \param ulLoadVal is the load value for the watchdog timer. //! -//! This function sets the value to load into the watchdog timer when the count -//! reaches zero for the first time; if the watchdog timer is running when this -//! function is called, then the value will be immediately loaded into the -//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an //! interrupt is immediately generated. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() //! @@ -322,21 +320,27 @@ WatchdogValueGet(unsigned long ulBase) //***************************************************************************** // -//! Registers an interrupt handler for watchdog timer interrupt. +//! Registers an interrupt handler for the watchdog timer interrupt. //! //! \param ulBase is the base address of the watchdog timer module. //! \param pfnHandler is a pointer to the function to be called when the //! watchdog timer interrupt occurs. //! //! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; the watchdog -//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via +//! function also enables the global interrupt in the interrupt controller; the +//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via //! WatchdogIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. //! +//! \note For parts with a watchdog timer module that has the ability to +//! generate an NMI instead of a standard interrupt, this function registers +//! the standard watchdog interrupt handler. To register the NMI watchdog +//! handler, use IntRegister() to register the handler for the +//! \b FAULT_NMI interrupt. +//! //! \return None. // //***************************************************************************** @@ -366,13 +370,19 @@ WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! \param ulBase is the base address of the watchdog timer module. //! //! This function does the actual unregistering of the interrupt handler. This -//! function will clear the handler to be called when a watchdog timer -//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt //! controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. //! +//! \note For parts with a watchdog timer module that has the ability to +//! generate an NMI instead of a standard interrupt, this function unregisters +//! the standard watchdog interrupt handler. To unregister the NMI watchdog +//! handler, use IntUnregister() to unregister the handler for the +//! \b FAULT_NMI interrupt. +//! //! \return None. // //***************************************************************************** @@ -401,10 +411,9 @@ WatchdogIntUnregister(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Enables the watchdog timer interrupt. +//! This function enables the watchdog timer interrupt. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() //! @@ -433,9 +442,9 @@ WatchdogIntEnable(unsigned long ulBase) //! \param bMasked is \b false if the raw interrupt status is required and //! \b true if the masked interrupt status is required. //! -//! This returns the interrupt status for the watchdog timer module. Either -//! the raw interrupt status or the status of interrupt that is allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the watchdog timer module. +//! Either the raw interrupt status or the status of interrupt that is allowed +//! to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, where a 1 indicates that the //! watchdog interrupt is active, and a 0 indicates that it is not active. @@ -472,14 +481,14 @@ WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) //! The watchdog timer interrupt source is cleared, so that it no longer //! asserts. //! -//! \note Since there is a write buffer in the Cortex-M3 processor, it may take -//! several clock cycles before the interrupt source is actually cleared. +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid //! returning from the interrupt handler before the interrupt source is //! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (since NVIC still sees the interrupt source -//! asserted). +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). //! //! \return None. // @@ -498,6 +507,46 @@ WatchdogIntClear(unsigned long ulBase) HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; } +//***************************************************************************** +// +//! Sets the type of interrupt generated by the watchdog. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulType is the type of interrupt to generate. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. \e ulType can be either \b WATCHDOG_INT_TYPE_INT to +//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to +//! generate a non-maskable interrupt (NMI). +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with WatchdogIntClear(). +//! +//! \note The ability to select an NMI interrupt varies with the Stellaris part +//! in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + ASSERT((ulType == WATCHDOG_INT_TYPE_INT) || + (ulType == WATCHDOG_INT_TYPE_NMI)); + + // + // Set the interrupt type. + // + HWREG(ulBase + WDT_O_CTL) = + (HWREG(ulBase + WDT_O_CTL) & ~WDT_CTL_INTTYPE) | ulType; +} + //***************************************************************************** // //! Enables stalling of the watchdog timer during debug events. @@ -507,9 +556,9 @@ WatchdogIntClear(unsigned long ulBase) //! This function allows the watchdog timer to stop counting when the processor //! is stopped by the debugger. By doing so, the watchdog is prevented from //! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog will instead -//! expired after the appropriate number of processor cycles have been executed -//! while debugging (or at the appropriate time after the processor has been +//! resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been //! restarted). //! //! \return None. diff --git a/bsp/lm3s8962/Libraries/driverlib/watchdog.h b/bsp/lm3s8962/Libraries/driverlib/watchdog.h index d1c6e5cf12..5efdcdbb23 100644 --- a/bsp/lm3s8962/Libraries/driverlib/watchdog.h +++ b/bsp/lm3s8962/Libraries/driverlib/watchdog.h @@ -2,7 +2,7 @@ // // watchdog.h - Prototypes for the Watchdog Timer API // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -36,6 +36,14 @@ extern "C" { #endif +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + //***************************************************************************** // // Prototypes for the APIs. @@ -56,6 +64,7 @@ extern void WatchdogIntUnregister(unsigned long ulBase); extern void WatchdogIntEnable(unsigned long ulBase); extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType); extern void WatchdogStallEnable(unsigned long ulBase); extern void WatchdogStallDisable(unsigned long ulBase); diff --git a/bsp/lm3s8962/Libraries/inc/asmdefs.h b/bsp/lm3s8962/Libraries/inc/asmdefs.h index 811f821078..cc9b5ef2f4 100644 --- a/bsp/lm3s8962/Libraries/inc/asmdefs.h +++ b/bsp/lm3s8962/Libraries/inc/asmdefs.h @@ -2,7 +2,7 @@ // // asmdefs.h - Macros to allow assembly code be portable among toolchains. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/inc/cr_project.xml b/bsp/lm3s8962/Libraries/inc/cr_project.xml deleted file mode 100644 index dec7adeb03..0000000000 --- a/bsp/lm3s8962/Libraries/inc/cr_project.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - - - diff --git a/bsp/lm3s8962/Libraries/inc/hw_adc.h b/bsp/lm3s8962/Libraries/inc/hw_adc.h index 8981d6a8d2..4e02573cf8 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_adc.h +++ b/bsp/lm3s8962/Libraries/inc/hw_adc.h @@ -2,7 +2,7 @@ // // hw_adc.h - Macros used when accessing the ADC hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -37,6 +37,7 @@ #define ADC_O_OSTAT 0x00000010 // ADC Overflow Status #define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select #define ADC_O_USTAT 0x00000018 // ADC Underflow Status +#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select #define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority #define ADC_O_SPC 0x00000024 // ADC Sample Phase Control #define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence @@ -55,6 +56,8 @@ #define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation #define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital // Comparator Select +#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended + // Input Multiplexer Select 0 #define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input // Multiplexer Select 1 #define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 @@ -65,6 +68,8 @@ #define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation #define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital // Comparator Select +#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended + // Input Multiplexer Select 1 #define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input // Multiplexer Select 2 #define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 @@ -75,6 +80,8 @@ #define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation #define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital // Comparator Select +#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended + // Input Multiplexer Select 2 #define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input // Multiplexer Select 3 #define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 @@ -85,6 +92,8 @@ #define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation #define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital // Comparator Select +#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended + // Input Multiplexer Select 3 #define ADC_O_TMLB 0x00000100 // ADC Test Mode Loopback #define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset // Initial Conditions @@ -104,6 +113,9 @@ #define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 #define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 #define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 +#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties +#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration +#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration //***************************************************************************** // @@ -237,6 +249,24 @@ #define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow #define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x03000000 // PWM Unit Select +#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS3_1 0x01000000 // PWM Unit 1 +#define ADC_TSSEL_PS2_M 0x00030000 // PWM Unit Select +#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS2_1 0x00010000 // PWM Unit 1 +#define ADC_TSSEL_PS1_M 0x00000300 // PWM Unit Select +#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS1_1 0x00000100 // PWM Unit 1 +#define ADC_TSSEL_PS0_M 0x00000003 // PWM Unit Select +#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS0_1 0x00000001 // PWM Unit 1 + //***************************************************************************** // // The following are defines for the bit fields in the ADC_O_SSPRI register. @@ -339,6 +369,19 @@ // The following are defines for the bit fields in the ADC_O_CTL register. // //***************************************************************************** +#define ADC_CTL_RES 0x00000010 // Sample Resolution +#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the + // voltage reference +#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is + // the voltage reference. The ADC + // conversion range is 0.0 V to the + // external reference value +#define ADC_CTL_VREF_EXT_1V 0x00000003 // A 1.0 V external VREFA input is + // the voltage reference. The ADC + // conversion range is 0.0 V to + // three times the external + // reference value #define ADC_CTL_VREF 0x00000001 // Voltage Reference Select //***************************************************************************** @@ -406,7 +449,7 @@ // The following are defines for the bit fields in the ADC_O_SSFIFO0 register. // //***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data #define ADC_SSFIFO0_DATA_S 0 //***************************************************************************** @@ -472,6 +515,28 @@ #define ADC_SSDC0_S1DCSEL_S 4 #define ADC_SSDC0_S0DCSEL_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. +// +//***************************************************************************** +#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + //***************************************************************************** // // The following are defines for the bit fields in the ADC_O_SSMUX1 register. @@ -513,7 +578,7 @@ // The following are defines for the bit fields in the ADC_O_SSFIFO1 register. // //***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data #define ADC_SSFIFO1_DATA_S 0 //***************************************************************************** @@ -559,6 +624,20 @@ #define ADC_SSDC1_S1DCSEL_S 4 #define ADC_SSDC1_S0DCSEL_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. +// +//***************************************************************************** +#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + //***************************************************************************** // // The following are defines for the bit fields in the ADC_O_SSMUX2 register. @@ -600,7 +679,7 @@ // The following are defines for the bit fields in the ADC_O_SSFIFO2 register. // //***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data #define ADC_SSFIFO2_DATA_S 0 //***************************************************************************** @@ -646,6 +725,20 @@ #define ADC_SSDC2_S1DCSEL_S 4 #define ADC_SSDC2_S0DCSEL_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. +// +//***************************************************************************** +#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + //***************************************************************************** // // The following are defines for the bit fields in the ADC_O_SSMUX3 register. @@ -669,7 +762,7 @@ // The following are defines for the bit fields in the ADC_O_SSFIFO3 register. // //***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data #define ADC_SSFIFO3_DATA_S 0 //***************************************************************************** @@ -700,6 +793,14 @@ #define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator // Select +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. +// +//***************************************************************************** +#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + //***************************************************************************** // // The following are defines for the bit fields in the ADC_O_TMLB register. @@ -942,8 +1043,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP0 register. // //***************************************************************************** -#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP0_COMP1_S 16 #define ADC_DCCMP0_COMP0_S 0 @@ -952,8 +1053,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP1 register. // //***************************************************************************** -#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP1_COMP1_S 16 #define ADC_DCCMP1_COMP0_S 0 @@ -962,8 +1063,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP2 register. // //***************************************************************************** -#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP2_COMP1_S 16 #define ADC_DCCMP2_COMP0_S 0 @@ -972,8 +1073,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP3 register. // //***************************************************************************** -#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP3_COMP1_S 16 #define ADC_DCCMP3_COMP0_S 0 @@ -982,8 +1083,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP4 register. // //***************************************************************************** -#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP4_COMP1_S 16 #define ADC_DCCMP4_COMP0_S 0 @@ -992,8 +1093,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP5 register. // //***************************************************************************** -#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP5_COMP1_S 16 #define ADC_DCCMP5_COMP0_S 0 @@ -1002,8 +1103,8 @@ // The following are defines for the bit fields in the ADC_O_DCCMP6 register. // //***************************************************************************** -#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP6_COMP1_S 16 #define ADC_DCCMP6_COMP0_S 0 @@ -1012,11 +1113,54 @@ // The following are defines for the bit fields in the ADC_O_DCCMP7 register. // //***************************************************************************** -#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1 -#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0 +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 #define ADC_DCCMP7_COMP1_S 16 #define ADC_DCCMP7_COMP0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the + // PLL bypass is in effect) or the + // 16 MHz clock derived from PLL / + // 25 (default) +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC + //***************************************************************************** // // The following are defines for the the interpretation of the data in the diff --git a/bsp/lm3s8962/Libraries/inc/hw_can.h b/bsp/lm3s8962/Libraries/inc/hw_can.h index c4bdc08f0f..c1b3ae9a7c 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_can.h +++ b/bsp/lm3s8962/Libraries/inc/hw_can.h @@ -2,7 +2,7 @@ // // hw_can.h - Defines and macros used when accessing the CAN controllers. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/inc/hw_comp.h b/bsp/lm3s8962/Libraries/inc/hw_comp.h index 34d42dbb42..18e3b8262a 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_comp.h +++ b/bsp/lm3s8962/Libraries/inc/hw_comp.h @@ -2,7 +2,7 @@ // // hw_comp.h - Macros used when accessing the comparator hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -44,6 +44,8 @@ #define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1 #define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2 #define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2 +#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral + // Properties //***************************************************************************** // @@ -182,6 +184,18 @@ #define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge #define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + //***************************************************************************** // // The following definitions are deprecated. diff --git a/bsp/lm3s8962/Libraries/inc/hw_eeprom.h b/bsp/lm3s8962/Libraries/inc/hw_eeprom.h new file mode 100644 index 0000000000..6428bdecc8 --- /dev/null +++ b/bsp/lm3s8962/Libraries/inc/hw_eeprom.h @@ -0,0 +1,206 @@ +//***************************************************************************** +// +// hw_eeprom.h - Macros used when accessing the EEPROM controller. +// +// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EEPROM_H__ +#define __HW_EEPROM_H__ + +//***************************************************************************** +// +// The following are defines for the EEPROM register offsets. +// +//***************************************************************************** +#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information +#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block +#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset +#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write +#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment +#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status +#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and + // Status +#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock +#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection +#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password +#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password +#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password +#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt +#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide +#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase +#define EEPROM_EEPROMPP 0x400AFFC0 // EEPROM + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_S 0 +#define EEPROM_EESIZE_BLKCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy +#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_START 0x00000001 // Start Erase +#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROMPP +// register. +// +//***************************************************************************** +#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size +#define EEPROM_EEPROMPP_SIZE_S 0 + +#endif // __HW_EEPROM_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_epi.h b/bsp/lm3s8962/Libraries/inc/hw_epi.h index c434b84622..ab7d076ca2 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_epi.h +++ b/bsp/lm3s8962/Libraries/inc/hw_epi.h @@ -2,7 +2,7 @@ // // hw_epi.h - Macros for use in accessing the EPI registers. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -206,6 +206,18 @@ #define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration #define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration #define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration +#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity +#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity +#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States +#define EPI_HB8CFG2_WRWS_0 0x00000000 // No wait states +#define EPI_HB8CFG2_WRWS_1 0x00000040 // 1 wait state +#define EPI_HB8CFG2_WRWS_2 0x00000080 // 2 wait states +#define EPI_HB8CFG2_WRWS_3 0x000000C0 // 3 wait states +#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States +#define EPI_HB8CFG2_RDWS_0 0x00000000 // No wait states +#define EPI_HB8CFG2_RDWS_1 0x00000010 // 1 wait state +#define EPI_HB8CFG2_RDWS_2 0x00000020 // 2 wait states +#define EPI_HB8CFG2_RDWS_3 0x00000030 // 3 wait states //***************************************************************************** // @@ -219,6 +231,18 @@ #define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration #define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration #define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration +#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity +#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity +#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States +#define EPI_HB16CFG2_WRWS_0 0x00000000 // No wait states +#define EPI_HB16CFG2_WRWS_1 0x00000040 // 1 wait state +#define EPI_HB16CFG2_WRWS_2 0x00000080 // 2 wait states +#define EPI_HB16CFG2_WRWS_3 0x000000C0 // 3 wait states +#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States +#define EPI_HB16CFG2_RDWS_0 0x00000000 // No wait states +#define EPI_HB16CFG2_RDWS_1 0x00000010 // 1 wait state +#define EPI_HB16CFG2_RDWS_2 0x00000020 // 2 wait states +#define EPI_HB16CFG2_RDWS_3 0x00000030 // 3 wait states //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/inc/hw_ethernet.h b/bsp/lm3s8962/Libraries/inc/hw_ethernet.h index 80ba508547..91da8867c1 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_ethernet.h +++ b/bsp/lm3s8962/Libraries/inc/hw_ethernet.h @@ -2,7 +2,7 @@ // // hw_ethernet.h - Macros used when accessing the Ethernet hardware. // -// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -45,6 +45,7 @@ #define MAC_O_THR 0x0000001C // Ethernet MAC Threshold #define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control #define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider +#define MAC_O_MADD 0x00000028 // Ethernet MAC Management Address #define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit // Data #define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive @@ -176,6 +177,14 @@ #define MAC_MDV_DIV_M 0x000000FF // Clock Divider #define MAC_MDV_DIV_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_O_MADD register. +// +//***************************************************************************** +#define MAC_MADD_PHYADR_M 0x0000001F // PHY Address +#define MAC_MADD_PHYADR_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the MAC_O_MTXD register. diff --git a/bsp/lm3s8962/Libraries/inc/hw_fan.h b/bsp/lm3s8962/Libraries/inc/hw_fan.h new file mode 100644 index 0000000000..22f9f05553 --- /dev/null +++ b/bsp/lm3s8962/Libraries/inc/hw_fan.h @@ -0,0 +1,636 @@ +//***************************************************************************** +// +// hw_fan.h - Macros used when accessing the fan control hardware. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_FAN_H__ +#define __HW_FAN_H__ + +//***************************************************************************** +// +// The following are defines for the Fan Control register offsets. +// +//***************************************************************************** +#define FAN_O_STS 0x00000000 // FAN Status +#define FAN_O_CTL 0x00000004 // FAN Control +#define FAN_O_CH0 0x00000010 // FAN Channel Command +#define FAN_O_CMD0 0x00000014 // FAN Channel Command +#define FAN_O_CST0 0x00000018 // FAN Channel Status +#define FAN_O_CH1 0x00000020 // FAN Channel Setup +#define FAN_O_CMD1 0x00000024 // FAN Channel Command +#define FAN_O_CST1 0x00000028 // FAN Channel Status +#define FAN_O_CH2 0x00000030 // FAN Channel Setup +#define FAN_O_CMD2 0x00000034 // FAN Channel Command +#define FAN_O_CST2 0x00000038 // FAN Channel Status +#define FAN_O_CH3 0x00000040 // FAN Channel Setup +#define FAN_O_CMD3 0x00000044 // FAN Channel Command +#define FAN_O_CST3 0x00000048 // FAN Channel Status +#define FAN_O_CH4 0x00000050 // FAN Channel Setup +#define FAN_O_CMD4 0x00000054 // FAN Channel Command +#define FAN_O_CST4 0x00000058 // FAN Channel Status +#define FAN_O_CH5 0x00000060 // FAN Channel Setup +#define FAN_O_CMD5 0x00000064 // FAN Channel Command +#define FAN_O_CST5 0x00000068 // FAN Channel Status +#define FAN_O_CH6 0x00000070 // FAN Channel Setup +#define FAN_O_CMD6 0x00000074 // FAN Channel Command +#define FAN_O_CST6 0x00000078 // FAN Channel Status +#define FAN_O_CH7 0x00000080 // FAN Channel Setup +#define FAN_O_CMD7 0x00000084 // FAN Channel Command +#define FAN_O_CST7 0x00000088 // FAN Channel Status +#define FAN_O_IM 0x00000090 // FAN Interrupt Mask +#define FAN_O_RIS 0x00000094 // FAN Raw Interrupt Status +#define FAN_O_MIS 0x00000098 // FAN Masked Interrupt Status +#define FAN_O_IC 0x0000009C // FAN Interrupt Clear +#define FAN_O_PP 0x00000FC0 // FAN Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_STS register. +// +//***************************************************************************** +#define FAN_STS_FANCNT_M 0x000F0000 // Fan Count +#define FAN_STS_ST5_M 0x00000C00 // Fan 5 Status +#define FAN_STS_ST5_STALLED 0x00000000 // Stalled +#define FAN_STS_ST5_CHANGING 0x00000400 // Changing +#define FAN_STS_ST5_LOCKED 0x00000800 // Locked +#define FAN_STS_ST5_UNBALANCED 0x00000C00 // Unbalanced Spin +#define FAN_STS_ST4_M 0x00000300 // Fan 4 Status +#define FAN_STS_ST3_M 0x000000C0 // Fan 3 Status +#define FAN_STS_ST2_M 0x00000030 // Fan 2 Status +#define FAN_STS_ST1_M 0x0000000C // Fan 1 Status +#define FAN_STS_ST0_M 0x00000003 // Fan 0 Status +#define FAN_STS_FANCNT_S 16 +#define FAN_STS_ST4_S 8 +#define FAN_STS_ST3_S 6 +#define FAN_STS_ST2_S 4 +#define FAN_STS_ST1_S 2 +#define FAN_STS_ST0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CTL register. +// +//***************************************************************************** +#define FAN_CTL_E5 0x00000020 // Fan 5 Enable +#define FAN_CTL_E4 0x00000010 // Fan 4 Enable +#define FAN_CTL_E3 0x00000008 // Fan 3 Enable +#define FAN_CTL_E2 0x00000004 // Fan 2 Enable +#define FAN_CTL_E1 0x00000002 // Fan 1 Enable +#define FAN_CTL_E0 0x00000001 // Fan 0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH0 register. +// +//***************************************************************************** +#define FAN_CH0_ASTART 0x00008000 // Auto Restart +#define FAN_CH0_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH0_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH0_STPER_M 0x00000700 // Start Period +#define FAN_CH0_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH0_START_NOFAST 0x00000000 // No fast start +#define FAN_CH0_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH0_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH0_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH0_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH0_AVG_0 0x00000000 // No averaging +#define FAN_CH0_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH0_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH0_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH0_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH0_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH0_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH0_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH0_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH0_MAN 0x00000001 // Control Type +#define FAN_CH0_HYST_S 11 +#define FAN_CH0_STPER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD0 register. +// +//***************************************************************************** +#define FAN_CMD0_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD0_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD0_DC_S 16 +#define FAN_CMD0_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST0 register. +// +//***************************************************************************** +#define FAN_CST0_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST0_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST0_COUNT_S 16 +#define FAN_CST0_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH1 register. +// +//***************************************************************************** +#define FAN_CH1_ASTART 0x00008000 // Auto Restart +#define FAN_CH1_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH1_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH1_STPER_M 0x00000700 // Start Period +#define FAN_CH1_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH1_START_NOFAST 0x00000000 // No fast start +#define FAN_CH1_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH1_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH1_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH1_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH1_AVG_0 0x00000000 // No averaging +#define FAN_CH1_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH1_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH1_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH1_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH1_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH1_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH1_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH1_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH1_MAN 0x00000001 // Control Type +#define FAN_CH1_HYST_S 11 +#define FAN_CH1_STPER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD1 register. +// +//***************************************************************************** +#define FAN_CMD1_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD1_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD1_DC_S 16 +#define FAN_CMD1_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST1 register. +// +//***************************************************************************** +#define FAN_CST1_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST1_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST1_COUNT_S 16 +#define FAN_CST1_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH2 register. +// +//***************************************************************************** +#define FAN_CH2_ASTART 0x00008000 // Auto Restart +#define FAN_CH2_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH2_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH2_STPER_M 0x00000700 // Start Period +#define FAN_CH2_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH2_START_NOFAST 0x00000000 // No fast start +#define FAN_CH2_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH2_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH2_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH2_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH2_AVG_0 0x00000000 // No averaging +#define FAN_CH2_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH2_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH2_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH2_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH2_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH2_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH2_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH2_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH2_MAN 0x00000001 // Control Type +#define FAN_CH2_HYST_S 11 +#define FAN_CH2_STPER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD2 register. +// +//***************************************************************************** +#define FAN_CMD2_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD2_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD2_DC_S 16 +#define FAN_CMD2_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST2 register. +// +//***************************************************************************** +#define FAN_CST2_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST2_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST2_COUNT_S 16 +#define FAN_CST2_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH3 register. +// +//***************************************************************************** +#define FAN_CH3_ASTART 0x00008000 // Auto Restart +#define FAN_CH3_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH3_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH3_STPER_M 0x00000700 // Start Period +#define FAN_CH3_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH3_START_NOFAST 0x00000000 // No fast start +#define FAN_CH3_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH3_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH3_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH3_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH3_AVG_0 0x00000000 // No averaging +#define FAN_CH3_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH3_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH3_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH3_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH3_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH3_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH3_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH3_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH3_MAN 0x00000001 // Control Type +#define FAN_CH3_HYST_S 11 +#define FAN_CH3_STPER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD3 register. +// +//***************************************************************************** +#define FAN_CMD3_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD3_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD3_DC_S 16 +#define FAN_CMD3_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST3 register. +// +//***************************************************************************** +#define FAN_CST3_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST3_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST3_COUNT_S 16 +#define FAN_CST3_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH4 register. +// +//***************************************************************************** +#define FAN_CH4_ASTART 0x00008000 // Auto Restart +#define FAN_CH4_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH4_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH4_STPER_M 0x00000700 // Start Period +#define FAN_CH4_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH4_START_NOFAST 0x00000000 // No fast start +#define FAN_CH4_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH4_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH4_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH4_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH4_AVG_0 0x00000000 // No averaging +#define FAN_CH4_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH4_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH4_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH4_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH4_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH4_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH4_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH4_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH4_MAN 0x00000001 // Control Type +#define FAN_CH4_HYST_S 11 +#define FAN_CH4_STPER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD4 register. +// +//***************************************************************************** +#define FAN_CMD4_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD4_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD4_DC_S 16 +#define FAN_CMD4_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST4 register. +// +//***************************************************************************** +#define FAN_CST4_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST4_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST4_COUNT_S 16 +#define FAN_CST4_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH5 register. +// +//***************************************************************************** +#define FAN_CH5_ASTART 0x00008000 // Auto Restart +#define FAN_CH5_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH5_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH5_STPER_M 0x00000700 // Start Period +#define FAN_CH5_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH5_START_NOFAST 0x00000000 // No fast start +#define FAN_CH5_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH5_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH5_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH5_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH5_AVG_0 0x00000000 // No averaging +#define FAN_CH5_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH5_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH5_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH5_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH5_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH5_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH5_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH5_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH5_MAN 0x00000001 // Control Type +#define FAN_CH5_HYST_S 11 +#define FAN_CH5_STPER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD5 register. +// +//***************************************************************************** +#define FAN_CMD5_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD5_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD5_DC_S 16 +#define FAN_CMD5_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST5 register. +// +//***************************************************************************** +#define FAN_CST5_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST5_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST5_COUNT_S 16 +#define FAN_CST5_RPM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH6 register. +// +//***************************************************************************** +#define FAN_CH6_MAN 0x00000001 // Control Type +#define FAN_CH6_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH6_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH6_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH6_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH6_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH6_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH6_AVG_0 0x00000000 // No averaging +#define FAN_CH6_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH6_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH6_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH6_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH6_START_NOFAST 0x00000000 // No fast start +#define FAN_CH6_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH6_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH6_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH6_STPER_M 0x00000700 // Start Period +#define FAN_CH6_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH6_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH6_ASTART 0x00008000 // Auto Restart +#define FAN_CH6_STPER_S 8 +#define FAN_CH6_HYST_S 11 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD6 register. +// +//***************************************************************************** +#define FAN_CMD6_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD6_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD6_RPM_S 0 +#define FAN_CMD6_DC_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST6 register. +// +//***************************************************************************** +#define FAN_CST6_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST6_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST6_RPM_S 0 +#define FAN_CST6_COUNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CH7 register. +// +//***************************************************************************** +#define FAN_CH7_MAN 0x00000001 // Control Type +#define FAN_CH7_PPR_M 0x0000000C // Pulse per Revolution on + // Tachometer +#define FAN_CH7_PPR_1 0x00000000 // 1 pulse per revolution +#define FAN_CH7_PPR_2 0x00000004 // 2 pulses per revolution +#define FAN_CH7_PPR_4 0x00000008 // 4 pulses per revolution +#define FAN_CH7_PPR_8 0x0000000C // 8 pulses per revolution +#define FAN_CH7_AVG_M 0x00000030 // Averaging of Tachometer +#define FAN_CH7_AVG_0 0x00000000 // No averaging +#define FAN_CH7_AVG_2 0x00000010 // Average 2 edges +#define FAN_CH7_AVG_4 0x00000020 // Average 4 edges +#define FAN_CH7_AVG_8 0x00000030 // Average 8 edges +#define FAN_CH7_START_M 0x000000C0 // Fast Start Rule +#define FAN_CH7_START_NOFAST 0x00000000 // No fast start +#define FAN_CH7_START_50DC 0x00000040 // 50% duty cycle +#define FAN_CH7_START_75DC 0x00000080 // 75% duty cycle +#define FAN_CH7_START_100DC 0x000000C0 // 100% duty cycle +#define FAN_CH7_STPER_M 0x00000700 // Start Period +#define FAN_CH7_HYST_M 0x00003800 // Hysteresis Adjustment on PID + // Adjust +#define FAN_CH7_ACCEL 0x00004000 // Acceleration and Deceleration + // Rule +#define FAN_CH7_ASTART 0x00008000 // Auto Restart +#define FAN_CH7_STPER_S 8 +#define FAN_CH7_HYST_S 11 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CMD7 register. +// +//***************************************************************************** +#define FAN_CMD7_RPM_M 0x00001FFF // Fan Speed (in RPM) +#define FAN_CMD7_DC_M 0x01FF0000 // PWM Duty Cycle +#define FAN_CMD7_RPM_S 0 +#define FAN_CMD7_DC_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_CST7 register. +// +//***************************************************************************** +#define FAN_CST7_RPM_M 0x00001FFF // Last Read RPM Speed Computed +#define FAN_CST7_COUNT_M 0x07FF0000 // Last Read Tachometer Count +#define FAN_CST7_RPM_S 0 +#define FAN_CST7_COUNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_IM register. +// +//***************************************************************************** +#define FAN_IM_C5INT1IM 0x00400000 // Channel 5 Interrupt 1 Mask +#define FAN_IM_C5INT0IM 0x00200000 // Channel 5 Interrupt 0 Mask +#define FAN_IM_C5STALLIM 0x00100000 // Channel 5 Stall Interrupt Mask +#define FAN_IM_C4INT1IM 0x00040000 // Channel 4 Interrupt 1 Mask +#define FAN_IM_C4INT0IM 0x00020000 // Channel 4 Interrupt 0 Mask +#define FAN_IM_C4STALLIM 0x00010000 // Channel 4 Stall Interrupt Mask +#define FAN_IM_C3INT1IM 0x00004000 // Channel 3 Interrupt 1 Mask +#define FAN_IM_C3INT0IM 0x00002000 // Channel 3 Interrupt 0 Mask +#define FAN_IM_C3STALLIM 0x00001000 // Channel 3 Stall Interrupt Mask +#define FAN_IM_C2INT1IM 0x00000400 // Channel 2 Interrupt 1 Mask +#define FAN_IM_C2INT0IM 0x00000200 // Channel 2 Interrupt 0 Mask +#define FAN_IM_C2STALLIM 0x00000100 // Channel 2 Stall Interrupt Mask +#define FAN_IM_C1INT1IM 0x00000040 // Channel 1 Interrupt 1 Mask +#define FAN_IM_C1INT0IM 0x00000020 // Channel 1 Interrupt 0 Mask +#define FAN_IM_C1STALLIM 0x00000010 // Channel 1 Stall Interrupt Mask +#define FAN_IM_C0INT1IM 0x00000004 // Channel 0 Interrupt 1 Mask +#define FAN_IM_C0INT0IM 0x00000002 // Channel 0 Interrupt 0 Mask +#define FAN_IM_C0STALLIM 0x00000001 // Channel 0 Stall Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_RIS register. +// +//***************************************************************************** +#define FAN_RIS_C5INT1RIS 0x00400000 // Channel 5 Raw Interrupt 1 Status +#define FAN_RIS_C5INT0RIS 0x00200000 // Channel 5 Raw Interrupt 0 Status +#define FAN_RIS_C5STALLRIS 0x00100000 // Channel 5 Raw Stall Interrupt + // Status +#define FAN_RIS_C4INT1RIS 0x00040000 // Channel 4 Raw Interrupt 1 Status +#define FAN_RIS_C4INT0RIS 0x00020000 // Channel 4 Raw Interrupt 0 Status +#define FAN_RIS_C4STALLRIS 0x00010000 // Channel 4 Raw Stall Interrupt + // Status +#define FAN_RIS_C3INT1RIS 0x00004000 // Channel 3 Raw Interrupt 1 Status +#define FAN_RIS_C3INT0RIS 0x00002000 // Channel 3 Raw Interrupt 0 Status +#define FAN_RIS_C3STALLRIS 0x00001000 // Channel 3 Raw Stall Interrupt + // Status +#define FAN_RIS_C2INT1RIS 0x00000400 // Channel 2 Raw Interrupt 1 Status +#define FAN_RIS_C2INT0RIS 0x00000200 // Channel 2 Raw Interrupt 0 Status +#define FAN_RIS_C2STALLRIS 0x00000100 // Channel 2 Raw Stall Interrupt + // Status +#define FAN_RIS_C1INT1RIS 0x00000040 // Channel 1 Raw Interrupt 1 Status +#define FAN_RIS_C1INT0RIS 0x00000020 // Channel 1 Raw Interrupt 0 Status +#define FAN_RIS_C1STALLRIS 0x00000010 // Channel 1 Raw Stall Interrupt + // Status +#define FAN_RIS_C0INT1RIS 0x00000004 // Channel 0 Raw Interrupt 1 Status +#define FAN_RIS_C0INT0RIS 0x00000002 // Channel 0 Raw Interrupt 0 Status +#define FAN_RIS_C0STALLRIS 0x00000001 // Channel 0 Raw Stall Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_MIS register. +// +//***************************************************************************** +#define FAN_MIS_C5INT1MIS 0x00400000 // Channel 5 Masked Interrupt 1 + // Status +#define FAN_MIS_C5INT0MIS 0x00200000 // Channel 5 Masked Interrupt 0 + // Status +#define FAN_MIS_C5STALLMIS 0x00100000 // Channel 5 Masked Stall Interrupt + // Status +#define FAN_MIS_C54NT1MIS 0x00040000 // Channel 4 Masked Interrupt 1 + // Status +#define FAN_MIS_C4INT0MIS 0x00020000 // Channel 4 Masked Interrupt 0 + // Status +#define FAN_MIS_C4STALLMIS 0x00010000 // Channel 4 Masked Stall Interrupt + // Status +#define FAN_MIS_C3INT1MIS 0x00004000 // Channel 3 Masked Interrupt 1 + // Status +#define FAN_MIS_C3INT0MIS 0x00002000 // Channel 3 Masked Interrupt 0 + // Status +#define FAN_MIS_C3STALLMIS 0x00001000 // Channel 3 Masked Stall Interrupt + // Status +#define FAN_MIS_C2INT1MIS 0x00000400 // Channel 2 Masked Interrupt 1 + // Status +#define FAN_MIS_C2INT0MIS 0x00000200 // Channel 2 Masked Interrupt 0 + // Status +#define FAN_MIS_C2STALLMIS 0x00000100 // Channel 2 Masked Stall Interrupt + // Status +#define FAN_MIS_C1INT1MIS 0x00000040 // Channel 1 Masked Interrupt 1 + // Status +#define FAN_MIS_C1INT0MIS 0x00000020 // Channel 1 Masked Interrupt 0 + // Status +#define FAN_MIS_C1STALLMIS 0x00000010 // Channel 1 Masked Stall Interrupt + // Status +#define FAN_MIS_C0INT1MIS 0x00000004 // Channel 0 Masked Interrupt 1 + // Status +#define FAN_MIS_C0INT0MIS 0x00000002 // Channel 0 Masked Interrupt 0 + // Status +#define FAN_MIS_C0STALLMIS 0x00000001 // Channel 0 Masked Stall Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_IC register. +// +//***************************************************************************** +#define FAN_IC_C5INT1IC 0x00400000 // Channel 5 Interrupt 1 Clear +#define FAN_IC_C5INT0IC 0x00200000 // Channel 5 Interrupt 0 Clear +#define FAN_IC_C5STALLIC 0x00100000 // Channel 5 Stall Interrupt Clear +#define FAN_IC_C4INT1IC 0x00040000 // Channel 4 Interrupt 1 Clear +#define FAN_IC_C4INT0IC 0x00020000 // Channel 4 Interrupt 0 Clear +#define FAN_IC_C4STALLIC 0x00010000 // Channel 4 Stall Interrupt Clear +#define FAN_IC_C3INT1IC 0x00004000 // Channel 3 Interrupt 1 Clear +#define FAN_IC_C53INT0IC 0x00002000 // Channel 3 Interrupt 0 Clear +#define FAN_IC_C3STALLIC 0x00001000 // Channel 3 Stall Interrupt Clear +#define FAN_IC_C2INT1IC 0x00000400 // Channel 2 Interrupt 1 Clear +#define FAN_IC_C2INT0IC 0x00000200 // Channel 2 Interrupt 0 Clear +#define FAN_IC_C2STALLIC 0x00000100 // Channel 2 Stall Interrupt Clear +#define FAN_IC_C1INT1IC 0x00000040 // Channel 1 Interrupt 1 Clear +#define FAN_IC_C1INT0IC 0x00000020 // Channel 1 Interrupt 0 Clear +#define FAN_IC_C1STALLIC 0x00000010 // Channel 1 Stall Interrupt Clear +#define FAN_IC_C0INT1IC 0x00000004 // Channel 0 Interrupt 1 Clear +#define FAN_IC_C0INT0IC 0x00000002 // Channel 0 Interrupt 0 Clear +#define FAN_IC_C0STALLIC 0x00000001 // Channel 0 Stall Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FAN_O_PP register. +// +//***************************************************************************** +#define FAN_PP_CHAN_M 0x0000000F // Channel Count +#define FAN_PP_CHAN_S 0 + +#endif // __HW_FAN_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_flash.h b/bsp/lm3s8962/Libraries/inc/hw_flash.h index 19b4c2b559..7a8c0697b3 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_flash.h +++ b/bsp/lm3s8962/Libraries/inc/hw_flash.h @@ -2,7 +2,7 @@ // // hw_flash.h - Macros used when accessing the flash controller. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -42,8 +42,10 @@ #define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid #define FLASH_FCTL 0x400FD0F8 // Flash Control #define FLASH_FWBN 0x400FD100 // Flash Write Buffer n +#define FLASH_FSIZE 0x400FDFC0 // Flash Size +#define FLASH_SSIZE 0x400FDFC4 // SRAM Size +#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map #define FLASH_RMCTL 0x400FE0F0 // ROM Control -#define FLASH_RMVER 0x400FE0F4 // ROM Version Register #define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read // Enable #define FLASH_FMPPE 0x400FE134 // Flash Memory Protection Program @@ -63,6 +65,14 @@ // Enable 2 #define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 #define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program // Enable 0 #define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program @@ -71,13 +81,21 @@ // Enable 2 #define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 //***************************************************************************** // // The following are defines for the bit fields in the FLASH_FMA register. // //***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset +#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset #define FLASH_FMA_OFFSET_S 0 //***************************************************************************** @@ -104,6 +122,12 @@ // The following are defines for the bit fields in the FLASH_FCRIS register. // //***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status #define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status #define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status @@ -112,6 +136,11 @@ // The following are defines for the bit fields in the FLASH_FCIM register. // //***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask #define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask #define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask @@ -120,6 +149,16 @@ // The following are defines for the bit fields in the FLASH_FCMISC register. // //***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear #define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt // Status and Clear #define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status @@ -155,6 +194,44 @@ //***************************************************************************** #define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash +#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash +#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash +#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash +#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash +#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash +#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM +#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM +#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM +#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM +#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM +#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM +#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM +#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present + //***************************************************************************** // // The following are defines for the bit fields in the FLASH_RMCTL register. @@ -162,27 +239,6 @@ //***************************************************************************** #define FLASH_RMCTL_BA 0x00000001 // Boot Alias -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RMVER register. -// -//***************************************************************************** -#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents -#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader & - // DriverLib -#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader & - // DriverLib with AES -#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \ - 0x03000000 // Stellaris Boot Loader & - // DriverLib with AES and SAFERTOS -#define FLASH_RMVER_CONT_LM_AES2 \ - 0x05000000 // Stellaris Boot Loader & - // DriverLib with AES -#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version -#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision -#define FLASH_RMVER_VER_S 8 -#define FLASH_RMVER_REV_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the FLASH_USECRL register. @@ -323,6 +379,13 @@ //***************************************************************************** #ifndef DEPRECATED +//***************************************************************************** +// +// The following are deprecated defines for the FLASH register offsets. +// +//***************************************************************************** +#define FLASH_RMVER 0x400FE0F4 // ROM Version Register + //***************************************************************************** // // The following are deprecated defines for the bit fields in the FLASH_FMC @@ -360,6 +423,28 @@ #define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status #define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_RMVER +// register. +// +//***************************************************************************** +#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents +#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader & + // DriverLib +#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader & + // DriverLib with AES +#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \ + 0x03000000 // Stellaris Boot Loader & + // DriverLib with AES and SAFERTOS +#define FLASH_RMVER_CONT_LM_AES2 \ + 0x05000000 // Stellaris Boot Loader & + // DriverLib with AES +#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version +#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision +#define FLASH_RMVER_VER_S 8 +#define FLASH_RMVER_REV_S 0 + //***************************************************************************** // // The following are deprecated defines for the bit fields in the FLASH_USECRL diff --git a/bsp/lm3s8962/Libraries/inc/hw_gpio.h b/bsp/lm3s8962/Libraries/inc/hw_gpio.h index 4558688f01..b2eaa072d9 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_gpio.h +++ b/bsp/lm3s8962/Libraries/inc/hw_gpio.h @@ -2,7 +2,7 @@ // // hw_gpio.h - Defines and Macros for GPIO hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -52,6 +52,9 @@ #define GPIO_O_CR 0x00000524 // GPIO Commit #define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select #define GPIO_O_PCTL 0x0000052C // GPIO Port Control +#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control +#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control +#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt //***************************************************************************** // @@ -70,460 +73,10 @@ //***************************************************************************** // -// The following are defines for the bit fields in the GPIO_PCTL register for -// port A. +// The following are defines for the bit fields in the GPIO_O_SI register. // //***************************************************************************** -#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask -#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 -#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0 -#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0 -#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask -#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 -#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1 -#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1 -#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask -#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2 -#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2 -#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2 -#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask -#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3 -#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3 -#define GPIO_PCTL_PA3_I2S0RXMCLK \ - 0x00009000 // I2S0RXMCLK on PA3 -#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask -#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4 -#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4 -#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4 -#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4 -#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask -#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5 -#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5 -#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5 -#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5 -#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask -#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6 -#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6 -#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6 -#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6 -#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6 -#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6 -#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6 -#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask -#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7 -#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7 -#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7 -#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7 -#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7 -#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7 -#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7 -#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port B. -// -//***************************************************************************** -#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask -#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0 -#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0 -#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0 -#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask -#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1 -#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1 -#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1 -#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1 -#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask -#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2 -#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2 -#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2 -#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2 -#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2 -#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask -#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3 -#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3 -#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3 -#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3 -#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask -#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4 -#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4 -#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4 -#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4 -#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4 -#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask -#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5 -#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5 -#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5 -#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5 -#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5 -#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5 -#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5 -#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5 -#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask -#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6 -#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6 -#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6 -#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6 -#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6 -#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6 -#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6 -#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask -#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port C. -// -//***************************************************************************** -#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask -#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0 -#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask -#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1 -#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask -#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2 -#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask -#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3 -#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask -#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4 -#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4 -#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4 -#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4 -#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4 -#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4 -#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4 -#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask -#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5 -#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5 -#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5 -#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5 -#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5 -#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5 -#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5 -#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask -#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6 -#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6 -#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6 -#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6 -#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6 -#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6 -#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6 -#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6 -#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask -#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7 -#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7 -#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7 -#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7 -#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7 -#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7 -#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port D. -// -//***************************************************************************** -#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask -#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0 -#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0 -#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0 -#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0 -#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0 -#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0 -#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0 -#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0 -#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask -#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1 -#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1 -#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1 -#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1 -#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1 -#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1 -#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1 -#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1 -#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1 -#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1 -#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask -#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2 -#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2 -#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2 -#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2 -#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2 -#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask -#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3 -#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3 -#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3 -#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3 -#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3 -#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask -#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4 -#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4 -#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4 -#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4 -#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4 -#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask -#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5 -#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5 -#define GPIO_PCTL_PD5_I2S0RXMCLK \ - 0x00800000 // I2S0RXMCLK on PD5 -#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5 -#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5 -#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask -#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6 -#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6 -#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6 -#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6 -#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask -#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7 -#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7 -#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7 -#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7 -#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7 -#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port E. -// -//***************************************************************************** -#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask -#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0 -#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0 -#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0 -#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0 -#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0 -#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask -#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1 -#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1 -#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1 -#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1 -#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1 -#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1 -#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask -#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2 -#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2 -#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2 -#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2 -#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2 -#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2 -#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask -#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3 -#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3 -#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3 -#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3 -#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3 -#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3 -#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask -#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4 -#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4 -#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4 -#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4 -#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4 -#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask -#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5 -#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5 -#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask -#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6 -#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6 -#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6 -#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask -#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7 -#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7 -#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port F. -// -//***************************************************************************** -#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask -#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0 -#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0 -#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0 -#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0 -#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0 -#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask -#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1 -#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1 -#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1 -#define GPIO_PCTL_PF1_I2S0TXMCLK \ - 0x00000080 // I2S0TXMCLK on PF1 -#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1 -#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1 -#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask -#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2 -#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2 -#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2 -#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2 -#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask -#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3 -#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3 -#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3 -#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3 -#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask -#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4 -#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4 -#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4 -#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4 -#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4 -#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask -#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5 -#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5 -#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5 -#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5 -#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask -#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6 -#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6 -#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6 -#define GPIO_PCTL_PF6_I2S0TXMCLK \ - 0x09000000 // I2S0TXMCLK on PF6 -#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6 -#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask -#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7 -#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7 -#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7 -#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port G. -// -//***************************************************************************** -#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask -#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0 -#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0 -#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0 -#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0 -#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0 -#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0 -#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask -#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1 -#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1 -#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1 -#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1 -#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1 -#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask -#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2 -#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2 -#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2 -#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2 -#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask -#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3 -#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3 -#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3 -#define GPIO_PCTL_PG3_I2S0RXMCLK \ - 0x00009000 // I2S0RXMCLK on PG3 -#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask -#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4 -#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4 -#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4 -#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4 -#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4 -#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask -#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5 -#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5 -#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5 -#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5 -#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5 -#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5 -#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask -#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6 -#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6 -#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6 -#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6 -#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6 -#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask -#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7 -#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7 -#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7 -#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port H. -// -//***************************************************************************** -#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask -#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0 -#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0 -#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0 -#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0 -#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask -#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1 -#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1 -#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1 -#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1 -#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask -#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2 -#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2 -#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2 -#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2 -#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask -#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3 -#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3 -#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3 -#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3 -#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask -#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4 -#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4 -#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4 -#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask -#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5 -#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5 -#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5 -#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask -#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6 -#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6 -#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6 -#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask -#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7 -#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7 -#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port J. -// -//***************************************************************************** -#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask -#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0 -#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0 -#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0 -#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask -#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1 -#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1 -#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1 -#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1 -#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask -#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2 -#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2 -#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2 -#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask -#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3 -#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3 -#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3 -#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask -#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4 -#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4 -#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4 -#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask -#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5 -#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5 -#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5 -#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask -#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6 -#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6 -#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6 -#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask -#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7 -#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7 +#define GPIO_SI_SUM 0x00000001 // Summary Interrupt //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/inc/hw_hibernate.h b/bsp/lm3s8962/Libraries/inc/hw_hibernate.h index 39a07e8a6b..46de994bc5 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_hibernate.h +++ b/bsp/lm3s8962/Libraries/inc/hw_hibernate.h @@ -2,7 +2,7 @@ // // hw_hibernate.h - Defines and Macros for the Hibernation module. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -41,6 +41,7 @@ // Status #define HIB_IC 0x400FC020 // Hibernation Interrupt Clear #define HIB_RTCT 0x400FC024 // Hibernation RTC Trim +#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds #define HIB_DATA 0x400FC030 // Hibernation Data //***************************************************************************** @@ -81,6 +82,17 @@ // //***************************************************************************** #define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_OSCHYS 0x00040000 // 32 +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery #define HIB_CTL_VDD3ON 0x00000100 // VDD Powered #define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable #define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable @@ -96,6 +108,8 @@ // The following are defines for the bit fields in the HIB_IM register. // //***************************************************************************** +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask #define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask #define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt // Mask @@ -107,6 +121,8 @@ // The following are defines for the bit fields in the HIB_RIS register. // //***************************************************************************** +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status #define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt // Status #define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw @@ -119,6 +135,8 @@ // The following are defines for the bit fields in the HIB_MIS register. // //***************************************************************************** +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status #define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked // Interrupt Status #define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked @@ -133,6 +151,8 @@ // The following are defines for the bit fields in the HIB_IC register. // //***************************************************************************** +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Clear #define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked // Interrupt Clear #define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked @@ -150,6 +170,16 @@ #define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value #define HIB_RTCT_TRIM_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the HIB_DATA register. diff --git a/bsp/lm3s8962/Libraries/inc/hw_i2c.h b/bsp/lm3s8962/Libraries/inc/hw_i2c.h index 22368b1737..dccfdafada 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_i2c.h +++ b/bsp/lm3s8962/Libraries/inc/hw_i2c.h @@ -2,7 +2,7 @@ // // hw_i2c.h - Macros used when accessing the I2C master and slave hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -47,7 +47,13 @@ #define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt // Status #define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear +#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2 #define I2C_O_MCR 0x00000020 // I2C Master Configuration +#define I2C_O_SACKCTL 0x00000020 // I2C ACK Control +#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout + // Count +#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor +#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties //***************************************************************************** // @@ -71,6 +77,9 @@ // The following are defines for the bit fields in the I2C_O_SCSR register. // //***************************************************************************** +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched #define I2C_SCSR_FBR 0x00000004 // First Byte Received #define I2C_SCSR_TREQ 0x00000002 // Transmit Request #define I2C_SCSR_DA 0x00000001 // Device Active @@ -81,9 +90,12 @@ // The following are defines for the bit fields in the I2C_O_MCS register. // //***************************************************************************** +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy #define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_QCMD 0x00000020 // Quick Command #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable #define I2C_MCS_DATACK 0x00000008 // Acknowledge Data #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address @@ -142,6 +154,7 @@ // The following are defines for the bit fields in the I2C_O_MIMR register. // //***************************************************************************** +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask #define I2C_MIMR_IM 0x00000001 // Interrupt Mask //***************************************************************************** @@ -149,6 +162,8 @@ // The following are defines for the bit fields in the I2C_O_MRIS register. // //***************************************************************************** +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status #define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status //***************************************************************************** @@ -176,6 +191,8 @@ // The following are defines for the bit fields in the I2C_O_MMIS register. // //***************************************************************************** +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status //***************************************************************************** @@ -183,8 +200,18 @@ // The following are defines for the bit fields in the I2C_O_MICR register. // //***************************************************************************** +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear #define I2C_MICR_IC 0x00000001 // Interrupt Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the I2C_O_MCR register. @@ -194,6 +221,37 @@ #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable #define I2C_MCR_LPBK 0x00000001 // I2C Loopback +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + //***************************************************************************** // // The following definitions are deprecated. diff --git a/bsp/lm3s8962/Libraries/inc/hw_i2s.h b/bsp/lm3s8962/Libraries/inc/hw_i2s.h index af9658252f..d139a79834 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_i2s.h +++ b/bsp/lm3s8962/Libraries/inc/hw_i2s.h @@ -2,7 +2,7 @@ // // hw_i2s.h - Macros for use in accessing the I2S registers. // -// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/inc/hw_ints.h b/bsp/lm3s8962/Libraries/inc/hw_ints.h index daa5917e85..e2becd15b8 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_ints.h +++ b/bsp/lm3s8962/Libraries/inc/hw_ints.h @@ -2,7 +2,7 @@ // // hw_ints.h - Macros that define the interrupt assignment on Stellaris. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -54,10 +54,10 @@ #define INT_UART1 22 // UART1 Rx and Tx #define INT_SSI0 23 // SSI0 Rx and Tx #define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 +#define INT_PWM0_FAULT 25 // PWM0 Fault +#define INT_PWM0_0 26 // PWM0 Generator 0 +#define INT_PWM0_1 27 // PWM0 Generator 1 +#define INT_PWM0_2 28 // PWM0 Generator 2 #define INT_QEI0 29 // Quadrature Encoder 0 #define INT_ADC0SS0 30 // ADC0 Sequence 0 #define INT_ADC0SS1 31 // ADC0 Sequence 1 @@ -90,7 +90,7 @@ #define INT_ETH 58 // Ethernet #define INT_HIBERNATE 59 // Hibernation module #define INT_USB0 60 // USB 0 Controller -#define INT_PWM3 61 // PWM Generator 3 +#define INT_PWM0_3 61 // PWM0 Generator 3 #define INT_UDMA 62 // uDMA controller #define INT_UDMAERR 63 // uDMA Error #define INT_ADC1SS0 64 // ADC1 Sequence 0 @@ -100,13 +100,69 @@ #define INT_I2S0 68 // I2S0 #define INT_EPI0 69 // EPI0 #define INT_GPIOJ 70 // GPIO Port J +#define INT_GPIOK 71 // GPIO Port K +#define INT_GPIOL 72 // GPIO Port L +#define INT_SSI2 73 // SSI2 +#define INT_SSI3 74 // SSI3 +#define INT_UART3 75 // UART3 +#define INT_UART4 76 // UART4 +#define INT_UART5 77 // UART5 +#define INT_UART6 78 // UART6 +#define INT_UART7 79 // UART7 +#define INT_I2C2 84 // I2C2 +#define INT_I2C3 85 // I2C3 +#define INT_TIMER4A 86 // Timer 4A +#define INT_TIMER4B 87 // Timer 4B +#define INT_TIMER5A 108 // Timer 5A +#define INT_TIMER5B 109 // Timer 5B +#define INT_WTIMER0A 110 // Wide Timer 0A +#define INT_WTIMER0B 111 // Wide Timer 0B +#define INT_WTIMER1A 112 // Wide Timer 1A +#define INT_WTIMER1B 113 // Wide Timer 1B +#define INT_WTIMER2A 114 // Wide Timer 2A +#define INT_WTIMER2B 115 // Wide Timer 2B +#define INT_WTIMER3A 116 // Wide Timer 3A +#define INT_WTIMER3B 117 // Wide Timer 3B +#define INT_WTIMER4A 118 // Wide Timer 4A +#define INT_WTIMER4B 119 // Wide Timer 4B +#define INT_WTIMER5A 120 // Wide Timer 5A +#define INT_WTIMER5B 121 // Wide Timer 5B +#define INT_SYSEXC 122 // System Exception (imprecise) +#define INT_PECI0 123 // PECI 0 +#define INT_LPC0 124 // LPC 0 +#define INT_I2C4 125 // I2C4 +#define INT_I2C5 126 // I2C5 +#define INT_GPIOM 127 // GPIO Port M +#define INT_GPION 128 // GPIO Port N +#define INT_FAN0 130 // FAN 0 +#define INT_GPIOP0 132 // GPIO Port P (Summary or P0) +#define INT_GPIOP1 133 // GPIO Port P1 +#define INT_GPIOP2 134 // GPIO Port P2 +#define INT_GPIOP3 135 // GPIO Port P3 +#define INT_GPIOP4 136 // GPIO Port P4 +#define INT_GPIOP5 137 // GPIO Port P5 +#define INT_GPIOP6 138 // GPIO Port P6 +#define INT_GPIOP7 139 // GPIO Port P7 +#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1 141 // GPIO Port Q1 +#define INT_GPIOQ2 142 // GPIO Port Q2 +#define INT_GPIOQ3 143 // GPIO Port Q3 +#define INT_GPIOQ4 144 // GPIO Port Q4 +#define INT_GPIOQ5 145 // GPIO Port Q5 +#define INT_GPIOQ6 146 // GPIO Port Q6 +#define INT_GPIOQ7 147 // GPIO Port Q7 +#define INT_PWM1_0 150 // PWM1 Generator 0 +#define INT_PWM1_1 151 // PWM1 Generator 1 +#define INT_PWM1_2 152 // PWM1 Generator 2 +#define INT_PWM1_3 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT 154 // PWM1 Fault //***************************************************************************** // // The following are defines for the total number of interrupts. // //***************************************************************************** -#define NUM_INTERRUPTS 71 +#define NUM_INTERRUPTS 155 //***************************************************************************** // @@ -130,11 +186,16 @@ //***************************************************************************** #define INT_SSI 23 // SSI Rx and Tx #define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 #define INT_QEI 29 // Quadrature Encoder #define INT_ADC0 30 // ADC Sequence 0 #define INT_ADC1 31 // ADC Sequence 1 #define INT_ADC2 32 // ADC Sequence 2 #define INT_ADC3 33 // ADC Sequence 3 +#define INT_PWM3 61 // PWM Generator 3 #endif diff --git a/bsp/lm3s8962/Libraries/inc/hw_lpc.h b/bsp/lm3s8962/Libraries/inc/hw_lpc.h new file mode 100644 index 0000000000..d39523f069 --- /dev/null +++ b/bsp/lm3s8962/Libraries/inc/hw_lpc.h @@ -0,0 +1,974 @@ +//***************************************************************************** +// +// hw_lpc.h - Macros used when accessing the LPC hardware. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_LPC_H__ +#define __HW_LPC_H__ + +//***************************************************************************** +// +// The following are defines for the LPC register addresses. +// +//***************************************************************************** +#define LPC_O_CTL 0x00000000 // LPC Control +#define LPC_O_STS 0x00000004 // LPC Status +#define LPC_O_IRQCTL 0x00000008 // LPC IRQ Control +#define LPC_O_IRQST 0x0000000C // LPC IRQ Status +#define LPC_O_CH0CTL 0x00000010 // LPC Channel 0 Control +#define LPC_O_CH0ST 0x00000014 // LPC Channel 0 Status +#define LPC_O_CH0ADR 0x00000018 // LPC Channel 0 Address +#define LPC_O_CH1CTL 0x00000020 // LPC Channel 1 Control +#define LPC_O_CH1ST 0x00000024 // LPC Channel 1 Status +#define LPC_O_CH1ADR 0x00000028 // LPC Channel 1 Address +#define LPC_O_CH2CTL 0x00000030 // LPC Channel 2 Control +#define LPC_O_CH2ST 0x00000034 // LPC Channel 2 Status +#define LPC_O_CH2ADR 0x00000038 // LPC Channel 2 Address +#define LPC_O_CH3CTL 0x00000040 // LPC Channel 3 Control +#define LPC_O_CH3ST 0x00000044 // LPC Channel 3 Status +#define LPC_O_CH3ADR 0x00000048 // LPC Channel 3 Address +#define LPC_O_CH4CTL 0x00000050 // LPC Channel 4 Control +#define LPC_O_CH4ST 0x00000054 // LPC Channel 4 Status +#define LPC_O_CH4ADR 0x00000058 // LPC Channel 4 Address +#define LPC_O_CH5CTL 0x00000060 // LPC Channel 5 Control +#define LPC_O_CH5ST 0x00000064 // LPC Channel 5 Status +#define LPC_O_CH5ADR 0x00000068 // LPC Channel 5 Address +#define LPC_O_CH6CTL 0x00000070 // LPC Channel 6 Control +#define LPC_O_CH6ST 0x00000074 // LPC Channel 6 Status +#define LPC_O_CH6ADR 0x00000078 // LPC Channel 6 Address +#define LPC_O_CH7CTL 0x00000080 // LPC Channel 7 / COMx Control +#define LPC_O_CH7ST 0x00000084 // LPC Channel 7 / COMx Status +#define LPC_O_CH7ADR 0x00000088 // LPC Channel 7 / COMx Address +#define LPC_O_STSADDR 0x000000A0 // LPC Status Block Address +#define LPC_O_IM 0x00000100 // LPC Interrupt Mask +#define LPC_O_RIS 0x00000104 // LPC Raw Interrupt Status +#define LPC_O_MIS 0x00000108 // LPC Masked Interrupt Status +#define LPC_O_IC 0x0000010C // LPC Interrupt Clear +#define LPC_O_DMACX 0x00000120 // LPC DMA and COMx Control +#define LPC_O_POOL 0x00000400 // LPC Register Pool +#define LPC_O_PP 0x00000FC0 // LPC Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CTL register. +// +//***************************************************************************** +#define LPC_CTL_SCICNT_M 0x00000C00 // LPC0SCI Pulse Length +#define LPC_CTL_SCICNT_0 0x00000000 // No pulse occurs on the LPC0SCI + // pin +#define LPC_CTL_SCICNT_2 0x00000400 // The pulse on the LPC0SCI pin is + // 2 LPC0CLK periods +#define LPC_CTL_SCICNT_4 0x00000800 // The pulse on the LPC0SCI pin is + // 4 LPC0CLK periods +#define LPC_CTL_SCICNT_8 0x00000C00 // The pulse on the LPC0SCI pin is + // 8 LPC0CLK periods +#define LPC_CTL_SCI 0x00000200 // Start SCI Pulse +#define LPC_CTL_WAKE 0x00000100 // Restart the LPC Bus +#define LPC_CTL_CE7 0x00000080 // Enable Channel 7 +#define LPC_CTL_CE6 0x00000040 // Enable Channel 6 +#define LPC_CTL_CE5 0x00000020 // Enable Channel 5 +#define LPC_CTL_CE4 0x00000010 // Enable Channel 4 +#define LPC_CTL_CE3 0x00000008 // Enable Channel 3 +#define LPC_CTL_CE2 0x00000004 // Enable Channel 2 +#define LPC_CTL_CE1 0x00000002 // Enable Channel 1 +#define LPC_CTL_CE0 0x00000001 // Enable Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_STS register. +// +//***************************************************************************** +#define LPC_STS_CHCNT_M 0x00700000 // Number of Channels +#define LPC_STS_POOLSZ_M 0x00070000 // Register Pool Size +#define LPC_STS_POOLSZ_256 0x00010000 // 256 bytes +#define LPC_STS_POOLSZ_512 0x00020000 // 512 bytes +#define LPC_STS_POOLSZ_768 0x00030000 // 768 bytes +#define LPC_STS_POOLSZ_1024 0x00040000 // 1024 bytes +#define LPC_STS_RST 0x00000400 // LPC is in Reset +#define LPC_STS_BUSY 0x00000200 // LPC is Busy +#define LPC_STS_SLEEP 0x00000100 // LPC is in Sleep Mode +#define LPC_STS_CA7 0x00000080 // Channel 7 Active +#define LPC_STS_CA6 0x00000040 // Channel 6 Active +#define LPC_STS_CA5 0x00000020 // Channel 5 Active +#define LPC_STS_CA4 0x00000010 // Channel 4 Active +#define LPC_STS_CA3 0x00000008 // Channel 3 Active +#define LPC_STS_CA2 0x00000004 // Channel 2 Active +#define LPC_STS_CA1 0x00000002 // Channel 1 Active +#define LPC_STS_CA0 0x00000001 // Channel 0 Active +#define LPC_STS_CHCNT_S 20 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_IRQCTL register. +// +//***************************************************************************** +#define LPC_IRQCTL_I15 0x80000000 // Manual IRQ15 State +#define LPC_IRQCTL_I14 0x40000000 // Manual IRQ14 State +#define LPC_IRQCTL_I13 0x20000000 // Manual IRQ13 State +#define LPC_IRQCTL_I12 0x10000000 // Manual IRQ12 State +#define LPC_IRQCTL_I11 0x08000000 // Manual IRQ11 State +#define LPC_IRQCTL_I10 0x04000000 // Manual IRQ10 State +#define LPC_IRQCTL_I9 0x02000000 // Manual IRQ9 State +#define LPC_IRQCTL_I8 0x01000000 // Manual IRQ8 State +#define LPC_IRQCTL_I7 0x00800000 // Manual IRQ7 State +#define LPC_IRQCTL_I6 0x00400000 // Manual IRQ6 State +#define LPC_IRQCTL_I5 0x00200000 // Manual IRQ5 State +#define LPC_IRQCTL_I4 0x00100000 // Manual IRQ4 State +#define LPC_IRQCTL_I3 0x00080000 // Manual IRQ3 State +#define LPC_IRQCTL_I2 0x00040000 // Manual IRQ2 State +#define LPC_IRQCTL_I1 0x00020000 // Manual IRQ1 State +#define LPC_IRQCTL_AH 0x00010000 // Active High Control +#define LPC_IRQCTL_PULSE 0x00000004 // Pulse IRQ States +#define LPC_IRQCTL_ONCHG 0x00000002 // Initiate on Change +#define LPC_IRQCTL_SND 0x00000001 // Initiate Immediately + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_IRQST register. +// +//***************************************************************************** +#define LPC_IRQST_I15 0x80000000 // Host IRQ15 State +#define LPC_IRQST_I14 0x40000000 // IRQ14 State +#define LPC_IRQST_I13 0x20000000 // IRQ13 State +#define LPC_IRQST_I12 0x10000000 // IRQ12 State +#define LPC_IRQST_I11 0x08000000 // IRQ11 State +#define LPC_IRQST_I10 0x04000000 // IRQ10 State +#define LPC_IRQST_I9 0x02000000 // IRQ9 State +#define LPC_IRQST_I8 0x01000000 // IRQ8 State +#define LPC_IRQST_I7 0x00800000 // IRQ7 State +#define LPC_IRQST_I6 0x00400000 // IRQ6 State +#define LPC_IRQST_I5 0x00200000 // IRQ5 State +#define LPC_IRQST_I4 0x00100000 // IRQ4 State +#define LPC_IRQST_I3 0x00080000 // IRQ3 State +#define LPC_IRQST_I2 0x00040000 // IRQ2 State +#define LPC_IRQST_I1 0x00020000 // IRQ1 State +#define LPC_IRQST_I0 0x00010000 // IRQ0 State +#define LPC_IRQST_SIRQ 0x00000004 // Pulse IRQ States +#define LPC_IRQST_CONT 0x00000001 // Initiate Immediately + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH0CTL register. +// +//***************************************************************************** +#define LPC_CH0CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH0CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH0CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH0CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH0CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH0CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH0CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH0CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH0CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH0CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 +#define LPC_CH0CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH0CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH0CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH0CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH0CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH0CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH0CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH0CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH0CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH0CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH0CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH0CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH0CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH0CTL_IRQSEL2_S 28 +#define LPC_CH0CTL_IRQSEL1_S 24 +#define LPC_CH0CTL_IRQSEL0_S 20 +#define LPC_CH0CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH0ST register. +// +//***************************************************************************** +#define LPC_CH0ST_USER_M 0x00001F00 // User Data +#define LPC_CH0ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH0ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH0ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH0ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH0ST_CMD 0x00000008 // Command or Data +#define LPC_CH0ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH0ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH0ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH0ADR register. +// +//***************************************************************************** +#define LPC_CH0ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH0ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH0ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 +#define LPC_CH0ADR_ADDRH_S 16 +#define LPC_CH0ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH1CTL register. +// +//***************************************************************************** +#define LPC_CH1CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH1CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH1CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH1CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH1CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH1CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH1CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH1CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH1CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH1CTL_IRQEN0_TRGI2 0x00020000 // Trigger 2 +#define LPC_CH1CTL_IRQEN0_TRGI3 0x00030000 // Trigger 3 +#define LPC_CH1CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH1CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH1CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH1CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH1CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH1CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH1CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH1CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH1CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH1CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH1CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH1CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH1CTL_IRQSEL2_S 28 +#define LPC_CH1CTL_IRQSEL1_S 24 +#define LPC_CH1CTL_IRQSEL0_S 20 +#define LPC_CH1CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH1ST register. +// +//***************************************************************************** +#define LPC_CH1ST_USER_M 0x00001F00 // User Data +#define LPC_CH1ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH1ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH1ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH1ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH1ST_CMD 0x00000008 // Command or Data +#define LPC_CH1ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH1ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH1ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH1ADR register. +// +//***************************************************************************** +#define LPC_CH1ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH1ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH1ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 +#define LPC_CH1ADR_ADDRH_S 16 +#define LPC_CH1ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH2CTL register. +// +//***************************************************************************** +#define LPC_CH2CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH2CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH2CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH2CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH2CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH2CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH2CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH2CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH2CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH2CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 +#define LPC_CH2CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH2CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH2CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH2CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH2CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH2CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH2CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH2CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH2CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH2CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH2CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH2CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH2CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH2CTL_IRQSEL2_S 28 +#define LPC_CH2CTL_IRQSEL1_S 24 +#define LPC_CH2CTL_IRQSEL0_S 20 +#define LPC_CH2CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH2ST register. +// +//***************************************************************************** +#define LPC_CH2ST_USER_M 0x00001F00 // User Data +#define LPC_CH2ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH2ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH2ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH2ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH2ST_CMD 0x00000008 // Command or Data +#define LPC_CH2ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH2ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH2ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH2ADR register. +// +//***************************************************************************** +#define LPC_CH2ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH2ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH2ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 +#define LPC_CH2ADR_ADDRH_S 16 +#define LPC_CH2ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH3CTL register. +// +//***************************************************************************** +#define LPC_CH3CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH3CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH3CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH3CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH3CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH3CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH3CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH3CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH3CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH3CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 +#define LPC_CH3CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH3CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH3CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH3CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH3CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH3CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH3CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH3CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH3CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH3CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH3CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH3CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH3CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH3CTL_IRQSEL2_S 28 +#define LPC_CH3CTL_IRQSEL1_S 24 +#define LPC_CH3CTL_IRQSEL0_S 20 +#define LPC_CH3CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH3ST register. +// +//***************************************************************************** +#define LPC_CH3ST_USER_M 0x00001F00 // User Data +#define LPC_CH3ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH3ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH3ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH3ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH3ST_CMD 0x00000008 // Command or Data +#define LPC_CH3ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH3ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH3ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH3ADR register. +// +//***************************************************************************** +#define LPC_CH3ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH3ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH3ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 +#define LPC_CH3ADR_ADDRH_S 16 +#define LPC_CH3ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH4CTL register. +// +//***************************************************************************** +#define LPC_CH4CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH4CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH4CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH4CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH4CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH4CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH4CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH4CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH4CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH4CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 +#define LPC_CH4CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH4CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH4CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH4CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH4CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH4CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH4CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH4CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH4CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH4CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH4CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH4CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH4CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH4CTL_IRQSEL2_S 28 +#define LPC_CH4CTL_IRQSEL1_S 24 +#define LPC_CH4CTL_IRQSEL0_S 20 +#define LPC_CH4CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH4ST register. +// +//***************************************************************************** +#define LPC_CH4ST_USER_M 0x00001F00 // User Data +#define LPC_CH4ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH4ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH4ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH4ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH4ST_CMD 0x00000008 // Command or Data +#define LPC_CH4ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH4ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH4ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH4ADR register. +// +//***************************************************************************** +#define LPC_CH4ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH4ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH4ADR_ADDRH_S 16 +#define LPC_CH4ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH5CTL register. +// +//***************************************************************************** +#define LPC_CH5CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH5CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH5CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH5CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH5CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH5CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH5CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH5CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH5CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH5CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 +#define LPC_CH5CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH5CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH5CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH5CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH5CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH5CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH5CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH5CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH5CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH5CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH5CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH5CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH5CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH5CTL_IRQSEL2_S 28 +#define LPC_CH5CTL_IRQSEL1_S 24 +#define LPC_CH5CTL_IRQSEL0_S 20 +#define LPC_CH5CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH5ST register. +// +//***************************************************************************** +#define LPC_CH5ST_USER_M 0x00001F00 // User Data +#define LPC_CH5ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH5ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH5ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH5ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH5ST_CMD 0x00000008 // Command or Data +#define LPC_CH5ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH5ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH5ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH5ADR register. +// +//***************************************************************************** +#define LPC_CH5ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH5ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH5ADR_ADDRH_S 16 +#define LPC_CH5ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH6CTL register. +// +//***************************************************************************** +#define LPC_CH6CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH6CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH6CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH6CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH6CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH6CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH6CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH6CTL_IRQEN0_DIS 0x00000000 // Trigger disabled +#define LPC_CH6CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 +#define LPC_CH6CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 +#define LPC_CH6CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH6CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH6CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH6CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH6CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH6CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH6CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH6CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH6CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH6CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH6CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH6CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH6CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH6CTL_IRQSEL2_S 28 +#define LPC_CH6CTL_IRQSEL1_S 24 +#define LPC_CH6CTL_IRQSEL0_S 20 +#define LPC_CH6CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH6ST register. +// +//***************************************************************************** +#define LPC_CH6ST_USER_M 0x00001F00 // User Data +#define LPC_CH6ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH6ST_HW1ST 0x00000040 // First Host Write +#define LPC_CH6ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH6ST_SW1ST 0x00000010 // First Slave Write +#define LPC_CH6ST_CMD 0x00000008 // Command or Data +#define LPC_CH6ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH6ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH6ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH6ADR register. +// +//***************************************************************************** +#define LPC_CH6ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH6ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH6ADR_ADDRH_S 16 +#define LPC_CH6ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH7CTL register. +// +//***************************************************************************** +#define LPC_CH7CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 +#define LPC_CH7CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 +#define LPC_CH7CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 +#define LPC_CH7CTL_CX 0x00080000 // IRQ Enable 2 +#define LPC_CH7CTL_IRQEN2 0x00080000 // IRQ Enable 2 +#define LPC_CH7CTL_IRQEN1 0x00040000 // IRQ Enable 1 +#define LPC_CH7CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 +#define LPC_CH7CTL_IRQEN0_AUTO 0x00000000 // The automatic IRQ trigger is + // disabled +#define LPC_CH7CTL_IRQEN0_MST 0x00010000 // If TYPE is set, the IRQ selected + // by IRQSEL0 is triggered when the + // master wins arbitration (the + // HW1ST bit is set) +#define LPC_CH7CTL_IRQEN0_SLV 0x00020000 // If TYPE is set, the IRQ selected + // by IRQSEL0 is triggered when the + // slave wins arbitration (the + // SW1ST bit is set) +#define LPC_CH7CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 +#define LPC_CH7CTL_ARBDIS 0x00008000 // Arbitration Disabled +#define LPC_CH7CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool +#define LPC_CH7CTL_AMASK_M 0x0000001C // Address Mask for Ranges +#define LPC_CH7CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox + // size of 4 bytes for an endpoint + // range or used for single + // endpoints +#define LPC_CH7CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox + // size of 8 bytes +#define LPC_CH7CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox + // size of 16 bytes +#define LPC_CH7CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox + // size of 32 bytes +#define LPC_CH7CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox + // size of 64 bytes +#define LPC_CH7CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox + // size of 128 bytes +#define LPC_CH7CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox + // size of 256 bytes +#define LPC_CH7CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox + // size of 512 bytes +#define LPC_CH7CTL_TYPE 0x00000001 // Channel Type +#define LPC_CH7CTL_IRQSEL2_S 28 +#define LPC_CH7CTL_IRQSEL1_S 24 +#define LPC_CH7CTL_IRQSEL0_S 20 +#define LPC_CH7CTL_OFFSET_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH7ST register. +// +//***************************************************************************** +#define LPC_CH7ST_USER_M 0x00001F00 // User Data +#define LPC_CH7ST_LASTHW 0x00000080 // Last Host Write +#define LPC_CH7ST_HW1ST 0x00000040 // Host Wrote First +#define LPC_CH7ST_LASTSW 0x00000020 // Last Slave Write +#define LPC_CH7ST_SW1ST 0x00000010 // Slave Wrote First +#define LPC_CH7ST_CMD 0x00000008 // Command or Data +#define LPC_CH7ST_FRMH 0x00000002 // From-Host Transaction +#define LPC_CH7ST_TOH 0x00000001 // To-Host Transaction +#define LPC_CH7ST_USER_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_CH7ADR register. +// +//***************************************************************************** +#define LPC_CH7ADR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_CH7ADR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_CH7ADR_ADDRH_S 16 +#define LPC_CH7ADR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_STSADDR register. +// +//***************************************************************************** +#define LPC_STSADDR_ADDRH_M 0xFFFF0000 // Upper Address Match +#define LPC_STSADDR_ADDRL_M 0x0000FFF8 // Lower Address Match +#define LPC_STSADDR_ENA 0x00000001 // Enable Status Block +#define LPC_STSADDR_ADDRH_S 16 +#define LPC_STSADDR_ADDRL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_IM register. +// +//***************************************************************************** +#define LPC_IM_RSTIM 0x80000000 // Reset State Interrupt Mask +#define LPC_IM_SLEEPIM 0x40000000 // Sleep State Interrupt Mask +#define LPC_IM_COMXIM 0x20000000 // COMx Interrupt Mask +#define LPC_IM_SIRQIM 0x10000000 // SERIRQ Frame Complete Interrupt + // Mask +#define LPC_IM_CH6IM3 0x08000000 // Channel 6 Interrupt Mask 3 +#define LPC_IM_CH6IM2 0x04000000 // Channel 6 Interrupt Mask 2 +#define LPC_IM_CH6IM1 0x02000000 // Channel 6 Interrupt Mask 1 +#define LPC_IM_CH6IM0 0x01000000 // Channel 6 Interrupt Mask 0 +#define LPC_IM_CH5IM3 0x00800000 // Channel 5 Interrupt Mask 3 +#define LPC_IM_CH5IM2 0x00400000 // Channel 5 Interrupt Mask 2 +#define LPC_IM_CH5IM1 0x00200000 // Channel 5 Interrupt Mask 1 +#define LPC_IM_CH5IM0 0x00100000 // Channel 5 Interrupt Mask 0 +#define LPC_IM_CH4IM3 0x00080000 // Channel 4 Interrupt Mask 3 +#define LPC_IM_CH4IM2 0x00040000 // Channel 4 Interrupt Mask 2 +#define LPC_IM_CH4IM1 0x00020000 // Channel 4 Interrupt Mask 1 +#define LPC_IM_CH4IM0 0x00010000 // Channel 4 Interrupt Mask 0 +#define LPC_IM_CH3IM3 0x00008000 // Channel 3 Interrupt Mask 3 +#define LPC_IM_CH3IM2 0x00004000 // Channel 3 Interrupt Mask 2 +#define LPC_IM_CH3IM1 0x00002000 // Channel 3 Interrupt Mask 1 +#define LPC_IM_CH3IM0 0x00001000 // Channel 3 Interrupt Mask 0 +#define LPC_IM_CH2IM3 0x00000800 // Channel 2 Interrupt Mask 3 +#define LPC_IM_CH2IM2 0x00000400 // Channel 2 Interrupt Mask 2 +#define LPC_IM_CH2IM1 0x00000200 // Channel 2 Interrupt Mask 1 +#define LPC_IM_CH2IM0 0x00000100 // Channel 2 Interrupt Mask 0 +#define LPC_IM_CH1IM3 0x00000080 // Channel 1 Interrupt Mask 3 +#define LPC_IM_CH1IM2 0x00000040 // Channel 1 Interrupt Mask 2 +#define LPC_IM_CH1IM1 0x00000020 // Channel 1 Interrupt Mask 1 +#define LPC_IM_CH1IM0 0x00000010 // Channel 1 Interrupt Mask 0 +#define LPC_IM_CH0IM3 0x00000008 // Channel 0 Interrupt Mask 3 +#define LPC_IM_CH0IM2 0x00000004 // Channel 0 Interrupt Mask 2 +#define LPC_IM_CH0IM1 0x00000002 // Channel 0 Interrupt Mask 1 +#define LPC_IM_CH0IM0 0x00000001 // Channel 0 Interrupt Mask 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_RIS register. +// +//***************************************************************************** +#define LPC_RIS_RSTRIS 0x80000000 // Reset State Raw Interrupt Status +#define LPC_RIS_SLEEPRIS 0x40000000 // Sleep State Raw Interrupt Status +#define LPC_RIS_COMXRIS 0x20000000 // COMx Raw Interrupt Status +#define LPC_RIS_SIRQRIS 0x10000000 // SERIRQ Frame Complete Raw + // Interrupt Status +#define LPC_RIS_CH6RIS3 0x08000000 // Channel 6 Raw Interrupt Status 3 +#define LPC_RIS_CH6RIS2 0x04000000 // Channel 6 Raw Interrupt Status 2 +#define LPC_RIS_CH6RIS1 0x02000000 // Channel 6 Raw Interrupt Status 1 +#define LPC_RIS_CH6RIS0 0x01000000 // Channel 6 Raw Interrupt Status 0 +#define LPC_RIS_CH5RIS3 0x00800000 // Channel 5 Raw Interrupt Status 3 +#define LPC_RIS_CH5RIS2 0x00400000 // Channel 5 Raw Interrupt Status 2 +#define LPC_RIS_CH5RIS1 0x00200000 // Channel 5 Raw Interrupt Status 1 +#define LPC_RIS_CH5RIS0 0x00100000 // Channel 5 Raw Interrupt Status 0 +#define LPC_RIS_CH4RIS3 0x00080000 // Channel 4 Raw Interrupt Status 3 +#define LPC_RIS_CH4RIS2 0x00040000 // Channel 4 Raw Interrupt Status 2 +#define LPC_RIS_CH4RIS1 0x00020000 // Channel 4 Raw Interrupt Status 1 +#define LPC_RIS_CH4RIS0 0x00010000 // Channel 4 Raw Interrupt Status 0 +#define LPC_RIS_CH3RIS3 0x00008000 // Channel 3 Raw Interrupt Status 3 +#define LPC_RIS_CH3RIS2 0x00004000 // Channel 3 Raw Interrupt Status 2 +#define LPC_RIS_CH3RIS1 0x00002000 // Channel 3 Raw Interrupt Status 1 +#define LPC_RIS_CH3RIS0 0x00001000 // Channel 3 Raw Interrupt Status 0 +#define LPC_RIS_CH2RIS3 0x00000800 // Channel 2 Raw Interrupt Status 3 +#define LPC_RIS_CH2RIS2 0x00000400 // Channel 2 Raw Interrupt Status 2 +#define LPC_RIS_CH2RIS1 0x00000200 // Channel 2 Raw Interrupt Status 1 +#define LPC_RIS_CH2RIS0 0x00000100 // Channel 2 Raw Interrupt Status 0 +#define LPC_RIS_CH1RIS3 0x00000080 // Channel 1 Raw Interrupt Status 3 +#define LPC_RIS_CH1RIS2 0x00000040 // Channel 1 Raw Interrupt Status 2 +#define LPC_RIS_CH1RIS1 0x00000020 // Channel 1 Raw Interrupt Status 1 +#define LPC_RIS_CH1RIS0 0x00000010 // Channel 1 Raw Interrupt Status 0 +#define LPC_RIS_CH0RIS3 0x00000008 // Channel 0 Raw Interrupt Status 3 +#define LPC_RIS_CH0RIS2 0x00000004 // Channel 0 Raw Interrupt Status 2 +#define LPC_RIS_CH0RIS1 0x00000002 // Channel 0 Raw Interrupt Status 1 +#define LPC_RIS_CH0RIS0 0x00000001 // Channel 0 Raw Interrupt Status 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_MIS register. +// +//***************************************************************************** +#define LPC_MIS_RSTMIS 0x80000000 // Reset State Masked Interrupt + // Status +#define LPC_MIS_SLEEPMIS 0x40000000 // Sleep State Masked Interrupt + // Status +#define LPC_MIS_COMXMIS 0x20000000 // COMx Masked Interrupt Status +#define LPC_MIS_SIRQMIS 0x10000000 // SERIRQ Frame Complete Masked + // Interrupt Status +#define LPC_MIS_CH6MIS3 0x08000000 // Channel 6 Masked Interrupt + // Status 3 +#define LPC_MIS_CH6MIS2 0x04000000 // Channel 6 Masked Interrupt + // Status 2 +#define LPC_MIS_CH6MIS1 0x02000000 // Channel 6 Masked Interrupt + // Status 1 +#define LPC_MIS_CH6MIS0 0x01000000 // Channel 6 Masked Interrupt + // Status 0 +#define LPC_MIS_CH5MIS3 0x00800000 // Channel 5 Masked Interrupt + // Status 3 +#define LPC_MIS_CH5MIS2 0x00400000 // Channel 5 Masked Interrupt + // Status 2 +#define LPC_MIS_CH5MIS1 0x00200000 // Channel 5 Masked Interrupt + // Status 1 +#define LPC_MIS_CH5MIS0 0x00100000 // Channel 5 Masked Interrupt + // Status 0 +#define LPC_MIS_CH4MIS3 0x00080000 // Channel 4 Masked Interrupt + // Status 3 +#define LPC_MIS_CH4MIS2 0x00040000 // Channel 4 Masked Interrupt + // Status 2 +#define LPC_MIS_CH4MIS1 0x00020000 // Channel 4 Masked Interrupt + // Status 1 +#define LPC_MIS_CH4MIS0 0x00010000 // Channel 4 Masked Interrupt + // Status 0 +#define LPC_MIS_CH3MIS3 0x00008000 // Channel 3 Masked Interrupt + // Status 3 +#define LPC_MIS_CH3MIS2 0x00004000 // Channel 3 Masked Interrupt + // Status 2 +#define LPC_MIS_CH3MIS1 0x00002000 // Channel 3 Masked Interrupt + // Status 1 +#define LPC_MIS_CH3MIS0 0x00001000 // Channel 3 Masked Interrupt + // Status 0 +#define LPC_MIS_CH2MIS3 0x00000800 // Channel 2 Masked Interrupt + // Status 3 +#define LPC_MIS_CH2MIS2 0x00000400 // Channel 2 Masked Interrupt + // Status 2 +#define LPC_MIS_CH2MIS1 0x00000200 // Channel 2 Masked Interrupt + // Status 1 +#define LPC_MIS_CH2MIS0 0x00000100 // Channel 2 Masked Interrupt + // Status 0 +#define LPC_MIS_CH1MIS3 0x00000080 // Channel 1 Masked Interrupt + // Status 3 +#define LPC_MIS_CH1MIS2 0x00000040 // Channel 1 Masked Interrupt + // Status 2 +#define LPC_MIS_CH1MIS1 0x00000020 // Channel 1 Masked Interrupt + // Status 1 +#define LPC_MIS_CH1MIS0 0x00000010 // Channel 1 Masked Interrupt + // Status 0 +#define LPC_MIS_CH0MIS3 0x00000008 // Channel 0 Masked Interrupt + // Status 3 +#define LPC_MIS_CH0MIS2 0x00000004 // Channel 0 Masked Interrupt + // Status 2 +#define LPC_MIS_CH0MIS1 0x00000002 // Channel 0 Masked Interrupt + // Status 1 +#define LPC_MIS_CH0MIS0 0x00000001 // Channel 0 Masked Interrupt + // Status 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_IC register. +// +//***************************************************************************** +#define LPC_IC_RSTIC 0x80000000 // Reset State Interrupt Clear +#define LPC_IC_SLEEPIC 0x40000000 // Sleep State Interrupt Clear +#define LPC_IC_COMXIC 0x20000000 // COMx Interrupt Clear +#define LPC_IC_SIRQRIC 0x10000000 // SERIRQ Frame Complete Interrupt + // Clear +#define LPC_IC_CH6IC3 0x08000000 // Channel 6 Interrupt Clear 3 +#define LPC_IC_CH6IC2 0x04000000 // Channel 6 Interrupt Clear 2 +#define LPC_IC_CH6IC1 0x02000000 // Channel 6 Interrupt Clear 1 +#define LPC_IC_CH6IC0 0x01000000 // Channel 6 Interrupt Clear 0 +#define LPC_IC_CH5IC3 0x00800000 // Channel 5 Interrupt Clear 3 +#define LPC_IC_CH5IC2 0x00400000 // Channel 5 Interrupt Clear 2 +#define LPC_IC_CH5IC1 0x00200000 // Channel 5 Interrupt Clear 1 +#define LPC_IC_CH5IC0 0x00100000 // Channel 5 Interrupt Clear 0 +#define LPC_IC_CH4IC3 0x00080000 // Channel 4 Interrupt Clear 3 +#define LPC_IC_CH4IC2 0x00040000 // Channel 4 Interrupt Clear 2 +#define LPC_IC_CH4IC1 0x00020000 // Channel 4 Interrupt Clear 1 +#define LPC_IC_CH4IC0 0x00010000 // Channel 4 Interrupt Clear 0 +#define LPC_IC_CH3IC3 0x00008000 // Channel 3 Interrupt Clear 3 +#define LPC_IC_CH3IC2 0x00004000 // Channel 3 Interrupt Clear 2 +#define LPC_IC_CH3IC1 0x00002000 // Channel 3 Interrupt Clear 1 +#define LPC_IC_CH3IC0 0x00001000 // Channel 3 Interrupt Clear 0 +#define LPC_IC_CH2IC3 0x00000800 // Channel 2 Interrupt Clear 3 +#define LPC_IC_CH2IC2 0x00000400 // Channel 2 Interrupt Clear 2 +#define LPC_IC_CH2IC1 0x00000200 // Channel 2 Interrupt Clear 1 +#define LPC_IC_CH2IC0 0x00000100 // Channel 2 Interrupt Clear 0 +#define LPC_IC_CH1IC3 0x00000080 // Channel 1 Interrupt Clear 3 +#define LPC_IC_CH1IC2 0x00000040 // Channel 1 Interrupt Clear 2 +#define LPC_IC_CH1IC1 0x00000020 // Channel 1 Interrupt Clear 1 +#define LPC_IC_CH1IC0 0x00000010 // Channel 1 Interrupt Clear 0 +#define LPC_IC_CH0IC3 0x00000008 // Channel 0 Interrupt Clear 3 +#define LPC_IC_CH0IC2 0x00000004 // Channel 0 Interrupt Clear 2 +#define LPC_IC_CH0IC1 0x00000002 // Channel 0 Interrupt Clear 1 +#define LPC_IC_CH0IC0 0x00000001 // Channel 0 Interrupt Clear 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_DMACX register. +// +//***************************************************************************** +#define LPC_DMACX_CXRES 0x02000000 // Raw Event State for COMx +#define LPC_DMACX_CXTXRES 0x01000000 // Raw Event State for COMx TX +#define LPC_DMACX_CXRXRES 0x00800000 // Raw Event State for COMx RX +#define LPC_DMACX_CXEM 0x00200000 // Event Mask for COMx +#define LPC_DMACX_CXTXEM 0x00100000 // Event Mask for COMx TX +#define LPC_DMACX_CXRXEM 0x00080000 // Event Mask for COMx RX +#define LPC_DMACX_CXACT_M 0x00060000 // COMx Action +#define LPC_DMACX_CXACT_FRMHNML 0x00000000 // Treat as normal FRMH model and + // let be full (and so marked as + // full) +#define LPC_DMACX_CXACT_FRMHIGN 0x00020000 // Ignore FRMH bytes and continue + // to mark FRMH as empty +#define LPC_DMACX_CXACT_FRMHDMA 0x00040000 // COMx DMA on FRMH byte (e.g. to + // memory) +#define LPC_DMACX_CXACT_UARTDMA 0x00060000 // COMx DMA model with UART +#define LPC_DMACX_COMX 0x00010000 // COMx Handling +#define LPC_DMACX_C3W 0x00000080 // Write Control for Channel 3 +#define LPC_DMACX_C3R 0x00000040 // Read Control for Channel 3 +#define LPC_DMACX_C2W 0x00000020 // Write Control for Channel 2 +#define LPC_DMACX_C2R 0x00000010 // Read Control for Channel 2 +#define LPC_DMACX_C1W 0x00000008 // Write Control for Channel 1 +#define LPC_DMACX_C1R 0x00000004 // Read Control for Channel 1 +#define LPC_DMACX_C0W 0x00000002 // Write Control for Channel 0 +#define LPC_DMACX_C0R 0x00000001 // Read Control for Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_POOL register. +// +//***************************************************************************** +#define LPC_POOL_BYTE3_M 0xFF000000 // Byte 3 +#define LPC_POOL_BYTE2_M 0x00FF0000 // Byte 2 +#define LPC_POOL_BYTE1_M 0x0000FF00 // Byte 1 +#define LPC_POOL_BYTE0_M 0x000000FF // Byte 0 +#define LPC_POOL_BYTE3_S 24 +#define LPC_POOL_BYTE2_S 16 +#define LPC_POOL_BYTE1_S 8 +#define LPC_POOL_BYTE0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LPC_O_PP register. +// +//***************************************************************************** +#define LPC_PP_COMX 0x00000010 // COMx Support Available +#define LPC_PP_CHANCNT_M 0x0000000F // Number of Channels (Excluding + // COMx) +#define LPC_PP_CHANCNT_S 0 + +#endif // __HW_LPC_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_memmap.h b/bsp/lm3s8962/Libraries/inc/hw_memmap.h index 04d75f729b..1a50ad9f2b 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_memmap.h +++ b/bsp/lm3s8962/Libraries/inc/hw_memmap.h @@ -2,7 +2,7 @@ // // hw_memmap.h - Macros defining the memory map of Stellaris. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -41,24 +41,40 @@ #define GPIO_PORTD_BASE 0x40007000 // GPIO Port D #define SSI0_BASE 0x40008000 // SSI0 #define SSI1_BASE 0x40009000 // SSI1 +#define SSI2_BASE 0x4000A000 // SSI2 +#define SSI3_BASE 0x4000B000 // SSI3 #define UART0_BASE 0x4000C000 // UART0 #define UART1_BASE 0x4000D000 // UART1 #define UART2_BASE 0x4000E000 // UART2 +#define UART3_BASE 0x4000F000 // UART3 +#define UART4_BASE 0x40010000 // UART4 +#define UART5_BASE 0x40011000 // UART5 +#define UART6_BASE 0x40012000 // UART6 +#define UART7_BASE 0x40013000 // UART7 #define I2C0_MASTER_BASE 0x40020000 // I2C0 Master #define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave #define I2C1_MASTER_BASE 0x40021000 // I2C1 Master #define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave +#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master +#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave +#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master +#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave #define GPIO_PORTE_BASE 0x40024000 // GPIO Port E #define GPIO_PORTF_BASE 0x40025000 // GPIO Port F #define GPIO_PORTG_BASE 0x40026000 // GPIO Port G #define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM +#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) +#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) #define QEI0_BASE 0x4002C000 // QEI0 #define QEI1_BASE 0x4002D000 // QEI1 #define TIMER0_BASE 0x40030000 // Timer0 #define TIMER1_BASE 0x40031000 // Timer1 #define TIMER2_BASE 0x40032000 // Timer2 #define TIMER3_BASE 0x40033000 // Timer3 +#define TIMER4_BASE 0x40034000 // Timer4 +#define TIMER5_BASE 0x40035000 // Timer5 +#define WTIMER0_BASE 0x40036000 // Wide Timer0 +#define WTIMER1_BASE 0x40037000 // Wide Timer1 #define ADC0_BASE 0x40038000 // ADC0 #define ADC1_BASE 0x40039000 // ADC1 #define COMP_BASE 0x4003C000 // Analog comparators @@ -68,6 +84,10 @@ #define CAN2_BASE 0x40042000 // CAN2 #define ETH_BASE 0x40048000 // Ethernet #define MAC_BASE 0x40048000 // Ethernet +#define WTIMER2_BASE 0x4004C000 // Wide Timer2 +#define WTIMER3_BASE 0x4004D000 // Wide Timer3 +#define WTIMER4_BASE 0x4004E000 // Wide Timer4 +#define WTIMER5_BASE 0x4004F000 // Wide Timer5 #define USB0_BASE 0x40050000 // USB 0 Controller #define I2S0_BASE 0x40054000 // I2S0 #define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) @@ -79,7 +99,23 @@ #define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) #define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) #define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K +#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L +#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M +#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N +#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P +#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q +#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC) +#define FAN0_BASE 0x40084000 // Fan Control (FAN) +#define EEPROM_BASE 0x400AF000 // EEPROM memory +#define PECI0_BASE 0x400B0000 // Platform Environment Control + // Interface (PECI) +#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master +#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave +#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master +#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave #define EPI0_BASE 0x400D0000 // EPI0 +#define SYSEXC_BASE 0x400F9000 // System Exception Module #define HIB_BASE 0x400FC000 // Hibernation Module #define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller #define SYSCTL_BASE 0x400FE000 // System Control @@ -107,6 +143,7 @@ #define SSI_BASE 0x40008000 // SSI #define I2C_MASTER_BASE 0x40020000 // I2C Master #define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define PWM_BASE 0x40028000 // PWM #define QEI_BASE 0x4002C000 // QEI #define ADC_BASE 0x40038000 // ADC diff --git a/bsp/lm3s8962/Libraries/inc/hw_nvic.h b/bsp/lm3s8962/Libraries/inc/hw_nvic.h index da01d3ec14..cdb06304b8 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_nvic.h +++ b/bsp/lm3s8962/Libraries/inc/hw_nvic.h @@ -2,7 +2,7 @@ // // hw_nvic.h - Macros used when accessing the NVIC hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -31,59 +31,110 @@ // //***************************************************************************** #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register -#define NVIC_PRI12 0xE000E430 // IRQ 48 to 51 Priority Register -#define NVIC_PRI13 0xE000E434 // IRQ 52 to 55 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control +#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address +#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status + // Control //***************************************************************************** // @@ -93,22 +144,35 @@ #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) #define NVIC_INT_TYPE_LINES_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_CTRL register. // //***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_RELOAD register. // //***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value #define NVIC_ST_RELOAD_S 0 //***************************************************************************** @@ -117,7 +181,7 @@ // register. // //***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value #define NVIC_ST_CURRENT_S 0 //***************************************************************************** @@ -135,540 +199,962 @@ // The following are defines for the bit fields in the NVIC_EN0 register. // //***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN1 register. // //***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS0 register. // //***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS1 register. // //***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND0 register. // //***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND1 register. // //***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND0 register. // //***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND1 register. // //***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE0 register. // //***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE1 register. // //***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI0 register. // //***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI1 register. // //***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI2 register. // //***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI3 register. // //***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI4 register. // //***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI5 register. // //***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI6 register. // //***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI7 register. // //***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI8 register. // //***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI9 register. // //***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI10 register. // //***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CPUID register. // //***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_CTRL register. // //***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // Set pending SysTick interrupt -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // Clear pending SysTick interrupt -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_S 12 #define NVIC_INT_CTRL_VEC_ACT_S 0 @@ -677,19 +1163,19 @@ // The following are defines for the bit fields in the NVIC_VTABLE register. // //***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_APINT register. // //***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split @@ -698,65 +1184,64 @@ #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_CTRL register. // //***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CFG_CTRL register. // //***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. // //***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. // //***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. // //***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 //***************************************************************************** // @@ -764,18 +1249,21 @@ // register. // //***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active //***************************************************************************** // @@ -783,23 +1271,30 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation //***************************************************************************** // @@ -807,9 +1302,9 @@ // register. // //***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault //***************************************************************************** // @@ -828,7 +1323,7 @@ // The following are defines for the bit fields in the NVIC_MM_ADDR register. // //***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address #define NVIC_MM_ADDR_S 0 //***************************************************************************** @@ -837,17 +1332,33 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address #define NVIC_FAULT_ADDR_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + //***************************************************************************** // // The following are defines for the bit fields in the NVIC_MPU_TYPE register. // //***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU #define NVIC_MPU_TYPE_IREGION_S 16 #define NVIC_MPU_TYPE_DREGION_S 8 @@ -856,9 +1367,9 @@ // The following are defines for the bit fields in the NVIC_MPU_CTRL register. // //***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable //***************************************************************************** // @@ -866,7 +1377,7 @@ // register. // //***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access #define NVIC_MPU_NUMBER_S 0 //***************************************************************************** @@ -874,10 +1385,10 @@ // The following are defines for the bit fields in the NVIC_MPU_BASE register. // //***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 #define NVIC_MPU_BASE_REGION_S 0 //***************************************************************************** @@ -886,19 +1397,19 @@ // //***************************************************************************** #define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask -#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits #define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable #define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable #define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable @@ -907,7 +1418,7 @@ #define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable #define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable #define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes @@ -936,7 +1447,94 @@ #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable //***************************************************************************** // @@ -1020,7 +1618,47 @@ // The following are defines for the bit fields in the NVIC_SW_TRIG register. // //***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID #define NVIC_SW_TRIG_INTID_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + #endif // __HW_NVIC_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_peci.h b/bsp/lm3s8962/Libraries/inc/hw_peci.h new file mode 100644 index 0000000000..012a0c821e --- /dev/null +++ b/bsp/lm3s8962/Libraries/inc/hw_peci.h @@ -0,0 +1,375 @@ +//***************************************************************************** +// +// hw_peci.h - Macros used when accessing the PECI hardware. +// +// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_PECI_H__ +#define __HW_PECI_H__ + +//***************************************************************************** +// +// The following are defines for the PECI register addresses. +// +//***************************************************************************** +#define PECI_O_CTL 0x00000000 // PECI Control +#define PECI_O_DIV 0x00000004 // PECI Poll-Rate Divider +#define PECI_O_CMP 0x00000008 // PECI Comparator +#define PECI_O_M0D0C 0x00000010 // PECI Microprocessor 0 / Domain 0 + // Control +#define PECI_O_M0D1C 0x00000014 // PECI Microprocessor 0 / Domain 1 + // Control +#define PECI_O_M1D0C 0x00000018 // PECI Microprocessor 1 / Domain 0 + // Control +#define PECI_O_M1D1C 0x0000001C // PECI Microprocessor 1 / Domain 1 + // Control +#define PECI_O_M0D0 0x00000040 // PECI Microprocessor 0 / Domain 0 + // Value +#define PECI_O_M0D1 0x00000044 // PECI Microprocessor 0 / Domain 1 + // Value +#define PECI_O_M1D0 0x00000048 // PECI Microprocessor 1 / Domain 0 + // Value +#define PECI_O_M1D1 0x0000004C // PECI Microprocessor 1 / Domain 1 + // Value +#define PECI_O_IM 0x00000080 // PECI Interrupt Mask +#define PECI_O_RIS 0x00000084 // PECI Raw Interrupt Status +#define PECI_O_MIS 0x00000088 // PECI Masked Interrupt Status +#define PECI_O_IC 0x0000008C // PECI Interrupt Clear +#define PECI_O_ACADDR 0x00000100 // PECI Advanced Command Address +#define PECI_O_ACARG 0x00000104 // PECI Advanced Command Argument +#define PECI_O_ACRDWR0 0x00000108 // PECI Advanced Command Data 0 +#define PECI_O_ACRDWR1 0x0000010C // PECI Advanced Command Data 1 +#define PECI_O_ACCMD 0x00000110 // PECI Advanced Command +#define PECI_O_ACCODE 0x00000114 // PECI Advanced Command Completion + // Code + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_CTL register. +// +//***************************************************************************** +#define PECI_CTL_OFFSET_M 0xFFFF0000 // Offset Value +#define PECI_CTL_CRETRY_M 0x00007000 // Number of Controller Retries +#define PECI_CTL_BYERR 0x00000800 // Number of Retries +#define PECI_CTL_RXINV 0x00000400 // Invert PECI RX Input +#define PECI_CTL_M1D1EN 0x00000008 // Enable Microprocessor 1 and + // Domain 1 +#define PECI_CTL_M1D0EN 0x00000004 // Enable Microprocessor 1 and + // Domain 0 +#define PECI_CTL_M0D1EN 0x00000002 // Enable Microprocessor 0 and + // Domain 1 +#define PECI_CTL_M0D0EN 0x00000001 // Enable Microprocessor 0 and + // Domain 0 +#define PECI_CTL_OFFSET_S 16 +#define PECI_CTL_CRETRY_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_DIV register. +// +//***************************************************************************** +#define PECI_DIV_BAUD_M 0xFFFF0000 // Initial Baud Rate +#define PECI_DIV_POLL_M 0x0000FFFF // Counter for Inter-Poll Delay +#define PECI_DIV_BAUD_S 16 +#define PECI_DIV_POLL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_CMP register. +// +//***************************************************************************** +#define PECI_CMP_VREF_M 0x00000007 // Resistor Ladder Voltage Ref +#define PECI_CMP_VREF_0_5000V 0x00000000 // 0.5000 +#define PECI_CMP_VREF_0_5125V 0x00000001 // 0.5125 +#define PECI_CMP_VREF_0_5250V 0x00000002 // 0.5250 +#define PECI_CMP_VREF_0_5375V 0x00000003 // 0.5375 +#define PECI_CMP_VREF_0_5500V 0x00000004 // 0.5500 +#define PECI_CMP_VREF_0_5625V 0x00000005 // 0.5625 +#define PECI_CMP_VREF_0_6000V 0x00000006 // 0.6000 +#define PECI_CMP_VREF_0_6625V 0x00000007 // 0.6625 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M0D0C register. +// +//***************************************************************************** +#define PECI_M0D0C_HITHR_M 0xFFFF0000 // High Threshold +#define PECI_M0D0C_LOTHR_M 0x0000FFFF // Low Threshold +#define PECI_M0D0C_HITHR_S 16 +#define PECI_M0D0C_LOTHR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M0D1C register. +// +//***************************************************************************** +#define PECI_M0D1C_HITHR_M 0xFFFF0000 // High Threshold +#define PECI_M0D1C_LOTHR_M 0x0000FFFF // Low Threshold +#define PECI_M0D1C_HITHR_S 16 +#define PECI_M0D1C_LOTHR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M1D0C register. +// +//***************************************************************************** +#define PECI_M1D0C_HITHR_M 0xFFFF0000 // High Threshold +#define PECI_M1D0C_LOTHR_M 0x0000FFFF // Low Threshold +#define PECI_M1D0C_HITHR_S 16 +#define PECI_M1D0C_LOTHR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M1D1C register. +// +//***************************************************************************** +#define PECI_M1D1C_HITHR_M 0xFFFF0000 // High Threshold +#define PECI_M1D1C_LOTHR_M 0x0000FFFF // Low Threshold +#define PECI_M1D1C_HITHR_S 16 +#define PECI_M1D1C_LOTHR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M0D0 register. +// +//***************************************************************************** +#define PECI_M0D0_MAXREAD_M 0xFFFF0000 // Highest Value Read +#define PECI_M0D0_VALUE_M 0x0000FFFF // Last Value Read +#define PECI_M0D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error + // on transmitted data +#define PECI_M0D0_VALUE_CRCRX 0x000081FA // CRC error on received data +#define PECI_M0D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data +#define PECI_M0D0_VALUE_NEG 0x000081FC // Negotiation error +#define PECI_M0D0_VALUE_TO 0x000081FD // Timeout error +#define PECI_M0D0_MAXREAD_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M0D1 register. +// +//***************************************************************************** +#define PECI_M0D1_MAXREAD_M 0xFFFF0000 // Highest Value Read +#define PECI_M0D1_VALUE_M 0x0000FFFF // Last Value Read +#define PECI_M0D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error + // on transmitted data +#define PECI_M0D1_VALUE_CRCRX 0x000081FA // CRC error on received data +#define PECI_M0D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data +#define PECI_M0D1_VALUE_NEG 0x000081FC // Negotiation error +#define PECI_M0D1_VALUE_TO 0x000081FD // Timeout error +#define PECI_M0D1_MAXREAD_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M1D0 register. +// +//***************************************************************************** +#define PECI_M1D0_MAXREAD_M 0xFFFF0000 // Highest Value Read +#define PECI_M1D0_VALUE_M 0x0000FFFF // Last Value Read +#define PECI_M1D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error + // on transmitted data +#define PECI_M1D0_VALUE_CRCRX 0x000081FA // CRC error on received data +#define PECI_M1D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data +#define PECI_M1D0_VALUE_NEG 0x000081FC // Negotiation error +#define PECI_M1D0_VALUE_TO 0x000081FD // Timeout error +#define PECI_M1D0_MAXREAD_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_M1D1 register. +// +//***************************************************************************** +#define PECI_M1D1_MAXREAD_M 0xFFFF0000 // Highest Value Read +#define PECI_M1D1_VALUE_M 0x0000FFFF // Last Value Read +#define PECI_M1D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error + // on transmitted data +#define PECI_M1D1_VALUE_CRCRX 0x000081FA // CRC error on received data +#define PECI_M1D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data +#define PECI_M1D1_VALUE_NEG 0x000081FC // Negotiation error +#define PECI_M1D1_VALUE_TO 0x000081FD // Timeout error +#define PECI_M1D1_MAXREAD_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_IM register. +// +//***************************************************************************** +#define PECI_IM_M1D1IM_M 0x00C00000 // Microprocessor 1 and Domain 1 + // Interrupt Mask +#define PECI_IM_M1D1IM_HIGH 0x00400000 // Interrupt when value is above + // high threshold +#define PECI_IM_M1D1IM_CROSSUP 0x00800000 // Interrupt when crossing above + // either threshold +#define PECI_IM_M1D1IM_CROSSANY 0x00C00000 // Interrupt when crossing either + // threshold in either direction +#define PECI_IM_M1D0IM_M 0x00300000 // Microprocessor 1 and Domain 0 + // Interrupt Mask +#define PECI_IM_M0D1IM_M 0x000C0000 // Microprocessor 0 and Domain 1 + // Interrupt Mask +#define PECI_IM_M0D0IM_M 0x00030000 // Microprocessor 0 and Domain 0 + // Interrupt Mask +#define PECI_IM_ACIM 0x00000004 // Advanced Command Interrupt Mask +#define PECI_IM_ERRIM 0x00000002 // Error Detected Interrupt Mask +#define PECI_IM_POLLIM 0x00000001 // Poll Completed Interrupt Mask +#define PECI_IM_M1D0IM_S 20 +#define PECI_IM_M0D1IM_S 18 +#define PECI_IM_M0D0IM_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_RIS register. +// +//***************************************************************************** +#define PECI_RIS_M1D1RIS_M 0x00C00000 // Microprocessor 1 and Domain 1 + // Raw Interrupt Status +#define PECI_RIS_M1D0RIS_M 0x00300000 // Microprocessor 1 and Domain 0 + // Raw Interrupt Status +#define PECI_RIS_M0D1RIS_M 0x000C0000 // Microprocessor 0 and Domain 1 + // Raw Interrupt Status +#define PECI_RIS_M0D0RIS_M 0x00030000 // Microprocessor 0 and Domain 0 + // Raw Interrupt Status +#define PECI_RIS_ACRIS 0x00000004 // Advanced Command Raw Interrupt + // Status +#define PECI_RIS_ERRRIS 0x00000002 // Error Detected Raw Interrupt + // Status +#define PECI_RIS_POLLRIS 0x00000001 // Poll Completed Raw Interrupt + // Status +#define PECI_RIS_M1D1RIS_S 22 +#define PECI_RIS_M1D0RIS_S 20 +#define PECI_RIS_M0D1RIS_S 18 +#define PECI_RIS_M0D0RIS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_MIS register. +// +//***************************************************************************** +#define PECI_MIS_M1D1MIS_M 0x00C00000 // Microprocessor 1 and Domain 1 + // Masked Interrupt Status +#define PECI_MIS_M1D0MIS_M 0x00300000 // Microprocessor 1 and Domain 0 + // Masked Interrupt Status +#define PECI_MIS_M0D1MIS_M 0x000C0000 // Microprocessor 0 and Domain 1 + // Masked Interrupt Status +#define PECI_MIS_M0D0MIS_M 0x00030000 // Microprocessor 0 and Domain 0 + // Masked Interrupt Status +#define PECI_MIS_ACMIS 0x00000004 // Advanced Command Masked + // Interrupt Status +#define PECI_MIS_ERRMIS 0x00000002 // Error Detected Masked Interrupt + // Status +#define PECI_MIS_POLLMIS 0x00000001 // Poll Completed Masked Interrupt + // Status +#define PECI_MIS_M1D1MIS_S 22 +#define PECI_MIS_M1D0MIS_S 20 +#define PECI_MIS_M0D1MIS_S 18 +#define PECI_MIS_M0D0MIS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_IC register. +// +//***************************************************************************** +#define PECI_IC_M1D1IC_M 0x00C00000 // Microprocessor 1 and Domain 1 + // Interrupt Clear +#define PECI_IC_M1D0IC_M 0x00300000 // Microprocessor 1 and Domain 0 + // Interrupt Clear +#define PECI_IC_M0D1IC_M 0x000C0000 // Microprocessor 0 and Domain 1 + // Interrupt Clear +#define PECI_IC_M0D0IC_M 0x00030000 // Microprocessor 0 and Domain 0 + // Interrupt Clear +#define PECI_IC_ACIC 0x00000004 // Advanced Command Interrupt Clear +#define PECI_IC_ERRIC 0x00000002 // Error Detected Interrupt Clear +#define PECI_IC_POLLIC 0x00000001 // Poll Completed Interrupt Clear +#define PECI_IC_M1D1IC_S 22 +#define PECI_IC_M1D0IC_S 20 +#define PECI_IC_M0D1IC_S 18 +#define PECI_IC_M0D0IC_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_ACADDR register. +// +//***************************************************************************** +#define PECI_ACADDR_HIDRE_M 0xFF000000 // HostID and Retry +#define PECI_ACADDR_SIZE_M 0x00FF0000 // Size Override +#define PECI_ACADDR_DOMAIN_M 0x0000FF00 // Domain Select +#define PECI_ACADDR_PROCADD_M 0x000000FF // Processor Address +#define PECI_ACADDR_HIDRE_S 24 +#define PECI_ACADDR_SIZE_S 16 +#define PECI_ACADDR_DOMAIN_S 8 +#define PECI_ACADDR_PROCADD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_ACARG register. +// +//***************************************************************************** +#define PECI_ACARG_ARG3_M 0xFF000000 // Argument 3 +#define PECI_ACARG_ARG2_M 0x00FF0000 // Argument 2 +#define PECI_ACARG_ARG1_M 0x0000FF00 // Argument 1 +#define PECI_ACARG_ARG0_M 0x000000FF // Argument 0 +#define PECI_ACARG_ARG3_S 24 +#define PECI_ACARG_ARG2_S 16 +#define PECI_ACARG_ARG1_S 8 +#define PECI_ACARG_ARG0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_ACRDWR0 register. +// +//***************************************************************************** +#define PECI_ACRDWR0_D3_M 0xFF000000 // Data 3 +#define PECI_ACRDWR0_D2_M 0x00FF0000 // Data 2 +#define PECI_ACRDWR0_D1_M 0x0000FF00 // Data 1 +#define PECI_ACRDWR0_D0_M 0x000000FF // Data 0 +#define PECI_ACRDWR0_D3_S 24 +#define PECI_ACRDWR0_D2_S 16 +#define PECI_ACRDWR0_D1_S 8 +#define PECI_ACRDWR0_D0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_ACRDWR1 register. +// +//***************************************************************************** +#define PECI_ACRDWR1_D3_M 0xFF000000 // Data 3 +#define PECI_ACRDWR1_D2_M 0x00FF0000 // Data 2 +#define PECI_ACRDWR1_D1_M 0x0000FF00 // Data 1 +#define PECI_ACRDWR1_D0_M 0x000000FF // Data 0 +#define PECI_ACRDWR1_D3_S 24 +#define PECI_ACRDWR1_D2_S 16 +#define PECI_ACRDWR1_D1_S 8 +#define PECI_ACRDWR1_D0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_ACCMD register. +// +//***************************************************************************** +#define PECI_ACCMD_CMD_M 0x000000FF // Base Command +#define PECI_ACCMD_CMD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PECI_O_ACCODE register. +// +//***************************************************************************** +#define PECI_ACCODE_CODE_M 0xFFFFFFFF // Signed Completion Code + +#endif // __HW_PECI_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_pwm.h b/bsp/lm3s8962/Libraries/inc/hw_pwm.h index 2e7e41ac1d..82d55e9198 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_pwm.h +++ b/bsp/lm3s8962/Libraries/inc/hw_pwm.h @@ -2,7 +2,7 @@ // // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -125,6 +125,8 @@ #define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense #define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 #define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 +#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties +#define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration //***************************************************************************** // @@ -594,6 +596,33 @@ #define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger #define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_GCNT_S 0 +#define PWM_PP_FCNT_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PC register. +// +//***************************************************************************** +#define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor +#define PWM_PC_PWMDIV_2 0x00000000 // /2 +#define PWM_PC_PWMDIV_4 0x00000001 // /4 +#define PWM_PC_PWMDIV_8 0x00000002 // /8 +#define PWM_PC_PWMDIV_16 0x00000003 // /16 +#define PWM_PC_PWMDIV_32 0x00000004 // /32 +#define PWM_PC_PWMDIV_64 0x00000007 // /64 (default) +#define PWM_PC_USEOPWMDIV 0x00000100 // Enable PWM Clock Divisor + //***************************************************************************** // // The following are defines for the PWM Generator standard offsets. diff --git a/bsp/lm3s8962/Libraries/inc/hw_qei.h b/bsp/lm3s8962/Libraries/inc/hw_qei.h index 22a4811fd5..0348852ffe 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_qei.h +++ b/bsp/lm3s8962/Libraries/inc/hw_qei.h @@ -2,7 +2,7 @@ // // hw_qei.h - Macros used when accessing the QEI hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm3s8962/Libraries/inc/hw_ssi.h b/bsp/lm3s8962/Libraries/inc/hw_ssi.h index 9a5bc99ae3..40be6a6de3 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_ssi.h +++ b/bsp/lm3s8962/Libraries/inc/hw_ssi.h @@ -2,7 +2,7 @@ // // hw_ssi.h - Macros used when accessing the SSI hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -40,6 +40,7 @@ #define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status #define SSI_O_ICR 0x00000020 // SSI Interrupt Clear #define SSI_O_DMACTL 0x00000024 // SSI DMA Control +#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration //***************************************************************************** // @@ -167,6 +168,17 @@ #define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable #define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the + // PLL bypass is in effect) or the + // PLL output (default) +#define SSI_CC_CS_PIOSC 0x00000001 // PIOSC + //***************************************************************************** // // The following definitions are deprecated. diff --git a/bsp/lm3s8962/Libraries/inc/hw_sysctl.h b/bsp/lm3s8962/Libraries/inc/hw_sysctl.h index ffc63e7a9f..34ae0b5f21 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_sysctl.h +++ b/bsp/lm3s8962/Libraries/inc/hw_sysctl.h @@ -2,7 +2,7 @@ // // hw_sysctl.h - Macros used when accessing the system control hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -54,7 +54,6 @@ #define SYSCTL_RESC 0x400FE05C // Reset Cause #define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration #define SYSCTL_PLLCFG 0x400FE064 // XTAL to PLL Translation -#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High-Speed Control #define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus // Control #define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 @@ -78,17 +77,280 @@ #define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating // Control Register 2 #define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration -#define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear +#define SYSCTL_SYSPROP 0x400FE14C // System Properties #define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator // Calibration +#define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear #define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator // Statistics #define SYSCTL_LDOARST 0x400FE160 // Allow Unregulated LDO to Reset // the Part +#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 +#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency +#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status #define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration #define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC // Digital Comparators #define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information +#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral + // Present +#define SYSCTL_PPTIMER 0x400FE304 // Timer Peripheral Present +#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output + // Peripheral Present +#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access + // Peripheral Present +#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present +#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Present +#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface + // Peripheral Present +#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit + // Peripheral Present +#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral + // Present +#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network + // Peripheral Present +#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter + // Peripheral Present +#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral + // Present +#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral + // Present +#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface + // Peripheral Present +#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface + // Peripheral Present +#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control + // Interface Peripheral Present +#define SYSCTL_PPFAN 0x400FE354 // FAN Peripheral Present +#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present +#define SYSCTL_PPWTIMER 0x400FE35C // Wide Timer Peripheral Present +#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset +#define SYSCTL_SRTIMER 0x400FE504 // Timer Software Reset +#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output + // Software Reset +#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access + // Software Reset +#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset +#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous + // Receiver/Transmitter Software + // Reset +#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface + // Software Reset +#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit + // Software Reset +#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software + // Reset +#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software + // Reset +#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter + // Software Reset +#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset +#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software + // Reset +#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface + // Software Reset +#define SYSCTL_SRLPC 0x400FE548 // Low Pin Count Interface Software + // Reset +#define SYSCTL_SRPECI 0x400FE550 // Platform Environment Control + // Interface Software Reset +#define SYSCTL_SRFAN 0x400FE554 // FAN Software Reset +#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset +#define SYSCTL_SRWTIMER 0x400FE55C // Wide Timer Software Reset +#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock + // Gating Control +#define SYSCTL_RCGCTIMER 0x400FE604 // Timer Run Mode Clock Gating + // Control +#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run + // Mode Clock Gating Control +#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run + // Mode Clock Gating Control +#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous + // Receiver/Transmitter Run Mode + // Clock Gating Control +#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run + // Mode Clock Gating Control +#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode + // Clock Gating Control +#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode + // Clock Gating Control +#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run + // Mode Clock Gating Control +#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode + // Clock Gating Control +#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCLPC 0x400FE648 // Low Pin Count Interface Run Mode + // Clock Gating Control +#define SYSCTL_RCGCPECI 0x400FE650 // Platform Environment Control + // Interface Run Mode Clock Gating + // Control +#define SYSCTL_RCGCFAN 0x400FE654 // FAN Run Mode Clock Gating + // Control +#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER 0x400FE65C // Wide Timer Run Mode Clock Gating + // Control +#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCTIMER 0x400FE704 // Timer Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous + // Receiver/Transmitter Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCLPC 0x400FE748 // Low Pin Count Interface Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCPECI 0x400FE750 // Platform Environment Control + // Interface Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCFAN 0x400FE754 // FAN Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER 0x400FE75C // Wide Timer Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCTIMER 0x400FE804 // Timer Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous + // Receiver/Transmitter Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCLPC 0x400FE848 // Low Pin Count Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCPECI 0x400FE850 // Platform Environment Control + // Interface Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCFAN 0x400FE854 // FAN Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER 0x400FE85C // Wide Timer Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control +#define SYSCTL_PCTIMER 0x400FE904 // Timer Power Control +#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output + // Power Control +#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power + // Control +#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control +#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous + // Receiver/Transmitter Power + // Control +#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface + // Power Control +#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power + // Control +#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power + // Control +#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power + // Control +#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter + // Power Control +#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control +#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power + // Control +#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface + // Power Control +#define SYSCTL_PCLPC 0x400FE948 // Low Pin Count Interface Power + // Control +#define SYSCTL_PCPECI 0x400FE950 // Platform Environment Control + // Interface Power Control +#define SYSCTL_PCFAN 0x400FE954 // Fan Power Control +#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control +#define SYSCTL_PCWTIMER 0x400FE95C // Wide Timer Power Control +#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready +#define SYSCTL_PRTIMER 0x400FEA04 // Timer Peripheral Ready +#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output + // Peripheral Ready +#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access + // Peripheral Ready +#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready +#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Ready +#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface + // Peripheral Ready +#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit + // Peripheral Ready +#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral + // Ready +#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network + // Peripheral Ready +#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter + // Peripheral Ready +#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral + // Ready +#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral + // Ready +#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface + // Peripheral Ready +#define SYSCTL_PRLPC 0x400FEA48 // Low Pin Count Interface + // Peripheral Ready +#define SYSCTL_PRPECI 0x400FEA50 // Platform Environment Control + // Interface Peripheral Ready +#define SYSCTL_PRFAN 0x400FEA54 // FAN Peripheral Ready +#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready +#define SYSCTL_PRWTIMER 0x400FEA5C // Wide Timer Peripheral Ready //***************************************************************************** // @@ -111,6 +373,12 @@ #define SYSCTL_DID0_CLASS_TEMPEST \ 0x00040000 // Stellaris(R) Tempest-class // microcontrollers +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Stellaris(R) Blizzard-class + // microcontrollers +#define SYSCTL_DID0_CLASS_FIRESTORM \ + 0x00060000 // Stellaris(R) Firestorm-class + // microcontrollers #define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision #define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) #define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer @@ -180,6 +448,7 @@ #define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 #define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 #define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 +#define SYSCTL_DID1_PRTNO_1166 0x00EC0000 // LM3S1166 #define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 #define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 #define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 @@ -189,10 +458,12 @@ #define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607 #define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608 #define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 +#define SYSCTL_DID1_PRTNO_1621 0x00CD0000 // LM3S1621 #define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625 #define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626 #define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627 #define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 +#define SYSCTL_DID1_PRTNO_1636 0x00EB0000 // LM3S1636 #define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 #define SYSCTL_DID1_PRTNO_1651 0x00B10000 // LM3S1651 #define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 @@ -206,14 +477,29 @@ #define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 #define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 #define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 +#define SYSCTL_DID1_PRTNO_1969 0x00EA0000 // LM3S1969 +#define SYSCTL_DID1_PRTNO_1B21 0x00CE0000 // LM3S1B21 +#define SYSCTL_DID1_PRTNO_1C21 0x00CA0000 // LM3S1C21 +#define SYSCTL_DID1_PRTNO_1C26 0x00CB0000 // LM3S1C26 +#define SYSCTL_DID1_PRTNO_1C58 0x00980000 // LM3S1C58 +#define SYSCTL_DID1_PRTNO_1D21 0x00B00000 // LM3S1D21 +#define SYSCTL_DID1_PRTNO_1D26 0x00CC0000 // LM3S1D26 +#define SYSCTL_DID1_PRTNO_1F11 0x001D0000 // LM3S1F11 +#define SYSCTL_DID1_PRTNO_1F16 0x001B0000 // LM3S1F16 +#define SYSCTL_DID1_PRTNO_1G21 0x00AF0000 // LM3S1G21 +#define SYSCTL_DID1_PRTNO_1G58 0x00950000 // LM3S1G58 +#define SYSCTL_DID1_PRTNO_1H11 0x001E0000 // LM3S1H11 +#define SYSCTL_DID1_PRTNO_1H16 0x001C0000 // LM3S1H16 #define SYSCTL_DID1_PRTNO_1J11 0x000F0000 // LM3S1J11 #define SYSCTL_DID1_PRTNO_1J16 0x003C0000 // LM3S1J16 #define SYSCTL_DID1_PRTNO_1N11 0x000E0000 // LM3S1N11 #define SYSCTL_DID1_PRTNO_1N16 0x003B0000 // LM3S1N16 #define SYSCTL_DID1_PRTNO_1P51 0x00B20000 // LM3S1P51 #define SYSCTL_DID1_PRTNO_1R21 0x009E0000 // LM3S1R21 +#define SYSCTL_DID1_PRTNO_1R26 0x00C90000 // LM3S1R26 #define SYSCTL_DID1_PRTNO_1W16 0x00300000 // LM3S1W16 #define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 // LM3S1Z16 +#define SYSCTL_DID1_PRTNO_2016 0x00D40000 // LM3S2016 #define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 #define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 #define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276 @@ -235,13 +521,17 @@ #define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793 #define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911 #define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918 +#define SYSCTL_DID1_PRTNO_2919 0x00ED0000 // LM3S2919 #define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 #define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 #define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 #define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 #define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93 +#define SYSCTL_DID1_PRTNO_2D93 0x00940000 // LM3S2D93 +#define SYSCTL_DID1_PRTNO_2U93 0x00930000 // LM3S2U93 #define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634 #define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651 +#define SYSCTL_DID1_PRTNO_3654 0x00C80000 // LM3S3654 #define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739 #define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748 #define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749 @@ -266,15 +556,28 @@ #define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951 #define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956 #define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91 +#define SYSCTL_DID1_PRTNO_5C31 0x002E0000 // LM3S5C31 +#define SYSCTL_DID1_PRTNO_5C36 0x002C0000 // LM3S5C36 +#define SYSCTL_DID1_PRTNO_5C51 0x005E0000 // LM3S5C51 +#define SYSCTL_DID1_PRTNO_5C56 0x005B0000 // LM3S5C56 +#define SYSCTL_DID1_PRTNO_5D51 0x005F0000 // LM3S5D51 +#define SYSCTL_DID1_PRTNO_5D56 0x005C0000 // LM3S5D56 +#define SYSCTL_DID1_PRTNO_5D91 0x00870000 // LM3S5D91 +#define SYSCTL_DID1_PRTNO_5G31 0x002D0000 // LM3S5G31 +#define SYSCTL_DID1_PRTNO_5G36 0x001F0000 // LM3S5G36 +#define SYSCTL_DID1_PRTNO_5G51 0x005D0000 // LM3S5G51 +#define SYSCTL_DID1_PRTNO_5G56 0x004F0000 // LM3S5G56 #define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31 #define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36 #define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31 #define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36 +#define SYSCTL_DID1_PRTNO_5P3B 0x00B60000 // LM3S5P3B #define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51 #define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56 #define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31 #define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36 #define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36 +#define SYSCTL_DID1_PRTNO_5U91 0x007F0000 // LM3S5U91 #define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36 #define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 #define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 @@ -289,12 +592,18 @@ #define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 #define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 #define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 +#define SYSCTL_DID1_PRTNO_6816 0x00D10000 // LM3S6816 #define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911 +#define SYSCTL_DID1_PRTNO_6916 0x00D30000 // LM3S6916 #define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918 #define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 #define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 #define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 #define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 +#define SYSCTL_DID1_PRTNO_6C11 0x00AA0000 // LM3S6C11 +#define SYSCTL_DID1_PRTNO_6C65 0x00AC0000 // LM3S6C65 +#define SYSCTL_DID1_PRTNO_6G11 0x009F0000 // LM3S6G11 +#define SYSCTL_DID1_PRTNO_6G65 0x00AB0000 // LM3S6G65 #define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 #define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 #define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 @@ -307,19 +616,136 @@ #define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 #define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 #define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971 +#define SYSCTL_DID1_PRTNO_8C62 0x00AE0000 // LM3S8C62 +#define SYSCTL_DID1_PRTNO_8G62 0x00AD0000 // LM3S8G62 +#define SYSCTL_DID1_PRTNO_9781 0x00CF0000 // LM3S9781 #define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790 #define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792 +#define SYSCTL_DID1_PRTNO_9971 0x002D0000 // LM3S9971 #define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997 +#define SYSCTL_DID1_PRTNO_9B81 0x00D00000 // LM3S9B81 #define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90 #define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92 #define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95 #define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96 +#define SYSCTL_DID1_PRTNO_9BN2 0x001D0000 // LM3S9BN2 +#define SYSCTL_DID1_PRTNO_9BN5 0x001E0000 // LM3S9BN5 +#define SYSCTL_DID1_PRTNO_9BN6 0x001F0000 // LM3S9BN6 +#define SYSCTL_DID1_PRTNO_9C97 0x00700000 // LM3S9C97 +#define SYSCTL_DID1_PRTNO_9CN5 0x007A0000 // LM3S9CN5 +#define SYSCTL_DID1_PRTNO_9D81 0x00A90000 // LM3S9D81 +#define SYSCTL_DID1_PRTNO_9D90 0x007E0000 // LM3S9D90 +#define SYSCTL_DID1_PRTNO_9D92 0x00920000 // LM3S9D92 +#define SYSCTL_DID1_PRTNO_9D95 0x00C80000 // LM3S9D95 +#define SYSCTL_DID1_PRTNO_9D96 0x009D0000 // LM3S9D96 +#define SYSCTL_DID1_PRTNO_9DN5 0x007B0000 // LM3S9DN5 +#define SYSCTL_DID1_PRTNO_9DN6 0x007C0000 // LM3S9DN6 +#define SYSCTL_DID1_PRTNO_9G97 0x00600000 // LM3S9G97 +#define SYSCTL_DID1_PRTNO_9GN5 0x00790000 // LM3S9GN5 +#define SYSCTL_DID1_PRTNO_9L71 0x001B0000 // LM3S9L71 #define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97 +#define SYSCTL_DID1_PRTNO_9U81 0x00A80000 // LM3S9U81 +#define SYSCTL_DID1_PRTNO_9U90 0x007D0000 // LM3S9U90 +#define SYSCTL_DID1_PRTNO_9U92 0x00900000 // LM3S9U92 +#define SYSCTL_DID1_PRTNO_9U95 0x00B70000 // LM3S9U95 +#define SYSCTL_DID1_PRTNO_9U96 0x009B0000 // LM3S9U96 +#define SYSCTL_DID1_PRTNO_LM4F110B2QR \ + 0x00180000 // LM4F110B2QR +#define SYSCTL_DID1_PRTNO_LM4F110C4QR \ + 0x00190000 // LM4F110C4QR +#define SYSCTL_DID1_PRTNO_LM4F110E5QR \ + 0x00100000 // LM4F110E5QR +#define SYSCTL_DID1_PRTNO_LM4F110H5QR \ + 0x00110000 // LM4F110H5QR +#define SYSCTL_DID1_PRTNO_LM4F111B2QR \ + 0x00220000 // LM4F111B2QR +#define SYSCTL_DID1_PRTNO_LM4F111C4QR \ + 0x00230000 // LM4F111C4QR +#define SYSCTL_DID1_PRTNO_LM4F111E5QR \ + 0x00200000 // LM4F111E5QR +#define SYSCTL_DID1_PRTNO_LM4F111H5QR \ + 0x00210000 // LM4F111H5QR +#define SYSCTL_DID1_PRTNO_LM4F112C4QC \ + 0x00360000 // LM4F112C4QC +#define SYSCTL_DID1_PRTNO_LM4F112E5QC \ + 0x00300000 // LM4F112E5QC +#define SYSCTL_DID1_PRTNO_LM4F112H5QC \ + 0x00310000 // LM4F112H5QC +#define SYSCTL_DID1_PRTNO_LM4F112H5QD \ + 0x00350000 // LM4F112H5QD +#define SYSCTL_DID1_PRTNO_LM4F120B2QR \ + 0x00010000 // LM4F120B2QR +#define SYSCTL_DID1_PRTNO_LM4F120C4QR \ + 0x00020000 // LM4F120C4QR +#define SYSCTL_DID1_PRTNO_LM4F120E5QR \ + 0x00030000 // LM4F120E5QR +#define SYSCTL_DID1_PRTNO_LM4F120H5QR \ + 0x00040000 // LM4F120H5QR +#define SYSCTL_DID1_PRTNO_LM4F121B2QR \ + 0x00080000 // LM4F121B2QR +#define SYSCTL_DID1_PRTNO_LM4F121C4QR \ + 0x00090000 // LM4F121C4QR +#define SYSCTL_DID1_PRTNO_LM4F121E5QR \ + 0x000A0000 // LM4F121E5QR +#define SYSCTL_DID1_PRTNO_LM4F121H5QR \ + 0x000B0000 // LM4F121H5QR +#define SYSCTL_DID1_PRTNO_LM4F122C4QC \ + 0x00D00000 // LM4F122C4QC +#define SYSCTL_DID1_PRTNO_LM4F122E5QC \ + 0x00D10000 // LM4F122E5QC +#define SYSCTL_DID1_PRTNO_LM4F122H5QC \ + 0x00D20000 // LM4F122H5QC +#define SYSCTL_DID1_PRTNO_LM4F122H5QD \ + 0x00D60000 // LM4F122H5QD +#define SYSCTL_DID1_PRTNO_LM4F130C4QR \ + 0x00480000 // LM4F130C4QR +#define SYSCTL_DID1_PRTNO_LM4F130E5QR \ + 0x00400000 // LM4F130E5QR +#define SYSCTL_DID1_PRTNO_LM4F130H5QR \ + 0x00410000 // LM4F130H5QR +#define SYSCTL_DID1_PRTNO_LM4F131C4QR \ + 0x00520000 // LM4F131C4QR +#define SYSCTL_DID1_PRTNO_LM4F131E5QR \ + 0x00500000 // LM4F131E5QR +#define SYSCTL_DID1_PRTNO_LM4F131H5QR \ + 0x00510000 // LM4F131H5QR +#define SYSCTL_DID1_PRTNO_LM4F132C4QC \ + 0x00660000 // LM4F132C4QC +#define SYSCTL_DID1_PRTNO_LM4F132E5QC \ + 0x00600000 // LM4F132E5QC +#define SYSCTL_DID1_PRTNO_LM4F132H5QC \ + 0x00610000 // LM4F132H5QC +#define SYSCTL_DID1_PRTNO_LM4F132H5QD \ + 0x00650000 // LM4F132H5QD +#define SYSCTL_DID1_PRTNO_LM4F230E5QR \ + 0x00A00000 // LM4F230E5QR +#define SYSCTL_DID1_PRTNO_LM4F230H5QR \ + 0x00A10000 // LM4F230H5QR +#define SYSCTL_DID1_PRTNO_LM4F231E5QR \ + 0x00B00000 // LM4F231E5QR +#define SYSCTL_DID1_PRTNO_LM4F231H5QR \ + 0x00B10000 // LM4F231H5QR +#define SYSCTL_DID1_PRTNO_LM4F232E5QC \ + 0x00C00000 // LM4F232E5QC +#define SYSCTL_DID1_PRTNO_LM4F232H5BB \ + 0x00E30000 // LM4F232H5BB +#define SYSCTL_DID1_PRTNO_LM4F232H5QC \ + 0x00C10000 // LM4F232H5QC +#define SYSCTL_DID1_PRTNO_LM4F232H5QD \ + 0x00C50000 // LM4F232H5QD +#define SYSCTL_DID1_PRTNO_LM4FS1AH5BB \ + 0x00E50000 // LM4FS1AH5BB +#define SYSCTL_DID1_PRTNO_LM4FS99H5BB \ + 0x00E40000 // LM4FS99H5BB +#define SYSCTL_DID1_PRTNO_LM4FSXAH5BB \ + 0x00E00000 // LM4FSXAH5BB #define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count #define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package -#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package +#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package #define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package #define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package #define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range #define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C // to 70C) @@ -364,7 +790,10 @@ #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash +#define SYSCTL_DC0_FLASHSZ_384K 0x000000BF // 384 KB of Flash +#define SYSCTL_DC0_FLASHSZ_512K 0x000000FF // 512 KB of Flash #define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift #define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift @@ -377,7 +806,8 @@ #define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present #define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present #define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present -#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present #define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present #define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present #define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider @@ -387,18 +817,21 @@ // 6 minimum #define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 #define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a // PLL divider of 8 #define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a // PLL divider of 10 -#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second #define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second #define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second #define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second #define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second #define SYSCTL_DC1_MPU 0x00000080 // MPU Present #define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present @@ -423,7 +856,9 @@ #define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present #define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present #define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed #define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed #define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present #define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present #define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present @@ -652,7 +1087,7 @@ #define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control #define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control #define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control -#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control #define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control #define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control #define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control @@ -833,6 +1268,10 @@ #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz #define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz #define SYSCTL_RCC_PLLVER 0x00000400 // PLL Verification #define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC @@ -864,21 +1303,6 @@ #define SYSCTL_PLLCFG_F_S 5 #define SYSCTL_PLLCFG_R_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL -// register. -// -//***************************************************************************** -#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed -#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed -#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed -#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed -#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed -#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed -#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed -#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed - //***************************************************************************** // // The following are defines for the bit fields in the SYSCTL_GPIOHBCTL @@ -994,6 +1418,8 @@ // The following are defines for the bit fields in the SYSCTL_MOSCCTL register. // //***************************************************************************** +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action #define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC //***************************************************************************** @@ -1005,7 +1431,7 @@ #define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control #define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control #define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control #define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control #define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control #define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed @@ -1084,7 +1510,7 @@ #define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control #define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control #define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control #define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control #define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control #define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed @@ -1163,7 +1589,7 @@ #define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control #define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control #define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control #define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control #define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control #define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control @@ -1288,15 +1714,17 @@ #define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC #define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz #define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request #define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source #define SYSCTL_DSLPCLKCFG_D_S 23 //***************************************************************************** // -// The following are defines for the bit fields in the SYSCTL_CLKVCLR register. +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. // //***************************************************************************** -#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present //***************************************************************************** // @@ -1310,6 +1738,13 @@ #define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value #define SYSCTL_PIOSCCAL_UT_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear + //***************************************************************************** // // The following are defines for the bit fields in the SYSCTL_PIOSCSTAT @@ -1335,6 +1770,35 @@ //***************************************************************************** #define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + //***************************************************************************** // // The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG @@ -1383,6 +1847,1470 @@ #define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer // Active +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPLPC register. +// +//***************************************************************************** +#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPECI register. +// +//***************************************************************************** +#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPFAN register. +// +//***************************************************************************** +#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset +#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset +#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset +#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset +#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset +#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset +#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset +#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset +#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset +#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRLPC register. +// +//***************************************************************************** +#define SYSCTL_SRLPC_R0 0x00000001 // LPC Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPECI register. +// +//***************************************************************************** +#define SYSCTL_SRPECI_R0 0x00000001 // PECI Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRFAN register. +// +//***************************************************************************** +#define SYSCTL_SRFAN_R0 0x00000001 // FAN Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCLPC register. +// +//***************************************************************************** +#define SYSCTL_RCGCLPC_R0 0x00000001 // LPC Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPECI +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCPECI_R0 0x00000001 // PECI Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCFAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCFAN_R0 0x00000001 // FAN Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCLPC register. +// +//***************************************************************************** +#define SYSCTL_SCGCLPC_S0 0x00000001 // LPC Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPECI +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCPECI_S0 0x00000001 // PECI Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCFAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCFAN_S0 0x00000001 // FAN Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D7 0x00000080 // 0Mode Clock Gating Control +#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCLPC register. +// +//***************************************************************************** +#define SYSCTL_DCGCLPC_D0 0x00000001 // LPC Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPECI +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCPECI_D0 0x00000001 // PECI Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCFAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCFAN_D0 0x00000001 // FAN Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWD register. +// +//***************************************************************************** +#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control +#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCTIMER register. +// +//***************************************************************************** +#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control +#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control +#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control +#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control +#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control +#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCGPIO register. +// +//***************************************************************************** +#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control +#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control +#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control +#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control +#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control +#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control +#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control +#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control +#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control +#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control +#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control +#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control +#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control +#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control +#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCDMA register. +// +//***************************************************************************** +#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCHIB register. +// +//***************************************************************************** +#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUART register. +// +//***************************************************************************** +#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control +#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control +#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control +#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control +#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control +#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control +#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control +#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCSSI register. +// +//***************************************************************************** +#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control +#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control +#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control +#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCI2C register. +// +//***************************************************************************** +#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control +#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control +#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control +#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control +#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control +#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUSB register. +// +//***************************************************************************** +#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCAN register. +// +//***************************************************************************** +#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control +#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCADC register. +// +//***************************************************************************** +#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control +#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCACMP register. +// +//***************************************************************************** +#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCPWM register. +// +//***************************************************************************** +#define SYSCTL_PCPWM_P1 0x00000002 // PWM Module 1 Power Control +#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCQEI register. +// +//***************************************************************************** +#define SYSCTL_PCQEI_P1 0x00000002 // QEI Module 1 Power Control +#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCLPC register. +// +//***************************************************************************** +#define SYSCTL_PCLPC_P0 0x00000001 // LPC Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCPECI register. +// +//***************************************************************************** +#define SYSCTL_PCPECI_P0 0x00000001 // PECI Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCFAN register. +// +//***************************************************************************** +#define SYSCTL_PCFAN_P0 0x00000001 // FAN Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control +#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control +#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control +#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control +#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control +#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready +#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready +#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready +#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready +#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready +#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready +#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready +#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready +#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready +#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRLPC register. +// +//***************************************************************************** +#define SYSCTL_PRLPC_R0 0x00000001 // LPC Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPECI register. +// +//***************************************************************************** +#define SYSCTL_PRPECI_R0 0x00000001 // PECI Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRFAN register. +// +//***************************************************************************** +#define SYSCTL_PRFAN_R0 0x00000001 // FAN Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready + //***************************************************************************** // // The following definitions are deprecated. @@ -1396,6 +3324,7 @@ // addresses. // //***************************************************************************** +#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High-Speed Control #define SYSCTL_USER0 0x400FE1E0 // NV User Register 0 #define SYSCTL_USER1 0x400FE1E4 // NV User Register 1 @@ -1446,9 +3375,15 @@ // register. // //***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present #define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present #define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask #define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second #define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present #define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present @@ -1501,6 +3436,7 @@ // register. // //***************************************************************************** +#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control #define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control #define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control @@ -1545,6 +3481,21 @@ #define SYSCTL_PLLCFG_F_SHIFT 5 #define SYSCTL_PLLCFG_R_SHIFT 0 +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_GPIOHSCTL register. +// +//***************************************************************************** +#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed +#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed +#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed +#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed +#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed +#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed +#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed +#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed + //***************************************************************************** // // The following are deprecated defines for the bit fields in the SYSCTL_RCC2 @@ -1562,6 +3513,7 @@ // register. // //***************************************************************************** +#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control #define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control #define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control @@ -1571,6 +3523,7 @@ // register. // //***************************************************************************** +#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control #define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control #define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control @@ -1580,6 +3533,7 @@ // register. // //***************************************************************************** +#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control #define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control #define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control diff --git a/bsp/lm3s8962/Libraries/inc/hw_sysexc.h b/bsp/lm3s8962/Libraries/inc/hw_sysexc.h new file mode 100644 index 0000000000..4dce20dec3 --- /dev/null +++ b/bsp/lm3s8962/Libraries/inc/hw_sysexc.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// hw_sysexc.h - Macros used when accessing the system exception module. +// +// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 8264 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSEXC_H__ +#define __HW_SYSEXC_H__ + +//***************************************************************************** +// +// The following are defines for the System Exception Module register +// addresses. +// +//***************************************************************************** +#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt + // Status +#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask +#define SYSEXC_MIS 0x400F9008 // System Exception Raw Interrupt + // Status +#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_IXCRIS 0x00000020 // Inexact Exception Flag +#define SYSEXC_RIS_OFCRIS 0x00000010 // Overflow Exception Flag +#define SYSEXC_RIS_UFCRIS 0x00000008 // Underflow Exception Flag +#define SYSEXC_RIS_IOCRIS 0x00000004 // Invalid Operation Flag +#define SYSEXC_RIS_DZCRIS 0x00000002 // Divide By 0 Exception Flag +#define SYSEXC_RIS_IDCRIS 0x00000001 // Input Denormal Exception Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_IXCIM 0x00000020 // Inexact Exception Flag +#define SYSEXC_IM_OFCIM 0x00000010 // Overflow Exception Flag +#define SYSEXC_IM_UFCIM 0x00000008 // Underflow Exception Flag +#define SYSEXC_IM_IOCIM 0x00000004 // Invalid Operation Flag +#define SYSEXC_IM_DZCIM 0x00000002 // Divide By 0 Exception Flag +#define SYSEXC_IM_IDCIM 0x00000001 // Input Denormal Exception Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_IXCMIS 0x00000020 // Inexact Exception Flag +#define SYSEXC_MIS_OFCMIS 0x00000010 // Overflow Exception Flag +#define SYSEXC_MIS_UFCMIS 0x00000008 // Underflow Exception Flag +#define SYSEXC_MIS_IOCMIS 0x00000004 // Invalid Operation Flag +#define SYSEXC_MIS_DZCMIS 0x00000002 // Divide By 0 Exception Flag +#define SYSEXC_MIS_IDCMIS 0x00000001 // Input Denormal Exception Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_IXCIC 0x00000020 // Inexact Exception Flag +#define SYSEXC_IC_OFCIC 0x00000010 // Overflow Exception Flag +#define SYSEXC_IC_UFCIC 0x00000008 // Underflow Exception Flag +#define SYSEXC_IC_IOCIC 0x00000004 // Invalid Operation Flag +#define SYSEXC_IC_DZCIC 0x00000002 // Divide By 0 Exception Flag +#define SYSEXC_IC_IDCIC 0x00000001 // Input Denormal Exception Flag + +#endif // __HW_SYSEXC_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_timer.h b/bsp/lm3s8962/Libraries/inc/hw_timer.h index 3a75bc9c65..b1d35979a8 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_timer.h +++ b/bsp/lm3s8962/Libraries/inc/hw_timer.h @@ -2,7 +2,7 @@ // // hw_timer.h - Defines and macros used when accessing the timer. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -34,6 +34,7 @@ #define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode #define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode #define TIMER_O_CTL 0x0000000C // GPTM Control +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize #define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask #define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status #define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status @@ -50,6 +51,12 @@ #define TIMER_O_TBR 0x0000004C // GPTM Timer B #define TIMER_O_TAV 0x00000050 // GPTM Timer A Value #define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties //***************************************************************************** // @@ -69,6 +76,13 @@ // The following are defines for the bit fields in the TIMER_O_TAMR register. // //***************************************************************************** +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write #define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode #define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger #define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt @@ -87,6 +101,13 @@ // The following are defines for the bit fields in the TIMER_O_TBMR register. // //***************************************************************************** +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write #define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode #define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger #define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt @@ -125,11 +146,175 @@ #define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable #define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer + // 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer + // 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer + // 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer + // 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer + // 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer + // 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 0 is triggered + //***************************************************************************** // // The following are defines for the bit fields in the TIMER_O_IMR register. // //***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Mask #define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match // Interrupt Mask #define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt @@ -153,6 +338,8 @@ // The following are defines for the bit fields in the TIMER_O_RIS register. // //***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Raw Interrupt Status #define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw // Interrupt #define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw @@ -176,6 +363,8 @@ // The following are defines for the bit fields in the TIMER_O_MIS register. // //***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Masked Interrupt Status #define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked // Interrupt #define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked @@ -199,6 +388,8 @@ // The following are defines for the bit fields in the TIMER_O_ICR register. // //***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear #define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match // Interrupt Clear #define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt @@ -222,21 +413,27 @@ // The following are defines for the bit fields in the TIMER_O_TAILR register. // //***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register #define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load // Register High #define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load // Register Low #define TIMER_TAILR_TAILRH_S 16 #define TIMER_TAILR_TAILRL_S 0 +#define TIMER_TAILR_S 0 //***************************************************************************** // // The following are defines for the bit fields in the TIMER_O_TBILR register. // //***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register #define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load // Register #define TIMER_TBILR_TBILRL_S 0 +#define TIMER_TBILR_S 0 //***************************************************************************** // @@ -244,10 +441,12 @@ // register. // //***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register #define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High #define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low #define TIMER_TAMATCHR_TAMRH_S 16 #define TIMER_TAMATCHR_TAMRL_S 0 +#define TIMER_TAMATCHR_TAMR_S 0 //***************************************************************************** // @@ -255,7 +454,9 @@ // register. // //***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register #define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low +#define TIMER_TBMATCHR_TBMR_S 0 #define TIMER_TBMATCHR_TBMRL_S 0 //***************************************************************************** @@ -263,7 +464,9 @@ // The following are defines for the bit fields in the TIMER_O_TAPR register. // //***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte #define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 #define TIMER_TAPR_TAPSR_S 0 //***************************************************************************** @@ -271,7 +474,9 @@ // The following are defines for the bit fields in the TIMER_O_TBPR register. // //***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte #define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 #define TIMER_TBPR_TBPSR_S 0 //***************************************************************************** @@ -279,7 +484,10 @@ // The following are defines for the bit fields in the TIMER_O_TAPMR register. // //***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte #define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 #define TIMER_TAPMR_TAPSMR_S 0 //***************************************************************************** @@ -287,7 +495,10 @@ // The following are defines for the bit fields in the TIMER_O_TBPMR register. // //***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte #define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 #define TIMER_TBPMR_TBPSMR_S 0 //***************************************************************************** @@ -295,36 +506,97 @@ // The following are defines for the bit fields in the TIMER_O_TAR register. // //***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register #define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High #define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low #define TIMER_TAR_TARH_S 16 #define TIMER_TAR_TARL_S 0 +#define TIMER_TAR_S 0 //***************************************************************************** // // The following are defines for the bit fields in the TIMER_O_TBR register. // //***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register #define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B #define TIMER_TBR_TBRL_S 0 +#define TIMER_TBR_S 0 //***************************************************************************** // // The following are defines for the bit fields in the TIMER_O_TAV register. // //***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value #define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High #define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low #define TIMER_TAV_TAVH_S 16 #define TIMER_TAV_TAVL_S 0 +#define TIMER_TAV_S 0 //***************************************************************************** // // The following are defines for the bit fields in the TIMER_O_TBV register. // //***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value #define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register #define TIMER_TBV_TBVL_S 0 +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter //***************************************************************************** // diff --git a/bsp/lm3s8962/Libraries/inc/hw_types.h b/bsp/lm3s8962/Libraries/inc/hw_types.h index d4e449777f..f08046f45a 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_types.h +++ b/bsp/lm3s8962/Libraries/inc/hw_types.h @@ -2,7 +2,7 @@ // // hw_types.h - Common types and macros. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -115,6 +115,18 @@ typedef unsigned char tBoolean; (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST)) #endif +#ifndef CLASS_IS_FIRESTORM +#define CLASS_IS_FIRESTORM \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM)) +#endif + +#ifndef CLASS_IS_BLIZZARD +#define CLASS_IS_BLIZZARD \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD)) +#endif + #ifndef REVISION_IS_A0 #define REVISION_IS_A0 \ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ @@ -163,6 +175,18 @@ typedef unsigned char tBoolean; (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) #endif +#ifndef REVISION_IS_C3 +#define REVISION_IS_C3 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3)) +#endif + +#ifndef REVISION_IS_C5 +#define REVISION_IS_C5 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5)) +#endif + //***************************************************************************** // // Deprecated silicon class and revision detection macros. diff --git a/bsp/lm3s8962/Libraries/inc/hw_uart.h b/bsp/lm3s8962/Libraries/inc/hw_uart.h index 8a7832a47d..daf55d1312 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_uart.h +++ b/bsp/lm3s8962/Libraries/inc/hw_uart.h @@ -2,7 +2,7 @@ // // hw_uart.h - Macros and defines used when accessing the UART hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -49,6 +49,10 @@ #define UART_O_LCTL 0x00000090 // UART LIN Control #define UART_O_LSS 0x00000094 // UART LIN Snap Shot #define UART_O_LTIM 0x00000098 // UART LIN Timer +#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address +#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask +#define UART_O_PP 0x00000FC0 // UART Peripheral Properties +#define UART_O_CC 0x00000FC8 // UART Clock Configuration //***************************************************************************** // @@ -185,6 +189,7 @@ #define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask #define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask #define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt // Mask #define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask @@ -215,6 +220,7 @@ // Status #define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status #define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt // Status #define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt @@ -249,6 +255,8 @@ // Status #define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status #define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked // Interrupt Status #define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked @@ -277,10 +285,11 @@ // The following are defines for the bit fields in the UART_O_ICR register. // //***************************************************************************** -#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear -#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear -#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt +#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear #define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear #define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear #define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear @@ -335,6 +344,45 @@ #define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value #define UART_LTIM_TIMER_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_RANGE_M 0x0000FF00 // Self Address Range for 9-Bit + // Mode +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_RANGE_S 8 +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default) +#define UART_CC_CS_PIOSC 0x00000001 // PIOSC + //***************************************************************************** // // The following definitions are deprecated. @@ -418,6 +466,10 @@ // register. // //***************************************************************************** +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear #define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \ UART_RSR_FE) diff --git a/bsp/lm3s8962/Libraries/inc/hw_udma.h b/bsp/lm3s8962/Libraries/inc/hw_udma.h index 8fb06da885..59466e6eca 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_udma.h +++ b/bsp/lm3s8962/Libraries/inc/hw_udma.h @@ -2,7 +2,7 @@ // // hw_udma.h - Macros for use in accessing the UDMA registers. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -52,7 +52,12 @@ #define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set #define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear #define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear -#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select +#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment +#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status +#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 +#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 +#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 +#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 //***************************************************************************** // @@ -201,11 +206,109 @@ //***************************************************************************** // -// The following are defines for the bit fields in the UDMA_CHALT register. +// The following are defines for the bit fields in the UDMA_CHASGN register. // //***************************************************************************** -#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment - // Select +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 //***************************************************************************** // @@ -298,6 +401,14 @@ //***************************************************************************** #ifndef DEPRECATED +//***************************************************************************** +// +// The following are deprecated defines for the Micro Direct Memory Access +// register addresses. +// +//***************************************************************************** +#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select + //***************************************************************************** // // The following are deprecated defines for the bit fields in the UDMA_ENASET @@ -306,6 +417,15 @@ //***************************************************************************** #define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UDMA_CHALT +// register. +// +//***************************************************************************** +#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment + // Select + #endif #endif // __HW_UDMA_H__ diff --git a/bsp/lm3s8962/Libraries/inc/hw_usb.h b/bsp/lm3s8962/Libraries/inc/hw_usb.h index 73c5e8e217..abee8349bc 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_usb.h +++ b/bsp/lm3s8962/Libraries/inc/hw_usb.h @@ -2,7 +2,7 @@ // // hw_usb.h - Macros for use in accessing the USB registers. // -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -629,6 +629,7 @@ #define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt // Status and Clear #define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties //***************************************************************************** // @@ -4569,11 +4570,29 @@ #define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select #define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select #define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 #define USB_DMASEL_DMABTX_S 12 #define USB_DMASEL_DMABRX_S 8 #define USB_DMASEL_DMAATX_S 4 #define USB_DMASEL_DMAARX_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + //***************************************************************************** // // The following definitions are deprecated. diff --git a/bsp/lm3s8962/Libraries/inc/hw_watchdog.h b/bsp/lm3s8962/Libraries/inc/hw_watchdog.h index 9b52ffc700..d00c90240d 100644 --- a/bsp/lm3s8962/Libraries/inc/hw_watchdog.h +++ b/bsp/lm3s8962/Libraries/inc/hw_watchdog.h @@ -2,7 +2,7 @@ // // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. // -// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 6459 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -61,6 +61,7 @@ // //***************************************************************************** #define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable diff --git a/bsp/lm3s8962/Libraries/inc/inc.sgxx b/bsp/lm3s8962/Libraries/inc/inc.sgxx deleted file mode 100644 index 68b958950b..0000000000 Binary files a/bsp/lm3s8962/Libraries/inc/inc.sgxx and /dev/null differ diff --git a/bsp/lm3s8962/Libraries/inc/lm3s8962.h b/bsp/lm3s8962/Libraries/inc/lm3s8962.h deleted file mode 100644 index 4e9aa86be6..0000000000 --- a/bsp/lm3s8962/Libraries/inc/lm3s8962.h +++ /dev/null @@ -1,5034 +0,0 @@ -//***************************************************************************** -// -// lm3s8962.h - LM3S8962 Register Definitions -// -// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 6459 of the Stellaris Firmware Development Package. -// -//***************************************************************************** - -#ifndef __LM3S8962_H__ -#define __LM3S8962_H__ - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG0) -// -//***************************************************************************** -#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000)) -#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004)) -#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008)) -#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C)) -#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010)) -#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014)) -#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418)) -#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00)) - -//***************************************************************************** -// -// GPIO registers (PORTA) -// -//***************************************************************************** -#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000) -#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC)) -#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400)) -#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404)) -#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408)) -#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C)) -#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410)) -#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414)) -#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418)) -#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C)) -#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420)) -#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500)) -#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504)) -#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508)) -#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C)) -#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510)) -#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514)) -#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518)) -#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C)) -#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520)) -#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524)) - -//***************************************************************************** -// -// GPIO registers (PORTB) -// -//***************************************************************************** -#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000) -#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC)) -#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400)) -#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404)) -#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408)) -#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C)) -#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410)) -#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414)) -#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418)) -#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C)) -#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420)) -#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500)) -#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504)) -#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508)) -#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C)) -#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510)) -#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514)) -#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518)) -#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C)) -#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520)) -#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524)) - -//***************************************************************************** -// -// GPIO registers (PORTC) -// -//***************************************************************************** -#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000) -#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC)) -#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400)) -#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404)) -#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408)) -#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C)) -#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410)) -#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414)) -#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418)) -#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C)) -#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420)) -#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500)) -#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504)) -#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508)) -#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C)) -#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510)) -#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514)) -#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518)) -#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C)) -#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520)) -#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524)) - -//***************************************************************************** -// -// GPIO registers (PORTD) -// -//***************************************************************************** -#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000) -#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC)) -#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400)) -#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404)) -#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408)) -#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C)) -#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410)) -#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414)) -#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418)) -#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C)) -#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420)) -#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500)) -#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504)) -#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508)) -#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C)) -#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510)) -#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514)) -#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518)) -#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C)) -#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520)) -#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524)) - -//***************************************************************************** -// -// SSI registers (SSI0) -// -//***************************************************************************** -#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000)) -#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004)) -#define SSI0_DR_R (*((volatile unsigned long *)0x40008008)) -#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C)) -#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010)) -#define SSI0_IM_R (*((volatile unsigned long *)0x40008014)) -#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018)) -#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C)) -#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020)) - -//***************************************************************************** -// -// UART registers (UART0) -// -//***************************************************************************** -#define UART0_DR_R (*((volatile unsigned long *)0x4000C000)) -#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004)) -#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004)) -#define UART0_FR_R (*((volatile unsigned long *)0x4000C018)) -#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020)) -#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024)) -#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028)) -#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C)) -#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030)) -#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034)) -#define UART0_IM_R (*((volatile unsigned long *)0x4000C038)) -#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C)) -#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040)) -#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044)) - -//***************************************************************************** -// -// UART registers (UART1) -// -//***************************************************************************** -#define UART1_DR_R (*((volatile unsigned long *)0x4000D000)) -#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004)) -#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004)) -#define UART1_FR_R (*((volatile unsigned long *)0x4000D018)) -#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020)) -#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024)) -#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028)) -#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C)) -#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030)) -#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034)) -#define UART1_IM_R (*((volatile unsigned long *)0x4000D038)) -#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C)) -#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040)) -#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044)) - -//***************************************************************************** -// -// I2C registers (I2C0 MASTER) -// -//***************************************************************************** -#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000)) -#define I2C0_MASTER_SOAR_R (*((volatile unsigned long *)0x40020000)) -#define I2C0_MASTER_SCSR_R (*((volatile unsigned long *)0x40020004)) -#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004)) -#define I2C0_MASTER_SDR_R (*((volatile unsigned long *)0x40020008)) -#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008)) -#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C)) -#define I2C0_MASTER_SIMR_R (*((volatile unsigned long *)0x4002000C)) -#define I2C0_MASTER_SRIS_R (*((volatile unsigned long *)0x40020010)) -#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010)) -#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014)) -#define I2C0_MASTER_SMIS_R (*((volatile unsigned long *)0x40020014)) -#define I2C0_MASTER_SICR_R (*((volatile unsigned long *)0x40020018)) -#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018)) -#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C)) -#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020)) - -//***************************************************************************** -// -// I2C registers (I2C0 SLAVE) -// -//***************************************************************************** -#define I2C0_SLAVE_MSA_R (*((volatile unsigned long *)0x40020800)) -#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800)) -#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804)) -#define I2C0_SLAVE_MCS_R (*((volatile unsigned long *)0x40020804)) -#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808)) -#define I2C0_SLAVE_MDR_R (*((volatile unsigned long *)0x40020808)) -#define I2C0_SLAVE_MTPR_R (*((volatile unsigned long *)0x4002080C)) -#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C)) -#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810)) -#define I2C0_SLAVE_MIMR_R (*((volatile unsigned long *)0x40020810)) -#define I2C0_SLAVE_MRIS_R (*((volatile unsigned long *)0x40020814)) -#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814)) -#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818)) -#define I2C0_SLAVE_MMIS_R (*((volatile unsigned long *)0x40020818)) -#define I2C0_SLAVE_MICR_R (*((volatile unsigned long *)0x4002081C)) -#define I2C0_SLAVE_MCR_R (*((volatile unsigned long *)0x40020820)) - -//***************************************************************************** -// -// GPIO registers (PORTE) -// -//***************************************************************************** -#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000) -#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC)) -#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400)) -#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404)) -#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408)) -#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C)) -#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410)) -#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414)) -#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418)) -#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C)) -#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420)) -#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500)) -#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504)) -#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508)) -#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C)) -#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510)) -#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514)) -#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518)) -#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C)) -#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520)) -#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524)) - -//***************************************************************************** -// -// GPIO registers (PORTF) -// -//***************************************************************************** -#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000) -#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC)) -#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400)) -#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404)) -#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408)) -#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C)) -#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410)) -#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414)) -#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418)) -#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C)) -#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420)) -#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500)) -#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504)) -#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508)) -#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C)) -#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510)) -#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514)) -#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518)) -#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C)) -#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520)) -#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524)) - -//***************************************************************************** -// -// GPIO registers (PORTG) -// -//***************************************************************************** -#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000) -#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC)) -#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400)) -#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404)) -#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408)) -#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C)) -#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410)) -#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414)) -#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418)) -#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C)) -#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420)) -#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500)) -#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504)) -#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508)) -#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C)) -#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510)) -#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514)) -#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518)) -#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C)) -#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520)) -#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524)) - -//***************************************************************************** -// -// PWM registers (PWM) -// -//***************************************************************************** -#define PWM_CTL_R (*((volatile unsigned long *)0x40028000)) -#define PWM_SYNC_R (*((volatile unsigned long *)0x40028004)) -#define PWM_ENABLE_R (*((volatile unsigned long *)0x40028008)) -#define PWM_INVERT_R (*((volatile unsigned long *)0x4002800C)) -#define PWM_FAULT_R (*((volatile unsigned long *)0x40028010)) -#define PWM_INTEN_R (*((volatile unsigned long *)0x40028014)) -#define PWM_RIS_R (*((volatile unsigned long *)0x40028018)) -#define PWM_ISC_R (*((volatile unsigned long *)0x4002801C)) -#define PWM_STATUS_R (*((volatile unsigned long *)0x40028020)) -#define PWM_0_CTL_R (*((volatile unsigned long *)0x40028040)) -#define PWM_0_INTEN_R (*((volatile unsigned long *)0x40028044)) -#define PWM_0_RIS_R (*((volatile unsigned long *)0x40028048)) -#define PWM_0_ISC_R (*((volatile unsigned long *)0x4002804C)) -#define PWM_0_LOAD_R (*((volatile unsigned long *)0x40028050)) -#define PWM_0_COUNT_R (*((volatile unsigned long *)0x40028054)) -#define PWM_0_CMPA_R (*((volatile unsigned long *)0x40028058)) -#define PWM_0_CMPB_R (*((volatile unsigned long *)0x4002805C)) -#define PWM_0_GENA_R (*((volatile unsigned long *)0x40028060)) -#define PWM_0_GENB_R (*((volatile unsigned long *)0x40028064)) -#define PWM_0_DBCTL_R (*((volatile unsigned long *)0x40028068)) -#define PWM_0_DBRISE_R (*((volatile unsigned long *)0x4002806C)) -#define PWM_0_DBFALL_R (*((volatile unsigned long *)0x40028070)) -#define PWM_1_CTL_R (*((volatile unsigned long *)0x40028080)) -#define PWM_1_INTEN_R (*((volatile unsigned long *)0x40028084)) -#define PWM_1_RIS_R (*((volatile unsigned long *)0x40028088)) -#define PWM_1_ISC_R (*((volatile unsigned long *)0x4002808C)) -#define PWM_1_LOAD_R (*((volatile unsigned long *)0x40028090)) -#define PWM_1_COUNT_R (*((volatile unsigned long *)0x40028094)) -#define PWM_1_CMPA_R (*((volatile unsigned long *)0x40028098)) -#define PWM_1_CMPB_R (*((volatile unsigned long *)0x4002809C)) -#define PWM_1_GENA_R (*((volatile unsigned long *)0x400280A0)) -#define PWM_1_GENB_R (*((volatile unsigned long *)0x400280A4)) -#define PWM_1_DBCTL_R (*((volatile unsigned long *)0x400280A8)) -#define PWM_1_DBRISE_R (*((volatile unsigned long *)0x400280AC)) -#define PWM_1_DBFALL_R (*((volatile unsigned long *)0x400280B0)) -#define PWM_2_CTL_R (*((volatile unsigned long *)0x400280C0)) -#define PWM_2_INTEN_R (*((volatile unsigned long *)0x400280C4)) -#define PWM_2_RIS_R (*((volatile unsigned long *)0x400280C8)) -#define PWM_2_ISC_R (*((volatile unsigned long *)0x400280CC)) -#define PWM_2_LOAD_R (*((volatile unsigned long *)0x400280D0)) -#define PWM_2_COUNT_R (*((volatile unsigned long *)0x400280D4)) -#define PWM_2_CMPA_R (*((volatile unsigned long *)0x400280D8)) -#define PWM_2_CMPB_R (*((volatile unsigned long *)0x400280DC)) -#define PWM_2_GENA_R (*((volatile unsigned long *)0x400280E0)) -#define PWM_2_GENB_R (*((volatile unsigned long *)0x400280E4)) -#define PWM_2_DBCTL_R (*((volatile unsigned long *)0x400280E8)) -#define PWM_2_DBRISE_R (*((volatile unsigned long *)0x400280EC)) -#define PWM_2_DBFALL_R (*((volatile unsigned long *)0x400280F0)) - -//***************************************************************************** -// -// QEI registers (QEI0) -// -//***************************************************************************** -#define QEI0_CTL_R (*((volatile unsigned long *)0x4002C000)) -#define QEI0_STAT_R (*((volatile unsigned long *)0x4002C004)) -#define QEI0_POS_R (*((volatile unsigned long *)0x4002C008)) -#define QEI0_MAXPOS_R (*((volatile unsigned long *)0x4002C00C)) -#define QEI0_LOAD_R (*((volatile unsigned long *)0x4002C010)) -#define QEI0_TIME_R (*((volatile unsigned long *)0x4002C014)) -#define QEI0_COUNT_R (*((volatile unsigned long *)0x4002C018)) -#define QEI0_SPEED_R (*((volatile unsigned long *)0x4002C01C)) -#define QEI0_INTEN_R (*((volatile unsigned long *)0x4002C020)) -#define QEI0_RIS_R (*((volatile unsigned long *)0x4002C024)) -#define QEI0_ISC_R (*((volatile unsigned long *)0x4002C028)) - -//***************************************************************************** -// -// QEI registers (QEI1) -// -//***************************************************************************** -#define QEI1_CTL_R (*((volatile unsigned long *)0x4002D000)) -#define QEI1_STAT_R (*((volatile unsigned long *)0x4002D004)) -#define QEI1_POS_R (*((volatile unsigned long *)0x4002D008)) -#define QEI1_MAXPOS_R (*((volatile unsigned long *)0x4002D00C)) -#define QEI1_LOAD_R (*((volatile unsigned long *)0x4002D010)) -#define QEI1_TIME_R (*((volatile unsigned long *)0x4002D014)) -#define QEI1_COUNT_R (*((volatile unsigned long *)0x4002D018)) -#define QEI1_SPEED_R (*((volatile unsigned long *)0x4002D01C)) -#define QEI1_INTEN_R (*((volatile unsigned long *)0x4002D020)) -#define QEI1_RIS_R (*((volatile unsigned long *)0x4002D024)) -#define QEI1_ISC_R (*((volatile unsigned long *)0x4002D028)) - -//***************************************************************************** -// -// Timer registers (TIMER0) -// -//***************************************************************************** -#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000)) -#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004)) -#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008)) -#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C)) -#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018)) -#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C)) -#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020)) -#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024)) -#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028)) -#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C)) -#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030)) -#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034)) -#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038)) -#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C)) -#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040)) -#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044)) -#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048)) -#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C)) - -//***************************************************************************** -// -// Timer registers (TIMER1) -// -//***************************************************************************** -#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000)) -#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004)) -#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008)) -#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C)) -#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018)) -#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C)) -#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020)) -#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024)) -#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028)) -#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C)) -#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030)) -#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034)) -#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038)) -#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C)) -#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040)) -#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044)) -#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048)) -#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C)) - -//***************************************************************************** -// -// Timer registers (TIMER2) -// -//***************************************************************************** -#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000)) -#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004)) -#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008)) -#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C)) -#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018)) -#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C)) -#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020)) -#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024)) -#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028)) -#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C)) -#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030)) -#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034)) -#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038)) -#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C)) -#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040)) -#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044)) -#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048)) -#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C)) - -//***************************************************************************** -// -// Timer registers (TIMER3) -// -//***************************************************************************** -#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000)) -#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004)) -#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008)) -#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C)) -#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018)) -#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C)) -#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020)) -#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024)) -#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028)) -#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C)) -#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030)) -#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034)) -#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038)) -#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C)) -#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040)) -#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044)) -#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048)) -#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C)) - -//***************************************************************************** -// -// ADC registers (ADC0) -// -//***************************************************************************** -#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000)) -#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004)) -#define ADC0_IM_R (*((volatile unsigned long *)0x40038008)) -#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C)) -#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010)) -#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014)) -#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018)) -#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020)) -#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028)) -#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030)) -#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040)) -#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044)) -#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048)) -#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C)) -#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060)) -#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064)) -#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068)) -#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C)) -#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080)) -#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084)) -#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088)) -#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C)) -#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0)) -#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4)) -#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8)) -#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC)) -#define ADC0_TMLB_R (*((volatile unsigned long *)0x40038100)) - -//***************************************************************************** -// -// Comparator registers (COMP) -// -//***************************************************************************** -#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000)) -#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004)) -#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008)) -#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010)) -#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020)) -#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024)) - -//***************************************************************************** -// -// CAN registers (CAN0) -// -//***************************************************************************** -#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000)) -#define CAN0_STS_R (*((volatile unsigned long *)0x40040004)) -#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008)) -#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C)) -#define CAN0_INT_R (*((volatile unsigned long *)0x40040010)) -#define CAN0_TST_R (*((volatile unsigned long *)0x40040014)) -#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018)) -#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020)) -#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024)) -#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028)) -#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C)) -#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030)) -#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034)) -#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038)) -#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C)) -#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040)) -#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044)) -#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048)) -#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080)) -#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084)) -#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088)) -#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C)) -#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090)) -#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094)) -#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098)) -#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C)) -#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0)) -#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4)) -#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8)) -#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100)) -#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104)) -#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120)) -#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124)) -#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140)) -#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144)) -#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160)) -#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164)) - -//***************************************************************************** -// -// Ethernet MAC registers (MAC) -// -//***************************************************************************** -#define MAC_RIS_R (*((volatile unsigned long *)0x40048000)) -#define MAC_IACK_R (*((volatile unsigned long *)0x40048000)) -#define MAC_IM_R (*((volatile unsigned long *)0x40048004)) -#define MAC_RCTL_R (*((volatile unsigned long *)0x40048008)) -#define MAC_TCTL_R (*((volatile unsigned long *)0x4004800C)) -#define MAC_DATA_R (*((volatile unsigned long *)0x40048010)) -#define MAC_IA0_R (*((volatile unsigned long *)0x40048014)) -#define MAC_IA1_R (*((volatile unsigned long *)0x40048018)) -#define MAC_THR_R (*((volatile unsigned long *)0x4004801C)) -#define MAC_MCTL_R (*((volatile unsigned long *)0x40048020)) -#define MAC_MDV_R (*((volatile unsigned long *)0x40048024)) -#define MAC_MTXD_R (*((volatile unsigned long *)0x4004802C)) -#define MAC_MRXD_R (*((volatile unsigned long *)0x40048030)) -#define MAC_NP_R (*((volatile unsigned long *)0x40048034)) -#define MAC_TR_R (*((volatile unsigned long *)0x40048038)) -#define MAC_TS_R (*((volatile unsigned long *)0x4004803C)) - -//***************************************************************************** -// -// Ethernet Controller PHY registers (MAC) -// -//***************************************************************************** -#define PHY_MR0 0x00000000 // Ethernet PHY Management Register - // 0 - Control -#define PHY_MR1 0x00000001 // Ethernet PHY Management Register - // 1 - Status -#define PHY_MR2 0x00000002 // Ethernet PHY Management Register - // 2 - PHY Identifier 1 -#define PHY_MR3 0x00000003 // Ethernet PHY Management Register - // 3 - PHY Identifier 2 -#define PHY_MR4 0x00000004 // Ethernet PHY Management Register - // 4 - Auto-Negotiation - // Advertisement -#define PHY_MR5 0x00000005 // Ethernet PHY Management Register - // 5 - Auto-Negotiation Link - // Partner Base Page Ability -#define PHY_MR6 0x00000006 // Ethernet PHY Management Register - // 6 - Auto-Negotiation Expansion -#define PHY_MR16 0x00000010 // Ethernet PHY Management Register - // 16 - Vendor-Specific -#define PHY_MR17 0x00000011 // Ethernet PHY Management Register - // 17 - Mode Control/Status -#define PHY_MR18 0x00000012 // Ethernet PHY Management Register - // 18 - Diagnostic -#define PHY_MR19 0x00000013 // Ethernet PHY Management Register - // 19 - Transceiver Control -#define PHY_MR23 0x00000017 // Ethernet PHY Management Register - // 23 - LED Configuration -#define PHY_MR24 0x00000018 // Ethernet PHY Management Register - // 24 -MDI/MDIX Control - -//***************************************************************************** -// -// Hibernation module registers (HIB) -// -//***************************************************************************** -#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000)) -#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004)) -#define HIB_RTCM1_R (*((volatile unsigned long *)0x400FC008)) -#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C)) -#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010)) -#define HIB_IM_R (*((volatile unsigned long *)0x400FC014)) -#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018)) -#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C)) -#define HIB_IC_R (*((volatile unsigned long *)0x400FC020)) -#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024)) -#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030)) - -//***************************************************************************** -// -// FLASH registers (FLASH CTRL) -// -//***************************************************************************** -#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000)) -#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004)) -#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008)) -#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C)) -#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010)) -#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014)) -#define FLASH_USECRL_R (*((volatile unsigned long *)0x400FE140)) -#define FLASH_USERDBG_R (*((volatile unsigned long *)0x400FE1D0)) -#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0)) -#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4)) -#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200)) -#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204)) -#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208)) -#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C)) -#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400)) -#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404)) -#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408)) -#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C)) - -//***************************************************************************** -// -// System Control registers (SYSCTL) -// -//***************************************************************************** -#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000)) -#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004)) -#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008)) -#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010)) -#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014)) -#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018)) -#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C)) -#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030)) -#define SYSCTL_LDOPCTL_R (*((volatile unsigned long *)0x400FE034)) -#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040)) -#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044)) -#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048)) -#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050)) -#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054)) -#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058)) -#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C)) -#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060)) -#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064)) -#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070)) -#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100)) -#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104)) -#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108)) -#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110)) -#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114)) -#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118)) -#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120)) -#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124)) -#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128)) -#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144)) - -//***************************************************************************** -// -// NVIC registers (NVIC) -// -//***************************************************************************** -#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004)) -#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010)) -#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014)) -#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018)) -#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C)) -#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) -#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104)) -#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180)) -#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184)) -#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200)) -#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204)) -#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280)) -#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284)) -#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300)) -#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304)) -#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400)) -#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404)) -#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408)) -#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C)) -#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) -#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414)) -#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418)) -#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C)) -#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420)) -#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424)) -#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428)) -#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00)) -#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04)) -#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08)) -#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C)) -#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10)) -#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14)) -#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18)) -#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C)) -#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20)) -#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24)) -#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28)) -#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C)) -#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30)) -#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34)) -#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38)) -#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90)) -#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94)) -#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98)) -#define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C)) -#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0)) -#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0)) -#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4)) -#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8)) -#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC)) -#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00)) - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//***************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//***************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//***************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//***************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//***************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock -#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked - // and may be modified -#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked - // and may not be modified -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR0 register. -// -//***************************************************************************** -#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate -#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase -#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity -#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select -#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format -#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous - // Serial Frame Format -#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format -#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select -#define SSI_CR0_DSS_4 0x00000003 // 4-bit data -#define SSI_CR0_DSS_5 0x00000004 // 5-bit data -#define SSI_CR0_DSS_6 0x00000005 // 6-bit data -#define SSI_CR0_DSS_7 0x00000006 // 7-bit data -#define SSI_CR0_DSS_8 0x00000007 // 8-bit data -#define SSI_CR0_DSS_9 0x00000008 // 9-bit data -#define SSI_CR0_DSS_10 0x00000009 // 10-bit data -#define SSI_CR0_DSS_11 0x0000000A // 11-bit data -#define SSI_CR0_DSS_12 0x0000000B // 12-bit data -#define SSI_CR0_DSS_13 0x0000000C // 13-bit data -#define SSI_CR0_DSS_14 0x0000000D // 14-bit data -#define SSI_CR0_DSS_15 0x0000000E // 15-bit data -#define SSI_CR0_DSS_16 0x0000000F // 16-bit data -#define SSI_CR0_SCR_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR1 register. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable -#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select -#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port - // Enable -#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DR register. -// -//***************************************************************************** -#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_SR register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI Busy Bit -#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full -#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty -#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full -#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CPSR register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_IM register. -// -//***************************************************************************** -#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask -#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask -#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt - // Mask -#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_RIS register. -// -//***************************************************************************** -#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt - // Status -#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt - // Status -#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw - // Interrupt Status -#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_MIS register. -// -//***************************************************************************** -#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked - // Interrupt Status -#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked - // Interrupt Status -#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked - // Interrupt Status -#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_ICR register. -// -//***************************************************************************** -#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt - // Clear -#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//***************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//***************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//***************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//***************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//***************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full -#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full -#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) -#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full -#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full -#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full -#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) -#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full -#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//***************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_RS 0x00000001 // Receive not send -#define I2C_MSA_SA_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//***************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//***************************************************************************** -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -#define I2C_SCSR_RREQ 0x00000001 // Receive Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//***************************************************************************** -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_STOP 0x00000004 // Generate STOP -#define I2C_MCS_START 0x00000002 // Generate START -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_RUN 0x00000001 // I2C Master Enable -#define I2C_MCS_BUSY 0x00000001 // I2C Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//***************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//***************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // Data Transferred -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//***************************************************************************** -#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//***************************************************************************** -#define I2C_MIMR_IM 0x00000001 // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//***************************************************************************** -#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//***************************************************************************** -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//***************************************************************************** -#define I2C_MICR_IC 0x00000001 // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//***************************************************************************** -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CTL register. -// -//***************************************************************************** -#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_SYNC register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENABLE register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INVERT register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal -#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal -#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal -#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal -#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal -#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULT register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INTEN register. -// -//***************************************************************************** -#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable -#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_RIS register. -// -//***************************************************************************** -#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted -#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ISC register. -// -//***************************************************************************** -#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted -#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_STATUS register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CTL register. -// -//***************************************************************************** -#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_X_CTL_MODE 0x00000002 // Counter Mode -#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_INTEN register. -// -//***************************************************************************** -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_RIS register. -// -//***************************************************************************** -#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_ISC register. -// -//***************************************************************************** -#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_LOAD register. -// -//***************************************************************************** -#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_X_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_COUNT register. -// -//***************************************************************************** -#define PWM_X_COUNT_M 0x0000FFFF // Counter Value -#define PWM_X_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPA register. -// -//***************************************************************************** -#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_X_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPB register. -// -//***************************************************************************** -#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_X_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENA register. -// -//***************************************************************************** -#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_X_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_X_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_X_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_X_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENB register. -// -//***************************************************************************** -#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_X_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_X_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_X_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_X_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBCTL register. -// -//***************************************************************************** -#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBRISE register. -// -//***************************************************************************** -#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_X_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBFALL register. -// -//***************************************************************************** -#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_X_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall QEI -#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse -#define QEI_CTL_INVB 0x00000400 // Invert PhB -#define QEI_CTL_INVA 0x00000200 // Invert PhA -#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity -#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 -#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 -#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 -#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 -#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 -#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 -#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 -#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 -#define QEI_CTL_VELEN 0x00000020 // Capture Velocity -#define QEI_CTL_RESMODE 0x00000010 // Reset Mode -#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode -#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode -#define QEI_CTL_SWAP 0x00000002 // Swap Signals -#define QEI_CTL_ENABLE 0x00000001 // Enable QEI - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation -#define QEI_STAT_ERROR 0x00000001 // Error Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator - // Value -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator - // Value -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Velocity -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable -#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt - // Enable -#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable -#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected -#define QEI_RIS_DIR 0x00000004 // Direction Change Detected -#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired -#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_ISC register. -// -//***************************************************************************** -#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt -#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt -#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt -#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) - // counter configuration -#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The - // function is controlled by bits - // 1:0 of GPTMTAMR and GPTMTBMR - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt - // Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt - // Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt - // Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt - // Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw - // Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw - // Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw - // Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw - // Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked - // Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked - // Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked - // Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked - // Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt - // Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt - // Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt - // Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt - // Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load - // Register High -#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load - // Register Low -#define TIMER_TAILR_TAILRH_S 16 -#define TIMER_TAILR_TAILRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_TBILRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High -#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low -#define TIMER_TAMATCHR_TAMRH_S 16 -#define TIMER_TAMATCHR_TAMRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low -#define TIMER_TBMATCHR_TBMRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High -#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low -#define TIMER_TAR_TARH_S 16 -#define TIMER_TAR_TARL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM Timer B -#define TIMER_TBR_TBRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4) -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4) -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4) -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4) -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX0 register. -// -//***************************************************************************** -#define ADC_SSMUX0_MUX7_M 0x30000000 // 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x03000000 // 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00300000 // 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x00030000 // 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x00003000 // 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000300 // 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x00000030 // 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x00000003 // 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL0 register. -// -//***************************************************************************** -#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select -#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select -#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select -#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select -#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select -#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select -#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select -#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. -// -//***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. -// -//***************************************************************************** -#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX1 register. -// -//***************************************************************************** -#define ADC_SSMUX1_MUX3_M 0x00003000 // 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000300 // 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x00000030 // 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x00000003 // 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL1 register. -// -//***************************************************************************** -#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select -#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select -#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select -#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. -// -//***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. -// -//***************************************************************************** -#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX2 register. -// -//***************************************************************************** -#define ADC_SSMUX2_MUX3_M 0x00003000 // 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000300 // 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x00000030 // 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x00000003 // 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL2 register. -// -//***************************************************************************** -#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select -#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select -#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select -#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. -// -//***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. -// -//***************************************************************************** -#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX3 register. -// -//***************************************************************************** -#define ADC_SSMUX3_MUX0_M 0x00000003 // 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL3 register. -// -//***************************************************************************** -#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. -// -//***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. -// -//***************************************************************************** -#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable - -//***************************************************************************** -// -// The following are defines for the the interpretation of the data in the -// SSFIFOx when the ADC TMLB is enabled. -// -//***************************************************************************** -#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter -#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator -#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator -#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator -#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator -#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift -#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACMIS register. -// -//***************************************************************************** -#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACRIS register. -// -//***************************************************************************** -#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACINTEN register. -// -//***************************************************************************** -#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACREFCTL -// register. -// -//***************************************************************************** -#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable -#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range -#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref -#define COMP_ACREFCTL_VREF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. -// -//***************************************************************************** -#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL0 register. -// -//***************************************************************************** -#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference - // (VIREF) -#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus-Off Status -#define CAN_STS_EWARN 0x00000040 // Warning Status -#define CAN_STS_EPASS 0x00000020 // Error Passive -#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully -#define CAN_STS_TXOK 0x00000008 // Transmitted a Message - // Successfully -#define CAN_STS_LEC_M 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No Error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error -#define CAN_STS_LEC_FORM 0x00000002 // Format Error -#define CAN_STS_LEC_ACK 0x00000003 // ACK Error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error -#define CAN_STS_LEC_CRC 0x00000006 // CRC Error -#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Received Error Passive -#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter -#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter -#define CAN_ERR_REC_S 8 -#define CAN_ERR_TEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point -#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point -#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width -#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler -#define CAN_BIT_TSEG2_S 12 -#define CAN_BIT_TSEG1_S 8 -#define CAN_BIT_SJW_S 6 -#define CAN_BIT_BRP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // Receive Observation -#define CAN_TST_TX_M 0x00000060 // Transmit Control -#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point -#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low -#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High -#define CAN_TST_LBACK 0x00000010 // Loopback Mode -#define CAN_TST_SILENT 0x00000008 // Silent Mode -#define CAN_TST_BASIC 0x00000004 // Basic Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension -#define CAN_BRPE_BRPE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CRQ register. -// -//***************************************************************************** -#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; - // it is interpreted as 0x20, or - // object 32 -#define CAN_IF1CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CMSK register. -// -//***************************************************************************** -#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. -// -//***************************************************************************** -#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF1MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. -// -//***************************************************************************** -#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF1MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. -// -//***************************************************************************** -#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF1ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. -// -//***************************************************************************** -#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF1ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MCTL register. -// -//***************************************************************************** -#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF1MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA1 register. -// -//***************************************************************************** -#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA2 register. -// -//***************************************************************************** -#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB1 register. -// -//***************************************************************************** -#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB2 register. -// -//***************************************************************************** -#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CRQ register. -// -//***************************************************************************** -#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; - // it is interpreted as 0x20, or - // object 32 -#define CAN_IF2CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CMSK register. -// -//***************************************************************************** -#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. -// -//***************************************************************************** -#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF2MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. -// -//***************************************************************************** -#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF2MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. -// -//***************************************************************************** -#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF2ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. -// -//***************************************************************************** -#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF2ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MCTL register. -// -//***************************************************************************** -#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF2MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA1 register. -// -//***************************************************************************** -#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA2 register. -// -//***************************************************************************** -#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB1 register. -// -//***************************************************************************** -#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB2 register. -// -//***************************************************************************** -#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ1_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ2_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA1_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA2_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1INT register. -// -//***************************************************************************** -#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG1INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2INT register. -// -//***************************************************************************** -#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG2INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1VAL register. -// -//***************************************************************************** -#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG1VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2VAL register. -// -//***************************************************************************** -#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG2VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_RIS register. -// -//***************************************************************************** -#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete -#define MAC_RIS_RXER 0x00000010 // Receive Error -#define MAC_RIS_FOV 0x00000008 // FIFO Overrun -#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty -#define MAC_RIS_TXER 0x00000002 // Transmit Error -#define MAC_RIS_RXINT 0x00000001 // Packet Received - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear Receive Error -#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty -#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error -#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask Receive Error -#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty -#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error -#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames -#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_DATA register. -// -//***************************************************************************** -#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data -#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data -#define MAC_DATA_RXDATA_S 0 -#define MAC_DATA_TXDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4 -#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3 -#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2 -#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1 -#define MAC_IA0_MACOCT4_S 24 -#define MAC_IA0_MACOCT3_S 16 -#define MAC_IA0_MACOCT2_S 8 -#define MAC_IA0_MACOCT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6 -#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5 -#define MAC_IA1_MACOCT6_S 8 -#define MAC_IA1_MACOCT5_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_THR register. -// -//***************************************************************************** -#define MAC_THR_THRESH_M 0x0000003F // Threshold Value -#define MAC_THR_THRESH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address -#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type -#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable -#define MAC_MCTL_REGADR_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV_M 0x000000FF // Clock Divider -#define MAC_MDV_DIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data -#define MAC_MTXD_MDTX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data -#define MAC_MRXD_MDRX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive - // FIFO -#define MAC_NP_NPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_TR register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // New Transmission - -//***************************************************************************** -// -// The following are defines for the bit fields in the MAC_O_TS register. -// -//***************************************************************************** -#define MAC_TS_TSEN 0x00000001 // Time Stamp Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR0 register. -// -//***************************************************************************** -#define PHY_MR0_RESET 0x00008000 // Reset Registers -#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode -#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select -#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable -#define PHY_MR0_PWRDN 0x00000800 // Power Down -#define PHY_MR0_ISO 0x00000400 // Isolate -#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation -#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode -#define PHY_MR0_COLT 0x00000080 // Collision Test - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR1 register. -// -//***************************************************************************** -#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode -#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode -#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode -#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode -#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble - // Suppressed -#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete -#define PHY_MR1_RFAULT 0x00000010 // Remote Fault -#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation -#define PHY_MR1_LINK 0x00000004 // Link Made -#define PHY_MR1_JAB 0x00000002 // Jabber Condition -#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR2 register. -// -//***************************************************************************** -#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique - // Identifier[21:6] -#define PHY_MR2_OUI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR3 register. -// -//***************************************************************************** -#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique - // Identifier[5:0] -#define PHY_MR3_MN_M 0x000003F0 // Model Number -#define PHY_MR3_RN_M 0x0000000F // Revision Number -#define PHY_MR3_OUI_S 10 -#define PHY_MR3_MN_S 4 -#define PHY_MR3_RN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR4 register. -// -//***************************************************************************** -#define PHY_MR4_NP 0x00008000 // Next Page -#define PHY_MR4_RF 0x00002000 // Remote Fault -#define PHY_MR4_A3 0x00000100 // Technology Ability Field [3] -#define PHY_MR4_A2 0x00000080 // Technology Ability Field [2] -#define PHY_MR4_A1 0x00000040 // Technology Ability Field [1] -#define PHY_MR4_A0 0x00000020 // Technology Ability Field [0] -#define PHY_MR4_S_M 0x0000001F // Selector Field -#define PHY_MR4_S_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR5 register. -// -//***************************************************************************** -#define PHY_MR5_NP 0x00008000 // Next Page -#define PHY_MR5_ACK 0x00004000 // Acknowledge -#define PHY_MR5_RF 0x00002000 // Remote Fault -#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field -#define PHY_MR5_S_M 0x0000001F // Selector Field -#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3 -#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T -#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5 -#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394 -#define PHY_MR5_A_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR6 register. -// -//***************************************************************************** -#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault -#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able -#define PHY_MR6_PRX 0x00000002 // New Page Received -#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation - // Able - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR16 register. -// -//***************************************************************************** -#define PHY_MR16_RPTR 0x00008000 // Repeater Mode -#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity -#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode -#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing -#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode -#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable -#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity -#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass -#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR17 register. -// -//***************************************************************************** -#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable -#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable -#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable -#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault - // Interrupt Enable -#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable -#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt - // Enable -#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable -#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete - // Interrupt Enable -#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt -#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt -#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt -#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault - // Interrupt -#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt -#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt -#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt -#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR18 register. -// -//***************************************************************************** -#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure -#define PHY_MR18_DPLX 0x00000800 // Duplex Mode -#define PHY_MR18_RATE 0x00000400 // Rate -#define PHY_MR18_RXSD 0x00000200 // Receive Detection -#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR19 register. -// -//***************************************************************************** -#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection -#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion - // loss -#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion - // loss -#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion - // loss -#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion - // loss - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR23 register. -// -//***************************************************************************** -#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source -#define PHY_MR23_LED1_LINK 0x00000000 // Link OK -#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1) -#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode -#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode -#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex -#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX - // Activity -#define PHY_MR23_LED0_M 0x0000000F // LED0 Source -#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0) -#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity -#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode -#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode -#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex -#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX - // Activity - -//***************************************************************************** -// -// The following are defines for the bit fields in the PHY_MR24 register. -// -//***************************************************************************** -#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode -#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable -#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration -#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete -#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed -#define PHY_MR24_MDIX_SD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCC register. -// -//***************************************************************************** -#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter -#define HIB_RTCC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM0 register. -// -//***************************************************************************** -#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 -#define HIB_RTCM0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM1 register. -// -//***************************************************************************** -#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1 -#define HIB_RTCM1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCLD register. -// -//***************************************************************************** -#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load -#define HIB_RTCLD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CTL register. -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable -#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable -#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable -#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable -#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable -#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select -#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request -#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IM register. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask -#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Mask -#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask -#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RIS register. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt - // Status -#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw - // Interrupt Status -#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status -#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_MIS register. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Status -#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Status -#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt - // Status -#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IC register. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Clear -#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Clear -#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt - // Clear -#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCT register. -// -//***************************************************************************** -#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value -#define HIB_RTCT_TRIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_DATA register. -// -//***************************************************************************** -#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data -#define HIB_DATA_RTD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMA register. -// -//***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset -#define FLASH_FMA_OFFSET_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMD register. -// -//***************************************************************************** -#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value -#define FLASH_FMD_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit Register Value -#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory -#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory -#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status -#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask -#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCMISC register. -// -//***************************************************************************** -#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value -#define FLASH_USECRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERDBG register. -// -//***************************************************************************** -#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written -#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data -#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1 -#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0 -#define FLASH_USERDBG_DATA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG0 register. -// -//***************************************************************************** -#define FLASH_USERREG0_NW 0x80000000 // Not Written -#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data -#define FLASH_USERREG0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG1 register. -// -//***************************************************************************** -#define FLASH_USERREG1_NW 0x80000000 // Not Written -#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data -#define FLASH_USERREG1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the erase size of the FLASH block that is -// erased by an erase operation, and the protect size is the size of the FLASH -// block that is protected by each protection register. -// -//***************************************************************************** -#define FLASH_PROTECT_SIZE 0x00000800 -#define FLASH_ERASE_SIZE 0x00000400 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version -#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 - // register format -#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(R) Fury-class devices -#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision -#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) -#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer - // revision) -#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer - // revision) -#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision -#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major - // revision update -#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change -#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version -#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1 - // register format -#define SYSCTL_DID1_FAM_M 0x0F000000 // Family -#define SYSCTL_DID1_FAM_STELLARIS \ - 0x00000000 // Stellaris family of - // microcontollers, that is, all - // devices with external part - // numbers starting with LM3S -#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number -#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 -#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package -#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C - // to 70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range - // (-40C to 85C) -#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C - // to 105C) -#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type -#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package -#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package -#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package -#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance -#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash -#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift -#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present -#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present -#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present -#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider -#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock - // with a PLL divider of 4 -#define SYSCTL_DC1_ADCSPD_M 0x00000300 // Max ADC Speed -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second -#define SYSCTL_DC1_MPU 0x00000080 // MPU Present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present -#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present -#define SYSCTL_DC1_PLL 0x00000010 // PLL Present -#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present -#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present -#define SYSCTL_DC1_SWD 0x00000002 // SWD Present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present -#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present -#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present -#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present -#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present -#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present -#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present -#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50 -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45 -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40 -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35 -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30 -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25 -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75 -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70 -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65 -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60 -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR0 register. -// -//***************************************************************************** -#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control -#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control -#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control -#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control -#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR1 register. -// -//***************************************************************************** -#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control -#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control -#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control -#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control -#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control -#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control -#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control -#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control -#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control -#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control -#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR2 register. -// -//***************************************************************************** -#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control -#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control -#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control -#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control -#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control -#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control -#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control -#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control -#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RIS register. -// -//***************************************************************************** -#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status -#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_IMC register. -// -//***************************************************************************** -#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask -#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MISC register. -// -//***************************************************************************** -#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status -#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_SW 0x00000010 // Software Reset -#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset -#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset -#define SYSCTL_RESC_EXT 0x00000001 // External Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating -#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider -#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor -#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass -#define SYSCTL_RCC_XTAL_M 0x000003C0 // Crystal Value -#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1 MHz -#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432 MHz -#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2 MHz -#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576 MHz -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz -#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz -#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz -#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 -#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable -#define SYSCTL_RCC_SYSDIV_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value -#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value -#define SYSCTL_PLLCFG_F_S 5 -#define SYSCTL_PLLCFG_R_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 -#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz -#define SYSCTL_RCC2_SYSDIV2_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC0 register. -// -//***************************************************************************** -#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control -#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_RCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed -#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second -#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second -#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC1 register. -// -//***************************************************************************** -#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC2 register. -// -//***************************************************************************** -#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control -#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control -#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC0 register. -// -//***************************************************************************** -#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control -#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_SCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed -#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second -#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second -#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second -#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC1 register. -// -//***************************************************************************** -#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC2 register. -// -//***************************************************************************** -#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control -#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control -#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC0 register. -// -//***************************************************************************** -#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control -#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC1 register. -// -//***************************************************************************** -#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC2 register. -// -//***************************************************************************** -#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control -#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control -#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override -#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1 -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz -#define SYSCTL_DSLPCLKCFG_D_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // Set pending SysTick interrupt -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // Clear pending SysTick interrupt -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask -#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none -#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only -#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw -#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none -#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask -#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask -#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable -#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable -#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable -#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable -#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable -#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable -#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable -#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask -#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes -#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes -#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes -#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes -#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes -#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes -#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes -#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes -#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes -#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes -#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes -#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes -#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes -#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes -#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes -#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes -#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes -#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes -#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes -#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes -#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes -#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes -#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes -#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes -#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes -#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes -#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes -#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// Deprecated defines for the Watchdog -// -//***************************************************************************** -#define WATCHDOG_LOAD_R (*((volatile unsigned long *)0x40000000)) -#define WATCHDOG_VALUE_R (*((volatile unsigned long *)0x40000004)) -#define WATCHDOG_CTL_R (*((volatile unsigned long *)0x40000008)) -#define WATCHDOG_ICR_R (*((volatile unsigned long *)0x4000000C)) -#define WATCHDOG_RIS_R (*((volatile unsigned long *)0x40000010)) -#define WATCHDOG_MIS_R (*((volatile unsigned long *)0x40000014)) -#define WATCHDOG_TEST_R (*((volatile unsigned long *)0x40000418)) -#define WATCHDOG_LOCK_R (*((volatile unsigned long *)0x40000C00)) - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_IC 0x00000001 // Clear Interrupt - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_IM 0x00000001 // Interrupt Mask - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the the interpretation of the data -// in the SSFIFOx when the ADC TMLB is enabled. register. -// -//***************************************************************************** -#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter -#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator -#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator -#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator -#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator -#define ADC_TMLB_CNT_S 6 // Sample counter shift -#define ADC_TMLB_MUX_S 0 // Input channel number shift - -//***************************************************************************** -// -// Deprecated defines for the ADC register offsets. -// -//***************************************************************************** -#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000)) -#define ADC_RIS_R (*((volatile unsigned long *)0x40038004)) -#define ADC_IM_R (*((volatile unsigned long *)0x40038008)) -#define ADC_ISC_R (*((volatile unsigned long *)0x4003800C)) -#define ADC_OSTAT_R (*((volatile unsigned long *)0x40038010)) -#define ADC_EMUX_R (*((volatile unsigned long *)0x40038014)) -#define ADC_USTAT_R (*((volatile unsigned long *)0x40038018)) -#define ADC_SSPRI_R (*((volatile unsigned long *)0x40038020)) -#define ADC_PSSI_R (*((volatile unsigned long *)0x40038028)) -#define ADC_SAC_R (*((volatile unsigned long *)0x40038030)) -#define ADC_SSMUX0_R (*((volatile unsigned long *)0x40038040)) -#define ADC_SSCTL0_R (*((volatile unsigned long *)0x40038044)) -#define ADC_SSFIFO0_R (*((volatile unsigned long *)0x40038048)) -#define ADC_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C)) -#define ADC_SSMUX1_R (*((volatile unsigned long *)0x40038060)) -#define ADC_SSCTL1_R (*((volatile unsigned long *)0x40038064)) -#define ADC_SSFIFO1_R (*((volatile unsigned long *)0x40038068)) -#define ADC_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C)) -#define ADC_SSMUX2_R (*((volatile unsigned long *)0x40038080)) -#define ADC_SSCTL2_R (*((volatile unsigned long *)0x40038084)) -#define ADC_SSFIFO2_R (*((volatile unsigned long *)0x40038088)) -#define ADC_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C)) -#define ADC_SSMUX3_R (*((volatile unsigned long *)0x400380A0)) -#define ADC_SSCTL3_R (*((volatile unsigned long *)0x400380A4)) -#define ADC_SSFIFO3_R (*((volatile unsigned long *)0x400380A8)) -#define ADC_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC)) -#define ADC_TMLB_R (*((volatile unsigned long *)0x40038100)) - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key -#define FLASH_FMC_WRKEY_S 16 - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // QFP package - -//***************************************************************************** -// -// Deprecated defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C)) - -#endif - -#endif // __LM3S8962_H__ diff --git a/bsp/lm3s8962/project.Uv2 b/bsp/lm3s8962/project.Uv2 index 16179a344b..2168aad07d 100644 --- a/bsp/lm3s8962/project.Uv2 +++ b/bsp/lm3s8962/project.Uv2 @@ -22,19 +22,24 @@ File 3,1, File 3,1, File 3,1, File 3,1, +File 3,1, File 3,1, File 3,1, +File 3,1, File 3,1, File 3,1, File 3,1, File 3,1, File 3,1, File 3,1, +File 3,1, File 3,1, +File 3,1, File 3,1, File 3,1, File 3,1, File 3,1, +File 3,1, File 3,1, File 3,1, File 3,1, @@ -177,7 +182,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' RV_STAVEC () ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ADSCMISC () - ADSCDEFN () + ADSCDEFN (PART_LM3S8962) ADSCUDEF () ADSCINCD (..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\include;drivers;..\..\components\dfs;.;Libraries;applications;..\..\components\net\lwip\src\arch\include;..\..\libcpu\arm\cortex-m3;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\finsh;..\..\components\net\lwip\src\include\netif;..\..\components\dfs\include) ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } diff --git a/bsp/lm3s8962/rtconfig.py b/bsp/lm3s8962/rtconfig.py index caef9a28a4..9c753dee70 100644 --- a/bsp/lm3s8962/rtconfig.py +++ b/bsp/lm3s8962/rtconfig.py @@ -3,6 +3,9 @@ ARCH='arm' CPU='cortex-m3' CROSS_TOOL = 'keil' +#device options +PART_TYPE = 'PART_LM3S8962' + if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' diff --git a/bsp/lm4f232/Libraries/SConscript b/bsp/lm4f232/Libraries/SConscript index 27ff3b7105..784d61658a 100644 --- a/bsp/lm4f232/Libraries/SConscript +++ b/bsp/lm4f232/Libraries/SConscript @@ -6,6 +6,10 @@ from building import * cwd = GetCurrentDir() src = Glob('driverlib/*.c') +# cortex-m3 no FPU. +if rtconfig.PART_TYPE.startswith('PART_LM4F') != True: + SrcRemove(src, 'fpu.c') + # add for startup script if rtconfig.CROSS_TOOL == 'gcc': src += ['startup/gcc/start_gcc.s'] @@ -16,6 +20,7 @@ elif rtconfig.CROSS_TOOL == 'iar': CPPPATH = [cwd] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) +CPPDEFINES = [rtconfig.PART_TYPE] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/lm4f232/Libraries/driverlib/Makefile b/bsp/lm4f232/Libraries/driverlib/Makefile deleted file mode 100644 index 7d4fb09a66..0000000000 --- a/bsp/lm4f232/Libraries/driverlib/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -#****************************************************************************** -# -# Makefile - Rules for building the driver library. -# -# Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. -# Software License Agreement -# -# Texas Instruments (TI) is supplying this software for use solely and -# exclusively on TI's microcontroller products. The software is owned by -# TI and/or its suppliers, and is protected under applicable copyright -# laws. You may not combine this software with "viral" open-source -# software in order to form a larger program. -# -# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -# DAMAGES, FOR ANY REASON WHATSOEVER. -# -# This is part of revision 8049 of the Stellaris Peripheral Driver Library. -# -#****************************************************************************** - -all: - @make -f Makefile.driverlib-cm3 - @make -f Makefile.driverlib-cm4f - -clean: - @make -f Makefile.driverlib-cm3 clean - @make -f Makefile.driverlib-cm4f clean - -realclean: - @make -f Makefile.driverlib-cm3 realclean - @make -f Makefile.driverlib-cm4f realclean diff --git a/bsp/lm4f232/Libraries/driverlib/Makefile.driverlib-cm4f b/bsp/lm4f232/Libraries/driverlib/Makefile.driverlib-cm4f deleted file mode 100644 index cf8a4edfe0..0000000000 --- a/bsp/lm4f232/Libraries/driverlib/Makefile.driverlib-cm4f +++ /dev/null @@ -1,106 +0,0 @@ -#****************************************************************************** -# -# Makefile.driverlib-cm4f - Rules for building the driver library. -# -# Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. -# Software License Agreement -# -# Texas Instruments (TI) is supplying this software for use solely and -# exclusively on TI's microcontroller products. The software is owned by -# TI and/or its suppliers, and is protected under applicable copyright -# laws. You may not combine this software with "viral" open-source -# software in order to form a larger program. -# -# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -# DAMAGES, FOR ANY REASON WHATSOEVER. -# -# This is part of revision 8049 of the Stellaris Peripheral Driver Library. -# -#****************************************************************************** - -# -# Defines the directory suffix that this project uses. -# -SUFFIX=-cm4f - -# -# Set the processor variant. -# -VARIANT=cm4f - -# -# The base directory for StellarisWare. -# -ROOT=.. - -# -# Include the common make definitions. -# -include ${ROOT}/makedefs - -# -# Where to find header files that do not live in the source directory. -# -IPATH=.. - -# -# The default rule, which causes the driver library to be built. -# -all: ${COMPILER}-cm4f -all: ${COMPILER}-cm4f/libdriver-cm4f.a - -# -# The rule to clean out all the build products. -# -clean: - @rm -rf ${COMPILER}-cm4f ${wildcard *~} - -# -# The rule to create the target directory. -# -${COMPILER}-cm4f: - @mkdir -p ${COMPILER}-cm4f - -# -# Rules for building the driver library. -# -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/adc.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/can.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/comp.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/cpu.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/eeprom.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/epi.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/ethernet.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/fan.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/flash.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/fpu.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/gpio.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/hibernate.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/i2c.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/i2s.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/interrupt.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/lpc.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/mpu.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/peci.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/pwm.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/qei.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/ssi.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/sysctl.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/sysexc.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/systick.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/timer.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/uart.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/udma.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/usb.o -${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/watchdog.o - -# -# Include the automatically generated dependency files. -# -ifneq (${MAKECMDGOALS},clean) --include ${wildcard ${COMPILER}-cm4f/*.d} __dummy__ -endif diff --git a/bsp/lm4f232/Libraries/driverlib/adc.c b/bsp/lm4f232/Libraries/driverlib/adc.c index b03c91aa91..c306389a5b 100644 --- a/bsp/lm4f232/Libraries/driverlib/adc.c +++ b/bsp/lm4f232/Libraries/driverlib/adc.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -72,10 +72,10 @@ static unsigned char g_pucOversampleFactor[3]; //! ADC sample sequence interrupt occurs. //! //! This function sets the handler to be called when a sample sequence -//! interrupt occurs. This will enable the global interrupt in the interrupt -//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It -//! is the interrupt handler's responsibility to clear the interrupt source via -//! ADCIntClear(). +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; the sequence interrupt must be enabled with +//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via ADCIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -119,9 +119,9 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This function unregisters the interrupt handler. This will disable the -//! global interrupt in the interrupt controller; the sequence interrupt must -//! be disabled via ADCIntDisable(). +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller; the sequence interrupt +//! must be disabled via ADCIntDisable(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -227,9 +227,9 @@ ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the specified sample sequence. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. +//! This function returns the interrupt status for the specified sample +//! sequence. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. //! //! \return The current raw or masked interrupt status. // @@ -283,10 +283,10 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulSequenceNum is the sample sequence number. //! //! The specified sample sequence interrupt is cleared, so that it no longer -//! asserts. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. +//! asserts. This function must be called in the interrupt handler to keep +//! the interrupt from being triggered again immediately upon exit. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -381,10 +381,10 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) //! respect to the other sample sequences. //! //! This function configures the initiation criteria for a sample sequence. -//! Valid sample sequences range from zero to three; sequence zero will capture -//! up to eight samples, sequences one and two will capture up to four samples, -//! and sequence three will capture a single sample. The trigger condition and -//! priority (with respect to other sample sequence execution) is set. +//! Valid sample sequencers range from zero to three; sequencer zero captures +//! up to eight samples, sequencers one and two capture up to four samples, +//! and sequencer three captures a single sample. The trigger condition and +//! priority (with respect to other sample sequencer execution) are set. //! //! The \e ulTrigger parameter can take on the following values: //! @@ -397,7 +397,9 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) //! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog //! comparator; configured with ComparatorConfigure(). //! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port -//! B4 pin. +//! B4 pin. Note that some microcontrollers can +//! select from any GPIO using the +//! GPIOADCTriggerEnable() function. //! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with //! TimerControlTrigger(). //! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; @@ -475,31 +477,32 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulStep is the step to be configured. //! \param ulConfig is the configuration of this step; must be a logical OR of //! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the -//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15), and one of +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of //! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). //! -//! This function will set the configuration of the ADC for one step of a -//! sample sequence. The ADC can be configured for single-ended or -//! differential operation (the \b ADC_CTL_D bit selects differential -//! operation when set), the channel to be sampled can be chosen (the -//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal -//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally, -//! this step can be defined as the last in the sequence (the \b ADC_CTL_END -//! bit) and it can be configured to cause an interrupt when the step is -//! complete (the \b ADC_CTL_IE bit). If the digital comparators are present -//! on the device, this step may also be configured to send the ADC sample to -//! the selected comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. -//! The configuration is used by the ADC at the appropriate time when the -//! trigger for this sequence occurs. +//! This function configures the ADC for one step of a sample sequence. The +//! ADC can be configured for single-ended or differential operation +//! (the \b ADC_CTL_D bit selects differential operation when set), the +//! channel to be sampled can be chosen (the \b ADC_CTL_CH0 through +//! \b ADC_CTL_CH23 values), and the internal temperature sensor can be +//! selected (the \b ADC_CTL_TS bit). Additionally, this step can be defined +//! as the last in the sequence (the \b ADC_CTL_END bit) and it can be +//! configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). If the digital comparators are present on the device, +//! this step may also be configured to send the ADC sample to the selected +//! comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration +//! is used by the ADC at the appropriate time when the trigger for +//! this sequence occurs. //! //! \note If the Digitial Comparator is present and enabled using the -//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample will NOT be +//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT //! written into the ADC sequence data FIFO. //! //! The \e ulStep parameter determines the order in which the samples are //! captured by the ADC when the trigger occurs. It can range from zero to -//! seven for the first sample sequence, from zero to three for the second and -//! third sample sequence, and can only be zero for the fourth sample sequence. +//! seven for the first sample sequencer, from zero to three for the second and +//! third sample sequencer, and can only be zero for the fourth sample +//! sequencer. //! //! Differential mode only works with adjacent channel pairs (for example, 0 //! and 1). The channel select must be the number of the channel pair to @@ -601,9 +604,9 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This determines if a sample sequence overflow has occurred. This will -//! happen if the captured samples are not read from the FIFO before the next -//! trigger occurs. +//! This function determines if a sample sequence overflow has occurred. +//! Overflow happens if the captured samples are not read from the FIFO before +//! the next trigger occurs. //! //! \return Returns zero if there was not an overflow, and non-zero if there //! was. @@ -631,9 +634,9 @@ ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This will clear an overflow condition on one of the sample sequences. The -//! overflow condition must be cleared in order to detect a subsequent overflow -//! condition (it otherwise causes no harm). +//! This function clears an overflow condition on one of the sample sequences. +//! The overflow condition must be cleared in order to detect a subsequent +//! overflow condition (it otherwise causes no harm). //! //! \return None. // @@ -660,8 +663,8 @@ ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This determines if a sample sequence underflow has occurred. This will -//! happen if too many samples are read from the FIFO. +//! This function determines if a sample sequence underflow has occurred. +//! Underflow happens if too many samples are read from the FIFO. //! //! \return Returns zero if there was not an underflow, and non-zero if there //! was. @@ -689,8 +692,8 @@ ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulBase is the base address of the ADC module. //! \param ulSequenceNum is the sample sequence number. //! -//! This will clear an underflow condition on one of the sample sequences. The -//! underflow condition must be cleared in order to detect a subsequent +//! This function clears an underflow condition on one of the sample sequencers. +//! The underflow condition must be cleared in order to detect a subsequent //! underflow condition (it otherwise causes no harm). //! //! \return None. @@ -719,12 +722,12 @@ ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum) //! \param ulSequenceNum is the sample sequence number. //! \param pulBuffer is the address where the data is stored. //! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer. The number of samples available in the hardware -//! FIFO are copied into the buffer, which is assumed to be large enough to -//! hold that many samples. This will only return the samples that are -//! presently available, which may not be the entire sample sequence if it is -//! in the process of being executed. +//! This function copies data from the specified sample sequencer output FIFO +//! to a memory resident buffer. The number of samples available in the +//! hardware FIFO are copied into the buffer, which is assumed to be large +//! enough to hold that many samples. This function only returns the samples +//! that are presently available, which may not be the entire sample sequence +//! if it is in the process of being executed. //! //! \return Returns the number of samples copied to the buffer. // @@ -949,7 +952,7 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase, //! This function copies data from the specified sample sequence output FIFO to //! a memory resident buffer with software oversampling applied. The requested //! number of samples are copied into the data buffer; if there are not enough -//! samples in the hardware FIFO to satisfy this many oversampled data items +//! samples in the hardware FIFO to satisfy this many oversampled data items, //! then incorrect results are returned. It is the caller's responsibility to //! read only the samples that are available and wait until enough data is //! available, for example as a result of receiving an interrupt. @@ -1012,21 +1015,18 @@ ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, //! be used to provide better resolution on the sampled data. Oversampling is //! accomplished by averaging multiple samples from the same analog input. Six //! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. -//! Specifying an oversampling factor of zero will disable hardware +//! Specifying an oversampling factor of zero disables hardware //! oversampling. //! //! Hardware oversampling applies uniformly to all sample sequencers. It does //! not reduce the depth of the sample sequencers like the software -//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! oversampling APIs; each sample written into the sample sequencer FIFO is a //! fully oversampled analog input reading. //! //! Enabling hardware averaging increases the precision of the ADC at the cost //! of throughput. For example, enabling 4x oversampling reduces the //! throughput of a 250 Ksps ADC to 62.5 Ksps. //! -//! \note Hardware oversampling is available beginning with Rev C0 of the -//! Stellaris microcontroller. -//! //! \return None. // //***************************************************************************** @@ -1064,7 +1064,7 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor) //! \param ulComp is the index of the comparator to configure. //! \param ulConfig is the configuration of the comparator. //! -//! This function will configure a comparator. The \e ulConfig parameter is +//! This function configures a comparator. The \e ulConfig parameter is //! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and //! \b ADC_COMP_INT_xxx values. //! @@ -1191,7 +1191,7 @@ ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp, //! \param bInterrupt is the flag to indicate reset of Interrupt conditions. //! //! Because the digital comparator uses current and previous ADC values, this -//! function is provide to allow the comparator to be reset to its initial +//! function allows the comparator to be reset to its initial //! value to prevent stale data from being used when a sequence is enabled. //! //! \return None. @@ -1285,8 +1285,8 @@ ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) //! //! \param ulBase is the base address of the ADC module. //! -//! This returns the digitial comparator interrupt status bits. This status -//! is sequence agnostic. +//! This function returns the digitial comparator interrupt status bits. This +//! status is sequence agnostic. //! //! \return The current comparator interrupt status. // @@ -1366,7 +1366,7 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef) // // Set the reference. // - HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) | + HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ulRef; } @@ -1397,7 +1397,7 @@ ADCReferenceGet(unsigned long ulBase) // // Return the value of the reference. // - return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF); + return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF_M); } //***************************************************************************** @@ -1411,8 +1411,8 @@ ADCReferenceGet(unsigned long ulBase) //! of \b ADC_RES_12BIT or \b ADC_RES_10BIT. //! //! \note The ADC resolution can only be set on parts that are capable of -//! greater than 10-bit conversions. Consult the data sheet for your part to -//! determine if it is capable of 12-bit conversions. +//! changing ADC resolution mode. Consult the data sheet for your part to +//! determine if it is capable of operating in more than one resolution mode. //! //! \return None. // @@ -1443,9 +1443,9 @@ ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution) //! \b ADC_RES_10BIT. //! //! \note The value returned by this function is only meaningful if used on a -//! part that is capable of higher than 10-bit ADC resolution. Consult the -//! data sheet for your part to determine if it is capable of 12-bit -//! conversions. +//! part that is capable of changing ADC resolution mode. Consult the +//! data sheet for your part to determine if it is capable of operating in +//! more than one resolution mode. //! //! \return The current setting of the ADC resolution. // diff --git a/bsp/lm4f232/Libraries/driverlib/adc.h b/bsp/lm4f232/Libraries/driverlib/adc.h index 86e7b979da..ea1a734e50 100644 --- a/bsp/lm4f232/Libraries/driverlib/adc.h +++ b/bsp/lm4f232/Libraries/driverlib/adc.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/can.c b/bsp/lm4f232/Libraries/driverlib/can.c index 69333be6df..e0f5f7ee18 100644 --- a/bsp/lm4f232/Libraries/driverlib/can.c +++ b/bsp/lm4f232/Libraries/driverlib/can.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -151,8 +151,8 @@ CANBaseValid(unsigned long ulBase) //! //! \param ulBase is the base address of the selected CAN controller //! -//! Given a CAN controller base address, returns the corresponding interrupt -//! number. +//! Given a CAN controller base address, this function returns the +//! corresponding interrupt number. //! //! This function replaces the original CANGetIntNumber() API and performs the //! same actions. A macro is provided in can.h to map the original @@ -552,7 +552,7 @@ CANInit(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller to enable. //! //! Enables the CAN controller for message processing. Once enabled, the -//! controller will automatically transmit any pending frames, and process any +//! controller automatically transmits any pending frames, and processes any //! received frames. The controller can be stopped by calling CANDisable(). //! Prior to calling CANEnable(), CANInit() should have been called to //! initialize the controller and the CAN bus clock should be configured by @@ -583,7 +583,7 @@ CANEnable(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller to disable. //! //! Disables the CAN controller for message processing. When disabled, the -//! controller will no longer automatically process data on the CAN bus. The +//! controller no longer automatically processes data on the CAN bus. The //! controller can be restarted by calling CANEnable(). The state of the CAN //! controller and the message objects in the controller are left as they were //! before this call was made. @@ -614,7 +614,7 @@ CANDisable(unsigned long ulBase) //! \param pClkParms is a pointer to a structure to hold the timing parameters. //! //! This function reads the current configuration of the CAN controller bit -//! clock timing, and stores the resulting information in the structure +//! clock timing and stores the resulting information in the structure //! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the //! values that are returned in the structure pointed to by \e pClkParms. //! @@ -668,24 +668,24 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms) //***************************************************************************** // -//! This function is used to set the CAN bit timing values to a nominal setting -//! based on a desired bit rate. +//! Sets the CAN bit timing values to a nominal setting based on a desired +//! bit rate. //! //! \param ulBase is the base address of the CAN controller. //! \param ulSourceClock is the system clock for the device in Hz. //! \param ulBitRate is the desired bit rate. //! -//! This function will set the CAN bit timing for the bit rate passed in the -//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Since the -//! CAN clock is based off of the system clock the calling function should pass +//! This function sets the CAN bit timing for the bit rate passed in the +//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Because the +//! CAN clock is based off of the system clock, the calling function should pass //! in the source clock rate either by retrieving it from SysCtlClockGet() or //! using a specific value in Hz. The CAN bit timing is calculated assuming a -//! minimal amount of propagation delay, which will work for most cases where +//! minimal amount of propagation delay, which works for most cases where //! the network length is short. If tighter timing requirements or longer //! network lengths are needed, then the CANBitTimingSet() function is //! available for full customization of all of the CAN bit timing values. -//! Since not all bit rates can be matched exactly, the bit rate is set to the -//! value closest to the desired bit rate without being higher than the +//! Because not all bit rates can be matched exactly, the bit rate is set to +//! the value closest to the desired bit rate without being higher than the //! \e ulBitRate value. //! //! \note On some devices the source clock is fixed at 8MHz so the @@ -832,12 +832,12 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock, //! quantum time is determined by the \e pClkParms->ulQuantumPrescaler value, //! which specifies the divisor for the CAN module clock. //! -//! The total bit time, in quanta, will be the sum of the two Seg parameters, +//! The total bit time, in quanta, is the sum of the two Seg parameters, //! as follows: //! //! bit_time_q = ulSyncPropPhase1Seg + ulPhase2Seg + 1 //! -//! Note that the Sync_Seg is always one quantum in duration, and will be added +//! Note that the Sync_Seg is always one quantum in duration, and is added //! to derive the correct duration of Prop_Seg and Phase1_Seg. //! //! The equation to determine the actual bit rate is as follows: @@ -845,8 +845,8 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock, //! CAN Clock / //! ((\e ulSyncPropPhase1Seg + \e ulPhase2Seg + 1) * (\e ulQuantumPrescaler)) //! -//! This means that with \e ulSyncPropPhase1Seg = 4, \e ulPhase2Seg = 1, -//! \e ulQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be +//! Thus with \e ulSyncPropPhase1Seg = 4, \e ulPhase2Seg = 1, +//! \e ulQuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is //! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. //! //! This function replaces the original CANSetBitTiming() API and performs the @@ -987,7 +987,7 @@ CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! \param ulBase is the base address of the controller. //! //! This function unregisters the previously registered interrupt handler and -//! disables the interrupt on the interrupt controller. +//! disables the interrupt in the interrupt controller. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1028,8 +1028,8 @@ CANIntUnregister(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables specific interrupt sources of the CAN controller. Only enabled -//! sources will cause a processor interrupt. +//! This function enables specific interrupt sources of the CAN controller. +//! Only enabled sources cause a processor interrupt. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! @@ -1043,7 +1043,7 @@ CANIntUnregister(unsigned long ulBase) //! an interrupt, that message object must have interrupts enabled (see //! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the //! controller enters the ``bus off'' condition, or if the error counters reach -//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few +//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few //! status conditions and may provide more interrupts than the application //! needs to handle. When an interrupt occurs, use CANIntStatus() to determine //! the cause. @@ -1106,19 +1106,19 @@ CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase is the base address of the CAN controller. //! \param eIntStsReg indicates which interrupt status register to read //! -//! Returns the value of one of two interrupt status registers. The interrupt -//! status register read is determined by the \e eIntStsReg parameter, which -//! can have one of the following values: +//! This function returns the value of one of two interrupt status registers. +//! The interrupt status register read is determined by the \e eIntStsReg +//! parameter, which can have one of the following values: //! //! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt //! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message //! objects //! //! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register -//! and indicates the cause of the interrupt. It will be a value of +//! and indicates the cause of the interrupt. The value returned is //! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, //! the status register should be read with the CANStatusGet() function. -//! Calling this function to read the status will also clear the status +//! Calling this function to read the status also clears the status //! interrupt. If the value of the interrupt register is in the range 1-32, //! then this indicates the number of the highest priority message object that //! has an interrupt pending. The message object interrupt can be cleared by @@ -1128,9 +1128,9 @@ CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! cleared before returning from the interrupt. //! //! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects -//! have pending interrupts. This can be used to discover all of the pending -//! interrupts at once, as opposed to repeatedly reading the interrupt register -//! by using \b CAN_INT_STS_CAUSE. +//! have pending interrupts. This value can be used to discover all of the +//! pending interrupts at once, as opposed to repeatedly reading the interrupt +//! register by using \b CAN_INT_STS_CAUSE. //! //! \return Returns the value of one of the interrupt status registers. // @@ -1205,14 +1205,14 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg) //! - 1-32 - Clears the specified message object interrupt //! //! It is not necessary to use this function to clear an interrupt. This -//! should only be used if the application wants to clear an interrupt source -//! without taking the normal interrupt action. +//! function should only be used if the application wants to clear an interrupt +//! source without taking the normal interrupt action. //! //! Normally, the status interrupt is cleared by reading the controller status //! using CANStatusGet(). A specific message object interrupt is normally //! cleared by reading the message object using CANMessageGet(). //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1277,9 +1277,9 @@ CANIntClear(unsigned long ulBase, unsigned long ulIntClr) //! \param ulBase is the base address of the CAN controller. //! \param bAutoRetry enables automatic retransmission. //! -//! Enables or disables automatic retransmission of messages with detected -//! errors. If \e bAutoRetry is \b true, then automatic retransmission is -//! enabled, otherwise it is disabled. +//! This function enables or disables automatic retransmission of messages with +//! detected errors. If \e bAutoRetry is \b true, then automatic retransmission +//! is enabled, otherwise it is disabled. //! //! \return None. // @@ -1326,7 +1326,7 @@ CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry) //! //! \param ulBase is the base address of the CAN controller. //! -//! Reads the current setting for the automatic retransmission in the CAN +//! This function reads the current setting for automatic retransmission in the CAN //! controller and returns it to the caller. //! //! \return Returns \b true if automatic retransmission is enabled, \b false @@ -1365,7 +1365,8 @@ CANRetryGet(unsigned long ulBase) //! \param ulBase is the base address of the CAN controller. //! \param eStatusReg is the status register to read. //! -//! Reads a status register of the CAN controller and returns it to the caller. +//! This function reads a status register of the CAN controller and returns it +//! to the caller. //! The different status registers are: //! //! - \b CAN_STS_CONTROL - the main controller status @@ -1374,9 +1375,9 @@ CANRetryGet(unsigned long ulBase) //! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration //! //! When reading the main controller status register, a pending status -//! interrupt will be cleared. This should be used in the interrupt handler -//! for the CAN controller if the cause is a status interrupt. The controller -//! status register fields are as follows: +//! interrupt is cleared. This parameter should be used in the interrupt +//! handler for the CAN controller if the cause is a status interrupt. The +//! controller status register fields are as follows: //! //! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition //! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 @@ -1396,20 +1397,21 @@ CANRetryGet(unsigned long ulBase) //! dominant mode //! - \b CAN_STATUS_LEC_CRC - CRC error in received message //! -//! The remaining status registers are 32-bit bit maps to the message objects. -//! They can be used to quickly obtain information about the status of all the -//! message objects without needing to query each one. They contain the -//! following information: +//! The remaining status registers consist of 32-bit-wide bit maps to the +//! message objects. They can be used to quickly obtain information about the +//! status of all the message objects without needing to query each one. They +//! contain the following information: //! -//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that -//! means that a transmission is pending on that object. The application can -//! use this to determine which objects are still waiting to send a message. -//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means -//! that a new message has been received in that object, and has not yet been -//! picked up by the host application -//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means -//! it has a valid configuration programmed. The host application can use this -//! to determine which message objects are empty/unused. +//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a +//! transmission is pending on that object. The application can use this +//! information to determine which objects are still waiting to send a +//! message. +//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new +//! message has been received in that object, and has not yet been picked up +//! by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object +//! has a valid configuration programmed. The host application can use this +//! information to determine which message objects are empty/unused. //! //! \return Returns the value of the status register. // @@ -1488,14 +1490,14 @@ CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg) //! \param pulRxCount is a pointer to storage for the receive error counter. //! \param pulTxCount is a pointer to storage for the transmit error counter. //! -//! Reads the error counter register and returns the transmit and receive error -//! counts to the caller along with a flag indicating if the controller receive -//! counter has reached the error passive limit. The values of the receive and -//! transmit error counters are returned through the pointers provided as -//! parameters. +//! This function reads the error counter register and returns the transmit and +//! receive error counts to the caller along with a flag indicating if the +//! controller receive counter has reached the error passive limit. The values +//! of the receive and transmit error counters are returned through the pointers +//! provided as parameters. //! -//! After this call, \e *pulRxCount will hold the current receive error count -//! and \e *pulTxCount will hold the current transmit error count. +//! After this call, \e *pulRxCount holds the current receive error count +//! and \e *pulTxCount holds the current transmit error count. //! //! \return Returns \b true if the receive error count has reached the error //! passive limit, and \b false if the error count is below the error passive @@ -1542,10 +1544,10 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! \param eMsgType indicates the type of message for this object. //! //! This function is used to configure any one of the 32 message objects in the -//! CAN controller. A message object can be configured as any type of CAN -//! message object as well as several options for automatic transmission and -//! reception. This call also allows the message object to be configured to -//! generate interrupts on completion of message receipt or transmission. The +//! CAN controller. A message object can be configured to be any type of CAN +//! message object as well as to use automatic transmission and reception. +//! This call also allows the message object to be configured to generate +//! interrupts on completion of message receipt or transmission. The //! message object can also be configured with a filter/mask so that actions //! are only taken when a message that meets certain parameters is seen on the //! CAN bus. @@ -1570,13 +1572,13 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. //! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the //! identifier mask specified by \e ulMsgIDMask. -//! - \e ulMsgLen - the number of bytes in the message data. This should be -//! non-zero even for a remote frame; it should match the expected bytes of the -//! data responding data frame. +//! - \e ulMsgLen - the number of bytes in the message data. This parameter +//! should be non-zero even for a remote frame; it should match the expected +//! bytes of data in the responding data frame. //! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a //! data frame. //! -//! \b Example: To send a data frame or remote frame(in response to a remote +//! \b Example: To send a data frame or remote frame (in response to a remote //! request), take the following steps: //! //! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. @@ -1598,7 +1600,7 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! -# Set \e pMsgObject->ulFlags as follows: //! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data frame //! is received. -//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based filtering. //! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data //! frame. //! -# The buffer pointed to by \e pMsgObject->pucMsgData is not used by this @@ -1606,7 +1608,7 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, //! -# Call this function with \e ulObjID set to one of the 32 object buffers. //! //! If you specify a message object buffer that already contains a message -//! definition, it will be overwritten. +//! definition, it is overwritten. //! //! \return None. // @@ -1944,27 +1946,27 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID, //! cleared. //! //! This function is used to read the contents of one of the 32 message objects -//! in the CAN controller, and return it to the caller. The data returned is +//! in the CAN controller and return it to the caller. The data returned is //! stored in the fields of the caller-supplied structure pointed to by //! \e pMsgObject. The data consists of all of the parts of a CAN message, //! plus some control and status information. //! -//! Normally this is used to read a message object that has received and stored -//! a CAN message with a certain identifier. However, this could also be used -//! to read the contents of a message object in order to load the fields of the -//! structure in case only part of the structure needs to be changed from a -//! previous setting. +//! Normally, this function is used to read a message object that has received +//! and stored a CAN message with a certain identifier. However, this function +//! could also be used to read the contents of a message object in order to +//! load the fields of the structure in case only part of the structure must +//! be changed from a previous setting. //! -//! When using CANMessageGet, all of the same fields of the structure are +//! When using CANMessageGet(), all of the same fields of the structure are //! populated in the same way as when the CANMessageSet() function is used, //! with the following exceptions: //! //! \e pMsgObject->ulFlags: //! -//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it +//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it //! was read //! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on -//! this message object, and not read by the host before being overwritten. +//! this message object and not read by the host before being overwritten. //! //! \return None. // @@ -2204,8 +2206,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID, //! \param ulObjID is the message object number to disable (1-32). //! //! This function frees the specified message object from use. Once a message -//! object has been ``cleared,'' it will no longer automatically send or -//! receive messages, or generate interrupts. +//! object has been ``cleared,'' it no longer automatically sends or +//! receives messages, nor does it generate interrupts. //! //! \return None. // diff --git a/bsp/lm4f232/Libraries/driverlib/can.h b/bsp/lm4f232/Libraries/driverlib/can.h index 38352940eb..369a4f009a 100644 --- a/bsp/lm4f232/Libraries/driverlib/can.h +++ b/bsp/lm4f232/Libraries/driverlib/can.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/comp.c b/bsp/lm4f232/Libraries/driverlib/comp.c index 3e946cc775..0ed7d8377d 100644 --- a/bsp/lm4f232/Libraries/driverlib/comp.c +++ b/bsp/lm4f232/Libraries/driverlib/comp.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -212,7 +212,7 @@ ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) //! \param pfnHandler is a pointer to the function to be called when the //! comparator interrupt occurs. //! -//! This sets the handler to be called when the comparator interrupt occurs +//! This function sets the handler to be called when the comparator interrupt occurs //! and enables the interrupt in the interrupt controller. It is the interrupt //! handler's responsibility to clear the interrupt source via //! ComparatorIntClear(). @@ -257,7 +257,7 @@ ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, //! \param ulComp is the index of the comparator. //! //! This function clears the handler to be called when a comparator interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller +//! occurs. This function also masks off the interrupt in the interrupt controller //! so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt @@ -299,7 +299,7 @@ ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) //! \param ulComp is the index of the comparator. //! //! This function enables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected +//! comparator. Only enabled comparator interrupts can be reflected //! to the processor. //! //! \return None. @@ -328,7 +328,7 @@ ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) //! \param ulComp is the index of the comparator. //! //! This function disables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected +//! comparator. Only enabled comparator interrupts can be reflected //! to the processor. //! //! \return None. @@ -358,7 +358,7 @@ ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) //! \param bMasked is \b false if the raw interrupt status is required and //! \b true if the masked interrupt status is required. //! -//! This returns the interrupt status for the comparator. Either the raw or +//! This function returns the interrupt status for the comparator. Either the raw or //! the masked interrupt status can be returned. //! //! \return \b true if the interrupt is asserted and \b false if it is not @@ -401,7 +401,7 @@ ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, //! being called again immediately upon exit. Note that for a level-triggered //! interrupt, the interrupt cannot be cleared until it stops asserting. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid diff --git a/bsp/lm4f232/Libraries/driverlib/comp.h b/bsp/lm4f232/Libraries/driverlib/comp.h index 274fb2887d..894295687a 100644 --- a/bsp/lm4f232/Libraries/driverlib/comp.h +++ b/bsp/lm4f232/Libraries/driverlib/comp.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/cpu.c b/bsp/lm4f232/Libraries/driverlib/cpu.c index 8ee10fe60d..80b74ab393 100644 --- a/bsp/lm4f232/Libraries/driverlib/cpu.c +++ b/bsp/lm4f232/Libraries/driverlib/cpu.c @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/cpu.h b/bsp/lm4f232/Libraries/driverlib/cpu.h index b5c6c26e3a..edb76b775b 100644 --- a/bsp/lm4f232/Libraries/driverlib/cpu.h +++ b/bsp/lm4f232/Libraries/driverlib/cpu.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/cr_driverlib-cm4f.xml b/bsp/lm4f232/Libraries/driverlib/cr_driverlib-cm4f.xml deleted file mode 100644 index 301eebbaa1..0000000000 --- a/bsp/lm4f232/Libraries/driverlib/cr_driverlib-cm4f.xml +++ /dev/null @@ -1,71 +0,0 @@ - - - - - {(Makefile|Makefile\..*|ccs-.*|codered-.*|ewarm-.*|gcc-.*|rvmdk-.*|sourcerygxx-.*)} - {.*\.(ewd|ewp|eww|icf|Opt|sct|sgxx|Uv2|uvopt|uvproj|xml|ld|cmd)} - - - inc - - - codered - - - DEBUG - - - NDEBUG - - - __CODE_RED - __NEWLIB__ - codered - - - -Os - - - -Os - - - -Os - - - -Os - - - ${workspace_loc:/} - - diff --git a/bsp/lm4f232/Libraries/driverlib/debug.h b/bsp/lm4f232/Libraries/driverlib/debug.h index ae07377e40..a0fa0f8100 100644 --- a/bsp/lm4f232/Libraries/driverlib/debug.h +++ b/bsp/lm4f232/Libraries/driverlib/debug.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.ewp b/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.ewp deleted file mode 100644 index 2e466a01df..0000000000 --- a/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.ewp +++ /dev/null @@ -1,857 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - General - 3 - - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 19 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 5 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Source - - $PROJ_DIR$\adc.c - - - $PROJ_DIR$\can.c - - - $PROJ_DIR$\comp.c - - - $PROJ_DIR$\cpu.c - - - $PROJ_DIR$\eeprom.c - - - $PROJ_DIR$\epi.c - - - $PROJ_DIR$\ethernet.c - - - $PROJ_DIR$\fan.c - - - $PROJ_DIR$\flash.c - - - $PROJ_DIR$\fpu.c - - - $PROJ_DIR$\gpio.c - - - $PROJ_DIR$\hibernate.c - - - $PROJ_DIR$\i2c.c - - - $PROJ_DIR$\i2s.c - - - $PROJ_DIR$\interrupt.c - - - $PROJ_DIR$\lpc.c - - - $PROJ_DIR$\mpu.c - - - $PROJ_DIR$\peci.c - - - $PROJ_DIR$\pwm.c - - - $PROJ_DIR$\qei.c - - - $PROJ_DIR$\ssi.c - - - $PROJ_DIR$\sysctl.c - - - $PROJ_DIR$\sysexc.c - - - $PROJ_DIR$\systick.c - - - $PROJ_DIR$\timer.c - - - $PROJ_DIR$\uart.c - - - $PROJ_DIR$\udma.c - - - $PROJ_DIR$\usb.c - - - $PROJ_DIR$\watchdog.c - - - diff --git a/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.sgxx b/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.sgxx deleted file mode 100644 index f7d58e766d..0000000000 Binary files a/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.sgxx and /dev/null differ diff --git a/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.uvopt b/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.uvopt deleted file mode 100644 index 9b33e69d09..0000000000 --- a/bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.uvopt +++ /dev/null @@ -1,636 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
- - - - driverlib-cm4f - 0x4 - ARM-ADS - - - LM4F110B2QR - Texas Instruments - IRAM(0x20000000-0x20002FFF) IROM(0-0x7FFF) CLOCK(8000000) CPUTYPE("Cortex-M4") FPU2 - - "STARTUP\Luminary\Startup.s" ("Luminary Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_32 -FS00 -FL08000) - 5919 - LM4Fxxxx.H - - - - - - - - - - SFD\Luminary\LM4F110B2QR.SFR - 0 - - - - Luminary\ - Luminary\ - - 0 - 0 - 0 - 0 - 1 - - .\rvmdk-cm4f\ - driverlib-cm4f - 0 - 1 - 0 - 1 - 1 - .\rvmdk-cm4f\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 0 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - - 0 - 3 - - - - - - - - - - - - - - BIN\lmidk-agdi.dll - - - - - 1 - 0 - 0 - 0 - 1 - 4097 - - BIN\lmidk-agdi.dll - - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 8 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x3000 - - - 1 - 0x0 - 0x8000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x8000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x3000 - - - 0 - 0x0 - 0x0 - - - - - - 0 - 3 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - - - rvmdk - - ..; - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - - - - - - - - - - - Source - - - adc.c - 1 - .\adc.c - - - can.c - 1 - .\can.c - - - comp.c - 1 - .\comp.c - - - cpu.c - 1 - .\cpu.c - - - eeprom.c - 1 - .\eeprom.c - - - epi.c - 1 - .\epi.c - - - ethernet.c - 1 - .\ethernet.c - - - fan.c - 1 - .\fan.c - - - flash.c - 1 - .\flash.c - - - fpu.c - 1 - .\fpu.c - - - gpio.c - 1 - .\gpio.c - - - hibernate.c - 1 - .\hibernate.c - - - i2c.c - 1 - .\i2c.c - - - i2s.c - 1 - .\i2s.c - - - interrupt.c - 1 - .\interrupt.c - - - lpc.c - 1 - .\lpc.c - - - mpu.c - 1 - .\mpu.c - - - peci.c - 1 - .\peci.c - - - pwm.c - 1 - .\pwm.c - - - qei.c - 1 - .\qei.c - - - ssi.c - 1 - .\ssi.c - - - sysctl.c - 1 - .\sysctl.c - - - sysexc.c - 1 - .\sysexc.c - - - systick.c - 1 - .\systick.c - - - timer.c - 1 - .\timer.c - - - uart.c - 1 - .\uart.c - - - udma.c - 1 - .\udma.c - - - usb.c - 1 - .\usb.c - - - watchdog.c - 1 - .\watchdog.c - - - - - Documentation - - - readme.txt - 5 - .\readme.txt - - - - - - - - diff --git a/bsp/lm4f232/Libraries/driverlib/eeprom.c b/bsp/lm4f232/Libraries/driverlib/eeprom.c index d065049118..8096899155 100644 --- a/bsp/lm4f232/Libraries/driverlib/eeprom.c +++ b/bsp/lm4f232/Libraries/driverlib/eeprom.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -68,7 +68,7 @@ //***************************************************************************** // // This function implements a workaround for a bug in Blizzard rev A silicon. -// It ensure that only the 1KB flash sector containing a given EEPROM address +// It ensures that only the 1KB flash sector containing a given EEPROM address // is erased if an erase/copy operation is required as a result of a following // EEPROM write. // @@ -97,7 +97,7 @@ EEPROMSetSectorMask(unsigned long ulAddress) //***************************************************************************** // // Clear the FSM sector erase mask to ensure that any following main array flash -// erase operations will operate as expected. +// erase operations operate as expected. // //***************************************************************************** static void @@ -137,18 +137,18 @@ EEPROMWaitForDone(void) //! //! This function must be called after SysCtlPeripheralEnable() and before //! the EEPROM is accessed to check for errors resulting from power failure -//! during a previous write operation. The function will detect these errors -//! and perform as much recovery as possible before returning information to -//! the caller on whether or not a previous data write was lost and will need -//! to be retried. +//! during a previous write operation. The function detects these errors +//! and performs as much recovery as possible before returning information to +//! the caller on whether or not a previous data write was lost and must +//! be retried. //! //! In cases where \b EEPROM_INIT_RETRY is returned, the application is //! responsible for determining which data write may have been lost and -//! rewriting this data. If \b EEPROM_INIT_ERROR is returned, this indicates -//! that the EEPROM was unable to recover its state. This condition may or -//! may not be resolved on future resets depending upon the cause of the -//! fault. For example, if the supply voltage is unstable, retrying the -//! operation once the voltage is stabilized may clear the error. +//! rewriting this data. If \b EEPROM_INIT_ERROR is returned, the EEPROM was +//! unable to recover its state. This condition may or may not be resolved on +//! future resets depending upon the cause of the fault. For example, if the +//! supply voltage is unstable, retrying the operation once the voltage is +//! stabilized may clear the error. //! //! Failure to call this function after a reset may lead to permanent data loss //! if the EEPROM is later written! @@ -268,7 +268,7 @@ EEPROMBlockCountGet(void) //! Reads data from the EEPROM. //! //! \param pulData is a pointer to storage for the data read from the EEPROM. -//! This must point to at least \e ulCount bytes of available memory. +//! This pointer must point to at least \e ulCount bytes of available memory. //! \param ulAddress is the byte address within the EEPROM from which data is //! to be read. This value must be a multiple of 4. //! \param ulCount is the number of bytes of data to read from the EEPROM. @@ -410,7 +410,7 @@ EEPROMProgram(unsigned long *pulData, unsigned long ulAddress, // // Make sure we completed the write without errors. Note that we - // must check this per-word since write permission can be set per + // must check this per-word because write permission can be set per // block resulting in only a section of the write not being performed. // if(ulStatus & (EEPROM_EEDONE_NOPERM | EEPROM_EEDONE_INVPL)) @@ -520,7 +520,7 @@ EEPROMProgramNonBlocking(unsigned long ulData, unsigned long ulAddress) // //! Erases the EEPROM and returns it to the factory default condition. //! -//! This function will completely erase the EEPROM and remove any and +//! This function completely erases the EEPROM and removes any and //! all access protection on its blocks, leaving the device in the factory //! default condition. After this operation, all EEPROM words contain the //! value 0xFFFFFFFF and all blocks are accessible for both read and write @@ -538,6 +538,14 @@ EEPROMProgramNonBlocking(unsigned long ulData, unsigned long ulAddress) unsigned long EEPROMMassErase(void) { + // + // This is a workaround for a silicon problem on Blizzard rev A. + // + if(CLASS_IS_BLIZZARD && REVISION_IS_A0) + { + EEPROMClearSectorMask(); + } + // // Start the mass erase processing // @@ -549,7 +557,7 @@ EEPROMMassErase(void) EEPROMWaitForDone(); // - // Reset the peripheral. This si required so that all protection + // Reset the peripheral. This is required so that all protection // mechanisms and passwords are reset now that the EEPROM data has been // scrubbed. // @@ -618,9 +626,10 @@ EEPROMBlockProtectGet(unsigned long ulBlock) //! access to the EEPROM peripheral as a whole. Protection settings applied to //! blocks numbered 1 and above are layered above any protection set on block 0 //! such that the effective protection on each block is the logical OR of the -//! protection flags set for block 0 and for the target block. This allows -//! global protection options to be set for the whole device via block 0 and -//! more restrictive protection settings to be set on a block-by-block basis. +//! protection flags set for block 0 and for the target block. This protocol +//! allows global protection options to be set for the whole device via block +//! 0 and more restrictive protection settings to be set on a block-by-block +//! basis. //! //! The protection flags indicate access permissions as follow: //! @@ -1022,9 +1031,9 @@ EEPROMIntStatus(tBoolean bMasked) // // If asked for the unmasked interrupt status, infer that an interrupt // is pending if the WORKING bit of the EEDONE register is clear. The - // actual interrupt will fire on the high to low transition of this bit + // actual interrupt fires on the high to low transition of this bit // but we don't have access to an unmasked interrupt status for the - // EEPROM since it's handled via the flash controller so we have to + // EEPROM because it's handled via the flash controller so we have to // make do with this instead. // return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ? diff --git a/bsp/lm4f232/Libraries/driverlib/eeprom.h b/bsp/lm4f232/Libraries/driverlib/eeprom.h index 591f251b8d..00ac97e883 100644 --- a/bsp/lm4f232/Libraries/driverlib/eeprom.h +++ b/bsp/lm4f232/Libraries/driverlib/eeprom.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/epi.c b/bsp/lm4f232/Libraries/driverlib/epi.c index 1a92dd3dd6..9bb281f7b8 100644 --- a/bsp/lm4f232/Libraries/driverlib/epi.c +++ b/bsp/lm4f232/Libraries/driverlib/epi.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -53,7 +53,7 @@ //! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface //! - \b EPI_MODE_DISABLE - disable the EPI module //! -//! Selection of any of the above modes will enable the EPI module, except +//! Selection of any of the above modes enables the EPI module, except //! for \b EPI_MODE_DISABLE which should be used to disable the module. //! //! \return None. @@ -86,15 +86,15 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode) //! \param ulDivider is the value of the clock divider to be applied to //! the external interface (0-65535). //! -//! This functions sets the clock divider(s) that is used to determine the +//! This function sets the clock divider(s) that is used to determine the //! clock rate of the external interface. The \e ulDivider value is used to -//! derive the EPI clock rate from the system clock based upon the following +//! derive the EPI clock rate from the system clock based on the following //! formula. //! //! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) //! //! For example, a divider value of 1 results in an EPI clock rate of half -//! the system clock, value of 2 or 3 yield one quarter of the system clock and +//! the system clock, value of 2 or 3 yields one quarter of the system clock and //! a value of 4 results in one sixth of the system clock rate. //! //! In cases where a dual chip select mode is in use and different clock rates @@ -292,8 +292,8 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, //! or \b EPI_HB16_RDWAIT_3 to select the number of read wait states (default //! is 0 wait states) //! - \b EPI_HB16_WORD_ACCESS - use Word Access mode to route bytes to the -//! correct byte lanes allowing data to be stored in bits [31:8]. If absent, -//! all data transfers use bits [7:0]. +//! correct byte lanes allowing data to be stored in bits [31:16]. If absent, +//! all data transfers use bits [15:0]. //! - \b EPI_HB16_BSEL - enables byte selects. In this mode, two EPI signals //! operate as byte selects allowing 8-bit transfers. If this flag is not //! specified, data must be read and written using only 16-bit transfers. @@ -367,9 +367,8 @@ EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, //! //! This function is used to configure the interface when used in //! general-purpose operation as chosen with the function EPIModeSet(). The -//! parameter -//! \e ulConfig is the logical OR of any of the following: -//! +//! parameter \e ulConfig is the logical OR of any of the following: +//! //! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin //! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction, //! otherwise it is free-running @@ -381,13 +380,13 @@ EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, //! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it //! is a pulse //! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins -//! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a +//! - \b EPI_GPMODE_WRITE2CYCLE - a two-cycle write is used, otherwise a //! single-cycle write is used -//! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a +//! - \b EPI_GPMODE_READ2CYCLE - a two-cycle read is used, otherwise a //! single-cycle read is used //! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4, //! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address -//! bus, or and address bus size of 4, 12, or 20 bits +//! bus or an address bus size of 4, 12, or 20 bits //! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16, //! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus //! size of 8, 16, 24, or 32 bits @@ -406,7 +405,7 @@ EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig, //! external clock enable is used, this parameter determines the maximum //! number of clocks to wait when the external clock enable signal is holding //! off a transaction. A value of 0 means to wait forever. If a non-zero -//! value is used and exceeded, an interrupt will occur and the transaction +//! value is used and exceeded, an interrupt occurs and the transaction //! aborted. //! //! \return None. @@ -515,7 +514,7 @@ EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap) //! Once configured, the non-blocking read is started by calling //! EPINonBlockingReadStart(). If the addresses to be read from the device //! are in a sequence, it is not necessary to call this function multiple -//! times. Until it is changed, the EPI module will remember the last address +//! times. Until it is changed, the EPI module stores the last address //! that was used for a non-blocking read (per channel). //! //! \return None. @@ -561,9 +560,9 @@ EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel, //! //! This function starts a non-blocking read that was previously configured //! with the function EPINonBlockingReadConfigure(). Once this function is -//! called, the EPI module will begin reading data from the external device -//! into the read FIFO. The EPI will stop reading when the FIFO fills up -//! and resume reading when the application drains the FIFO, until the +//! called, the EPI module begins reading data from the external device +//! into the read FIFO. The EPI stops reading when the FIFO fills up +//! and resumes reading when the application drains the FIFO, until the //! total specified count of data items has been read. //! //! Once a read transaction is completed and the FIFO drained, another @@ -627,7 +626,7 @@ EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel) ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); // - // Write a 0 to the read count register, which will cancel the transaction. + // Write a 0 to the read count register, which cancels the transaction. // HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0; } @@ -705,7 +704,7 @@ EPINonBlockingReadAvail(unsigned long ulBase) //! be stored. //! //! This function reads 32-bit data items from the read FIFO and stores -//! the values in a caller supplied buffer. The function will read and store +//! the values in a caller-supplied buffer. The function reads and stores //! data from the FIFO until there is no more data in the FIFO or the maximum //! count is reached as specified in the parameter \e ulCount. The actual //! count of items is returned. @@ -727,8 +726,8 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount, ASSERT(pulBuf); // - // Read from the FIFO while there are any items to read, and - // the callers specified count is not exceeded. + // Read from the FIFO while there are any items to read and + // the caller's specified count is not exceeded. // while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) { @@ -756,11 +755,11 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount, //! //! \param ulBase is the EPI module base address. //! \param ulCount is the maximum count of items to read. -//! \param pusBuf is the caller supplied buffer where the read data should +//! \param pusBuf is the caller-supplied buffer where the read data should //! be stored. //! //! This function reads 16-bit data items from the read FIFO and stores -//! the values in a caller supplied buffer. The function will read and store +//! the values in a caller-supplied buffer. The function reads and stores //! data from the FIFO until there is no more data in the FIFO or the maximum //! count is reached as specified in the parameter \e ulCount. The actual //! count of items is returned. @@ -783,12 +782,12 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount, // // Read from the FIFO while there are any items to read, and - // the callers specified count is not exceeded. + // the caller's specified count is not exceeded. // while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) { // - // Read from the FIFO and store in the caller supplied buffer. + // Read from the FIFO and store in the caller-supplied buffer. // *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO); @@ -811,11 +810,11 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount, //! //! \param ulBase is the EPI module base address. //! \param ulCount is the maximum count of items to read. -//! \param pucBuf is the caller supplied buffer where the read data should +//! \param pucBuf is the caller-supplied buffer where the read data should //! be stored. //! //! This function reads 8-bit data items from the read FIFO and stores -//! the values in a caller supplied buffer. The function will read and store +//! the values in a caller-supplied buffer. The function reads and stores //! data from the FIFO until there is no more data in the FIFO or the maximum //! count is reached as specified in the parameter \e ulCount. The actual //! count of items is returned. @@ -838,7 +837,7 @@ EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount, // // Read from the FIFO while there are any items to read, and - // the callers specified count is not exceeded. + // the caller's specified count is not exceeded. // while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) { @@ -1140,7 +1139,7 @@ EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the EPI module base address. //! -//! This function will disable and clear the handler to be called when the +//! This function disables and clears the handler to be called when the //! EPI interrupt occurs. //! //! \sa IntRegister() for important information about registering interrupt diff --git a/bsp/lm4f232/Libraries/driverlib/epi.h b/bsp/lm4f232/Libraries/driverlib/epi.h index 25b3d45076..54d8b1511c 100644 --- a/bsp/lm4f232/Libraries/driverlib/epi.h +++ b/bsp/lm4f232/Libraries/driverlib/epi.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/ethernet.c b/bsp/lm4f232/Libraries/driverlib/ethernet.c index 6941369fdc..9597ec99df 100644 --- a/bsp/lm4f232/Libraries/driverlib/ethernet.c +++ b/bsp/lm4f232/Libraries/driverlib/ethernet.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -44,11 +44,11 @@ //! \param ulBase is the base address of the controller. //! \param ulEthClk is the rate of the clock supplied to the Ethernet module. //! -//! This function will prepare the Ethernet controller for first time use in +//! This function prepares the Ethernet controller for first-time use in //! a given hardware/software configuration. This function should be called //! before any other Ethernet API functions are called. //! -//! The peripheral clock is the same as the processor clock. This is the value +//! The peripheral clock is the same as the processor clock. This value is //! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtlClockGet()). @@ -112,14 +112,16 @@ EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk) //! //! The Ethernet controller provides three control registers that are used //! to configure the controller's operation. The transmit control register -//! provides settings to enable full duplex operation, to auto-generate the +//! provides settings to enable full-duplex operation, to auto-generate the //! frame check sequence, and to pad the transmit packets to the minimum //! length as required by the IEEE standard. The receive control register //! provides settings to enable reception of packets with bad frame check //! sequence values and to enable multi-cast or promiscuous modes. The //! timestamp control register provides settings that enable support logic in //! the controller that allow the use of the General Purpose Timer 3 to capture -//! timestamps for the transmitted and received packets. +//! timestamps for the transmitted and received packets. Note that not all +//! devices support this functionality; see the data sheet to determine if +//! this feature is supported. //! //! The \e ulConfig parameter is the logical OR of the following values: //! @@ -183,11 +185,11 @@ EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig) //! //! \param ulBase is the base address of the controller. //! -//! This function will query the control registers of the Ethernet controller -//! and return a bit-mapped configuration value. +//! This function queries the control registers of the Ethernet controller +//! and returns a bit-mapped configuration value. //! //! \sa The description of the EthernetConfigSet() function provides detailed -//! information for the bit-mapped configuration values that is returned. +//! information for the bit-mapped configuration values that are returned. //! //! \return Returns the bit-mapped Ethernet controller configuration value. // @@ -219,7 +221,7 @@ EthernetConfigGet(unsigned long ulBase) //! \param ulBase is the base address of the controller. //! \param pucMACAddr is the pointer to the array of MAC-48 address octets. //! -//! This function will program the IEEE-defined MAC-48 address specified in +//! This function programs the IEEE-defined MAC-48 address specified in //! \e pucMACAddr into the Ethernet controller. This address is used by the //! Ethernet controller for hardware-level filtering of incoming Ethernet //! packets (when promiscuous mode is not enabled). @@ -282,7 +284,7 @@ EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr) //! \param pucMACAddr is the pointer to the location in which to store the //! array of MAC-48 address octets. //! -//! This function will read the currently programmed MAC address into the +//! This function reads the currently programmed MAC address into the //! \e pucMACAddr buffer. //! //! \sa Refer to EthernetMACAddrSet() API description for more details about @@ -329,8 +331,8 @@ EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr) //! the EthernetMACAddrSet() function, this API function can be called to //! enable the controller for normal operation. //! -//! This function will enable the controller's transmitter and receiver, and -//! will reset the receive FIFO. +//! This function enables the controller's transmitter and receiver, and +//! resets the receive FIFO. //! //! \return None. // @@ -371,8 +373,8 @@ EthernetEnable(unsigned long ulBase) //! \param ulBase is the base address of the controller. //! //! When terminating operations on the Ethernet interface, this function should -//! be called. This function will disable the transmitter and receiver, and -//! will clear out the receive FIFO. +//! be called. This function disables the transmitter and receiver, and +//! clears out the receive FIFO. //! //! \return None. // @@ -447,7 +449,7 @@ EthernetPacketAvail(unsigned long ulBase) //! packet at a time. After the packet has been written into the FIFO, the //! transmit request bit must be set to enable the transmission of the packet. //! Only after the packet has been transmitted can a new packet be written -//! into the FIFO. This function will simply check to see if a packet is +//! into the FIFO. This function simply checks to see if a packet is //! in progress. If so, there is no space available in the transmit FIFO. //! //! \return Returns \b true if a space is available in the transmit FIFO, and @@ -608,20 +610,20 @@ EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf, //! \param lBufLen is the maximum number of bytes to be read into the buffer. //! //! This function reads a packet from the receive FIFO of the controller and -//! places it into \e pucBuf. If no packet is available the function will -//! return immediately. Otherwise, the function will read the entire packet -//! from the receive FIFO. If there are more bytes in the packet than will fit -//! into \e pucBuf (as specified by \e lBufLen), the function will return the -//! negated length of the packet and the buffer will contain \e lBufLen bytes -//! of the packet. Otherwise, the function will return the length of the -//! packet that was read and \e pucBuf will contain the entire packet +//! places it into \e pucBuf. If no packet is available the function +//! returns immediately. Otherwise, the function reads the entire packet +//! from the receive FIFO. If there are more bytes in the packet than can fit +//! into \e pucBuf (as specified by \e lBufLen), the function returns the +//! negated length of the packet and the buffer contains \e lBufLen bytes +//! of the packet. Otherwise, the function returns the length of the +//! packet that was read and \e pucBuf contains the entire packet //! (excluding the frame check sequence bytes). //! //! This function replaces the original EthernetPacketNonBlockingGet() API and //! performs the same actions. A macro is provided in ethernet.h to //! map the original API to this API. //! -//! \note This function will return immediately if no packet is available. +//! \note This function returns immediately if no packet is available. //! //! \return Returns \b 0 if no packet is available, the negated packet length //! \b -n if the packet is too large for \e pucBuf, and the packet length \b n @@ -662,16 +664,16 @@ EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf, //! \param lBufLen is the maximum number of bytes to be read into the buffer. //! //! This function reads a packet from the receive FIFO of the controller and -//! places it into \e pucBuf. The function will wait until a packet is -//! available in the FIFO. Then the function will read the entire packet -//! from the receive FIFO. If there are more bytes in the packet than will -//! fit into \e pucBuf (as specified by \e lBufLen), the function will return -//! the negated length of the packet and the buffer will contain \e lBufLen -//! bytes of the packet. Otherwise, the function will return the length of -//! the packet that was read and \e pucBuf will contain the entire packet +//! places it into \e pucBuf. The function waits until a packet is +//! available in the FIFO. Then the function reads the entire packet +//! from the receive FIFO. If there are more bytes in the packet than can +//! fit into \e pucBuf (as specified by \e lBufLen), the function returns +//! the negated length of the packet and the buffer contains \e lBufLen +//! bytes of the packet. Otherwise, the function returns the length of +//! the packet that was read and \e pucBuf contains the entire packet //! (excluding the frame check sequence bytes). //! -//! \note This function is blocking and will not return until a packet arrives. +//! \note This function is blocking and does not return until a packet arrives. //! //! \return Returns the negated packet length \b -n if the packet is too large //! for \e pucBuf, and returns the packet length \b n otherwise. @@ -831,10 +833,10 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf, //! This function writes \e lBufLen bytes of the packet contained in \e pucBuf //! into the transmit FIFO of the controller and then activates the //! transmitter for this packet. If no space is available in the FIFO, the -//! function will return immediately. If space is available, the -//! function will return once \e lBufLen bytes of the packet have been placed -//! into the FIFO and the transmitter has been started. The function will not -//! wait for the transmission to complete. The function will return the +//! function returns immediately. If space is available, the +//! function returns once \e lBufLen bytes of the packet have been placed +//! into the FIFO and the transmitter has been started. The function does not +//! wait for the transmission to complete. The function returns the //! negated \e lBufLen if the length is larger than the space available in //! the transmit FIFO. //! @@ -842,7 +844,7 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf, //! performs the same actions. A macro is provided in ethernet.h to //! map the original API to this API. //! -//! \note This function does not block and will return immediately if no space +//! \note This function does not block and returns immediately if no space //! is available for the transmit packet. //! //! \return Returns \b 0 if no space is available in the transmit FIFO, the @@ -885,14 +887,14 @@ EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf, //! //! This function writes \e lBufLen bytes of the packet contained in \e pucBuf //! into the transmit FIFO of the controller and then activates the transmitter -//! for this packet. This function will wait until the transmit FIFO is empty. -//! Once space is available, the function will return once \e lBufLen bytes of +//! for this packet. This function waits until the transmit FIFO is empty. +//! Once space is available, the function returns once \e lBufLen bytes of //! the packet have been placed into the FIFO and the transmitter has been -//! started. The function will not wait for the transmission to complete. The -//! function will return the negated \e lBufLen if the length is larger than +//! started. The function does not wait for the transmission to complete. The +//! function returns the negated \e lBufLen if the length is larger than //! the space available in the transmit FIFO. //! -//! \note This function blocks and will wait until space is available for the +//! \note This function blocks and waits until space is available for the //! transmit packet before returning. //! //! \return Returns the negated packet length \b -lBufLen if the packet is too @@ -932,9 +934,10 @@ EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, //! enabled Ethernet interrupts occur. //! //! This function sets the handler to be called when the Ethernet interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It -//! is the interrupt handler's responsibility to clear the interrupt source. +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific Ethernet interrupts must be enabled via +//! EthernetIntEnable(). It is the interrupt handler's responsibility to clear +//! the interrupt source. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -968,9 +971,9 @@ EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the base address of the controller. //! -//! This function unregisters the interrupt handler. This will disable the -//! global interrupt in the interrupt controller so that the interrupt handler -//! no longer is called. +//! This function unregisters the interrupt handler. This function disables +//! the global interrupt in the interrupt controller so that the interrupt +//! handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1004,16 +1007,17 @@ EthernetIntUnregister(unsigned long ulBase) //! \param ulBase is the base address of the controller. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated Ethernet interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function enables the indicated Ethernet interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! //! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated -//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17, -//! must be read to determine which PHY interrupt has occurred. This register -//! can be read using the EthernetPHYRead() API function. +//! PHY supports a number of interrupt conditions. The appropriate PHY +//! register, PHY_MR17 or PHY_MR29 depending on the device class, must be read +//! to determine which PHY interrupt has occurred. This register can be read +//! using the EthernetPHYRead() API function. //! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the //! management interface has completed successfully. //! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred @@ -1092,9 +1096,9 @@ EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true //! if the masked interrupt status is required. //! -//! This returns the interrupt status for the Ethernet controller. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the Ethernet controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in EthernetIntEnable(). @@ -1137,13 +1141,13 @@ EthernetIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified Ethernet interrupt sources are cleared so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to EthernetIntEnable(). //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1180,9 +1184,9 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags) //! \param ucAddr is the address of the PHY. //! //! This function sets the address of the PHY that is accessed via -//! EthernetPHYRead() and EthernePHYWrite(). This is only needed when -//! connecting to an external PHY via MII, and should not be used on devices -//! that have integrated PHYs. +//! EthernetPHYRead() and EthernePHYWrite(). This configuration is only needed +//! when connecting to an external PHY via MII, and should not be used on +//! devices that have integrated PHYs. //! //! \return None. // @@ -1216,7 +1220,7 @@ EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr) //! \param ucRegAddr is the address of the PHY register to be accessed. //! \param ulData is the data to be written to the PHY register. //! -//! This function will write the \e ulData to the PHY register specified by +//! This function writes the \e ulData to the PHY register specified by //! \e ucRegAddr. //! //! \return None. @@ -1264,7 +1268,7 @@ EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, //! \param ulBase is the base address of the controller. //! \param ucRegAddr is the address of the PHY register to be accessed. //! -//! This function will return the contents of the PHY register specified by +//! This function returns the contents of the PHY register specified by //! \e ucRegAddr. //! //! \return Returns the 16-bit value read from the PHY. @@ -1310,8 +1314,8 @@ EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr) //! //! \param ulBase is the base address of the controller. //! -//! This function will power off the Ethernet PHY, reducing the current -//! consuption of the device. While in the powered off state, the Ethernet +//! This function powers off the Ethernet PHY, reducing the current +//! consumption of the device. While in the powered off state, the Ethernet //! controller is unable to connect to the Ethernet. //! //! \return None. @@ -1335,9 +1339,9 @@ EthernetPHYPowerOff(unsigned long ulBase) //! //! \param ulBase is the base address of the controller. //! -//! This function will power on the Ethernet PHY, enabling it return to normal -//! operation. By default, the PHY is powered on, so this function only needs -//! to be called if EthernetPHYPowerOff() has previously been called. +//! This function powers on the Ethernet PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function is only +//! called if EthernetPHYPowerOff() has previously been called. //! //! \return None. // diff --git a/bsp/lm4f232/Libraries/driverlib/ethernet.h b/bsp/lm4f232/Libraries/driverlib/ethernet.h index 43fabe7586..015d4b1981 100644 --- a/bsp/lm4f232/Libraries/driverlib/ethernet.h +++ b/bsp/lm4f232/Libraries/driverlib/ethernet.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/fan.c b/bsp/lm4f232/Libraries/driverlib/fan.c index 40eb9f70cb..eb1b887e5d 100644 --- a/bsp/lm4f232/Libraries/driverlib/fan.c +++ b/bsp/lm4f232/Libraries/driverlib/fan.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -386,9 +386,10 @@ FanChannelRPMGet(unsigned long ulBase, unsigned long ulChannel) //! \param ulBase is the base address of the FAN module. //! \param ulFlags is the logical OR of all the interrupts to be enabled. //! -//! This enables one or more interrupts from the FAN module. The \e ulFlags -//! parameter is the logical OR of all the possible interrupts that can be -//! enabled. For each channel, the following interrupt flags are available: +//! This function enables one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be enabled. For each channel, the following interrupt flags are +//! available: //! //! - \b FAN_CHn_INT_STALL means that a stall was detected (in either mode). //! - \b FAN_CHn_INT_AUTO_SPEED_ERROR means that in automatic mode, the cooling @@ -403,7 +404,7 @@ FanChannelRPMGet(unsigned long ulBase, unsigned long ulChannel) //! configured for manual mode. The following alternate set of flag names is //! available for convenience to use in manual mode: //! -//! - \b FAN_CHn_INT_MANUAL_SPEED_UPDATE means that in manual mode the speed +//! - \b FAN_CHn_INT_MANUAL_SPEED_UPDATE means that in manual mode, the speed //! was calculated. //! - \b FAN_CHn_INT_MANUAL_SPEED_CHANGE means that in manual mode, the speed //! changed. @@ -504,9 +505,9 @@ FanIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the base address of the FAN module. //! \param ulFlags is the logical OR of all the interrupts to be cleared. //! -//! This clears one or more interrupts from the FAN module. The \e ulFlags -//! parameter is the logical OR of all the possible interrupts that can be -//! cleared. For a list of possible interrupt flags, refer to the +//! This function clears one or more interrupts from the FAN module. The +//! \e ulFlags parameter is the logical OR of all the possible interrupts that +//! can be cleared. For a list of possible interrupt flags, refer to the //! documentation for the function FanIntEnable(). //! //! \return None. diff --git a/bsp/lm4f232/Libraries/driverlib/fan.h b/bsp/lm4f232/Libraries/driverlib/fan.h index b3b023ec10..1b9fb94059 100644 --- a/bsp/lm4f232/Libraries/driverlib/fan.h +++ b/bsp/lm4f232/Libraries/driverlib/fan.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/flash.c b/bsp/lm4f232/Libraries/driverlib/flash.c index ac0e4f3cbc..48dcd7af29 100644 --- a/bsp/lm4f232/Libraries/driverlib/flash.c +++ b/bsp/lm4f232/Libraries/driverlib/flash.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -70,7 +70,8 @@ static const unsigned long g_pulFMPRERegs[] = //! Gets the number of processor clocks per micro-second. //! //! This function returns the number of clocks per micro-second, as presently -//! known by the flash controller. +//! known by the flash controller. This function is only valid on Sandstorm- +//! and Fury-class devices. //! //! \return Returns the number of processor clocks per micro-second. // @@ -93,7 +94,7 @@ FlashUsecGet(void) //! This function is used to tell the flash controller the number of processor //! clocks per micro-second. This value must be programmed correctly or the //! flash most likely will not program correctly; it has no affect on reading -//! flash. +//! flash. This function is only valid on Sandstorm- and Fury-class devices. //! //! \return None. // @@ -113,11 +114,11 @@ FlashUsecSet(unsigned long ulClocks) //! //! \param ulAddress is the start address of the flash block to be erased. //! -//! This function will erase a 1 kB block of the on-chip flash. After erasing, +//! This function erases a 1-kB block of the on-chip flash. After erasing, //! the block is filled with 0xFF bytes. Read-only and execute-only blocks //! cannot be erased. //! -//! This function will not return until the block has been erased. +//! This function does not return until the block has been erased. //! //! \return Returns 0 on success, or -1 if an invalid block address was //! specified or the block is write-protected. @@ -175,16 +176,16 @@ FlashErase(unsigned long ulAddress) //! \param ulCount is the number of bytes to be programmed. Must be a multiple //! of four. //! -//! This function will program a sequence of words into the on-chip flash. +//! This function programs a sequence of words into the on-chip flash. //! Each word in a page of flash can only be programmed one time between an -//! erase of that page; programming a word multiple times will result in an +//! erase of that page; programming a word multiple times results in an //! unpredictable value in that word of flash. //! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to +//! Because the flash is programmed one word at a time, the starting address +//! and byte count must both be multiples of four. It is up to the caller to //! verify the programmed contents, if such verification is required. //! -//! This function will not return until the data has been programmed. +//! This function does not return until the data has been programmed. //! //! \return Returns 0 on success, or -1 if a programming error is encountered. // @@ -298,7 +299,7 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress, //! //! \param ulAddress is the start address of the flash block to be queried. //! -//! This function will get the current protection for the specified 2 kB block +//! This function gets the current protection for the specified 2-kB block //! of flash. Each block can be read/write, read-only, or execute-only. //! Read/write blocks can be read, executed, erased, and programmed. Read-only //! blocks can be read and executed. Execute-only blocks can only be executed; @@ -391,17 +392,17 @@ FlashProtectGet(unsigned long ulAddress) //! \param eProtect is the protection to be applied to the block. Can be one //! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. //! -//! This function will set the protection for the specified 2 kB block of -//! flash. Blocks which are read/write can be made read-only or execute-only. -//! Blocks which are read-only can be made execute-only. Blocks which are +//! This function sets the protection for the specified 2-kB block of +//! flash. Blocks that are read/write can be made read-only or execute-only. +//! Blocks that are read-only can be made execute-only. Blocks that are //! execute-only cannot have their protection modified. Attempts to make the -//! block protection less stringent (that is, read-only to read/write) will -//! result in a failure (and be prevented by the hardware). +//! block protection less stringent (that is, read-only to read/write) +//! result in a failure (and are prevented by the hardware). //! //! Changes to the flash protection are maintained only until the next reset. -//! This allows the application to be executed in the desired flash protection -//! environment to check for inappropriate flash access (via the flash -//! interrupt). To make the flash protection permanent, use the +//! This protocol allows the application to be executed in the desired flash +//! protection environment to check for inappropriate flash access (via the +//! flash interrupt). To make the flash protection permanent, use the //! FlashProtectSave() function. //! //! \return Returns 0 on success, or -1 if an invalid address or an invalid @@ -556,11 +557,11 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) // //! Saves the flash protection settings. //! -//! This function will make the currently programmed flash protection settings -//! permanent. This is a non-reversible operation; a chip reset or power cycle -//! will not change the flash protection. +//! This function makes the currently programmed flash protection settings +//! permanent. On some devices, this operation is non-reversible; a chip reset +//! or power cycle does not change the flash protection. //! -//! This function will not return until the protection has been saved. +//! This function does not return until the protection has been saved. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. // @@ -605,8 +606,8 @@ FlashProtectSave(void) //! \param pulUser0 is a pointer to the location to store USER Register 0. //! \param pulUser1 is a pointer to the location to store USER Register 1. //! -//! This function will read the contents of user registers (0 and 1), and -//! store them in the specified locations. +//! This function reads the contents of user registers (0 and 1), and +//! stores them in the specified locations. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. // @@ -647,7 +648,7 @@ FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1) //! \param ulUser0 is the value to store in USER Register 0. //! \param ulUser1 is the value to store in USER Register 1. //! -//! This function will set the contents of the user registers (0 and 1) to +//! This function sets the contents of the user registers (0 and 1) to //! the specified values. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. @@ -680,11 +681,11 @@ FlashUserSet(unsigned long ulUser0, unsigned long ulUser1) // //! Saves the user registers. //! -//! This function will make the currently programmed user register settings -//! permanent. This is a non-reversible operation; a chip reset or power cycle -//! will not change this setting. +//! This function makes the currently programmed user register settings +//! permanent. On some devices, this operation is non-reversible; a chip reset +//! or power cycle does not change this setting. //! -//! This function will not return until the protection has been saved. +//! This function does not return until the protection has been saved. //! //! \return Returns 0 on success, or -1 if a hardware error is encountered. // @@ -740,8 +741,8 @@ FlashUserSave(void) //! \param pfnHandler is a pointer to the function to be called when the flash //! interrupt occurs. //! -//! This sets the handler to be called when the flash interrupt occurs. The -//! flash controller can generate an interrupt when an invalid flash access +//! This function sets the handler to be called when the flash interrupt occurs. +//! The flash controller can generate an interrupt when an invalid flash access //! occurs, such as trying to program or erase a read-only block, or trying to //! read from an execute-only block. It can also generate an interrupt when a //! program or erase operation has completed. The interrupt is automatically @@ -771,9 +772,9 @@ FlashIntRegister(void (*pfnHandler)(void)) // //! Unregisters the interrupt handler for the flash interrupt. //! -//! This function will clear the handler to be called when the flash interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler is no longer called. +//! This function clears the handler to be called when the flash interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -802,9 +803,9 @@ FlashIntUnregister(void) //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values. //! -//! Enables the indicated flash controller interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. +//! This function enables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -825,9 +826,9 @@ FlashIntEnable(unsigned long ulIntFlags) //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values. //! -//! Disables the indicated flash controller interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. +//! This function disables the indicated flash controller interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -848,9 +849,9 @@ FlashIntDisable(unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the flash controller. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the flash controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return The current interrupt status, enumerated as a bit field of //! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS. @@ -881,10 +882,10 @@ FlashIntStatus(tBoolean bMasked) //! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values. //! //! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. This must be done in the interrupt handler to keep it -//! from being called again immediately upon exit. +//! no longer assert. This function must be called in the interrupt handler +//! to keep the interrupt from being triggered again immediately upon exit. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid diff --git a/bsp/lm4f232/Libraries/driverlib/flash.h b/bsp/lm4f232/Libraries/driverlib/flash.h index e5a5357018..e089d43e7a 100644 --- a/bsp/lm4f232/Libraries/driverlib/flash.h +++ b/bsp/lm4f232/Libraries/driverlib/flash.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/fpu.c b/bsp/lm4f232/Libraries/driverlib/fpu.c index aeb9ad29cc..a61be4c95e 100644 --- a/bsp/lm4f232/Libraries/driverlib/fpu.c +++ b/bsp/lm4f232/Libraries/driverlib/fpu.c @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -122,10 +122,10 @@ FPUStackingEnable(void) //! interrupt handler, the floating-point context is only restored if it was //! saved (as the result of executing a floating-point instruction). //! -//! This provides a compromise between fast interrupt response (because the -//! floating-point state is not saved on interrupt entry) and the ability to -//! use floating-point in interrupt handlers (because the floating-point state -//! is saved if floating-point instructions are used). +//! This method provides a compromise between fast interrupt response (because +//! the floating-point state is not saved on interrupt entry) and the ability +//! to use floating-point in interrupt handlers (because the floating-point +//! state is saved if floating-point instructions are used). //! //! \return None. // @@ -166,7 +166,7 @@ FPUStackingDisable(void) // //! Selects the format of half-precision floating-point values. //! -//! \param ulMode is the format for half-precision floating-point values; which +//! \param ulMode is the format for half-precision floating-point value, which //! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. //! //! This function selects between the IEEE half-precision floating-point diff --git a/bsp/lm4f232/Libraries/driverlib/fpu.h b/bsp/lm4f232/Libraries/driverlib/fpu.h index f4310a2e57..30d25d5cff 100644 --- a/bsp/lm4f232/Libraries/driverlib/fpu.h +++ b/bsp/lm4f232/Libraries/driverlib/fpu.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/gpio.c b/bsp/lm4f232/Libraries/driverlib/gpio.c index 22389d1a6f..0e88fdbe11 100644 --- a/bsp/lm4f232/Libraries/driverlib/gpio.c +++ b/bsp/lm4f232/Libraries/driverlib/gpio.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -102,7 +102,8 @@ GPIOBaseValid(unsigned long ulPort) //! //! \param ulPort is the base address of the GPIO port. //! -//! Given a GPIO base address, returns the corresponding interrupt number. +//! Given a GPIO base address, this function returns the corresponding +//! interrupt number. //! //! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. // @@ -236,8 +237,8 @@ GPIOGetIntNumber(unsigned long ulPort) //! \param ucPins is the bit-packed representation of the pin(s). //! \param ulPinIO is the pin direction and/or mode. //! -//! This function will set the specified pin(s) on the selected GPIO port -//! as either an input or output under software control, or it will set the +//! This function configures the specified pin(s) on the selected GPIO port +//! as either input or output under software control, or it configures the //! pin to be under hardware control. //! //! The parameter \e ulPinIO is an enumerated data type that can be one of @@ -354,7 +355,7 @@ GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) //! giving each pin a separate interrupt vector. To use this feature, the //! \b GPIO_DISCRETE_INT can be included to enable an interrupt per pin. The //! \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports, -//! consult the data sheet to insure that the device and the GPIO port supports +//! consult the data sheet to ensure that the device and the GPIO port supports //! discrete interrupts. //! //! The pin(s) are specified using a bit-packed byte, where each bit that is @@ -402,9 +403,9 @@ GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, //! \param ucPin is the pin number. //! //! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling edge, rising edge, or -//! both edge detected interrupt, or it can be configured as a low level or -//! high level detected interrupt. The type of interrupt detection mechanism +//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or +//! both-edges detected interrupt, or it can be configured as a low-level or +//! high-level detected interrupt. The type of interrupt detection mechanism //! is returned as an enumerated data type. //! //! \return Returns one of the enumerated data types described for @@ -749,9 +750,9 @@ GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) //! \param pfnIntHandler is a pointer to the GPIO port interrupt handling //! function. //! -//! This function will ensure that the interrupt handler specified by +//! This function ensures that the interrupt handler specified by //! \e pfnIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function will also enable the corresponding GPIO interrupt +//! GPIO port. This function also enables the corresponding GPIO interrupt //! in the interrupt controller; individual pin interrupts and interrupt //! sources must be enabled with GPIOPinIntEnable(). //! @@ -791,8 +792,8 @@ GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) //! //! \param ulPort is the base address of the GPIO port. //! -//! This function will unregister the interrupt handler for the specified -//! GPIO port. This function will also disable the corresponding +//! This function unregisters the interrupt handler for the specified +//! GPIO port. This function also disables the corresponding //! GPIO port interrupt in the interrupt controller; individual GPIO interrupts //! and interrupt sources must be disabled with GPIOPinIntDisable(). //! @@ -901,15 +902,16 @@ GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) //! \param ucPins is the bit-packed representation of the pin(s). //! //! The analog-to-digital converter input pins must be properly configured -//! to function correctly on DustDevil-class devices. This function provides -//! the proper configuration for those pin(s). +//! to function correctly on devices that are not Sandstorm- or Fury-class. +//! This function provides the proper configuration for those pin(s). //! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an ADC input; it only -//! configures an ADC input pin for proper operation. +//! \note This function cannot be used to turn any pin into an ADC input; it +//! only configures an ADC input pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -949,8 +951,9 @@ GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a CAN pin; it only -//! configures a CAN pin for proper operation. +//! \note This function cannot be used to turn any pin into a CAN pin; it only +//! configures a CAN pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -989,8 +992,10 @@ GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an analog comparator input; -//! it only configures an analog comparator pin for proper operation. +//! \note This function cannot be used to turn any pin into an analog comparator +//! input; it only configures an analog comparator pin for proper operation. +//! Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. //! //! \return None. // @@ -1031,9 +1036,10 @@ GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an external peripheral -//! interface pin; it only configures an external peripheral interface pin for -//! proper operation. +//! \note This function cannot be used to turn any pin into an external +//! peripheral interface pin; it only configures an external peripheral +//! interface pin for proper operation. Devices with flexible pin muxing also +//! require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1072,8 +1078,9 @@ GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an Ethernet LED pin; it only -//! configures an Ethernet LED pin for proper operation. +//! \note This function cannot be used to turn any pin into an Ethernet LED pin; +//! it only configures an Ethernet LED pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1112,8 +1119,9 @@ GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an Ethernet MII pin; it only -//! configures an Ethernet MII pin for proper operation. +//! \note This function cannot be used to turn any pin into an Ethernet MII pin; +//! it only configures an Ethernet MII pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1153,8 +1161,9 @@ GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a fan pin; it only -//! configures a fan pin for proper operation. +//! \note This function cannot be used to turn any pin into a fan pin; it only +//! configures a fan pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1194,6 +1203,9 @@ GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! +//! \note Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! //! \return None. // //***************************************************************************** @@ -1232,6 +1244,9 @@ GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! +//! \note Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! //! \return None. // //***************************************************************************** @@ -1270,6 +1285,9 @@ GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! +//! \note Devices with flexible pin muxing also require a GPIOPinConfigure() +//! function call. +//! //! \return None. // //***************************************************************************** @@ -1307,8 +1325,9 @@ GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an I2C pin; it only -//! configures an I2C pin for proper operation. +//! \note This function cannot be used to turn any pin into an I2C pin; it +//! only configures an I2C pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1347,8 +1366,10 @@ GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into an I2C SCL pin; it only -//! configures an I2C SCL pin for proper operation. +//! \note This function should only be used for Blizzard-class devices. It +//! cannot be used to turn any pin into an I2C SCL pin; it only configures an +//! I2C SCL pin for proper operation. Devices with flexible pin muxing also +//! require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1395,8 +1416,9 @@ GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a I2S pin; it only -//! configures a I2S pin for proper operation. +//! \note This function cannot be used to turn any pin into a I2S pin; it only +//! configures a I2S pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1436,8 +1458,9 @@ GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a LPC pin; it only -//! configures a LPC pin for proper operation. +//! \note This function cannot be used to turn any pin into a LPC pin; it only +//! configures a LPC pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1476,8 +1499,9 @@ GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins) //! identifies the pin to be accessed, and where bit 0 of the byte represents //! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a PECI receive pin; it only -//! configures a PECI receive pin for proper operation. +//! \note This function cannot be used to turn any pin into a PECI receive pin; +//! it only configures a PECI receive pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1516,8 +1540,9 @@ GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins) //! identifies the pin to be accessed, and where bit 0 of the byte represents //! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a PECI transmit pin; it only -//! configures a PECI transmit pin for proper operation. +//! \note This function cannot be used to turn any pin into a PECI transmit pin; +//! it only configures a PECI transmit pin for proper operation. Devices with +//! flexible pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1557,8 +1582,9 @@ GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a PWM pin; it only -//! configures a PWM pin for proper operation. +//! \note This function cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. Devices wtih flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1598,8 +1624,9 @@ GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a QEI pin; it only -//! configures a QEI pin for proper operation. +//! \note This function cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1639,8 +1666,9 @@ GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a SSI pin; it only -//! configures a SSI pin for proper operation. +//! \note This function cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1680,8 +1708,9 @@ GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a timer pin; it only -//! configures a timer pin for proper operation. +//! \note This function cannot be used to turn any pin into a timer pin; it +//! only configures a timer pin for proper operation. Devices with flexible +//! pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1721,8 +1750,9 @@ GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a UART pin; it only -//! configures a UART pin for proper operation. +//! \note This function cannot be used to turn any pin into a UART pin; it +//! only configures a UART pin for proper operation. Devices with flexible +//! pin muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1762,8 +1792,9 @@ GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1807,8 +1838,9 @@ GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins) //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. +//! \note This function cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. Devices with flexible pin +//! muxing also require a GPIOPinConfigure() function call. //! //! \return None. // @@ -1843,10 +1875,11 @@ GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins) //! associated with a particular GPIO pin. Only one peripheral function at a //! time can be associated with a GPIO pin, and each peripheral function should //! only be associated with a single GPIO pin at a time (despite the fact that -//! many of them can be associated with more than one GPIO pin). +//! many of them can be associated with more than one GPIO pin). To fully +//! configure a pin, a GPIOPinType*() function should also be called. //! //! The available mappings are supplied on a per-device basis in -//! pin_map.h. The \b PART_IS_ define will enable the +//! pin_map.h. The \b PART_IS_ define enables the //! appropriate set of defines for the device that is being used. //! //! \note This function is not valid on Sandstorm, Fury, and Dustdevil-class @@ -1907,11 +1940,11 @@ GPIOPinConfigure(unsigned long ulPinConfig) //! //! This function enables a GPIO pin to be used as a trigger to start a uDMA //! transaction. Any GPIO pin can be configured to be an external trigger for -//! the uDMA. The GPIO pin will still generate interrupts if the interrupt is +//! the uDMA. The GPIO pin still generates interrupts if the interrupt is //! enabled for the selected pin. //! //! \note This function is not available on all devices, consult the data sheet -//! to insure that the device you are using supports GPIO DMA Control. +//! to ensure that the device you are using supports GPIO DMA Control. //! //! \return None. // @@ -1937,12 +1970,12 @@ GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins) //! \param ulPort is the base address of the GPIO port. //! \param ucPins is the bit-packed representation of the pin(s). //! -//! This function disables a GPIO pin to be used as a trigger to start a uDMA -//! transaction. This function can be used to disable this feature if it was -//! enabled via a call to GPIODMATriggerEnable(). +//! This function disables a GPIO pin from being used as a trigger to start a +//! uDMA transaction. This function can be used to disable this feature if it +//! was enabled via a call to GPIODMATriggerEnable(). //! //! \note This function is not available on all devices, consult the data sheet -//! to insure that the device you are using supports GPIO DMA Control. +//! to ensure that the device you are using supports GPIO DMA Control. //! //! \return None. // @@ -1970,11 +2003,13 @@ GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins) //! //! This function enables a GPIO pin to be used as a trigger to start an ADC //! sequence. Any GPIO pin can be configured to be an external trigger for -//! an ADC sequence. The GPIO pin will still generate interrupts if the -//! interrupt is enabled for the selected pin. +//! an ADC sequence. The GPIO pin still generates interrupts if the +//! interrupt is enabled for the selected pin. To enable the use of a GPIO pin +//! to trigger the ADC module, the ADCSequenceConfigure() function must be called +//! with the ADC_TRIGGER_EXTERNAL parameter. //! //! \note This function is not available on all devices, consult the data sheet -//! to insure that the device you are using supports GPIO ADC Control. +//! to ensure that the device you are using supports GPIO ADC Control. //! //! \return None. // @@ -2005,7 +2040,7 @@ GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins) //! enabled via a call to GPIOADCTriggerEnable(). //! //! \note This function is not available on all devices, consult the data sheet -//! to insure that the device you are using supports GPIO ADC Control. +//! to ensure that the device you are using supports GPIO ADC Control. //! //! \return None. // diff --git a/bsp/lm4f232/Libraries/driverlib/gpio.h b/bsp/lm4f232/Libraries/driverlib/gpio.h index ba7d00b650..5320682910 100644 --- a/bsp/lm4f232/Libraries/driverlib/gpio.h +++ b/bsp/lm4f232/Libraries/driverlib/gpio.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/hibernate.c b/bsp/lm4f232/Libraries/driverlib/hibernate.c index 6c6b23136d..97d0d7fc48 100644 --- a/bsp/lm4f232/Libraries/driverlib/hibernate.c +++ b/bsp/lm4f232/Libraries/driverlib/hibernate.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -69,9 +69,9 @@ static unsigned long g_ulWriteDelay; //! \param None. //! //! On non-Fury-class devices, the hibernate module provides an indication when -//! any write is completed. This is used to pace writes to the module. This -//! function merely polls this bit and returns as soon as it is set. At this -//! point, it is safe to perform another write to the module. +//! any write is completed. This mechanism is used to pace writes to the +//! module. This function merely polls this bit and returns as soon as it is +//! set. At this point, it is safe to perform another write to the module. //! //! \return None. // @@ -108,10 +108,10 @@ HibernateWriteComplete(void) //! \param ulHibClk is the rate of the clock supplied to the Hibernation //! module. //! -//! Enables the Hibernation module for operation. This function should be -//! called before any of the Hibernation module features are used. +//! This function enables the Hibernation module for operation. This function +//! should be called before any of the Hibernation module features are used. //! -//! The peripheral clock is the same as the processor clock. This is the value +//! The peripheral clock is the same as the processor clock. This value is //! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtlClockGet()). @@ -156,8 +156,8 @@ HibernateEnableExpClk(unsigned long ulHibClk) // //! Disables the Hibernation module for operation. //! -//! Disables the Hibernation module for operation. After this function is -//! called, none of the Hibernation module features are available. +//! This function disables the Hibernation module for operation. After this +//! function is called, none of the Hibernation module features are available. //! //! \return None. // @@ -182,10 +182,10 @@ HibernateDisable(void) //! //! \param ulClockInput specifies the clock input. //! -//! Configures the clock input for the Hibernation module. The configuration -//! option chosen depends entirely on hardware design. The clock input for the -//! module will either be a 32.768 kHz oscillator or a 4.194304 MHz crystal. -//! The \e ulClockFlags parameter must be one of the following: +//! This function configures the clock input for the Hibernation module. The +//! configuration option chosen depends entirely on hardware design. The clock +//! input for the module is either a 32.768 kHz oscillator or a 4.194304 MHz +//! crystal. The \e ulClockFlags parameter must be one of the following: //! //! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz //! oscillator. @@ -289,10 +289,10 @@ HibernateClockConfig(unsigned long ulConfig) // //! Enables the RTC feature of the Hibernation module. //! -//! Enables the RTC in the Hibernation module. The RTC can be used to wake the -//! processor from hibernation at a certain time, or to generate interrupts at -//! certain times. This function must be called before using any of the RTC -//! features of the Hibernation module. +//! This function enables the RTC in the Hibernation module. The RTC can be +//! used to wake the processor from hibernation at a certain time, or to +//! generate interrupts at certain times. This function must be called before +//! using any of the RTC features of the Hibernation module. //! //! \return None. // @@ -315,8 +315,9 @@ HibernateRTCEnable(void) // //! Disables the RTC feature of the Hibernation module. //! -//! Disables the RTC in the Hibernation module. After calling this function -//! the RTC features of the Hibernation module will not be available. +//! This function disables the RTC in the Hibernation module. After calling +//! this function, the RTC features of the Hibernation module are not +//! available. //! //! \return None. // @@ -350,6 +351,7 @@ HibernateRTCDisable(void) //! indicate that the battery level is low. //! //! \note A hibernation request is held off if a battery check is in progress. +//! This function is only available on some Stellaris devices. //! //! \return None. // @@ -373,15 +375,17 @@ HibernateBatCheckStart(void) //! Returns if a forced battery check has completed. //! //! This function returns if the forced battery check initiated by a call to -//! the HibernateBatCheckStart() function has completed. This function will -//! return a non-zero value until the battery level check has completed. Once +//! the HibernateBatCheckStart() function has completed. This function +//! returns a non-zero value until the battery level check has completed. Once //! this function returns a value of zero, the hibernation module has completed //! the battery check and the HibernateIntStatus() function can be used to //! check if the battery was low by checking if the value returned has the //! \b HIBERNATE_INT_LOW_BAT set. //! +//! \note This function is only available on some Stellaris devices. +//! //! \return The value is zero when the battery level check has completed or -//! non-zero if the check is still in process. +//! non-zero if the check is still in process. // //***************************************************************************** unsigned long @@ -399,15 +403,18 @@ HibernateBatCheckDone(void) //! //! \param ulWakeFlags specifies which conditions should be used for waking. //! -//! Enables the conditions under which the Hibernation module will wake. The -//! \e ulWakeFlags parameter is the logical OR of any combination of the -//! following: +//! This function enables the conditions under which the Hibernation module +//! wakes. The \e ulWakeFlags parameter is the logical OR of any combination +//! of the following: //! //! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. //! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. //! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low battery //! level being detected. //! +//! \note The \b HIBERNATE_WAKE_LOW_BAT parameter is only available on some +//! Stellaris devices. +//! //! \return None. // //***************************************************************************** @@ -438,14 +445,18 @@ HibernateWakeSet(unsigned long ulWakeFlags) // //! Gets the currently configured wake conditions for the Hibernation module. //! -//! Returns the flags representing the wake configuration for the Hibernation -//! module. The return value is a combination of the following flags: +//! This function returns the flags representing the wake configuration for the +//! Hibernation module. The return value is a combination of the following +//! flags: //! //! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. //! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. //! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low battery //! level being detected. //! +//! \note The \b HIBERNATE_WAKE_LOW_BAT parameter is only available on some +//! Stellaris devices. +//! //! \return Returns flags indicating the configured wake conditions. // //***************************************************************************** @@ -466,11 +477,11 @@ HibernateWakeGet(void) //! //! \param ulLowBatFlags specifies behavior of low battery detection. //! -//! Enables the low battery detection and whether hibernation is allowed if a -//! low battery is detected. If low battery detection is enabled, then a low -//! battery condition is indicated in the raw interrupt status register, and -//! can also trigger an interrupt. Optionally, hibernation can be aborted if a -//! low battery is detected. +//! This function enables the low battery detection and whether hibernation is +//! allowed if a low battery is detected. If low battery detection is enabled, +//! then a low battery condition is indicated in the raw interrupt status +//! register, and can also trigger an interrupt. Optionally, hibernation can be +//! aborted if a low battery is detected. //! //! The \e ulLowBatFlags parameter is one of the following values: //! @@ -492,6 +503,9 @@ HibernateWakeGet(void) //! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V); //! \endverbatim //! +//! \note The parameters with the specific voltage levels are only available on +//! some Stellaris devices. +//! //! \return None. // //***************************************************************************** @@ -521,8 +535,8 @@ HibernateLowBatSet(unsigned long ulLowBatFlags) // //! Gets the currently configured low battery detection behavior. //! -//! Returns a value representing the currently configured low battery detection -//! behavior. +//! This function returns a value representing the currently configured low +//! battery detection behavior. //! //! The return value is a combination of the values described in the //! HibernateLowBatSet() function. @@ -546,8 +560,8 @@ HibernateLowBatGet(void) //! //! \param ulRTCValue is the new value for the RTC. //! -//! Sets the value of the RTC. The RTC will count seconds if the hardware is -//! configured correctly. The RTC must be enabled by calling +//! This function sets the value of the RTC. The RTC count seconds if the +//! hardware is configured correctly. The RTC must be enabled by calling //! HibernateRTCEnable() before calling this function. //! //! \return None. @@ -571,7 +585,7 @@ HibernateRTCSet(unsigned long ulRTCValue) // //! Gets the value of the real time clock (RTC) counter. //! -//! Gets the value of the RTC and returns it to the caller. +//! This function gets the value of the RTC and returns it to the caller. //! //! \return Returns the value of the RTC. // @@ -591,9 +605,10 @@ HibernateRTCGet(void) //! //! \param ulMatch is the value for the match register. //! -//! Sets the match 0 register for the RTC. The Hibernation module can be -//! configured to wake from hibernation, and/or generate an interrupt when the -//! value of the RTC counter is the same as the match register. +//! This function sets the match 0 register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. //! //! \return None. // @@ -616,7 +631,7 @@ HibernateRTCMatch0Set(unsigned long ulMatch) // //! Gets the value of the RTC match 0 register. //! -//! Gets the value of the match 0 register for the RTC. +//! This function gets the value of the match 0 register for the RTC. //! //! \return Returns the value of the match register. // @@ -636,9 +651,10 @@ HibernateRTCMatch0Get(void) //! //! \param ulMatch is the value for the match register. //! -//! Sets the match 1 register for the RTC. The Hibernation module can be -//! configured to wake from hibernation, and/or generate an interrupt when the -//! value of the RTC counter is the same as the match register. +//! This function sets the match 1 register for the RTC. The Hibernation +//! module can be configured to wake from hibernation, and/or generate an +//! interrupt when the value of the RTC counter is the same as the match +//! register. //! //! \note The Hibernation RTC Match 1 feature is not available on all Stellaris //! devices. Please consult the data sheet for the Stellaris device that you @@ -665,7 +681,7 @@ HibernateRTCMatch1Set(unsigned long ulMatch) // //! Gets the value of the RTC match 1 register. //! -//! Gets the value of the match 1 register for the RTC. +//! This function gets the value of the match 1 register for the RTC. //! //! \note The Hibernation RTC Match 1 feature is not available on all Stellaris //! devices. Please consult the data sheet for the Stellaris device that you @@ -689,10 +705,11 @@ HibernateRTCMatch1Get(void) //! //! \param ulMatch is the value for the sub second match register. //! -//! Sets the sub second match 0 register for the RTC in 1/32768 of a second -//! increments. The Hibernation module can be configured to wake from -//! hibernation, and/or generate an interrupt when the value of the RTC counter -//! is the same as the match combined with the sub second match register. +//! This function sets the sub second match 0 register for the RTC in 1/32768 +//! of a second increments. The Hibernation module can be configured to wake +//! from hibernation, and/or generate an interrupt when the value of the RTC +//! counter is the same as the match combined with the sub second match +//! register. //! //! \note The Hibernation sub second RTC Match 0 feature is not available on //! all Stellaris devices. Please consult the data sheet for the Stellaris @@ -742,7 +759,7 @@ HibernateRTCSSMatch0Get(void) // //! Returns the current value of the RTC sub second count. //! -//! This function will return the current value of the sub second count for the +//! This function returns the current value of the sub second count for the //! for the RTC in 1/32768 of a second increments. //! //! \note The Hibernation sub second RTC Match 0 feature is not available on @@ -767,14 +784,14 @@ HibernateRTCSSGet(void) //! //! \param ulTrim is the new value for the pre-divider trim register. //! -//! Sets the value of the pre-divider trim register. The input time source is -//! divided by the pre-divider to achieve a one-second clock rate. Once every -//! 64 seconds, the value of the pre-divider trim register is applied to the -//! predivider to allow fine-tuning of the RTC rate, in order to make -//! corrections to the rate. The software application can make adjustments to -//! the predivider trim register to account for variations in the accuracy of -//! the input time source. The nominal value is 0x7FFF, and it can be adjusted -//! up or down in order to fine-tune the RTC rate. +//! This function sets the value of the pre-divider trim register. The input +//! time source is divided by the pre-divider to achieve a one-second clock +//! rate. Once every 64 seconds, the value of the pre-divider trim register is +//! applied to the predivider to allow fine-tuning of the RTC rate, in order +//! to make corrections to the rate. The software application can make +//! adjustments to the predivider trim register to account for variations in +//! the accuracy of the input time source. The nominal value is 0x7FFF, and it +//! can be adjusted up or down in order to fine-tune the RTC rate. //! //! \return None. // @@ -802,9 +819,9 @@ HibernateRTCTrimSet(unsigned long ulTrim) // //! Gets the value of the RTC predivider trim register. //! -//! Gets the value of the pre-divider trim register. This function can be used -//! to get the current value of the trim register prior to making an adjustment -//! by using the HibernateRTCTrimSet() function. +//! This function gets the value of the pre-divider trim register. This +//! function can be used to get the current value of the trim register prior +//! to making an adjustment by using the HibernateRTCTrimSet() function. //! //! \return None. // @@ -820,17 +837,17 @@ HibernateRTCTrimGet(void) //***************************************************************************** // -//! Stores data in the non-volatile memory of the Hibernation module. +//! Stores data in the battery-backed memory of the Hibernation module. //! //! \param pulData points to the data that the caller wants to store in the //! memory of the Hibernation module. //! \param ulCount is the count of 32-bit words to store. //! -//! Stores a set of data in the Hibernation module non-volatile memory. This -//! memory is preserved when the power to the processor is turned off, and can -//! be used to store application state information which will be available when -//! the processor wakes. Up to 64 32-bit words can be stored in the -//! non-volatile memory. The data can be restored by calling the +//! Stores a set of data in the Hibernation module battery-backed memory. +//! This memory is preserved when the power to the processor is turned off, +//! and can be used to store application state information which is available +//! when the processor wakes. Up to 64 32-bit words can be stored in the +//! battery-backed memory. The data can be restored by calling the //! HibernateDataGet() function. //! //! \note The amount of memory available in the Hibernation module varies @@ -858,7 +875,7 @@ HibernateDataSet(unsigned long *pulData, unsigned long ulCount) for(ulIdx = 0; ulIdx < ulCount; ulIdx++) { // - // Write a word to the non-volatile storage area. + // Write a word to the battery-backed storage area. // HWREG(HIB_DATA + (ulIdx * 4)) = pulData[ulIdx]; @@ -871,16 +888,18 @@ HibernateDataSet(unsigned long *pulData, unsigned long ulCount) //***************************************************************************** // -//! Reads a set of data from the non-volatile memory of the Hibernation module. +//! Reads a set of data from the battery-backed memory of the Hibernation +//! module. //! //! \param pulData points to a location where the data that is read from the -//! Hibernation module will be stored. +//! Hibernation module is stored. //! \param ulCount is the count of 32-bit words to read. //! -//! Retrieves a set of data from the Hibernation module non-volatile memory -//! that was previously stored with the HibernateDataSet() function. The -//! caller must ensure that \e pulData points to a large enough memory block to -//! hold all the data that is read from the non-volatile memory. +//! This function retrieves a set of data from the Hibernation module battery- +//! backed memory that was previously stored with the HibernateDataSet() +//! function. The caller must ensure that \e pulData points to a large enough +//! memory block to hold all the data that is read from the battery-backed +//! memory. //! //! \note The amount of memory available in the Hibernation module varies //! across Stellaris devices. Please consult the data sheet for the Stellaris @@ -907,7 +926,7 @@ HibernateDataGet(unsigned long *pulData, unsigned long ulCount) for(ulIdx = 0; ulIdx < ulCount; ulIdx++) { // - // Read a word from the non-volatile storage area. No delay is + // Read a word from the battery-backed storage area. No delay is // required between reads. // pulData[ulIdx] = HWREG(HIB_DATA + (ulIdx * 4)); @@ -920,24 +939,25 @@ HibernateDataGet(unsigned long *pulData, unsigned long ulCount) //! //! This function requests the Hibernation module to disable the external //! regulator, thus removing power from the processor and all peripherals. The -//! Hibernation module will remain powered from the battery or auxiliary power +//! Hibernation module remains powered from the battery or auxiliary power //! supply. //! -//! The Hibernation module will re-enable the external regulator when one of +//! The Hibernation module re-enables the external regulator when one of //! the configured wake conditions occurs (such as RTC match or external -//! \b WAKE pin). When the power is restored the processor will go through a -//! normal power-on reset. The processor can retrieve saved state information -//! with the HibernateDataGet() function. Prior to calling the function to -//! request hibernation mode, the conditions for waking must have already been -//! set by using the HibernateWakeSet() function. +//! \b WAKE pin). When the power is restored the processor goes through a +//! power-on reset although the Hibernation module is not reset. The processor +//! can retrieve saved state information with the HibernateDataGet() function. +//! Prior to calling the function to request hibernation mode, the conditions +//! for waking must have already been set by using the HibernateWakeSet() +//! function. //! //! Note that this function may return because some time may elapse before the //! power is actually removed, or it may not be removed at all. For this -//! reason, the processor will continue to execute instructions for some time +//! reason, the processor continues to execute instructions for some time //! and the caller should be prepared for this function to return. There are //! various reasons why the power may not be removed. For example, if the //! HibernateLowBatSet() function was used to configure an abort if low -//! battery is detected, then the power will not be removed if the battery +//! battery is detected, then the power is not removed if the battery //! voltage is too low. There may be other reasons, related to the external //! circuit design, that a request for hibernation may not actually occur. //! @@ -968,7 +988,8 @@ HibernateRequest(void) //! //! \param ulIntFlags is the bit mask of the interrupts to be enabled. //! -//! Enables the specified interrupt sources from the Hibernation module. +//! This function enables the specified interrupt sources from the Hibernation +//! module. //! //! The \e ulIntFlags parameter must be the logical OR of any combination of //! the following: @@ -979,10 +1000,10 @@ HibernateRequest(void) //! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt //! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt //! -//! \note The \b HIBERNATE_INT_RTC_MATCH_1 setting is not available on all -//! Stellaris devices. Please consult the data sheet for the Stellaris device -//! that you are using to determine if the Hibernation RTC Match 1 feature is -//! available. +//! \note The \b HIBERNATE_INT_WR_COMPLETE and \b HIBERNATE_INT_RTC_MATCH_1 +//! settings are not available on all Stellaris devices. Please consult the +//! data sheet for the Stellaris device that you are using to determine if +//! these interrupt sources are available. //! //! \return None. // @@ -1015,7 +1036,8 @@ HibernateIntEnable(unsigned long ulIntFlags) //! //! \param ulIntFlags is the bit mask of the interrupts to be disabled. //! -//! Disables the specified interrupt sources from the Hibernation module. +//! This function disables the specified interrupt sources from the +//! Hibernation module. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to the HibernateIntEnable() function. @@ -1052,9 +1074,10 @@ HibernateIntDisable(unsigned long ulIntFlags) //! \param pfnHandler points to the function to be called when a hibernation //! interrupt occurs. //! -//! Registers the interrupt handler in the system interrupt controller. The -//! interrupt is enabled at the global level, but individual interrupt sources -//! must still be enabled with a call to HibernateIntEnable(). +//! This function registers the interrupt handler in the system interrupt +//! controller. The interrupt is enabled at the global level, but individual +//! interrupt sources must still be enabled with a call to +//! HibernateIntEnable(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1080,9 +1103,9 @@ HibernateIntRegister(void (*pfnHandler)(void)) // //! Unregisters an interrupt handler for the Hibernation module interrupt. //! -//! Unregisters the interrupt handler in the system interrupt controller. The -//! interrupt is disabled at the global level, and the interrupt handler will -//! no longer be called. +//! This function unregisters the interrupt handler in the system interrupt +//! controller. The interrupt is disabled at the global level, and the +//! interrupt handler is longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1111,9 +1134,9 @@ HibernateIntUnregister(void) //! \param bMasked is false to retrieve the raw interrupt status, and true to //! retrieve the masked interrupt status. //! -//! Returns the interrupt status of the Hibernation module. The caller can use -//! this to determine the cause of a hibernation interrupt. Either the masked -//! or raw interrupt status can be returned. +//! This function returns the interrupt status of the Hibernation module. The +//! caller can use this function to determine the cause of a hibernation +//! interrupt. Either the masked or raw interrupt status can be returned. //! //! \return Returns the interrupt status as a bit field with the values as //! described in the HibernateIntEnable() function. @@ -1141,13 +1164,14 @@ HibernateIntStatus(tBoolean bMasked) //! //! \param ulIntFlags is the bit mask of the interrupts to be cleared. //! -//! Clears the specified interrupt sources. This must be done from within the -//! interrupt handler or else the handler is called again upon exit. +//! This function clears the specified interrupt sources. This function must +//! be called within the interrupt handler or else the handler is called again +//! upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to the HibernateIntEnable() function. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid diff --git a/bsp/lm4f232/Libraries/driverlib/hibernate.h b/bsp/lm4f232/Libraries/driverlib/hibernate.h index 48ec1e054b..87cdf3d558 100644 --- a/bsp/lm4f232/Libraries/driverlib/hibernate.h +++ b/bsp/lm4f232/Libraries/driverlib/hibernate.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/i2c.c b/bsp/lm4f232/Libraries/driverlib/i2c.c index 7c1b8c6d60..87d363e9f6 100644 --- a/bsp/lm4f232/Libraries/driverlib/i2c.c +++ b/bsp/lm4f232/Libraries/driverlib/i2c.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -106,9 +106,10 @@ I2CSlaveBaseValid(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Master module. //! -//! Given a I2C base address, returns the corresponding interrupt number. +//! Given a I2C base address, this function returns the corresponding +//! interrupt number. //! -//! \return Returns a I2C interrupt number, or -1 if \e ulBase is invalid. +//! \return Returns an I2C interrupt number, or -1 if \e ulBase is invalid. // //***************************************************************************** static long @@ -149,15 +150,14 @@ I2CIntNumberGet(unsigned long ulBase) //! \param ulI2CClk is the rate of the clock supplied to the I2C module. //! \param bFast set up for fast data transfers //! -//! This function initializes operation of the I2C Master block. Upon -//! successful initialization of the I2C block, this function will have set the -//! bus speed for the master, and will have enabled the I2C Master block. +//! This function initializes operation of the I2C Master block by configuring +//! the bus speed for the master and enabling the I2C Master block. //! //! If the parameter \e bFast is \b true, then the master block is set up to //! transfer data at 400 kbps; otherwise, it is set up to transfer data at //! 100 kbps. //! -//! The peripheral clock is the same as the processor clock. This is the value +//! The peripheral clock is the same as the processor clock. This value is //! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtlClockGet()). @@ -215,9 +215,8 @@ I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, //! \param ulBase is the base address of the I2C Slave module. //! \param ucSlaveAddr 7-bit slave address //! -//! This function initializes operation of the I2C Slave block. Upon -//! successful initialization of the I2C blocks, this function will have set -//! the slave address and have enabled the I2C Slave block. +//! This function initializes operation of the I2C Slave block by configuring +//! the slave address and enabling the I2C Slave block. //! //! The parameter \e ucSlaveAddr is the value that is compared against the //! slave address sent by an I2C master. @@ -255,7 +254,10 @@ I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) //! //! This function writes the specified slave address. The \e ulAddrNum field //! dictates which slave address is configured. For example, a value of 0 -//! configures the primary address and a value of 1 the secondary. +//! configures the primary address and a value of 1, the secondary. +//! +//! \note Not all Stellaris devices support a secondary address. Please consult +//! the device data sheet to know if this feature is supported. //! //! \return None. // @@ -302,7 +304,7 @@ I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum, //! //! \param ulBase is the base address of the I2C Master module. //! -//! This will enable operation of the I2C Master block. +//! This function enables operation of the I2C Master block. //! //! \return None. // @@ -327,7 +329,7 @@ I2CMasterEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! This will enable operation of the I2C Slave block. +//! This fucntion enables operation of the I2C Slave block. //! //! \return None. // @@ -358,7 +360,7 @@ I2CSlaveEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Master module. //! -//! This will disable operation of the I2C master block. +//! This function disables operation of the I2C master block. //! //! \return None. // @@ -383,7 +385,7 @@ I2CMasterDisable(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! This will disable operation of the I2C slave block. +//! This function disables operation of the I2C slave block. //! //! \return None. // @@ -416,9 +418,9 @@ I2CSlaveDisable(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! I2C interrupt occurs. //! -//! This sets the handler to be called when an I2C interrupt occurs. This will -//! enable the global interrupt in the interrupt controller; specific I2C -//! interrupts must be enabled via I2CMasterIntEnable() and +//! This function sets the handler to be called when an I2C interrupt occurs. +//! This function enables the global interrupt in the interrupt controller; +//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and //! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's //! responsibility to clear the interrupt source via I2CMasterIntClear() and //! I2CSlaveIntClear(). @@ -461,9 +463,9 @@ I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the base address of the I2C Master module. //! -//! This function will clear the handler to be called when an I2C interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. +//! This function clears the handler to be called when an I2C interrupt +//! occurs. This function also masks off the interrupt in the interrupt r +//! controlle so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -503,7 +505,7 @@ I2CIntUnregister(unsigned long ulBase) //! //! \param ulBase is the base address of the I2C Master module. //! -//! Enables the I2C Master interrupt source. +//! This function enables the I2C Master interrupt source. //! //! \return None. // @@ -529,15 +531,19 @@ I2CMasterIntEnable(unsigned long ulBase) //! \param ulBase is the base address of the I2C Master module. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated I2C Master interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function enables the indicated I2C Master interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! //! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt //! - \b I2C_MASTER_INT_DATA - Data interrupt //! +//! \note Not all Stellaris devices support the Clock Timeout interrupt. +//! Please consult the device data sheet to know if this feature is +//! supported. +//! //! \return None. // //***************************************************************************** @@ -561,7 +567,7 @@ I2CMasterIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! Enables the I2C Slave interrupt source. +//! This function enables the I2C Slave interrupt source. //! //! \return None. // @@ -587,9 +593,9 @@ I2CSlaveIntEnable(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated I2C Slave interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function enables the indicated I2C Slave interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! @@ -597,6 +603,10 @@ I2CSlaveIntEnable(unsigned long ulBase) //! - \b I2C_SLAVE_INT_START - Start condition detected interrupt //! - \b I2C_SLAVE_INT_DATA - Data interrupt //! +//! \note Not all Stellaris devices support the Stop and Start condition +//! interrupts. Please consult the device data sheet to know if these features +//! are supported. +//! //! \return None. // //***************************************************************************** @@ -620,7 +630,7 @@ I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) //! //! \param ulBase is the base address of the I2C Master module. //! -//! Disables the I2C Master interrupt source. +//! This function disables the I2C Master interrupt source. //! //! \return None. // @@ -646,9 +656,9 @@ I2CMasterIntDisable(unsigned long ulBase) //! \param ulBase is the base address of the I2C Master module. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated I2C Master interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function disables the indicated I2C Master interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to I2CMasterIntEnableEx(). @@ -676,7 +686,7 @@ I2CMasterIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! Disables the I2C Slave interrupt source. +//! This function disables the I2C Slave interrupt source. //! //! \return None. // @@ -702,9 +712,9 @@ I2CSlaveIntDisable(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated I2C Slave interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. +//! This function disables the indicated I2C Slave interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to I2CSlaveIntEnableEx(). @@ -734,8 +744,8 @@ I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Master module. Either the -//! raw interrupt status or the status of interrupts that are allowed to +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are allowed to //! reflect to the processor can be returned. //! //! \return The current interrupt status, returned as \b true if active @@ -772,9 +782,9 @@ I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Master module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in I2CMasterIntEnableEx(). @@ -810,9 +820,9 @@ I2CMasterIntStatusEx(unsigned long ulBase, tBoolean bMasked) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Slave module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return The current interrupt status, returned as \b true if active //! or \b false if not active. @@ -848,9 +858,9 @@ I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param bMasked is false if the raw interrupt status is requested and //! true if the masked interrupt status is requested. //! -//! This returns the interrupt status for the I2C Slave module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in I2CSlaveIntEnableEx(). @@ -899,10 +909,10 @@ I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the base address of the I2C Master module. //! //! The I2C Master interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -943,13 +953,13 @@ I2CMasterIntClear(unsigned long ulBase) //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified I2C Master interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to I2CMasterIntEnableEx(). //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -982,10 +992,10 @@ I2CMasterIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase is the base address of the I2C Slave module. //! //! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1019,13 +1029,13 @@ I2CSlaveIntClear(unsigned long ulBase) //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to I2CSlaveIntEnableEx(). //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1053,16 +1063,16 @@ I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) //***************************************************************************** // -//! Sets the address that the I2C Master will place on the bus. +//! Sets the address that the I2C Master places on the bus. //! //! \param ulBase is the base address of the I2C Master module. //! \param ucSlaveAddr 7-bit slave address //! \param bReceive flag indicating the type of communication with the slave //! -//! This function will set the address that the I2C Master will place on the +//! This function configures the address that the I2C Master places on the //! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address will indicate that the I2C Master is initiating a -//! read from the slave; otherwise the address will indicate that the I2C +//! to \b true, the address indicates that the I2C Master is initiating a +//! read from the slave; otherwise the address indicates that the I2C //! Master is initiating a write to the slave. //! //! \return None. @@ -1093,6 +1103,9 @@ I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, //! This function returns the state of the I2C bus by providing the real time //! values of the SDA and SCL pins. //! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to know if this feature is supported. +//! //! \return Returns the state of the bus with SDA in bit position 1 and SCL in //! bit position 0. // @@ -1185,7 +1198,7 @@ I2CMasterBusBusy(unsigned long ulBase) //! Controls the state of the I2C Master module. //! //! \param ulBase is the base address of the I2C Master module. -//! \param ulCmd command to be issued to the I2C Master module +//! \param ulCmd command to be issued to the I2C Master module. //! //! This function is used to control the state of the Master module send and //! receive operations. The \e ucCmd parameter can be one of the following @@ -1285,9 +1298,9 @@ I2CMasterErr(unsigned long ulBase) //! Transmits a byte from the I2C Master. //! //! \param ulBase is the base address of the I2C Master module. -//! \param ucData data to be transmitted from the I2C Master +//! \param ucData data to be transmitted from the I2C Master. //! -//! This function will place the supplied data into I2C Master Data Register. +//! This function places the supplied data into I2C Master Data Register. //! //! \return None. // @@ -1344,6 +1357,9 @@ I2CMasterDataGet(unsigned long ulBase) //! upper 8-bits being programmable. For example, to program a timeout of 20ms //! with a 100kHz SCL frequency, \e ulValue would be 0x7d. //! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to know if this feature is supported. +//! //! \return None. // //***************************************************************************** @@ -1371,6 +1387,9 @@ I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue) //! This function enables or disables ACK override, allowing the user //! application to drive the value on SDA during the ACK cycle. //! +//! \note Not all Stellaris devices support this function. Please consult the +//! device data sheet to know if this feature is supported. +//! //! \return None. // //***************************************************************************** @@ -1436,7 +1455,7 @@ I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK) //! //! \param ulBase is the base address of the I2C Slave module. //! -//! This function will return the action requested from a master, if any. +//! This function returns the action requested from a master, if any. //! Possible values are: //! //! - \b I2C_SLAVE_ACT_NONE @@ -1457,6 +1476,10 @@ I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK) //! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick //! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the //! data bit was set when the quick command was received. +//! +//! \note Not all Stellaris devices support the second I2C slave's own address +//! or the quick command function. Please consult the device data sheet to +//! know if these features are supported. // //***************************************************************************** unsigned long @@ -1480,7 +1503,7 @@ I2CSlaveStatus(unsigned long ulBase) //! \param ulBase is the base address of the I2C Slave module. //! \param ucData data to be transmitted from the I2C Slave //! -//! This function will place the supplied data into I2C Slave Data Register. +//! This function places the supplied data into I2C Slave Data Register. //! //! \return None. // diff --git a/bsp/lm4f232/Libraries/driverlib/i2c.h b/bsp/lm4f232/Libraries/driverlib/i2c.h index 318e6e955a..e85a9cad40 100644 --- a/bsp/lm4f232/Libraries/driverlib/i2c.h +++ b/bsp/lm4f232/Libraries/driverlib/i2c.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/i2s.c b/bsp/lm4f232/Libraries/driverlib/i2s.c index fe7dc610d4..3cd12ffb64 100644 --- a/bsp/lm4f232/Libraries/driverlib/i2s.c +++ b/bsp/lm4f232/Libraries/driverlib/i2s.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -101,9 +101,9 @@ I2STxDisable(unsigned long ulBase) //! Writes data samples to the I2S transmit FIFO with blocking. //! //! \param ulBase is the I2S module base address. -//! \param ulData is the single or dual channel I2S data. +//! \param ulData is the single- or dual-channel I2S data. //! -//! This function writes a single channel sample or combined left-right +//! This function writes a single-channel sample or combined left-right //! samples to the I2S transmit FIFO. The format of the sample is determined //! by the configuration that was used with the function I2STxConfigSet(). //! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData @@ -122,7 +122,7 @@ I2STxDisable(unsigned long ulBase) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no room in the transmit FIFO, then this function will wait +//! If there is no room in the transmit FIFO, then this function waits //! in a polling loop until the data can be written. //! //! \return None. @@ -154,9 +154,9 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData) //! Writes data samples to the I2S transmit FIFO without blocking. //! //! \param ulBase is the I2S module base address. -//! \param ulData is the single or dual channel I2S data. +//! \param ulData is the single- or dual-channel I2S data. //! -//! This function writes a single channel sample or combined left-right +//! This function writes a single-channel sample or combined left-right //! samples to the I2S transmit FIFO. The format of the sample is determined //! by the configuration that was used with the function I2STxConfigSet(). //! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData @@ -165,7 +165,7 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData) //! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or //! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both //! the left and right samples. If the transmit mode is -//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single +//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single- //! channel sample. //! //! For the compact modes, both the left and right samples are written at @@ -175,7 +175,7 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no room in the transmit FIFO, then this function will return +//! If there is no room in the transmit FIFO, then this function returns //! immediately without writing any data to the FIFO. //! //! \return The number of elements written to the I2S transmit FIFO (1 or 0). @@ -256,7 +256,7 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) // // If compact 8 mode is used, then need to adjust some bits // before writing the config register. Also set the FIFO - // config register for 8 bit compact samples. + // config register for 8-bit compact samples. // ulConfig &= ~I2S_CONFIG_MODE_MONO; HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; @@ -265,14 +265,14 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) { // // If compact 8 mode is not used, then set the FIFO config - // register for 16 bit. This is okay if a compact mode is - // not used. + // register for 16 bit. This setting is okay if a compact + // mode is not used. // HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; } // - // Write the configuration register. Since all the fields are + // Write the configuration register. Because all the fields are // specified by the configuration parameter, it is not necessary // to do a read-modify-write. // @@ -287,8 +287,8 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! \param ulLevel is the FIFO service request limit. //! //! This function is used to set the transmit FIFO fullness level at which a -//! service request will occur. The service request is used to generate an -//! interrupt or a DMA transfer request. The transmit FIFO will generate a +//! service request occurs. The service request is used to generate an +//! interrupt or a DMA transfer request. The transmit FIFO generates a //! service request when the number of items in the FIFO is less than the level //! specified in the \e ulLevel parameter. For example, if \e ulLevel is 8, //! then a service request is generated when there are less than 8 samples @@ -297,9 +297,9 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! For the purposes of counting the FIFO level, a left-right sample pair //! counts as 2, whether the mode is dual or compact stereo. When mono mode is //! used, internally the mono sample is still treated as a sample pair, so a -//! single mono sample counts as 2. Since the FIFO always deals with sample +//! single mono sample counts as 2. Because the FIFO always deals with sample //! pairs, the level must be an even number from 0 to 16. The maximum value is -//! 16, which will cause a service request when there is any room in the FIFO. +//! 16, which causes a service request when there is any room in the FIFO. //! The minimum value is 0, which disables the service request. //! //! \return None. @@ -357,14 +357,14 @@ I2STxFIFOLimitGet(unsigned long ulBase) //! For the purposes of measuring the FIFO level, a left-right sample pair //! counts as 2, whether the mode is dual or compact stereo. When mono mode is //! used, internally the mono sample is still treated as a sample pair, so a -//! single mono sample counts as 2. Since the FIFO always deals with sample +//! single mono sample counts as 2. Because the FIFO always deals with sample //! pairs, normally the level is an even number from 0 to 16. If dual stereo //! mode is used and only the left sample has been written without the matching //! right sample, then the FIFO level is an odd value. If the FIFO level is //! odd, it indicates a left-right sample mismatch. //! -//! \return Returns the number of samples in the transmit FIFO, which will -//! normally be an even number. +//! \return Returns the number of samples in the transmit FIFO, which is +//! normally an even number. // //***************************************************************************** unsigned long @@ -465,7 +465,7 @@ I2SRxDisable(unsigned long ulBase) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no data in the receive FIFO, then this function will wait +//! If there is no data in the receive FIFO, then this function waits //! in a polling loop until data is available. //! //! \return None. @@ -517,7 +517,7 @@ I2SRxDataGet(unsigned long ulBase, unsigned long *pulData) //! contain the left sample, and the next 8 bits contain the right sample, //! with the upper 16 bits unused. //! -//! If there is no data in the receive FIFO, then this function will return +//! If there is no data in the receive FIFO, then this function returns //! immediately without reading any data from the FIFO. //! //! \return The number of elements read from the I2S receive FIFO (1 or 0). @@ -608,14 +608,14 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) } // - // The "mono" bits needs to be removed from the configuration word + // The "mono" bits must be removed from the configuration word // prior to writing to hardware, because the RX configuration register // does not actually use these bits. // ulConfig &= ~I2S_CONFIG_MODE_MONO; // - // Write the configuration register. Since all the fields are + // Write the configuration register. Because all the fields are // specified by the configuration parameter, it is not necessary // to do a read-modify-write. // @@ -630,8 +630,8 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! \param ulLevel is the FIFO service request limit. //! //! This function is used to set the receive FIFO fullness level at which a -//! service request will occur. The service request is used to generate an -//! interrupt or a DMA transfer request. The receive FIFO will generate a +//! service request occurs. The service request is used to generate an +//! interrupt or a DMA transfer request. The receive FIFO generates a //! service request when the number of items in the FIFO is greater than the //! level specified in the \e ulLevel parameter. For example, if \e ulLevel is //! 4, then a service request is generated when there are more than 4 samples @@ -640,9 +640,9 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! For the purposes of counting the FIFO level, a left-right sample pair //! counts as 2, whether the mode is dual or compact stereo. When mono mode is //! used, internally the mono sample is still treated as a sample pair, so a -//! single mono sample counts as 2. Since the FIFO always deals with sample +//! single mono sample counts as 2. Because the FIFO always deals with sample //! pairs, the level must be an even number from 0 to 16. The minimum value is -//! 0, which will cause a service request when there is any data available in +//! 0, which causes a service request when there is any data available in //! the FIFO. The maximum value is 16, which disables the service request //! (because there cannot be more than 16 items in the FIFO). //! @@ -687,7 +687,7 @@ I2SRxFIFOLimitGet(unsigned long ulBase) // // Read and return the FIFO limit. The lower bit is masked - // because it always reads as 1, and has no meaning. + // because it always reads as 1 and has no meaning. // return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); } @@ -702,14 +702,14 @@ I2SRxFIFOLimitGet(unsigned long ulBase) //! For the purposes of measuring the FIFO level, a left-right sample pair //! counts as 2, whether the mode is dual or compact stereo. When mono mode is //! used, internally the mono sample is still treated as a sample pair, so a -//! single mono sample counts as 2. Since the FIFO always deals with sample +//! single mono sample counts as 2. Because the FIFO always deals with sample //! pairs, normally the level is an even number from 0 to 16. If dual stereo //! mode is used and only the left sample has been read without reading the //! matching right sample, then the FIFO level is an odd value. If the FIFO //! level is odd, it indicates a left-right sample mismatch. //! -//! \return Returns the number of samples in the transmit FIFO, which will -//! normally be an even number. +//! \return Returns the number of samples in the transmit FIFO, which is +//! normally an even number. // //***************************************************************************** unsigned long @@ -735,7 +735,7 @@ I2SRxFIFOLevelGet(unsigned long ulBase) //! This function simultaneously enables the transmit and receive modules for //! operation, providing a synchronized SCLK and LRCLK. The module should be //! enabled after configuration. When the module is disabled, no data or -//! clocks will be generated on the I2S signals. +//! clocks are generated on the I2S signals. //! //! \return None. // @@ -771,7 +771,7 @@ I2STxRxEnable(unsigned long ulBase) //! \param ulBase is the I2S module base address. //! //! This function simultaneously disables the transmit and receive modules. -//! When the module is disabled, no data or clocks will be generated on the I2S +//! When the module is disabled, no data or clocks are generated on the I2S //! signals. //! //! \return None. @@ -806,10 +806,10 @@ I2STxRxDisable(unsigned long ulBase) //! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or //! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. //! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. -//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, +//! - \b I2S_CONFIG_MODE_DUAL for dual-channel stereo, //! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, //! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or -//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! \b I2S_CONFIG_MODE_MONO for single-channel mono format. //! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether //! the I2S transmitter is the clock master or slave. //! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 @@ -861,8 +861,8 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) } // - // Write the configuration register. Since all the fields are specified by - // the configuration parameter, it is not necessary to do a + // Write the configuration register. Because all the fields are specified + // by the configuration parameter, it is not necessary to do a // read-modify-write. // HWREG(ulBase + I2S_O_TXCFG) = ulConfig; @@ -878,7 +878,7 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) //! choices. //! //! This function selects whether the master clock is sourced from the device -//! internal PLL, or comes from an external pin. The I2S serial bit clock +//! internal PLL or comes from an external pin. The I2S serial bit clock //! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master //! clock. The transmit and receive modules can be configured independently. //! The \e ulMClock parameter is chosen from the following: @@ -1019,13 +1019,13 @@ I2SIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the I2S module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! This function clears the specified pending I2S interrupts. This must -//! be done in the interrupt handler to keep the handler from being called -//! again immediately upon exit. The \e ulIntFlags parameter can be the -//! logical OR of any of the following values: \b I2S_INT_RXERR, +//! This function clears the specified pending I2S interrupts. This function +//! must be called in the interrupt handler to keep the interrupt from being +//! triggered again immediately upon exit. The \e ulIntFlags parameter can be +//! the logical OR of any of the following values: \b I2S_INT_RXERR, //! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1061,9 +1061,9 @@ I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags) //! \param pfnHandler is a pointer to the function to be called when the //! interrupt is activated. //! -//! This sets and enables the handler to be called when the I2S controller -//! generates an interrupt. Specific I2S interrupts must still be enabled -//! with the I2SIntEnable() function. It is the responsibility of the +//! This function sets and enables the handler to be called when the I2S +//! controller generates an interrupt. Specific I2S interrupts must still be +//! enabled with the I2SIntEnable() function. It is the responsibility of the //! interrupt handler to clear any pending interrupts with I2SIntClear(). //! //! \sa IntRegister() for important information about registering interrupt @@ -1098,7 +1098,7 @@ I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the I2S module base address. //! -//! This function will disable and clear the handler to be called when the +//! This function disables and clears the handler to be called when the //! I2S interrupt occurs. //! //! \sa IntRegister() for important information about registering interrupt diff --git a/bsp/lm4f232/Libraries/driverlib/i2s.h b/bsp/lm4f232/Libraries/driverlib/i2s.h index e011f26faf..f7abacf8c6 100644 --- a/bsp/lm4f232/Libraries/driverlib/i2s.h +++ b/bsp/lm4f232/Libraries/driverlib/i2s.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/interrupt.c b/bsp/lm4f232/Libraries/driverlib/interrupt.c index 4149308185..7eed9758b0 100644 --- a/bsp/lm4f232/Libraries/driverlib/interrupt.c +++ b/bsp/lm4f232/Libraries/driverlib/interrupt.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -166,14 +166,14 @@ void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); // //! Enables the processor interrupt. //! -//! Allows the processor to respond to interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. +//! This function allows the processor to respond to interrupts. This function +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the single interrupt from the controller to the processor. //! //! \note Previously, this function had no return value. As such, it was //! possible to include interrupt.h and call this function without //! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution +//! tBoolean, a compiler error occurs in this case. The solution //! is to include hw_types.h before including interrupt.h. //! //! \return Returns \b true if interrupts were disabled when the function was @@ -193,14 +193,15 @@ IntMasterEnable(void) // //! Disables the processor interrupt. //! -//! Prevents the processor from receiving interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. +//! This function prevents the processor from receiving interrupts. This +//! function does not affect the set of interrupts enabled in the interrupt +//! controller; it just gates the single interrupt from the controller to the +//! processor. //! //! \note Previously, this function had no return value. As such, it was //! possible to include interrupt.h and call this function without //! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution +//! tBoolean, a compiler error occurs in this case. The solution //! is to include hw_types.h before including interrupt.h. //! //! \return Returns \b true if interrupts were already disabled when the @@ -226,15 +227,15 @@ IntMasterDisable(void) //! This function is used to specify the handler function to be called when the //! given interrupt is asserted to the processor. When the interrupt occurs, //! if it is enabled (via IntEnable()), the handler function is called in -//! interrupt context. Since the handler function can preempt other code, care -//! must be taken to protect memory or peripherals that are accessed by the -//! handler and other non-handler code. +//! interrupt context. Because the handler function can preempt other code, +//! care must be taken to protect memory or peripherals that are accessed by +//! the handler and other non-handler code. //! //! \note The use of this function (directly or indirectly via a peripheral //! driver interrupt register function) moves the interrupt vector table from //! flash to SRAM. Therefore, care must be taken when linking the application //! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise NVIC will not look in the correct portion of memory for the +//! otherwise the NVIC does not look in the correct portion of memory for the //! vector table (it requires the vector table be on a 1 kB memory alignment). //! Normally, the SRAM vector table is so placed via the use of linker scripts. //! See the discussion of compile-time versus run-time interrupt handler @@ -275,7 +276,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) } // - // Point NVIC at the RAM vector table. + // Point the NVIC at the RAM vector table. // HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; } @@ -399,7 +400,7 @@ IntPriorityGroupingGet(void) //! correspond to higher interrupt priorities; priority 0 is the highest //! interrupt priority. //! -//! The hardware priority mechanism will only look at the upper N bits of the +//! The hardware priority mechanism only looks at the upper N bits of the //! priority level (where N is 3 for the Stellaris family), so any //! prioritization must be performed in those bits. The remaining bits can be //! used to sub-prioritize the interrupt sources, and may be used by the @@ -587,13 +588,13 @@ IntDisable(unsigned long ulInterrupt) //! //! \param ulInterrupt specifies the interrupt to be pended. //! -//! The specified interrupt is pended in the interrupt controller. This will -//! cause the interrupt controller to execute the corresponding interrupt -//! handler at the next available time, based on the current interrupt state -//! priorities. For example, if called by a higher priority interrupt handler, -//! the specified interrupt handler will not be called until after the current -//! interrupt handler has completed execution. The interrupt must have been -//! enabled for it to be called. +//! The specified interrupt is pended in the interrupt controller. Pending an +//! interrupt causes the interrupt controller to execute the corresponding +//! interrupt handler at the next available time, based on the current +//! interrupt state priorities. For example, if called by a higher priority +//! interrupt handler, the specified interrupt handler is not called until +//! after the current interrupt handler has completed execution. The interrupt +//! must have been enabled for it to be called. //! //! \return None. // @@ -646,10 +647,10 @@ IntPendSet(unsigned long ulInterrupt) //! //! \param ulInterrupt specifies the interrupt to be unpended. //! -//! The specified interrupt is unpended in the interrupt controller. This will -//! cause any previously generated interrupts that have not been handled yet -//! (due to higher priority interrupts or the interrupt no having been enabled -//! yet) to be discarded. +//! The specified interrupt is unpended in the interrupt controller. Unpending +//! an interrupt causes any previously generated interrupts that have not been +//! handled yet (due to higher priority interrupts or the interrupt not having +//! been enabled yet) to be discarded. //! //! \return None. // @@ -696,16 +697,16 @@ IntPendClear(unsigned long ulInterrupt) //! \param ulPriorityMask is the priority level that is masked. //! //! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level is masked. This -//! can be used to globally disable a set of interrupts with priority below -//! a predetermined threshold. A value of 0 disables priority +//! interrupts at the specified or lesser priority level are masked. Masking +//! interrupts can be used to globally disable a set of interrupts with +//! priority below a predetermined threshold. A value of 0 disables priority //! masking. //! //! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater is blocked. +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. //! -//! The hardware priority mechanism will only look at the upper N bits of the +//! The hardware priority mechanism only looks at the upper N bits of the //! priority level (where N is 3 for the Stellaris family), so any //! prioritization must be performed in those bits. //! @@ -728,10 +729,10 @@ IntPriorityMaskSet(unsigned long ulPriorityMask) //! masking is disabled. //! //! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater is blocked. +//! a priority level mask of 4 allows interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater are blocked. //! -//! The hardware priority mechanism will only look at the upper N bits of the +//! The hardware priority mechanism only looks at the upper N bits of the //! priority level (where N is 3 for the Stellaris family), so any //! prioritization must be performed in those bits. //! diff --git a/bsp/lm4f232/Libraries/driverlib/interrupt.h b/bsp/lm4f232/Libraries/driverlib/interrupt.h index b821209742..5ab98d6431 100644 --- a/bsp/lm4f232/Libraries/driverlib/interrupt.h +++ b/bsp/lm4f232/Libraries/driverlib/interrupt.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/lpc.c b/bsp/lm4f232/Libraries/driverlib/lpc.c index be412b6876..0e8cab7821 100644 --- a/bsp/lm4f232/Libraries/driverlib/lpc.c +++ b/bsp/lm4f232/Libraries/driverlib/lpc.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -79,7 +79,7 @@ LPCChannelValid(unsigned long ulChannel) //! //! The \e ulConfig parameter is the logical OR of the following values: //! - \b LPC_CFG_WAKE - Force assertion of the LPC0CLKRUN signal when the -//! LPC bus is powered down (LPC0PD asserted). +//! LPC bus is powered down (LPC0PD is asserted). //! //! \return None. // @@ -478,11 +478,11 @@ LPCIRQSend(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! LPC interrupt occurs. //! -//! This sets the handler to be called when an LPC interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific -//! LPC interrupts must be enabled via LPCIntEnable(). If necessary, it is -//! the interrupt handler's responsibility to clear the interrupt source via -//! LPCIntClear(). +//! This function registers the handler to be called when an LPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific LPC interrupts must be enabled via LPCIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via LPCIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -516,9 +516,9 @@ LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase specifies the LPC module base address. //! -//! This function will clear the handler to be called when an LPC interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when an LPC interrupt +//! occurs. This fucntion also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -552,9 +552,9 @@ LPCIntUnregister(unsigned long ulBase) //! \param ulBase specifies the LPC module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated LPC interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function enables the indicated LPC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter can be any of the following values: //! \b LPC_INT_RST, \b LPC_INT_SLEEP, \b LPC_INT_COMx, \b LPC_INT_SIRQ, @@ -588,9 +588,9 @@ LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase specifies the LPC module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated LPC interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This funciton disables the indicated LPC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! \sa The description of the LPCIntEnable() function provides detailed //! information for the bit-mapped values in \e ulIntFlags. @@ -734,7 +734,7 @@ LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel) //! \param ulBase specifies the LPC module base address. //! \param ulChannel specifies the LPC channel to disable. //! -//! The specified LPC Channel is disabled. +//! This function disables the specified LPC Channel. //! //! \sa The description of the LPCChannelEnable() function provides detailed //! information for the values that can be usd for the \e ulChannel parameter. @@ -769,7 +769,7 @@ LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel) //! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this //! channel. //! -//! The specified LPC Channel is enabled as an endpoint. +//! This function enables the specified LPC Channel as an endpoint. //! //! \return None. // @@ -821,7 +821,7 @@ LPCChannelConfigEPSet(unsigned long ulBase, unsigned long ulChannel, //! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this //! channel. //! -//! The specified LPC Channel is enabled as a mailbox. +//! This function enables the specified LPC Channel as a mailbox. //! //! \return None. // @@ -946,7 +946,8 @@ LPCChannelConfigCOMxSet(unsigned long ulBase, unsigned long ulChannel, //! \param pulAddress is a pointer to storage for the channel bus address. //! \param pulCOMxMode is a pointer to storage for the channel COMx mode. //! -//! The configuration for the specified channel is determined and returned. +//! This function determines and returns the configuration for the specified +//! channel. //! //! \return Returns the bit-mapped channel control register value. // @@ -979,8 +980,7 @@ LPCChannelConfigGet(unsigned long ulBase, unsigned long ulChannel, } // - // Get the IO/Memory address that this endpoint will respond - // to. + // Get the IO/Memory address that this endpoint responds to. // if(pulAddress) { @@ -1008,10 +1008,10 @@ LPCChannelConfigGet(unsigned long ulBase, unsigned long ulChannel, //! \param ulBase specifies the LPC module base address. //! \param ulChannel specifies the LPC channel to configure. //! -//! The absolute address of the channel pool is calculated from the channel -//! configuration setting and returned. +//! Thos function calculates the absolute address of the channel pool from the +//! channel configuration setting and returns it. //! -//! \return Returns absolute base address of the channel pool. +//! \return Returns the absolute base address of the channel pool. // //***************************************************************************** unsigned long @@ -1056,7 +1056,8 @@ LPCChannelPoolAddressGet(unsigned long ulBase, unsigned long ulChannel) //! \param ulBase specifies the LPC module base address. //! \param ulChannel specifies the LPC Channel. //! -//! Reads the status word from an LPC channel and returns it to the caller. +//! This function reads the status word from an LPC channel and returns it to +//! the caller. //! //! \return content of the channel status register. // @@ -1084,7 +1085,8 @@ LPCChannelStatusGet(unsigned long ulBase, unsigned long ulChannel) //! \param ulChannel specifies the LPC Channel. //! \param ulStatus is the user bit values to set. //! -//! Sets the selected user bits of the status word for an LPC channel. +//! This function sets the selected user bits of the status word for an LPC +//! channel. //! //! \return None // @@ -1103,7 +1105,7 @@ LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0); // - // Read thestatus from the LPC Channel, and set new values for + // Read the status from the LPC Channel, and set new values for // the user bits. // ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)); @@ -1119,7 +1121,8 @@ LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, //! \param ulChannel specifies the LPC Channel. //! \param ulStatus is the user bit values to clear. //! -//! Sets the selected user bits of the status word for an LPC channel. +//! This function sets the selected user bits of the status word for an LPC +//! channel. //! //! \return None // @@ -1138,7 +1141,7 @@ LPCChannelStatusClear(unsigned long ulBase, unsigned long ulChannel, ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0); // - // Read thestatus from the LPC Channel, and set new values for + // Read the status from the LPC Channel, and set new values for // the user bits. // ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)); @@ -1154,8 +1157,8 @@ LPCChannelStatusClear(unsigned long ulBase, unsigned long ulChannel, //! \param ulConfig specifies the DMA channel configuration. //! \param ulMask specifies the configuration mask to be used. //! -//! Sets the specified DMA channel operation based on the \e ulConfig -//! parameter. +//! This function sets the specified DMA channel operation based on the +//! \e ulConfig parameter. //! //! \return None. // @@ -1192,7 +1195,7 @@ LPCChannelDMAConfigSet(unsigned long ulBase, unsigned long ulConfig, //! //! \param ulBase specifies the LPC module base address. //! -//! Returns the configuration of the LPC DMA channels. +//! This function returns the configuration of the LPC DMA channels. //! //! \return Returns the bit-mapped DMA channel configuration. // @@ -1219,7 +1222,7 @@ LPCChannelDMAConfigGet(unsigned long ulBase) //! \param ulOffset specifies the offset from the beginning of the LPC channel //! pool. //! -//! This function may be called to read a byte from the channel pool. +//! This function reads a byte from the channel pool. //! //! \return Returns the byte read from the pool memory. // @@ -1249,7 +1252,7 @@ LPCByteRead(unsigned long ulBase, unsigned long ulOffset) //! pool. //! \param ucData specifies the byte to write. //! -//! Ths function may be called to write a byte to the channel pool. +//! This function writes a byte to the channel pool. //! //! \return None // @@ -1279,8 +1282,8 @@ LPCByteWrite(unsigned long ulBase, unsigned long ulOffset, //! \param ulOffset specifies the offset from the beginning of the LPC channel //! pool. //! -//! This function may be called to read a half-word from the channel pool. The -//! \e ulOffset specified must be half-word aligned. +//! This function reads a half-word from the channel pool. The \e ulOffset +//! specified must be half-word aligned. //! //! \return Returns the half-word read from the pool memory. // @@ -1311,8 +1314,8 @@ LPCHalfWordRead(unsigned long ulBase, unsigned long ulOffset) //! pool. //! \param usData specifies the byte to write. //! -//! Ths function may be called to write a half-word to the channel pool. The -//! \e ulOffset specified must be half-word aligned. +//! This function writes a half-word to the channel pool. The \e ulOffset +//! specified must be half-word aligned. //! //! \return None // @@ -1343,10 +1346,10 @@ LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset, //! \param ulOffset specifies the offset from the beginning of the LPC channel //! pool. //! -//! This function may be called to read a word from the channel pool. The -//! \e ulOffset specified must be word aligned. +//! This function reads a word from the channel pool. The \e ulOffset +//! specified must be word aligned. //! -//! \return Returns the half-word read from the pool memory. +//! \return Returns the word read from the pool memory. // //***************************************************************************** unsigned long @@ -1368,15 +1371,15 @@ LPCWordRead(unsigned long ulBase, unsigned long ulOffset) //***************************************************************************** // -//! Writes a byte to the LPC channel pool. +//! Writes a word to the LPC channel pool. //! //! \param ulBase specifies the LPC module base address. //! \param ulOffset specifies the offset from the beginning of the LPC channel //! pool. -//! \param ulData specifies the byte to write. +//! \param ulData specifies the word to write. //! -//! Ths function may be called to write a half-word to the channel pool. The -//! \e ulOffset specified must be half-word aligned. +//! This function writes a word to the channel pool. The \e ulOffset +//! specified must be word aligned. //! //! \return None // @@ -1406,8 +1409,8 @@ LPCWordWrite(unsigned long ulBase, unsigned long ulOffset, //! \param ulBase specifies the LPC module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated COMx interrupt sources to trigger the COMx interrupt -//! in the primary LPC interrupt registers. +//! This function enables the indicated COMx interrupt sources to trigger the +//! COMx interrupt in the primary LPC interrupt registers. //! //! \return None. // @@ -1435,8 +1438,8 @@ LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase specifies the LPC module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated COMx interrupt sources from triggering the COMx -//! interrupt in the primary LPC interrupt registers. +//! This function disables the indicated COMx interrupt sources from triggering +//! the COMx interrupt in the primary LPC interrupt registers. //! //! \return None. // @@ -1500,8 +1503,8 @@ LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase specifies the LPC module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! The specified COMx interrupt sources are cleared so that they no longer -//! assert. +//! This function clears the specified COMx interrupt sources so that they no +//! longer assert. //! //! \return None. // diff --git a/bsp/lm4f232/Libraries/driverlib/lpc.h b/bsp/lm4f232/Libraries/driverlib/lpc.h index 8fd9c96b09..ec67c6578c 100644 --- a/bsp/lm4f232/Libraries/driverlib/lpc.h +++ b/bsp/lm4f232/Libraries/driverlib/lpc.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/mpu.c b/bsp/lm4f232/Libraries/driverlib/mpu.c index 1bef83f5d9..a0bc0c404e 100644 --- a/bsp/lm4f232/Libraries/driverlib/mpu.c +++ b/bsp/lm4f232/Libraries/driverlib/mpu.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -42,13 +42,13 @@ //! //! \param ulMPUConfig is the logical OR of the possible configurations. //! -//! This function enables the Cortex-M3 memory protection unit. It also +//! This function enables the Cortex-M memory protection unit. It also //! configures the default behavior when in privileged mode and while handling //! a hard fault or NMI. Prior to enabling the MPU, at least one region must //! be set by calling MPURegionSet() or else by enabling the default region for //! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to -//! MPUEnable(). Once the MPU is enabled, a memory management fault are -//! generated for any memory access violations. +//! MPUEnable(). Once the MPU is enabled, a memory management fault is +//! generated for memory access violations. //! //! The \e ulMPUConfig parameter should be the logical OR of any of the //! following: @@ -62,8 +62,8 @@ //! disabled while in one of these exception handlers and the default //! memory map is applied. //! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, -//! no default memory map is provided in privileged mode, and the MPU will -//! not be enabled in the fault handlers. +//! no default memory map is provided in privileged mode, and the MPU isl +//! not enabled in the fault handlers. //! //! \return None. // @@ -88,7 +88,7 @@ MPUEnable(unsigned long ulMPUConfig) // //! Disables the MPU for use. //! -//! This function disables the Cortex-M3 memory protection unit. When the +//! This function disables the Cortex-M memory protection unit. When the //! MPU is disabled, the default memory map is used and memory management //! faults are not generated. //! @@ -108,9 +108,8 @@ MPUDisable(void) // //! Gets the count of regions supported by the MPU. //! -//! This function is used to get the number of regions that are supported by -//! the MPU. This is the total number that are supported, including regions -//! that are already programmed. +//! This function is used to get the total number of regions that are supported +//! by the MPU, including regions that are already programmed. //! //! \return The number of memory protection regions that are available //! for programming using MPURegionSet(). @@ -120,7 +119,7 @@ unsigned long MPURegionCountGet(void) { // - // Read the DREGION field of the MPU type register, and mask off + // Read the DREGION field of the MPU type register and mask off // the bits of interest to get the count of regions. // return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) @@ -134,9 +133,9 @@ MPURegionCountGet(void) //! \param ulRegion is the region number to enable. //! //! This function is used to enable a memory protection region. The region -//! should already be set up with the MPURegionSet() function. Once enabled, -//! the memory protection rules of the region are applied and access violations -//! will cause a memory management fault. +//! should already be configured with the MPURegionSet() function. Once +//! enabled, the memory protection rules of the region are applied and access +//! violations cause a memory management fault. //! //! \return None. // @@ -167,7 +166,7 @@ MPURegionEnable(unsigned long ulRegion) //! \param ulRegion is the region number to disable. //! //! This function is used to disable a previously enabled memory protection -//! region. The region will remain configured if it is not overwritten with +//! region. The region remains configured if it is not overwritten with //! another call to MPURegionSet(), and can be enabled again by calling //! MPURegionEnable(). //! @@ -203,16 +202,16 @@ MPURegionDisable(unsigned long ulRegion) //! \param ulFlags is a set of flags to define the attributes of the region. //! //! This function sets up the protection rules for a region. The region has -//! a base address and a set of attributes including the size, which must -//! be a power of 2. The base address parameter, \e ulAddr, must be aligned -//! according to the size. +//! a base address and a set of attributes including the size. The base +//! address parameter, \e ulAddr, must be aligned according to the size, and +//! the size must be a power of 2. //! //! The \e ulFlags parameter is the logical OR of all of the attributes //! of the region. It is a combination of choices for region size, //! execute permission, read/write permissions, disabled sub-regions, //! and a flag to determine if the region is enabled. //! -//! The size flag determines the size of a region, and must be one of the +//! The size flag determines the size of a region and must be one of the //! following: //! //! - \b MPU_RGN_SIZE_32B @@ -262,8 +261,8 @@ MPURegionDisable(unsigned long ulRegion) //! //! The region is automatically divided into 8 equally-sized sub-regions by //! the MPU. Sub-regions can only be used in regions of size 256 bytes -//! or larger. Any of these 8 sub-regions can be disabled. This allows -//! for creation of ``holes'' in a region which can be left open, or overlaid +//! or larger. Any of these 8 sub-regions can be disabled, allowing for +//! creation of ``holes'' in a region which can be left open, or overlaid //! by another region with different attributes. Any of the 8 sub-regions //! can be disabled with a logical OR of any of the following flags: //! @@ -292,7 +291,7 @@ MPURegionDisable(unsigned long ulRegion) //! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) //! //! -//! \note This function will write to multiple registers and is not protected +//! \note This function writes to multiple registers and is not protected //! from interrupts. It is possible that an interrupt which accesses a //! region may occur while that region is in the process of being changed. //! The safest way to handle this is to disable a region before changing it. @@ -382,8 +381,9 @@ MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, //! \param pfnHandler is a pointer to the function to be called when the //! memory management fault occurs. //! -//! This sets and enables the handler to be called when the MPU generates -//! a memory management fault due to a protection region access violation. +//! This function sets and enables the handler to be called when the MPU +//! generates a memory management fault due to a protection region access +//! violation. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -414,7 +414,7 @@ MPUIntRegister(void (*pfnHandler)(void)) // //! Unregisters an interrupt handler for the memory management fault. //! -//! This function will disable and clear the handler to be called when a +//! This function disables and clears the handler to be called when a //! memory management fault occurs. //! //! \sa IntRegister() for important information about registering interrupt diff --git a/bsp/lm4f232/Libraries/driverlib/mpu.h b/bsp/lm4f232/Libraries/driverlib/mpu.h index 8b8bbbca66..655228da60 100644 --- a/bsp/lm4f232/Libraries/driverlib/mpu.h +++ b/bsp/lm4f232/Libraries/driverlib/mpu.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/peci.c b/bsp/lm4f232/Libraries/driverlib/peci.c index a6d3c88b0c..e07cfc54af 100644 --- a/bsp/lm4f232/Libraries/driverlib/peci.c +++ b/bsp/lm4f232/Libraries/driverlib/peci.c @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -99,7 +99,7 @@ PECIDomainValid(unsigned long ulDomain) //! host/domain combination can be configured/enabled with a call to //! PECIDomainEnable(). //! -//! The peripheral clock is the same as the processor clock. This is the value +//! The peripheral clock is the same as the processor clock. This value is //! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtlClockGet()). @@ -185,7 +185,7 @@ PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk, //! rates being used; they may not be the same as the requested rates, due to //! rounding in the calculations. //! -//! The peripheral clock is the same as the processor clock. This is the value +//! The peripheral clock is the same as the processor clock. This value is //! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtlClockGet()). @@ -295,8 +295,8 @@ PECIBypassDisable(unsigned long ulBase) //! //! This function configures the specified PECI domain for temperature //! monitoring operations. The values for \e ulHigh and \e ulLow can be -//! specified as a value relative to the maximum temperature allowed, or it -//! can be specified as an absolute temperature (if an offset was programmed +//! specified as values relative to the maximum temperature allowed, or they +//! can be specified as absolute temperatures if an offset was programmed //! in the PECIConfigSet() function. //! //! The \e ulDomain parameter can be one of the following values: @@ -339,8 +339,8 @@ PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain, //! //! This function configures the specified PECI domain for temperature //! monitoring operations. The values for \e ulHigh and \e ulLow can be -//! specified as a value relative to the maximum temperature allowed, or it -//! can be specified as an absolute temperature (if an offset was programmed +//! specified as values relative to the maximum temperature allowed, or they +//! can be specified as absolute temperatures if an offset was programmed //! in the PECIConfigSet() function. //! //! The \e ulDomain parameter can be one of the following values: @@ -574,11 +574,11 @@ PECIDomainMaxReadClear(unsigned long ulBase, unsigned long ulDomain) //! \param pfnHandler is a pointer to the function to be called when the //! PECI interrupt occurs. //! -//! This sets the handler to be called when an PECI interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific -//! PECI interrupts must be enabled via PECIIntEnable(). If necessary, it is -//! the interrupt handler's responsibility to clear the interrupt source via -//! PECIIntClear(). +//! This function registers the handler to be called when an PECI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific PECI interrupts must be enabled via PECIIntEnable(). +//! If necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via PECIIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -612,9 +612,9 @@ PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase specifies the PECI module base address. //! -//! This function will clear the handler to be called when a PECI interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when a PECI interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -649,9 +649,9 @@ PECIIntUnregister(unsigned long ulBase) //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! \param ulIntMode is the mode for the PECI domain interrupts. //! -//! Enables the indicated PECI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function enables the indicated PECI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter can be any of the following values: //! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, @@ -692,8 +692,8 @@ PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags, // // Set/Enable the bit/bit-fields based on the value in the flags and mode - // parameter. The flags parameter will alter the bits in the lower half - // of the mask, while the mode will alter the bit fields in the upper + // parameter. The flags parameter alters the bits in the lower half + // of the mask, while the mode alters the bit fields in the upper // half of the mask. // ulTemp |= (0x0000FFFF & ulIntFlags); @@ -708,9 +708,9 @@ PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags, //! \param ulBase specifies the PECI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated PECI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function disables the indicated PECI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter can be any of the following values: //! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, @@ -785,12 +785,12 @@ PECIIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase specifies the PECI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! The specified PECI interrupt sources are cleared so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupts from being recognized again immediately upon exit. The -//! \e ulIntFlags parameter can consist of any combination of the \b PECI_READ, -//! \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, \b PECI_M1D0, or -//! \b PECI_M1D1 values. +//! This function clears the specified PECI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being recognized again immediately upon exit. +//! The \e ulIntFlags parameter can consist of any combination of the +//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, +//! \b PECI_M1D0, or \b PECI_M1D1 values. //! //! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. diff --git a/bsp/lm4f232/Libraries/driverlib/peci.h b/bsp/lm4f232/Libraries/driverlib/peci.h index c81223184c..e1b0b9016b 100644 --- a/bsp/lm4f232/Libraries/driverlib/peci.h +++ b/bsp/lm4f232/Libraries/driverlib/peci.h @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/pin_map.h b/bsp/lm4f232/Libraries/driverlib/pin_map.h index 60bf360def..51c4a2e342 100644 --- a/bsp/lm4f232/Libraries/driverlib/pin_map.h +++ b/bsp/lm4f232/Libraries/driverlib/pin_map.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/pwm.c b/bsp/lm4f232/Libraries/driverlib/pwm.c index e527200662..c6432735d1 100644 --- a/bsp/lm4f232/Libraries/driverlib/pwm.c +++ b/bsp/lm4f232/Libraries/driverlib/pwm.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -105,8 +105,8 @@ PWMOutValid(unsigned long ulPWMOut) //! Configures a PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to configure. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to configure. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulConfig is the configuration for the PWM generator. //! //! This function is used to set the mode of operation for a PWM generator. @@ -115,31 +115,31 @@ PWMOutValid(unsigned long ulPWMOut) //! state. //! //! A PWM generator can count in two different modes: count down mode or count -//! up/down mode. In count down mode, it will count from a value down to zero, -//! and then reset to the preset value. This will produce left-aligned PWM -//! signals (that is the rising edge of the two PWM signals produced by the -//! generator will occur at the same time). In count up/down mode, it will -//! count up from zero to the preset value, count back down to zero, and then -//! repeat the process. This will produce center-aligned PWM signals (that is, +//! up/down mode. In count down mode, it counts from a value down to zero, +//! and then resets to the preset value, producing left-aligned PWM +//! signals (that is, the rising edge of the two PWM signals produced by the +//! generator occur at the same time). In count up/down mode, it counts up +//! from zero to the preset value, counts back down to zero, and then repeats +//! the process, producing center-aligned PWM signals (that is, //! the middle of the high/low period of the PWM signals produced by the -//! generator will occur at the same time). +//! generator occurs at the same time). //! //! When the PWM generator parameters (period and pulse width) are modified, -//! their affect on the output PWM signals can be delayed. In synchronous +//! their effect on the output PWM signals can be delayed. In synchronous //! mode, the parameter updates are not applied until a synchronization event -//! occurs. This allows multiple parameters to be modified and take affect -//! simultaneously, instead of one at a time. Additionally, parameters to -//! multiple PWM generators in synchronous mode can be updated simultaneously, -//! allowing them to be treated as if they were a unified generator. In -//! non-synchronous mode, the parameter updates are not delayed until a -//! synchronization event. In either mode, the parameter updates only occur -//! when the counter is at zero to help prevent oddly formed PWM signals during -//! the update (that is, a PWM pulse that is too short or too long). +//! occurs. This mode allows multiple parameters to be modified and take +//! effect simultaneously, instead of one at a time. Additionally, parameters +//! to multiple PWM generators in synchronous mode can be updated +//! simultaneously, allowing them to be treated as if they were a unified +//! generator. In non-synchronous mode, the parameter updates are not delayed +//! until a synchronization event. In either mode, the parameter updates only +//! occur when the counter is at zero to help prevent oddly formed PWM signals +//! during the update (that is, a PWM pulse that is too short or too long). //! //! The PWM generator can either pause or continue running when the processor -//! is stopped via the debugger. If configured to pause, it will continue to -//! count until it reaches zero, at which point it will pause until the -//! processor is restarted. If configured to continue running, it will keep +//! is stopped via the debugger. If configured to pause, it continues to +//! count until it reaches zero, at which point it pauses until the +//! processor is restarted. If configured to continue running, it keeps //! counting as if nothing had happened. //! //! The \e ulConfig parameter contains the desired configuration. It is the @@ -165,14 +165,14 @@ PWMOutValid(unsigned long ulPWMOut) //! whether extended fault source selection support is enabled or not //! //! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the -//! minimum duration of a PWM fault signal. Faults will be signaled for at +//! minimum duration of a PWM fault signal. Faults are signaled for at //! least this time even if the external fault pin deasserts earlier. Care -//! should be taken when using this mode since during the fault signal period, -//! the fault interrupt from the PWM generator will remain asserted. The fault -//! interrupt handler may, therefore, reenter immediately if it exits prior to -//! expiration of the fault timer. +//! should be taken when using this mode because during the fault signal +//! period, the fault interrupt from the PWM generator remains asserted. The +//! fault interrupt handler may, therefore, reenter immediately if it exits +//! prior to expiration of the fault timer. //! -//! \note Changes to the counter mode will affect the period of the PWM signals +//! \note Changes to the counter mode affect the period of the PWM signals //! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after //! any changes to the counter mode of a generator. //! @@ -238,11 +238,11 @@ PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, //***************************************************************************** // -//! Set the period of a PWM generator. +//! Sets the period of a PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be modified. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to be modified. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulPeriod specifies the period of PWM generator output, measured //! in clock ticks. //! @@ -251,7 +251,7 @@ PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, //! ticks between pulses on the generator block zero signal. //! //! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. +//! cause the previous values to be overwritten. //! //! \return None. // @@ -299,7 +299,7 @@ PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, //! Gets the period of a PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of +//! \param ulGen is the PWM generator to query. This parameter must be one of //! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function gets the period of the specified PWM generator block. The @@ -352,8 +352,8 @@ PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) //! Enables the timer/counter for a PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be enabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to be enabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function allows the PWM clock to drive the timer/counter for the //! specified generator block. @@ -381,8 +381,8 @@ PWMGenEnable(unsigned long ulBase, unsigned long ulGen) //! Disables the timer/counter for a PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be disabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to be disabled. This parameter must be +//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function blocks the PWM clock from driving the timer/counter for the //! specified generator block. @@ -410,16 +410,16 @@ PWMGenDisable(unsigned long ulBase, unsigned long ulGen) //! Sets the pulse width for the specified PWM output. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5, -//! \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ulPWMOut is the PWM output to modify. This parameter must be one +//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. //! \param ulWidth specifies the width of the positive portion of the pulse. //! //! This function sets the pulse width for the specified PWM output, where the //! pulse width is defined as the number of PWM clock ticks. //! //! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. +//! cause the previous values to be overwritten. //! //! \return None. // @@ -482,9 +482,9 @@ PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, //! Gets the pulse width of a PWM output. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5, -//! \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ulPWMOut is the PWM output to query. This parameter must be one of +//! \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, +//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. //! //! This function gets the currently programmed pulse width for the specified //! PWM output. If the update of the comparator for the specified output has @@ -542,11 +542,11 @@ PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) //***************************************************************************** // -//! Enables the PWM dead band output, and sets the dead band delays. +//! Enables the PWM dead band output and sets the dead band delays. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to modify. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param usRise specifies the width of delay from the rising edge. //! \param usFall specifies the width of delay from the falling edge. //! @@ -557,7 +557,7 @@ PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) //! //! \return None. // -//***************************************************************************** +//**************************************************************************** void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, unsigned short usRise, unsigned short usFall) @@ -592,7 +592,7 @@ PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, //! Disables the PWM dead band output. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of +//! \param ulGen is the PWM generator to modify. This parameter must be one of //! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! //! This function disables the dead band mode for the specified PWM generator. @@ -622,9 +622,9 @@ PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) //! Synchronizes all pending updates. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be updated. Must be the -//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, -//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! \param ulGenBits are the PWM generator blocks to be updated. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. //! //! For the selected PWM generators, this function causes all queued updates to //! the period or pulse width to be applied the next time the corresponding @@ -654,9 +654,9 @@ PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) //! Synchronizes the counters in one or multiple PWM generator blocks. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be -//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, -//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! \param ulGenBits are the PWM generator blocks to be synchronized. This +//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, +//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. //! //! For the selected PWM module, this function synchronizes the time base //! of the generator blocks by causing the specified generator counters to be @@ -687,17 +687,17 @@ PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) //! Enables or disables PWM outputs. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, -//! or \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bEnable determines if the signal is enabled or disabled. //! -//! This function is used to enable or disable the selected PWM outputs. The +//! This function enables or disables the selected PWM outputs. The //! outputs are selected using the parameter \e ulPWMOutBits. The parameter //! \e bEnable determines the state of the selected outputs. If \e bEnable is //! \b true, then the selected PWM outputs are enabled, or placed in the active -//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! state. If \e bEnable is \b false, then the selected outputs are disabled //! or placed in the inactive state. //! //! \return None. @@ -716,7 +716,7 @@ PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's ENABLE output control register, and set or clear the + // Read the module's ENABLE output control register and set or clear the // requested bits. // if(bEnable == true) @@ -734,18 +734,18 @@ PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, //! Selects the inversion mode for PWM outputs. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or -//! \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bInvert determines if the signal is inverted or passed through. //! //! This function is used to select the inversion mode for the selected PWM //! outputs. The outputs are selected using the parameter \e ulPWMOutBits. //! The parameter \e bInvert determines the inversion mode for the selected -//! outputs. If \e bInvert is \b true, this function will cause the specified -//! PWM output signals to be inverted, or made active low. If \e bInvert is -//! \b false, the specified outputs are passed through as is, or be made active +//! outputs. If \e bInvert is \b true, this function causes the specified +//! PWM output signals to be inverted or made active low. If \e bInvert is +//! \b false, the specified outputs are passed through as is or made active //! high. //! //! \return None. @@ -764,7 +764,7 @@ PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's INVERT output control register, and set or clear the + // Read the module's INVERT output control register and set or clear the // requested bits. // if(bInvert == true) @@ -783,10 +783,10 @@ PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, //! condition. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or -//! \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bDriveHigh determines if the signal is driven high or low during an //! active fault condition. //! @@ -820,7 +820,7 @@ PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's FAULT output control register, and set or clear the + // Read the module's FAULT output control register and set or clear the // requested bits. // if(bDriveHigh == true) @@ -838,10 +838,10 @@ PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, //! Specifies the state of PWM outputs in response to a fault condition. //! //! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or -//! \b PWM_OUT_7_BIT. +//! \param ulPWMOutBits are the PWM outputs to be modified. This parameter +//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, +//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, +//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. //! \param bFaultSuppress determines if the signal is suppressed or passed //! through during an active fault condition. //! @@ -873,7 +873,7 @@ PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, PWM_OUT_6_BIT | PWM_OUT_7_BIT))); // - // Read the module's FAULT output control register, and set or clear the + // Read the module's FAULT output control register and set or clear the // requested bits. // if(bFaultSuppress == true) @@ -891,10 +891,10 @@ PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, //! Gets the PWM generator interrupt number. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! -//! This function will return the interrupt number of the corresponding PWM +//! This function returns the interrupt number of the corresponding PWM //! generator. //! //! \return Returns the interrupt number. @@ -987,14 +987,14 @@ PWMGenIntGet(unsigned long ulBase, unsigned long ulGen) //! Registers an interrupt handler for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param pfnIntHandler is a pointer to the function to be called when the PWM //! generator interrupt occurs. //! -//! This function will ensure that the interrupt handler specified by +//! This function ensures that the interrupt handler specified by //! \e pfnIntHandler is called when an interrupt is detected for the specified -//! PWM generator block. This function will also enable the corresponding +//! PWM generator block. This function also enables the corresponding //! PWM generator interrupt in the interrupt controller; individual generator //! interrupts and interrupt sources must be enabled with PWMIntEnable() and //! PWMGenIntTrigEnable(). @@ -1038,11 +1038,11 @@ PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, //! Removes an interrupt handler for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator in question. This parameter must be one +//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! -//! This function will unregister the interrupt handler for the specified -//! PWM generator block. This function will also disable the corresponding +//! This function unregisters the interrupt handler for the specified +//! PWM generator block. This function also disables the corresponding //! PWM generator interrupt in the interrupt controller; individual generator //! interrupts and interrupt sources must be disabled with PWMIntDisable() and //! PWMGenIntTrigDisable(). @@ -1086,7 +1086,7 @@ PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) //! //! \param ulBase is the base address of the PWM module. //! -//! This function will return the fault interrupt number of the corresponding +//! This function returns the fault interrupt number of the corresponding //! PWM module. //! //! \return Returns the interrupt number. @@ -1110,9 +1110,9 @@ PWMFaultIntGet(unsigned long ulBase) //! \param pfnIntHandler is a pointer to the function to be called when the PWM //! fault interrupt occurs. //! -//! This function will ensure that the interrupt handler specified by +//! This function ensures that the interrupt handler specified by //! \e pfnIntHandler is called when a fault interrupt is detected for the -//! selected PWM module. This function will also enable the PWM fault +//! selected PWM module. This function also enables the PWM fault //! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the //! module level using PWMIntEnable(). //! @@ -1154,8 +1154,8 @@ PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) //! //! \param ulBase is the base address of the PWM module. //! -//! This function will remove the interrupt handler for a PWM fault interrupt -//! from the selected PWM module. This function will also disable the PWM +//! This function removes the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function also disables the PWM //! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled //! at the module level using PWMIntDisable(). //! @@ -1197,12 +1197,13 @@ PWMFaultIntUnregister(unsigned long ulBase) //! //! \param ulBase is the base address of the PWM module. //! \param ulGen is the PWM generator to have interrupts and triggers enabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. //! \param ulIntTrig specifies the interrupts and triggers to be enabled. //! -//! Unmasks the specified interrupt(s) and trigger(s) by setting the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The \e ulIntTrig parameter is the logical OR of +//! This function unmasks the specified interrupt(s) and trigger(s) by setting +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ulIntTrig parameter is the logical OR of //! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, //! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, //! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, @@ -1238,12 +1239,13 @@ PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, //! //! \param ulBase is the base address of the PWM module. //! \param ulGen is the PWM generator to have interrupts and triggers disabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. //! \param ulIntTrig specifies the interrupts and triggers to be disabled. //! -//! Masks the specified interrupt(s) and trigger(s) by clearing the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The \e ulIntTrig parameter is the logical OR of +//! This function masks the specified interrupt(s) and trigger(s) by clearing +//! the specified bits of the interrupt/trigger enable register for the +//! specified PWM generator. The \e ulIntTrig parameter is the logical OR of //! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, //! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, //! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, @@ -1278,16 +1280,16 @@ PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, //! Gets interrupt status for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param bMasked specifies whether masked or raw interrupt status is //! returned. //! //! If \e bMasked is set as \b true, then the masked interrupt status is //! returned; otherwise, the raw interrupt status is returned. //! -//! \return Returns the contents of the interrupt status register, or the -//! contents of the raw interrupt status register, for the specified +//! \return Returns the contents of the interrupt status register or the +//! contents of the raw interrupt status register for the specified //! PWM generator. // //***************************************************************************** @@ -1324,17 +1326,17 @@ PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) //! Clears the specified interrupt(s) for the specified PWM generator block. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator to query. This parameter must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulInts specifies the interrupts to be cleared. //! -//! Clears the specified interrupt(s) by writing a 1 to the specified bits -//! of the interrupt status register for the specified PWM generator. The -//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO, -//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD, -//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. +//! This funciton clears the specified interrupt(s) by writing a 1 to the +//! specified bits of the interrupt status register for the specified PWM +//! generator. The \e ulInts parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1370,13 +1372,13 @@ PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) //! Enables generator and fault interrupts for a PWM module. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be enabled. Must be a logical -//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, -//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, -//! or \b PWM_INT_FAULT3. +//! \param ulGenFault contains the interrupts to be enabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! -//! Unmasks the specified interrupt(s) by setting the specified bits of -//! the interrupt enable register for the selected PWM module. +//! This function unmasks the specified interrupt(s) by setting the specified +//! bits of the interrupt enable register for the selected PWM module. //! //! \return None. // @@ -1393,7 +1395,7 @@ PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); // - // Read the module's interrupt enable register, and enable interrupts + // Read the module's interrupt enable register and enable interrupts // for the specified PWM generators. // HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; @@ -1404,13 +1406,13 @@ PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) //! Disables generator and fault interrupts for a PWM module. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be disabled. Must be a -//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, -//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, -//! or \b PWM_INT_FAULT3. +//! \param ulGenFault contains the interrupts to be disabled. This parameter +//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, +//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! -//! Masks the specified interrupt(s) by clearing the specified bits of -//! the interrupt enable register for the selected PWM module. +//! This function masks the specified interrupt(s) by clearing the specified +//! bits of the interrupt enable register for the selected PWM module. //! //! \return None. // @@ -1427,7 +1429,7 @@ PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); // - // Read the module's interrupt enable register, and disable interrupts + // Read the module's interrupt enable register and disable interrupts // for the specified PWM generators. // HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); @@ -1439,15 +1441,15 @@ PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) //! //! \param ulBase is the base address of the PWM module. //! -//! Clears the fault interrupt by writing to the appropriate bit of the -//! interrupt status register for the selected PWM module. +//! This function clears the fault interrupt by writing to the appropriate bit +//! of the interrupt status register for the selected PWM module. //! //! This function clears only the FAULT0 interrupt and is retained for //! backwards compatibility. It is recommended that PWMFaultIntClearExt() be -//! used instead since it supports all fault interrupts supported on devices +//! used instead because it supports all fault interrupts supported on devices //! with and without extended PWM fault handling support. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1518,10 +1520,10 @@ PWMIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase is the base address of the PWM module. //! \param ulFaultInts specifies the fault interrupts to clear. //! -//! Clears one or more fault interrupts by writing to the appropriate bit of -//! the PWM interrupt status register. The parameter \e ulFaultInts must be -//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, -//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! This function clears one or more fault interrupts by writing to the +//! appropriate bit of the PWM interrupt status register. The parameter +//! \e ulFaultInts must be the logical OR of any of \b PWM_INT_FAULT0, +//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. //! //! When running on a device supporting extended PWM fault handling, the fault //! interrupts are derived by performing a logical OR of each of the configured @@ -1531,7 +1533,7 @@ PWMIntStatus(unsigned long ulBase, tBoolean bMasked) //! generators. On a device without extended PWM fault handling, the interrupt //! is directly related to the state of the single FAULT pin. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1565,17 +1567,18 @@ PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts) //! PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault configuration is being set. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault configuration is being +//! set. This function must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, +//! or \b PWM_GEN_3. //! \param ulMinFaultPeriod is the minimum fault active period expressed in //! PWM clock cycles. //! \param ulFaultSenses indicates which sense of each FAULT input should be //! considered the ``asserted'' state. Valid values are logical OR //! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. //! -//! This function sets the minimum fault period for a given generator along -//! with the sense of each of the 4 possible fault inputs. The minimum fault -//! period is expressed in PWM clock cycles and takes effect only if +//! This function configures the minimum fault period for a given generator +//! along with the sense of each of the 4 possible fault inputs. The minimum +//! fault period is expressed in PWM clock cycles and takes effect only if //! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the //! \e ulConfig parameter. When a fault input is asserted, the minimum fault //! period timer ensures that it remains asserted for at least the number of @@ -1620,10 +1623,12 @@ PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, //! Configures the set of fault triggers for a given PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault triggers are being set. Must -//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault triggers are being set. +//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. //! \param ulGroup indicates the subset of possible faults that are to be -//! configured. This must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! configured. This parameter must be \b PWM_FAULT_GROUP_0 or +//! \b PWM_FAULT_GROUP_1. //! \param ulFaultTriggers defines the set of inputs that are to contribute //! towards generation of the fault signal to the given PWM generator. For //! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0, @@ -1641,9 +1646,9 @@ PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, //! must be called to configure the fault triggers. //! //! The fault signal to the PWM generator is generated by ORing together each -//! of the signals whose inputs are specified in the \e ulFaultTriggers -//! parameter after having adjusted the sense of each FAULTn input based on the -//! configuration previously set using a call to PWMGenFaultConfigure(). +//! of the signals specified in the \e ulFaultTriggers parameter after having +//! adjusted the sense of each FAULTn input based on the configuration +//! previously set using a call to PWMGenFaultConfigure(). //! //! \note This function is only available on devices supporting extended PWM //! fault handling. @@ -1691,15 +1696,15 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, //! generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault triggers are being queried. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault triggers are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulGroup indicates the subset of faults that are being queried. This -//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. //! //! This function allows an application to query the current set of inputs that -//! contribute towards the generation of a fault condition to a given PWM -//! generator. -//! +//! contribute to the generation of a fault condition to a given PWM generator. +//! //! \note This function is only available on devices supporting extended PWM //! fault handling. //! @@ -1741,17 +1746,17 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen, //! Returns the current state of the fault triggers for a given PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault trigger states are being -//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or -//! \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault trigger states are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulGroup indicates the subset of faults that are being queried. This -//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. //! //! This function allows an application to query the current state of each of //! the fault trigger inputs to a given PWM generator. The current state of //! each fault trigger input is returned unless PWMGenConfigure() has //! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the -//! \e ulConfig parameter in which case the returned status is the latched +//! \e ulConfig parameter, in which case the returned status is the latched //! fault trigger status. //! //! If latched faults are configured, the application must call @@ -1799,17 +1804,18 @@ PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen, //! Clears one or more latched fault triggers for a given PWM generator. //! //! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator whose fault trigger states are being -//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or -//! \b PWM_GEN_3. +//! \param ulGen is the PWM generator for which fault trigger states are being +//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, +//! \b PWM_GEN_2, or \b PWM_GEN_3. //! \param ulGroup indicates the subset of faults that are being queried. This -//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. +//! parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. //! \param ulFaultTriggers is the set of fault triggers which are to be //! cleared. //! //! This function allows an application to clear the fault triggers for a given -//! PWM generator. This is only required if PWMGenConfigure() has previously -//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig. +//! PWM generator. This function is only required if PWMGenConfigure() has +//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter +//! \e ulConfig. //! //! \note This function is only available on devices supporting extended PWM //! fault handling. diff --git a/bsp/lm4f232/Libraries/driverlib/pwm.h b/bsp/lm4f232/Libraries/driverlib/pwm.h index e45af7d377..520adbc072 100644 --- a/bsp/lm4f232/Libraries/driverlib/pwm.h +++ b/bsp/lm4f232/Libraries/driverlib/pwm.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/qei.c b/bsp/lm4f232/Libraries/driverlib/qei.c index a24780f576..4c701a88a9 100644 --- a/bsp/lm4f232/Libraries/driverlib/qei.c +++ b/bsp/lm4f232/Libraries/driverlib/qei.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -43,8 +43,8 @@ //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will enable operation of the quadrature encoder module. It must be -//! configured before it is enabled. +//! This function enables operation of the quadrature encoder module. The +//! module must be configured before it is enabled. //! //! \sa QEIConfigure() //! @@ -71,7 +71,7 @@ QEIEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will disable operation of the quadrature encoder module. +//! This function disables operation of the quadrature encoder module. //! //! \return None. // @@ -99,22 +99,22 @@ QEIDisable(unsigned long ulBase) //! for a description of this parameter. //! \param ulMaxPosition specifies the maximum position value. //! -//! This will configure the operation of the quadrature encoder. The +//! This function configures the operation of the quadrature encoder. The //! \e ulConfig parameter provides the configuration of the encoder and is the //! logical OR of several values: //! -//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges //! on channel A or on both channels A and B should be counted by the //! position integrator and velocity accumulator. -//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the //! position integrator should be reset when the index pulse is detected. -//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if //! quadrature signals are being provided on ChA and ChB, or if a direction //! signal and a clock are being provided instead. //! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals //! provided on ChA and ChB should be swapped before being processed. //! -//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! \e ulMaxPosition is the maximum value of the position integrator and is //! the value used to reset the position capture when in index reset mode and //! moving in the reverse (negative) direction. //! @@ -150,11 +150,11 @@ QEIConfigure(unsigned long ulBase, unsigned long ulConfig, //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the current position of the encoder. Depending upon the -//! configuration of the encoder, and the incident of an index pulse, this +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this //! value may or may not contain the expected data (that is, if in reset on //! index mode, if an index pulse has not been encountered, the position -//! counter will not be aligned with the index pulse yet). +//! counter is not yet aligned with the index pulse). //! //! \return The current position of the encoder. // @@ -180,8 +180,8 @@ QEIPositionGet(unsigned long ulBase) //! \param ulBase is the base address of the quadrature encoder module. //! \param ulPosition is the new position for the encoder. //! -//! This sets the current position of the encoder; the encoder position will -//! then be measured relative to this value. +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. //! //! \return None. // @@ -206,9 +206,10 @@ QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the current direction of rotation. In this case, current -//! means the most recently detected direction of the encoder; it may not be -//! presently moving but this is the direction it last moved before it stopped. +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. //! //! \return Returns 1 if moving in the forward direction or -1 if moving in the //! reverse direction. @@ -234,9 +235,9 @@ QEIDirectionGet(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the error indicator for the quadrature encoder. It is an -//! error for both of the signals of the quadrature input to change at the same -//! time. +//! This function returns the error indicator for the quadrature encoder. It +//! is an error for both of the signals of the quadrature input to change at +//! the same time. //! //! \return Returns \b true if an error has occurred and \b false otherwise. // @@ -261,9 +262,9 @@ QEIErrorGet(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will enable operation of the velocity capture in the quadrature -//! encoder module. It must be configured before it is enabled. Velocity -//! capture will not occur if the quadrature encoder is not enabled. +//! This function enables operation of the velocity capture in the quadrature +//! encoder module. The module must be configured before velocity capture is +//! enabled. //! //! \sa QEIVelocityConfigure() and QEIEnable() //! @@ -290,7 +291,7 @@ QEIVelocityEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This will disable operation of the velocity capture in the quadrature +//! This function disables operation of the velocity capture in the quadrature //! encoder module. //! //! \return None. @@ -322,8 +323,8 @@ QEIVelocityDisable(unsigned long ulBase) //! \param ulPeriod specifies the number of clock ticks over which to measure //! the velocity; must be non-zero. //! -//! This will configure the operation of the velocity capture portion of the -//! quadrature encoder. The position increment signal is predivided as +//! This function configures the operation of the velocity capture portion of +//! the quadrature encoder. The position increment signal is predivided as //! specified by \e ulPreDiv before being accumulated by the velocity capture. //! The divided signal is accumulated over \e ulPeriod system clock before //! being saved and resetting the accumulator. @@ -360,10 +361,10 @@ QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This returns the current speed of the encoder. The value returned is the -//! number of pulses detected in the specified time period; this number can be -//! multiplied by the number of time periods per second and divided by the -//! number of pulses per revolution to obtain the number of revolutions per +//! This function returns the current speed of the encoder. The value returned +//! is the number of pulses detected in the specified time period; this number +//! can be multiplied by the number of time periods per second and divided by +//! the number of pulses per revolution to obtain the number of revolutions per //! second. //! //! \return Returns the number of pulses captured in the given time period. @@ -391,11 +392,11 @@ QEIVelocityGet(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! quadrature encoder interrupt occurs. //! -//! This sets the handler to be called when a quadrature encoder interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via QEIIntClear(). +//! This function registers the handler to be called when a quadrature encoder +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific quadrature encoder interrupts must be +//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via QEIIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -435,9 +436,9 @@ QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase is the base address of the quadrature encoder module. //! -//! This function will clear the handler to be called when a quadrature encoder -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when a quadrature +//! encoder interrupt occurs. This function also masks off the interrupt in +//! the interrupt controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -480,9 +481,9 @@ QEIIntUnregister(unsigned long ulBase) //! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or //! \b QEI_INTINDEX values. //! -//! Enables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. +//! This function enables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -507,12 +508,12 @@ QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! //! \param ulBase is the base address of the quadrature encoder module. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or -//! \b QEI_INTINDEX values. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. //! -//! Disables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. +//! This function disables the indicated quadrature encoder interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. //! //! \return None. // @@ -539,9 +540,9 @@ QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the quadrature encoder module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. +//! This function returns the interrupt status for the quadrature encoder +//! module. Either the raw interrupt status or the status of interrupts that +//! are allowed to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. @@ -575,14 +576,15 @@ QEIIntStatus(unsigned long ulBase, tBoolean bMasked) //! //! \param ulBase is the base address of the quadrature encoder module. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or -//! \b QEI_INTINDEX values. +//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, +//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. //! //! The specified quadrature encoder interrupt sources are cleared, so that -//! they no longer assert. This must be done in the interrupt handler to keep -//! it from being called again immediately upon exit. +//! they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being triggered again immediately upon +//! exit. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid diff --git a/bsp/lm4f232/Libraries/driverlib/qei.h b/bsp/lm4f232/Libraries/driverlib/qei.h index 78a6c02d67..30c0858a51 100644 --- a/bsp/lm4f232/Libraries/driverlib/qei.h +++ b/bsp/lm4f232/Libraries/driverlib/qei.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/readme.txt b/bsp/lm4f232/Libraries/driverlib/readme.txt index ac63debee5..7c6f97ea54 100644 --- a/bsp/lm4f232/Libraries/driverlib/readme.txt +++ b/bsp/lm4f232/Libraries/driverlib/readme.txt @@ -18,4 +18,4 @@ A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -This is part of revision 8049 of the Stellaris Peripheral Driver Library. +This is part of revision 8264 of the Stellaris Peripheral Driver Library. diff --git a/bsp/lm4f232/Libraries/driverlib/rom.h b/bsp/lm4f232/Libraries/driverlib/rom.h index d5ba474130..0f1a029eef 100644 --- a/bsp/lm4f232/Libraries/driverlib/rom.h +++ b/bsp/lm4f232/Libraries/driverlib/rom.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/rom_map.h b/bsp/lm4f232/Libraries/driverlib/rom_map.h index 8d729a681e..f2c88ec67f 100644 --- a/bsp/lm4f232/Libraries/driverlib/rom_map.h +++ b/bsp/lm4f232/Libraries/driverlib/rom_map.h @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/ssi.c b/bsp/lm4f232/Libraries/driverlib/ssi.c index ec650b5e88..d46b29b474 100644 --- a/bsp/lm4f232/Libraries/driverlib/ssi.c +++ b/bsp/lm4f232/Libraries/driverlib/ssi.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -53,7 +53,7 @@ static const unsigned long g_ppulSSIIntMap[][2] = //***************************************************************************** // //! \internal -//! Checks a SSI base address. +//! Checks an SSI base address. //! //! \param ulBase specifies the SSI module base address. //! @@ -81,7 +81,7 @@ SSIBaseValid(unsigned long ulBase) //! //! Given a SSI base address, returns the corresponding interrupt number. //! -//! \return Returns a SSI interrupt number, or -1 if \e ulBase is invalid. +//! \return Returns an SSI interrupt number, or -1 if \e ulBase is invalid. // //***************************************************************************** static long @@ -132,7 +132,7 @@ SSIIntNumberGet(unsigned long ulBase) //! \e ulProtocol parameter can be one of the following values: //! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, //! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola -//! frame formats imply the following polarity and phase configurations: +//! frame formats encode the following polarity and phase configurations: //! //! 
 //! Polarity Phase       Mode
@@ -143,23 +143,24 @@ SSIIntNumberGet(unsigned long ulBase)
 //!
//! //! The \e ulMode parameter defines the operating mode of the SSI module. The -//! SSI module can operate as a master or slave; if a slave, the SSI can be -//! configured to disable output on its serial output line. The \e ulMode +//! SSI module can operate as a master or slave; if it is a slave, the SSI can +//! be configured to disable output on its serial output line. The \e ulMode //! parameter can be one of the following values: \b SSI_MODE_MASTER, //! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. //! //! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate //! must satisfy the following clock ratio criteria: //! -//! - FSSI >= 2 * bit rate (master mode) -//! - FSSI >= 12 * bit rate (slave modes) +//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz. +//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the +//! capability of the specific microcontroller //! //! where FSSI is the frequency of the clock supplied to the SSI module. //! -//! The \e ulDataWidth parameter defines the width of the data transfers, and +//! The \e ulDataWidth parameter defines the width of the data transfers and //! can be a value between 4 and 16, inclusive. //! -//! The peripheral clock is the same as the processor clock. This is the value +//! The peripheral clock is the same as the processor clock. This value is //! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtlClockGet()). @@ -288,11 +289,11 @@ SSIDisable(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the //! synchronous serial interface interrupt occurs. //! -//! This sets the handler to be called when an SSI interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, -//! it is the interrupt handler's responsibility to clear the interrupt source -//! via SSIIntClear(). +//! This function registers the handler to be called when an SSI interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If +//! necessary, it is the interrupt handler's responsibility to clear the +//! interrupt source via SSIIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -332,8 +333,8 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! //! \param ulBase specifies the SSI module base address. //! -//! This function will clear the handler to be called when a SSI -//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! This function clears the handler to be called when an SSI interrupt +//! occurs. This function also masks off the interrupt in the interrupt //! controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt @@ -375,10 +376,11 @@ SSIIntUnregister(unsigned long ulBase) //! \param ulBase specifies the SSI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated SSI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. The \e ulIntFlags parameter can be any of the -//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values. +//! This function enables the indicated SSI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. The \e ulIntFlags +//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or +//! \b SSI_RXOR values. //! //! \return None. // @@ -404,9 +406,9 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase specifies the SSI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter -//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR -//! values. +//! This function disables the indicated SSI interrupt sources. The +//! \e ulIntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, +//! \b SSI_RXTO, or \b SSI_RXOR values. //! //! \return None. // @@ -470,13 +472,13 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked) //! \param ulBase specifies the SSI module base address. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! The specified SSI interrupt sources are cleared so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupts from being recognized again immediately upon exit. The +//! This function clears the specified SSI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The //! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and //! \b SSI_RXOR values. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -687,7 +689,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) //! \param ulBase is the base address of the SSI port. //! \param ulDMAFlags is a bit mask of the DMA features to enable. //! -//! The specified SSI DMA features are enabled. The SSI can be +//! This function enables the specified SSI DMA features. The SSI can be //! configured to use DMA for transmit and/or receive data transfers. //! The \e ulDMAFlags parameter is the logical OR of any of the following //! values: @@ -752,10 +754,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) //! //! \param ulBase is the base address of the SSI port. //! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \b false is returned, then the transmit FIFO -//! is empty and all bits of the last transmitted word have left the hardware -//! shift register. +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. //! //! \return Returns \b true if the SSI is transmitting or \b false if all //! transmissions are complete. @@ -786,7 +788,7 @@ SSIBusy(unsigned long ulBase) //! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or //! the precision internal oscillator (\b SSI_CLOCK_PIOSC). //! -//! Changing the baud clock source will change the data rate generated by the +//! Changing the baud clock source changes the data rate generated by the //! SSI. Therefore, the data rate should be reconfigured after any change to //! the SSI clock source. //! diff --git a/bsp/lm4f232/Libraries/driverlib/ssi.h b/bsp/lm4f232/Libraries/driverlib/ssi.h index ac4f3aef3f..b0cfd1ec5b 100644 --- a/bsp/lm4f232/Libraries/driverlib/ssi.h +++ b/bsp/lm4f232/Libraries/driverlib/ssi.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/sysctl.c b/bsp/lm4f232/Libraries/driverlib/sysctl.c index 9da020b674..43755758e4 100644 --- a/bsp/lm4f232/Libraries/driverlib/sysctl.c +++ b/bsp/lm4f232/Libraries/driverlib/sysctl.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -268,7 +268,7 @@ SysCtlPeripheralValid(unsigned long ulPeripheral) //***************************************************************************** // // A map of old peripheral defines to new peripheral defines. Note that the -// new peripheral defines will not work on old parts. +// new peripheral defines will not work on parts that precede Blizzard class. // //***************************************************************************** static const unsigned long g_ppulPeripheralMap[][2] = @@ -389,10 +389,10 @@ SysCtlFlashSizeGet(void) //! //! \param ulPin is the pin in question. //! -//! Determines if a particular pin is present in the device. The PWM, analog -//! comparators, ADC, and timers have a varying number of pins across members -//! of the Stellaris family; this will determine which are present on this -//! device. +//! This function determines if a particular pin is present in the device. The +//! PWM, analog comparators, ADC, and timers have a varying number of pins +//! across members of the Stellaris family; this function determines which pins +//! are present on this device. //! //! The \e ulPin argument must be only one of the following values: //! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, @@ -468,9 +468,9 @@ SysCtlPinPresent(unsigned long ulPin) //! //! \param ulPeripheral is the peripheral in question. //! -//! Determines if a particular peripheral is present in the device. Each -//! member of the Stellaris family has a different peripheral set; this will -//! determine which are present on this device. +//! This function determines if a particular peripheral is present in the +//! device. Each member of the Stellaris family has a different peripheral +//! set; this function determines which peripherals are present on this device. //! //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, @@ -526,7 +526,7 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral) else if(ulPeripheral == SYSCTL_PERIPH_USB0) { // - // USB is a special case since the DC bit is missing for USB0. + // USB is a special case because the DC bit is missing for USB0. // if(HWREG(SYSCTL_DC6) & SYSCTL_DC6_USB0_M) { @@ -554,10 +554,10 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral) //! //! \param ulPeripheral is the peripheral in question. //! -//! Determines if a particular peripheral is ready to be accessed. The -//! peripheral may be in a non-ready state if it is not enabled, is being held -//! in reset, or is in the process of becoming ready after be enabled or taken -//! out of reset. +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. //! //! The \e ulPeripheral paramter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, @@ -586,7 +586,7 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral) //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \note The ability to check for a peripheral being ready varies based on the -//! Stellaris part in use. Please consult the datasheet for the part you are +//! Stellaris part in use. Please consult the data sheet for the part you are //! using to determine if this feature is available. //! //! \return Returns \b true if the specified peripheral is ready and \b false @@ -620,8 +620,8 @@ SysCtlPeripheralReady(unsigned long ulPeripheral) //! //! \param ulPeripheral is the peripheral to be powered on. //! -//! This function turns on the power to a peripheral. It will continue to -//! receive power even when its clock is not enabled. +//! This function turns on the power to a peripheral. The peripheral continues +//! to receive power even when its clock is not enabled. //! //! The \e ulPeripheral paramter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, @@ -650,7 +650,7 @@ SysCtlPeripheralReady(unsigned long ulPeripheral) //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \note The ability to power off a peripheral varies based on the Stellaris -//! part in use. Please consult the datasheet for the part you are using to +//! part in use. Please consult the data sheet for the part you are using to //! determine if this feature is available. //! //! \return None. @@ -684,8 +684,8 @@ SysCtlPeripheralPowerOn(unsigned long ulPeripheral) //! \param ulPeripheral is the peripheral to be powered off. //! //! This function allows the power to a peripheral to be turned off. The -//! peripheral will continue to receive power when its clock is enabled, but -//! the power will be removed when its clock is disabled. +//! peripheral continues to receive power when its clock is enabled, but +//! the power is removed when its clock is disabled. //! //! The \e ulPeripheral paramter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, @@ -714,7 +714,7 @@ SysCtlPeripheralPowerOn(unsigned long ulPeripheral) //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5. //! //! \note The ability to power off a peripheral varies based on the Stellaris -//! part in use. Please consult the datasheet for the part you are using to +//! part in use. Please consult the data sheet for the part you are using to //! determine if this feature is available. //! //! \return None. @@ -793,7 +793,7 @@ SysCtlPeripheralReset(unsigned long ulPeripheral) // // See if the peripheral index is 15, indicating a peripheral that is - // accessed via the SSYCTL_SRperiph registers. + // accessed via the SYSCTL_SRperiph registers. // if((ulPeripheral & 0xf0000000) == 0xf0000000) { @@ -845,7 +845,7 @@ SysCtlPeripheralReset(unsigned long ulPeripheral) //! //! \param ulPeripheral is the peripheral to enable. //! -//! Peripherals are enabled with this function. At power-up, all peripherals +//! This function enables peripherals. At power-up, all peripherals //! are disabled; they must be enabled in order to operate or respond to //! register reads/writes. //! @@ -877,7 +877,7 @@ SysCtlPeripheralReset(unsigned long ulPeripheral) //! //! \note It takes five clock cycles after the write to enable a peripheral //! before the the peripheral is actually enabled. During this time, attempts -//! to access the peripheral will result in a bus fault. Care should be taken +//! to access the peripheral result in a bus fault. Care should be taken //! to ensure that the peripheral is not accessed during this brief time //! period. //! @@ -920,8 +920,8 @@ SysCtlPeripheralEnable(unsigned long ulPeripheral) //! //! \param ulPeripheral is the peripheral to disable. //! -//! Peripherals are disabled with this function. Once disabled, they will not -//! operate or respond to register reads/writes. +//! This function disables peripherals are disabled with this function. Once +//! disabled, they do not operate or respond to register reads/writes. //! //! The \e ulPeripheral parameter must be only one of the following values: //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, @@ -989,9 +989,9 @@ SysCtlPeripheralDisable(unsigned long ulPeripheral) //! \param ulPeripheral is the peripheral to enable in sleep mode. //! //! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Since the clocking configuration of the device does -//! not change, any peripheral can safely continue operating while the -//! processor is in sleep mode, and can therefore wake the processor from sleep +//! goes into sleep mode. Because the clocking configuration of the device +//! does not change, any peripheral can safely continue operating while the +//! processor is in sleep mode and can therefore wake the processor from sleep //! mode. //! //! Sleep mode clocking of peripherals must be enabled via @@ -1066,7 +1066,7 @@ SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) //! This function causes a peripheral to stop operating when the processor goes //! into sleep mode. Disabling peripherals while in sleep mode helps to lower //! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), -//! the peripheral will automatically resume operation when the processor +//! the peripheral automatically resumes operation when the processor //! leaves sleep mode, maintaining its entire state from before sleep mode was //! entered. //! @@ -1140,11 +1140,11 @@ SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) //! \param ulPeripheral is the peripheral to enable in deep-sleep mode. //! //! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Since the clocking configuration of the device -//! may change, not all peripherals can safely continue operating while the -//! processor is in sleep mode. Those that must run at a particular frequency -//! (such as a UART) will not work as expected if the clock changes. It is the -//! responsibility of the caller to make sensible choices. +//! goes into deep-sleep mode. Because the clocking configuration of the +//! device may change, not all peripherals can safely continue operating while +//! the processor is in sleep mode. Those that must run at a particular +//! frequency (such as a UART) do not work as expected if the clock changes. +//! It is the responsibility of the caller to make sensible choices. //! //! Deep-sleep mode clocking of peripherals must be enabled via //! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode @@ -1221,7 +1221,7 @@ SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) //! to lower the current draw of the device, and can keep peripherals that //! require a particular clock frequency from operating when the clock changes //! as a result of entering deep-sleep mode. If enabled (via -//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! SysCtlPeripheralEnable()), the peripheral automatically resumes //! operation when the processor leaves deep-sleep mode, maintaining its entire //! state from before deep-sleep mode was entered. //! @@ -1298,10 +1298,10 @@ SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) //! //! This function controls how peripherals are clocked when the processor goes //! into sleep or deep-sleep mode. By default, the peripherals are clocked the -//! same as in run mode; if peripheral clock gating is enabled they are clocked -//! according to the configuration set by SysCtlPeripheralSleepEnable(), -//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and -//! SysCtlPeripheralDeepSleepDisable(). +//! same as in run mode; if peripheral clock gating is enabled, they are +//! clocked according to the configuration set by +//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), +//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable(). //! //! \return None. // @@ -1329,20 +1329,24 @@ SysCtlPeripheralClockGating(tBoolean bEnable) //! \param pfnHandler is a pointer to the function to be called when the system //! control interrupt occurs. //! -//! This sets the handler to be called when a system control interrupt occurs. -//! This will enable the global interrupt in the interrupt controller; specific -//! system control interrupts must be enabled via SysCtlIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! SysCtlIntClear(). +//! This function registers the handler to be called when a system control +//! interrupt occurs. This function enables the global interrupt in the +//! interrupt controller; specific system control interrupts must be enabled +//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to +//! clear the interrupt source via SysCtlIntClear(). //! //! System control can generate interrupts when the PLL achieves lock, if the //! internal LDO current limit is exceeded, if the internal oscillator fails, //! if the main oscillator fails, if the internal LDO output voltage droops too -//! much, if the external voltage droops too much, or if the PLL fails. +//! much, if the external voltage droops too much, or if the PLL fails. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. //! +//! \note The events that cause system control interrupts vary based on the +//! Stellaris part in use. Please consult the data sheet for the part you are +//! using to determine which interrupt sources are available. +//! //! \return None. // //***************************************************************************** @@ -1364,9 +1368,9 @@ SysCtlIntRegister(void (*pfnHandler)(void)) // //! Unregisters the interrupt handler for the system control interrupt. //! -//! This function will clear the handler to be called when a system control -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. +//! This function unregisters the handler to be called when a system control +//! interrupt occurs. This function also masks off the interrupt in the +//! interrupt controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1397,9 +1401,13 @@ SysCtlIntUnregister(void) //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. //! -//! Enables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. +//! This function enables the indicated system control interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. //! //! \return None. // @@ -1422,9 +1430,13 @@ SysCtlIntEnable(unsigned long ulInts) //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. //! -//! Disables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. +//! This function disables the indicated system control interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. //! //! \return None. // @@ -1448,10 +1460,10 @@ SysCtlIntDisable(unsigned long ulInts) //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. //! //! The specified system control interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. +//! longer assert. This function must be called in the interrupt handler to +//! keep it from being called again immediately upon exit. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1460,6 +1472,10 @@ SysCtlIntDisable(unsigned long ulInts) //! being immediately reentered (because the interrupt controller still sees //! the interrupt source asserted). //! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. +//! //! \return None. // //***************************************************************************** @@ -1479,14 +1495,18 @@ SysCtlIntClear(unsigned long ulInts) //! \param bMasked is false if the raw interrupt status is required and true if //! the masked interrupt status is required. //! -//! This returns the interrupt status for the system controller. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the system controller. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. //! //! \return The current interrupt status, enumerated as a bit field of //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, //! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and //! \b SYSCTL_INT_PLL_FAIL. +//! +//! \note The interrupt sources vary based on the Stellaris part in use. +//! Please consult the data sheet for the part you are using to determine +//! which interrupt sources are available. // //***************************************************************************** unsigned long @@ -1606,10 +1626,10 @@ SysCtlLDOConfigSet(unsigned long ulConfig) // //! Resets the device. //! -//! This function will perform a software reset of the entire device. The -//! processor and all peripherals are reset and all device registers will -//! return to their default values (with the exception of the reset cause -//! register, which will maintain its current value but have the software reset +//! This function performs a software reset of the entire device. The +//! processor and all peripherals are reset and all device registers are +//! returned to their default values (with the exception of the reset cause +//! register, which maintains its current value but has the software reset //! bit set as well). //! //! \return This function does not return. @@ -1619,8 +1639,8 @@ void SysCtlReset(void) { // - // Perform a software reset request. This will cause the device to reset, - // no further code is executed. + // Perform a software reset request. This request causes the device to + // reset, no further code is executed. // HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; @@ -1637,7 +1657,7 @@ SysCtlReset(void) // //! Puts the processor into sleep mode. //! -//! This function places the processor into sleep mode; it will not return +//! This function places the processor into sleep mode; it does not return //! until the processor returns to run mode. The peripherals that are enabled //! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the //! processor (if automatic clock gating is enabled with @@ -1660,7 +1680,7 @@ SysCtlSleep(void) // //! Puts the processor into deep-sleep mode. //! -//! This function places the processor into deep-sleep mode; it will not return +//! This function places the processor into deep-sleep mode; it does not return //! until the processor returns to run mode. The peripherals that are enabled //! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up //! the processor (if automatic clock gating is enabled with @@ -1693,8 +1713,9 @@ SysCtlDeepSleep(void) // //! Gets the reason for a reset. //! -//! This function will return the reason(s) for a reset. Since the reset -//! reasons are sticky until either cleared by software or an external reset, +//! This function returns the reason(s) for a reset. Because the reset +//! reasons are sticky until either cleared by software or an external reset +//! (for Sandstorm-class devices) or a power-on reset (for all other classes), //! multiple reset reasons may be returned if multiple resets have occurred. //! The reset reason is a logical OR of \b SYSCTL_CAUSE_LDO, //! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, @@ -1755,6 +1776,10 @@ SysCtlResetCauseClear(unsigned long ulCauses) //! When it detects a brown-out condition, it can either reset the device or //! generate a processor interrupt. //! +//! \note The availability of the resample feature is only available on +//! Sandstorm-class devices. Please consult the datasheet for the part you +//! are using to determine whether this feature is available. +//! //! \return None. // //***************************************************************************** @@ -1848,11 +1873,9 @@ SysCtlDelay(unsigned long ulCount) //! the OSC0/OSC1 pins, allowing power consumption to be reduced. //! //! \note The availability of MOSC control varies based on the Stellaris part -//! in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. -//! -//! \note The capability of MOSC control varies based on the Stellaris part in -//! use. +//! in use. Please consult the data sheet for the part you are using to +//! determine whether this support is available. In addition, the capability +//! of MOSC control varies based on the Stellaris part in use. //! //! \return None. // @@ -1877,9 +1900,9 @@ SysCtlMOSCConfigSet(unsigned long ulConfig) //! \e ulType is one of: //! //! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the -//! 32 kHz clock from the hibernate module as a reference. This is only -//! possible on parts that have a hibernate module and then only if it is -//! enabled and the hibernate module's RTC is also enabled. +//! 32-kHz clock from the hibernate module as a reference. This type is +//! only possible on parts that have a hibernate module, and then only if +//! it is enabled and the hibernate module's RTC is also enabled. //! //! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory //! provided calibration. @@ -1887,8 +1910,8 @@ SysCtlMOSCConfigSet(unsigned long ulConfig) //! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied //! value. The value to be used is ORed into the lower 7-bits of this value, //! with 0x40 being the ``nominal'' value (in other words, if everything were -//! perfect, this would provide exactly 16 MHz). Values larger than 0x40 -//! will slow down PIOSC, and values smaller than 0x40 will speed up PIOSC. +//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 +//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC. //! //! \return None. // @@ -1954,7 +1977,9 @@ SysCtlPIOSCCalibrate(unsigned long ulType) //! The system clock divider is chosen with one of the following values: //! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... //! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16 -//! are valid on Sandstorm-class devices. +//! are valid on Sandstorm-class devices. Half-dividers, such as +//! \b SYSCTL_SYSDIV_2_5 and \b SYSCTL_SYSDIV_3_5. are available on Tempest-, +//! Firestorm-, and Blizzard-class devices. //! //! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or //! \b SYSCTL_USE_OSC. @@ -1967,10 +1992,16 @@ SysCtlPIOSCCalibrate(unsigned long ulType) //! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, //! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, //! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, -//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below -//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On -//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are -//! not valid. +//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, +//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. +//! Values below \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in +//! operation on Sandstorm-, Fury-, Dustdevil-, Tempest-, and Firestorm-class. +//! devices. Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in +//! operation on Blizzard-class devices. Values below \b SYSCTL_XTAL_4MHZ +//! are never valid on Blizzard-class devices. On Sandstorm- and Fury-class +//! devices, values above \b SYSCTL_XTAL_8_19MHZ are not valid. On Dustdevil-, +//! Tempest-, and Firestorm-class devices, values above \b SYSCTL_XTAL_16_3MHZ +//! are not valid. //! //! The oscillator source is chosen with one of the following values: //! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, @@ -1993,10 +2024,10 @@ SysCtlPIOSCCalibrate(unsigned long ulType) //! crystal with one of the \b SYSCTL_XTAL_xxx values. //! //! \note If selecting the PLL as the system clock source (that is, via -//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to //! determine when the PLL has locked. If an interrupt handler for the //! system control interrupt is in place, and it responds to and clears the -//! PLL lock interrupt, this function will delay until its timeout has occurred +//! PLL lock interrupt, this function delays until its timeout has occurred //! instead of completing as soon as PLL lock is achieved. //! //! \return None. @@ -2014,7 +2045,7 @@ SysCtlClockSet(unsigned long ulConfig) if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2)) { // - // Return without changing the clocking since the requested + // Return without changing the clocking because the requested // configuration can not be achieved. // return; @@ -2022,8 +2053,8 @@ SysCtlClockSet(unsigned long ulConfig) // // Get the current value of the RCC and RCC2 registers. If using a - // Sandstorm-class device, the RCC2 register will read back as zero and the - // writes to it from within this function is ignored. + // Sandstorm-class device, the RCC2 register reads back as zero and the + // writes to it from within this function are ignored. // ulRCC = HWREG(SYSCTL_RCC); ulRCC2 = HWREG(SYSCTL_RCC2); @@ -2086,7 +2117,7 @@ SysCtlClockSet(unsigned long ulConfig) } // - // Set the new crystal value and oscillator source. Since the OSCSRC2 + // Set the new crystal value and oscillator source. Because the OSCSRC2 // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a // special encoding within ulConfig to avoid the overlap. // @@ -2137,7 +2168,7 @@ SysCtlClockSet(unsigned long ulConfig) // // Set the requested system divider and disable the appropriate - // oscillators. This will not get written immediately. + // oscillators. This value is not written immediately. // ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); @@ -2195,14 +2226,15 @@ SysCtlClockSet(unsigned long ulConfig) // //! Gets the processor clock rate. //! -//! This function determines the clock rate of the processor clock. This is -//! also the clock rate of all the peripheral modules (with the exception of -//! PWM, which has its own clock divider). +//! This function determines the clock rate of the processor clock, which is +//! also the clock rate of the peripheral modules (with the exception of +//! PWM, which has its own clock divider; other peripherals may have different +//! clocking, see the device data sheet for details). //! -//! \note This will not return accurate results if SysCtlClockSet() has not +//! \note This cannot return accurate results if SysCtlClockSet() has not //! been called to configure the clocking of the device, or if the device is //! directly clocked from a crystal (or a clock source) that is not one of the -//! supported crystal frequencies. In the later case, this function should be +//! supported crystal frequencies. In the latter case, this function should be //! modified to directly return the correct system clock rate. //! //! \return The processor clock rate. @@ -2216,8 +2248,8 @@ SysCtlClockGet(void) // // Read RCC and RCC2. For Sandstorm-class devices (which do not have - // RCC2), the RCC2 read will return 0, which indicates that RCC2 is - // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear). + // RCC2), the RCC2 read returns 0, indicating that RCC2 is + // disabled (because the SYSCTL_RCC2_USERCC2 bit is clear). // ulRCC = HWREG(SYSCTL_RCC); ulRCC2 = HWREG(SYSCTL_RCC2); @@ -2261,7 +2293,7 @@ SysCtlClockGet(void) { // // The internal oscillator on a rev A2 Fury-class device and a - // rev A0 Dustdevil-class device is 12 MHz +/- 30%. + // Dustdevil-class device is 12 MHz +/- 30%. // ulClk = 12000000; } @@ -2296,7 +2328,7 @@ SysCtlClockGet(void) { // // The internal oscillator on a rev A2 Fury-class device and a - // rev A0 Dustdevil-class device is 12 MHz +/- 30%. + // Dustdevil-class device is 12 MHz +/- 30%. // ulClk = 12000000 / 4; } @@ -2311,19 +2343,19 @@ SysCtlClockGet(void) } // - // The internal 30 KHz oscillator is the source clock. + // The internal 30-KHz oscillator is the source clock. // case SYSCTL_RCC_OSCSRC_30: { // - // The internal 30 KHz oscillator has an accuracy of +/- 30%. + // The internal 30-KHz oscillator has an accuracy of +/- 30%. // ulClk = 30000; break; } // - // The 4.19 MHz clock from the hibernate module is the clock source. + // The 4.194304-MHz clock from the hibernate module is the clock source. // case SYSCTL_RCC2_OSCSRC2_419: { @@ -2332,7 +2364,7 @@ SysCtlClockGet(void) } // - // The 32 KHz clock from the hibernate module is the source clock. + // The 32.768-KHz clock from the hibernate module is the source clock. // case SYSCTL_RCC2_OSCSRC2_32: { @@ -2363,7 +2395,7 @@ SysCtlClockGet(void) { // // Read the two PLL frequency registers. The formula for a - // Garnet-class device is "(xtal * m) / ((q + 1) * (n + 1))". + // Blizzard-class device is "(xtal * m) / ((q + 1) * (n + 1))". // ulPLL = HWREG(SYSCTL_PLLFREQ0); ulPLL1 = HWREG(SYSCTL_PLLFREQ1); @@ -2443,7 +2475,7 @@ SysCtlClockGet(void) // // Force the system divider to be enabled. It is always used when - // using the PLL, but in some cases it will not read as being enabled. + // using the PLL, but in some cases it does not read as being enabled. // ulRCC |= SYSCTL_RCC_USESYSDIV; } @@ -2541,8 +2573,8 @@ SysCtlDeepSleepClockSet(unsigned long ulConfig) //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or //! \b SYSCTL_PWMDIV_64. //! -//! This function sets the rate of the clock provided to the PWM module as a -//! ratio of the processor clock. This clock is used by the PWM module to +//! This function configures the rate of the clock provided to the PWM module +//! as a ratio of the processor clock. This clock is used by the PWM module to //! generate PWM signals; its rate forms the basis for all PWM signals. //! //! \note The clocking of the PWM is dependent upon the system clock rate as @@ -2628,10 +2660,10 @@ SysCtlPWMClockGet(void) //! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, //! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. //! -//! This function sets the rate at which the ADC samples are captured by the -//! ADC block. The sampling speed may be limited by the hardware, so the +//! This function configures the rate at which the ADC samples are captured by +//! the ADC block. The sampling speed may be limited by the hardware, so the //! sample rate may end up being slower than requested. SysCtlADCSpeedGet() -//! will return the actual speed in use. +//! returns the actual speed in use. //! //! \return None. // @@ -2653,7 +2685,7 @@ SysCtlADCSpeedSet(unsigned long ulSpeed) ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0); // - // Set the ADC speed in run, sleep, and deep-sleep mode. + // Set the ADC speed in run and sleep mode. // HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) | ulSpeed); @@ -2701,7 +2733,7 @@ SysCtlADCSpeedGet(void) //! Sandstorm-class devices. //! //! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the main oscillator will verify the +//! verification timer to operate as the main oscillator verifies the //! internal oscillator. //! //! \return None. @@ -2739,7 +2771,7 @@ SysCtlIOSCVerificationSet(tBoolean bEnable) //! Sandstorm-class devices. //! //! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the internal oscillator will verify the +//! verification timer to operate as the internal oscillator verifies the //! main oscillator. //! //! \return None. @@ -2840,7 +2872,7 @@ SysCtlClkVerificationClear(void) //! The \e ulGPIOPeripheral argument must be only one of the following values: //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH. +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. //! //! \return None. // @@ -2875,12 +2907,12 @@ SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral) //! //! This function disables the specified GPIO peripheral for access from the //! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed -//! from the legacy Advanced Peripheral Bus (AHB). +//! from the legacy Advanced Peripheral Bus (APB). //! //! The \b ulGPIOPeripheral argument must be only one of the following values: //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH. +//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. //! //! \return None. // @@ -2911,7 +2943,7 @@ SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral) // //! Powers up the USB PLL. //! -//! This function will enable the USB controller's PLL which is used by it's +//! This function enables the USB controller's PLL, which is used by it's //! physical layer. This call is necessary before connecting to any external //! devices. //! @@ -2931,9 +2963,9 @@ SysCtlUSBPLLEnable(void) // //! Powers down the USB PLL. //! -//! This function will disable the USB controller's PLL which is used by it's +//! This function disables the USB controller's PLL, which is used by it's //! physical layer. The USB registers are still accessible, but the physical -//! layer will no longer function. +//! layer no longer functions. //! //! \return None. // @@ -2942,7 +2974,7 @@ void SysCtlUSBPLLDisable(void) { // - // Turn of USB PLL. + // Turn off the USB PLL. // HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; } @@ -2951,20 +2983,20 @@ SysCtlUSBPLLDisable(void) // //! Sets the MCLK frequency provided to the I2S module. //! -//! \param ulInputClock is the input clock to the MCLK divider. If this is -//! zero, the value is computed from the current PLL configuration. -//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output -//! is disabled. +//! \param ulInputClock is the input clock to the MCLK divider. If this value +//! is zero, the value is computed from the current PLL configuration. +//! \param ulMClk is the desired MCLK frequency. If this value is zero, MCLK +//! output is disabled. //! -//! This function sets the dividers to provide MCLK to the I2S module. A MCLK -//! divider is chosen that produces the MCLK frequency that is the closest +//! This function confgiures the dividers to provide MCLK to the I2S module. A +//! MCLK divider is chosen that produces the MCLK frequency that is the closest //! possible to the requested frequency, which may be above or below the //! requested frequency. //! //! The actual MCLK frequency is returned. It is the responsibility of the //! application to determine if the selected MCLK is acceptable; in general the //! human ear can not discern the frequency difference if it is within 0.3% of -//! the desired frequency (though there is a very small percentage of the +//! the desired frequency (although there is a very small percentage of the //! population that can discern lower frequency deviations). //! //! \return Returns the actual MCLK frequency. diff --git a/bsp/lm4f232/Libraries/driverlib/sysctl.h b/bsp/lm4f232/Libraries/driverlib/sysctl.h index 7ccf713bca..a718c67b25 100644 --- a/bsp/lm4f232/Libraries/driverlib/sysctl.h +++ b/bsp/lm4f232/Libraries/driverlib/sysctl.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/sysexc.c b/bsp/lm4f232/Libraries/driverlib/sysexc.c index 70bb7eebd1..c3129e4c53 100644 --- a/bsp/lm4f232/Libraries/driverlib/sysexc.c +++ b/bsp/lm4f232/Libraries/driverlib/sysexc.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -42,10 +42,10 @@ //! exception interrupt occurs. //! //! This function places the address of the system exception interrupt handler -//! into the interrupt vector table in SRAM. It also enables the global -//! interrupt in the interrupt controller; specific system exception interrupts -//! must be enabled via SysExcIntEnable(). It is the interrupt handler's -//! responsibility to clear the interrupt source. +//! into the interrupt vector table in SRAM. This function also enables the +//! global interrupt in the interrupt controller; specific system exception +//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -72,8 +72,9 @@ SysExcIntRegister(void (*pfnHandler)(void)) //! Unregisters the system exception interrupt handler. //! //! This function removes the system exception interrupt handler from the -//! vector table in SRAM. It also masks off the system exception interrupt in -//! the interrupt controller so that the interrupt handler is no longer called. +//! vector table in SRAM. This function also masks off the system exception +//! interrupt in the interrupt controller so that the interrupt handler is no +//! longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -197,9 +198,10 @@ SysExcIntStatus(tBoolean bMasked) //! //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. //! -//! The specified system exception interrupt sources are cleared, so that they -//! no longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being recognized again immediately upon exit. +//! This function clears the specified system exception interrupt sources, so +//! that they no longer assert. This function must be called in the interrupt +//! handler to keep the interrupt from being recognized again immediately upon +//! exit. //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! diff --git a/bsp/lm4f232/Libraries/driverlib/sysexc.h b/bsp/lm4f232/Libraries/driverlib/sysexc.h index f31f8eee9a..78088cb05a 100644 --- a/bsp/lm4f232/Libraries/driverlib/sysexc.h +++ b/bsp/lm4f232/Libraries/driverlib/sysexc.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/systick.c b/bsp/lm4f232/Libraries/driverlib/systick.c index c8a581d80a..1fb10993c9 100644 --- a/bsp/lm4f232/Libraries/driverlib/systick.c +++ b/bsp/lm4f232/Libraries/driverlib/systick.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -40,15 +40,15 @@ // //! Enables the SysTick counter. //! -//! This will start the SysTick counter. If an interrupt handler has been +//! This function starts the SysTick counter. If an interrupt handler has been //! registered, it is called when the SysTick counter rolls over. //! -//! \note Calling this function will cause the SysTick counter to (re)commence +//! \note Calling this function causes the SysTick counter to (re)commence //! counting from its current value. The counter is not automatically reloaded //! with the period as specified in a previous call to SysTickPeriodSet(). If //! an immediate reload is required, the \b NVIC_ST_CURRENT register must be -//! written to force this. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the supplied period on the next +//! written to force the reload. Any write to this register clears the SysTick +//! counter to 0 and causes a reload with the supplied period on the next //! clock. //! //! \return None. @@ -67,8 +67,8 @@ SysTickEnable(void) // //! Disables the SysTick counter. //! -//! This will stop the SysTick counter. If an interrupt handler has been -//! registered, it will no longer be called until SysTick is restarted. +//! This function stops the SysTick counter. If an interrupt handler has been +//! registered, it is not called until SysTick is restarted. //! //! \return None. // @@ -89,7 +89,8 @@ SysTickDisable(void) //! \param pfnHandler is a pointer to the function to be called when the //! SysTick interrupt occurs. //! -//! This sets the handler to be called when a SysTick interrupt occurs. +//! This function registers the handler to be called when a SysTick interrupt +//! occurs. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -115,7 +116,7 @@ SysTickIntRegister(void (*pfnHandler)(void)) // //! Unregisters the interrupt handler for the SysTick interrupt. //! -//! This function will clear the handler to be called when a SysTick interrupt +//! This function unregisters the handler to be called when a SysTick interrupt //! occurs. //! //! \sa IntRegister() for important information about registering interrupt @@ -142,12 +143,12 @@ SysTickIntUnregister(void) // //! Enables the SysTick interrupt. //! -//! This function will enable the SysTick interrupt, allowing it to be +//! This function enables the SysTick interrupt, allowing it to be //! reflected to the processor. //! -//! \note The SysTick interrupt handler does not need to clear the SysTick -//! interrupt source as this is done automatically by NVIC when the interrupt -//! handler is called. +//! \note The SysTick interrupt handler is not required to clear the SysTick +//! interrupt source because it is cleared automatically by the NVIC when the +//! interrupt handler is called. //! //! \return None. // @@ -165,7 +166,7 @@ SysTickIntEnable(void) // //! Disables the SysTick interrupt. //! -//! This function will disable the SysTick interrupt, preventing it from being +//! This function disables the SysTick interrupt, preventing it from being //! reflected to the processor. //! //! \return None. @@ -185,16 +186,16 @@ SysTickIntDisable(void) //! Sets the period of the SysTick counter. //! //! \param ulPeriod is the number of clock ticks in each period of the SysTick -//! counter; must be between 1 and 16,777,216, inclusive. +//! counter and must be between 1 and 16,777,216, inclusive. //! -//! This function sets the rate at which the SysTick counter wraps; this +//! This function sets the rate at which the SysTick counter wraps, which //! equates to the number of processor clocks between interrupts. //! //! \note Calling this function does not cause the SysTick counter to reload //! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT //! register must be written. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on -//! the next clock after the SysTick is enabled. +//! counter to 0 and causes a reload with the \e ulPeriod supplied here on +//! the next clock after SysTick is enabled. //! //! \return None. // @@ -217,7 +218,7 @@ SysTickPeriodSet(unsigned long ulPeriod) // //! Gets the period of the SysTick counter. //! -//! This function returns the rate at which the SysTick counter wraps; this +//! This function returns the rate at which the SysTick counter wraps, which //! equates to the number of processor clocks between interrupts. //! //! \return Returns the period of the SysTick counter. @@ -236,8 +237,8 @@ SysTickPeriodGet(void) // //! Gets the current value of the SysTick counter. //! -//! This function returns the current value of the SysTick counter; this will -//! be a value between the period - 1 and zero, inclusive. +//! This function returns the current value of the SysTick counter, which is +//! a value between the period - 1 and zero, inclusive. //! //! \return Returns the current value of the SysTick counter. // diff --git a/bsp/lm4f232/Libraries/driverlib/systick.h b/bsp/lm4f232/Libraries/driverlib/systick.h index c9d0d5fe9e..fc33f25eef 100644 --- a/bsp/lm4f232/Libraries/driverlib/systick.h +++ b/bsp/lm4f232/Libraries/driverlib/systick.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/timer.c b/bsp/lm4f232/Libraries/driverlib/timer.c index 5a8cac15ea..ae255e058b 100644 --- a/bsp/lm4f232/Libraries/driverlib/timer.c +++ b/bsp/lm4f232/Libraries/driverlib/timer.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -91,7 +91,8 @@ TimerBaseValid(unsigned long ulBase) //! //! \param ulBase is the base address of the timer module. //! -//! Given a timer base address, returns the corresponding interrupt number. +//! Given a timer base address, this function returns the corresponding +//! interrupt number. //! //! \return Returns a timer interrupt number, or -1 if \e ulBase is invalid. // @@ -194,7 +195,7 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer) //! \param ulConfig is the configuration for the timer. //! //! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured, and is left in the disabled +//! module is disabled before being configured and is left in the disabled //! state. There are two types of timers; a 16/32-bit variety and a 32/64-bit //! variety. The 16/32-bit variety is comprised of two 16-bit timers that can //! operate independently or be concatenated to form a 32-bit timer. @@ -298,8 +299,8 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig) //! \b TIMER_B, or \b TIMER_BOTH. //! \param bInvert specifies the output level. //! -//! This function sets the PWM output level for the specified timer. If the -//! \e bInvert parameter is \b true, then the timer's output is made active +//! This function configures the PWM output level for the specified timer. If +//! the \e bInvert parameter is \b true, then the timer's output is made active //! low; otherwise, it is made active high. //! //! \return None. @@ -327,15 +328,15 @@ TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, //***************************************************************************** // -//! Enables or disables the trigger output. +//! Enables or disables the ADC trigger output. //! //! \param ulBase is the base address of the timer module. //! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. -//! \param bEnable specifies the desired trigger state. +//! \param bEnable specifies the desired ADC trigger state. //! -//! This function controls the trigger output for the specified timer. If the -//! \e bEnable parameter is \b true, then the timer's output trigger is +//! This function controls the ADC trigger output for the specified timer. If +//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is //! enabled; otherwise it is disabled. //! //! \return None. @@ -354,6 +355,7 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, // // Set the trigger output as requested. + // Set the ADC trigger output as requested. // ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; HWREG(ulBase + TIMER_O_CTL) = (bEnable ? @@ -372,8 +374,8 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, //! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or //! \b TIMER_EVENT_BOTH_EDGES. //! -//! This function sets the signal edge(s) that triggers the timer when in -//! capture mode. +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. //! //! \return None. // @@ -448,7 +450,8 @@ TimerControlStall(unsigned long ulBase, unsigned long ulTimer, //! count to its timeout in order for this timer to start counting. Refer to //! the part's data sheet for a description of the trigger chain. //! -//! \note This functionality is not available on all parts. +//! \note This functionality is not available on all parts. This function +//! should not be used for Timer 0A or Wide Timer 0A. //! //! \return None. // @@ -557,9 +560,11 @@ TimerRTCDisable(unsigned long ulBase) //! (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) for //! 32/64-bit timers. //! -//! This function sets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. +//! This function configures the value of the input clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. The prescaler provides the least +//! significant bits when counting down in periodic and one-shot modes; in all +//! other modes, the prescaler provides the most significant bits. //! //! \note The availability of the prescaler varies with the Stellaris part and //! timer mode in use. Please consult the datasheet for the part you are using @@ -607,7 +612,9 @@ TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, //! //! This function gets the value of the input clock prescaler. The prescaler //! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. +//! of the half-width timer modes. The prescaler provides the least significant +//! bits when counting down in periodic and one-shot modes; in all other modes, +//! the prescaler provides the most significant bits. //! //! \note The availability of the prescaler varies with the Stellaris part and //! timer mode in use. Please consult the datasheet for the part you are using @@ -644,9 +651,12 @@ TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) //! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 //! (inclusive) for 32/64-bit timers. //! -//! This function sets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and the prescaler, -//! the prescale match effectively extends the range of the match. +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. //! //! \note The availability of the prescaler match varies with the Stellaris //! part and timer mode in use. Please consult the datasheet for the part you @@ -694,7 +704,10 @@ TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, //! //! This function gets the value of the input clock prescaler match value. //! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. //! //! \note The availability of the prescaler match varies with the Stellaris //! part and timer mode in use. Please consult the datasheet for the part you @@ -730,11 +743,11 @@ TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) //! timer is configured for full-width operation. //! \param ulValue is the load value. //! -//! This function sets the timer load value; if the timer is running then the -//! value is immediately loaded into the timer. +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. //! //! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers, and for half-width modes of 32/64-bit timers. Use +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use //! TimerLoadSet64() for full-width modes of 32/64-bit timers. //! //! \return None. @@ -781,7 +794,7 @@ TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, //! specified timer. //! //! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers, and for half-width modes of 32/64-bit timers. Use +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use //! TimerLoadGet64() for full-width modes of 32/64-bit timers. //! //! \return Returns the load value for the timer. @@ -810,8 +823,8 @@ TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ullValue is the load value. //! -//! This function sets the timer load value for a 64-bit timer; if the timer is -//! running then the value is immediately loaded into the timer. +//! This function configures the timer load value for a 64-bit timer; if the +//! timer is running, then the value is immediately loaded into the timer. //! //! \return None. // @@ -888,7 +901,7 @@ TimerLoadGet64(unsigned long ulBase) //! This function reads the current value of the specified timer. //! //! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers, and for half-width modes of 32/64-bit timers. Use +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use //! TimerValueGet64() for full-width modes of 32/64-bit timers. //! //! \return Returns the current value of the timer. @@ -962,12 +975,14 @@ TimerValueGet64(unsigned long ulBase) //! timer is configured for full-width operation. //! \param ulValue is the match value. //! -//! This function sets the match value for a timer. This value is used in -//! capture count mode to determine when to interrupt the processor and in PWM -//! mode to determine the duty cycle of the output signal. +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. On some +//! Stellaris devices, match interrupts can also be generated in periodic and +//! one-shot modes. //! //! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers, and for half-width modes of 32/64-bit timers. Use +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use //! TimerMatchSet64() for full-width modes of 32/64-bit timers. //! //! \return None. @@ -1013,7 +1028,7 @@ TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, //! This function gets the match value for the specified timer. //! //! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers, and for half-width modes of 32/64-bit timers. Use +//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use //! TimerMatchGet64() for full-width modes of 32/64-bit timers. //! //! \return Returns the match value for the timer. @@ -1042,9 +1057,9 @@ TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ullValue is the match value. //! -//! This function sets the match value for a timer. This value is used in -//! capture count mode to determine when to interrupt the processor and in PWM -//! mode to determine the duty cycle of the output signal. +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. //! //! \return None. // @@ -1118,11 +1133,11 @@ TimerMatchGet64(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when the timer //! interrupt occurs. //! -//! This function sets the handler to be called when a timer interrupt occurs. -//! In addition, this function enables the global interrupt in the interrupt -//! controller; specific timer interrupts must be enabled via TimerIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via TimerIntClear(). +//! This function registers the handler to be called when a timer interrupt +//! occurs. In addition, this function enables the global interrupt in the +//! interrupt controller; specific timer interrupts must be enabled via +//! TimerIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt source via TimerIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1187,9 +1202,9 @@ TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, //! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, //! \b TIMER_B, or \b TIMER_BOTH. //! -//! This function clears the handler to be called when a timer interrupt +//! This function unregisters the handler to be called when a timer interrupt //! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. +//! controller so that the interrupt handler is no longer called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -1252,9 +1267,9 @@ TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) //! \param ulBase is the base address of the timer module. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. //! -//! Enables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter must be the logical OR of any combination of //! the following: @@ -1291,9 +1306,9 @@ TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulBase is the base address of the timer module. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. //! -//! Disables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to TimerIntEnable(). @@ -1361,7 +1376,7 @@ TimerIntStatus(unsigned long ulBase, tBoolean bMasked) //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to TimerIntEnable(). //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1391,11 +1406,11 @@ TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) // //! Synchronizes the counters in a set of timers. //! -//! \param ulBase is the base address of the timer module. This must be the -//! base address of Timer0 (in other words, \b TIMER0_BASE). +//! \param ulBase is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b TIMER0_BASE). //! \param ulTimers is the set of timers to synchronize. //! -//! This function will synchronize the counters in a specified set of timers. +//! This function synchronizes the counters in a specified set of timers. //! When a timer is running in half-width mode, each half can be included or //! excluded in the synchronization event. When a timer is running in //! full-width mode, only the A timer can be synchronized (specifying the B @@ -1454,9 +1469,9 @@ TimerSynchronize(unsigned long ulBase, unsigned long ulTimers) // // \param ulBase is the base address of the timer module. // -// The specified timer is disabled, and all its interrupts are disabled, -// cleared, and unregistered. Then the timer registers are set to their reset -// value. +// This function disables the specified timer, and all its interrupts are +// disabled, cleared, and unregistered. Then the timer registers are set to +// their reset value. // // \return None. // @@ -1486,7 +1501,7 @@ TimerQuiesce(unsigned long ulBase) HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; // - // Unregister the interrupt handler. This also disables interrupts to the + // Unregister the interrupt handler, which also disables interrupts to the // core. // TimerIntUnregister(ulBase, TIMER_BOTH); diff --git a/bsp/lm4f232/Libraries/driverlib/timer.h b/bsp/lm4f232/Libraries/driverlib/timer.h index f881805eae..c27ac8d18e 100644 --- a/bsp/lm4f232/Libraries/driverlib/timer.h +++ b/bsp/lm4f232/Libraries/driverlib/timer.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/uart.c b/bsp/lm4f232/Libraries/driverlib/uart.c index 8f8bb453af..5323cb86d5 100644 --- a/bsp/lm4f232/Libraries/driverlib/uart.c +++ b/bsp/lm4f232/Libraries/driverlib/uart.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -97,7 +97,8 @@ UARTBaseValid(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! Given a UART base address, returns the corresponding interrupt number. +//! Given a UART base address, this function returns the corresponding +//! interrupt number. //! //! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid. // @@ -139,12 +140,12 @@ UARTIntNumberGet(unsigned long ulBase) //! \param ulBase is the base address of the UART port. //! \param ulParity specifies the type of parity to use. //! -//! This function sets the type of parity to use for transmitting and expect -//! when receiving. The \e ulParity parameter must be one of +//! This function configures the type of parity to use for transmitting and +//! expect when receiving. The \e ulParity parameter must be one of //! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two allow -//! direct control of the parity bit; it is always either one or zero based on -//! the mode. +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two +//! parameters allow direct control of the parity bit; it is always either one +//! or zero based on the mode. //! //! \return None. // @@ -211,8 +212,8 @@ UARTParityModeGet(unsigned long ulBase) //! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, //! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. //! -//! This function sets the FIFO level at which transmit and receive interrupts -//! are generated. +//! This function configures the FIFO level at which transmit and receive +//! interrupts are generated. //! //! \return None. // @@ -403,8 +404,8 @@ UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, //! \param pulBaud is a pointer to storage for the baud rate. //! \param pulConfig is a pointer to storage for the data format. //! -//! The baud rate and data format for the UART is determined, given an -//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! This function determines the baud rate and data format for the UART, given +//! an explicitly provided peripheral clock (hence the ExpClk suffix). The //! returned baud rate is the actual baud rate; it may not be the exact baud //! rate requested or an ``official'' baud rate. The data format returned in //! \e pulConfig is enumerated the same as the \e ulConfig parameter of @@ -471,7 +472,7 @@ UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, //! //! \param ulBase is the base address of the UART port. //! -//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit +//! This function sets the UARTEN, TXE, and RXE bits and enables the transmit //! and receive FIFOs. //! //! \return None. @@ -567,7 +568,7 @@ UARTFIFOEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! This functions disables the transmit and receive FIFOs in the UART. +//! This function disables the transmit and receive FIFOs in the UART. //! //! \return None. // @@ -594,8 +595,8 @@ UARTFIFODisable(unsigned long ulBase) //! \param bLowPower indicates if SIR Low Power Mode is to be used. //! //! This function enables the SIREN control bit for IrDA mode on the UART. If -//! the \e bLowPower flag is set, then SIRLP bit will also be set. This -//! function will only have an effect if the UART has not been enabled +//! the \e bLowPower flag is set, then SIRLP bit is also set. This +//! function only has an effect if the UART has not been enabled //! by a call to UARTEnable(). The call UARTEnableSIR() must be made before //! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function //! calls the UARTEnable() function. Another option is to call UARTDisable() @@ -603,8 +604,8 @@ UARTFIFODisable(unsigned long ulBase) //! UARTEnable(). //! //! \note The availability of SIR (IrDA) operation varies with the Stellaris -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. //! //! \return None. // @@ -637,7 +638,7 @@ UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower) //! \param ulBase is the base address of the UART port. //! //! This function clears the SIREN (IrDA) and SIRLP (Low Power) bits. This -//! function will only have an effect if the UART has not been enabled by a +//! function only has an effect if the UART has not been enabled by a //! call to UARTEnable(). The call UARTEnableSIR() must be made before //! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function //! calls the UARTEnable() function. Another option is to call UARTDisable() @@ -645,8 +646,8 @@ UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower) //! UARTEnable(). //! //! \note The availability of SIR (IrDA) operation varies with the Stellaris -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. //! //! \return None. // @@ -671,13 +672,13 @@ UARTDisableSIR(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! This function enables the SMART control bit for ISO7816 smart card mode on -//! the UART. This call also sets 8 bit word length and even parity as +//! This function enables the SMART control bit for the ISO7816 smart card mode +//! on the UART. This call also sets 8-bit word length and even parity as //! required by ISO7816. //! -//! \note The availability of ISO7816 smart card mode varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! \note The availability of SIR (IrDA) operation varies with the Stellaris +//! part in use. Please consult the datasheet for the part you are using to +//! determine whether this support is available. //! //! \return None. // @@ -694,9 +695,9 @@ UARTSmartCardEnable(unsigned long ulBase) ASSERT(UARTBaseValid(ulBase)); // - // Set 8 bit word length, even parity, 2 stop bits (even though the STP2 - // bit is ignored when in smartcard mode, this lets the caller read back - // the actual setting in use). + // Set 8-bit word length, even parity, 2 stop bits (note that although the + // STP2 bit is ignored when in smartcard mode, this code lets the caller + // read back the actual setting in use). // ulVal = HWREG(ulBase + UART_O_LCRH); ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | @@ -716,12 +717,12 @@ UARTSmartCardEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the UART port. //! -//! This function clears the SMART (ISO7816 smart card) bits in the UART +//! This function clears the SMART (ISO7816 smart card) bit in the UART //! control register. //! //! \note The availability of ISO7816 smart card mode varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. //! //! \return None. // @@ -749,17 +750,17 @@ UARTSmartCardDisable(unsigned long ulBase) //! \param ulControl is a bit-mapped flag indicating which modem control bits //! should be set. //! -//! This function sets the states of the DTR or RTS modem handshake outputs -//! from the UART. +//! This function configures the states of the DTR or RTS modem handshake +//! outputs from the UART. //! //! The \e ulControl parameter is the logical OR of any of the following: //! //! - \b UART_OUTPUT_DTR - The Modem Control DTR signal //! - \b UART_OUTPUT_RTS - The Modem Control RTS signal //! -//! \note The availability of hardware modem handshake signals varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! \note The availability of ISO7816 smart card mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. //! //! \return None. // @@ -840,8 +841,8 @@ UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) //! Stellaris part and UART in use. Please consult the datasheet for the part //! you are using to determine whether this support is available. //! -//! \return Returns the states of the handshake output signals. This is a -//! logical logical OR combination of values \b UART_OUTPUT_RTS and +//! \return Returns the states of the handshake output signals. This value is +//! a logical OR combination of values \b UART_OUTPUT_RTS and //! \b UART_OUTPUT_DTR where the presence of each flag indicates that the //! associated signal is asserted. // @@ -872,7 +873,7 @@ UARTModemControlGet(unsigned long ulBase) //! you are using to determine whether this support is available. //! //! \return Returns the states of the handshake output signals. This value -//! is a logical logical OR combination of values \b UART_INPUT_RI, +//! is a logical OR combination of values \b UART_INPUT_RI, //! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the //! presence of each flag indicates that the associated signal is asserted. // @@ -900,9 +901,9 @@ UARTModemStatusGet(unsigned long ulBase) //! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) //! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. //! -//! This function sets the required hardware flow control modes. If \e ulMode -//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the -//! incoming CTS signal is asserted. If \e ulMode contains flag +//! This function configures the required hardware flow control modes. If +//! \e ulMode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted +//! if the incoming CTS signal is asserted. If \e ulMode contains flag //! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is //! asserted only when there is space available in the receive FIFO. If no //! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be @@ -945,7 +946,7 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) //! part and UART in use. Please consult the datasheet for the part you are //! using to determine whether this support is available. //! -//! \return Returns the current flow control mode in use. This is a +//! \return Returns the current flow control mode in use. This value is a //! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit //! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) //! flow control is in use. If hardware flow control is disabled, @@ -1016,11 +1017,11 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) //! //! This function returns the current operating mode for the UART transmit //! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit -//! interrupt is currently set to be asserted once the transmitter is +//! interrupt is currently configured to be asserted once the transmitter is //! completely idle - the transmit FIFO is empty and all bits, including any //! stop bits, have cleared the transmitter. The return value is -//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon -//! the level of the transmit FIFO. +//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based +//! on the level of the transmit FIFO. //! //! \note The availability of end-of-transmission mode varies with the //! Stellaris part in use. Please consult the datasheet for the part you are @@ -1188,7 +1189,7 @@ UARTCharGet(unsigned long ulBase) //! //! This function writes the character \e ucData to the transmit FIFO for the //! specified port. This function does not block, so if there is no space -//! available, then a \b false is returned, and the application must retry the +//! available, then a \b false is returned and the application must retry the //! function later. //! //! This function replaces the original UARTCharNonBlockingPut() API and @@ -1305,10 +1306,10 @@ UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) //! //! \param ulBase is the base address of the UART port. //! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \b false is returned, the transmit FIFO is -//! empty and all bits of the last transmitted character, including all stop -//! bits, have left the hardware shift register. +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, the +//! transmit FIFO is empty and all bits of the last transmitted character, +//! including all stop bits, have left the hardware shift register. //! //! \return Returns \b true if the UART is transmitting or \b false if all //! transmissions are complete. @@ -1429,7 +1430,7 @@ UARTIntUnregister(unsigned long ulBase) //! //! The \e ulIntFlags parameter is the logical OR of any of the following: //! -//! - \b UART_INT_9BIT - 9-bit address match interrupt +//! - \b UART_INT_9BIT - 9-bit Address Match interrupt //! - \b UART_INT_OE - Overrun Error interrupt //! - \b UART_INT_BE - Break Error interrupt //! - \b UART_INT_PE - Parity Error interrupt @@ -1537,12 +1538,12 @@ UARTIntStatus(unsigned long ulBase, tBoolean bMasked) //! //! The specified UART interrupt sources are cleared, so that they no longer //! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. +//! interrupt from being triggered again immediately upon exit. //! //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags //! parameter to UARTIntEnable(). //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -1576,7 +1577,7 @@ UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) //! \param ulDMAFlags is a bit mask of the DMA features to enable. //! //! The specified UART DMA features are enabled. The UART can be -//! configured to use DMA for transmit or receive, and to disable +//! configured to use DMA for transmit or receive and to disable //! receive if an error occurs. The \e ulDMAFlags parameter is the //! logical OR of any of the following values: //! @@ -1645,8 +1646,8 @@ UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) //! This function returns the current state of each of the 4 receiver error //! sources. The returned errors are equivalent to the four error bits //! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately the overrun -//! occurs rather than when a character is next read. +//! with the exception that the overrun error is set immediately when the +//! overrun occurs rather than when a character is next read. //! //! \return Returns a logical OR combination of the receiver error flags, //! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK @@ -1690,7 +1691,7 @@ UARTRxErrorClear(unsigned long ulBase) ASSERT(UARTBaseValid(ulBase)); // - // Any write to the Error Clear Register will clear all bits which are + // Any write to the Error Clear Register clears all bits which are // currently set. // HWREG(ulBase + UART_O_ECR) = 0; @@ -1707,13 +1708,13 @@ UARTRxErrorClear(unsigned long ulBase) //! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or //! the precision internal oscillator (\b UART_CLOCK_PIOSC). //! -//! Changing the baud clock source will change the baud rate generated by the +//! Changing the baud clock source changes the baud rate generated by the //! UART. Therefore, the baud rate should be reconfigured after any change to //! the baud clock source. //! //! \note The ability to specify the UART baud clock source varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. //! //! \return None. // @@ -1744,8 +1745,8 @@ UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource) //! the precision internal oscillator (\b UART_CLOCK_PIOSC). //! //! \note The ability to specify the UART baud clock source varies with the -//! Stellaris part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. //! //! \return None. // @@ -1772,9 +1773,9 @@ UARTClockSourceGet(unsigned long ulBase) //! //! This function enables the 9-bit operational mode of the UART. //! -//! \note The availability of 9-bit mode varies with the Stellaris part and -//! UART in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. //! //! \return None. // @@ -1801,9 +1802,9 @@ UART9BitEnable(unsigned long ulBase) //! //! This function disables the 9-bit operational mode of the UART. //! -//! \note The availability of 9-bit mode varies with the Stellaris part and -//! UART in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. //! //! \return None. // @@ -1830,15 +1831,15 @@ UART9BitDisable(unsigned long ulBase) //! \param ucAddr is the device address. //! \param ucMask is the device address mask. //! -//! This function sets the device address, or range of device addresses, that -//! respond to requests on the 9-bit UART port. The received address is masked -//! with the mask and then compared against the given address, allowing either -//! a single address (if \b ucMask is 0xff) or a set of addresses to be +//! This function configures the device address or range of device addresses +//! that respond to requests on the 9-bit UART port. The received address is +//! masked with the mask and then compared against the given address, allowing +//! either a single address (if \b ucMask is 0xff) or a set of addresses to be //! matched. //! -//! \note The availability of 9-bit mode varies with the Stellaris part and -//! UART in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. //! //! \return None. // @@ -1875,9 +1876,9 @@ UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, //! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive //! data characters in 9-bit mode. //! -//! \note The availability of 9-bit mode varies with the Stellaris part and -//! UART in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. +//! \note The availability of 9-bit mode varies with the Stellaris part in use. +//! Please consult the datasheet for the part you are using to determine +//! whether this support is available. //! //! \return None. // diff --git a/bsp/lm4f232/Libraries/driverlib/uart.h b/bsp/lm4f232/Libraries/driverlib/uart.h index 13a166ed1a..7a91483769 100644 --- a/bsp/lm4f232/Libraries/driverlib/uart.h +++ b/bsp/lm4f232/Libraries/driverlib/uart.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/udma.c b/bsp/lm4f232/Libraries/driverlib/udma.c index 7e699ce509..4124b52312 100644 --- a/bsp/lm4f232/Libraries/driverlib/udma.c +++ b/bsp/lm4f232/Libraries/driverlib/udma.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -60,7 +60,7 @@ uDMAEnable(void) //! Disables the uDMA controller for use. //! //! This function disables the uDMA controller. Once disabled, the uDMA -//! controller will not operate until re-enabled with uDMAEnable(). +//! controller cannot operate until re-enabled with uDMAEnable(). //! //! \return None. // @@ -98,8 +98,9 @@ uDMAErrorStatusGet(void) // //! Clears the uDMA error interrupt. //! -//! This function clears a pending uDMA error interrupt. It should be called -//! from within the uDMA error interrupt handler to clear the interrupt. +//! This function clears a pending uDMA error interrupt. This function should +//! be called from within the uDMA error interrupt handler to clear the +//! interrupt. //! //! \return None. // @@ -151,7 +152,7 @@ uDMAChannelEnable(unsigned long ulChannelNum) //! \param ulChannelNum is the channel number to disable. //! //! This function disables a specific uDMA channel. Once disabled, a channel -//! will not respond to uDMA transfer requests until re-enabled via +//! cannot respond to uDMA transfer requests until re-enabled via //! uDMAChannelEnable(). //! //! \return None. @@ -178,8 +179,8 @@ uDMAChannelDisable(unsigned long ulChannelNum) //! \param ulChannelNum is the channel number to check. //! //! This function checks to see if a specific uDMA channel is enabled. This -//! can be used to check the status of a transfer, since the channel will -//! be automatically disabled at the end of a transfer. +//! function can be used to check the status of a transfer, as the channel is +//! automatically disabled at the end of a transfer. //! //! \return Returns \b true if the channel is enabled, \b false if disabled. // @@ -193,7 +194,7 @@ uDMAChannelIsEnabled(unsigned long ulChannelNum) ASSERT((ulChannelNum & 0xffff) < 32); // - // AND the specified channel bit with the enable register, and return the + // AND the specified channel bit with the enable register and return the // result. // return((HWREG(UDMA_ENASET) & (1 << (ulChannelNum & 0x1f))) ? true : false); @@ -203,16 +204,16 @@ uDMAChannelIsEnabled(unsigned long ulChannelNum) // //! Sets the base address for the channel control table. //! -//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! \param pControlTable is a pointer to the 1024-byte-aligned base address //! of the uDMA channel control table. //! -//! This function sets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. The table must be aligned on a 1024 byte boundary. The base -//! address must be set before any of the channel functions can be used. +//! This function configures the base address of the channel control table. +//! This table resides in system memory and holds control information for each +//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base +//! address must be configured before any of the channel functions can be used. //! //! The size of the channel control table depends on the number of uDMA -//! channels, and which transfer modes are used. Refer to the introductory +//! channels and the transfer modes that are used. Refer to the introductory //! text and the microcontroller datasheet for more information about the //! channel control table. //! @@ -250,7 +251,7 @@ void * uDMAControlBaseGet(void) { // - // Read the current value of the control base register, and return it to + // Read the current value of the control base register and return it to // the caller. // return((void *)HWREG(UDMA_CTLBASE)); @@ -271,7 +272,7 @@ void * uDMAControlAlternateBaseGet(void) { // - // Read the current value of the control base register, and return it to + // Read the current value of the control base register and return it to // the caller. // return((void *)HWREG(UDMA_ALTBASE)); @@ -285,9 +286,9 @@ uDMAControlAlternateBaseGet(void) //! transfer. //! //! This function allows software to request a uDMA channel to begin a -//! transfer. This could be used for performing a memory to memory transfer, -//! or if for some reason a transfer needs to be initiated by software instead -//! of the peripheral associated with that channel. +//! transfer. This function could be used for performing a memory-to-memory +//! transfer or if for some reason, a transfer needs to be initiated by software +//! instead of the peripheral associated with that channel. //! //! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then //! the completion is signaled on the uDMA dedicated interrupt. If a @@ -322,7 +323,7 @@ uDMAChannelRequest(unsigned long ulChannelNum) //! //! The \e ulAttr parameter is the logical OR of any of the following: //! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst //! mode. //! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure //! for this channel (it is very unlikely that this flag should be used). @@ -395,7 +396,7 @@ uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) //! //! The \e ulAttr parameter is the logical OR of any of the following: //! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst //! mode. //! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure //! for this channel. @@ -468,7 +469,7 @@ uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) //! //! \return Returns the logical OR of the attributes of the uDMA channel, which //! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst //! mode. //! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure //! for this channel. @@ -542,7 +543,7 @@ uDMAChannelAttributeGet(unsigned long ulChannelNum) //! parameters for the channel. //! //! This function is used to set control parameters for a uDMA transfer. These -//! are typically parameters that are not changed often. +//! parameters are typically not changed often. //! //! The \e ulChannelStructIndex parameter should be the logical OR of the //! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to @@ -630,8 +631,8 @@ uDMAChannelControlSet(unsigned long ulChannelStructIndex, //! \param pvDstAddr is the destination address for the transfer. //! \param ulTransferSize is the number of data items to transfer. //! -//! This function is used to set the parameters for a uDMA transfer. These are -//! typically parameters that are changed often. The function +//! This function is used to configure the parameters for a uDMA transfer. +//! These parameters are typically changed often. The function //! uDMAChannelControlSet() MUST be called at least once for this channel prior //! to calling this function. //! @@ -644,11 +645,11 @@ uDMAChannelControlSet(unsigned long ulChannelStructIndex, //! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode //! to this value at the end of a transfer. //! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that will always complete once -//! started even if request is removed. +//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once +//! started even if the request is removed. //! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This allows -//! use of ping-pong buffering for uDMA transfers. +//! primary and alternate control structures for the channel. This mode +//! allows use of ping-pong buffering for uDMA transfers. //! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather //! transfer. //! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather @@ -656,24 +657,24 @@ uDMAChannelControlSet(unsigned long ulChannelStructIndex, //! //! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first //! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler will take care of this if the -//! pointers are pointing to storage of the appropriate data type. +//! according to the item size. The compiler takes care of this alignment if +//! the pointers are pointing to storage of the appropriate data type. //! //! The \e ulTransferSize parameter is the number of data items, not the number //! of bytes. //! -//! The two scatter/gather modes, memory and peripheral, are actually different +//! The two scatter-gather modes, memory and peripheral, are actually different //! depending on whether the primary or alternate control structure is -//! selected. This function will look for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and will set the -//! scatter/gather mode as appropriate for the primary or alternate control +//! selected. This function looks for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and sets the +//! scatter-gather mode as appropriate for the primary or alternate control //! structure. //! //! The channel must also be enabled using uDMAChannelEnable() after calling -//! this function. The transfer will not begin until the channel has been set -//! up and enabled. Note that the channel is automatically disabled after the -//! transfer is completed, meaning that uDMAChannelEnable() must be called -//! again after setting up the next transfer. +//! this function. The transfer does not begin until the channel has been +//! configured and enabled. Note that the channel is automatically disabled +//! after the transfer is completed, meaning that uDMAChannelEnable() must be +//! called again after setting up the next transfer. //! //! \note Great care must be taken to not modify a channel control structure //! that is in use or else the results are unpredictable, including the @@ -682,7 +683,7 @@ uDMAChannelControlSet(unsigned long ulChannelStructIndex, //! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For //! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the //! primary or alternate control structure only when the other is being used. -//! The uDMAChannelModeGet() function will return \b UDMA_MODE_STOP when a +//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a //! channel control structure is inactive and safe to modify. //! //! \return None. @@ -782,7 +783,7 @@ uDMAChannelTransferSet(unsigned long ulChannelStructIndex, { // // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer needs to point to the end of + // transfer. The destination pointer must point to the end of // the alternate structure for this channel instead of calculating // the end of the buffer in the normal way. // @@ -827,12 +828,12 @@ uDMAChannelTransferSet(unsigned long ulChannelStructIndex, //! transfer (else it is memory scatter-gather transfer) //! //! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list, and pass a pointer to +//! The caller must have already set up a task list and must pass a pointer to //! the start of the task list as the \e pvTaskList parameter. The //! \e ulTaskCount parameter is the count of tasks in the task list, not the //! size of the task list. The flag \e bIsPeriphSG should be used to indicate -//! if the scatter-gather should be configured for a peripheral or memory -//! scatter-gather operation. +//! if scatter-gather should be configured for peripheral or memory +//! operation. //! //! \sa uDMATaskStructEntry //! @@ -873,15 +874,15 @@ uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, pTaskTable = (tDMAControlTable *)pvTaskList; // - // Compute the ending address for the source pointer. This is the last - // element of the last task in the task table + // Compute the ending address for the source pointer. This address is the + // last element of the last task in the task table // pControlTable[ulChannelNum].pvSrcEndAddr = &pTaskTable[ulTaskCount - 1].ulSpare; // - // Compute the ending address for the destination pointer. This is the end - // of the alternate structure for this channel. + // Compute the ending address for the destination pointer. This address + // is the end of the alternate structure for this channel. // pControlTable[ulChannelNum].pvDstEndAddr = &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; @@ -977,9 +978,9 @@ uDMAChannelSizeGet(unsigned long ulChannelStructIndex) //! \param ulChannelStructIndex is the logical OR of the uDMA channel number //! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. //! -//! This function is used to get the transfer mode for the uDMA channel. It -//! can be used to query the status of a transfer on a channel. When the -//! transfer is complete the mode is \b UDMA_MODE_STOP. +//! This function is used to get the transfer mode for the uDMA channel and +//! to query the status of a transfer on a channel. When the transfer is +//! complete the mode is \b UDMA_MODE_STOP. //! //! \return Returns the transfer mode of the specified channel and control //! structure, which is one of the following values: \b UDMA_MODE_STOP, @@ -1036,7 +1037,7 @@ uDMAChannelModeGet(unsigned long ulChannelStructIndex) // //! Selects the secondary peripheral for a set of uDMA channels. //! -//! \param ulSecPeriphs is the logical or of the uDMA channels for which to use +//! \param ulSecPeriphs is the logical OR of the uDMA channels for which to use //! the secondary peripheral, instead of the default peripheral. //! //! This function is used to select the secondary peripheral assignment for a @@ -1095,7 +1096,7 @@ uDMAChannelSelectSecondary(unsigned long ulSecPeriphs) // //! Selects the default peripheral for a set of uDMA channels. //! -//! \param ulDefPeriphs is the logical or of the uDMA channels for which to use +//! \param ulDefPeriphs is the logical OR of the uDMA channels for which to use //! the default peripheral, instead of the secondary peripheral. //! //! This function is used to select the default peripheral assignment for a set @@ -1156,9 +1157,9 @@ uDMAChannelSelectDefault(unsigned long ulDefPeriphs) //! \param pfnHandler is a pointer to the function to be called when the //! interrupt is activated. //! -//! This sets and enables the handler to be called when the uDMA controller -//! generates an interrupt. The \e ulIntChannel parameter should be one of the -//! following: +//! This function registers and enables the handler to be called when the uDMA +//! controller generates an interrupt. The \e ulIntChannel parameter should be +//! one of the following: //! //! - \b UDMA_INT_SW to register an interrupt handler to process interrupts //! from the uDMA software channel (UDMA_CHANNEL_SW) @@ -1168,8 +1169,8 @@ uDMAChannelSelectDefault(unsigned long ulDefPeriphs) //! \sa IntRegister() for important information about registering interrupt //! handlers. //! -//! \note The interrupt handler for uDMA is for transfer completion when the -//! channel UDMA_CHANNEL_SW is used, and for error interrupts. The +//! \note The interrupt handler for the uDMA is for transfer completion when +//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The //! interrupts for each peripheral channel are handled through the individual //! peripheral interrupt handlers. //! @@ -1202,7 +1203,7 @@ uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) //! //! \param ulIntChannel identifies which uDMA interrupt to unregister. //! -//! This function will disable and clear the handler to be called for the +//! This function disables and unregisters the handler to be called for the //! specified uDMA interrupt. The \e ulIntChannel parameter should be one of //! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function //! uDMAIntRegister(). @@ -1242,7 +1243,7 @@ uDMAIntUnregister(unsigned long ulIntChannel) //! your part. //! //! \return Returns a 32-bit mask which indicates requesting uDMA channels. -//! There is a bit for each channel, and a 1 in a bit indicates that channel +//! There is a bit for each channel and a 1 indicates that the channel //! is requesting an interrupt. Multiple bits can be set. // //***************************************************************************** @@ -1269,10 +1270,10 @@ uDMAIntStatus(void) //! //! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. //! -//! Clears bits in the uDMA interrupt status register according to which bits -//! are set in \e ulChanMask. There is one bit for each channel. If a a bit is -//! set in \e ulChanMask, then that corresponding channel's interrupt status is -//! cleared (if it was set). +//! This function clears bits in the uDMA interrupt status register according +//! to which bits are set in \e ulChanMask. There is one bit for each channel. +//! If a a bit is set in \e ulChanMask, then that corresponding channel's +//! interrupt status is cleared (if it was set). //! //! \note This function is only available on devices that have the DMA Channel //! Interrupt Status Register (DMACHIS). Please consult the data sheet for @@ -1303,7 +1304,7 @@ uDMAIntClear(unsigned long ulChanMask) //! Assigns a peripheral mapping for a uDMA channel. //! //! \param ulMapping is a macro specifying the peripheral assignment for -//! a channel +//! a channel. //! //! This function assigns a peripheral mapping to a uDMA channel. It is //! used to select which peripheral is used for a uDMA channel. The parameter diff --git a/bsp/lm4f232/Libraries/driverlib/udma.h b/bsp/lm4f232/Libraries/driverlib/udma.h index 71c3cf465c..a217ae5048 100644 --- a/bsp/lm4f232/Libraries/driverlib/udma.h +++ b/bsp/lm4f232/Libraries/driverlib/udma.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/usb.c b/bsp/lm4f232/Libraries/driverlib/usb.c index 2df9a82057..654948d014 100644 --- a/bsp/lm4f232/Libraries/driverlib/usb.c +++ b/bsp/lm4f232/Libraries/driverlib/usb.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -85,7 +85,7 @@ // \param ucValue is the value to write to the register. // // This function is used to access the indexed registers for each endpoint. -// The only registers that are indexed are the FIFO configuration registers +// The only registers that are indexed are the FIFO configuration registers, // which are not used after configuration. // // \return None. @@ -150,7 +150,7 @@ USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint, // // This function is used internally to access the indexed registers for each // endpoint. The only registers that are indexed are the FIFO configuration -// registers which are not used after configuration. +// registers, which are not used after configuration. // // \return The value in the register requested. // @@ -215,7 +215,7 @@ USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! -//! When used in host mode, this function will put the USB bus in the suspended +//! When used in host mode, this function puts the USB bus in the suspended //! state. //! //! \note This function should only be called in host mode. @@ -246,7 +246,7 @@ USBHostSuspend(unsigned long ulBase) //! bus. //! //! When this function is called with the \e bStart parameter set to \b true, -//! this function will cause the start of a reset condition on the USB bus. +//! this function causes the start of a reset condition on the USB bus. //! The caller should then delay at least 20ms before calling this function //! again with the \e bStart parameter set to \b false. //! @@ -284,17 +284,17 @@ USBHostReset(unsigned long ulBase, tBoolean bStart) //! \param bStart specifies if the USB controller is entering or leaving the //! resume signaling state. //! -//! When in device mode this function will bring the USB controller out of the +//! When in device mode, this function brings the USB controller out of the //! suspend state. This call should first be made with the \e bStart parameter //! set to \b true to start resume signaling. The device application should //! then delay at least 10ms but not more than 15ms before calling this //! function with the \e bStart parameter set to \b false. //! -//! When in host mode this function will signal devices to leave the suspend +//! When in host mode, this function signals devices to leave the suspend //! state. This call should first be made with the \e bStart parameter set to //! \b true to start resume signaling. The host application should then delay //! at least 20ms before calling this function with the \e bStart parameter set -//! to \b false. This will cause the controller to complete the resume +//! to \b false. This action causes the controller to complete the resume //! signaling on the USB bus. //! //! \return None. @@ -327,7 +327,7 @@ USBHostResume(unsigned long ulBase, tBoolean bStart) //! //! \param ulBase specifies the USB module base address. //! -//! This function will return the current speed of the USB bus. +//! This function returns the current speed of the USB bus. //! //! \note This function should only be called in host mode. //! @@ -371,16 +371,15 @@ USBHostSpeedGet(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function will read the source of the interrupt for the USB controller. +//! This function reads the source of the interrupt for the USB controller. //! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints, -//! and general status changes. This call will return the current status for +//! and general status changes. This call returns the current status for //! all of these interrupts. The bit values returned should be compared //! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0, //! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values. //! -//! \note This call will clear the source of all of the general status -//! interrupts. -//! +//! \note This call clears the source of all of the general status interrupts. +//! //! \note WARNING: This API cannot be used on endpoint numbers greater than //! endpoint 3 so USBIntStatusControl() or USBIntStatusEndpoint() should be //! used instead. @@ -436,7 +435,7 @@ USBIntStatus(unsigned long ulBase) if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) { // - // Indicate a id detection was detected. + // Indicate an id detection was detected. // ulStatus |= USB_INT_MODE_DETECT; @@ -460,12 +459,12 @@ USBIntStatus(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which interrupts to disable. //! -//! This function will disable the USB controller from generating the +//! This function disables the USB controller from generating the //! interrupts indicated by the \e ulFlags parameter. There are three groups //! of interrupt sources, IN Endpoints, OUT Endpoints, and general status //! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT, //! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS. If -//! \b USB_INT_ALL is specified then all interrupts are disabled. +//! \b USB_INT_ALL is specified, then all interrupts are disabled. //! //! \note WARNING: This API cannot be used on endpoint numbers greater than //! endpoint 3 so USBIntDisableControl() or USBIntDisableEndpoint() should be @@ -485,7 +484,7 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) ASSERT((ulFlags & ~(USB_INT_ALL)) == 0); // - // If any transmit interrupts were disabled then write the transmit + // If any transmit interrupts were disabled, then write the transmit // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) @@ -495,8 +494,8 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) } // - // If any receive interrupts were disabled then write the receive interrupt - // settings out to the hardware. + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) { @@ -506,8 +505,8 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) } // - // If any general interrupts were disabled then write the general interrupt - // settings out to the hardware. + // If any general interrupts were disabled, then write the general + // interrupt settings out to the hardware. // if(ulFlags & USB_INT_STATUS) { @@ -540,7 +539,7 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which interrupts to enable. //! -//! This function will enable the USB controller's ability to generate the +//! This function enables the USB controller's ability to generate the //! interrupts indicated by the \e ulFlags parameter. There are three //! groups of interrupt sources, IN Endpoints, OUT Endpoints, and //! general status changes, specified by \b USB_INT_HOST_IN, @@ -550,9 +549,9 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags) //! //! \note A call must be made to enable the interrupt in the main interrupt //! controller to receive interrupts. The USBIntRegister() API performs this -//! controller level interrupt enable. However if static interrupt handlers -//! are used then then a call to IntEnable() must be made in order to allow any -//! USB interrupts to occur. +//! controller-level interrupt enable. However if static interrupt handlers +//! are used, then then a call to IntEnable() must be made in order to allow +//! any USB interrupts to occur. //! //! \note WARNING: This API cannot be used on endpoint numbers greater than //! endpoint 3 so USBIntEnableControl() or USBIntEnableEndpoint() should be @@ -572,7 +571,7 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) ASSERT((ulFlags & (~USB_INT_ALL)) == 0); // - // If any transmit interrupts were enabled then write the transmit + // If any transmit interrupts were enabled, then write the transmit // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) @@ -582,8 +581,8 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) } // - // If any receive interrupts were enabled then write the receive interrupt - // settings out to the hardware. + // If any receive interrupts were enabled, then write the receive + // interrupt settings out to the hardware. // if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) { @@ -593,8 +592,8 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) } // - // If any general interrupts were enabled then write the general interrupt - // settings out to the hardware. + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. // if(ulFlags & USB_INT_STATUS) { @@ -627,7 +626,7 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which control interrupts to disable. //! -//! This function will disable the control interrupts for the USB controller +//! This function disables the control interrupts for the USB controller //! specified by the \e ulBase parameter. The \e ulFlags parameter specifies //! which control interrupts to disable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTCTRL_* and @@ -678,7 +677,7 @@ USBIntDisableControl(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which control interrupts to enable. //! -//! This function will enable the control interrupts for the USB controller +//! This function enables the control interrupts for the USB controller //! specified by the \e ulBase parameter. The \e ulFlags parameter specifies //! which control interrupts to enable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTCTRL_* and @@ -697,8 +696,8 @@ USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) ASSERT((ulFlags & (~USB_INTCTRL_ALL)) == 0); // - // If any general interrupts were enabled then write the general interrupt - // settings out to the hardware. + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. // if(ulFlags & USB_INTCTRL_STATUS) { @@ -728,17 +727,17 @@ USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) //! //! \param ulBase specifies the USB module base address. //! -//! This function will read control interrupt status for a USB controller. -//! This call will return the current status for control interrupts only, the -//! endpoint interrupt status is retrieved by calling USBIntStatusEndpoint(). -//! The bit values returned should be compared against the \b USB_INTCTRL_* +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned should be compared against the \b USB_INTCTRL_* //! values. //! //! The following are the meanings of all \b USB_INCTRL_ flags and the modes //! for which they are valid. These values apply to any calls to //! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). //! Some of these flags are only valid in the following modes as indicated in -//! the parenthesis: Host, Device, and OTG. +//! the parentheses: Host, Device, and OTG. //! //! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. //! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). @@ -758,9 +757,8 @@ USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags) //! (OTG Only) //! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected. (Host Only) //! -//! \note This call will clear the source of all of the control status -//! interrupts. -//! +//! \note This call clears the source of all of the control status interrupts. +//! //! \return Returns the status of the control interrupts for a USB controller. // //***************************************************************************** @@ -799,7 +797,7 @@ USBIntStatusControl(unsigned long ulBase) if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) { // - // Indicate a id detection was detected. + // Indicate an id detection. // ulStatus |= USB_INTCTRL_MODE_DETECT; @@ -822,9 +820,9 @@ USBIntStatusControl(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which endpoint interrupts to disable. //! -//! This function will disable endpoint interrupts for the USB controller -//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies -//! which endpoint interrupts to disable. The flags passed in the \e ulFlags +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ulBase parameter. The \e ulFlags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTEP_* and not //! any other \b USB_INT flags. //! @@ -840,14 +838,14 @@ USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags) ASSERT(ulBase == USB0_BASE); // - // If any transmit interrupts were disabled then write the transmit + // If any transmit interrupts were disabled, then write the transmit // interrupt settings out to the hardware. // HWREGH(ulBase + USB_O_TXIE) &= ~(ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); // - // If any receive interrupts were disabled then write the receive interrupt + // If any receive interrupts were disabled, then write the receive interrupt // settings out to the hardware. // HWREGH(ulBase + USB_O_RXIE) &= @@ -862,9 +860,9 @@ USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! \param ulFlags specifies which endpoint interrupts to enable. //! -//! This function will enable endpoint interrupts for the USB controller -//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies -//! which endpoint interrupts to enable. The flags passed in the \e ulFlags +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ulBase parameter. The \e ulFlags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ulFlags //! parameters should be the definitions that start with \b USB_INTEP_* and not //! any other \b USB_INT flags. //! @@ -899,15 +897,15 @@ USBIntEnableEndpoint(unsigned long ulBase, unsigned long ulFlags) //! //! \param ulBase specifies the USB module base address. //! -//! This function will read endpoint interrupt status for a USB controller. -//! This call will return the current status for endpoint interrupts only, the -//! control interrupt status is retrieved by calling USBIntStatusControl(). -//! The bit values returned should be compared against the \b USB_INTEP_* -//! values. These are grouped into classes for \b USB_INTEP_HOST_* and +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned should be compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and //! \b USB_INTEP_DEV_* values to handle both host and device modes with all //! endpoints. //! -//! \note This call will clear the source of all of the endpoint interrupts. +//! \note This call clears the source of all of the endpoint interrupts. //! //! \return Returns the status of the endpoint interrupts for a USB controller. // @@ -943,11 +941,11 @@ USBIntStatusEndpoint(unsigned long ulBase) //! \param pfnHandler is a pointer to the function to be called when a USB //! interrupt occurs. //! -//! This sets the handler to be called when a USB interrupt occurs. This will -//! also enable the global USB interrupt in the interrupt controller. The -//! specific desired USB interrupts must be enabled via a separate call to +//! This function registers the handler to be called when a USB interrupt +//! occurs and enables the global USB interrupt in the interrupt controller. +//! The specific desired USB interrupts must be enabled via a separate call to //! USBIntEnable(). It is the interrupt handler's responsibility to clear the -//! interrupt sources via a calls to USBIntStatusControl() and +//! interrupt sources via calls to USBIntStatusControl() and //! USBIntStatusEndpoint(). //! //! \sa IntRegister() for important information about registering interrupt @@ -981,8 +979,8 @@ USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) //! //! \param ulBase specifies the USB module base address. //! -//! This function unregister the interrupt handler. This function will also -//! disable the USB interrupt in the interrupt controller. +//! This function unregisters the interrupt handler. This function also +//! disables the USB interrupt in the interrupt controller. //! //! \sa IntRegister() for important information about registering or //! unregistering interrupt handlers. @@ -1016,11 +1014,10 @@ USBIntUnregister(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will return the status of a given endpoint. If any of these -//! status bits need to be cleared, then these these values must be cleared by -//! calling the USBDevEndpointStatusClear() or USBHostEndpointStatusClear() -//! functions. -//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions should be called. +//! //! The following are the status flags for host mode: //! //! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. @@ -1123,7 +1120,7 @@ USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint) //! \param ulEndpoint is the endpoint to access. //! \param ulFlags are the status bits that should be cleared. //! -//! This function will clear the status of any bits that are passed in the +//! This function clears the status of any bits that are passed in the //! \e ulFlags parameter. The \e ulFlags parameter can take the value returned //! from the USBEndpointStatus() call. //! @@ -1172,7 +1169,7 @@ USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulFlags are the status bits that should be cleared. //! -//! This function will clear the status of any bits that are passed in the +//! This function clears the status of any bits that are passed in the //! \e ulFlags parameter. The \e ulFlags parameter can take the value returned //! from the USBEndpointStatus() call. //! @@ -1199,8 +1196,8 @@ USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); // - // If this is endpoint 0 then the bits have different meaning and map into - // the TX memory location. + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. // if(ulEndpoint == USB_EP_0) { @@ -1352,13 +1349,13 @@ USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint, //***************************************************************************** // -//! Sets the Data toggle on an endpoint to zero. +//! Sets the data toggle on an endpoint to zero. //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint specifies the endpoint to reset the data toggle. //! \param ulFlags specifies whether to access the IN or OUT endpoint. //! -//! This function will cause the controller to clear the data toggle for an +//! This function causes the USB controller to clear the data toggle for an //! endpoint. This call is not valid for endpoint zero and can be made with //! host or device controllers. //! @@ -1408,10 +1405,10 @@ USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint specifies the endpoint to stall. //! \param ulFlags specifies whether to stall the IN or OUT endpoint. //! -//! This function will cause to endpoint number passed in to go into a stall -//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN, then the stall //! is issued on the IN portion of this endpoint. If the \e ulFlags parameter -//! is \b USB_EP_DEV_OUT then the stall is issued on the OUT portion of this +//! is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion of this //! endpoint. //! //! \note This function should only be called in device mode. @@ -1475,10 +1472,10 @@ USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies whether to remove the stall condition from the IN //! or the OUT portion of this endpoint. //! -//! This function will cause the endpoint number passed in to exit the stall -//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN, then the stall //! is cleared on the IN portion of this endpoint. If the \e ulFlags parameter -//! is \b USB_EP_DEV_OUT then the stall is cleared on the OUT portion of this +//! is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT portion of this //! endpoint. //! //! \note This function should only be called in device mode. @@ -1550,7 +1547,7 @@ USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! -//! This function will cause the soft connect feature of the USB controller to +//! This function causes the soft connect feature of the USB controller to //! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. //! //! \note This function should only be called in device mode. @@ -1578,7 +1575,7 @@ USBDevConnect(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function will cause the soft connect feature of the USB controller to +//! This function causes the soft connect feature of the USB controller to //! remove the device from the USB bus. A call to USBDevConnect() is needed to //! reconnect to the bus. //! @@ -1608,8 +1605,8 @@ USBDevDisconnect(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! \param ulAddress is the address to use for a device. //! -//! This function will set the device address on the USB bus. This address was -//! likely received via a SET ADDRESS command from the host controller. +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. //! //! \note This function should only be called in device mode. //! @@ -1636,7 +1633,7 @@ USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress) //! //! \param ulBase specifies the USB module base address. //! -//! This function will return the current device address. This address was set +//! This function returns the current device address. This address was set //! by a call to USBDevAddrSet(). //! //! \note This function should only be called in device mode. @@ -1666,18 +1663,19 @@ USBDevAddrGet(unsigned long ulBase) //! \param ulEndpoint is the endpoint to access. //! \param ulMaxPayload is the maximum payload for this endpoint. //! \param ulNAKPollInterval is the either the NAK timeout limit or the polling -//! interval depending on the type of endpoint. +//! interval, depending on the type of endpoint. //! \param ulTargetEndpoint is the endpoint that the host endpoint is //! targeting. //! \param ulFlags are used to configure other endpoint settings. //! -//! This function will set the basic configuration for the transmit or receive +//! This function sets the basic configuration for the transmit or receive //! portion of an endpoint in host mode. The \e ulFlags parameter determines //! some of the configuration while the other parameters provide the rest. The //! \e ulFlags parameter determines whether this is an IN endpoint -//! (USB_EP_HOST_IN or USB_EP_DEV_IN) or an OUT endpoint (USB_EP_HOST_OUT or -//! USB_EP_DEV_OUT), whether this is a Full speed endpoint (USB_EP_SPEED_FULL) -//! or a Low speed endpoint (USB_EP_SPEED_LOW). +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). //! //! The \b USB_EP_MODE_ flags control the type of the endpoint. //! - \b USB_EP_MODE_CTRL is a control endpoint. @@ -1693,18 +1691,18 @@ USBDevAddrGet(unsigned long ulBase) //! isochronous or interrupt endpoint, this value is the polling interval for //! this endpoint. //! -//! For interrupt endpoints the polling interval is simply the number of +//! For interrupt endpoints, the polling interval is simply the number of //! frames between polling an interrupt endpoint. For isochronous endpoints //! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1) //! frames. When used as a NAK timeout, the \e ulNAKPollInterval value //! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out. //! There are two special time out values that can be specified when setting -//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT which is the -//! maximum value that can be passed in this variable. The other is -//! \b DISABLE_NAK_LIMIT which indicates that there should be no limit on the +//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is +//! the maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT, which indicates that there should be no limit on the //! number of NAKs. //! -//! The \b USB_EP_DMA_MODE_ flags enables the type of DMA used to access the +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the //! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA //! controller is configured and how it is being used. See the ``Using USB //! with the uDMA Controller'' section for more information on DMA @@ -1712,15 +1710,15 @@ USBDevAddrGet(unsigned long ulBase) //! //! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit //! is specified to cause the transmission of data on the USB bus to start -//! as soon as the number of bytes specified by \e ulMaxPayload have been +//! as soon as the number of bytes specified by \e ulMaxPayload has been //! written into the OUT FIFO for this endpoint. //! //! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST //! bit can be specified to trigger the request for more data once the FIFO has //! been drained enough to fit \e ulMaxPayload bytes. The \b USB_EP_AUTO_CLEAR //! bit can be used to clear the data packet ready flag automatically once the -//! data has been read from the FIFO. If this is not used, this flag must be -//! manually cleared via a call to USBDevEndpointStatusClear() or +//! data has been read from the FIFO. If this option is not used, this flag +//! must be manually cleared via a call to USBDevEndpointStatusClear() or //! USBHostEndpointStatusClear(). //! //! \note This function should only be called in host mode. @@ -1942,9 +1940,9 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulMaxPacketSize is the maximum packet size for this endpoint. //! \param ulFlags are used to configure other endpoint settings. //! -//! This function will set the basic configuration for an endpoint in device -//! mode. Endpoint zero does not have a dynamic configuration, so this -//! function should not be called for endpoint zero. The \e ulFlags parameter +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! should not be called for endpoint zero. The \e ulFlags parameter //! determines some of the configuration while the other parameters provide the //! rest. //! @@ -1955,7 +1953,7 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! - \b USB_EP_MODE_BULK is a bulk endpoint. //! - \b USB_EP_MODE_INT is an interrupt endpoint. //! -//! The \b USB_EP_DMA_MODE_ flags determines the type of DMA access to the +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the //! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA //! controller is configured and how it is being used. See the ``Using USB //! with the uDMA Controller'' section for more information on DMA @@ -1964,7 +1962,7 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be //! specified to cause the automatic transmission of data on the USB bus as //! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for -//! this endpoint. This is commonly used with DMA as no interaction is +//! this endpoint. This option is commonly used with DMA as no interaction is //! required to start the transmission of data. //! //! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is @@ -1972,9 +1970,9 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, //! drained enough to receive \e ulMaxPacketSize more bytes of data. Also for //! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data //! packet ready flag automatically once the data has been read from the FIFO. -//! If this is not used, this flag must be manually cleared via a call to -//! USBDevEndpointStatusClear(). Both of these settings can be used to remove -//! the need for extra calls when using the controller in DMA mode. +//! If this option is not used, this flag must be manually cleared via a call +//! to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. //! //! \note This function should only be called in device mode. //! @@ -2126,7 +2124,7 @@ USBDevEndpointConfigSet(unsigned long ulBase, unsigned long ulEndpoint, //! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT //! endpoint is to be queried. //! -//! This function will return the basic configuration for an endpoint in device +//! This function returns the basic configuration for an endpoint in device //! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are //! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to //! USBDevEndpointConfigSet() for this endpoint. @@ -2216,9 +2214,9 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, // // The hardware doesn't differentiate between bulk, interrupt // and control mode for the endpoint so we just set something - // that isn't isochronous. This ensures that anyone modifying - // the returned flags in preparation for a call to - // USBDevEndpointConfigSet will not see an unexpected mode change. + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. // If they decode the returned mode, however, they may be in for // a surprise. // @@ -2281,9 +2279,9 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, // // The hardware doesn't differentiate between bulk, interrupt // and control mode for the endpoint so we just set something - // that isn't isochronous. This ensures that anyone modifying - // the returned flags in preparation for a call to - // USBDevEndpointConfigSet will not see an unexpected mode change. + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. // If they decode the returned mode, however, they may be in for // a surprise. // @@ -2303,24 +2301,24 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, //! USB_FIFO_SZ_ values. //! \param ulFlags specifies what information to set in the FIFO configuration. //! -//! This function will set the starting FIFO RAM address and size of the FIFO +//! This function configures the starting FIFO RAM address and size of the FIFO //! for a given endpoint. Endpoint zero does not have a dynamically -//! configurable FIFO so this function should not be called for endpoint zero. +//! configurable FIFO, so this function should not be called for endpoint zero. //! The \e ulFIFOSize parameter should be one of the values in the -//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering +//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering, //! it should use the values with the \b _DB at the end of the value. For -//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16 -//! byte double buffered FIFO. If a double buffered FIFO is used, then the +//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16- +//! byte, double-buffered FIFO. If a double-buffered FIFO is used, then the //! actual size of the FIFO is twice the size indicated by the \e ulFIFOSize -//! parameter. This means that the \b USB_FIFO_SZ_16_DB value will use 32 -//! bytes of the USB controller's FIFO memory. +//! parameter. For example, the \b USB_FIFO_SZ_16_DB value uses 32 bytes of +//! the USB controller's FIFO memory. //! //! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly //! indicates the starting address in the USB controller's FIFO RAM. For //! example, a value of 64 indicates that the FIFO should start 64 bytes into //! the USB controller's FIFO memory. The \e ulFlags value specifies whether //! the endpoint's OUT or IN FIFO should be configured. If in host mode, use -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use //! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. //! //! \return None. @@ -2379,12 +2377,12 @@ USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies what information to retrieve from the FIFO //! configuration. //! -//! This function will return the starting address and size of the FIFO for a +//! This function returns the starting address and size of the FIFO for a //! given endpoint. Endpoint zero does not have a dynamically configurable -//! FIFO so this function should not be called for endpoint zero. The +//! FIFO, so this function should not be called for endpoint zero. The //! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should //! be read. If in host mode, the \e ulFlags parameter should be -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode the +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the //! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or //! \b USB_EP_DEV_IN. //! @@ -2446,7 +2444,7 @@ USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies which direction and what mode to use when enabling //! DMA. //! -//! This function will enable DMA on a given endpoint and set the mode +//! This function enables DMA on a given endpoint and configures the mode //! according to the values in the \e ulFlags parameter. The \e ulFlags //! parameter should have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. //! @@ -2463,7 +2461,7 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, if(ulFlags & USB_EP_DEV_IN) { // - // Enable DMA on the transmit end point. + // Enable DMA on the transmit endpoint. // HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |= USB_TXCSRH1_DMAEN; @@ -2471,7 +2469,7 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, else { // - // Enable DMA on the receive end point. + // Enable DMA on the receive endpoint. // HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |= USB_RXCSRH1_DMAEN; @@ -2486,9 +2484,9 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulFlags specifies which direction to disable. //! -//! This function will disable DMA on a given end point to allow non-DMA -//! USB transactions to generate interrupts normally. The ulFlags should be -//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT all other bits are ignored. +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The ulFlags should be +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. //! //! \return None. // @@ -2498,7 +2496,7 @@ USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint, unsigned long ulFlags) { // - // If this was a request to disable DMA on the IN portion of the end point + // If this was a request to disable DMA on the IN portion of the endpoint // then handle it. // if(ulFlags & USB_EP_DEV_IN) @@ -2526,13 +2524,13 @@ USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will return the number of bytes of data currently available -//! in the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to //! calling USBEndpointDataGet() to determine the size of buffer required to //! hold the newly-received packet. //! -//! \return This call will return the number of bytes available in a given -//! endpoint FIFO. +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. // //***************************************************************************** unsigned long @@ -2592,15 +2590,15 @@ USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint) //! via the \e pucData parameter. It is set to the amount of data returned in //! the buffer. //! -//! This function will return the data from the FIFO for the given endpoint. +//! This function returns the data from the FIFO for the given endpoint. //! The \e pulSize parameter should indicate the size of the buffer passed in //! the \e pulData parameter. The data in the \e pulSize parameter is changed //! to match the amount of data returned in the \e pucData parameter. If a -//! zero byte packet was received this call will not return a error but will -//! instead just return a zero in the \e pulSize parameter. The only error +//! zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pulSize parameter. The only error //! case occurs when there is no data packet available. //! -//! \return This call will return 0, or -1 if no packet was received. +//! \return This call returns 0, or -1 if no packet was received. // //***************************************************************************** long @@ -2695,7 +2693,7 @@ USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint, //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. -//! \param bIsLastPacket indicates if this is the last packet. +//! \param bIsLastPacket indicates if this packet is the last one. //! //! This function acknowledges that the data was read from the endpoint's FIFO. //! The \e bIsLastPacket parameter is set to a \b true value if this is the @@ -2804,13 +2802,13 @@ USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint) //! data to put into the FIFO. //! \param ulSize is the amount of data to put into the FIFO. //! -//! This function will put the data from the \e pucData parameter into the FIFO -//! for this endpoint. If a packet is already pending for transmission then -//! this call will not put any of the data into the FIFO and will return -1. -//! Care should be taken to not write more data than can fit into the FIFO +//! This function puts the data from the \e pucData parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! should be taken to not write more data than can fit into the FIFO //! allocated by the call to USBFIFOConfigSet(). //! -//! \return This call will return 0 on success, or -1 to indicate that the FIFO +//! \return This call returns 0 on success, or -1 to indicate that the FIFO //! is in use and cannot be written. // //***************************************************************************** @@ -2881,21 +2879,21 @@ USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulTransType is set to indicate what type of data is being sent. //! -//! This function will start the transfer of data from the FIFO for a given -//! endpoint. This is necessary if the \b USB_EP_AUTO_SET bit was not enabled -//! for the endpoint. Setting the \e ulTransType parameter will allow the -//! appropriate signaling on the USB bus for the type of transaction being +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function should be called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ulTransType parameter allows +//! the appropriate signaling on the USB bus for the type of transaction being //! requested. The \e ulTransType parameter should be one of the following: //! -//! - USB_TRANS_OUT for OUT transaction on any endpoint in host mode. -//! - USB_TRANS_IN for IN transaction on any endpoint in device mode. -//! - USB_TRANS_IN_LAST for the last IN transactions on endpoint zero in a +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a //! sequence of IN transactions. -//! - USB_TRANS_SETUP for setup transactions on endpoint zero. -//! - USB_TRANS_STATUS for status results on endpoint zero. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. //! -//! \return This call will return 0 on success, or -1 if a transmission is -//! already in progress. +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. // //***************************************************************************** long @@ -2905,7 +2903,7 @@ USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, unsigned long ulTxPktRdy; // - // CHeck the arguments. + // Check the arguments. // ASSERT(ulBase == USB0_BASE); ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || @@ -2956,7 +2954,7 @@ USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulEndpoint is the endpoint to access. //! \param ulFlags specifies if the IN or OUT endpoint should be accessed. //! -//! This function will force the controller to flush out the data in the FIFO. +//! This function forces the USB controller to flush out the data in the FIFO. //! The function can be called with either host or device controllers and //! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT, //! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. @@ -3043,9 +3041,9 @@ USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will schedule a request for an IN transaction. When the USB -//! device being communicated with responds the data, the data can be retrieved -//! by calling USBEndpointDataGet() or via a DMA transfer. +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. //! //! \note This function should only be called in host mode and only for IN //! endpoints. @@ -3096,10 +3094,10 @@ USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint) //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! -//! This function will clear a previously scheduled IN transaction if it is +//! This function clears a previously scheduled IN transaction if it is //! still pending. This function should be used to safely disable any //! scheduled IN transactions if the endpoint specified by \e ulEndpoint -//! is reconfigured used for communications with other devices. +//! is reconfigured for communications with other devices. //! //! \note This function should only be called in host mode and only for IN //! endpoints. @@ -3149,11 +3147,12 @@ USBHostRequestINClear(unsigned long ulBase, unsigned long ulEndpoint) //! //! \param ulBase specifies the USB module base address. //! -//! This function is used to cause a request for an status IN transaction from +//! This function is used to cause a request for a status IN transaction from //! a device on endpoint zero. This function can only be used with endpoint //! zero as that is the only control endpoint that supports this ability. This -//! is used to complete the last phase of a control transaction to a device and -//! an interrupt is signaled when the status packet has been received. +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. //! //! \return None. // @@ -3183,9 +3182,9 @@ USBHostRequestStatus(unsigned long ulBase) //! endpoint. //! \param ulFlags determines if this is an IN or an OUT endpoint. //! -//! This function will set the functional address for a device that is using +//! This function configures the functional address for a device that is using //! this endpoint for communication. This \e ulAddr parameter is the address -//! of the target device that this endpoint is used to communicate with. The +//! of the target device that this endpoint is communicating with. The //! \e ulFlags parameter indicates if the IN or OUT endpoint should be set. //! //! \note This function should only be called in host mode. @@ -3284,7 +3283,7 @@ USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //***************************************************************************** // -//! Set the hub address for the device that is connected to an endpoint. +//! Sets the hub address for the device that is connected to an endpoint. //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. @@ -3293,10 +3292,10 @@ USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! port number in bits 0 through 6. //! \param ulFlags determines if this is an IN or an OUT endpoint. //! -//! This function will set the hub address for a device that is using this +//! This function configures the hub address for a device that is using this //! endpoint for communication. The \e ulFlags parameter determines if the -//! device address for the IN or the OUT endpoint is set by this call and sets -//! the speed of the downstream device. Valid values are one of \b +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of \b //! USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with \b //! USB_EP_SPEED_LOW. //! @@ -3341,9 +3340,9 @@ USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, } // - // Set the speed of communication for endpoint 0. This is done here since - // it will change on a transaction-by-transaction basis for EP0. For other - // endpoints, this is set in USBHostEndpointConfig(). + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). // if(ulEndpoint == USB_EP_0) { @@ -3360,13 +3359,13 @@ USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, //***************************************************************************** // -//! Get the current device hub address for this endpoint. +//! Gets the current device hub address for this endpoint. //! //! \param ulBase specifies the USB module base address. //! \param ulEndpoint is the endpoint to access. //! \param ulFlags determines if this is an IN or an OUT endpoint. //! -//! This function will return the current hub address that an endpoint is using +//! This function returns the current hub address that an endpoint is using //! to communicate with a device. The \e ulFlags parameter determines if the //! device address for the IN or OUT endpoint is returned. //! @@ -3420,7 +3419,7 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! \param ulFlags specifies the configuration of the power fault. //! //! This function controls how the USB controller uses its external power -//! control pins (USBnPFTL and USBnEPEN). The flags specify the power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power //! fault level sensitivity, the power fault action, and the power enable level //! and source. //! @@ -3435,7 +3434,7 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! //! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault //! detected. -//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBnEPEN pin on a +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a //! power fault. //! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a //! power fault. @@ -3444,21 +3443,23 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! //! One of the following can be selected as the power enable level and source: //! -//! - \b USB_HOST_PWREN_MAN_LOW - USBEPEN is driven low by the USB controller +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller //! when USBHostPwrEnable() is called. -//! - \b USB_HOST_PWREN_MAN_HIGH - USBEPEN is driven high by the USB controller -//! when USBHostPwrEnable() is called. -//! - \b USB_HOST_PWREN_AUTOLOW - USBEPEN is driven low by the USB controller +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller //! automatically if USBOTGSessionRequest() has //! enabled a session. -//! - \b USB_HOST_PWREN_AUTOHIGH - USBEPEN is driven high by the USB controller -//! automatically if USBOTGSessionRequest() has -//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. //! //! On devices that support the VBUS glitch filter, the //! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS -//! level caused by high power consumption. This is mainly used to avoid -//! causing VBUS errors caused by devices with high in-rush current. +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. //! //! \note The following values have been deprecated and should no longer be //! used. @@ -3468,8 +3469,8 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, //! enabled. //! - \b USB_HOST_PWREN_VBLOW - Automatically drive USBnEPEN low when power is //! enabled. -//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power is -//! enabled. +//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power +//! is enabled. //! //! \note This function should only be called on microcontrollers that support //! host mode or OTG operation. @@ -3495,8 +3496,8 @@ USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags) HWREG(ulBase + USB_O_VDC) = ulFlags >> 16; // - // Set the power fault configuration as specified. This will not change - // whether fault detection is enabled or not. + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. // HWREGH(ulBase + USB_O_EPC) = (ulFlags | (HWREGH(ulBase + USB_O_EPC) & @@ -3511,7 +3512,7 @@ USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags) //! \param ulBase specifies the USB module base address. //! //! This function enables power fault detection in the USB controller. If the -//! USBPFLT pin is not in use this function should not be used. +//! USBnPFLT pin is not in use, this function should not be used. //! //! \note This function should only be called in host mode. //! @@ -3565,8 +3566,8 @@ USBHostPwrFaultDisable(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function enables the USBEPEN signal to enable an external power supply -//! in host mode operation. +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. //! //! \note This function should only be called in host mode. //! @@ -3593,8 +3594,8 @@ USBHostPwrEnable(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function disables the USBEPEN signal to disable an external power -//! supply in host mode operation. +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. //! //! \note This function should only be called in host mode. //! @@ -3649,7 +3650,7 @@ USBFrameNumberGet(unsigned long ulBase) //! //! This function is used in OTG mode to start a session request or end a //! session. If the \e bStart parameter is set to \b true, then this function -//! start a session and if it is \b false it will end a session. +//! starts a session and if it is \b false it ends a session. //! //! \return None. // @@ -3682,10 +3683,10 @@ USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart) //! \param ulBase specifies the USB module base address. //! \param ulEndpoint specifies which endpoint's FIFO address to return. //! -//! This function returns the actual physical address of the FIFO. This is -//! needed when the USB is going to be used with the uDMA controller and the -//! source or destination address needs to be set to the physical FIFO address -//! for a given endpoint. +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. //! //! \return None. // @@ -3710,7 +3711,7 @@ USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint) //! //! For OTG controllers: //! -//! The function will return on of the following values on OTG controllers: +//! The function returns one of the following values on OTG controllers: //! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, //! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, //! \b USB_OTG_MODE_NONE. @@ -3725,15 +3726,15 @@ USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint) //! on the B-side of the cable. //! //! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode -//! on the B-side of the cable. If and OTG session request is started with no -//! cable in place this is the default mode for the controller. +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. //! //! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to //! determine its role in the system. //! //! For Dual Mode controllers: //! -//! The function will return on of the following values: +//! The function returns one of the following values: //! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or //! \b USB_DUAL_MODE_NONE. //! @@ -3784,14 +3785,14 @@ USBModeGet(unsigned long ulBase) //! //! This function is used to configure which DMA channel to use with a given //! endpoint. Receive DMA channels can only be used with receive endpoints -//! and transmit DMA channels can only be used with transmit endpoints. This -//! allows the 3 receive and 3 transmit DMA channels to be mapped to any +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any //! endpoint other than 0. The values that should be passed into the //! \e ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. //! //! \note This function only has an effect on microcontrollers that have the //! ability to change the DMA channel for an endpoint. Calling this function -//! on other devices will have no effect. +//! on other devices has no effect. //! //! \return None. //! @@ -3817,7 +3818,7 @@ USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX); // - // The input select mask needs to be shifted into the correct position + // The input select mask must be shifted into the correct position // based on the channel. // ulMask = 0xf << (ulChannel * 4); @@ -3847,6 +3848,9 @@ USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, //! //! This function changes the mode of the USB controller to host mode. //! +//! \note This function should only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! //! \return None. // //***************************************************************************** @@ -3875,6 +3879,9 @@ USBHostMode(unsigned long ulBase) //! //! This function changes the mode of the USB controller to device mode. //! +//! \note This function should only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! //! \return None. // //***************************************************************************** @@ -3899,7 +3906,7 @@ USBDevMode(unsigned long ulBase) //! \param ulBase specifies the USB module base address. //! //! This function changes the mode of the USB controller to OTG mode. This -//! is only valid on microcontrollers that have the OTG capabilities. +//! function is only valid on microcontrollers that have the OTG capabilities. //! //! \return None. // @@ -3925,8 +3932,8 @@ USBOTGMode(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function will power off the USB PHY, reducing the current consuption -//! of the device. While in the powered off state, the USB controller is +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is //! unable to operate. //! //! \return None. @@ -3947,9 +3954,9 @@ USBPHYPowerOff(unsigned long ulBase) //! //! \param ulBase specifies the USB module base address. //! -//! This function will power on the USB PHY, enabling it return to normal -//! operation. By default, the PHY is powered on, so this function only needs -//! to be called if USBPHYPowerOff() has previously been called. +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function should +//! only be called if USBPHYPowerOff() has previously been called. //! //! \return None. // @@ -3964,6 +3971,7 @@ USBPHYPowerOn(unsigned long ulBase) HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; } + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/lm4f232/Libraries/driverlib/usb.h b/bsp/lm4f232/Libraries/driverlib/usb.h index b57af1c309..66a94d0876 100644 --- a/bsp/lm4f232/Libraries/driverlib/usb.h +++ b/bsp/lm4f232/Libraries/driverlib/usb.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/driverlib/watchdog.c b/bsp/lm4f232/Libraries/driverlib/watchdog.c index 8a72f68254..b3961c9494 100644 --- a/bsp/lm4f232/Libraries/driverlib/watchdog.c +++ b/bsp/lm4f232/Libraries/driverlib/watchdog.c @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** @@ -43,9 +43,9 @@ //! //! \param ulBase is the base address of the watchdog timer module. //! -//! This will check to see if the watchdog timer is enabled. +//! This function checks to see if the watchdog timer is enabled. //! -//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! \return Returns \b true if the watchdog timer is enabled and \b false //! if it is not. // //***************************************************************************** @@ -69,10 +69,9 @@ WatchdogRunning(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! This will enable the watchdog timer counter and interrupt. +//! This function enables the watchdog timer counter and interrupt. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock() //! @@ -99,12 +98,11 @@ WatchdogEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Enables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. //! +//! \note This function has no effect if the watchdog timer has been locked. +//! //! \sa WatchdogLock(), WatchdogUnlock() //! //! \return None. @@ -130,11 +128,10 @@ WatchdogResetEnable(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Disables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock() //! @@ -161,7 +158,8 @@ WatchdogResetDisable(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Locks out write access to the watchdog timer configuration registers. +//! This function locks out write access to the watchdog timer configuration +//! registers. //! //! \return None. // @@ -187,7 +185,8 @@ WatchdogLock(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Enables write access to the watchdog timer configuration registers. +//! This function enables write access to the watchdog timer configuration +//! registers. //! //! \return None. // @@ -212,7 +211,7 @@ WatchdogUnlock(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Returns the lock state of the watchdog timer registers. +//! This function returns the lock state of the watchdog timer registers. //! //! \return Returns \b true if the watchdog timer registers are locked, and //! \b false if they are not locked. @@ -239,14 +238,13 @@ WatchdogLockState(unsigned long ulBase) //! \param ulBase is the base address of the watchdog timer module. //! \param ulLoadVal is the load value for the watchdog timer. //! -//! This function sets the value to load into the watchdog timer when the count -//! reaches zero for the first time; if the watchdog timer is running when this -//! function is called, then the value is immediately loaded into the watchdog -//! timer counter. If the \e ulLoadVal parameter is 0, then an interrupt is -//! immediately generated. +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an +//! interrupt is immediately generated. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() //! @@ -322,25 +320,25 @@ WatchdogValueGet(unsigned long ulBase) //***************************************************************************** // -//! Registers an interrupt handler for watchdog timer interrupt. +//! Registers an interrupt handler for the watchdog timer interrupt. //! //! \param ulBase is the base address of the watchdog timer module. //! \param pfnHandler is a pointer to the function to be called when the //! watchdog timer interrupt occurs. //! //! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; the watchdog -//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via +//! function also enables the global interrupt in the interrupt controller; the +//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via //! WatchdogIntClear(). //! //! \sa IntRegister() for important information about registering interrupt //! handlers. //! //! \note For parts with a watchdog timer module that has the ability to -//! generate an NMI instead of a standard interrupt, this function will -//! register the standard watchdog interrupt handler. To register the NMI -//! watchdog handler, use IntRegister() to register the handler for the +//! generate an NMI instead of a standard interrupt, this function registers +//! the standard watchdog interrupt handler. To register the NMI watchdog +//! handler, use IntRegister() to register the handler for the //! \b FAULT_NMI interrupt. //! //! \return None. @@ -372,17 +370,17 @@ WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) //! \param ulBase is the base address of the watchdog timer module. //! //! This function does the actual unregistering of the interrupt handler. This -//! function will clear the handler to be called when a watchdog timer -//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt //! controller so that the interrupt handler no longer is called. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. //! //! \note For parts with a watchdog timer module that has the ability to -//! generate an NMI instead of a standard interrupt, this function will -//! unregister the standard watchdog interrupt handler. To unregister the NMI -//! watchdog handler, use IntUnregister() to unregister the handler for the +//! generate an NMI instead of a standard interrupt, this function unregisters +//! the standard watchdog interrupt handler. To unregister the NMI watchdog +//! handler, use IntUnregister() to unregister the handler for the //! \b FAULT_NMI interrupt. //! //! \return None. @@ -413,10 +411,9 @@ WatchdogIntUnregister(unsigned long ulBase) //! //! \param ulBase is the base address of the watchdog timer module. //! -//! Enables the watchdog timer interrupt. +//! This function enables the watchdog timer interrupt. //! -//! \note This function will have no effect if the watchdog timer has -//! been locked. +//! \note This function has no effect if the watchdog timer has been locked. //! //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() //! @@ -445,9 +442,9 @@ WatchdogIntEnable(unsigned long ulBase) //! \param bMasked is \b false if the raw interrupt status is required and //! \b true if the masked interrupt status is required. //! -//! This returns the interrupt status for the watchdog timer module. Either -//! the raw interrupt status or the status of interrupt that is allowed to -//! reflect to the processor can be returned. +//! This function returns the interrupt status for the watchdog timer module. +//! Either the raw interrupt status or the status of interrupt that is allowed +//! to reflect to the processor can be returned. //! //! \return Returns the current interrupt status, where a 1 indicates that the //! watchdog interrupt is active, and a 0 indicates that it is not active. @@ -484,7 +481,7 @@ WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) //! The watchdog timer interrupt source is cleared, so that it no longer //! asserts. //! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! \note Because there is a write buffer in the Cortex-M processor, it may //! take several clock cycles before the interrupt source is actually cleared. //! Therefore, it is recommended that the interrupt source be cleared early in //! the interrupt handler (as opposed to the very last action) to avoid @@ -559,9 +556,9 @@ WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType) //! This function allows the watchdog timer to stop counting when the processor //! is stopped by the debugger. By doing so, the watchdog is prevented from //! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog will instead -//! expired after the appropriate number of processor cycles have been executed -//! while debugging (or at the appropriate time after the processor has been +//! resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been //! restarted). //! //! \return None. diff --git a/bsp/lm4f232/Libraries/driverlib/watchdog.h b/bsp/lm4f232/Libraries/driverlib/watchdog.h index ca159a70b4..5efdcdbb23 100644 --- a/bsp/lm4f232/Libraries/driverlib/watchdog.h +++ b/bsp/lm4f232/Libraries/driverlib/watchdog.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Peripheral Driver Library. +// This is part of revision 8264 of the Stellaris Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/asmdefs.h b/bsp/lm4f232/Libraries/inc/asmdefs.h index 38fe4b7484..cc9b5ef2f4 100644 --- a/bsp/lm4f232/Libraries/inc/asmdefs.h +++ b/bsp/lm4f232/Libraries/inc/asmdefs.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/cr_project.xml b/bsp/lm4f232/Libraries/inc/cr_project.xml deleted file mode 100644 index 7ba1836aeb..0000000000 --- a/bsp/lm4f232/Libraries/inc/cr_project.xml +++ /dev/null @@ -1,27 +0,0 @@ - - - - - {.*\.(ewd|ewp|eww|icf|Opt|sct|sgxx|Uv2|uvopt|uvproj|cmd)} - - diff --git a/bsp/lm4f232/Libraries/inc/hw_adc.h b/bsp/lm4f232/Libraries/inc/hw_adc.h index 332a23842f..4e02573cf8 100644 --- a/bsp/lm4f232/Libraries/inc/hw_adc.h +++ b/bsp/lm4f232/Libraries/inc/hw_adc.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_can.h b/bsp/lm4f232/Libraries/inc/hw_can.h index 8f608ae7e0..c1b3ae9a7c 100644 --- a/bsp/lm4f232/Libraries/inc/hw_can.h +++ b/bsp/lm4f232/Libraries/inc/hw_can.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_comp.h b/bsp/lm4f232/Libraries/inc/hw_comp.h index 234d57da4f..18e3b8262a 100644 --- a/bsp/lm4f232/Libraries/inc/hw_comp.h +++ b/bsp/lm4f232/Libraries/inc/hw_comp.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_eeprom.h b/bsp/lm4f232/Libraries/inc/hw_eeprom.h index 67a59c026a..6428bdecc8 100644 --- a/bsp/lm4f232/Libraries/inc/hw_eeprom.h +++ b/bsp/lm4f232/Libraries/inc/hw_eeprom.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_epi.h b/bsp/lm4f232/Libraries/inc/hw_epi.h index a34dabafd7..ab7d076ca2 100644 --- a/bsp/lm4f232/Libraries/inc/hw_epi.h +++ b/bsp/lm4f232/Libraries/inc/hw_epi.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_ethernet.h b/bsp/lm4f232/Libraries/inc/hw_ethernet.h index 6461772ebd..91da8867c1 100644 --- a/bsp/lm4f232/Libraries/inc/hw_ethernet.h +++ b/bsp/lm4f232/Libraries/inc/hw_ethernet.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_fan.h b/bsp/lm4f232/Libraries/inc/hw_fan.h index 6df7067e59..22f9f05553 100644 --- a/bsp/lm4f232/Libraries/inc/hw_fan.h +++ b/bsp/lm4f232/Libraries/inc/hw_fan.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_flash.h b/bsp/lm4f232/Libraries/inc/hw_flash.h index 2a72db116a..7a8c0697b3 100644 --- a/bsp/lm4f232/Libraries/inc/hw_flash.h +++ b/bsp/lm4f232/Libraries/inc/hw_flash.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_gpio.h b/bsp/lm4f232/Libraries/inc/hw_gpio.h index abeeeb4d3a..b2eaa072d9 100644 --- a/bsp/lm4f232/Libraries/inc/hw_gpio.h +++ b/bsp/lm4f232/Libraries/inc/hw_gpio.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_hibernate.h b/bsp/lm4f232/Libraries/inc/hw_hibernate.h index 37a76db3fc..46de994bc5 100644 --- a/bsp/lm4f232/Libraries/inc/hw_hibernate.h +++ b/bsp/lm4f232/Libraries/inc/hw_hibernate.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_i2c.h b/bsp/lm4f232/Libraries/inc/hw_i2c.h index ebeb9205b2..dccfdafada 100644 --- a/bsp/lm4f232/Libraries/inc/hw_i2c.h +++ b/bsp/lm4f232/Libraries/inc/hw_i2c.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_i2s.h b/bsp/lm4f232/Libraries/inc/hw_i2s.h index e0ba3d40c7..d139a79834 100644 --- a/bsp/lm4f232/Libraries/inc/hw_i2s.h +++ b/bsp/lm4f232/Libraries/inc/hw_i2s.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_ints.h b/bsp/lm4f232/Libraries/inc/hw_ints.h index 3d45969978..e2becd15b8 100644 --- a/bsp/lm4f232/Libraries/inc/hw_ints.h +++ b/bsp/lm4f232/Libraries/inc/hw_ints.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_lpc.h b/bsp/lm4f232/Libraries/inc/hw_lpc.h index 28bad99536..d39523f069 100644 --- a/bsp/lm4f232/Libraries/inc/hw_lpc.h +++ b/bsp/lm4f232/Libraries/inc/hw_lpc.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_memmap.h b/bsp/lm4f232/Libraries/inc/hw_memmap.h index af71904e48..1a50ad9f2b 100644 --- a/bsp/lm4f232/Libraries/inc/hw_memmap.h +++ b/bsp/lm4f232/Libraries/inc/hw_memmap.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_nvic.h b/bsp/lm4f232/Libraries/inc/hw_nvic.h index 1fa6c0206e..cdb06304b8 100644 --- a/bsp/lm4f232/Libraries/inc/hw_nvic.h +++ b/bsp/lm4f232/Libraries/inc/hw_nvic.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_peci.h b/bsp/lm4f232/Libraries/inc/hw_peci.h index f4d12059b1..012a0c821e 100644 --- a/bsp/lm4f232/Libraries/inc/hw_peci.h +++ b/bsp/lm4f232/Libraries/inc/hw_peci.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_pwm.h b/bsp/lm4f232/Libraries/inc/hw_pwm.h index 268aaf3140..82d55e9198 100644 --- a/bsp/lm4f232/Libraries/inc/hw_pwm.h +++ b/bsp/lm4f232/Libraries/inc/hw_pwm.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_qei.h b/bsp/lm4f232/Libraries/inc/hw_qei.h index 7d08aeede8..0348852ffe 100644 --- a/bsp/lm4f232/Libraries/inc/hw_qei.h +++ b/bsp/lm4f232/Libraries/inc/hw_qei.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_ssi.h b/bsp/lm4f232/Libraries/inc/hw_ssi.h index dd946bfe93..40be6a6de3 100644 --- a/bsp/lm4f232/Libraries/inc/hw_ssi.h +++ b/bsp/lm4f232/Libraries/inc/hw_ssi.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_sysctl.h b/bsp/lm4f232/Libraries/inc/hw_sysctl.h index 4cdd345f16..34ae0b5f21 100644 --- a/bsp/lm4f232/Libraries/inc/hw_sysctl.h +++ b/bsp/lm4f232/Libraries/inc/hw_sysctl.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_sysexc.h b/bsp/lm4f232/Libraries/inc/hw_sysexc.h index 4b5a9648d4..4dce20dec3 100644 --- a/bsp/lm4f232/Libraries/inc/hw_sysexc.h +++ b/bsp/lm4f232/Libraries/inc/hw_sysexc.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_timer.h b/bsp/lm4f232/Libraries/inc/hw_timer.h index 68ecad9809..b1d35979a8 100644 --- a/bsp/lm4f232/Libraries/inc/hw_timer.h +++ b/bsp/lm4f232/Libraries/inc/hw_timer.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_types.h b/bsp/lm4f232/Libraries/inc/hw_types.h index ab96c422e9..f08046f45a 100644 --- a/bsp/lm4f232/Libraries/inc/hw_types.h +++ b/bsp/lm4f232/Libraries/inc/hw_types.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_uart.h b/bsp/lm4f232/Libraries/inc/hw_uart.h index 0bacfa31b3..daf55d1312 100644 --- a/bsp/lm4f232/Libraries/inc/hw_uart.h +++ b/bsp/lm4f232/Libraries/inc/hw_uart.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_udma.h b/bsp/lm4f232/Libraries/inc/hw_udma.h index 11f14a83de..59466e6eca 100644 --- a/bsp/lm4f232/Libraries/inc/hw_udma.h +++ b/bsp/lm4f232/Libraries/inc/hw_udma.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_usb.h b/bsp/lm4f232/Libraries/inc/hw_usb.h index 763f9243bc..abee8349bc 100644 --- a/bsp/lm4f232/Libraries/inc/hw_usb.h +++ b/bsp/lm4f232/Libraries/inc/hw_usb.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/hw_watchdog.h b/bsp/lm4f232/Libraries/inc/hw_watchdog.h index 7fca54f31d..d00c90240d 100644 --- a/bsp/lm4f232/Libraries/inc/hw_watchdog.h +++ b/bsp/lm4f232/Libraries/inc/hw_watchdog.h @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 8049 of the Stellaris Firmware Development Package. +// This is part of revision 8264 of the Stellaris Firmware Development Package. // //***************************************************************************** diff --git a/bsp/lm4f232/Libraries/inc/lm4f232h5qd.h b/bsp/lm4f232/Libraries/inc/lm4f232h5qd.h deleted file mode 100644 index 1728f3ee56..0000000000 --- a/bsp/lm4f232/Libraries/inc/lm4f232h5qd.h +++ /dev/null @@ -1,12986 +0,0 @@ -//***************************************************************************** -// -// lm4f232h5qd.h - LM4F232H5QD Register Definitions -// -// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 8049 of the Stellaris Firmware Development Package. -// -//***************************************************************************** - -#ifndef __LM4F232H5QD_H__ -#define __LM4F232H5QD_H__ - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG0) -// -//***************************************************************************** -#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000)) -#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004)) -#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008)) -#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C)) -#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010)) -#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014)) -#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418)) -#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00)) - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG1) -// -//***************************************************************************** -#define WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000)) -#define WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004)) -#define WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008)) -#define WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C)) -#define WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010)) -#define WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014)) -#define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418)) -#define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00)) - -//***************************************************************************** -// -// GPIO registers (PORTA) -// -//***************************************************************************** -#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000) -#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC)) -#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400)) -#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404)) -#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408)) -#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C)) -#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410)) -#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414)) -#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418)) -#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C)) -#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420)) -#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500)) -#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504)) -#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508)) -#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C)) -#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510)) -#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514)) -#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518)) -#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C)) -#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520)) -#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524)) -#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528)) -#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C)) -#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530)) -#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534)) -#define GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538)) - -//***************************************************************************** -// -// GPIO registers (PORTB) -// -//***************************************************************************** -#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000) -#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC)) -#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400)) -#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404)) -#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408)) -#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C)) -#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410)) -#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414)) -#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418)) -#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C)) -#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420)) -#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500)) -#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504)) -#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508)) -#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C)) -#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510)) -#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514)) -#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518)) -#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C)) -#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520)) -#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524)) -#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528)) -#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C)) -#define GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530)) -#define GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534)) -#define GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538)) - -//***************************************************************************** -// -// GPIO registers (PORTC) -// -//***************************************************************************** -#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000) -#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC)) -#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400)) -#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404)) -#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408)) -#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C)) -#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410)) -#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414)) -#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418)) -#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C)) -#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420)) -#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500)) -#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504)) -#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508)) -#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C)) -#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510)) -#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514)) -#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518)) -#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C)) -#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520)) -#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524)) -#define GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528)) -#define GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C)) -#define GPIO_PORTC_ADCCTL_R (*((volatile unsigned long *)0x40006530)) -#define GPIO_PORTC_DMACTL_R (*((volatile unsigned long *)0x40006534)) -#define GPIO_PORTC_SI_R (*((volatile unsigned long *)0x40006538)) - -//***************************************************************************** -// -// GPIO registers (PORTD) -// -//***************************************************************************** -#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000) -#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC)) -#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400)) -#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404)) -#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408)) -#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C)) -#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410)) -#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414)) -#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418)) -#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C)) -#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420)) -#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500)) -#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504)) -#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508)) -#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C)) -#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510)) -#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514)) -#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518)) -#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C)) -#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520)) -#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524)) -#define GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528)) -#define GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C)) -#define GPIO_PORTD_ADCCTL_R (*((volatile unsigned long *)0x40007530)) -#define GPIO_PORTD_DMACTL_R (*((volatile unsigned long *)0x40007534)) -#define GPIO_PORTD_SI_R (*((volatile unsigned long *)0x40007538)) - -//***************************************************************************** -// -// SSI registers (SSI0) -// -//***************************************************************************** -#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000)) -#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004)) -#define SSI0_DR_R (*((volatile unsigned long *)0x40008008)) -#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C)) -#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010)) -#define SSI0_IM_R (*((volatile unsigned long *)0x40008014)) -#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018)) -#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C)) -#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020)) -#define SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024)) -#define SSI0_CC_R (*((volatile unsigned long *)0x40008FC8)) - -//***************************************************************************** -// -// SSI registers (SSI1) -// -//***************************************************************************** -#define SSI1_CR0_R (*((volatile unsigned long *)0x40009000)) -#define SSI1_CR1_R (*((volatile unsigned long *)0x40009004)) -#define SSI1_DR_R (*((volatile unsigned long *)0x40009008)) -#define SSI1_SR_R (*((volatile unsigned long *)0x4000900C)) -#define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010)) -#define SSI1_IM_R (*((volatile unsigned long *)0x40009014)) -#define SSI1_RIS_R (*((volatile unsigned long *)0x40009018)) -#define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C)) -#define SSI1_ICR_R (*((volatile unsigned long *)0x40009020)) -#define SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024)) -#define SSI1_CC_R (*((volatile unsigned long *)0x40009FC8)) - -//***************************************************************************** -// -// SSI registers (SSI2) -// -//***************************************************************************** -#define SSI2_CR0_R (*((volatile unsigned long *)0x4000A000)) -#define SSI2_CR1_R (*((volatile unsigned long *)0x4000A004)) -#define SSI2_DR_R (*((volatile unsigned long *)0x4000A008)) -#define SSI2_SR_R (*((volatile unsigned long *)0x4000A00C)) -#define SSI2_CPSR_R (*((volatile unsigned long *)0x4000A010)) -#define SSI2_IM_R (*((volatile unsigned long *)0x4000A014)) -#define SSI2_RIS_R (*((volatile unsigned long *)0x4000A018)) -#define SSI2_MIS_R (*((volatile unsigned long *)0x4000A01C)) -#define SSI2_ICR_R (*((volatile unsigned long *)0x4000A020)) -#define SSI2_DMACTL_R (*((volatile unsigned long *)0x4000A024)) -#define SSI2_CC_R (*((volatile unsigned long *)0x4000AFC8)) - -//***************************************************************************** -// -// SSI registers (SSI3) -// -//***************************************************************************** -#define SSI3_CR0_R (*((volatile unsigned long *)0x4000B000)) -#define SSI3_CR1_R (*((volatile unsigned long *)0x4000B004)) -#define SSI3_DR_R (*((volatile unsigned long *)0x4000B008)) -#define SSI3_SR_R (*((volatile unsigned long *)0x4000B00C)) -#define SSI3_CPSR_R (*((volatile unsigned long *)0x4000B010)) -#define SSI3_IM_R (*((volatile unsigned long *)0x4000B014)) -#define SSI3_RIS_R (*((volatile unsigned long *)0x4000B018)) -#define SSI3_MIS_R (*((volatile unsigned long *)0x4000B01C)) -#define SSI3_ICR_R (*((volatile unsigned long *)0x4000B020)) -#define SSI3_DMACTL_R (*((volatile unsigned long *)0x4000B024)) -#define SSI3_CC_R (*((volatile unsigned long *)0x4000BFC8)) - -//***************************************************************************** -// -// UART registers (UART0) -// -//***************************************************************************** -#define UART0_DR_R (*((volatile unsigned long *)0x4000C000)) -#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004)) -#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004)) -#define UART0_FR_R (*((volatile unsigned long *)0x4000C018)) -#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020)) -#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024)) -#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028)) -#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C)) -#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030)) -#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034)) -#define UART0_IM_R (*((volatile unsigned long *)0x4000C038)) -#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C)) -#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040)) -#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044)) -#define UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048)) -#define UART0_LCTL_R (*((volatile unsigned long *)0x4000C090)) -#define UART0_LSS_R (*((volatile unsigned long *)0x4000C094)) -#define UART0_LTIM_R (*((volatile unsigned long *)0x4000C098)) -#define UART0_9BITADDR_R (*((volatile unsigned long *)0x4000C0A4)) -#define UART0_9BITAMASK_R (*((volatile unsigned long *)0x4000C0A8)) -#define UART0_PP_R (*((volatile unsigned long *)0x4000CFC0)) -#define UART0_CC_R (*((volatile unsigned long *)0x4000CFC8)) - -//***************************************************************************** -// -// UART registers (UART1) -// -//***************************************************************************** -#define UART1_DR_R (*((volatile unsigned long *)0x4000D000)) -#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004)) -#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004)) -#define UART1_FR_R (*((volatile unsigned long *)0x4000D018)) -#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020)) -#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024)) -#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028)) -#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C)) -#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030)) -#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034)) -#define UART1_IM_R (*((volatile unsigned long *)0x4000D038)) -#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C)) -#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040)) -#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044)) -#define UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048)) -#define UART1_LCTL_R (*((volatile unsigned long *)0x4000D090)) -#define UART1_LSS_R (*((volatile unsigned long *)0x4000D094)) -#define UART1_LTIM_R (*((volatile unsigned long *)0x4000D098)) -#define UART1_9BITADDR_R (*((volatile unsigned long *)0x4000D0A4)) -#define UART1_9BITAMASK_R (*((volatile unsigned long *)0x4000D0A8)) -#define UART1_PP_R (*((volatile unsigned long *)0x4000DFC0)) -#define UART1_CC_R (*((volatile unsigned long *)0x4000DFC8)) - -//***************************************************************************** -// -// UART registers (UART2) -// -//***************************************************************************** -#define UART2_DR_R (*((volatile unsigned long *)0x4000E000)) -#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004)) -#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004)) -#define UART2_FR_R (*((volatile unsigned long *)0x4000E018)) -#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020)) -#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024)) -#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028)) -#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C)) -#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030)) -#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034)) -#define UART2_IM_R (*((volatile unsigned long *)0x4000E038)) -#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C)) -#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040)) -#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044)) -#define UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048)) -#define UART2_LCTL_R (*((volatile unsigned long *)0x4000E090)) -#define UART2_LSS_R (*((volatile unsigned long *)0x4000E094)) -#define UART2_LTIM_R (*((volatile unsigned long *)0x4000E098)) -#define UART2_9BITADDR_R (*((volatile unsigned long *)0x4000E0A4)) -#define UART2_9BITAMASK_R (*((volatile unsigned long *)0x4000E0A8)) -#define UART2_PP_R (*((volatile unsigned long *)0x4000EFC0)) -#define UART2_CC_R (*((volatile unsigned long *)0x4000EFC8)) - -//***************************************************************************** -// -// UART registers (UART3) -// -//***************************************************************************** -#define UART3_DR_R (*((volatile unsigned long *)0x4000F000)) -#define UART3_RSR_R (*((volatile unsigned long *)0x4000F004)) -#define UART3_ECR_R (*((volatile unsigned long *)0x4000F004)) -#define UART3_FR_R (*((volatile unsigned long *)0x4000F018)) -#define UART3_ILPR_R (*((volatile unsigned long *)0x4000F020)) -#define UART3_IBRD_R (*((volatile unsigned long *)0x4000F024)) -#define UART3_FBRD_R (*((volatile unsigned long *)0x4000F028)) -#define UART3_LCRH_R (*((volatile unsigned long *)0x4000F02C)) -#define UART3_CTL_R (*((volatile unsigned long *)0x4000F030)) -#define UART3_IFLS_R (*((volatile unsigned long *)0x4000F034)) -#define UART3_IM_R (*((volatile unsigned long *)0x4000F038)) -#define UART3_RIS_R (*((volatile unsigned long *)0x4000F03C)) -#define UART3_MIS_R (*((volatile unsigned long *)0x4000F040)) -#define UART3_ICR_R (*((volatile unsigned long *)0x4000F044)) -#define UART3_DMACTL_R (*((volatile unsigned long *)0x4000F048)) -#define UART3_LCTL_R (*((volatile unsigned long *)0x4000F090)) -#define UART3_LSS_R (*((volatile unsigned long *)0x4000F094)) -#define UART3_LTIM_R (*((volatile unsigned long *)0x4000F098)) -#define UART3_9BITADDR_R (*((volatile unsigned long *)0x4000F0A4)) -#define UART3_9BITAMASK_R (*((volatile unsigned long *)0x4000F0A8)) -#define UART3_PP_R (*((volatile unsigned long *)0x4000FFC0)) -#define UART3_CC_R (*((volatile unsigned long *)0x4000FFC8)) - -//***************************************************************************** -// -// UART registers (UART4) -// -//***************************************************************************** -#define UART4_DR_R (*((volatile unsigned long *)0x40010000)) -#define UART4_RSR_R (*((volatile unsigned long *)0x40010004)) -#define UART4_ECR_R (*((volatile unsigned long *)0x40010004)) -#define UART4_FR_R (*((volatile unsigned long *)0x40010018)) -#define UART4_ILPR_R (*((volatile unsigned long *)0x40010020)) -#define UART4_IBRD_R (*((volatile unsigned long *)0x40010024)) -#define UART4_FBRD_R (*((volatile unsigned long *)0x40010028)) -#define UART4_LCRH_R (*((volatile unsigned long *)0x4001002C)) -#define UART4_CTL_R (*((volatile unsigned long *)0x40010030)) -#define UART4_IFLS_R (*((volatile unsigned long *)0x40010034)) -#define UART4_IM_R (*((volatile unsigned long *)0x40010038)) -#define UART4_RIS_R (*((volatile unsigned long *)0x4001003C)) -#define UART4_MIS_R (*((volatile unsigned long *)0x40010040)) -#define UART4_ICR_R (*((volatile unsigned long *)0x40010044)) -#define UART4_DMACTL_R (*((volatile unsigned long *)0x40010048)) -#define UART4_LCTL_R (*((volatile unsigned long *)0x40010090)) -#define UART4_LSS_R (*((volatile unsigned long *)0x40010094)) -#define UART4_LTIM_R (*((volatile unsigned long *)0x40010098)) -#define UART4_9BITADDR_R (*((volatile unsigned long *)0x400100A4)) -#define UART4_9BITAMASK_R (*((volatile unsigned long *)0x400100A8)) -#define UART4_PP_R (*((volatile unsigned long *)0x40010FC0)) -#define UART4_CC_R (*((volatile unsigned long *)0x40010FC8)) - -//***************************************************************************** -// -// UART registers (UART5) -// -//***************************************************************************** -#define UART5_DR_R (*((volatile unsigned long *)0x40011000)) -#define UART5_RSR_R (*((volatile unsigned long *)0x40011004)) -#define UART5_ECR_R (*((volatile unsigned long *)0x40011004)) -#define UART5_FR_R (*((volatile unsigned long *)0x40011018)) -#define UART5_ILPR_R (*((volatile unsigned long *)0x40011020)) -#define UART5_IBRD_R (*((volatile unsigned long *)0x40011024)) -#define UART5_FBRD_R (*((volatile unsigned long *)0x40011028)) -#define UART5_LCRH_R (*((volatile unsigned long *)0x4001102C)) -#define UART5_CTL_R (*((volatile unsigned long *)0x40011030)) -#define UART5_IFLS_R (*((volatile unsigned long *)0x40011034)) -#define UART5_IM_R (*((volatile unsigned long *)0x40011038)) -#define UART5_RIS_R (*((volatile unsigned long *)0x4001103C)) -#define UART5_MIS_R (*((volatile unsigned long *)0x40011040)) -#define UART5_ICR_R (*((volatile unsigned long *)0x40011044)) -#define UART5_DMACTL_R (*((volatile unsigned long *)0x40011048)) -#define UART5_LCTL_R (*((volatile unsigned long *)0x40011090)) -#define UART5_LSS_R (*((volatile unsigned long *)0x40011094)) -#define UART5_LTIM_R (*((volatile unsigned long *)0x40011098)) -#define UART5_9BITADDR_R (*((volatile unsigned long *)0x400110A4)) -#define UART5_9BITAMASK_R (*((volatile unsigned long *)0x400110A8)) -#define UART5_PP_R (*((volatile unsigned long *)0x40011FC0)) -#define UART5_CC_R (*((volatile unsigned long *)0x40011FC8)) - -//***************************************************************************** -// -// UART registers (UART6) -// -//***************************************************************************** -#define UART6_DR_R (*((volatile unsigned long *)0x40012000)) -#define UART6_RSR_R (*((volatile unsigned long *)0x40012004)) -#define UART6_ECR_R (*((volatile unsigned long *)0x40012004)) -#define UART6_FR_R (*((volatile unsigned long *)0x40012018)) -#define UART6_ILPR_R (*((volatile unsigned long *)0x40012020)) -#define UART6_IBRD_R (*((volatile unsigned long *)0x40012024)) -#define UART6_FBRD_R (*((volatile unsigned long *)0x40012028)) -#define UART6_LCRH_R (*((volatile unsigned long *)0x4001202C)) -#define UART6_CTL_R (*((volatile unsigned long *)0x40012030)) -#define UART6_IFLS_R (*((volatile unsigned long *)0x40012034)) -#define UART6_IM_R (*((volatile unsigned long *)0x40012038)) -#define UART6_RIS_R (*((volatile unsigned long *)0x4001203C)) -#define UART6_MIS_R (*((volatile unsigned long *)0x40012040)) -#define UART6_ICR_R (*((volatile unsigned long *)0x40012044)) -#define UART6_DMACTL_R (*((volatile unsigned long *)0x40012048)) -#define UART6_LCTL_R (*((volatile unsigned long *)0x40012090)) -#define UART6_LSS_R (*((volatile unsigned long *)0x40012094)) -#define UART6_LTIM_R (*((volatile unsigned long *)0x40012098)) -#define UART6_9BITADDR_R (*((volatile unsigned long *)0x400120A4)) -#define UART6_9BITAMASK_R (*((volatile unsigned long *)0x400120A8)) -#define UART6_PP_R (*((volatile unsigned long *)0x40012FC0)) -#define UART6_CC_R (*((volatile unsigned long *)0x40012FC8)) - -//***************************************************************************** -// -// UART registers (UART7) -// -//***************************************************************************** -#define UART7_DR_R (*((volatile unsigned long *)0x40013000)) -#define UART7_RSR_R (*((volatile unsigned long *)0x40013004)) -#define UART7_ECR_R (*((volatile unsigned long *)0x40013004)) -#define UART7_FR_R (*((volatile unsigned long *)0x40013018)) -#define UART7_ILPR_R (*((volatile unsigned long *)0x40013020)) -#define UART7_IBRD_R (*((volatile unsigned long *)0x40013024)) -#define UART7_FBRD_R (*((volatile unsigned long *)0x40013028)) -#define UART7_LCRH_R (*((volatile unsigned long *)0x4001302C)) -#define UART7_CTL_R (*((volatile unsigned long *)0x40013030)) -#define UART7_IFLS_R (*((volatile unsigned long *)0x40013034)) -#define UART7_IM_R (*((volatile unsigned long *)0x40013038)) -#define UART7_RIS_R (*((volatile unsigned long *)0x4001303C)) -#define UART7_MIS_R (*((volatile unsigned long *)0x40013040)) -#define UART7_ICR_R (*((volatile unsigned long *)0x40013044)) -#define UART7_DMACTL_R (*((volatile unsigned long *)0x40013048)) -#define UART7_LCTL_R (*((volatile unsigned long *)0x40013090)) -#define UART7_LSS_R (*((volatile unsigned long *)0x40013094)) -#define UART7_LTIM_R (*((volatile unsigned long *)0x40013098)) -#define UART7_9BITADDR_R (*((volatile unsigned long *)0x400130A4)) -#define UART7_9BITAMASK_R (*((volatile unsigned long *)0x400130A8)) -#define UART7_PP_R (*((volatile unsigned long *)0x40013FC0)) -#define UART7_CC_R (*((volatile unsigned long *)0x40013FC8)) - -//***************************************************************************** -// -// I2C registers (I2C0 MASTER) -// -//***************************************************************************** -#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000)) -#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004)) -#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008)) -#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C)) -#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010)) -#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014)) -#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018)) -#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C)) -#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020)) -#define I2C0_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40020024)) -#define I2C0_MASTER_MBMON_R (*((volatile unsigned long *)0x4002002C)) - -//***************************************************************************** -// -// I2C registers (I2C0 SLAVE) -// -//***************************************************************************** -#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800)) -#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804)) -#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808)) -#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C)) -#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810)) -#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814)) -#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818)) -#define I2C0_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002081C)) -#define I2C0_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40020820)) - -//***************************************************************************** -// -// I2C registers (I2C1 MASTER) -// -//***************************************************************************** -#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000)) -#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004)) -#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008)) -#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C)) -#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010)) -#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014)) -#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018)) -#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C)) -#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020)) -#define I2C1_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40021024)) -#define I2C1_MASTER_MBMON_R (*((volatile unsigned long *)0x4002102C)) - -//***************************************************************************** -// -// I2C registers (I2C1 SLAVE) -// -//***************************************************************************** -#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800)) -#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804)) -#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808)) -#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C)) -#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810)) -#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814)) -#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818)) -#define I2C1_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002181C)) -#define I2C1_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40021820)) - -//***************************************************************************** -// -// I2C registers (I2C2 MASTER) -// -//***************************************************************************** -#define I2C2_MASTER_MSA_R (*((volatile unsigned long *)0x40022000)) -#define I2C2_MASTER_MCS_R (*((volatile unsigned long *)0x40022004)) -#define I2C2_MASTER_MDR_R (*((volatile unsigned long *)0x40022008)) -#define I2C2_MASTER_MTPR_R (*((volatile unsigned long *)0x4002200C)) -#define I2C2_MASTER_MIMR_R (*((volatile unsigned long *)0x40022010)) -#define I2C2_MASTER_MRIS_R (*((volatile unsigned long *)0x40022014)) -#define I2C2_MASTER_MMIS_R (*((volatile unsigned long *)0x40022018)) -#define I2C2_MASTER_MICR_R (*((volatile unsigned long *)0x4002201C)) -#define I2C2_MASTER_MCR_R (*((volatile unsigned long *)0x40022020)) -#define I2C2_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40022024)) -#define I2C2_MASTER_MBMON_R (*((volatile unsigned long *)0x4002202C)) - -//***************************************************************************** -// -// I2C registers (I2C2 SLAVE) -// -//***************************************************************************** -#define I2C2_SLAVE_SOAR_R (*((volatile unsigned long *)0x40022800)) -#define I2C2_SLAVE_SCSR_R (*((volatile unsigned long *)0x40022804)) -#define I2C2_SLAVE_SDR_R (*((volatile unsigned long *)0x40022808)) -#define I2C2_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002280C)) -#define I2C2_SLAVE_SRIS_R (*((volatile unsigned long *)0x40022810)) -#define I2C2_SLAVE_SMIS_R (*((volatile unsigned long *)0x40022814)) -#define I2C2_SLAVE_SICR_R (*((volatile unsigned long *)0x40022818)) -#define I2C2_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002281C)) -#define I2C2_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40022820)) - -//***************************************************************************** -// -// I2C registers (I2C3 MASTER) -// -//***************************************************************************** -#define I2C3_MASTER_MSA_R (*((volatile unsigned long *)0x40023000)) -#define I2C3_MASTER_MCS_R (*((volatile unsigned long *)0x40023004)) -#define I2C3_MASTER_MDR_R (*((volatile unsigned long *)0x40023008)) -#define I2C3_MASTER_MTPR_R (*((volatile unsigned long *)0x4002300C)) -#define I2C3_MASTER_MIMR_R (*((volatile unsigned long *)0x40023010)) -#define I2C3_MASTER_MRIS_R (*((volatile unsigned long *)0x40023014)) -#define I2C3_MASTER_MMIS_R (*((volatile unsigned long *)0x40023018)) -#define I2C3_MASTER_MICR_R (*((volatile unsigned long *)0x4002301C)) -#define I2C3_MASTER_MCR_R (*((volatile unsigned long *)0x40023020)) -#define I2C3_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40023024)) -#define I2C3_MASTER_MBMON_R (*((volatile unsigned long *)0x4002302C)) - -//***************************************************************************** -// -// I2C registers (I2C3 SLAVE) -// -//***************************************************************************** -#define I2C3_SLAVE_SOAR_R (*((volatile unsigned long *)0x40023800)) -#define I2C3_SLAVE_SCSR_R (*((volatile unsigned long *)0x40023804)) -#define I2C3_SLAVE_SDR_R (*((volatile unsigned long *)0x40023808)) -#define I2C3_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002380C)) -#define I2C3_SLAVE_SRIS_R (*((volatile unsigned long *)0x40023810)) -#define I2C3_SLAVE_SMIS_R (*((volatile unsigned long *)0x40023814)) -#define I2C3_SLAVE_SICR_R (*((volatile unsigned long *)0x40023818)) -#define I2C3_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002381C)) -#define I2C3_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40023820)) - -//***************************************************************************** -// -// GPIO registers (PORTE) -// -//***************************************************************************** -#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000) -#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC)) -#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400)) -#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404)) -#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408)) -#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C)) -#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410)) -#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414)) -#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418)) -#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C)) -#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420)) -#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500)) -#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504)) -#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508)) -#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C)) -#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510)) -#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514)) -#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518)) -#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C)) -#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520)) -#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524)) -#define GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528)) -#define GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C)) -#define GPIO_PORTE_ADCCTL_R (*((volatile unsigned long *)0x40024530)) -#define GPIO_PORTE_DMACTL_R (*((volatile unsigned long *)0x40024534)) -#define GPIO_PORTE_SI_R (*((volatile unsigned long *)0x40024538)) - -//***************************************************************************** -// -// GPIO registers (PORTF) -// -//***************************************************************************** -#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000) -#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC)) -#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400)) -#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404)) -#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408)) -#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C)) -#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410)) -#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414)) -#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418)) -#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C)) -#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420)) -#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500)) -#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504)) -#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508)) -#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C)) -#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510)) -#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514)) -#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518)) -#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C)) -#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520)) -#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524)) -#define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528)) -#define GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C)) -#define GPIO_PORTF_ADCCTL_R (*((volatile unsigned long *)0x40025530)) -#define GPIO_PORTF_DMACTL_R (*((volatile unsigned long *)0x40025534)) -#define GPIO_PORTF_SI_R (*((volatile unsigned long *)0x40025538)) - -//***************************************************************************** -// -// GPIO registers (PORTG) -// -//***************************************************************************** -#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000) -#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC)) -#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400)) -#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404)) -#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408)) -#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C)) -#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410)) -#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414)) -#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418)) -#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C)) -#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420)) -#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500)) -#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504)) -#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508)) -#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C)) -#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510)) -#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514)) -#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518)) -#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C)) -#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520)) -#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524)) -#define GPIO_PORTG_AMSEL_R (*((volatile unsigned long *)0x40026528)) -#define GPIO_PORTG_PCTL_R (*((volatile unsigned long *)0x4002652C)) -#define GPIO_PORTG_ADCCTL_R (*((volatile unsigned long *)0x40026530)) -#define GPIO_PORTG_DMACTL_R (*((volatile unsigned long *)0x40026534)) -#define GPIO_PORTG_SI_R (*((volatile unsigned long *)0x40026538)) - -//***************************************************************************** -// -// GPIO registers (PORTH) -// -//***************************************************************************** -#define GPIO_PORTH_DATA_BITS_R ((volatile unsigned long *)0x40027000) -#define GPIO_PORTH_DATA_R (*((volatile unsigned long *)0x400273FC)) -#define GPIO_PORTH_DIR_R (*((volatile unsigned long *)0x40027400)) -#define GPIO_PORTH_IS_R (*((volatile unsigned long *)0x40027404)) -#define GPIO_PORTH_IBE_R (*((volatile unsigned long *)0x40027408)) -#define GPIO_PORTH_IEV_R (*((volatile unsigned long *)0x4002740C)) -#define GPIO_PORTH_IM_R (*((volatile unsigned long *)0x40027410)) -#define GPIO_PORTH_RIS_R (*((volatile unsigned long *)0x40027414)) -#define GPIO_PORTH_MIS_R (*((volatile unsigned long *)0x40027418)) -#define GPIO_PORTH_ICR_R (*((volatile unsigned long *)0x4002741C)) -#define GPIO_PORTH_AFSEL_R (*((volatile unsigned long *)0x40027420)) -#define GPIO_PORTH_DR2R_R (*((volatile unsigned long *)0x40027500)) -#define GPIO_PORTH_DR4R_R (*((volatile unsigned long *)0x40027504)) -#define GPIO_PORTH_DR8R_R (*((volatile unsigned long *)0x40027508)) -#define GPIO_PORTH_ODR_R (*((volatile unsigned long *)0x4002750C)) -#define GPIO_PORTH_PUR_R (*((volatile unsigned long *)0x40027510)) -#define GPIO_PORTH_PDR_R (*((volatile unsigned long *)0x40027514)) -#define GPIO_PORTH_SLR_R (*((volatile unsigned long *)0x40027518)) -#define GPIO_PORTH_DEN_R (*((volatile unsigned long *)0x4002751C)) -#define GPIO_PORTH_LOCK_R (*((volatile unsigned long *)0x40027520)) -#define GPIO_PORTH_CR_R (*((volatile unsigned long *)0x40027524)) -#define GPIO_PORTH_AMSEL_R (*((volatile unsigned long *)0x40027528)) -#define GPIO_PORTH_PCTL_R (*((volatile unsigned long *)0x4002752C)) -#define GPIO_PORTH_ADCCTL_R (*((volatile unsigned long *)0x40027530)) -#define GPIO_PORTH_DMACTL_R (*((volatile unsigned long *)0x40027534)) -#define GPIO_PORTH_SI_R (*((volatile unsigned long *)0x40027538)) - -//***************************************************************************** -// -// PWM registers (PWM0) -// -//***************************************************************************** -#define PWM0_CTL_R (*((volatile unsigned long *)0x40028000)) -#define PWM0_SYNC_R (*((volatile unsigned long *)0x40028004)) -#define PWM0_ENABLE_R (*((volatile unsigned long *)0x40028008)) -#define PWM0_INVERT_R (*((volatile unsigned long *)0x4002800C)) -#define PWM0_FAULT_R (*((volatile unsigned long *)0x40028010)) -#define PWM0_INTEN_R (*((volatile unsigned long *)0x40028014)) -#define PWM0_RIS_R (*((volatile unsigned long *)0x40028018)) -#define PWM0_ISC_R (*((volatile unsigned long *)0x4002801C)) -#define PWM0_STATUS_R (*((volatile unsigned long *)0x40028020)) -#define PWM0_FAULTVAL_R (*((volatile unsigned long *)0x40028024)) -#define PWM0_ENUPD_R (*((volatile unsigned long *)0x40028028)) -#define PWM0_0_CTL_R (*((volatile unsigned long *)0x40028040)) -#define PWM0_0_INTEN_R (*((volatile unsigned long *)0x40028044)) -#define PWM0_0_RIS_R (*((volatile unsigned long *)0x40028048)) -#define PWM0_0_ISC_R (*((volatile unsigned long *)0x4002804C)) -#define PWM0_0_LOAD_R (*((volatile unsigned long *)0x40028050)) -#define PWM0_0_COUNT_R (*((volatile unsigned long *)0x40028054)) -#define PWM0_0_CMPA_R (*((volatile unsigned long *)0x40028058)) -#define PWM0_0_CMPB_R (*((volatile unsigned long *)0x4002805C)) -#define PWM0_0_GENA_R (*((volatile unsigned long *)0x40028060)) -#define PWM0_0_GENB_R (*((volatile unsigned long *)0x40028064)) -#define PWM0_0_DBCTL_R (*((volatile unsigned long *)0x40028068)) -#define PWM0_0_DBRISE_R (*((volatile unsigned long *)0x4002806C)) -#define PWM0_0_DBFALL_R (*((volatile unsigned long *)0x40028070)) -#define PWM0_0_FLTSRC0_R (*((volatile unsigned long *)0x40028074)) -#define PWM0_0_FLTSRC1_R (*((volatile unsigned long *)0x40028078)) -#define PWM0_0_MINFLTPER_R (*((volatile unsigned long *)0x4002807C)) -#define PWM0_1_CTL_R (*((volatile unsigned long *)0x40028080)) -#define PWM0_1_INTEN_R (*((volatile unsigned long *)0x40028084)) -#define PWM0_1_RIS_R (*((volatile unsigned long *)0x40028088)) -#define PWM0_1_ISC_R (*((volatile unsigned long *)0x4002808C)) -#define PWM0_1_LOAD_R (*((volatile unsigned long *)0x40028090)) -#define PWM0_1_COUNT_R (*((volatile unsigned long *)0x40028094)) -#define PWM0_1_CMPA_R (*((volatile unsigned long *)0x40028098)) -#define PWM0_1_CMPB_R (*((volatile unsigned long *)0x4002809C)) -#define PWM0_1_GENA_R (*((volatile unsigned long *)0x400280A0)) -#define PWM0_1_GENB_R (*((volatile unsigned long *)0x400280A4)) -#define PWM0_1_DBCTL_R (*((volatile unsigned long *)0x400280A8)) -#define PWM0_1_DBRISE_R (*((volatile unsigned long *)0x400280AC)) -#define PWM0_1_DBFALL_R (*((volatile unsigned long *)0x400280B0)) -#define PWM0_1_FLTSRC0_R (*((volatile unsigned long *)0x400280B4)) -#define PWM0_1_FLTSRC1_R (*((volatile unsigned long *)0x400280B8)) -#define PWM0_1_MINFLTPER_R (*((volatile unsigned long *)0x400280BC)) -#define PWM0_2_CTL_R (*((volatile unsigned long *)0x400280C0)) -#define PWM0_2_INTEN_R (*((volatile unsigned long *)0x400280C4)) -#define PWM0_2_RIS_R (*((volatile unsigned long *)0x400280C8)) -#define PWM0_2_ISC_R (*((volatile unsigned long *)0x400280CC)) -#define PWM0_2_LOAD_R (*((volatile unsigned long *)0x400280D0)) -#define PWM0_2_COUNT_R (*((volatile unsigned long *)0x400280D4)) -#define PWM0_2_CMPA_R (*((volatile unsigned long *)0x400280D8)) -#define PWM0_2_CMPB_R (*((volatile unsigned long *)0x400280DC)) -#define PWM0_2_GENA_R (*((volatile unsigned long *)0x400280E0)) -#define PWM0_2_GENB_R (*((volatile unsigned long *)0x400280E4)) -#define PWM0_2_DBCTL_R (*((volatile unsigned long *)0x400280E8)) -#define PWM0_2_DBRISE_R (*((volatile unsigned long *)0x400280EC)) -#define PWM0_2_DBFALL_R (*((volatile unsigned long *)0x400280F0)) -#define PWM0_2_FLTSRC0_R (*((volatile unsigned long *)0x400280F4)) -#define PWM0_2_FLTSRC1_R (*((volatile unsigned long *)0x400280F8)) -#define PWM0_2_MINFLTPER_R (*((volatile unsigned long *)0x400280FC)) -#define PWM0_3_CTL_R (*((volatile unsigned long *)0x40028100)) -#define PWM0_3_INTEN_R (*((volatile unsigned long *)0x40028104)) -#define PWM0_3_RIS_R (*((volatile unsigned long *)0x40028108)) -#define PWM0_3_ISC_R (*((volatile unsigned long *)0x4002810C)) -#define PWM0_3_LOAD_R (*((volatile unsigned long *)0x40028110)) -#define PWM0_3_COUNT_R (*((volatile unsigned long *)0x40028114)) -#define PWM0_3_CMPA_R (*((volatile unsigned long *)0x40028118)) -#define PWM0_3_CMPB_R (*((volatile unsigned long *)0x4002811C)) -#define PWM0_3_GENA_R (*((volatile unsigned long *)0x40028120)) -#define PWM0_3_GENB_R (*((volatile unsigned long *)0x40028124)) -#define PWM0_3_DBCTL_R (*((volatile unsigned long *)0x40028128)) -#define PWM0_3_DBRISE_R (*((volatile unsigned long *)0x4002812C)) -#define PWM0_3_DBFALL_R (*((volatile unsigned long *)0x40028130)) -#define PWM0_3_FLTSRC0_R (*((volatile unsigned long *)0x40028134)) -#define PWM0_3_FLTSRC1_R (*((volatile unsigned long *)0x40028138)) -#define PWM0_3_MINFLTPER_R (*((volatile unsigned long *)0x4002813C)) -#define PWM0_0_FLTSEN_R (*((volatile unsigned long *)0x40028800)) -#define PWM0_0_FLTSTAT0_R (*((volatile unsigned long *)0x40028804)) -#define PWM0_0_FLTSTAT1_R (*((volatile unsigned long *)0x40028808)) -#define PWM0_1_FLTSEN_R (*((volatile unsigned long *)0x40028880)) -#define PWM0_1_FLTSTAT0_R (*((volatile unsigned long *)0x40028884)) -#define PWM0_1_FLTSTAT1_R (*((volatile unsigned long *)0x40028888)) -#define PWM0_2_FLTSEN_R (*((volatile unsigned long *)0x40028900)) -#define PWM0_2_FLTSTAT0_R (*((volatile unsigned long *)0x40028904)) -#define PWM0_2_FLTSTAT1_R (*((volatile unsigned long *)0x40028908)) -#define PWM0_3_FLTSEN_R (*((volatile unsigned long *)0x40028980)) -#define PWM0_3_FLTSTAT0_R (*((volatile unsigned long *)0x40028984)) -#define PWM0_3_FLTSTAT1_R (*((volatile unsigned long *)0x40028988)) -#define PWM0_PP_R (*((volatile unsigned long *)0x40028FC0)) -#define PWM0_PC_R (*((volatile unsigned long *)0x40028FC4)) - -//***************************************************************************** -// -// PWM registers (PWM1) -// -//***************************************************************************** -#define PWM1_CTL_R (*((volatile unsigned long *)0x40029000)) -#define PWM1_SYNC_R (*((volatile unsigned long *)0x40029004)) -#define PWM1_ENABLE_R (*((volatile unsigned long *)0x40029008)) -#define PWM1_INVERT_R (*((volatile unsigned long *)0x4002900C)) -#define PWM1_FAULT_R (*((volatile unsigned long *)0x40029010)) -#define PWM1_INTEN_R (*((volatile unsigned long *)0x40029014)) -#define PWM1_RIS_R (*((volatile unsigned long *)0x40029018)) -#define PWM1_ISC_R (*((volatile unsigned long *)0x4002901C)) -#define PWM1_STATUS_R (*((volatile unsigned long *)0x40029020)) -#define PWM1_FAULTVAL_R (*((volatile unsigned long *)0x40029024)) -#define PWM1_ENUPD_R (*((volatile unsigned long *)0x40029028)) -#define PWM1_0_CTL_R (*((volatile unsigned long *)0x40029040)) -#define PWM1_0_INTEN_R (*((volatile unsigned long *)0x40029044)) -#define PWM1_0_RIS_R (*((volatile unsigned long *)0x40029048)) -#define PWM1_0_ISC_R (*((volatile unsigned long *)0x4002904C)) -#define PWM1_0_LOAD_R (*((volatile unsigned long *)0x40029050)) -#define PWM1_0_COUNT_R (*((volatile unsigned long *)0x40029054)) -#define PWM1_0_CMPA_R (*((volatile unsigned long *)0x40029058)) -#define PWM1_0_CMPB_R (*((volatile unsigned long *)0x4002905C)) -#define PWM1_0_GENA_R (*((volatile unsigned long *)0x40029060)) -#define PWM1_0_GENB_R (*((volatile unsigned long *)0x40029064)) -#define PWM1_0_DBCTL_R (*((volatile unsigned long *)0x40029068)) -#define PWM1_0_DBRISE_R (*((volatile unsigned long *)0x4002906C)) -#define PWM1_0_DBFALL_R (*((volatile unsigned long *)0x40029070)) -#define PWM1_0_FLTSRC0_R (*((volatile unsigned long *)0x40029074)) -#define PWM1_0_FLTSRC1_R (*((volatile unsigned long *)0x40029078)) -#define PWM1_0_MINFLTPER_R (*((volatile unsigned long *)0x4002907C)) -#define PWM1_1_CTL_R (*((volatile unsigned long *)0x40029080)) -#define PWM1_1_INTEN_R (*((volatile unsigned long *)0x40029084)) -#define PWM1_1_RIS_R (*((volatile unsigned long *)0x40029088)) -#define PWM1_1_ISC_R (*((volatile unsigned long *)0x4002908C)) -#define PWM1_1_LOAD_R (*((volatile unsigned long *)0x40029090)) -#define PWM1_1_COUNT_R (*((volatile unsigned long *)0x40029094)) -#define PWM1_1_CMPA_R (*((volatile unsigned long *)0x40029098)) -#define PWM1_1_CMPB_R (*((volatile unsigned long *)0x4002909C)) -#define PWM1_1_GENA_R (*((volatile unsigned long *)0x400290A0)) -#define PWM1_1_GENB_R (*((volatile unsigned long *)0x400290A4)) -#define PWM1_1_DBCTL_R (*((volatile unsigned long *)0x400290A8)) -#define PWM1_1_DBRISE_R (*((volatile unsigned long *)0x400290AC)) -#define PWM1_1_DBFALL_R (*((volatile unsigned long *)0x400290B0)) -#define PWM1_1_FLTSRC0_R (*((volatile unsigned long *)0x400290B4)) -#define PWM1_1_FLTSRC1_R (*((volatile unsigned long *)0x400290B8)) -#define PWM1_1_MINFLTPER_R (*((volatile unsigned long *)0x400290BC)) -#define PWM1_2_CTL_R (*((volatile unsigned long *)0x400290C0)) -#define PWM1_2_INTEN_R (*((volatile unsigned long *)0x400290C4)) -#define PWM1_2_RIS_R (*((volatile unsigned long *)0x400290C8)) -#define PWM1_2_ISC_R (*((volatile unsigned long *)0x400290CC)) -#define PWM1_2_LOAD_R (*((volatile unsigned long *)0x400290D0)) -#define PWM1_2_COUNT_R (*((volatile unsigned long *)0x400290D4)) -#define PWM1_2_CMPA_R (*((volatile unsigned long *)0x400290D8)) -#define PWM1_2_CMPB_R (*((volatile unsigned long *)0x400290DC)) -#define PWM1_2_GENA_R (*((volatile unsigned long *)0x400290E0)) -#define PWM1_2_GENB_R (*((volatile unsigned long *)0x400290E4)) -#define PWM1_2_DBCTL_R (*((volatile unsigned long *)0x400290E8)) -#define PWM1_2_DBRISE_R (*((volatile unsigned long *)0x400290EC)) -#define PWM1_2_DBFALL_R (*((volatile unsigned long *)0x400290F0)) -#define PWM1_2_FLTSRC0_R (*((volatile unsigned long *)0x400290F4)) -#define PWM1_2_FLTSRC1_R (*((volatile unsigned long *)0x400290F8)) -#define PWM1_2_MINFLTPER_R (*((volatile unsigned long *)0x400290FC)) -#define PWM1_3_CTL_R (*((volatile unsigned long *)0x40029100)) -#define PWM1_3_INTEN_R (*((volatile unsigned long *)0x40029104)) -#define PWM1_3_RIS_R (*((volatile unsigned long *)0x40029108)) -#define PWM1_3_ISC_R (*((volatile unsigned long *)0x4002910C)) -#define PWM1_3_LOAD_R (*((volatile unsigned long *)0x40029110)) -#define PWM1_3_COUNT_R (*((volatile unsigned long *)0x40029114)) -#define PWM1_3_CMPA_R (*((volatile unsigned long *)0x40029118)) -#define PWM1_3_CMPB_R (*((volatile unsigned long *)0x4002911C)) -#define PWM1_3_GENA_R (*((volatile unsigned long *)0x40029120)) -#define PWM1_3_GENB_R (*((volatile unsigned long *)0x40029124)) -#define PWM1_3_DBCTL_R (*((volatile unsigned long *)0x40029128)) -#define PWM1_3_DBRISE_R (*((volatile unsigned long *)0x4002912C)) -#define PWM1_3_DBFALL_R (*((volatile unsigned long *)0x40029130)) -#define PWM1_3_FLTSRC0_R (*((volatile unsigned long *)0x40029134)) -#define PWM1_3_FLTSRC1_R (*((volatile unsigned long *)0x40029138)) -#define PWM1_3_MINFLTPER_R (*((volatile unsigned long *)0x4002913C)) -#define PWM1_0_FLTSEN_R (*((volatile unsigned long *)0x40029800)) -#define PWM1_0_FLTSTAT0_R (*((volatile unsigned long *)0x40029804)) -#define PWM1_0_FLTSTAT1_R (*((volatile unsigned long *)0x40029808)) -#define PWM1_1_FLTSEN_R (*((volatile unsigned long *)0x40029880)) -#define PWM1_1_FLTSTAT0_R (*((volatile unsigned long *)0x40029884)) -#define PWM1_1_FLTSTAT1_R (*((volatile unsigned long *)0x40029888)) -#define PWM1_2_FLTSEN_R (*((volatile unsigned long *)0x40029900)) -#define PWM1_2_FLTSTAT0_R (*((volatile unsigned long *)0x40029904)) -#define PWM1_2_FLTSTAT1_R (*((volatile unsigned long *)0x40029908)) -#define PWM1_3_FLTSEN_R (*((volatile unsigned long *)0x40029980)) -#define PWM1_3_FLTSTAT0_R (*((volatile unsigned long *)0x40029984)) -#define PWM1_3_FLTSTAT1_R (*((volatile unsigned long *)0x40029988)) -#define PWM1_PP_R (*((volatile unsigned long *)0x40029FC0)) -#define PWM1_PC_R (*((volatile unsigned long *)0x40029FC4)) - -//***************************************************************************** -// -// QEI registers (QEI0) -// -//***************************************************************************** -#define QEI0_CTL_R (*((volatile unsigned long *)0x4002C000)) -#define QEI0_STAT_R (*((volatile unsigned long *)0x4002C004)) -#define QEI0_POS_R (*((volatile unsigned long *)0x4002C008)) -#define QEI0_MAXPOS_R (*((volatile unsigned long *)0x4002C00C)) -#define QEI0_LOAD_R (*((volatile unsigned long *)0x4002C010)) -#define QEI0_TIME_R (*((volatile unsigned long *)0x4002C014)) -#define QEI0_COUNT_R (*((volatile unsigned long *)0x4002C018)) -#define QEI0_SPEED_R (*((volatile unsigned long *)0x4002C01C)) -#define QEI0_INTEN_R (*((volatile unsigned long *)0x4002C020)) -#define QEI0_RIS_R (*((volatile unsigned long *)0x4002C024)) -#define QEI0_ISC_R (*((volatile unsigned long *)0x4002C028)) - -//***************************************************************************** -// -// QEI registers (QEI1) -// -//***************************************************************************** -#define QEI1_CTL_R (*((volatile unsigned long *)0x4002D000)) -#define QEI1_STAT_R (*((volatile unsigned long *)0x4002D004)) -#define QEI1_POS_R (*((volatile unsigned long *)0x4002D008)) -#define QEI1_MAXPOS_R (*((volatile unsigned long *)0x4002D00C)) -#define QEI1_LOAD_R (*((volatile unsigned long *)0x4002D010)) -#define QEI1_TIME_R (*((volatile unsigned long *)0x4002D014)) -#define QEI1_COUNT_R (*((volatile unsigned long *)0x4002D018)) -#define QEI1_SPEED_R (*((volatile unsigned long *)0x4002D01C)) -#define QEI1_INTEN_R (*((volatile unsigned long *)0x4002D020)) -#define QEI1_RIS_R (*((volatile unsigned long *)0x4002D024)) -#define QEI1_ISC_R (*((volatile unsigned long *)0x4002D028)) - -//***************************************************************************** -// -// Timer registers (TIMER0) -// -//***************************************************************************** -#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000)) -#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004)) -#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008)) -#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C)) -#define TIMER0_SYNC_R (*((volatile unsigned long *)0x40030010)) -#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018)) -#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C)) -#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020)) -#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024)) -#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028)) -#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C)) -#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030)) -#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034)) -#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038)) -#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C)) -#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040)) -#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044)) -#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048)) -#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C)) -#define TIMER0_TAV_R (*((volatile unsigned long *)0x40030050)) -#define TIMER0_TBV_R (*((volatile unsigned long *)0x40030054)) -#define TIMER0_RTCPD_R (*((volatile unsigned long *)0x40030058)) -#define TIMER0_TAPS_R (*((volatile unsigned long *)0x4003005C)) -#define TIMER0_TBPS_R (*((volatile unsigned long *)0x40030060)) -#define TIMER0_TAPV_R (*((volatile unsigned long *)0x40030064)) -#define TIMER0_TBPV_R (*((volatile unsigned long *)0x40030068)) -#define TIMER0_PP_R (*((volatile unsigned long *)0x40030FC0)) - -//***************************************************************************** -// -// Timer registers (TIMER1) -// -//***************************************************************************** -#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000)) -#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004)) -#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008)) -#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C)) -#define TIMER1_SYNC_R (*((volatile unsigned long *)0x40031010)) -#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018)) -#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C)) -#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020)) -#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024)) -#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028)) -#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C)) -#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030)) -#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034)) -#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038)) -#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C)) -#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040)) -#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044)) -#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048)) -#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C)) -#define TIMER1_TAV_R (*((volatile unsigned long *)0x40031050)) -#define TIMER1_TBV_R (*((volatile unsigned long *)0x40031054)) -#define TIMER1_RTCPD_R (*((volatile unsigned long *)0x40031058)) -#define TIMER1_TAPS_R (*((volatile unsigned long *)0x4003105C)) -#define TIMER1_TBPS_R (*((volatile unsigned long *)0x40031060)) -#define TIMER1_TAPV_R (*((volatile unsigned long *)0x40031064)) -#define TIMER1_TBPV_R (*((volatile unsigned long *)0x40031068)) -#define TIMER1_PP_R (*((volatile unsigned long *)0x40031FC0)) - -//***************************************************************************** -// -// Timer registers (TIMER2) -// -//***************************************************************************** -#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000)) -#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004)) -#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008)) -#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C)) -#define TIMER2_SYNC_R (*((volatile unsigned long *)0x40032010)) -#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018)) -#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C)) -#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020)) -#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024)) -#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028)) -#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C)) -#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030)) -#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034)) -#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038)) -#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C)) -#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040)) -#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044)) -#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048)) -#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C)) -#define TIMER2_TAV_R (*((volatile unsigned long *)0x40032050)) -#define TIMER2_TBV_R (*((volatile unsigned long *)0x40032054)) -#define TIMER2_RTCPD_R (*((volatile unsigned long *)0x40032058)) -#define TIMER2_TAPS_R (*((volatile unsigned long *)0x4003205C)) -#define TIMER2_TBPS_R (*((volatile unsigned long *)0x40032060)) -#define TIMER2_TAPV_R (*((volatile unsigned long *)0x40032064)) -#define TIMER2_TBPV_R (*((volatile unsigned long *)0x40032068)) -#define TIMER2_PP_R (*((volatile unsigned long *)0x40032FC0)) - -//***************************************************************************** -// -// Timer registers (TIMER3) -// -//***************************************************************************** -#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000)) -#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004)) -#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008)) -#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C)) -#define TIMER3_SYNC_R (*((volatile unsigned long *)0x40033010)) -#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018)) -#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C)) -#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020)) -#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024)) -#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028)) -#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C)) -#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030)) -#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034)) -#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038)) -#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C)) -#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040)) -#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044)) -#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048)) -#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C)) -#define TIMER3_TAV_R (*((volatile unsigned long *)0x40033050)) -#define TIMER3_TBV_R (*((volatile unsigned long *)0x40033054)) -#define TIMER3_RTCPD_R (*((volatile unsigned long *)0x40033058)) -#define TIMER3_TAPS_R (*((volatile unsigned long *)0x4003305C)) -#define TIMER3_TBPS_R (*((volatile unsigned long *)0x40033060)) -#define TIMER3_TAPV_R (*((volatile unsigned long *)0x40033064)) -#define TIMER3_TBPV_R (*((volatile unsigned long *)0x40033068)) -#define TIMER3_PP_R (*((volatile unsigned long *)0x40033FC0)) - -//***************************************************************************** -// -// Timer registers (TIMER4) -// -//***************************************************************************** -#define TIMER4_CFG_R (*((volatile unsigned long *)0x40034000)) -#define TIMER4_TAMR_R (*((volatile unsigned long *)0x40034004)) -#define TIMER4_TBMR_R (*((volatile unsigned long *)0x40034008)) -#define TIMER4_CTL_R (*((volatile unsigned long *)0x4003400C)) -#define TIMER4_SYNC_R (*((volatile unsigned long *)0x40034010)) -#define TIMER4_IMR_R (*((volatile unsigned long *)0x40034018)) -#define TIMER4_RIS_R (*((volatile unsigned long *)0x4003401C)) -#define TIMER4_MIS_R (*((volatile unsigned long *)0x40034020)) -#define TIMER4_ICR_R (*((volatile unsigned long *)0x40034024)) -#define TIMER4_TAILR_R (*((volatile unsigned long *)0x40034028)) -#define TIMER4_TBILR_R (*((volatile unsigned long *)0x4003402C)) -#define TIMER4_TAMATCHR_R (*((volatile unsigned long *)0x40034030)) -#define TIMER4_TBMATCHR_R (*((volatile unsigned long *)0x40034034)) -#define TIMER4_TAPR_R (*((volatile unsigned long *)0x40034038)) -#define TIMER4_TBPR_R (*((volatile unsigned long *)0x4003403C)) -#define TIMER4_TAPMR_R (*((volatile unsigned long *)0x40034040)) -#define TIMER4_TBPMR_R (*((volatile unsigned long *)0x40034044)) -#define TIMER4_TAR_R (*((volatile unsigned long *)0x40034048)) -#define TIMER4_TBR_R (*((volatile unsigned long *)0x4003404C)) -#define TIMER4_TAV_R (*((volatile unsigned long *)0x40034050)) -#define TIMER4_TBV_R (*((volatile unsigned long *)0x40034054)) -#define TIMER4_RTCPD_R (*((volatile unsigned long *)0x40034058)) -#define TIMER4_TAPS_R (*((volatile unsigned long *)0x4003405C)) -#define TIMER4_TBPS_R (*((volatile unsigned long *)0x40034060)) -#define TIMER4_TAPV_R (*((volatile unsigned long *)0x40034064)) -#define TIMER4_TBPV_R (*((volatile unsigned long *)0x40034068)) -#define TIMER4_PP_R (*((volatile unsigned long *)0x40034FC0)) - -//***************************************************************************** -// -// Timer registers (TIMER5) -// -//***************************************************************************** -#define TIMER5_CFG_R (*((volatile unsigned long *)0x40035000)) -#define TIMER5_TAMR_R (*((volatile unsigned long *)0x40035004)) -#define TIMER5_TBMR_R (*((volatile unsigned long *)0x40035008)) -#define TIMER5_CTL_R (*((volatile unsigned long *)0x4003500C)) -#define TIMER5_SYNC_R (*((volatile unsigned long *)0x40035010)) -#define TIMER5_IMR_R (*((volatile unsigned long *)0x40035018)) -#define TIMER5_RIS_R (*((volatile unsigned long *)0x4003501C)) -#define TIMER5_MIS_R (*((volatile unsigned long *)0x40035020)) -#define TIMER5_ICR_R (*((volatile unsigned long *)0x40035024)) -#define TIMER5_TAILR_R (*((volatile unsigned long *)0x40035028)) -#define TIMER5_TBILR_R (*((volatile unsigned long *)0x4003502C)) -#define TIMER5_TAMATCHR_R (*((volatile unsigned long *)0x40035030)) -#define TIMER5_TBMATCHR_R (*((volatile unsigned long *)0x40035034)) -#define TIMER5_TAPR_R (*((volatile unsigned long *)0x40035038)) -#define TIMER5_TBPR_R (*((volatile unsigned long *)0x4003503C)) -#define TIMER5_TAPMR_R (*((volatile unsigned long *)0x40035040)) -#define TIMER5_TBPMR_R (*((volatile unsigned long *)0x40035044)) -#define TIMER5_TAR_R (*((volatile unsigned long *)0x40035048)) -#define TIMER5_TBR_R (*((volatile unsigned long *)0x4003504C)) -#define TIMER5_TAV_R (*((volatile unsigned long *)0x40035050)) -#define TIMER5_TBV_R (*((volatile unsigned long *)0x40035054)) -#define TIMER5_RTCPD_R (*((volatile unsigned long *)0x40035058)) -#define TIMER5_TAPS_R (*((volatile unsigned long *)0x4003505C)) -#define TIMER5_TBPS_R (*((volatile unsigned long *)0x40035060)) -#define TIMER5_TAPV_R (*((volatile unsigned long *)0x40035064)) -#define TIMER5_TBPV_R (*((volatile unsigned long *)0x40035068)) -#define TIMER5_PP_R (*((volatile unsigned long *)0x40035FC0)) - -//***************************************************************************** -// -// Timer registers (WTIMER0) -// -//***************************************************************************** -#define WTIMER0_CFG_R (*((volatile unsigned long *)0x40036000)) -#define WTIMER0_TAMR_R (*((volatile unsigned long *)0x40036004)) -#define WTIMER0_TBMR_R (*((volatile unsigned long *)0x40036008)) -#define WTIMER0_CTL_R (*((volatile unsigned long *)0x4003600C)) -#define WTIMER0_SYNC_R (*((volatile unsigned long *)0x40036010)) -#define WTIMER0_IMR_R (*((volatile unsigned long *)0x40036018)) -#define WTIMER0_RIS_R (*((volatile unsigned long *)0x4003601C)) -#define WTIMER0_MIS_R (*((volatile unsigned long *)0x40036020)) -#define WTIMER0_ICR_R (*((volatile unsigned long *)0x40036024)) -#define WTIMER0_TAILR_R (*((volatile unsigned long *)0x40036028)) -#define WTIMER0_TBILR_R (*((volatile unsigned long *)0x4003602C)) -#define WTIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40036030)) -#define WTIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40036034)) -#define WTIMER0_TAPR_R (*((volatile unsigned long *)0x40036038)) -#define WTIMER0_TBPR_R (*((volatile unsigned long *)0x4003603C)) -#define WTIMER0_TAPMR_R (*((volatile unsigned long *)0x40036040)) -#define WTIMER0_TBPMR_R (*((volatile unsigned long *)0x40036044)) -#define WTIMER0_TAR_R (*((volatile unsigned long *)0x40036048)) -#define WTIMER0_TBR_R (*((volatile unsigned long *)0x4003604C)) -#define WTIMER0_TAV_R (*((volatile unsigned long *)0x40036050)) -#define WTIMER0_TBV_R (*((volatile unsigned long *)0x40036054)) -#define WTIMER0_RTCPD_R (*((volatile unsigned long *)0x40036058)) -#define WTIMER0_TAPS_R (*((volatile unsigned long *)0x4003605C)) -#define WTIMER0_TBPS_R (*((volatile unsigned long *)0x40036060)) -#define WTIMER0_TAPV_R (*((volatile unsigned long *)0x40036064)) -#define WTIMER0_TBPV_R (*((volatile unsigned long *)0x40036068)) -#define WTIMER0_PP_R (*((volatile unsigned long *)0x40036FC0)) - -//***************************************************************************** -// -// Timer registers (WTIMER1) -// -//***************************************************************************** -#define WTIMER1_CFG_R (*((volatile unsigned long *)0x40037000)) -#define WTIMER1_TAMR_R (*((volatile unsigned long *)0x40037004)) -#define WTIMER1_TBMR_R (*((volatile unsigned long *)0x40037008)) -#define WTIMER1_CTL_R (*((volatile unsigned long *)0x4003700C)) -#define WTIMER1_SYNC_R (*((volatile unsigned long *)0x40037010)) -#define WTIMER1_IMR_R (*((volatile unsigned long *)0x40037018)) -#define WTIMER1_RIS_R (*((volatile unsigned long *)0x4003701C)) -#define WTIMER1_MIS_R (*((volatile unsigned long *)0x40037020)) -#define WTIMER1_ICR_R (*((volatile unsigned long *)0x40037024)) -#define WTIMER1_TAILR_R (*((volatile unsigned long *)0x40037028)) -#define WTIMER1_TBILR_R (*((volatile unsigned long *)0x4003702C)) -#define WTIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40037030)) -#define WTIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40037034)) -#define WTIMER1_TAPR_R (*((volatile unsigned long *)0x40037038)) -#define WTIMER1_TBPR_R (*((volatile unsigned long *)0x4003703C)) -#define WTIMER1_TAPMR_R (*((volatile unsigned long *)0x40037040)) -#define WTIMER1_TBPMR_R (*((volatile unsigned long *)0x40037044)) -#define WTIMER1_TAR_R (*((volatile unsigned long *)0x40037048)) -#define WTIMER1_TBR_R (*((volatile unsigned long *)0x4003704C)) -#define WTIMER1_TAV_R (*((volatile unsigned long *)0x40037050)) -#define WTIMER1_TBV_R (*((volatile unsigned long *)0x40037054)) -#define WTIMER1_RTCPD_R (*((volatile unsigned long *)0x40037058)) -#define WTIMER1_TAPS_R (*((volatile unsigned long *)0x4003705C)) -#define WTIMER1_TBPS_R (*((volatile unsigned long *)0x40037060)) -#define WTIMER1_TAPV_R (*((volatile unsigned long *)0x40037064)) -#define WTIMER1_TBPV_R (*((volatile unsigned long *)0x40037068)) -#define WTIMER1_PP_R (*((volatile unsigned long *)0x40037FC0)) - -//***************************************************************************** -// -// ADC registers (ADC0) -// -//***************************************************************************** -#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000)) -#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004)) -#define ADC0_IM_R (*((volatile unsigned long *)0x40038008)) -#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C)) -#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010)) -#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014)) -#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018)) -#define ADC0_TSSEL_R (*((volatile unsigned long *)0x4003801C)) -#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020)) -#define ADC0_SPC_R (*((volatile unsigned long *)0x40038024)) -#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028)) -#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030)) -#define ADC0_DCISC_R (*((volatile unsigned long *)0x40038034)) -#define ADC0_CTL_R (*((volatile unsigned long *)0x40038038)) -#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040)) -#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044)) -#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048)) -#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C)) -#define ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050)) -#define ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054)) -#define ADC0_SSEMUX0_R (*((volatile unsigned long *)0x40038058)) -#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060)) -#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064)) -#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068)) -#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C)) -#define ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070)) -#define ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074)) -#define ADC0_SSEMUX1_R (*((volatile unsigned long *)0x40038078)) -#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080)) -#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084)) -#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088)) -#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C)) -#define ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090)) -#define ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094)) -#define ADC0_SSEMUX2_R (*((volatile unsigned long *)0x40038098)) -#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0)) -#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4)) -#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8)) -#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC)) -#define ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0)) -#define ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4)) -#define ADC0_SSEMUX3_R (*((volatile unsigned long *)0x400380B8)) -#define ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00)) -#define ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00)) -#define ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04)) -#define ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08)) -#define ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C)) -#define ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10)) -#define ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14)) -#define ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18)) -#define ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C)) -#define ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40)) -#define ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44)) -#define ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48)) -#define ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C)) -#define ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50)) -#define ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54)) -#define ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58)) -#define ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C)) -#define ADC0_PP_R (*((volatile unsigned long *)0x40038FC0)) -#define ADC0_PC_R (*((volatile unsigned long *)0x40038FC4)) -#define ADC0_CC_R (*((volatile unsigned long *)0x40038FC8)) - -//***************************************************************************** -// -// ADC registers (ADC1) -// -//***************************************************************************** -#define ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000)) -#define ADC1_RIS_R (*((volatile unsigned long *)0x40039004)) -#define ADC1_IM_R (*((volatile unsigned long *)0x40039008)) -#define ADC1_ISC_R (*((volatile unsigned long *)0x4003900C)) -#define ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010)) -#define ADC1_EMUX_R (*((volatile unsigned long *)0x40039014)) -#define ADC1_USTAT_R (*((volatile unsigned long *)0x40039018)) -#define ADC1_TSSEL_R (*((volatile unsigned long *)0x4003901C)) -#define ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020)) -#define ADC1_SPC_R (*((volatile unsigned long *)0x40039024)) -#define ADC1_PSSI_R (*((volatile unsigned long *)0x40039028)) -#define ADC1_SAC_R (*((volatile unsigned long *)0x40039030)) -#define ADC1_DCISC_R (*((volatile unsigned long *)0x40039034)) -#define ADC1_CTL_R (*((volatile unsigned long *)0x40039038)) -#define ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040)) -#define ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044)) -#define ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048)) -#define ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C)) -#define ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050)) -#define ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054)) -#define ADC1_SSEMUX0_R (*((volatile unsigned long *)0x40039058)) -#define ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060)) -#define ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064)) -#define ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068)) -#define ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C)) -#define ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070)) -#define ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074)) -#define ADC1_SSEMUX1_R (*((volatile unsigned long *)0x40039078)) -#define ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080)) -#define ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084)) -#define ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088)) -#define ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C)) -#define ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090)) -#define ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094)) -#define ADC1_SSEMUX2_R (*((volatile unsigned long *)0x40039098)) -#define ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0)) -#define ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4)) -#define ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8)) -#define ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC)) -#define ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0)) -#define ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4)) -#define ADC1_SSEMUX3_R (*((volatile unsigned long *)0x400390B8)) -#define ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00)) -#define ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00)) -#define ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04)) -#define ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08)) -#define ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C)) -#define ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10)) -#define ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14)) -#define ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18)) -#define ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C)) -#define ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40)) -#define ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44)) -#define ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48)) -#define ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C)) -#define ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50)) -#define ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54)) -#define ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58)) -#define ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C)) -#define ADC1_PP_R (*((volatile unsigned long *)0x40039FC0)) -#define ADC1_PC_R (*((volatile unsigned long *)0x40039FC4)) -#define ADC1_CC_R (*((volatile unsigned long *)0x40039FC8)) - -//***************************************************************************** -// -// Comparator registers (COMP) -// -//***************************************************************************** -#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000)) -#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004)) -#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008)) -#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010)) -#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020)) -#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024)) -#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040)) -#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044)) -#define COMP_ACSTAT2_R (*((volatile unsigned long *)0x4003C060)) -#define COMP_ACCTL2_R (*((volatile unsigned long *)0x4003C064)) -#define COMP_PP_R (*((volatile unsigned long *)0x4003CFC0)) - -//***************************************************************************** -// -// GPIO registers (PORTJ) -// -//***************************************************************************** -#define GPIO_PORTJ_DATA_BITS_R ((volatile unsigned long *)0x4003D000) -#define GPIO_PORTJ_DATA_R (*((volatile unsigned long *)0x4003D3FC)) -#define GPIO_PORTJ_DIR_R (*((volatile unsigned long *)0x4003D400)) -#define GPIO_PORTJ_IS_R (*((volatile unsigned long *)0x4003D404)) -#define GPIO_PORTJ_IBE_R (*((volatile unsigned long *)0x4003D408)) -#define GPIO_PORTJ_IEV_R (*((volatile unsigned long *)0x4003D40C)) -#define GPIO_PORTJ_IM_R (*((volatile unsigned long *)0x4003D410)) -#define GPIO_PORTJ_RIS_R (*((volatile unsigned long *)0x4003D414)) -#define GPIO_PORTJ_MIS_R (*((volatile unsigned long *)0x4003D418)) -#define GPIO_PORTJ_ICR_R (*((volatile unsigned long *)0x4003D41C)) -#define GPIO_PORTJ_AFSEL_R (*((volatile unsigned long *)0x4003D420)) -#define GPIO_PORTJ_DR2R_R (*((volatile unsigned long *)0x4003D500)) -#define GPIO_PORTJ_DR4R_R (*((volatile unsigned long *)0x4003D504)) -#define GPIO_PORTJ_DR8R_R (*((volatile unsigned long *)0x4003D508)) -#define GPIO_PORTJ_ODR_R (*((volatile unsigned long *)0x4003D50C)) -#define GPIO_PORTJ_PUR_R (*((volatile unsigned long *)0x4003D510)) -#define GPIO_PORTJ_PDR_R (*((volatile unsigned long *)0x4003D514)) -#define GPIO_PORTJ_SLR_R (*((volatile unsigned long *)0x4003D518)) -#define GPIO_PORTJ_DEN_R (*((volatile unsigned long *)0x4003D51C)) -#define GPIO_PORTJ_LOCK_R (*((volatile unsigned long *)0x4003D520)) -#define GPIO_PORTJ_CR_R (*((volatile unsigned long *)0x4003D524)) -#define GPIO_PORTJ_AMSEL_R (*((volatile unsigned long *)0x4003D528)) -#define GPIO_PORTJ_PCTL_R (*((volatile unsigned long *)0x4003D52C)) -#define GPIO_PORTJ_ADCCTL_R (*((volatile unsigned long *)0x4003D530)) -#define GPIO_PORTJ_DMACTL_R (*((volatile unsigned long *)0x4003D534)) -#define GPIO_PORTJ_SI_R (*((volatile unsigned long *)0x4003D538)) - -//***************************************************************************** -// -// CAN registers (CAN0) -// -//***************************************************************************** -#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000)) -#define CAN0_STS_R (*((volatile unsigned long *)0x40040004)) -#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008)) -#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C)) -#define CAN0_INT_R (*((volatile unsigned long *)0x40040010)) -#define CAN0_TST_R (*((volatile unsigned long *)0x40040014)) -#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018)) -#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020)) -#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024)) -#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028)) -#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C)) -#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030)) -#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034)) -#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038)) -#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C)) -#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040)) -#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044)) -#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048)) -#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080)) -#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084)) -#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088)) -#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C)) -#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090)) -#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094)) -#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098)) -#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C)) -#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0)) -#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4)) -#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8)) -#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100)) -#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104)) -#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120)) -#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124)) -#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140)) -#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144)) -#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160)) -#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164)) - -//***************************************************************************** -// -// CAN registers (CAN1) -// -//***************************************************************************** -#define CAN1_CTL_R (*((volatile unsigned long *)0x40041000)) -#define CAN1_STS_R (*((volatile unsigned long *)0x40041004)) -#define CAN1_ERR_R (*((volatile unsigned long *)0x40041008)) -#define CAN1_BIT_R (*((volatile unsigned long *)0x4004100C)) -#define CAN1_INT_R (*((volatile unsigned long *)0x40041010)) -#define CAN1_TST_R (*((volatile unsigned long *)0x40041014)) -#define CAN1_BRPE_R (*((volatile unsigned long *)0x40041018)) -#define CAN1_IF1CRQ_R (*((volatile unsigned long *)0x40041020)) -#define CAN1_IF1CMSK_R (*((volatile unsigned long *)0x40041024)) -#define CAN1_IF1MSK1_R (*((volatile unsigned long *)0x40041028)) -#define CAN1_IF1MSK2_R (*((volatile unsigned long *)0x4004102C)) -#define CAN1_IF1ARB1_R (*((volatile unsigned long *)0x40041030)) -#define CAN1_IF1ARB2_R (*((volatile unsigned long *)0x40041034)) -#define CAN1_IF1MCTL_R (*((volatile unsigned long *)0x40041038)) -#define CAN1_IF1DA1_R (*((volatile unsigned long *)0x4004103C)) -#define CAN1_IF1DA2_R (*((volatile unsigned long *)0x40041040)) -#define CAN1_IF1DB1_R (*((volatile unsigned long *)0x40041044)) -#define CAN1_IF1DB2_R (*((volatile unsigned long *)0x40041048)) -#define CAN1_IF2CRQ_R (*((volatile unsigned long *)0x40041080)) -#define CAN1_IF2CMSK_R (*((volatile unsigned long *)0x40041084)) -#define CAN1_IF2MSK1_R (*((volatile unsigned long *)0x40041088)) -#define CAN1_IF2MSK2_R (*((volatile unsigned long *)0x4004108C)) -#define CAN1_IF2ARB1_R (*((volatile unsigned long *)0x40041090)) -#define CAN1_IF2ARB2_R (*((volatile unsigned long *)0x40041094)) -#define CAN1_IF2MCTL_R (*((volatile unsigned long *)0x40041098)) -#define CAN1_IF2DA1_R (*((volatile unsigned long *)0x4004109C)) -#define CAN1_IF2DA2_R (*((volatile unsigned long *)0x400410A0)) -#define CAN1_IF2DB1_R (*((volatile unsigned long *)0x400410A4)) -#define CAN1_IF2DB2_R (*((volatile unsigned long *)0x400410A8)) -#define CAN1_TXRQ1_R (*((volatile unsigned long *)0x40041100)) -#define CAN1_TXRQ2_R (*((volatile unsigned long *)0x40041104)) -#define CAN1_NWDA1_R (*((volatile unsigned long *)0x40041120)) -#define CAN1_NWDA2_R (*((volatile unsigned long *)0x40041124)) -#define CAN1_MSG1INT_R (*((volatile unsigned long *)0x40041140)) -#define CAN1_MSG2INT_R (*((volatile unsigned long *)0x40041144)) -#define CAN1_MSG1VAL_R (*((volatile unsigned long *)0x40041160)) -#define CAN1_MSG2VAL_R (*((volatile unsigned long *)0x40041164)) - -//***************************************************************************** -// -// Timer registers (WTIMER2) -// -//***************************************************************************** -#define WTIMER2_CFG_R (*((volatile unsigned long *)0x4004C000)) -#define WTIMER2_TAMR_R (*((volatile unsigned long *)0x4004C004)) -#define WTIMER2_TBMR_R (*((volatile unsigned long *)0x4004C008)) -#define WTIMER2_CTL_R (*((volatile unsigned long *)0x4004C00C)) -#define WTIMER2_SYNC_R (*((volatile unsigned long *)0x4004C010)) -#define WTIMER2_IMR_R (*((volatile unsigned long *)0x4004C018)) -#define WTIMER2_RIS_R (*((volatile unsigned long *)0x4004C01C)) -#define WTIMER2_MIS_R (*((volatile unsigned long *)0x4004C020)) -#define WTIMER2_ICR_R (*((volatile unsigned long *)0x4004C024)) -#define WTIMER2_TAILR_R (*((volatile unsigned long *)0x4004C028)) -#define WTIMER2_TBILR_R (*((volatile unsigned long *)0x4004C02C)) -#define WTIMER2_TAMATCHR_R (*((volatile unsigned long *)0x4004C030)) -#define WTIMER2_TBMATCHR_R (*((volatile unsigned long *)0x4004C034)) -#define WTIMER2_TAPR_R (*((volatile unsigned long *)0x4004C038)) -#define WTIMER2_TBPR_R (*((volatile unsigned long *)0x4004C03C)) -#define WTIMER2_TAPMR_R (*((volatile unsigned long *)0x4004C040)) -#define WTIMER2_TBPMR_R (*((volatile unsigned long *)0x4004C044)) -#define WTIMER2_TAR_R (*((volatile unsigned long *)0x4004C048)) -#define WTIMER2_TBR_R (*((volatile unsigned long *)0x4004C04C)) -#define WTIMER2_TAV_R (*((volatile unsigned long *)0x4004C050)) -#define WTIMER2_TBV_R (*((volatile unsigned long *)0x4004C054)) -#define WTIMER2_RTCPD_R (*((volatile unsigned long *)0x4004C058)) -#define WTIMER2_TAPS_R (*((volatile unsigned long *)0x4004C05C)) -#define WTIMER2_TBPS_R (*((volatile unsigned long *)0x4004C060)) -#define WTIMER2_TAPV_R (*((volatile unsigned long *)0x4004C064)) -#define WTIMER2_TBPV_R (*((volatile unsigned long *)0x4004C068)) -#define WTIMER2_PP_R (*((volatile unsigned long *)0x4004CFC0)) - -//***************************************************************************** -// -// Timer registers (WTIMER3) -// -//***************************************************************************** -#define WTIMER3_CFG_R (*((volatile unsigned long *)0x4004D000)) -#define WTIMER3_TAMR_R (*((volatile unsigned long *)0x4004D004)) -#define WTIMER3_TBMR_R (*((volatile unsigned long *)0x4004D008)) -#define WTIMER3_CTL_R (*((volatile unsigned long *)0x4004D00C)) -#define WTIMER3_SYNC_R (*((volatile unsigned long *)0x4004D010)) -#define WTIMER3_IMR_R (*((volatile unsigned long *)0x4004D018)) -#define WTIMER3_RIS_R (*((volatile unsigned long *)0x4004D01C)) -#define WTIMER3_MIS_R (*((volatile unsigned long *)0x4004D020)) -#define WTIMER3_ICR_R (*((volatile unsigned long *)0x4004D024)) -#define WTIMER3_TAILR_R (*((volatile unsigned long *)0x4004D028)) -#define WTIMER3_TBILR_R (*((volatile unsigned long *)0x4004D02C)) -#define WTIMER3_TAMATCHR_R (*((volatile unsigned long *)0x4004D030)) -#define WTIMER3_TBMATCHR_R (*((volatile unsigned long *)0x4004D034)) -#define WTIMER3_TAPR_R (*((volatile unsigned long *)0x4004D038)) -#define WTIMER3_TBPR_R (*((volatile unsigned long *)0x4004D03C)) -#define WTIMER3_TAPMR_R (*((volatile unsigned long *)0x4004D040)) -#define WTIMER3_TBPMR_R (*((volatile unsigned long *)0x4004D044)) -#define WTIMER3_TAR_R (*((volatile unsigned long *)0x4004D048)) -#define WTIMER3_TBR_R (*((volatile unsigned long *)0x4004D04C)) -#define WTIMER3_TAV_R (*((volatile unsigned long *)0x4004D050)) -#define WTIMER3_TBV_R (*((volatile unsigned long *)0x4004D054)) -#define WTIMER3_RTCPD_R (*((volatile unsigned long *)0x4004D058)) -#define WTIMER3_TAPS_R (*((volatile unsigned long *)0x4004D05C)) -#define WTIMER3_TBPS_R (*((volatile unsigned long *)0x4004D060)) -#define WTIMER3_TAPV_R (*((volatile unsigned long *)0x4004D064)) -#define WTIMER3_TBPV_R (*((volatile unsigned long *)0x4004D068)) -#define WTIMER3_PP_R (*((volatile unsigned long *)0x4004DFC0)) - -//***************************************************************************** -// -// Timer registers (WTIMER4) -// -//***************************************************************************** -#define WTIMER4_CFG_R (*((volatile unsigned long *)0x4004E000)) -#define WTIMER4_TAMR_R (*((volatile unsigned long *)0x4004E004)) -#define WTIMER4_TBMR_R (*((volatile unsigned long *)0x4004E008)) -#define WTIMER4_CTL_R (*((volatile unsigned long *)0x4004E00C)) -#define WTIMER4_SYNC_R (*((volatile unsigned long *)0x4004E010)) -#define WTIMER4_IMR_R (*((volatile unsigned long *)0x4004E018)) -#define WTIMER4_RIS_R (*((volatile unsigned long *)0x4004E01C)) -#define WTIMER4_MIS_R (*((volatile unsigned long *)0x4004E020)) -#define WTIMER4_ICR_R (*((volatile unsigned long *)0x4004E024)) -#define WTIMER4_TAILR_R (*((volatile unsigned long *)0x4004E028)) -#define WTIMER4_TBILR_R (*((volatile unsigned long *)0x4004E02C)) -#define WTIMER4_TAMATCHR_R (*((volatile unsigned long *)0x4004E030)) -#define WTIMER4_TBMATCHR_R (*((volatile unsigned long *)0x4004E034)) -#define WTIMER4_TAPR_R (*((volatile unsigned long *)0x4004E038)) -#define WTIMER4_TBPR_R (*((volatile unsigned long *)0x4004E03C)) -#define WTIMER4_TAPMR_R (*((volatile unsigned long *)0x4004E040)) -#define WTIMER4_TBPMR_R (*((volatile unsigned long *)0x4004E044)) -#define WTIMER4_TAR_R (*((volatile unsigned long *)0x4004E048)) -#define WTIMER4_TBR_R (*((volatile unsigned long *)0x4004E04C)) -#define WTIMER4_TAV_R (*((volatile unsigned long *)0x4004E050)) -#define WTIMER4_TBV_R (*((volatile unsigned long *)0x4004E054)) -#define WTIMER4_RTCPD_R (*((volatile unsigned long *)0x4004E058)) -#define WTIMER4_TAPS_R (*((volatile unsigned long *)0x4004E05C)) -#define WTIMER4_TBPS_R (*((volatile unsigned long *)0x4004E060)) -#define WTIMER4_TAPV_R (*((volatile unsigned long *)0x4004E064)) -#define WTIMER4_TBPV_R (*((volatile unsigned long *)0x4004E068)) -#define WTIMER4_PP_R (*((volatile unsigned long *)0x4004EFC0)) - -//***************************************************************************** -// -// Timer registers (WTIMER5) -// -//***************************************************************************** -#define WTIMER5_CFG_R (*((volatile unsigned long *)0x4004F000)) -#define WTIMER5_TAMR_R (*((volatile unsigned long *)0x4004F004)) -#define WTIMER5_TBMR_R (*((volatile unsigned long *)0x4004F008)) -#define WTIMER5_CTL_R (*((volatile unsigned long *)0x4004F00C)) -#define WTIMER5_SYNC_R (*((volatile unsigned long *)0x4004F010)) -#define WTIMER5_IMR_R (*((volatile unsigned long *)0x4004F018)) -#define WTIMER5_RIS_R (*((volatile unsigned long *)0x4004F01C)) -#define WTIMER5_MIS_R (*((volatile unsigned long *)0x4004F020)) -#define WTIMER5_ICR_R (*((volatile unsigned long *)0x4004F024)) -#define WTIMER5_TAILR_R (*((volatile unsigned long *)0x4004F028)) -#define WTIMER5_TBILR_R (*((volatile unsigned long *)0x4004F02C)) -#define WTIMER5_TAMATCHR_R (*((volatile unsigned long *)0x4004F030)) -#define WTIMER5_TBMATCHR_R (*((volatile unsigned long *)0x4004F034)) -#define WTIMER5_TAPR_R (*((volatile unsigned long *)0x4004F038)) -#define WTIMER5_TBPR_R (*((volatile unsigned long *)0x4004F03C)) -#define WTIMER5_TAPMR_R (*((volatile unsigned long *)0x4004F040)) -#define WTIMER5_TBPMR_R (*((volatile unsigned long *)0x4004F044)) -#define WTIMER5_TAR_R (*((volatile unsigned long *)0x4004F048)) -#define WTIMER5_TBR_R (*((volatile unsigned long *)0x4004F04C)) -#define WTIMER5_TAV_R (*((volatile unsigned long *)0x4004F050)) -#define WTIMER5_TBV_R (*((volatile unsigned long *)0x4004F054)) -#define WTIMER5_RTCPD_R (*((volatile unsigned long *)0x4004F058)) -#define WTIMER5_TAPS_R (*((volatile unsigned long *)0x4004F05C)) -#define WTIMER5_TBPS_R (*((volatile unsigned long *)0x4004F060)) -#define WTIMER5_TAPV_R (*((volatile unsigned long *)0x4004F064)) -#define WTIMER5_TBPV_R (*((volatile unsigned long *)0x4004F068)) -#define WTIMER5_PP_R (*((volatile unsigned long *)0x4004FFC0)) - -//***************************************************************************** -// -// Univeral Serial Bus registers (USB0) -// -//***************************************************************************** -#define USB0_FADDR_R (*((volatile unsigned char *)0x40050000)) -#define USB0_POWER_R (*((volatile unsigned char *)0x40050001)) -#define USB0_TXIS_R (*((volatile unsigned short *)0x40050002)) -#define USB0_RXIS_R (*((volatile unsigned short *)0x40050004)) -#define USB0_TXIE_R (*((volatile unsigned short *)0x40050006)) -#define USB0_RXIE_R (*((volatile unsigned short *)0x40050008)) -#define USB0_IS_R (*((volatile unsigned char *)0x4005000A)) -#define USB0_IE_R (*((volatile unsigned char *)0x4005000B)) -#define USB0_FRAME_R (*((volatile unsigned short *)0x4005000C)) -#define USB0_EPIDX_R (*((volatile unsigned char *)0x4005000E)) -#define USB0_TEST_R (*((volatile unsigned char *)0x4005000F)) -#define USB0_FIFO0_R (*((volatile unsigned long *)0x40050020)) -#define USB0_FIFO1_R (*((volatile unsigned long *)0x40050024)) -#define USB0_FIFO2_R (*((volatile unsigned long *)0x40050028)) -#define USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C)) -#define USB0_FIFO4_R (*((volatile unsigned long *)0x40050030)) -#define USB0_FIFO5_R (*((volatile unsigned long *)0x40050034)) -#define USB0_FIFO6_R (*((volatile unsigned long *)0x40050038)) -#define USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C)) -#define USB0_DEVCTL_R (*((volatile unsigned char *)0x40050060)) -#define USB0_TXFIFOSZ_R (*((volatile unsigned char *)0x40050062)) -#define USB0_RXFIFOSZ_R (*((volatile unsigned char *)0x40050063)) -#define USB0_TXFIFOADD_R (*((volatile unsigned short *)0x40050064)) -#define USB0_RXFIFOADD_R (*((volatile unsigned short *)0x40050066)) -#define USB0_CONTIM_R (*((volatile unsigned char *)0x4005007A)) -#define USB0_VPLEN_R (*((volatile unsigned char *)0x4005007B)) -#define USB0_FSEOF_R (*((volatile unsigned char *)0x4005007D)) -#define USB0_LSEOF_R (*((volatile unsigned char *)0x4005007E)) -#define USB0_TXFUNCADDR0_R (*((volatile unsigned char *)0x40050080)) -#define USB0_TXHUBADDR0_R (*((volatile unsigned char *)0x40050082)) -#define USB0_TXHUBPORT0_R (*((volatile unsigned char *)0x40050083)) -#define USB0_TXFUNCADDR1_R (*((volatile unsigned char *)0x40050088)) -#define USB0_TXHUBADDR1_R (*((volatile unsigned char *)0x4005008A)) -#define USB0_TXHUBPORT1_R (*((volatile unsigned char *)0x4005008B)) -#define USB0_RXFUNCADDR1_R (*((volatile unsigned char *)0x4005008C)) -#define USB0_RXHUBADDR1_R (*((volatile unsigned char *)0x4005008E)) -#define USB0_RXHUBPORT1_R (*((volatile unsigned char *)0x4005008F)) -#define USB0_TXFUNCADDR2_R (*((volatile unsigned char *)0x40050090)) -#define USB0_TXHUBADDR2_R (*((volatile unsigned char *)0x40050092)) -#define USB0_TXHUBPORT2_R (*((volatile unsigned char *)0x40050093)) -#define USB0_RXFUNCADDR2_R (*((volatile unsigned char *)0x40050094)) -#define USB0_RXHUBADDR2_R (*((volatile unsigned char *)0x40050096)) -#define USB0_RXHUBPORT2_R (*((volatile unsigned char *)0x40050097)) -#define USB0_TXFUNCADDR3_R (*((volatile unsigned char *)0x40050098)) -#define USB0_TXHUBADDR3_R (*((volatile unsigned char *)0x4005009A)) -#define USB0_TXHUBPORT3_R (*((volatile unsigned char *)0x4005009B)) -#define USB0_RXFUNCADDR3_R (*((volatile unsigned char *)0x4005009C)) -#define USB0_RXHUBADDR3_R (*((volatile unsigned char *)0x4005009E)) -#define USB0_RXHUBPORT3_R (*((volatile unsigned char *)0x4005009F)) -#define USB0_TXFUNCADDR4_R (*((volatile unsigned char *)0x400500A0)) -#define USB0_TXHUBADDR4_R (*((volatile unsigned char *)0x400500A2)) -#define USB0_TXHUBPORT4_R (*((volatile unsigned char *)0x400500A3)) -#define USB0_RXFUNCADDR4_R (*((volatile unsigned char *)0x400500A4)) -#define USB0_RXHUBADDR4_R (*((volatile unsigned char *)0x400500A6)) -#define USB0_RXHUBPORT4_R (*((volatile unsigned char *)0x400500A7)) -#define USB0_TXFUNCADDR5_R (*((volatile unsigned char *)0x400500A8)) -#define USB0_TXHUBADDR5_R (*((volatile unsigned char *)0x400500AA)) -#define USB0_TXHUBPORT5_R (*((volatile unsigned char *)0x400500AB)) -#define USB0_RXFUNCADDR5_R (*((volatile unsigned char *)0x400500AC)) -#define USB0_RXHUBADDR5_R (*((volatile unsigned char *)0x400500AE)) -#define USB0_RXHUBPORT5_R (*((volatile unsigned char *)0x400500AF)) -#define USB0_TXFUNCADDR6_R (*((volatile unsigned char *)0x400500B0)) -#define USB0_TXHUBADDR6_R (*((volatile unsigned char *)0x400500B2)) -#define USB0_TXHUBPORT6_R (*((volatile unsigned char *)0x400500B3)) -#define USB0_RXFUNCADDR6_R (*((volatile unsigned char *)0x400500B4)) -#define USB0_RXHUBADDR6_R (*((volatile unsigned char *)0x400500B6)) -#define USB0_RXHUBPORT6_R (*((volatile unsigned char *)0x400500B7)) -#define USB0_TXFUNCADDR7_R (*((volatile unsigned char *)0x400500B8)) -#define USB0_TXHUBADDR7_R (*((volatile unsigned char *)0x400500BA)) -#define USB0_TXHUBPORT7_R (*((volatile unsigned char *)0x400500BB)) -#define USB0_RXFUNCADDR7_R (*((volatile unsigned char *)0x400500BC)) -#define USB0_RXHUBADDR7_R (*((volatile unsigned char *)0x400500BE)) -#define USB0_RXHUBPORT7_R (*((volatile unsigned char *)0x400500BF)) -#define USB0_CSRL0_R (*((volatile unsigned char *)0x40050102)) -#define USB0_CSRH0_R (*((volatile unsigned char *)0x40050103)) -#define USB0_COUNT0_R (*((volatile unsigned char *)0x40050108)) -#define USB0_TYPE0_R (*((volatile unsigned char *)0x4005010A)) -#define USB0_NAKLMT_R (*((volatile unsigned char *)0x4005010B)) -#define USB0_TXMAXP1_R (*((volatile unsigned short *)0x40050110)) -#define USB0_TXCSRL1_R (*((volatile unsigned char *)0x40050112)) -#define USB0_TXCSRH1_R (*((volatile unsigned char *)0x40050113)) -#define USB0_RXMAXP1_R (*((volatile unsigned short *)0x40050114)) -#define USB0_RXCSRL1_R (*((volatile unsigned char *)0x40050116)) -#define USB0_RXCSRH1_R (*((volatile unsigned char *)0x40050117)) -#define USB0_RXCOUNT1_R (*((volatile unsigned short *)0x40050118)) -#define USB0_TXTYPE1_R (*((volatile unsigned char *)0x4005011A)) -#define USB0_TXINTERVAL1_R (*((volatile unsigned char *)0x4005011B)) -#define USB0_RXTYPE1_R (*((volatile unsigned char *)0x4005011C)) -#define USB0_RXINTERVAL1_R (*((volatile unsigned char *)0x4005011D)) -#define USB0_TXMAXP2_R (*((volatile unsigned short *)0x40050120)) -#define USB0_TXCSRL2_R (*((volatile unsigned char *)0x40050122)) -#define USB0_TXCSRH2_R (*((volatile unsigned char *)0x40050123)) -#define USB0_RXMAXP2_R (*((volatile unsigned short *)0x40050124)) -#define USB0_RXCSRL2_R (*((volatile unsigned char *)0x40050126)) -#define USB0_RXCSRH2_R (*((volatile unsigned char *)0x40050127)) -#define USB0_RXCOUNT2_R (*((volatile unsigned short *)0x40050128)) -#define USB0_TXTYPE2_R (*((volatile unsigned char *)0x4005012A)) -#define USB0_TXINTERVAL2_R (*((volatile unsigned char *)0x4005012B)) -#define USB0_RXTYPE2_R (*((volatile unsigned char *)0x4005012C)) -#define USB0_RXINTERVAL2_R (*((volatile unsigned char *)0x4005012D)) -#define USB0_TXMAXP3_R (*((volatile unsigned short *)0x40050130)) -#define USB0_TXCSRL3_R (*((volatile unsigned char *)0x40050132)) -#define USB0_TXCSRH3_R (*((volatile unsigned char *)0x40050133)) -#define USB0_RXMAXP3_R (*((volatile unsigned short *)0x40050134)) -#define USB0_RXCSRL3_R (*((volatile unsigned char *)0x40050136)) -#define USB0_RXCSRH3_R (*((volatile unsigned char *)0x40050137)) -#define USB0_RXCOUNT3_R (*((volatile unsigned short *)0x40050138)) -#define USB0_TXTYPE3_R (*((volatile unsigned char *)0x4005013A)) -#define USB0_TXINTERVAL3_R (*((volatile unsigned char *)0x4005013B)) -#define USB0_RXTYPE3_R (*((volatile unsigned char *)0x4005013C)) -#define USB0_RXINTERVAL3_R (*((volatile unsigned char *)0x4005013D)) -#define USB0_TXMAXP4_R (*((volatile unsigned short *)0x40050140)) -#define USB0_TXCSRL4_R (*((volatile unsigned char *)0x40050142)) -#define USB0_TXCSRH4_R (*((volatile unsigned char *)0x40050143)) -#define USB0_RXMAXP4_R (*((volatile unsigned short *)0x40050144)) -#define USB0_RXCSRL4_R (*((volatile unsigned char *)0x40050146)) -#define USB0_RXCSRH4_R (*((volatile unsigned char *)0x40050147)) -#define USB0_RXCOUNT4_R (*((volatile unsigned short *)0x40050148)) -#define USB0_TXTYPE4_R (*((volatile unsigned char *)0x4005014A)) -#define USB0_TXINTERVAL4_R (*((volatile unsigned char *)0x4005014B)) -#define USB0_RXTYPE4_R (*((volatile unsigned char *)0x4005014C)) -#define USB0_RXINTERVAL4_R (*((volatile unsigned char *)0x4005014D)) -#define USB0_TXMAXP5_R (*((volatile unsigned short *)0x40050150)) -#define USB0_TXCSRL5_R (*((volatile unsigned char *)0x40050152)) -#define USB0_TXCSRH5_R (*((volatile unsigned char *)0x40050153)) -#define USB0_RXMAXP5_R (*((volatile unsigned short *)0x40050154)) -#define USB0_RXCSRL5_R (*((volatile unsigned char *)0x40050156)) -#define USB0_RXCSRH5_R (*((volatile unsigned char *)0x40050157)) -#define USB0_RXCOUNT5_R (*((volatile unsigned short *)0x40050158)) -#define USB0_TXTYPE5_R (*((volatile unsigned char *)0x4005015A)) -#define USB0_TXINTERVAL5_R (*((volatile unsigned char *)0x4005015B)) -#define USB0_RXTYPE5_R (*((volatile unsigned char *)0x4005015C)) -#define USB0_RXINTERVAL5_R (*((volatile unsigned char *)0x4005015D)) -#define USB0_TXMAXP6_R (*((volatile unsigned short *)0x40050160)) -#define USB0_TXCSRL6_R (*((volatile unsigned char *)0x40050162)) -#define USB0_TXCSRH6_R (*((volatile unsigned char *)0x40050163)) -#define USB0_RXMAXP6_R (*((volatile unsigned short *)0x40050164)) -#define USB0_RXCSRL6_R (*((volatile unsigned char *)0x40050166)) -#define USB0_RXCSRH6_R (*((volatile unsigned char *)0x40050167)) -#define USB0_RXCOUNT6_R (*((volatile unsigned short *)0x40050168)) -#define USB0_TXTYPE6_R (*((volatile unsigned char *)0x4005016A)) -#define USB0_TXINTERVAL6_R (*((volatile unsigned char *)0x4005016B)) -#define USB0_RXTYPE6_R (*((volatile unsigned char *)0x4005016C)) -#define USB0_RXINTERVAL6_R (*((volatile unsigned char *)0x4005016D)) -#define USB0_TXMAXP7_R (*((volatile unsigned short *)0x40050170)) -#define USB0_TXCSRL7_R (*((volatile unsigned char *)0x40050172)) -#define USB0_TXCSRH7_R (*((volatile unsigned char *)0x40050173)) -#define USB0_RXMAXP7_R (*((volatile unsigned short *)0x40050174)) -#define USB0_RXCSRL7_R (*((volatile unsigned char *)0x40050176)) -#define USB0_RXCSRH7_R (*((volatile unsigned char *)0x40050177)) -#define USB0_RXCOUNT7_R (*((volatile unsigned short *)0x40050178)) -#define USB0_TXTYPE7_R (*((volatile unsigned char *)0x4005017A)) -#define USB0_TXINTERVAL7_R (*((volatile unsigned char *)0x4005017B)) -#define USB0_RXTYPE7_R (*((volatile unsigned char *)0x4005017C)) -#define USB0_RXINTERVAL7_R (*((volatile unsigned char *)0x4005017D)) -#define USB0_RQPKTCOUNT1_R (*((volatile unsigned short *)0x40050304)) -#define USB0_RQPKTCOUNT2_R (*((volatile unsigned short *)0x40050308)) -#define USB0_RQPKTCOUNT3_R (*((volatile unsigned short *)0x4005030C)) -#define USB0_RQPKTCOUNT4_R (*((volatile unsigned short *)0x40050310)) -#define USB0_RQPKTCOUNT5_R (*((volatile unsigned short *)0x40050314)) -#define USB0_RQPKTCOUNT6_R (*((volatile unsigned short *)0x40050318)) -#define USB0_RQPKTCOUNT7_R (*((volatile unsigned short *)0x4005031C)) -#define USB0_RXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050340)) -#define USB0_TXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050342)) -#define USB0_EPC_R (*((volatile unsigned long *)0x40050400)) -#define USB0_EPCRIS_R (*((volatile unsigned long *)0x40050404)) -#define USB0_EPCIM_R (*((volatile unsigned long *)0x40050408)) -#define USB0_EPCISC_R (*((volatile unsigned long *)0x4005040C)) -#define USB0_DRRIS_R (*((volatile unsigned long *)0x40050410)) -#define USB0_DRIM_R (*((volatile unsigned long *)0x40050414)) -#define USB0_DRISC_R (*((volatile unsigned long *)0x40050418)) -#define USB0_GPCS_R (*((volatile unsigned long *)0x4005041C)) -#define USB0_VDC_R (*((volatile unsigned long *)0x40050430)) -#define USB0_VDCRIS_R (*((volatile unsigned long *)0x40050434)) -#define USB0_VDCIM_R (*((volatile unsigned long *)0x40050438)) -#define USB0_VDCISC_R (*((volatile unsigned long *)0x4005043C)) -#define USB0_IDVRIS_R (*((volatile unsigned long *)0x40050444)) -#define USB0_IDVIM_R (*((volatile unsigned long *)0x40050448)) -#define USB0_IDVISC_R (*((volatile unsigned long *)0x4005044C)) -#define USB0_DMASEL_R (*((volatile unsigned long *)0x40050450)) -#define USB0_PP_R (*((volatile unsigned long *)0x40050FC0)) - -//***************************************************************************** -// -// GPIO registers (PORTA AHB) -// -//***************************************************************************** -#define GPIO_PORTA_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x40058000) -#define GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC)) -#define GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400)) -#define GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404)) -#define GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408)) -#define GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C)) -#define GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410)) -#define GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414)) -#define GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418)) -#define GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C)) -#define GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420)) -#define GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500)) -#define GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504)) -#define GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508)) -#define GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C)) -#define GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510)) -#define GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514)) -#define GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518)) -#define GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C)) -#define GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520)) -#define GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524)) -#define GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528)) -#define GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C)) -#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile unsigned long *)0x40058530)) -#define GPIO_PORTA_AHB_DMACTL_R (*((volatile unsigned long *)0x40058534)) -#define GPIO_PORTA_AHB_SI_R (*((volatile unsigned long *)0x40058538)) - -//***************************************************************************** -// -// GPIO registers (PORTB AHB) -// -//***************************************************************************** -#define GPIO_PORTB_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x40059000) -#define GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC)) -#define GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400)) -#define GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404)) -#define GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408)) -#define GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C)) -#define GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410)) -#define GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414)) -#define GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418)) -#define GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C)) -#define GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420)) -#define GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500)) -#define GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504)) -#define GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508)) -#define GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C)) -#define GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510)) -#define GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514)) -#define GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518)) -#define GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C)) -#define GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520)) -#define GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524)) -#define GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528)) -#define GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C)) -#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile unsigned long *)0x40059530)) -#define GPIO_PORTB_AHB_DMACTL_R (*((volatile unsigned long *)0x40059534)) -#define GPIO_PORTB_AHB_SI_R (*((volatile unsigned long *)0x40059538)) - -//***************************************************************************** -// -// GPIO registers (PORTC AHB) -// -//***************************************************************************** -#define GPIO_PORTC_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x4005A000) -#define GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC)) -#define GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400)) -#define GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404)) -#define GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408)) -#define GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C)) -#define GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410)) -#define GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414)) -#define GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418)) -#define GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C)) -#define GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420)) -#define GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500)) -#define GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504)) -#define GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508)) -#define GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C)) -#define GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510)) -#define GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514)) -#define GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518)) -#define GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C)) -#define GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520)) -#define GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524)) -#define GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528)) -#define GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C)) -#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005A530)) -#define GPIO_PORTC_AHB_DMACTL_R (*((volatile unsigned long *)0x4005A534)) -#define GPIO_PORTC_AHB_SI_R (*((volatile unsigned long *)0x4005A538)) - -//***************************************************************************** -// -// GPIO registers (PORTD AHB) -// -//***************************************************************************** -#define GPIO_PORTD_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x4005B000) -#define GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC)) -#define GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400)) -#define GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404)) -#define GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408)) -#define GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C)) -#define GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410)) -#define GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414)) -#define GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418)) -#define GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C)) -#define GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420)) -#define GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500)) -#define GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504)) -#define GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508)) -#define GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C)) -#define GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510)) -#define GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514)) -#define GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518)) -#define GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C)) -#define GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520)) -#define GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524)) -#define GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528)) -#define GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C)) -#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005B530)) -#define GPIO_PORTD_AHB_DMACTL_R (*((volatile unsigned long *)0x4005B534)) -#define GPIO_PORTD_AHB_SI_R (*((volatile unsigned long *)0x4005B538)) - -//***************************************************************************** -// -// GPIO registers (PORTE AHB) -// -//***************************************************************************** -#define GPIO_PORTE_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x4005C000) -#define GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC)) -#define GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400)) -#define GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404)) -#define GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408)) -#define GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C)) -#define GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410)) -#define GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414)) -#define GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418)) -#define GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C)) -#define GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420)) -#define GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500)) -#define GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504)) -#define GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508)) -#define GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C)) -#define GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510)) -#define GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514)) -#define GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518)) -#define GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C)) -#define GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520)) -#define GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524)) -#define GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528)) -#define GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C)) -#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005C530)) -#define GPIO_PORTE_AHB_DMACTL_R (*((volatile unsigned long *)0x4005C534)) -#define GPIO_PORTE_AHB_SI_R (*((volatile unsigned long *)0x4005C538)) - -//***************************************************************************** -// -// GPIO registers (PORTF AHB) -// -//***************************************************************************** -#define GPIO_PORTF_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x4005D000) -#define GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC)) -#define GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400)) -#define GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404)) -#define GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408)) -#define GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C)) -#define GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410)) -#define GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414)) -#define GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418)) -#define GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C)) -#define GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420)) -#define GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500)) -#define GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504)) -#define GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508)) -#define GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C)) -#define GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510)) -#define GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514)) -#define GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518)) -#define GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C)) -#define GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520)) -#define GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524)) -#define GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528)) -#define GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C)) -#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005D530)) -#define GPIO_PORTF_AHB_DMACTL_R (*((volatile unsigned long *)0x4005D534)) -#define GPIO_PORTF_AHB_SI_R (*((volatile unsigned long *)0x4005D538)) - -//***************************************************************************** -// -// GPIO registers (PORTG AHB) -// -//***************************************************************************** -#define GPIO_PORTG_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x4005E000) -#define GPIO_PORTG_AHB_DATA_R (*((volatile unsigned long *)0x4005E3FC)) -#define GPIO_PORTG_AHB_DIR_R (*((volatile unsigned long *)0x4005E400)) -#define GPIO_PORTG_AHB_IS_R (*((volatile unsigned long *)0x4005E404)) -#define GPIO_PORTG_AHB_IBE_R (*((volatile unsigned long *)0x4005E408)) -#define GPIO_PORTG_AHB_IEV_R (*((volatile unsigned long *)0x4005E40C)) -#define GPIO_PORTG_AHB_IM_R (*((volatile unsigned long *)0x4005E410)) -#define GPIO_PORTG_AHB_RIS_R (*((volatile unsigned long *)0x4005E414)) -#define GPIO_PORTG_AHB_MIS_R (*((volatile unsigned long *)0x4005E418)) -#define GPIO_PORTG_AHB_ICR_R (*((volatile unsigned long *)0x4005E41C)) -#define GPIO_PORTG_AHB_AFSEL_R (*((volatile unsigned long *)0x4005E420)) -#define GPIO_PORTG_AHB_DR2R_R (*((volatile unsigned long *)0x4005E500)) -#define GPIO_PORTG_AHB_DR4R_R (*((volatile unsigned long *)0x4005E504)) -#define GPIO_PORTG_AHB_DR8R_R (*((volatile unsigned long *)0x4005E508)) -#define GPIO_PORTG_AHB_ODR_R (*((volatile unsigned long *)0x4005E50C)) -#define GPIO_PORTG_AHB_PUR_R (*((volatile unsigned long *)0x4005E510)) -#define GPIO_PORTG_AHB_PDR_R (*((volatile unsigned long *)0x4005E514)) -#define GPIO_PORTG_AHB_SLR_R (*((volatile unsigned long *)0x4005E518)) -#define GPIO_PORTG_AHB_DEN_R (*((volatile unsigned long *)0x4005E51C)) -#define GPIO_PORTG_AHB_LOCK_R (*((volatile unsigned long *)0x4005E520)) -#define GPIO_PORTG_AHB_CR_R (*((volatile unsigned long *)0x4005E524)) -#define GPIO_PORTG_AHB_AMSEL_R (*((volatile unsigned long *)0x4005E528)) -#define GPIO_PORTG_AHB_PCTL_R (*((volatile unsigned long *)0x4005E52C)) -#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005E530)) -#define GPIO_PORTG_AHB_DMACTL_R (*((volatile unsigned long *)0x4005E534)) -#define GPIO_PORTG_AHB_SI_R (*((volatile unsigned long *)0x4005E538)) - -//***************************************************************************** -// -// GPIO registers (PORTH AHB) -// -//***************************************************************************** -#define GPIO_PORTH_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x4005F000) -#define GPIO_PORTH_AHB_DATA_R (*((volatile unsigned long *)0x4005F3FC)) -#define GPIO_PORTH_AHB_DIR_R (*((volatile unsigned long *)0x4005F400)) -#define GPIO_PORTH_AHB_IS_R (*((volatile unsigned long *)0x4005F404)) -#define GPIO_PORTH_AHB_IBE_R (*((volatile unsigned long *)0x4005F408)) -#define GPIO_PORTH_AHB_IEV_R (*((volatile unsigned long *)0x4005F40C)) -#define GPIO_PORTH_AHB_IM_R (*((volatile unsigned long *)0x4005F410)) -#define GPIO_PORTH_AHB_RIS_R (*((volatile unsigned long *)0x4005F414)) -#define GPIO_PORTH_AHB_MIS_R (*((volatile unsigned long *)0x4005F418)) -#define GPIO_PORTH_AHB_ICR_R (*((volatile unsigned long *)0x4005F41C)) -#define GPIO_PORTH_AHB_AFSEL_R (*((volatile unsigned long *)0x4005F420)) -#define GPIO_PORTH_AHB_DR2R_R (*((volatile unsigned long *)0x4005F500)) -#define GPIO_PORTH_AHB_DR4R_R (*((volatile unsigned long *)0x4005F504)) -#define GPIO_PORTH_AHB_DR8R_R (*((volatile unsigned long *)0x4005F508)) -#define GPIO_PORTH_AHB_ODR_R (*((volatile unsigned long *)0x4005F50C)) -#define GPIO_PORTH_AHB_PUR_R (*((volatile unsigned long *)0x4005F510)) -#define GPIO_PORTH_AHB_PDR_R (*((volatile unsigned long *)0x4005F514)) -#define GPIO_PORTH_AHB_SLR_R (*((volatile unsigned long *)0x4005F518)) -#define GPIO_PORTH_AHB_DEN_R (*((volatile unsigned long *)0x4005F51C)) -#define GPIO_PORTH_AHB_LOCK_R (*((volatile unsigned long *)0x4005F520)) -#define GPIO_PORTH_AHB_CR_R (*((volatile unsigned long *)0x4005F524)) -#define GPIO_PORTH_AHB_AMSEL_R (*((volatile unsigned long *)0x4005F528)) -#define GPIO_PORTH_AHB_PCTL_R (*((volatile unsigned long *)0x4005F52C)) -#define GPIO_PORTH_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005F530)) -#define GPIO_PORTH_AHB_DMACTL_R (*((volatile unsigned long *)0x4005F534)) -#define GPIO_PORTH_AHB_SI_R (*((volatile unsigned long *)0x4005F538)) - -//***************************************************************************** -// -// GPIO registers (PORTJ AHB) -// -//***************************************************************************** -#define GPIO_PORTJ_AHB_DATA_BITS_R \ - ((volatile unsigned long *)0x40060000) -#define GPIO_PORTJ_AHB_DATA_R (*((volatile unsigned long *)0x400603FC)) -#define GPIO_PORTJ_AHB_DIR_R (*((volatile unsigned long *)0x40060400)) -#define GPIO_PORTJ_AHB_IS_R (*((volatile unsigned long *)0x40060404)) -#define GPIO_PORTJ_AHB_IBE_R (*((volatile unsigned long *)0x40060408)) -#define GPIO_PORTJ_AHB_IEV_R (*((volatile unsigned long *)0x4006040C)) -#define GPIO_PORTJ_AHB_IM_R (*((volatile unsigned long *)0x40060410)) -#define GPIO_PORTJ_AHB_RIS_R (*((volatile unsigned long *)0x40060414)) -#define GPIO_PORTJ_AHB_MIS_R (*((volatile unsigned long *)0x40060418)) -#define GPIO_PORTJ_AHB_ICR_R (*((volatile unsigned long *)0x4006041C)) -#define GPIO_PORTJ_AHB_AFSEL_R (*((volatile unsigned long *)0x40060420)) -#define GPIO_PORTJ_AHB_DR2R_R (*((volatile unsigned long *)0x40060500)) -#define GPIO_PORTJ_AHB_DR4R_R (*((volatile unsigned long *)0x40060504)) -#define GPIO_PORTJ_AHB_DR8R_R (*((volatile unsigned long *)0x40060508)) -#define GPIO_PORTJ_AHB_ODR_R (*((volatile unsigned long *)0x4006050C)) -#define GPIO_PORTJ_AHB_PUR_R (*((volatile unsigned long *)0x40060510)) -#define GPIO_PORTJ_AHB_PDR_R (*((volatile unsigned long *)0x40060514)) -#define GPIO_PORTJ_AHB_SLR_R (*((volatile unsigned long *)0x40060518)) -#define GPIO_PORTJ_AHB_DEN_R (*((volatile unsigned long *)0x4006051C)) -#define GPIO_PORTJ_AHB_LOCK_R (*((volatile unsigned long *)0x40060520)) -#define GPIO_PORTJ_AHB_CR_R (*((volatile unsigned long *)0x40060524)) -#define GPIO_PORTJ_AHB_AMSEL_R (*((volatile unsigned long *)0x40060528)) -#define GPIO_PORTJ_AHB_PCTL_R (*((volatile unsigned long *)0x4006052C)) -#define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile unsigned long *)0x40060530)) -#define GPIO_PORTJ_AHB_DMACTL_R (*((volatile unsigned long *)0x40060534)) -#define GPIO_PORTJ_AHB_SI_R (*((volatile unsigned long *)0x40060538)) - -//***************************************************************************** -// -// GPIO registers (PORTK) -// -//***************************************************************************** -#define GPIO_PORTK_DATA_BITS_R ((volatile unsigned long *)0x40061000) -#define GPIO_PORTK_DATA_R (*((volatile unsigned long *)0x400613FC)) -#define GPIO_PORTK_DIR_R (*((volatile unsigned long *)0x40061400)) -#define GPIO_PORTK_IS_R (*((volatile unsigned long *)0x40061404)) -#define GPIO_PORTK_IBE_R (*((volatile unsigned long *)0x40061408)) -#define GPIO_PORTK_IEV_R (*((volatile unsigned long *)0x4006140C)) -#define GPIO_PORTK_IM_R (*((volatile unsigned long *)0x40061410)) -#define GPIO_PORTK_RIS_R (*((volatile unsigned long *)0x40061414)) -#define GPIO_PORTK_MIS_R (*((volatile unsigned long *)0x40061418)) -#define GPIO_PORTK_ICR_R (*((volatile unsigned long *)0x4006141C)) -#define GPIO_PORTK_AFSEL_R (*((volatile unsigned long *)0x40061420)) -#define GPIO_PORTK_DR2R_R (*((volatile unsigned long *)0x40061500)) -#define GPIO_PORTK_DR4R_R (*((volatile unsigned long *)0x40061504)) -#define GPIO_PORTK_DR8R_R (*((volatile unsigned long *)0x40061508)) -#define GPIO_PORTK_ODR_R (*((volatile unsigned long *)0x4006150C)) -#define GPIO_PORTK_PUR_R (*((volatile unsigned long *)0x40061510)) -#define GPIO_PORTK_PDR_R (*((volatile unsigned long *)0x40061514)) -#define GPIO_PORTK_SLR_R (*((volatile unsigned long *)0x40061518)) -#define GPIO_PORTK_DEN_R (*((volatile unsigned long *)0x4006151C)) -#define GPIO_PORTK_LOCK_R (*((volatile unsigned long *)0x40061520)) -#define GPIO_PORTK_CR_R (*((volatile unsigned long *)0x40061524)) -#define GPIO_PORTK_AMSEL_R (*((volatile unsigned long *)0x40061528)) -#define GPIO_PORTK_PCTL_R (*((volatile unsigned long *)0x4006152C)) -#define GPIO_PORTK_ADCCTL_R (*((volatile unsigned long *)0x40061530)) -#define GPIO_PORTK_DMACTL_R (*((volatile unsigned long *)0x40061534)) -#define GPIO_PORTK_SI_R (*((volatile unsigned long *)0x40061538)) - -//***************************************************************************** -// -// GPIO registers (PORTL) -// -//***************************************************************************** -#define GPIO_PORTL_DATA_BITS_R ((volatile unsigned long *)0x40062000) -#define GPIO_PORTL_DATA_R (*((volatile unsigned long *)0x400623FC)) -#define GPIO_PORTL_DIR_R (*((volatile unsigned long *)0x40062400)) -#define GPIO_PORTL_IS_R (*((volatile unsigned long *)0x40062404)) -#define GPIO_PORTL_IBE_R (*((volatile unsigned long *)0x40062408)) -#define GPIO_PORTL_IEV_R (*((volatile unsigned long *)0x4006240C)) -#define GPIO_PORTL_IM_R (*((volatile unsigned long *)0x40062410)) -#define GPIO_PORTL_RIS_R (*((volatile unsigned long *)0x40062414)) -#define GPIO_PORTL_MIS_R (*((volatile unsigned long *)0x40062418)) -#define GPIO_PORTL_ICR_R (*((volatile unsigned long *)0x4006241C)) -#define GPIO_PORTL_AFSEL_R (*((volatile unsigned long *)0x40062420)) -#define GPIO_PORTL_DR2R_R (*((volatile unsigned long *)0x40062500)) -#define GPIO_PORTL_DR4R_R (*((volatile unsigned long *)0x40062504)) -#define GPIO_PORTL_DR8R_R (*((volatile unsigned long *)0x40062508)) -#define GPIO_PORTL_ODR_R (*((volatile unsigned long *)0x4006250C)) -#define GPIO_PORTL_PUR_R (*((volatile unsigned long *)0x40062510)) -#define GPIO_PORTL_PDR_R (*((volatile unsigned long *)0x40062514)) -#define GPIO_PORTL_SLR_R (*((volatile unsigned long *)0x40062518)) -#define GPIO_PORTL_DEN_R (*((volatile unsigned long *)0x4006251C)) -#define GPIO_PORTL_LOCK_R (*((volatile unsigned long *)0x40062520)) -#define GPIO_PORTL_CR_R (*((volatile unsigned long *)0x40062524)) -#define GPIO_PORTL_AMSEL_R (*((volatile unsigned long *)0x40062528)) -#define GPIO_PORTL_PCTL_R (*((volatile unsigned long *)0x4006252C)) -#define GPIO_PORTL_ADCCTL_R (*((volatile unsigned long *)0x40062530)) -#define GPIO_PORTL_DMACTL_R (*((volatile unsigned long *)0x40062534)) -#define GPIO_PORTL_SI_R (*((volatile unsigned long *)0x40062538)) - -//***************************************************************************** -// -// GPIO registers (PORTM) -// -//***************************************************************************** -#define GPIO_PORTM_DATA_BITS_R ((volatile unsigned long *)0x40063000) -#define GPIO_PORTM_DATA_R (*((volatile unsigned long *)0x400633FC)) -#define GPIO_PORTM_DIR_R (*((volatile unsigned long *)0x40063400)) -#define GPIO_PORTM_IS_R (*((volatile unsigned long *)0x40063404)) -#define GPIO_PORTM_IBE_R (*((volatile unsigned long *)0x40063408)) -#define GPIO_PORTM_IEV_R (*((volatile unsigned long *)0x4006340C)) -#define GPIO_PORTM_IM_R (*((volatile unsigned long *)0x40063410)) -#define GPIO_PORTM_RIS_R (*((volatile unsigned long *)0x40063414)) -#define GPIO_PORTM_MIS_R (*((volatile unsigned long *)0x40063418)) -#define GPIO_PORTM_ICR_R (*((volatile unsigned long *)0x4006341C)) -#define GPIO_PORTM_AFSEL_R (*((volatile unsigned long *)0x40063420)) -#define GPIO_PORTM_DR2R_R (*((volatile unsigned long *)0x40063500)) -#define GPIO_PORTM_DR4R_R (*((volatile unsigned long *)0x40063504)) -#define GPIO_PORTM_DR8R_R (*((volatile unsigned long *)0x40063508)) -#define GPIO_PORTM_ODR_R (*((volatile unsigned long *)0x4006350C)) -#define GPIO_PORTM_PUR_R (*((volatile unsigned long *)0x40063510)) -#define GPIO_PORTM_PDR_R (*((volatile unsigned long *)0x40063514)) -#define GPIO_PORTM_SLR_R (*((volatile unsigned long *)0x40063518)) -#define GPIO_PORTM_DEN_R (*((volatile unsigned long *)0x4006351C)) -#define GPIO_PORTM_LOCK_R (*((volatile unsigned long *)0x40063520)) -#define GPIO_PORTM_CR_R (*((volatile unsigned long *)0x40063524)) -#define GPIO_PORTM_AMSEL_R (*((volatile unsigned long *)0x40063528)) -#define GPIO_PORTM_PCTL_R (*((volatile unsigned long *)0x4006352C)) -#define GPIO_PORTM_ADCCTL_R (*((volatile unsigned long *)0x40063530)) -#define GPIO_PORTM_DMACTL_R (*((volatile unsigned long *)0x40063534)) -#define GPIO_PORTM_SI_R (*((volatile unsigned long *)0x40063538)) - -//***************************************************************************** -// -// GPIO registers (PORTN) -// -//***************************************************************************** -#define GPIO_PORTN_DATA_BITS_R ((volatile unsigned long *)0x40064000) -#define GPIO_PORTN_DATA_R (*((volatile unsigned long *)0x400643FC)) -#define GPIO_PORTN_DIR_R (*((volatile unsigned long *)0x40064400)) -#define GPIO_PORTN_IS_R (*((volatile unsigned long *)0x40064404)) -#define GPIO_PORTN_IBE_R (*((volatile unsigned long *)0x40064408)) -#define GPIO_PORTN_IEV_R (*((volatile unsigned long *)0x4006440C)) -#define GPIO_PORTN_IM_R (*((volatile unsigned long *)0x40064410)) -#define GPIO_PORTN_RIS_R (*((volatile unsigned long *)0x40064414)) -#define GPIO_PORTN_MIS_R (*((volatile unsigned long *)0x40064418)) -#define GPIO_PORTN_ICR_R (*((volatile unsigned long *)0x4006441C)) -#define GPIO_PORTN_AFSEL_R (*((volatile unsigned long *)0x40064420)) -#define GPIO_PORTN_DR2R_R (*((volatile unsigned long *)0x40064500)) -#define GPIO_PORTN_DR4R_R (*((volatile unsigned long *)0x40064504)) -#define GPIO_PORTN_DR8R_R (*((volatile unsigned long *)0x40064508)) -#define GPIO_PORTN_ODR_R (*((volatile unsigned long *)0x4006450C)) -#define GPIO_PORTN_PUR_R (*((volatile unsigned long *)0x40064510)) -#define GPIO_PORTN_PDR_R (*((volatile unsigned long *)0x40064514)) -#define GPIO_PORTN_SLR_R (*((volatile unsigned long *)0x40064518)) -#define GPIO_PORTN_DEN_R (*((volatile unsigned long *)0x4006451C)) -#define GPIO_PORTN_LOCK_R (*((volatile unsigned long *)0x40064520)) -#define GPIO_PORTN_CR_R (*((volatile unsigned long *)0x40064524)) -#define GPIO_PORTN_AMSEL_R (*((volatile unsigned long *)0x40064528)) -#define GPIO_PORTN_PCTL_R (*((volatile unsigned long *)0x4006452C)) -#define GPIO_PORTN_ADCCTL_R (*((volatile unsigned long *)0x40064530)) -#define GPIO_PORTN_DMACTL_R (*((volatile unsigned long *)0x40064534)) -#define GPIO_PORTN_SI_R (*((volatile unsigned long *)0x40064538)) - -//***************************************************************************** -// -// GPIO registers (PORTP) -// -//***************************************************************************** -#define GPIO_PORTP_DATA_BITS_R ((volatile unsigned long *)0x40065000) -#define GPIO_PORTP_DATA_R (*((volatile unsigned long *)0x400653FC)) -#define GPIO_PORTP_DIR_R (*((volatile unsigned long *)0x40065400)) -#define GPIO_PORTP_IS_R (*((volatile unsigned long *)0x40065404)) -#define GPIO_PORTP_IBE_R (*((volatile unsigned long *)0x40065408)) -#define GPIO_PORTP_IEV_R (*((volatile unsigned long *)0x4006540C)) -#define GPIO_PORTP_IM_R (*((volatile unsigned long *)0x40065410)) -#define GPIO_PORTP_RIS_R (*((volatile unsigned long *)0x40065414)) -#define GPIO_PORTP_MIS_R (*((volatile unsigned long *)0x40065418)) -#define GPIO_PORTP_ICR_R (*((volatile unsigned long *)0x4006541C)) -#define GPIO_PORTP_AFSEL_R (*((volatile unsigned long *)0x40065420)) -#define GPIO_PORTP_DR2R_R (*((volatile unsigned long *)0x40065500)) -#define GPIO_PORTP_DR4R_R (*((volatile unsigned long *)0x40065504)) -#define GPIO_PORTP_DR8R_R (*((volatile unsigned long *)0x40065508)) -#define GPIO_PORTP_ODR_R (*((volatile unsigned long *)0x4006550C)) -#define GPIO_PORTP_PUR_R (*((volatile unsigned long *)0x40065510)) -#define GPIO_PORTP_PDR_R (*((volatile unsigned long *)0x40065514)) -#define GPIO_PORTP_SLR_R (*((volatile unsigned long *)0x40065518)) -#define GPIO_PORTP_DEN_R (*((volatile unsigned long *)0x4006551C)) -#define GPIO_PORTP_LOCK_R (*((volatile unsigned long *)0x40065520)) -#define GPIO_PORTP_CR_R (*((volatile unsigned long *)0x40065524)) -#define GPIO_PORTP_AMSEL_R (*((volatile unsigned long *)0x40065528)) -#define GPIO_PORTP_PCTL_R (*((volatile unsigned long *)0x4006552C)) -#define GPIO_PORTP_ADCCTL_R (*((volatile unsigned long *)0x40065530)) -#define GPIO_PORTP_DMACTL_R (*((volatile unsigned long *)0x40065534)) -#define GPIO_PORTP_SI_R (*((volatile unsigned long *)0x40065538)) - -//***************************************************************************** -// -// I2C registers (I2C4 MASTER) -// -//***************************************************************************** -#define I2C4_MASTER_MSA_R (*((volatile unsigned long *)0x400C0000)) -#define I2C4_MASTER_MCS_R (*((volatile unsigned long *)0x400C0004)) -#define I2C4_MASTER_MDR_R (*((volatile unsigned long *)0x400C0008)) -#define I2C4_MASTER_MTPR_R (*((volatile unsigned long *)0x400C000C)) -#define I2C4_MASTER_MIMR_R (*((volatile unsigned long *)0x400C0010)) -#define I2C4_MASTER_MRIS_R (*((volatile unsigned long *)0x400C0014)) -#define I2C4_MASTER_MMIS_R (*((volatile unsigned long *)0x400C0018)) -#define I2C4_MASTER_MICR_R (*((volatile unsigned long *)0x400C001C)) -#define I2C4_MASTER_MCR_R (*((volatile unsigned long *)0x400C0020)) -#define I2C4_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x400C0024)) -#define I2C4_MASTER_MBMON_R (*((volatile unsigned long *)0x400C002C)) - -//***************************************************************************** -// -// I2C registers (I2C4 SLAVE) -// -//***************************************************************************** -#define I2C4_SLAVE_SOAR_R (*((volatile unsigned long *)0x400C0800)) -#define I2C4_SLAVE_SCSR_R (*((volatile unsigned long *)0x400C0804)) -#define I2C4_SLAVE_SDR_R (*((volatile unsigned long *)0x400C0808)) -#define I2C4_SLAVE_SIMR_R (*((volatile unsigned long *)0x400C080C)) -#define I2C4_SLAVE_SRIS_R (*((volatile unsigned long *)0x400C0810)) -#define I2C4_SLAVE_SMIS_R (*((volatile unsigned long *)0x400C0814)) -#define I2C4_SLAVE_SICR_R (*((volatile unsigned long *)0x400C0818)) -#define I2C4_SLAVE_SOAR2_R (*((volatile unsigned long *)0x400C081C)) -#define I2C4_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x400C0820)) - -//***************************************************************************** -// -// I2C registers (I2C5 MASTER) -// -//***************************************************************************** -#define I2C5_MASTER_MSA_R (*((volatile unsigned long *)0x400C1000)) -#define I2C5_MASTER_MCS_R (*((volatile unsigned long *)0x400C1004)) -#define I2C5_MASTER_MDR_R (*((volatile unsigned long *)0x400C1008)) -#define I2C5_MASTER_MTPR_R (*((volatile unsigned long *)0x400C100C)) -#define I2C5_MASTER_MIMR_R (*((volatile unsigned long *)0x400C1010)) -#define I2C5_MASTER_MRIS_R (*((volatile unsigned long *)0x400C1014)) -#define I2C5_MASTER_MMIS_R (*((volatile unsigned long *)0x400C1018)) -#define I2C5_MASTER_MICR_R (*((volatile unsigned long *)0x400C101C)) -#define I2C5_MASTER_MCR_R (*((volatile unsigned long *)0x400C1020)) -#define I2C5_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x400C1024)) -#define I2C5_MASTER_MBMON_R (*((volatile unsigned long *)0x400C102C)) - -//***************************************************************************** -// -// I2C registers (I2C5 SLAVE) -// -//***************************************************************************** -#define I2C5_SLAVE_SOAR_R (*((volatile unsigned long *)0x400C1800)) -#define I2C5_SLAVE_SCSR_R (*((volatile unsigned long *)0x400C1804)) -#define I2C5_SLAVE_SDR_R (*((volatile unsigned long *)0x400C1808)) -#define I2C5_SLAVE_SIMR_R (*((volatile unsigned long *)0x400C180C)) -#define I2C5_SLAVE_SRIS_R (*((volatile unsigned long *)0x400C1810)) -#define I2C5_SLAVE_SMIS_R (*((volatile unsigned long *)0x400C1814)) -#define I2C5_SLAVE_SICR_R (*((volatile unsigned long *)0x400C1818)) -#define I2C5_SLAVE_SOAR2_R (*((volatile unsigned long *)0x400C181C)) -#define I2C5_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x400C1820)) - -//***************************************************************************** -// -// System Exception Module registers (SYSEXC) -// -//***************************************************************************** -#define SYSEXC_RIS_R (*((volatile unsigned long *)0x400F9000)) -#define SYSEXC_IM_R (*((volatile unsigned long *)0x400F9004)) -#define SYSEXC_MIS_R (*((volatile unsigned long *)0x400F9008)) -#define SYSEXC_IC_R (*((volatile unsigned long *)0x400F900C)) - -//***************************************************************************** -// -// Hibernation module registers (HIB) -// -//***************************************************************************** -#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000)) -#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004)) -#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C)) -#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010)) -#define HIB_IM_R (*((volatile unsigned long *)0x400FC014)) -#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018)) -#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C)) -#define HIB_IC_R (*((volatile unsigned long *)0x400FC020)) -#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024)) -#define HIB_RTCSS_R (*((volatile unsigned long *)0x400FC028)) -#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030)) - -//***************************************************************************** -// -// FLASH registers (FLASH CTRL) -// -//***************************************************************************** -#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000)) -#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004)) -#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008)) -#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C)) -#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010)) -#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014)) -#define FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020)) -#define FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030)) -#define FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100)) -#define FLASH_FSIZE_R (*((volatile unsigned long *)0x400FDFC0)) -#define FLASH_SSIZE_R (*((volatile unsigned long *)0x400FDFC4)) -#define FLASH_ROMSWMAP_R (*((volatile unsigned long *)0x400FDFCC)) -#define FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0)) -#define FLASH_BOOTCFG_R (*((volatile unsigned long *)0x400FE1D0)) -#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0)) -#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4)) -#define FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8)) -#define FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC)) -#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200)) -#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204)) -#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208)) -#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C)) -#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400)) -#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404)) -#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408)) -#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C)) - -//***************************************************************************** -// -// System Control registers (SYSCTL) -// -//***************************************************************************** -#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000)) -#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004)) -#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008)) -#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010)) -#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014)) -#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018)) -#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C)) -#define SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020)) -#define SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024)) -#define SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028)) -#define SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C)) -#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030)) -#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040)) -#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044)) -#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048)) -#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050)) -#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054)) -#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058)) -#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C)) -#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060)) -#define SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C)) -#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070)) -#define SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C)) -#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100)) -#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104)) -#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108)) -#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110)) -#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114)) -#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118)) -#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120)) -#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124)) -#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128)) -#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144)) -#define SYSCTL_SYSPROP_R (*((volatile unsigned long *)0x400FE14C)) -#define SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150)) -#define SYSCTL_PIOSCSTAT_R (*((volatile unsigned long *)0x400FE154)) -#define SYSCTL_PLLFREQ0_R (*((volatile unsigned long *)0x400FE160)) -#define SYSCTL_PLLFREQ1_R (*((volatile unsigned long *)0x400FE164)) -#define SYSCTL_PLLSTAT_R (*((volatile unsigned long *)0x400FE168)) -#define SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190)) -#define SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0)) -#define SYSCTL_PPWD_R (*((volatile unsigned long *)0x400FE300)) -#define SYSCTL_PPTIMER_R (*((volatile unsigned long *)0x400FE304)) -#define SYSCTL_PPGPIO_R (*((volatile unsigned long *)0x400FE308)) -#define SYSCTL_PPDMA_R (*((volatile unsigned long *)0x400FE30C)) -#define SYSCTL_PPHIB_R (*((volatile unsigned long *)0x400FE314)) -#define SYSCTL_PPUART_R (*((volatile unsigned long *)0x400FE318)) -#define SYSCTL_PPSSI_R (*((volatile unsigned long *)0x400FE31C)) -#define SYSCTL_PPI2C_R (*((volatile unsigned long *)0x400FE320)) -#define SYSCTL_PPUSB_R (*((volatile unsigned long *)0x400FE328)) -#define SYSCTL_PPCAN_R (*((volatile unsigned long *)0x400FE334)) -#define SYSCTL_PPADC_R (*((volatile unsigned long *)0x400FE338)) -#define SYSCTL_PPACMP_R (*((volatile unsigned long *)0x400FE33C)) -#define SYSCTL_PPPWM_R (*((volatile unsigned long *)0x400FE340)) -#define SYSCTL_PPQEI_R (*((volatile unsigned long *)0x400FE344)) -#define SYSCTL_PPEEPROM_R (*((volatile unsigned long *)0x400FE358)) -#define SYSCTL_PPWTIMER_R (*((volatile unsigned long *)0x400FE35C)) -#define SYSCTL_SRWD_R (*((volatile unsigned long *)0x400FE500)) -#define SYSCTL_SRTIMER_R (*((volatile unsigned long *)0x400FE504)) -#define SYSCTL_SRGPIO_R (*((volatile unsigned long *)0x400FE508)) -#define SYSCTL_SRDMA_R (*((volatile unsigned long *)0x400FE50C)) -#define SYSCTL_SRHIB_R (*((volatile unsigned long *)0x400FE514)) -#define SYSCTL_SRUART_R (*((volatile unsigned long *)0x400FE518)) -#define SYSCTL_SRSSI_R (*((volatile unsigned long *)0x400FE51C)) -#define SYSCTL_SRI2C_R (*((volatile unsigned long *)0x400FE520)) -#define SYSCTL_SRUSB_R (*((volatile unsigned long *)0x400FE528)) -#define SYSCTL_SRCAN_R (*((volatile unsigned long *)0x400FE534)) -#define SYSCTL_SRADC_R (*((volatile unsigned long *)0x400FE538)) -#define SYSCTL_SRACMP_R (*((volatile unsigned long *)0x400FE53C)) -#define SYSCTL_SRPWM_R (*((volatile unsigned long *)0x400FE540)) -#define SYSCTL_SRQEI_R (*((volatile unsigned long *)0x400FE544)) -#define SYSCTL_SREEPROM_R (*((volatile unsigned long *)0x400FE558)) -#define SYSCTL_SRWTIMER_R (*((volatile unsigned long *)0x400FE55C)) -#define SYSCTL_RCGCWD_R (*((volatile unsigned long *)0x400FE600)) -#define SYSCTL_RCGCTIMER_R (*((volatile unsigned long *)0x400FE604)) -#define SYSCTL_RCGCGPIO_R (*((volatile unsigned long *)0x400FE608)) -#define SYSCTL_RCGCDMA_R (*((volatile unsigned long *)0x400FE60C)) -#define SYSCTL_RCGCHIB_R (*((volatile unsigned long *)0x400FE614)) -#define SYSCTL_RCGCUART_R (*((volatile unsigned long *)0x400FE618)) -#define SYSCTL_RCGCSSI_R (*((volatile unsigned long *)0x400FE61C)) -#define SYSCTL_RCGCI2C_R (*((volatile unsigned long *)0x400FE620)) -#define SYSCTL_RCGCUSB_R (*((volatile unsigned long *)0x400FE628)) -#define SYSCTL_RCGCCAN_R (*((volatile unsigned long *)0x400FE634)) -#define SYSCTL_RCGCADC_R (*((volatile unsigned long *)0x400FE638)) -#define SYSCTL_RCGCACMP_R (*((volatile unsigned long *)0x400FE63C)) -#define SYSCTL_RCGCPWM_R (*((volatile unsigned long *)0x400FE640)) -#define SYSCTL_RCGCQEI_R (*((volatile unsigned long *)0x400FE644)) -#define SYSCTL_RCGCEEPROM_R (*((volatile unsigned long *)0x400FE658)) -#define SYSCTL_RCGCWTIMER_R (*((volatile unsigned long *)0x400FE65C)) -#define SYSCTL_SCGCWD_R (*((volatile unsigned long *)0x400FE700)) -#define SYSCTL_SCGCTIMER_R (*((volatile unsigned long *)0x400FE704)) -#define SYSCTL_SCGCGPIO_R (*((volatile unsigned long *)0x400FE708)) -#define SYSCTL_SCGCDMA_R (*((volatile unsigned long *)0x400FE70C)) -#define SYSCTL_SCGCHIB_R (*((volatile unsigned long *)0x400FE714)) -#define SYSCTL_SCGCUART_R (*((volatile unsigned long *)0x400FE718)) -#define SYSCTL_SCGCSSI_R (*((volatile unsigned long *)0x400FE71C)) -#define SYSCTL_SCGCI2C_R (*((volatile unsigned long *)0x400FE720)) -#define SYSCTL_SCGCUSB_R (*((volatile unsigned long *)0x400FE728)) -#define SYSCTL_SCGCCAN_R (*((volatile unsigned long *)0x400FE734)) -#define SYSCTL_SCGCADC_R (*((volatile unsigned long *)0x400FE738)) -#define SYSCTL_SCGCACMP_R (*((volatile unsigned long *)0x400FE73C)) -#define SYSCTL_SCGCPWM_R (*((volatile unsigned long *)0x400FE740)) -#define SYSCTL_SCGCQEI_R (*((volatile unsigned long *)0x400FE744)) -#define SYSCTL_SCGCEEPROM_R (*((volatile unsigned long *)0x400FE758)) -#define SYSCTL_SCGCWTIMER_R (*((volatile unsigned long *)0x400FE75C)) -#define SYSCTL_DCGCWD_R (*((volatile unsigned long *)0x400FE800)) -#define SYSCTL_DCGCTIMER_R (*((volatile unsigned long *)0x400FE804)) -#define SYSCTL_DCGCGPIO_R (*((volatile unsigned long *)0x400FE808)) -#define SYSCTL_DCGCDMA_R (*((volatile unsigned long *)0x400FE80C)) -#define SYSCTL_DCGCHIB_R (*((volatile unsigned long *)0x400FE814)) -#define SYSCTL_DCGCUART_R (*((volatile unsigned long *)0x400FE818)) -#define SYSCTL_DCGCSSI_R (*((volatile unsigned long *)0x400FE81C)) -#define SYSCTL_DCGCI2C_R (*((volatile unsigned long *)0x400FE820)) -#define SYSCTL_DCGCUSB_R (*((volatile unsigned long *)0x400FE828)) -#define SYSCTL_DCGCCAN_R (*((volatile unsigned long *)0x400FE834)) -#define SYSCTL_DCGCADC_R (*((volatile unsigned long *)0x400FE838)) -#define SYSCTL_DCGCACMP_R (*((volatile unsigned long *)0x400FE83C)) -#define SYSCTL_DCGCPWM_R (*((volatile unsigned long *)0x400FE840)) -#define SYSCTL_DCGCQEI_R (*((volatile unsigned long *)0x400FE844)) -#define SYSCTL_DCGCEEPROM_R (*((volatile unsigned long *)0x400FE858)) -#define SYSCTL_DCGCWTIMER_R (*((volatile unsigned long *)0x400FE85C)) -#define SYSCTL_PCWD_R (*((volatile unsigned long *)0x400FE900)) -#define SYSCTL_PCTIMER_R (*((volatile unsigned long *)0x400FE904)) -#define SYSCTL_PCGPIO_R (*((volatile unsigned long *)0x400FE908)) -#define SYSCTL_PCDMA_R (*((volatile unsigned long *)0x400FE90C)) -#define SYSCTL_PCHIB_R (*((volatile unsigned long *)0x400FE914)) -#define SYSCTL_PCUART_R (*((volatile unsigned long *)0x400FE918)) -#define SYSCTL_PCSSI_R (*((volatile unsigned long *)0x400FE91C)) -#define SYSCTL_PCI2C_R (*((volatile unsigned long *)0x400FE920)) -#define SYSCTL_PCUSB_R (*((volatile unsigned long *)0x400FE928)) -#define SYSCTL_PCCAN_R (*((volatile unsigned long *)0x400FE934)) -#define SYSCTL_PCADC_R (*((volatile unsigned long *)0x400FE938)) -#define SYSCTL_PCACMP_R (*((volatile unsigned long *)0x400FE93C)) -#define SYSCTL_PCPWM_R (*((volatile unsigned long *)0x400FE940)) -#define SYSCTL_PCQEI_R (*((volatile unsigned long *)0x400FE944)) -#define SYSCTL_PCEEPROM_R (*((volatile unsigned long *)0x400FE958)) -#define SYSCTL_PCWTIMER_R (*((volatile unsigned long *)0x400FE95C)) -#define SYSCTL_PRWD_R (*((volatile unsigned long *)0x400FEA00)) -#define SYSCTL_PRTIMER_R (*((volatile unsigned long *)0x400FEA04)) -#define SYSCTL_PRGPIO_R (*((volatile unsigned long *)0x400FEA08)) -#define SYSCTL_PRDMA_R (*((volatile unsigned long *)0x400FEA0C)) -#define SYSCTL_PRHIB_R (*((volatile unsigned long *)0x400FEA14)) -#define SYSCTL_PRUART_R (*((volatile unsigned long *)0x400FEA18)) -#define SYSCTL_PRSSI_R (*((volatile unsigned long *)0x400FEA1C)) -#define SYSCTL_PRI2C_R (*((volatile unsigned long *)0x400FEA20)) -#define SYSCTL_PRUSB_R (*((volatile unsigned long *)0x400FEA28)) -#define SYSCTL_PRCAN_R (*((volatile unsigned long *)0x400FEA34)) -#define SYSCTL_PRADC_R (*((volatile unsigned long *)0x400FEA38)) -#define SYSCTL_PRACMP_R (*((volatile unsigned long *)0x400FEA3C)) -#define SYSCTL_PRPWM_R (*((volatile unsigned long *)0x400FEA40)) -#define SYSCTL_PRQEI_R (*((volatile unsigned long *)0x400FEA44)) -#define SYSCTL_PREEPROM_R (*((volatile unsigned long *)0x400FEA58)) -#define SYSCTL_PRWTIMER_R (*((volatile unsigned long *)0x400FEA5C)) - -//***************************************************************************** -// -// Micro Direct Memory Access registers (UDMA) -// -//***************************************************************************** -#define UDMA_STAT_R (*((volatile unsigned long *)0x400FF000)) -#define UDMA_CFG_R (*((volatile unsigned long *)0x400FF004)) -#define UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008)) -#define UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C)) -#define UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010)) -#define UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014)) -#define UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018)) -#define UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C)) -#define UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020)) -#define UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024)) -#define UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028)) -#define UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C)) -#define UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030)) -#define UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034)) -#define UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038)) -#define UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C)) -#define UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C)) -#define UDMA_CHASGN_R (*((volatile unsigned long *)0x400FF500)) -#define UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504)) -#define UDMA_CHMAP0_R (*((volatile unsigned long *)0x400FF510)) -#define UDMA_CHMAP1_R (*((volatile unsigned long *)0x400FF514)) -#define UDMA_CHMAP2_R (*((volatile unsigned long *)0x400FF518)) -#define UDMA_CHMAP3_R (*((volatile unsigned long *)0x400FF51C)) - -//***************************************************************************** -// -// Micro Direct Memory Access (uDMA) offsets (UDMA) -// -//***************************************************************************** -#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// NVIC registers (NVIC) -// -//***************************************************************************** -#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004)) -#define NVIC_ACTLR_R (*((volatile unsigned long *)0xE000E008)) -#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010)) -#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014)) -#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018)) -#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C)) -#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) -#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104)) -#define NVIC_EN2_R (*((volatile unsigned long *)0xE000E108)) -#define NVIC_EN3_R (*((volatile unsigned long *)0xE000E10C)) -#define NVIC_EN4_R (*((volatile unsigned long *)0xE000E110)) -#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180)) -#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184)) -#define NVIC_DIS2_R (*((volatile unsigned long *)0xE000E188)) -#define NVIC_DIS3_R (*((volatile unsigned long *)0xE000E18C)) -#define NVIC_DIS4_R (*((volatile unsigned long *)0xE000E190)) -#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200)) -#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204)) -#define NVIC_PEND2_R (*((volatile unsigned long *)0xE000E208)) -#define NVIC_PEND3_R (*((volatile unsigned long *)0xE000E20C)) -#define NVIC_PEND4_R (*((volatile unsigned long *)0xE000E210)) -#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280)) -#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284)) -#define NVIC_UNPEND2_R (*((volatile unsigned long *)0xE000E288)) -#define NVIC_UNPEND3_R (*((volatile unsigned long *)0xE000E28C)) -#define NVIC_UNPEND4_R (*((volatile unsigned long *)0xE000E290)) -#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300)) -#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304)) -#define NVIC_ACTIVE2_R (*((volatile unsigned long *)0xE000E308)) -#define NVIC_ACTIVE3_R (*((volatile unsigned long *)0xE000E30C)) -#define NVIC_ACTIVE4_R (*((volatile unsigned long *)0xE000E310)) -#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400)) -#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404)) -#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408)) -#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C)) -#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) -#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414)) -#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418)) -#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C)) -#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420)) -#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424)) -#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428)) -#define NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C)) -#define NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430)) -#define NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434)) -#define NVIC_PRI14_R (*((volatile unsigned long *)0xE000E438)) -#define NVIC_PRI15_R (*((volatile unsigned long *)0xE000E43C)) -#define NVIC_PRI16_R (*((volatile unsigned long *)0xE000E440)) -#define NVIC_PRI17_R (*((volatile unsigned long *)0xE000E444)) -#define NVIC_PRI18_R (*((volatile unsigned long *)0xE000E448)) -#define NVIC_PRI19_R (*((volatile unsigned long *)0xE000E44C)) -#define NVIC_PRI20_R (*((volatile unsigned long *)0xE000E450)) -#define NVIC_PRI21_R (*((volatile unsigned long *)0xE000E454)) -#define NVIC_PRI22_R (*((volatile unsigned long *)0xE000E458)) -#define NVIC_PRI23_R (*((volatile unsigned long *)0xE000E45C)) -#define NVIC_PRI24_R (*((volatile unsigned long *)0xE000E460)) -#define NVIC_PRI25_R (*((volatile unsigned long *)0xE000E464)) -#define NVIC_PRI26_R (*((volatile unsigned long *)0xE000E468)) -#define NVIC_PRI27_R (*((volatile unsigned long *)0xE000E46C)) -#define NVIC_PRI28_R (*((volatile unsigned long *)0xE000E470)) -#define NVIC_PRI29_R (*((volatile unsigned long *)0xE000E474)) -#define NVIC_PRI30_R (*((volatile unsigned long *)0xE000E478)) -#define NVIC_PRI31_R (*((volatile unsigned long *)0xE000E47C)) -#define NVIC_PRI32_R (*((volatile unsigned long *)0xE000E480)) -#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00)) -#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04)) -#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08)) -#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C)) -#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10)) -#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14)) -#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18)) -#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C)) -#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20)) -#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24)) -#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28)) -#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C)) -#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30)) -#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34)) -#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38)) -#define NVIC_CPAC_R (*((volatile unsigned long *)0xE000ED88)) -#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90)) -#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94)) -#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98)) -#define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C)) -#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0)) -#define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4)) -#define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8)) -#define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC)) -#define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0)) -#define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4)) -#define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8)) -#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0)) -#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4)) -#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8)) -#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC)) -#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00)) -#define NVIC_FPCC_R (*((volatile unsigned long *)0xE000EF34)) -#define NVIC_FPCA_R (*((volatile unsigned long *)0xE000EF38)) -#define NVIC_FPDSC_R (*((volatile unsigned long *)0xE000EF3C)) - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//***************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//***************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//***************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//***************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//***************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//***************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock -#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked - // and may be modified -#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked - // and may not be modified -#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_SI register. -// -//***************************************************************************** -#define GPIO_SI_SUM 0x00000001 // Summary Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port A. -// -//***************************************************************************** -#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask -#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7 -#define GPIO_PCTL_PA7_M1PWM3 0x50000000 // M1PWM3 on PA7 -#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask -#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6 -#define GPIO_PCTL_PA6_M1PWM2 0x05000000 // M1PWM2 on PA6 -#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask -#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5 -#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask -#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4 -#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask -#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3 -#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask -#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2 -#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask -#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 -#define GPIO_PCTL_PA1_CAN1TX 0x00000080 // CAN1TX on PA1 -#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask -#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 -#define GPIO_PCTL_PA0_CAN1RX 0x00000008 // CAN1RX on PA0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port B. -// -//***************************************************************************** -#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask -#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5 -#define GPIO_PCTL_PB5_M0PWM3 0x00400000 // M0PWM3 on PB5 -#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5 -#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5 -#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask -#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4 -#define GPIO_PCTL_PB4_M0PWM2 0x00040000 // M0PWM2 on PB4 -#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4 -#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4 -#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask -#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3 -#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3 -#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask -#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2 -#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2 -#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask -#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1 -#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1 -#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask -#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0 -#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port C. -// -//***************************************************************************** -#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask -#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7 -#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7 -#define GPIO_PCTL_PC7_USB0PFLT 0x80000000 // USB0PFLT on PC7 -#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask -#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6 -#define GPIO_PCTL_PC6_PHB1 0x06000000 // PHB1 on PC6 -#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6 -#define GPIO_PCTL_PC6_USB0EPEN 0x08000000 // USB0EPEN on PC6 -#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask -#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5 -#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5 -#define GPIO_PCTL_PC5_M0PWM7 0x00400000 // M0PWM7 on PC5 -#define GPIO_PCTL_PC5_PHA1 0x00600000 // PHA1 on PC5 -#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5 -#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5 -#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask -#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4 -#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4 -#define GPIO_PCTL_PC4_M0PWM6 0x00040000 // M0PWM6 on PC4 -#define GPIO_PCTL_PC4_IDX1 0x00060000 // IDX1 on PC4 -#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4 -#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4 -#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask -#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3 -#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3 -#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask -#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2 -#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2 -#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask -#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1 -#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1 -#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask -#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0 -#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port D. -// -//***************************************************************************** -#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask -#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7 -#define GPIO_PCTL_PD7_M0FAULT1 0x40000000 // M0FAULT1 on PD7 -#define GPIO_PCTL_PD7_PHB0 0x60000000 // PHB0 on PD7 -#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7 -#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7 -#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask -#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6 -#define GPIO_PCTL_PD6_M0FAULT0 0x04000000 // M0FAULT0 on PD6 -#define GPIO_PCTL_PD6_PHA0 0x06000000 // PHA0 on PD6 -#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6 -#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask -#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5 -#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5 -#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask -#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4 -#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4 -#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask -#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3 -#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3 -#define GPIO_PCTL_PD3_IDX0 0x00006000 // IDX0 on PD3 -#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3 -#define GPIO_PCTL_PD3_USB0PFLT 0x00008000 // USB0PFLT on PD3 -#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask -#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2 -#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2 -#define GPIO_PCTL_PD2_M0FAULT0 0x00000400 // M0FAULT0 on PD2 -#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2 -#define GPIO_PCTL_PD2_USB0EPEN 0x00000800 // USB0EPEN on PD2 -#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask -#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1 -#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1 -#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1 -#define GPIO_PCTL_PD1_M0PWM7 0x00000040 // M0PWM7 on PD1 -#define GPIO_PCTL_PD1_M1PWM1 0x00000050 // M1PWM1 on PD1 -#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1 -#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask -#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0 -#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0 -#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0 -#define GPIO_PCTL_PD0_M0PWM6 0x00000004 // M0PWM6 on PD0 -#define GPIO_PCTL_PD0_M1PWM0 0x00000005 // M1PWM0 on PD0 -#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port E. -// -//***************************************************************************** -#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask -#define GPIO_PCTL_PE7_U1RI 0x10000000 // U1RI on PE7 -#define GPIO_PCTL_PE7_CAN1TX 0x80000000 // CAN1TX on PE7 -#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask -#define GPIO_PCTL_PE6_CAN1RX 0x08000000 // CAN1RX on PE6 -#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask -#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5 -#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5 -#define GPIO_PCTL_PE5_M0PWM5 0x00400000 // M0PWM5 on PE5 -#define GPIO_PCTL_PE5_M1PWM3 0x00500000 // M1PWM3 on PE5 -#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5 -#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask -#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4 -#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4 -#define GPIO_PCTL_PE4_M0PWM4 0x00040000 // M0PWM4 on PE4 -#define GPIO_PCTL_PE4_M1PWM2 0x00050000 // M1PWM2 on PE4 -#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4 -#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask -#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1 -#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask -#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port F. -// -//***************************************************************************** -#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask -#define GPIO_PCTL_PF7_I2C2SDA 0x30000000 // I2C2SDA on PF7 -#define GPIO_PCTL_PF7_M1FAULT0 0x50000000 // M1FAULT0 on PF7 -#define GPIO_PCTL_PF7_T3CCP1 0x70000000 // T3CCP1 on PF7 -#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask -#define GPIO_PCTL_PF6_I2C2SCL 0x03000000 // I2C2SCL on PF6 -#define GPIO_PCTL_PF6_T3CCP0 0x07000000 // T3CCP0 on PF6 -#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask -#define GPIO_PCTL_PF5_M0FAULT3 0x00400000 // M0FAULT3 on PF5 -#define GPIO_PCTL_PF5_T2CCP1 0x00700000 // T2CCP1 on PF5 -#define GPIO_PCTL_PF5_USB0PFLT 0x00800000 // USB0PFLT on PF5 -#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask -#define GPIO_PCTL_PF4_U1DTR 0x00010000 // U1DTR on PF4 -#define GPIO_PCTL_PF4_M0FAULT2 0x00040000 // M0FAULT2 on PF4 -#define GPIO_PCTL_PF4_M1FAULT0 0x00050000 // M1FAULT0 on PF4 -#define GPIO_PCTL_PF4_IDX0 0x00060000 // IDX0 on PF4 -#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4 -#define GPIO_PCTL_PF4_USB0EPEN 0x00080000 // USB0EPEN on PF4 -#define GPIO_PCTL_PF4_TRD3 0x000E0000 // TRD3 on PF4 -#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask -#define GPIO_PCTL_PF3_U1DSR 0x00001000 // U1DSR on PF3 -#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3 -#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3 -#define GPIO_PCTL_PF3_M0FAULT1 0x00004000 // M0FAULT1 on PF3 -#define GPIO_PCTL_PF3_M1PWM7 0x00005000 // M1PWM7 on PF3 -#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3 -#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3 -#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask -#define GPIO_PCTL_PF2_U1DCD 0x00000100 // U1DCD on PF2 -#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2 -#define GPIO_PCTL_PF2_M0FAULT0 0x00000400 // M0FAULT0 on PF2 -#define GPIO_PCTL_PF2_M1PWM6 0x00000500 // M1PWM6 on PF2 -#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2 -#define GPIO_PCTL_PF2_C2O 0x00000900 // C2O on PF2 -#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2 -#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask -#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1 -#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1 -#define GPIO_PCTL_PF1_M1PWM5 0x00000050 // M1PWM5 on PF1 -#define GPIO_PCTL_PF1_PHB0 0x00000060 // PHB0 on PF1 -#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1 -#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1 -#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1 -#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask -#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0 -#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0 -#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0 -#define GPIO_PCTL_PF0_M1PWM4 0x00000005 // M1PWM4 on PF0 -#define GPIO_PCTL_PF0_PHA0 0x00000006 // PHA0 on PF0 -#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0 -#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0 -#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0 -#define GPIO_PCTL_PF0_TRD2 0x0000000E // TRD2 on PF0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port G. -// -//***************************************************************************** -#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask -#define GPIO_PCTL_PG7_I2C5SDA 0x30000000 // I2C5SDA on PG7 -#define GPIO_PCTL_PG7_M0PWM7 0x40000000 // M0PWM7 on PG7 -#define GPIO_PCTL_PG7_IDX1 0x50000000 // IDX1 on PG7 -#define GPIO_PCTL_PG7_WT1CCP1 0x70000000 // WT1CCP1 on PG7 -#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask -#define GPIO_PCTL_PG6_I2C5SCL 0x03000000 // I2C5SCL on PG6 -#define GPIO_PCTL_PG6_M0PWM6 0x04000000 // M0PWM6 on PG6 -#define GPIO_PCTL_PG6_WT1CCP0 0x07000000 // WT1CCP0 on PG6 -#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask -#define GPIO_PCTL_PG5_U2TX 0x00100000 // U2TX on PG5 -#define GPIO_PCTL_PG5_I2C1SDA 0x00300000 // I2C1SDA on PG5 -#define GPIO_PCTL_PG5_M0PWM5 0x00400000 // M0PWM5 on PG5 -#define GPIO_PCTL_PG5_M1PWM3 0x00500000 // M1PWM3 on PG5 -#define GPIO_PCTL_PG5_IDX1 0x00600000 // IDX1 on PG5 -#define GPIO_PCTL_PG5_WT0CCP1 0x00700000 // WT0CCP1 on PG5 -#define GPIO_PCTL_PG5_USB0PFLT 0x00800000 // USB0PFLT on PG5 -#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask -#define GPIO_PCTL_PG4_U2RX 0x00010000 // U2RX on PG4 -#define GPIO_PCTL_PG4_I2C1SCL 0x00030000 // I2C1SCL on PG4 -#define GPIO_PCTL_PG4_M0PWM4 0x00040000 // M0PWM4 on PG4 -#define GPIO_PCTL_PG4_M1PWM2 0x00050000 // M1PWM2 on PG4 -#define GPIO_PCTL_PG4_PHB1 0x00060000 // PHB1 on PG4 -#define GPIO_PCTL_PG4_WT0CCP0 0x00070000 // WT0CCP0 on PG4 -#define GPIO_PCTL_PG4_USB0EPEN 0x00080000 // USB0EPEN on PG4 -#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask -#define GPIO_PCTL_PG3_I2C4SDA 0x00003000 // I2C4SDA on PG3 -#define GPIO_PCTL_PG3_M0FAULT2 0x00004000 // M0FAULT2 on PG3 -#define GPIO_PCTL_PG3_M1PWM1 0x00005000 // M1PWM1 on PG3 -#define GPIO_PCTL_PG3_PHA1 0x00006000 // PHA1 on PG3 -#define GPIO_PCTL_PG3_T5CCP1 0x00007000 // T5CCP1 on PG3 -#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask -#define GPIO_PCTL_PG2_I2C4SCL 0x00000300 // I2C4SCL on PG2 -#define GPIO_PCTL_PG2_M0FAULT1 0x00000400 // M0FAULT1 on PG2 -#define GPIO_PCTL_PG2_M1PWM0 0x00000500 // M1PWM0 on PG2 -#define GPIO_PCTL_PG2_T5CCP0 0x00000700 // T5CCP0 on PG2 -#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask -#define GPIO_PCTL_PG1_I2C3SDA 0x00000030 // I2C3SDA on PG1 -#define GPIO_PCTL_PG1_M1FAULT2 0x00000050 // M1FAULT2 on PG1 -#define GPIO_PCTL_PG1_PHB1 0x00000060 // PHB1 on PG1 -#define GPIO_PCTL_PG1_T4CCP1 0x00000070 // T4CCP1 on PG1 -#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask -#define GPIO_PCTL_PG0_I2C3SCL 0x00000003 // I2C3SCL on PG0 -#define GPIO_PCTL_PG0_M1FAULT1 0x00000005 // M1FAULT1 on PG0 -#define GPIO_PCTL_PG0_PHA1 0x00000006 // PHA1 on PG0 -#define GPIO_PCTL_PG0_T4CCP0 0x00000007 // T4CCP0 on PG0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port H. -// -//***************************************************************************** -#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask -#define GPIO_PCTL_PH7_SSI2TX 0x20000000 // SSI2TX on PH7 -#define GPIO_PCTL_PH7_M0PWM7 0x40000000 // M0PWM7 on PH7 -#define GPIO_PCTL_PH7_WT4CCP1 0x70000000 // WT4CCP1 on PH7 -#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask -#define GPIO_PCTL_PH6_SSI2RX 0x02000000 // SSI2RX on PH6 -#define GPIO_PCTL_PH6_M0PWM6 0x04000000 // M0PWM6 on PH6 -#define GPIO_PCTL_PH6_WT4CCP0 0x07000000 // WT4CCP0 on PH6 -#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask -#define GPIO_PCTL_PH5_SSI2FSS 0x00200000 // SSI2FSS on PH5 -#define GPIO_PCTL_PH5_M0PWM5 0x00400000 // M0PWM5 on PH5 -#define GPIO_PCTL_PH5_PHB0 0x00500000 // PHB0 on PH5 -#define GPIO_PCTL_PH5_WT3CCP1 0x00700000 // WT3CCP1 on PH5 -#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask -#define GPIO_PCTL_PH4_SSI2CLK 0x00020000 // SSI2CLK on PH4 -#define GPIO_PCTL_PH4_M0PWM4 0x00040000 // M0PWM4 on PH4 -#define GPIO_PCTL_PH4_PHA0 0x00050000 // PHA0 on PH4 -#define GPIO_PCTL_PH4_WT3CCP0 0x00070000 // WT3CCP0 on PH4 -#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask -#define GPIO_PCTL_PH3_SSI3TX 0x00002000 // SSI3TX on PH3 -#define GPIO_PCTL_PH3_M0PWM3 0x00004000 // M0PWM3 on PH3 -#define GPIO_PCTL_PH3_M0FAULT3 0x00006000 // M0FAULT3 on PH3 -#define GPIO_PCTL_PH3_WT5CCP1 0x00007000 // WT5CCP1 on PH3 -#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask -#define GPIO_PCTL_PH2_SSI3RX 0x00000200 // SSI3RX on PH2 -#define GPIO_PCTL_PH2_M0PWM2 0x00000400 // M0PWM2 on PH2 -#define GPIO_PCTL_PH2_M0FAULT2 0x00000600 // M0FAULT2 on PH2 -#define GPIO_PCTL_PH2_WT5CCP0 0x00000700 // WT5CCP0 on PH2 -#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask -#define GPIO_PCTL_PH1_SSI3FSS 0x00000020 // SSI3FSS on PH1 -#define GPIO_PCTL_PH1_M0PWM1 0x00000040 // M0PWM1 on PH1 -#define GPIO_PCTL_PH1_IDX0 0x00000050 // IDX0 on PH1 -#define GPIO_PCTL_PH1_M0FAULT1 0x00000060 // M0FAULT1 on PH1 -#define GPIO_PCTL_PH1_WT2CCP1 0x00000070 // WT2CCP1 on PH1 -#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask -#define GPIO_PCTL_PH0_SSI3CLK 0x00000002 // SSI3CLK on PH0 -#define GPIO_PCTL_PH0_M0PWM0 0x00000004 // M0PWM0 on PH0 -#define GPIO_PCTL_PH0_M0FAULT0 0x00000006 // M0FAULT0 on PH0 -#define GPIO_PCTL_PH0_WT2CCP0 0x00000007 // WT2CCP0 on PH0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port J. -// -//***************************************************************************** -#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask -#define GPIO_PCTL_PJ5_U6TX 0x00100000 // U6TX on PJ5 -#define GPIO_PCTL_PJ5_T3CCP1 0x00700000 // T3CCP1 on PJ5 -#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask -#define GPIO_PCTL_PJ4_U6RX 0x00010000 // U6RX on PJ4 -#define GPIO_PCTL_PJ4_T3CCP0 0x00070000 // T3CCP0 on PJ4 -#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask -#define GPIO_PCTL_PJ3_U5TX 0x00001000 // U5TX on PJ3 -#define GPIO_PCTL_PJ3_T2CCP1 0x00007000 // T2CCP1 on PJ3 -#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask -#define GPIO_PCTL_PJ2_U5RX 0x00000100 // U5RX on PJ2 -#define GPIO_PCTL_PJ2_IDX0 0x00000500 // IDX0 on PJ2 -#define GPIO_PCTL_PJ2_T2CCP0 0x00000700 // T2CCP0 on PJ2 -#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask -#define GPIO_PCTL_PJ1_U4TX 0x00000010 // U4TX on PJ1 -#define GPIO_PCTL_PJ1_T1CCP1 0x00000070 // T1CCP1 on PJ1 -#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask -#define GPIO_PCTL_PJ0_U4RX 0x00000001 // U4RX on PJ0 -#define GPIO_PCTL_PJ0_T1CCP0 0x00000007 // T1CCP0 on PJ0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port K. -// -//***************************************************************************** -#define GPIO_PCTL_PK7_M 0xF0000000 // PK7 Mask -#define GPIO_PCTL_PK7_M0FAULT3 0x60000000 // M0FAULT3 on PK7 -#define GPIO_PCTL_PK7_WT1CCP1 0x70000000 // WT1CCP1 on PK7 -#define GPIO_PCTL_PK6_M 0x0F000000 // PK6 Mask -#define GPIO_PCTL_PK6_M0FAULT2 0x06000000 // M0FAULT2 on PK6 -#define GPIO_PCTL_PK6_WT1CCP0 0x07000000 // WT1CCP0 on PK6 -#define GPIO_PCTL_PK6_C2O 0x08000000 // C2O on PK6 -#define GPIO_PCTL_PK5_M 0x00F00000 // PK5 Mask -#define GPIO_PCTL_PK5_U7TX 0x00100000 // U7TX on PK5 -#define GPIO_PCTL_PK5_M0FAULT1 0x00600000 // M0FAULT1 on PK5 -#define GPIO_PCTL_PK5_C1O 0x00800000 // C1O on PK5 -#define GPIO_PCTL_PK4_M 0x000F0000 // PK4 Mask -#define GPIO_PCTL_PK4_U7RX 0x00010000 // U7RX on PK4 -#define GPIO_PCTL_PK4_M0FAULT0 0x00060000 // M0FAULT0 on PK4 -#define GPIO_PCTL_PK4_RTCCLK 0x00070000 // RTCCLK on PK4 -#define GPIO_PCTL_PK4_C0O 0x00080000 // C0O on PK4 -#define GPIO_PCTL_PK3_M 0x0000F000 // PK3 Mask -#define GPIO_PCTL_PK3_SSI3TX 0x00002000 // SSI3TX on PK3 -#define GPIO_PCTL_PK3_M1FAULT3 0x00006000 // M1FAULT3 on PK3 -#define GPIO_PCTL_PK2_M 0x00000F00 // PK2 Mask -#define GPIO_PCTL_PK2_SSI3RX 0x00000200 // SSI3RX on PK2 -#define GPIO_PCTL_PK2_M1FAULT2 0x00000600 // M1FAULT2 on PK2 -#define GPIO_PCTL_PK1_M 0x000000F0 // PK1 Mask -#define GPIO_PCTL_PK1_SSI3FSS 0x00000020 // SSI3FSS on PK1 -#define GPIO_PCTL_PK1_M1FAULT1 0x00000060 // M1FAULT1 on PK1 -#define GPIO_PCTL_PK0_M 0x0000000F // PK0 Mask -#define GPIO_PCTL_PK0_SSI3CLK 0x00000002 // SSI3CLK on PK0 -#define GPIO_PCTL_PK0_M1FAULT0 0x00000006 // M1FAULT0 on PK0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port L. -// -//***************************************************************************** -#define GPIO_PCTL_PL7_M 0xF0000000 // PL7 Mask -#define GPIO_PCTL_PL7_T3CCP1 0x70000000 // T3CCP1 on PL7 -#define GPIO_PCTL_PL7_WT3CCP1 0x80000000 // WT3CCP1 on PL7 -#define GPIO_PCTL_PL6_M 0x0F000000 // PL6 Mask -#define GPIO_PCTL_PL6_T3CCP0 0x07000000 // T3CCP0 on PL6 -#define GPIO_PCTL_PL6_WT3CCP0 0x08000000 // WT3CCP0 on PL6 -#define GPIO_PCTL_PL5_M 0x00F00000 // PL5 Mask -#define GPIO_PCTL_PL5_T2CCP1 0x00700000 // T2CCP1 on PL5 -#define GPIO_PCTL_PL5_WT2CCP1 0x00800000 // WT2CCP1 on PL5 -#define GPIO_PCTL_PL5_LPC0RESET_N \ - 0x00F00000 // LPC0RESET_N on PL5 -#define GPIO_PCTL_PL4_M 0x000F0000 // PL4 Mask -#define GPIO_PCTL_PL4_T2CCP0 0x00070000 // T2CCP0 on PL4 -#define GPIO_PCTL_PL4_WT2CCP0 0x00080000 // WT2CCP0 on PL4 -#define GPIO_PCTL_PL4_LPC0FRAME_N \ - 0x000F0000 // LPC0FRAME_N on PL4 -#define GPIO_PCTL_PL3_M 0x0000F000 // PL3 Mask -#define GPIO_PCTL_PL3_T1CCP1 0x00007000 // T1CCP1 on PL3 -#define GPIO_PCTL_PL3_WT1CCP1 0x00008000 // WT1CCP1 on PL3 -#define GPIO_PCTL_PL2_M 0x00000F00 // PL2 Mask -#define GPIO_PCTL_PL2_T1CCP0 0x00000700 // T1CCP0 on PL2 -#define GPIO_PCTL_PL2_WT1CCP0 0x00000800 // WT1CCP0 on PL2 -#define GPIO_PCTL_PL1_M 0x000000F0 // PL1 Mask -#define GPIO_PCTL_PL1_T0CCP1 0x00000070 // T0CCP1 on PL1 -#define GPIO_PCTL_PL1_WT0CCP1 0x00000080 // WT0CCP1 on PL1 -#define GPIO_PCTL_PL0_M 0x0000000F // PL0 Mask -#define GPIO_PCTL_PL0_T0CCP0 0x00000007 // T0CCP0 on PL0 -#define GPIO_PCTL_PL0_WT0CCP0 0x00000008 // WT0CCP0 on PL0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port M. -// -//***************************************************************************** -#define GPIO_PCTL_PM7_M 0xF0000000 // PM7 Mask -#define GPIO_PCTL_PM7_M0PWM5 0x20000000 // M0PWM5 on PM7 -#define GPIO_PCTL_PM7_WT0CCP1 0x70000000 // WT0CCP1 on PM7 -#define GPIO_PCTL_PM6_M 0x0F000000 // PM6 Mask -#define GPIO_PCTL_PM6_M0PWM4 0x02000000 // M0PWM4 on PM6 -#define GPIO_PCTL_PM6_WT0CCP0 0x07000000 // WT0CCP0 on PM6 -#define GPIO_PCTL_PM3_M 0x0000F000 // PM3 Mask -#define GPIO_PCTL_PM3_T5CCP1 0x00007000 // T5CCP1 on PM3 -#define GPIO_PCTL_PM3_WT5CCP1 0x00008000 // WT5CCP1 on PM3 -#define GPIO_PCTL_PM2_M 0x00000F00 // PM2 Mask -#define GPIO_PCTL_PM2_T5CCP0 0x00000700 // T5CCP0 on PM2 -#define GPIO_PCTL_PM2_WT5CCP0 0x00000800 // WT5CCP0 on PM2 -#define GPIO_PCTL_PM2_LPC0CLKRUN_N \ - 0x00000F00 // LPC0CLKRUN_N on PM2 -#define GPIO_PCTL_PM1_M 0x000000F0 // PM1 Mask -#define GPIO_PCTL_PM1_T4CCP1 0x00000070 // T4CCP1 on PM1 -#define GPIO_PCTL_PM1_WT4CCP1 0x00000080 // WT4CCP1 on PM1 -#define GPIO_PCTL_PM1_LPC0SCI_N 0x000000F0 // LPC0SCI_N on PM1 -#define GPIO_PCTL_PM0_M 0x0000000F // PM0 Mask -#define GPIO_PCTL_PM0_T4CCP0 0x00000007 // T4CCP0 on PM0 -#define GPIO_PCTL_PM0_WT4CCP0 0x00000008 // WT4CCP0 on PM0 -#define GPIO_PCTL_PM0_LPC0PD_N 0x0000000F // LPC0PD_N on PM0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port N. -// -//***************************************************************************** -#define GPIO_PCTL_PN7_M 0xF0000000 // PN7 Mask -#define GPIO_PCTL_PN7_M1PWM7 0x20000000 // M1PWM7 on PN7 -#define GPIO_PCTL_PN7_WT4CCP1 0x70000000 // WT4CCP1 on PN7 -#define GPIO_PCTL_PN6_M 0x0F000000 // PN6 Mask -#define GPIO_PCTL_PN6_M1PWM6 0x02000000 // M1PWM6 on PN6 -#define GPIO_PCTL_PN6_WT4CCP0 0x07000000 // WT4CCP0 on PN6 -#define GPIO_PCTL_PN5_M 0x00F00000 // PN5 Mask -#define GPIO_PCTL_PN5_M1PWM5 0x00200000 // M1PWM5 on PN5 -#define GPIO_PCTL_PN5_WT3CCP1 0x00700000 // WT3CCP1 on PN5 -#define GPIO_PCTL_PN4_M 0x000F0000 // PN4 Mask -#define GPIO_PCTL_PN4_M1PWM4 0x00020000 // M1PWM4 on PN4 -#define GPIO_PCTL_PN4_WT3CCP0 0x00070000 // WT3CCP0 on PN4 -#define GPIO_PCTL_PN3_M 0x0000F000 // PN3 Mask -#define GPIO_PCTL_PN3_M0PWM7 0x00002000 // M0PWM7 on PN3 -#define GPIO_PCTL_PN3_WT2CCP1 0x00007000 // WT2CCP1 on PN3 -#define GPIO_PCTL_PN2_M 0x00000F00 // PN2 Mask -#define GPIO_PCTL_PN2_M0PWM6 0x00000200 // M0PWM6 on PN2 -#define GPIO_PCTL_PN2_WT2CCP0 0x00000700 // WT2CCP0 on PN2 -#define GPIO_PCTL_PN1_M 0x000000F0 // PN1 Mask -#define GPIO_PCTL_PN1_CAN0TX 0x00000010 // CAN0TX on PN1 -#define GPIO_PCTL_PN0_M 0x0000000F // PN0 Mask -#define GPIO_PCTL_PN0_CAN0RX 0x00000001 // CAN0RX on PN0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_PCTL register for -// port P. -// -//***************************************************************************** -#define GPIO_PCTL_PP2_M 0x00000F00 // PP2 Mask -#define GPIO_PCTL_PP2_M0PWM2 0x00000100 // M0PWM2 on PP2 -#define GPIO_PCTL_PP2_T5CCP0 0x00000700 // T5CCP0 on PP2 -#define GPIO_PCTL_PP1_M 0x000000F0 // PP1 Mask -#define GPIO_PCTL_PP1_M0PWM1 0x00000010 // M0PWM1 on PP1 -#define GPIO_PCTL_PP1_T4CCP1 0x00000070 // T4CCP1 on PP1 -#define GPIO_PCTL_PP0_M 0x0000000F // PP0 Mask -#define GPIO_PCTL_PP0_M0PWM0 0x00000001 // M0PWM0 on PP0 -#define GPIO_PCTL_PP0_T4CCP0 0x00000007 // T4CCP0 on PP0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR0 register. -// -//***************************************************************************** -#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate -#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase -#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity -#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select -#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format -#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous - // Serial Frame Format -#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format -#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select -#define SSI_CR0_DSS_4 0x00000003 // 4-bit data -#define SSI_CR0_DSS_5 0x00000004 // 5-bit data -#define SSI_CR0_DSS_6 0x00000005 // 6-bit data -#define SSI_CR0_DSS_7 0x00000006 // 7-bit data -#define SSI_CR0_DSS_8 0x00000007 // 8-bit data -#define SSI_CR0_DSS_9 0x00000008 // 9-bit data -#define SSI_CR0_DSS_10 0x00000009 // 10-bit data -#define SSI_CR0_DSS_11 0x0000000A // 11-bit data -#define SSI_CR0_DSS_12 0x0000000B // 12-bit data -#define SSI_CR0_DSS_13 0x0000000C // 13-bit data -#define SSI_CR0_DSS_14 0x0000000D // 14-bit data -#define SSI_CR0_DSS_15 0x0000000E // 15-bit data -#define SSI_CR0_DSS_16 0x0000000F // 16-bit data -#define SSI_CR0_SCR_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR1 register. -// -//***************************************************************************** -#define SSI_CR1_EOT 0x00000010 // End of Transmission -#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable -#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select -#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port - // Enable -#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DR register. -// -//***************************************************************************** -#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_SR register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI Busy Bit -#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full -#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty -#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full -#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CPSR register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_IM register. -// -//***************************************************************************** -#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask -#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask -#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt - // Mask -#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_RIS register. -// -//***************************************************************************** -#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt - // Status -#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt - // Status -#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw - // Interrupt Status -#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_MIS register. -// -//***************************************************************************** -#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked - // Interrupt Status -#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked - // Interrupt Status -#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked - // Interrupt Status -#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_ICR register. -// -//***************************************************************************** -#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt - // Clear -#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DMACTL register. -// -//***************************************************************************** -#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CC register. -// -//***************************************************************************** -#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source -#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the - // PLL bypass is in effect) or the - // PLL output (default) -#define SSI_CC_CS_PIOSC 0x00000001 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//***************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//***************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//***************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//***************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//***************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_LIN 0x00000040 // LIN Mode Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//***************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full -#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full -#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) -#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full -#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full -#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full -#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) -#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full -#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//***************************************************************************** -#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask -#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask -#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt - // Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//***************************************************************************** -#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt - // Status -#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt - // Status -#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw - // Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//***************************************************************************** -#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt - // Status -#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt - // Status -#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked - // Interrupt Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//***************************************************************************** -#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear -#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear -#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt - // Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//***************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCTL register. -// -//***************************************************************************** -#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length -#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits - // (default) -#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits -#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits -#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits -#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LSS register. -// -//***************************************************************************** -#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot -#define UART_LSS_TSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LTIM register. -// -//***************************************************************************** -#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value -#define UART_LTIM_TIMER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITADDR -// register. -// -//***************************************************************************** -#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode -#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode -#define UART_9BITADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITAMASK -// register. -// -//***************************************************************************** -#define UART_9BITAMASK_RANGE_M 0x0000FF00 // Self Address Range for 9-Bit - // Mode -#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode -#define UART_9BITAMASK_RANGE_S 8 -#define UART_9BITAMASK_MASK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//***************************************************************************** -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//***************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source -#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default) -#define UART_CC_CS_PIOSC 0x00000001 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//***************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_RS 0x00000001 // Receive not send -#define I2C_MSA_SA_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//***************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//***************************************************************************** -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -#define I2C_SCSR_RREQ 0x00000001 // Receive Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//***************************************************************************** -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_STOP 0x00000004 // Generate STOP -#define I2C_MCS_START 0x00000002 // Generate START -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_RUN 0x00000001 // I2C Master Enable -#define I2C_MCS_BUSY 0x00000001 // I2C Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//***************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//***************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // Data Transferred -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//***************************************************************************** -#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//***************************************************************************** -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//***************************************************************************** -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//***************************************************************************** -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//***************************************************************************** -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//***************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//***************************************************************************** -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//***************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//***************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//***************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//***************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CTL register. -// -//***************************************************************************** -#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 -#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_SYNC register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter -#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENABLE register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable -#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INVERT register. -// -//***************************************************************************** -#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal -#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal -#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal -#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal -#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal -#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal -#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal -#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULT register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault -#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INTEN register. -// -//***************************************************************************** -#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 -#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 -#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 -#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 -#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable -#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_RIS register. -// -//***************************************************************************** -#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 -#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 -#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 -#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 -#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted -#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ISC register. -// -//***************************************************************************** -#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted -#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted -#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted -#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted -#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status -#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_STATUS register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status -#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status -#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status -#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULTVAL register. -// -//***************************************************************************** -#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value -#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value -#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value -#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value -#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value -#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value -#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value -#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENUPD register. -// -//***************************************************************************** -#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode -#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized -#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized -#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode -#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized -#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized -#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode -#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized -#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized -#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode -#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized -#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized -#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode -#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized -#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized -#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode -#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized -#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized -#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode -#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized -#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized -#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode -#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized -#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CTL register. -// -//***************************************************************************** -#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_X_CTL_MODE 0x00000002 // Counter Mode -#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_INTEN register. -// -//***************************************************************************** -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_RIS register. -// -//***************************************************************************** -#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_ISC register. -// -//***************************************************************************** -#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_LOAD register. -// -//***************************************************************************** -#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_X_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_COUNT register. -// -//***************************************************************************** -#define PWM_X_COUNT_M 0x0000FFFF // Counter Value -#define PWM_X_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPA register. -// -//***************************************************************************** -#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_X_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPB register. -// -//***************************************************************************** -#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_X_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENA register. -// -//***************************************************************************** -#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_X_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_X_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_X_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_X_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENB register. -// -//***************************************************************************** -#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_X_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_X_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_X_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_X_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBCTL register. -// -//***************************************************************************** -#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBRISE register. -// -//***************************************************************************** -#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_X_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBFALL register. -// -//***************************************************************************** -#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_X_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_X_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. -// -//***************************************************************************** -#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_PP register. -// -//***************************************************************************** -#define PWM_PP_ONE 0x00000400 // One-Shot Mode -#define PWM_PP_EFAULT 0x00000200 // Extended Fault -#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization -#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs -#define PWM_PP_GCNT_M 0x0000000F // Generators -#define PWM_PP_FCNT_S 4 -#define PWM_PP_GCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_PC register. -// -//***************************************************************************** -#define PWM_PC_USEOPWMDIV 0x00000100 // Enable PWM Clock Divisor -#define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor -#define PWM_PC_PWMDIV_2 0x00000000 // /2 -#define PWM_PC_PWMDIV_4 0x00000001 // /4 -#define PWM_PC_PWMDIV_8 0x00000002 // /8 -#define PWM_PC_PWMDIV_16 0x00000003 // /16 -#define PWM_PC_PWMDIV_32 0x00000004 // /32 -#define PWM_PC_PWMDIV_64 0x00000007 // /64 (default) - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_CTL register. -// -//***************************************************************************** -#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count -#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter -#define QEI_CTL_STALLEN 0x00001000 // Stall QEI -#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse -#define QEI_CTL_INVB 0x00000400 // Invert PhB -#define QEI_CTL_INVA 0x00000200 // Invert PhA -#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity -#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 -#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 -#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 -#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 -#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 -#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 -#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 -#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 -#define QEI_CTL_VELEN 0x00000020 // Capture Velocity -#define QEI_CTL_RESMODE 0x00000010 // Reset Mode -#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode -#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode -#define QEI_CTL_SWAP 0x00000002 // Swap Signals -#define QEI_CTL_ENABLE 0x00000001 // Enable QEI -#define QEI_CTL_FILTCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation -#define QEI_STAT_ERROR 0x00000001 // Error Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator - // Value -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator - // Value -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Velocity -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable -#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt - // Enable -#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable -#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected -#define QEI_RIS_DIR 0x00000004 // Direction Change Detected -#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired -#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_ISC register. -// -//***************************************************************************** -#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt -#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt -#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt -#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) - // counter configuration -#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The - // function is controlled by bits - // 1:0 of GPTMTAMR and GPTMTBMR - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer - // 5 -#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not - // affected -#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 5 is triggered -#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer - // 4 -#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not - // affected -#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 4 is triggered -#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer - // 3 -#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not - // affected -#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 3 is triggered -#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer - // 2 -#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not - // affected -#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 2 is triggered -#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer - // 1 -#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not - // affected -#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 1 is triggered -#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer - // 0 -#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not - // affected -#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 0 is triggered -#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer - // 5 -#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not - // affected -#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of - // GPTM 16/32-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of - // GPTM 16/32-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM 16/32-Bit - // Timer 5 is triggered -#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer - // 4 -#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not - // affected -#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of - // GPTM 16/32-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of - // GPTM 16/32-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM 16/32-Bit - // Timer 4 is triggered -#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer - // 3 -#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not - // affected -#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of - // GPTM 16/32-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of - // GPTM 16/32-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM 16/32-Bit - // Timer 3 is triggered -#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer - // 2 -#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not - // affected -#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of - // GPTM 16/32-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of - // GPTM 16/32-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM 16/32-Bit - // Timer 2 is triggered -#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer - // 1 -#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not - // affected -#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of - // GPTM 16/32-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of - // GPTM 16/32-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM 16/32-Bit - // Timer 1 is triggered -#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer - // 0 -#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not - // affected -#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of - // GPTM 16/32-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of - // GPTM 16/32-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM 16/32-Bit - // Timer 0 is triggered - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update - // Error Interrupt Mask -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match - // Interrupt Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt - // Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt - // Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match - // Interrupt Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt - // Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt - // Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update - // Error Raw Interrupt Status -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw - // Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw - // Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw - // Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw - // Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw - // Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw - // Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update - // Error Masked Interrupt Status -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked - // Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked - // Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked - // Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked - // Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update - // Error Interrupt Clear -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match - // Interrupt Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt - // Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt - // Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match - // Interrupt Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt - // Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt - // Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -#define TIMER_TAILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -#define TIMER_TAMATCHR_TAMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -#define TIMER_TBMATCHR_TBMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -#define TIMER_TAPR_TAPSRH_S 8 -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -#define TIMER_TBPR_TBPSRH_S 8 -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High - // Byte -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -#define TIMER_TAPMR_TAPSMRH_S 8 -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High - // Byte -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -#define TIMER_TBPMR_TBPSMRH_S 8 -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -#define TIMER_TAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -#define TIMER_TBR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -#define TIMER_TAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPV register. -// -//***************************************************************************** -#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TAPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPV register. -// -//***************************************************************************** -#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value -#define TIMER_TBPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are - // 32 bits each with a 16-bit - // prescale counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt - // Status -#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_IM register. -// -//***************************************************************************** -#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on - // SS3 -#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on - // SS2 -#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on - // SS1 -#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on - // SS0 -#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ISC register. -// -//***************************************************************************** -#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt - // Status on SS3 -#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt - // Status on SS2 -#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt - // Status on SS1 -#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt - // Status on SS0 -#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4) -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 -#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3 -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4) -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 -#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3 -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4) -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 -#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3 -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4) -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 -#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3 -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_TSSEL register. -// -//***************************************************************************** -#define ADC_TSSEL_PS3_M 0x03000000 // PWM Unit Select -#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0 -#define ADC_TSSEL_PS3_1 0x01000000 // PWM Unit 1 -#define ADC_TSSEL_PS2_M 0x00030000 // PWM Unit Select -#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0 -#define ADC_TSSEL_PS2_1 0x00010000 // PWM Unit 1 -#define ADC_TSSEL_PS1_M 0x00000300 // PWM Unit Select -#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0 -#define ADC_TSSEL_PS1_1 0x00000100 // PWM Unit 1 -#define ADC_TSSEL_PS0_M 0x00000003 // PWM Unit Select -#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0 -#define ADC_TSSEL_PS0_1 0x00000001 // PWM Unit 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SPC register. -// -//***************************************************************************** -#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference -#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 -#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 -#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 -#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 -#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 -#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 -#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 -#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 -#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 -#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 -#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 -#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 -#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 -#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 -#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 -#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize -#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait -#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCISC register. -// -//***************************************************************************** -#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CTL register. -// -//***************************************************************************** -#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select -#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the - // voltage reference -#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is - // the voltage reference. The ADC - // conversion range is 0.0 V to the - // external reference value - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX0 register. -// -//***************************************************************************** -#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL0 register. -// -//***************************************************************************** -#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select -#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select -#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select -#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select -#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select -#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select -#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select -#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. -// -//***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. -// -//***************************************************************************** -#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP0 register. -// -//***************************************************************************** -#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator - // Operation -#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator - // Operation -#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator - // Operation -#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator - // Operation -#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC0 register. -// -//***************************************************************************** -#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator - // Select -#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator - // Select -#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator - // Select -#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_S 24 -#define ADC_SSDC0_S5DCSEL_S 20 -#define ADC_SSDC0_S4DCSEL_S 16 -#define ADC_SSDC0_S3DCSEL_S 12 -#define ADC_SSDC0_S2DCSEL_S 8 -#define ADC_SSDC0_S1DCSEL_S 4 -#define ADC_SSDC0_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. -// -//***************************************************************************** -#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX1 register. -// -//***************************************************************************** -#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL1 register. -// -//***************************************************************************** -#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select -#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select -#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select -#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. -// -//***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. -// -//***************************************************************************** -#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP1 register. -// -//***************************************************************************** -#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC1 register. -// -//***************************************************************************** -#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_S 8 -#define ADC_SSDC1_S1DCSEL_S 4 -#define ADC_SSDC1_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. -// -//***************************************************************************** -#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX2 register. -// -//***************************************************************************** -#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL2 register. -// -//***************************************************************************** -#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select -#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select -#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select -#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. -// -//***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. -// -//***************************************************************************** -#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP2 register. -// -//***************************************************************************** -#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC2 register. -// -//***************************************************************************** -#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_S 8 -#define ADC_SSDC2_S1DCSEL_S 4 -#define ADC_SSDC2_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. -// -//***************************************************************************** -#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX3 register. -// -//***************************************************************************** -#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL3 register. -// -//***************************************************************************** -#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. -// -//***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. -// -//***************************************************************************** -#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP3 register. -// -//***************************************************************************** -#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC3 register. -// -//***************************************************************************** -#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. -// -//***************************************************************************** -#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCRIC register. -// -//***************************************************************************** -#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 -#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 -#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 -#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 -#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 -#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 -#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 -#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 -#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 -#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 -#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 -#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 -#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 -#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 -#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 -#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL0 register. -// -//***************************************************************************** -#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL1 register. -// -//***************************************************************************** -#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL2 register. -// -//***************************************************************************** -#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL3 register. -// -//***************************************************************************** -#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL4 register. -// -//***************************************************************************** -#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL5 register. -// -//***************************************************************************** -#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL6 register. -// -//***************************************************************************** -#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL7 register. -// -//***************************************************************************** -#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP0 register. -// -//***************************************************************************** -#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP0_COMP1_S 16 -#define ADC_DCCMP0_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP1 register. -// -//***************************************************************************** -#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP1_COMP1_S 16 -#define ADC_DCCMP1_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP2 register. -// -//***************************************************************************** -#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP2_COMP1_S 16 -#define ADC_DCCMP2_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP3 register. -// -//***************************************************************************** -#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP3_COMP1_S 16 -#define ADC_DCCMP3_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP4 register. -// -//***************************************************************************** -#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP4_COMP1_S 16 -#define ADC_DCCMP4_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP5 register. -// -//***************************************************************************** -#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP5_COMP1_S 16 -#define ADC_DCCMP5_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP6 register. -// -//***************************************************************************** -#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP6_COMP1_S 16 -#define ADC_DCCMP6_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP7 register. -// -//***************************************************************************** -#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP7_COMP1_S 16 -#define ADC_DCCMP7_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PP register. -// -//***************************************************************************** -#define ADC_PP_TS 0x00800000 // Temperature Sensor -#define ADC_PP_RSL_M 0x007C0000 // Resolution -#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture -#define ADC_PP_TYPE_SAR 0x00000000 // SAR -#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count -#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count -#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate -#define ADC_PP_MSR_125K 0x00000001 // 125 ksps -#define ADC_PP_MSR_250K 0x00000003 // 250 ksps -#define ADC_PP_MSR_500K 0x00000005 // 500 ksps -#define ADC_PP_MSR_1M 0x00000007 // 1 Msps -#define ADC_PP_RSL_S 18 -#define ADC_PP_DC_S 10 -#define ADC_PP_CH_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PC register. -// -//***************************************************************************** -#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate -#define ADC_PC_SR_125K 0x00000001 // 125 ksps -#define ADC_PC_SR_250K 0x00000003 // 250 ksps -#define ADC_PC_SR_500K 0x00000005 // 500 ksps -#define ADC_PC_SR_1M 0x00000007 // 1 Msps - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CC register. -// -//***************************************************************************** -#define ADC_CC_CS_M 0x0000000F // ADC Clock Source -#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the - // PLL bypass is in effect) or the - // 16 MHz clock derived from PLL / - // 25 (default) -#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACMIS register. -// -//***************************************************************************** -#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt - // Status -#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt - // Status -#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACRIS register. -// -//***************************************************************************** -#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status -#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status -#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACINTEN register. -// -//***************************************************************************** -#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable -#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable -#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACREFCTL -// register. -// -//***************************************************************************** -#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable -#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range -#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref -#define COMP_ACREFCTL_VREF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. -// -//***************************************************************************** -#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL0 register. -// -//***************************************************************************** -#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference - // (VIREF) -#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. -// -//***************************************************************************** -#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL1 register. -// -//***************************************************************************** -#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference - // (VIREF) -#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. -// -//***************************************************************************** -#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL2 register. -// -//***************************************************************************** -#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference - // (VIREF) -#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_PP register. -// -//***************************************************************************** -#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present -#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present -#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present -#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present -#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present -#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus-Off Status -#define CAN_STS_EWARN 0x00000040 // Warning Status -#define CAN_STS_EPASS 0x00000020 // Error Passive -#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully -#define CAN_STS_TXOK 0x00000008 // Transmitted a Message - // Successfully -#define CAN_STS_LEC_M 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No Error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error -#define CAN_STS_LEC_FORM 0x00000002 // Format Error -#define CAN_STS_LEC_ACK 0x00000003 // ACK Error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error -#define CAN_STS_LEC_CRC 0x00000006 // CRC Error -#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Received Error Passive -#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter -#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter -#define CAN_ERR_REC_S 8 -#define CAN_ERR_TEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point -#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point -#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width -#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler -#define CAN_BIT_TSEG2_S 12 -#define CAN_BIT_TSEG1_S 8 -#define CAN_BIT_SJW_S 6 -#define CAN_BIT_BRP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // Receive Observation -#define CAN_TST_TX_M 0x00000060 // Transmit Control -#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point -#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low -#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High -#define CAN_TST_LBACK 0x00000010 // Loopback Mode -#define CAN_TST_SILENT 0x00000008 // Silent Mode -#define CAN_TST_BASIC 0x00000004 // Basic Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension -#define CAN_BRPE_BRPE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CRQ register. -// -//***************************************************************************** -#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF1CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CMSK register. -// -//***************************************************************************** -#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. -// -//***************************************************************************** -#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF1MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. -// -//***************************************************************************** -#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF1MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. -// -//***************************************************************************** -#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF1ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. -// -//***************************************************************************** -#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF1ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MCTL register. -// -//***************************************************************************** -#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF1MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA1 register. -// -//***************************************************************************** -#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA2 register. -// -//***************************************************************************** -#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB1 register. -// -//***************************************************************************** -#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB2 register. -// -//***************************************************************************** -#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CRQ register. -// -//***************************************************************************** -#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF2CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CMSK register. -// -//***************************************************************************** -#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. -// -//***************************************************************************** -#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF2MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. -// -//***************************************************************************** -#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF2MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. -// -//***************************************************************************** -#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF2ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. -// -//***************************************************************************** -#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF2ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MCTL register. -// -//***************************************************************************** -#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF2MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA1 register. -// -//***************************************************************************** -#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA2 register. -// -//***************************************************************************** -#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB1 register. -// -//***************************************************************************** -#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB2 register. -// -//***************************************************************************** -#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ1_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ2_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA1_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA2_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1INT register. -// -//***************************************************************************** -#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG1INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2INT register. -// -//***************************************************************************** -#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG2INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1VAL register. -// -//***************************************************************************** -#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG1VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2VAL register. -// -//***************************************************************************** -#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG2VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FADDR register. -// -//***************************************************************************** -#define USB_FADDR_M 0x0000007F // Function Address -#define USB_FADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_POWER register. -// -//***************************************************************************** -#define USB_POWER_ISOUP 0x00000080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_RESET 0x00000008 // RESET Signaling -#define USB_POWER_RESUME 0x00000004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIS register. -// -//***************************************************************************** -#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt -#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt -#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt -#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt -#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt -#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt -#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt -#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIS register. -// -//***************************************************************************** -#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt -#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt -#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt -#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt -#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt -#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt -#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIE register. -// -//***************************************************************************** -#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable -#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable -#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable -#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable -#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable -#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable -#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable -#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIE register. -// -//***************************************************************************** -#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable -#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable -#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable -#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable -#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable -#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable -#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IS register. -// -//***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST -#define USB_IS_DISCON 0x00000020 // Session Disconnect -#define USB_IS_CONN 0x00000010 // Session Connect -#define USB_IS_SOF 0x00000008 // Start of Frame -#define USB_IS_BABBLE 0x00000004 // Babble Detected -#define USB_IS_RESET 0x00000004 // RESET Signaling Detected -#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IE register. -// -//***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt -#define USB_IE_SESREQ 0x00000040 // Enable Session Request -#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt -#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt -#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FRAME register. -// -//***************************************************************************** -#define USB_FRAME_M 0x000007FF // Frame Number -#define USB_FRAME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPIDX register. -// -//***************************************************************************** -#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index -#define USB_EPIDX_EPIDX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TEST register. -// -//***************************************************************************** -#define USB_TEST_FORCEH 0x00000080 // Force Host Mode -#define USB_TEST_FIFOACC 0x00000040 // FIFO Access -#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO0 register. -// -//***************************************************************************** -#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO0_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO1 register. -// -//***************************************************************************** -#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO1_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO2 register. -// -//***************************************************************************** -#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO2_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO3 register. -// -//***************************************************************************** -#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO3_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO4 register. -// -//***************************************************************************** -#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO4_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO5 register. -// -//***************************************************************************** -#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO5_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO6 register. -// -//***************************************************************************** -#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO6_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO7 register. -// -//***************************************************************************** -#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO7_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DEVCTL register. -// -//***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode -#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level -#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. -// -//***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. -// -//***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOADD -// register. -// -//***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_TXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOADD -// register. -// -//***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_RXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CONTIM register. -// -//***************************************************************************** -#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x0000000F // Wait ID -#define USB_CONTIM_WTCON_S 4 -#define USB_CONTIM_WTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VPLEN register. -// -//***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length -#define USB_VPLEN_VPLEN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FSEOF register. -// -//***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap -#define USB_FSEOF_FSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LSEOF register. -// -//***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap -#define USB_LSEOF_LSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR0 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT0 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT0_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRL0 register. -// -//***************************************************************************** -#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear -#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x00000020 // Request Packet -#define USB_CSRL0_STALL 0x00000020 // Send Stall -#define USB_CSRL0_SETEND 0x00000010 // Setup End -#define USB_CSRL0_ERROR 0x00000010 // Error -#define USB_CSRL0_DATAEND 0x00000008 // Data End -#define USB_CSRL0_SETUP 0x00000008 // Setup Packet -#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRH0 register. -// -//***************************************************************************** -#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x00000002 // Data Toggle -#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_COUNT0 register. -// -//***************************************************************************** -#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count -#define USB_COUNT0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TYPE0 register. -// -//***************************************************************************** -#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_FULL 0x00000080 // Full -#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_NAKLMT register. -// -//***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit -#define USB_NAKLMT_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP1 register. -// -//***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL1 register. -// -//***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x00000010 // Send STALL -#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x00000004 // Error -#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH1 register. -// -//***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x00000020 // Mode -#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP1 register. -// -//***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL1 register. -// -//***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x00000020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x00000004 // Overrun -#define USB_RXCSRL1_ERROR 0x00000004 // Error -#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH1 register. -// -//***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. -// -//***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT1_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE1 register. -// -//***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ - 0 -#define USB_TXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE1 register. -// -//***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ - 0 -#define USB_RXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP2 register. -// -//***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL2 register. -// -//***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL2_STALL 0x00000010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x00000004 // Error -#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH2 register. -// -//***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x00000020 // Mode -#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP2 register. -// -//***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL2 register. -// -//***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL2_STALL 0x00000020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x00000004 // Error -#define USB_RXCSRL2_OVER 0x00000004 // Overrun -#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH2 register. -// -//***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. -// -//***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT2_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE2 register. -// -//***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ - 0 -#define USB_TXINTERVAL2_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE2 register. -// -//***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ - 0 -#define USB_RXINTERVAL2_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP3 register. -// -//***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL3 register. -// -//***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL3_STALL 0x00000010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x00000004 // Error -#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH3 register. -// -//***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x00000020 // Mode -#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP3 register. -// -//***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL3 register. -// -//***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x00000020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x00000004 // Error -#define USB_RXCSRL3_OVER 0x00000004 // Overrun -#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH3 register. -// -//***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. -// -//***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT3_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE3 register. -// -//***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ - 0 -#define USB_TXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE3 register. -// -//***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ - 0 -#define USB_RXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP4 register. -// -//***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL4 register. -// -//***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL4_STALL 0x00000010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x00000004 // Error -#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH4 register. -// -//***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x00000020 // Mode -#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP4 register. -// -//***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL4 register. -// -//***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x00000020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL4_OVER 0x00000004 // Overrun -#define USB_RXCSRL4_ERROR 0x00000004 // Error -#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH4 register. -// -//***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. -// -//***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE4 register. -// -//***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ - 0 -#define USB_TXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE4 register. -// -//***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ - 0 -#define USB_RXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP5 register. -// -//***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL5 register. -// -//***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL5_STALL 0x00000010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x00000004 // Error -#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH5 register. -// -//***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x00000020 // Mode -#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP5 register. -// -//***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL5 register. -// -//***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x00000020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL5_ERROR 0x00000004 // Error -#define USB_RXCSRL5_OVER 0x00000004 // Overrun -#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH5 register. -// -//***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. -// -//***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE5 register. -// -//***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ - 0 -#define USB_TXINTERVAL5_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE5 register. -// -//***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ - 0 -#define USB_RXINTERVAL5_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP6 register. -// -//***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL6 register. -// -//***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x00000010 // Send STALL -#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x00000004 // Error -#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH6 register. -// -//***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x00000020 // Mode -#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP6 register. -// -//***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL6 register. -// -//***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL6_STALL 0x00000020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL6_ERROR 0x00000004 // Error -#define USB_RXCSRL6_OVER 0x00000004 // Overrun -#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH6 register. -// -//***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. -// -//***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE6 register. -// -//***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ - 0 -#define USB_TXINTERVAL6_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE6 register. -// -//***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ - 0 -#define USB_RXINTERVAL6_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP7 register. -// -//***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL7 register. -// -//***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x00000010 // Send STALL -#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x00000004 // Error -#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH7 register. -// -//***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x00000020 // Mode -#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP7 register. -// -//***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL7 register. -// -//***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL7_STALL 0x00000020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x00000004 // Error -#define USB_RXCSRL7_OVER 0x00000004 // Overrun -#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH7 register. -// -//***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x00000002 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. -// -//***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE7 register. -// -//***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ - 0 -#define USB_TXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE7 register. -// -//***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ - 0 -#define USB_RXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT3_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPC register. -// -//***************************************************************************** -#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x00000200 // Low -#define USB_EPC_PFLTACT_HIGH 0x00000300 // High -#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable - // Configuration -#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low -#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCRIS register. -// -//***************************************************************************** -#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCIM register. -// -//***************************************************************************** -#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCISC register. -// -//***************************************************************************** -#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRRIS register. -// -//***************************************************************************** -#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRIM register. -// -//***************************************************************************** -#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRISC register. -// -//***************************************************************************** -#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_GPCS register. -// -//***************************************************************************** -#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode -#define USB_GPCS_DEVMOD 0x00000001 // Device Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDC register. -// -//***************************************************************************** -#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCRIS register. -// -//***************************************************************************** -#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCIM register. -// -//***************************************************************************** -#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCISC register. -// -//***************************************************************************** -#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IDVRIS register. -// -//***************************************************************************** -#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IDVIM register. -// -//***************************************************************************** -#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IDVISC register. -// -//***************************************************************************** -#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMASEL register. -// -//***************************************************************************** -#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select -#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select -#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select -#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select -#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select -#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select -#define USB_DMASEL_DMACTX_S 20 -#define USB_DMASEL_DMACRX_S 16 -#define USB_DMASEL_DMABTX_S 12 -#define USB_DMASEL_DMABRX_S 8 -#define USB_DMASEL_DMAATX_S 4 -#define USB_DMASEL_DMAARX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PP register. -// -//***************************************************************************** -#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count -#define USB_PP_USB_M 0x000000C0 // USB Capability -#define USB_PP_USB_DEVICE 0x00000040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST -#define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_PHY 0x00000010 // PHY Present -#define USB_PP_TYPE_M 0x0000000F // Controller Type -#define USB_PP_TYPE_0 0x00000000 // The first-generation USB - // controller -#define USB_PP_ECNT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_RIS register. -// -//***************************************************************************** -#define SYSEXC_RIS_IXCRIS 0x00000020 // Inexact Exception Flag -#define SYSEXC_RIS_OFCRIS 0x00000010 // Overflow Exception Flag -#define SYSEXC_RIS_UFCRIS 0x00000008 // Underflow Exception Flag -#define SYSEXC_RIS_IOCRIS 0x00000004 // Invalid Operation Flag -#define SYSEXC_RIS_DZCRIS 0x00000002 // Divide By 0 Exception Flag -#define SYSEXC_RIS_IDCRIS 0x00000001 // Input Denormal Exception Flag - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IM register. -// -//***************************************************************************** -#define SYSEXC_IM_IXCIM 0x00000020 // Inexact Exception Flag -#define SYSEXC_IM_OFCIM 0x00000010 // Overflow Exception Flag -#define SYSEXC_IM_UFCIM 0x00000008 // Underflow Exception Flag -#define SYSEXC_IM_IOCIM 0x00000004 // Invalid Operation Flag -#define SYSEXC_IM_DZCIM 0x00000002 // Divide By 0 Exception Flag -#define SYSEXC_IM_IDCIM 0x00000001 // Input Denormal Exception Flag - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_MIS register. -// -//***************************************************************************** -#define SYSEXC_MIS_IXCMIS 0x00000020 // Inexact Exception Flag -#define SYSEXC_MIS_OFCMIS 0x00000010 // Overflow Exception Flag -#define SYSEXC_MIS_UFCMIS 0x00000008 // Underflow Exception Flag -#define SYSEXC_MIS_IOCMIS 0x00000004 // Invalid Operation Flag -#define SYSEXC_MIS_DZCMIS 0x00000002 // Divide By 0 Exception Flag -#define SYSEXC_MIS_IDCMIS 0x00000001 // Input Denormal Exception Flag - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IC register. -// -//***************************************************************************** -#define SYSEXC_IC_IXCIC 0x00000020 // Inexact Exception Flag -#define SYSEXC_IC_OFCIC 0x00000010 // Overflow Exception Flag -#define SYSEXC_IC_UFCIC 0x00000008 // Underflow Exception Flag -#define SYSEXC_IC_IOCIC 0x00000004 // Invalid Operation Flag -#define SYSEXC_IC_DZCIC 0x00000002 // Divide By 0 Exception Flag -#define SYSEXC_IC_IDCIC 0x00000001 // Input Denormal Exception Flag - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCC register. -// -//***************************************************************************** -#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter -#define HIB_RTCC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM0 register. -// -//***************************************************************************** -#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 -#define HIB_RTCM0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCLD register. -// -//***************************************************************************** -#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load -#define HIB_RTCLD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CTL register. -// -//***************************************************************************** -#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable -#define HIB_CTL_OSCHYS 0x00040000 // 32 -#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability -#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass -#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery - // Comparator -#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts -#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) -#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts -#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts -#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status -#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery -#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered -#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable -#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable -#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable -#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable -#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable -#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request -#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IM register. -// -//***************************************************************************** -#define HIB_IM_WC 0x00000010 // External Write Complete/Capable - // Interrupt Mask -#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask -#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Mask -#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RIS register. -// -//***************************************************************************** -#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw - // Interrupt Status -#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt - // Status -#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw - // Interrupt Status -#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_MIS register. -// -//***************************************************************************** -#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked - // Interrupt Status -#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Status -#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Status -#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IC register. -// -//***************************************************************************** -#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked - // Interrupt Clear -#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Clear -#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Clear -#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCT register. -// -//***************************************************************************** -#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value -#define HIB_RTCT_TRIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCSS register. -// -//***************************************************************************** -#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match -#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count -#define HIB_RTCSS_RTCSSM_S 16 -#define HIB_RTCSS_RTCSSC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_DATA register. -// -//***************************************************************************** -#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data -#define HIB_DATA_RTD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMA register. -// -//***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset -#define FLASH_FMA_OFFSET_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMD register. -// -//***************************************************************************** -#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value -#define FLASH_FMD_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit Register Value -#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory -#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory -#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status -#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status -#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt - // Status -#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status -#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status -#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status -#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask -#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask -#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask -#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask -#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask -#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCMISC register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and - // Clear -#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC2 register. -// -//***************************************************************************** -#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBVAL register. -// -//***************************************************************************** -#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBN register. -// -//***************************************************************************** -#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FSIZE register. -// -//***************************************************************************** -#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash -#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash -#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash -#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash -#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash -#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash -#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash -#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_SSIZE register. -// -//***************************************************************************** -#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size -#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM -#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM -#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM -#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM -#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM -#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM -#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM -#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM -#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_ROMSWMAP register. -// -//***************************************************************************** -#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RMCTL register. -// -//***************************************************************************** -#define FLASH_RMCTL_BA 0x00000001 // Boot Alias - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_BOOTCFG register. -// -//***************************************************************************** -#define FLASH_BOOTCFG_NW 0x80000000 // Not Written -#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port -#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A -#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B -#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C -#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D -#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E -#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F -#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G -#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H -#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin -#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 -#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 -#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 -#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 -#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 -#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 -#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 -#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 -#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity -#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable -#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 -#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG0 register. -// -//***************************************************************************** -#define FLASH_USERREG0_NW 0x80000000 // Not Written -#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data -#define FLASH_USERREG0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG1 register. -// -//***************************************************************************** -#define FLASH_USERREG1_NW 0x80000000 // Not Written -#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data -#define FLASH_USERREG1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG2 register. -// -//***************************************************************************** -#define FLASH_USERREG2_NW 0x80000000 // Not Written -#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data -#define FLASH_USERREG2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG3 register. -// -//***************************************************************************** -#define FLASH_USERREG3_NW 0x80000000 // Not Written -#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data -#define FLASH_USERREG3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version -#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 - // register format -#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_BLIZZARD \ - 0x00050000 // Stellaris(R) Blizzard-class - // microcontrollers -#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision -#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) -#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer - // revision) -#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer - // revision) -#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision -#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major - // revision update -#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change -#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version -#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format - // definition, indicating a - // Stellaris LM3Snnn device -#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1 - // register format -#define SYSCTL_DID1_FAM_M 0x0F000000 // Family -#define SYSCTL_DID1_FAM_STELLARIS \ - 0x00000000 // Stellaris family of - // microcontollers, that is, all - // devices with external part - // numbers starting with LM3S -#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number -#define SYSCTL_DID1_PRTNO_LM4F232H5QD \ - 0x00C50000 // LM4F232H5QD -#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count -#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package -#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package -#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package -#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package -#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package -#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C - // to 70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range - // (-40C to 85C) -#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C - // to 105C) -#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type -#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package -#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package -#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package -#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance -#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash -#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash -#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift -#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present -#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present -#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present -#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present -#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present -#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present -#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider -#define SYSCTL_DC1_MINSYSDIV_100 \ - 0x00001000 // Divide VCO (400MHZ) by 5 minimum -#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 = - // 6 minimum -#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock - // with a PLL divider of 4 -#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock - // with a PLL divider of 5 -#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a - // PLL divider of 8 -#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a - // PLL divider of 10 -#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed -#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second -#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second -#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second -#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second -#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed -#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second -#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second -#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second -#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second -#define SYSCTL_DC1_MPU 0x00000080 // MPU Present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present -#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present -#define SYSCTL_DC1_PLL 0x00000010 // PLL Present -#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present -#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present -#define SYSCTL_DC1_SWD 0x00000002 // SWD Present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present -#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present -#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present -#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed -#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present -#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed -#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present -#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present -#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present -#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present -#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present -#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present -#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present -#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present -#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present -#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present -#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present -#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present -#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present -#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present -#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present -#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present -#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present -#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present -#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present -#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable -#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate -#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present -#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present -#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present -#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present -#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC5 register. -// -//***************************************************************************** -#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present -#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present -#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present -#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present -#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active -#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active -#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present -#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present -#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC6 register. -// -//***************************************************************************** -#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present -#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present -#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only -#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host -#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC7 register. -// -//***************************************************************************** -#define SYSCTL_DC7_DMACH30 0x40000000 // SW -#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX -#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX -#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3 -#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2 -#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1 -#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0 -#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX -#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX -#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO -#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO -#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B -#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A -#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3 -#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2 -#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B -#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A -#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX -#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX -#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX -#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX -#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX -#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX -#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B -#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A -#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B -#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A -#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B -#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A -#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX -#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC8 register. -// -//***************************************************************************** -#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present -#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present -#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present -#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present -#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present -#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present -#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present -#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present -#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present -#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present -#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present -#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present -#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present -#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present -#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present -#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present -#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present -#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present -#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present -#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present -#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present -#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present -#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present -#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present -#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present -#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present -#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present -#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present -#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present -#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present -#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present -#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR0 register. -// -//***************************************************************************** -#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control -#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control -#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control -#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control -#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control -#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control -#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control -#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR1 register. -// -//***************************************************************************** -#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control -#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control -#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control -#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control -#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control -#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control -#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control -#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control -#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control -#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control -#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control -#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control -#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control -#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control -#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control -#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR2 register. -// -//***************************************************************************** -#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control -#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control -#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control -#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control -#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control -#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control -#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control -#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control -#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control -#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control -#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RIS register. -// -//***************************************************************************** -#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt - // Status -#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt - // Status -#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status -#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw - // Interrupt Status -#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_IMC register. -// -//***************************************************************************** -#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask -#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask -#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask -#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt - // Mask -#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MISC register. -// -//***************************************************************************** -#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt - // Status -#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt - // Status -#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status -#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked - // Interrupt Status -#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset -#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset -#define SYSCTL_RESC_SW 0x00000010 // Software Reset -#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset -#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset -#define SYSCTL_RESC_EXT 0x00000001 // External Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating -#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor -#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider -#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor -#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass -#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value -#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz -#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz -#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz -#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz -#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz -#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz -#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz -#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz -#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz -#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz -#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz -#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz -#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 -#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable -#define SYSCTL_RCC_SYSDIV_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL -// register. -// -//***************************************************************************** -#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance - // Bus - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 - // MHz -#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 -#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL -#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 -#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz -#define SYSCTL_RCC2_SYSDIV2_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. -// -//***************************************************************************** -#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected -#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action -#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC0 register. -// -//***************************************************************************** -#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed -#define SYSCTL_RCGC0_ADC1SPD_125K \ - 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADC1SPD_250K \ - 0x00000400 // 250K samples/second -#define SYSCTL_RCGC0_ADC1SPD_500K \ - 0x00000800 // 500K samples/second -#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second -#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed -#define SYSCTL_RCGC0_ADC0SPD_125K \ - 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADC0SPD_250K \ - 0x00000100 // 250K samples/second -#define SYSCTL_RCGC0_ADC0SPD_500K \ - 0x00000200 // 500K samples/second -#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second -#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC1 register. -// -//***************************************************************************** -#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC2 register. -// -//***************************************************************************** -#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC0 register. -// -//***************************************************************************** -#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC1 register. -// -//***************************************************************************** -#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC2 register. -// -//***************************************************************************** -#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC0 register. -// -//***************************************************************************** -#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC1 register. -// -//***************************************************************************** -#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC2 register. -// -//***************************************************************************** -#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override -#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1 -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SYSPROP register. -// -//***************************************************************************** -#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCCAL -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value -#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration -#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim -#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value -#define SYSCTL_PIOSCCAL_UT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value -#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result -#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been - // attempted -#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation - // completed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation - // failed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value -#define SYSCTL_PIOSCSTAT_DT_S 16 -#define SYSCTL_PIOSCSTAT_CT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value -#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value -#define SYSCTL_PLLFREQ0_MFRAC_S 10 -#define SYSCTL_PLLFREQ0_MINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value -#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value -#define SYSCTL_PLLFREQ1_Q_S 8 -#define SYSCTL_PLLFREQ1_N_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. -// -//***************************************************************************** -#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC9 register. -// -//***************************************************************************** -#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present -#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present -#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present -#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present -#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present -#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present -#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present -#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present -#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present -#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present -#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present -#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present -#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present -#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present -#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present -#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. -// -//***************************************************************************** -#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present -#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer - // Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWD register. -// -//***************************************************************************** -#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present -#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPTIMER register. -// -//***************************************************************************** -#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present -#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present -#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present -#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present -#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present -#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPGPIO register. -// -//***************************************************************************** -#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present -#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present -#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present -#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present -#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present -#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present -#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present -#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present -#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present -#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present -#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present -#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present -#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present -#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present -#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPDMA register. -// -//***************************************************************************** -#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIB register. -// -//***************************************************************************** -#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUART register. -// -//***************************************************************************** -#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present -#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present -#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present -#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present -#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present -#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present -#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present -#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPSSI register. -// -//***************************************************************************** -#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present -#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present -#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present -#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPI2C register. -// -//***************************************************************************** -#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present -#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present -#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present -#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present -#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present -#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUSB register. -// -//***************************************************************************** -#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCAN register. -// -//***************************************************************************** -#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present -#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPADC register. -// -//***************************************************************************** -#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present -#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPACMP register. -// -//***************************************************************************** -#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPWM register. -// -//***************************************************************************** -#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present -#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPQEI register. -// -//***************************************************************************** -#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present -#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present -#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present -#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present -#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present -#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present -#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWD register. -// -//***************************************************************************** -#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset -#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRTIMER register. -// -//***************************************************************************** -#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset -#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset -#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset -#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset -#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset -#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRGPIO register. -// -//***************************************************************************** -#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset -#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset -#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset -#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset -#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset -#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset -#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset -#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset -#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset -#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset -#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset -#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset -#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset -#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset -#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRDMA register. -// -//***************************************************************************** -#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRHIB register. -// -//***************************************************************************** -#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUART register. -// -//***************************************************************************** -#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset -#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset -#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset -#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset -#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset -#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset -#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset -#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRSSI register. -// -//***************************************************************************** -#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset -#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset -#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset -#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRI2C register. -// -//***************************************************************************** -#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset -#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset -#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset -#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset -#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset -#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUSB register. -// -//***************************************************************************** -#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCAN register. -// -//***************************************************************************** -#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset -#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRADC register. -// -//***************************************************************************** -#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset -#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRACMP register. -// -//***************************************************************************** -#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRPWM register. -// -//***************************************************************************** -#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset -#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRQEI register. -// -//***************************************************************************** -#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset -#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset -#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset -#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset -#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset -#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset -#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWD register. -// -//***************************************************************************** -#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCADC register. -// -//***************************************************************************** -#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module Run - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWD register. -// -//***************************************************************************** -#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCADC register. -// -//***************************************************************************** -#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWD register. -// -//***************************************************************************** -#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D7 0x00000080 // 0Mode Clock Gating Control -#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCADC register. -// -//***************************************************************************** -#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCWD register. -// -//***************************************************************************** -#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control -#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCTIMER register. -// -//***************************************************************************** -#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control -#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control -#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control -#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control -#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control -#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCGPIO register. -// -//***************************************************************************** -#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control -#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control -#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control -#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control -#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control -#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control -#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control -#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control -#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control -#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control -#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control -#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control -#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control -#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control -#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCDMA register. -// -//***************************************************************************** -#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCHIB register. -// -//***************************************************************************** -#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUART register. -// -//***************************************************************************** -#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control -#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control -#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control -#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control -#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control -#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control -#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control -#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCSSI register. -// -//***************************************************************************** -#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control -#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control -#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control -#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCI2C register. -// -//***************************************************************************** -#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control -#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control -#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control -#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control -#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control -#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUSB register. -// -//***************************************************************************** -#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCAN register. -// -//***************************************************************************** -#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control -#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCADC register. -// -//***************************************************************************** -#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control -#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCACMP register. -// -//***************************************************************************** -#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCPWM register. -// -//***************************************************************************** -#define SYSCTL_PCPWM_P1 0x00000002 // PWM Module 1 Power Control -#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCQEI register. -// -//***************************************************************************** -#define SYSCTL_PCQEI_P1 0x00000002 // QEI Module 1 Power Control -#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control -#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control -#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control -#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control -#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control -#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWD register. -// -//***************************************************************************** -#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral - // Ready -#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRTIMER register. -// -//***************************************************************************** -#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready -#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready -#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready -#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready -#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready -#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRGPIO register. -// -//***************************************************************************** -#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready -#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready -#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready -#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready -#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready -#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready -#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready -#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready -#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready -#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready -#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready -#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready -#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready -#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready -#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRDMA register. -// -//***************************************************************************** -#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRHIB register. -// -//***************************************************************************** -#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUART register. -// -//***************************************************************************** -#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready -#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready -#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready -#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready -#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready -#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready -#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready -#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRSSI register. -// -//***************************************************************************** -#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready -#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready -#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready -#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRI2C register. -// -//***************************************************************************** -#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready -#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready -#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready -#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready -#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready -#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUSB register. -// -//***************************************************************************** -#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCAN register. -// -//***************************************************************************** -#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready -#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRADC register. -// -//***************************************************************************** -#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready -#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRACMP register. -// -//***************************************************************************** -#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRPWM register. -// -//***************************************************************************** -#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready -#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRQEI register. -// -//***************************************************************************** -#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready -#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready -#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready -#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready -#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready -#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready -#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_STAT register. -// -//***************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status -#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle -#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data -#define UDMA_STAT_STATE_RD_SRCENDP \ - 0x00000020 // Reading source end pointer -#define UDMA_STAT_STATE_RD_DSTENDP \ - 0x00000030 // Reading destination end pointer -#define UDMA_STAT_STATE_RD_SRCDAT \ - 0x00000040 // Reading source data -#define UDMA_STAT_STATE_WR_DSTDAT \ - 0x00000050 // Writing destination data -#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to - // clear -#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data -#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled -#define UDMA_STAT_STATE_DONE 0x00000090 // Done -#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -#define UDMA_STAT_DMACHANS_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CFG register. -// -//***************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CTLBASE register. -// -//***************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTBASE register. -// -//***************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_WAITSTAT register. -// -//***************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_SWREQ register. -// -//***************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTSET -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTCLR -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKSET -// register. -// -//***************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKCLR -// register. -// -//***************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENASET register. -// -//***************************************************************************** -#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENACLR register. -// -//***************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTSET register. -// -//***************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTCLR register. -// -//***************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOSET register. -// -//***************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOCLR register. -// -//***************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ERRCLR register. -// -//***************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHASGN register. -// -//***************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel - // assignment -#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel - // assignment - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHIS register. -// -//***************************************************************************** -#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP0 register. -// -//***************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP1 register. -// -//***************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP2 register. -// -//***************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP3 register. -// -//***************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating - // Point -#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN4 register. -// -//***************************************************************************** -#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS4 register. -// -//***************************************************************************** -#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND4 register. -// -//***************************************************************************** -#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND4 register. -// -//***************************************************************************** -#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE4 register. -// -//***************************************************************************** -#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI29 register. -// -//***************************************************************************** -#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask -#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask -#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask -#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask -#define NVIC_PRI29_INTD_S 29 -#define NVIC_PRI29_INTC_S 21 -#define NVIC_PRI29_INTB_S 13 -#define NVIC_PRI29_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI30 register. -// -//***************************************************************************** -#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask -#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask -#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask -#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask -#define NVIC_PRI30_INTD_S 29 -#define NVIC_PRI30_INTC_S 21 -#define NVIC_PRI30_INTB_S 13 -#define NVIC_PRI30_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI31 register. -// -//***************************************************************************** -#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask -#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask -#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask -#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask -#define NVIC_PRI31_INTD_S 29 -#define NVIC_PRI31_INTC_S 21 -#define NVIC_PRI31_INTB_S 13 -#define NVIC_PRI31_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI32 register. -// -//***************************************************************************** -#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask -#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask -#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask -#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask -#define NVIC_PRI32_INTD_S 29 -#define NVIC_PRI32_INTC_S 21 -#define NVIC_PRI32_INTB_S 13 -#define NVIC_PRI32_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPAC register. -// -//***************************************************************************** -#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only -#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access -#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only -#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCC register. -// -//***************************************************************************** -#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation - // Enable -#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable -#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready -#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready -#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready -#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready -#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode -#define NVIC_FPCC_USER 0x00000002 // User Privilege Level -#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCA register. -// -//***************************************************************************** -#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address -#define NVIC_FPCA_ADDRESS_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPDSC register. -// -//***************************************************************************** -#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default -#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default -#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default -#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default -#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode -#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) - // mode -#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity - // (RM) mode -#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode - -#endif // __LM4F232H5QD_H__ diff --git a/bsp/lm4f232/project.uvproj b/bsp/lm4f232/project.uvproj index e31fcb4326..5b210bbe5b 100644 --- a/bsp/lm4f232/project.uvproj +++ b/bsp/lm4f232/project.uvproj @@ -43,7 +43,7 @@ 0 1 - .\obj\ + .\build\ project 1 0 @@ -344,9 +344,9 @@ 0 - + PART_LM4F232H5QD - ..\..\include;drivers;.;Libraries;applications;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\finsh + .;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries;applications;drivers @@ -571,25 +571,25 @@ Kernel + + clock.c + 1 + ..\..\src\clock.c + device.c 1 ..\..\src\device.c - thread.c + idle.c 1 - ..\..\src\thread.c + ..\..\src\idle.c - scheduler.c + ipc.c 1 - ..\..\src\scheduler.c - - - src_timer.c - 1 - ..\..\src\timer.c + ..\..\src\ipc.c irq.c @@ -602,14 +602,9 @@ ..\..\src\kservice.c - clock.c + mem.c 1 - ..\..\src\clock.c - - - object.c - 1 - ..\..\src\object.c + ..\..\src\mem.c mempool.c @@ -617,19 +612,24 @@ ..\..\src\mempool.c - ipc.c + object.c 1 - ..\..\src\ipc.c + ..\..\src\object.c - idle.c + scheduler.c 1 - ..\..\src\idle.c + ..\..\src\scheduler.c - mem.c + thread.c 1 - ..\..\src\mem.c + ..\..\src\thread.c + + + src_timer.c + 1 + ..\..\src\timer.c diff --git a/bsp/lm4f232/rtconfig.py b/bsp/lm4f232/rtconfig.py index 4076805b93..903a5e9281 100644 --- a/bsp/lm4f232/rtconfig.py +++ b/bsp/lm4f232/rtconfig.py @@ -3,6 +3,9 @@ ARCH='arm' CPU='cortex-m4' CROSS_TOOL='keil' +#device options +PART_TYPE = 'PART_LM4F232H5QD' + # cross_tool provides the cross compiler # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR if CROSS_TOOL == 'gcc': diff --git a/bsp/lm4f232/template.uvproj b/bsp/lm4f232/template.uvproj index e4824f5943..22d359c599 100644 --- a/bsp/lm4f232/template.uvproj +++ b/bsp/lm4f232/template.uvproj @@ -43,14 +43,14 @@ 0 1 - .\obj\ + .\build\ project 1 0 0 1 1 - .\obj\ + .\build\ 1 0 0