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Merge pull request #1 from RT-Thread/master

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陈豪
2014-08-06 22:55:49 +08:00
parent 0c8335d5ab a8fadf15b1
commit 5fc32bf12e
722 changed files with 469423 additions and 50505 deletions
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.travis.yml
+6 -8
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@@ -24,14 +24,11 @@ env:
- RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
# - RTT_BSP='bf533' # no scons
- RTT_BSP='dev3210' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='jz47xx' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='lpc1114' # no scons
# - RTT_BSP='lpc122x' # no scons
- RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
@@ -40,13 +37,12 @@ env:
# - RTT_BSP='m16c62p' # m32c
- RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='microblaze' # no scons
- RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='mini4020' # no scons
# - RTT_BSP='nios_ii' # no scons
# - RTT_BSP='nuc140' # no scons
# - RTT_BSP='pic32ethernet' # no scons
# - RTT_BSP='sam7s' # no scons
- RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='simulator' # x86
- RTT_BSP='stm32f0x' RTT_TOOL_CHAIN='sourcery-arm'
@@ -56,8 +52,10 @@ env:
- RTT_BSP='stm32f40x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
# - RTT_BSP='upd70f3454' # iar
# - RTT_BSP='wh44b0' # no scons
# - RTT_BSP='x86' # x86
- RTT_BSP='xplorer4330/m4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
ChangeLog_CN.md
+1454
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File diff suppressed because it is too large Load Diff
bsp/K60Fxxxx/drivers/led.c
-55
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@@ -1,55 +0,0 @@
/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-07-11 reynolds port to TWR-K60F120M
*/
#include <MK60F12.H>
#include "led.h"
const rt_uint32_t led_mask[] = { 1 << 11, 1 << 28, 1 << 29, 1 << 10 };
void rt_hw_led_init(void)
{
SIM->SCGC5 |= (1UL << 9); //Enable Port A Clock
PORTA->PCR[10] = (1UL << 8); //PTA10 is GPIO pin
PORTA->PCR[11] = (1UL << 8); //PTA11 is GPIO pin
PORTA->PCR[28] = (1UL << 8); //PTA28 is GPIO pin
PORTA->PCR[29] = (1UL << 8); //PTA29 is GPIO pin
/* Switch LEDs off and enable output*/
PTA->PDOR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
PTA->PDDR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
}
void rt_hw_led_uninit(void)
{
PORTA->PCR[10] = 0; //PTA10 is at reset state
PORTA->PCR[11] = 0; //PTA11 is at reset state
PORTA->PCR[28] = 0; //PTA28 is at reset state
PORTA->PCR[29] = 0; //PTA29 is at reset state
}
void rt_hw_led_on(rt_uint32_t n)
{
if (n < LED_MAX)
{
PTA->PCOR = led_mask[n];
}
}
void rt_hw_led_off(rt_uint32_t n)
{
if (n < LED_MAX) {
PTA->PSOR = led_mask[n];
}
}
bsp/K60Fxxxx/drivers/system_MK60F12.c
-366
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@@ -1,366 +0,0 @@
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K60P144M150SF3RM, Rev. 2, Dec 2011
** Version: rev. 1.3, 2012-04-13
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-08-24)
** Initial version
** - rev. 1.1 (2011-11-03)
** Registers updated according to the new reference manual revision - Rev. 1, Oct 2011
** Registers of the following modules have been updated - AXBS, CAN, I2S, MCG, MPU, NFC, RCM, RTC, SDHC, SIM, USBHS, WDOG
** The following modules have been removed - DDR, DRY
** - rev. 1.2 (2012-01-04)
** Registers updated according to the new reference manual revision - Rev. 2, Dec 2011
** EWM - INTEN bit in EWM_CTRL register has been added.
** PDB - register PDB_PO0EN renamed to PRB_POEN.
** PMC - BGEN bit in PMC_REGSC register has been removed.
** SIM - several changes in SCGC registers. Bit USBHS in SOPT2 register removed.
** UART - new bits RXOFE in regiter CFIFO and RXOF in register SFIFO.
** - rev. 1.3 (2012-04-13)
** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
** Added new #define symbols <peripheralType>_BASE_PTRS.
**
** ###################################################################
*/
/**
* @file MK60F12
* @version 1.3
* @date 2012-04-13
* @brief Device specific configuration file for MK60F12 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MK60F12.h"
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external reference clock source 50MHz
Core clock = 120MHz, BusClock = 60MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external reference clock source 50MHz with no multiplication
Core clock = 50MHz, BusClock = 50MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
#define CPU_XTAL1_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
#define CPU_XTAL1_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
#define CPU_XTAL1_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 50000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 2) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = (uint16_t)0x01D2u;
#endif /* (DISABLE_WDOG) */
/* System clock initialization */
#if (CLOCK_SETUP == 0)
/* SIM_SCGC5: PORTA=1 */
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=0 */
SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SCGC1: OSC1=1 */
SIM->SCGC1 |= (uint32_t)0x20UL;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
/* Switch to FEI Mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x06U;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x20U;
/* MCG_C4: DMX32=0,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint8_t)0x80U;
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC1->CR = (uint8_t)0x80U;
/* MCG_C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00U;
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00U; /* 3 */
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
MCG->C11 = (uint8_t)0x00U; /* 3 */
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
MCG->C12 = (uint8_t)0x00U; /* 3 */
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1)
/* SIM_SCGC5: PORTA=1 */
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x01350000UL; /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SCGC1: OSC1=1 */
SIM->SCGC1 |= (uint32_t)0x20UL;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint8_t)0x80U;
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC1->CR = (uint8_t)0x80U;
/* MCG_C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x20U;
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0xAAU;
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
MCG->C5 = (uint8_t)0x04U;
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
MCG->C6 = (uint8_t)0x08U;
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
MCG->C11 = (uint8_t)0x00U;
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
MCG->C12 = (uint8_t)0x00U;
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
MCG->C6 = (uint8_t)0x48U;
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
}
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x2AU;
while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
#elif (CLOCK_SETUP == 2)
/* SIM_SCGC5: PORTA=1 */
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=0 */
SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SCGC1: OSC1=1 */
SIM->SCGC1 |= (uint32_t)0x20UL;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint8_t)0x80U;
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC1->CR = (uint8_t)0x80U;
/* MCG_C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x20U;
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0xAAU;
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00U;
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00U;
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
MCG->C11 = (uint8_t)0x00U;
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
MCG->C12 = (uint8_t)0x00U;
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to BLPE Mode */
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
MCG->C2 = (uint8_t)0x22U;
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
#endif /* (CLOCK_SETUP == 2) */
/* Disable MPU */
MPU->CESR &= ~MPU_CESR_VLD_MASK;
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL0_CLK_HZ; /* System oscillator 0 drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
/* PLL is selected */
if ((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u) {
/* PLL1 output is selected */
if ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u) {
/* OSC1 clock source used as an external reference clock */
MCGOUTClock = CPU_XTAL1_CLK_HZ;
} else { /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
/* OSC0 clock source used as an external reference clock */
MCGOUTClock = CPU_XTAL0_CLK_HZ;
} /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
Divider = (1u + (MCG->C11 & MCG_C11_PRDIV1_MASK));
MCGOUTClock /= Divider; /* Calculate the PLL reference clock */
Divider = ((MCG->C12 & MCG_C12_VDIV1_MASK) + 16u);
MCGOUTClock = (MCGOUTClock * Divider) / 2u; /* Calculate the MCG output clock */
} else { /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
/* PLL0 output is selected */
if ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u) {
/* OSC1 clock source used as an external reference clock */
MCGOUTClock = CPU_XTAL1_CLK_HZ;
} else { /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
/* OSC0 clock source used as an external reference clock */
MCGOUTClock = CPU_XTAL0_CLK_HZ;
} /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUTClock /= Divider; /* Calculate the PLL reference clock */
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 16u);
MCGOUTClock = (MCGOUTClock * Divider) / 2u; /* Calculate the MCG output clock */
} /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL0_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}
bsp/K60Fxxxx/readme.txt
-8
View File
@@ -1,8 +0,0 @@
board info:
Freescale Tower TWR-K60F120M
http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-K60F120M
with:
TWR-SER
http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-SER
and TWR-ELEV
http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-ELEV
bsp/at91sam9260/applications/application.c
-2
View File
@@ -138,8 +138,6 @@ void rt_init_thread_entry(void* parameter)
/* register ethernetif device */
eth_system_device_init();
rt_hw_macb_init();
/* re-init device driver */
rt_device_init_all();
/* init lwip system */
lwip_sys_init();
}
bsp/at91sam9260/drivers/usart.c
+10 -14
View File
@@ -95,7 +95,7 @@ void rt_at91_usart_handler(int vector, void *param)
return;
}
rt_interrupt_enter();
rt_hw_serial_isr(dev);
rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
rt_interrupt_leave();
}
@@ -231,7 +231,6 @@ static const struct rt_uart_ops at91_usart_ops =
#if defined(RT_USING_DBGU)
static struct rt_serial_device serial_dbgu;
static struct serial_ringbuffer dbgu_int_rx;
struct at91_uart dbgu = {
DBGU,
AT91_ID_SYS
@@ -241,7 +240,6 @@ struct at91_uart dbgu = {
#if defined(RT_USING_UART0)
static struct rt_serial_device serial0;
static struct serial_ringbuffer uart0_int_rx;
struct at91_uart uart0 = {
UART0,
AT91SAM9260_ID_US0
@@ -250,7 +248,6 @@ struct at91_uart uart0 = {
#if defined(RT_USING_UART1)
static struct rt_serial_device serial1;
static struct serial_ringbuffer uart1_int_rx;
struct at91_uart uart1 = {
UART1,
AT91SAM9260_ID_US1
@@ -259,7 +256,6 @@ struct at91_uart uart1 = {
#if defined(RT_USING_UART2)
static struct rt_serial_device serial2;
static struct serial_ringbuffer uart2_int_rx;
struct at91_uart uart2 = {
UART2,
AT91SAM9260_ID_US2
@@ -268,7 +264,6 @@ struct at91_uart uart2 = {
#if defined(RT_USING_UART3)
static struct rt_serial_device serial3;
static struct serial_ringbuffer uart3_int_rx;
struct at91_uart uart3 = {
UART3,
AT91SAM9260_ID_US3
@@ -337,29 +332,29 @@ void rt_hw_uart_init(void)
#if defined(RT_USING_DBGU)
serial_dbgu.ops = &at91_usart_ops;
serial_dbgu.int_rx = &dbgu_int_rx;
serial_dbgu.config.baud_rate = BAUD_RATE_115200;
serial_dbgu.config.bit_order = BIT_ORDER_LSB;
serial_dbgu.config.data_bits = DATA_BITS_8;
serial_dbgu.config.parity = PARITY_NONE;
serial_dbgu.config.stop_bits = STOP_BITS_1;
serial_dbgu.config.invert = NRZ_NORMAL;
serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial_dbgu, "dbgu",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&dbgu);
#endif
#if defined(RT_USING_UART0)
serial0.ops = &at91_usart_ops;
serial0.int_rx = &uart0_int_rx;
serial0.config.baud_rate = BAUD_RATE_115200;
serial0.config.bit_order = BIT_ORDER_LSB;
serial0.config.data_bits = DATA_BITS_8;
serial0.config.parity = PARITY_NONE;
serial0.config.stop_bits = STOP_BITS_1;
serial0.config.invert = NRZ_NORMAL;
serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial0, "uart0",
@@ -379,10 +374,11 @@ void rt_hw_uart_init(void)
serial1.config.parity = PARITY_NONE;
serial1.config.stop_bits = STOP_BITS_1;
serial1.config.invert = NRZ_NORMAL;
serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart1);
rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
(void *)&(serial1.parent), "UART1");
@@ -391,17 +387,17 @@ void rt_hw_uart_init(void)
#if defined(RT_USING_UART2)
serial2.ops = &at91_usart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config.baud_rate = BAUD_RATE_115200;
serial2.config.bit_order = BIT_ORDER_LSB;
serial2.config.data_bits = DATA_BITS_8;
serial2.config.parity = PARITY_NONE;
serial2.config.stop_bits = STOP_BITS_1;
serial2.config.invert = NRZ_NORMAL;
serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart2);
rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
(void *)&(serial2.parent), "UART2");
@@ -410,17 +406,17 @@ void rt_hw_uart_init(void)
#if defined(RT_USING_UART3)
serial3.ops = &at91_usart_ops;
serial3.int_rx = &uart3_int_rx;
serial3.config.baud_rate = BAUD_RATE_115200;
serial3.config.bit_order = BIT_ORDER_LSB;
serial3.config.data_bits = DATA_BITS_8;
serial3.config.parity = PARITY_NONE;
serial3.config.stop_bits = STOP_BITS_1;
serial3.config.invert = NRZ_NORMAL;
serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart3);
rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
(void *)&(serial3.parent), "UART3");
bsp/avr32uc3b0/startup.c
-1
View File
@@ -39,7 +39,6 @@ int main(void)
#endif
rt_system_scheduler_init();
rt_device_init_all();
rt_application_init();
#ifdef RT_USING_FINSH
bsp/beaglebone/drivers/serial.c
+17 -19
View File
@@ -41,7 +41,7 @@ static void am33xx_uart_isr(int irqno, void* param)
if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
{
rt_hw_serial_isr(serial);
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
}
@@ -165,7 +165,6 @@ static const struct rt_uart_ops am33xx_uart_ops =
/* UART device driver structure */
#ifdef RT_USING_UART0
struct serial_ringbuffer uart0_int_rx;
struct am33xx_uart uart0 =
{
UART0_BASE,
@@ -175,7 +174,6 @@ struct rt_serial_device serial0;
#endif
#ifdef RT_USING_UART1
struct serial_ringbuffer uart1_int_rx;
struct am33xx_uart uart1 =
{
UART1_BASE,
@@ -185,7 +183,6 @@ struct rt_serial_device serial1;
#endif
#ifdef RT_USING_UART2
struct serial_ringbuffer uart2_int_rx;
struct am33xx_uart uart2 =
{
UART2_BASE,
@@ -195,7 +192,6 @@ struct rt_serial_device serial2;
#endif
#ifdef RT_USING_UART3
struct serial_ringbuffer uart3_int_rx;
struct am33xx_uart uart3 =
{
UART3_BASE,
@@ -205,7 +201,6 @@ struct rt_serial_device serial3;
#endif
#ifdef RT_USING_UART4
struct serial_ringbuffer uart4_int_rx;
struct am33xx_uart uart4 =
{
UART4_BASE,
@@ -215,7 +210,6 @@ struct rt_serial_device serial4;
#endif
#ifdef RT_USING_UART5
struct serial_ringbuffer uart5_int_rx;
struct am33xx_uart uart5 =
{
UART5_BASE,
@@ -359,8 +353,9 @@ int rt_hw_serial_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial0.ops = &am33xx_uart_ops;
serial0.int_rx = &uart0_int_rx;
serial0.config = config;
/* enable RX interrupt */
UART_IER_REG(uart0.base) = 0x01;
@@ -370,7 +365,7 @@ int rt_hw_serial_init(void)
rt_hw_interrupt_mask(uart0.irq);
/* register UART0 device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart0);
#endif
@@ -381,8 +376,9 @@ int rt_hw_serial_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial1.ops = &am33xx_uart_ops;
serial1.int_rx = &uart1_int_rx;
serial1.config = config;
/* enable RX interrupt */
UART_IER_REG(uart1.base) = 0x01;
@@ -392,7 +388,7 @@ int rt_hw_serial_init(void)
rt_hw_interrupt_mask(uart1.irq);
/* register UART0 device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart1);
#endif
@@ -403,8 +399,9 @@ int rt_hw_serial_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial2.ops = &am33xx_uart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config = config;
/* enable RX interrupt */
UART_IER_REG(uart2.base) = 0x01;
@@ -414,7 +411,7 @@ int rt_hw_serial_init(void)
rt_hw_interrupt_mask(uart2.irq);
/* register UART2 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart2);
#endif
@@ -425,8 +422,9 @@ int rt_hw_serial_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial3.ops = &am33xx_uart_ops;
serial3.int_rx = &uart_3_int_rx;
serial3.config = config;
/* enable RX interrupt */
UART_IER_REG(uart3.base) = 0x01;
@@ -436,7 +434,7 @@ int rt_hw_serial_init(void)
rt_hw_interrupt_mask(uart3.irq);
/* register UART3 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart3);
#endif
@@ -447,9 +445,9 @@ int rt_hw_serial_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial4.ops = &am33xx_uart_ops;
serial4.int_rx = &uart4_int_rx;
serial4.config = config;
/* enable RX interrupt */
UART_IER_REG(uart4.base) = 0x01;
@@ -459,7 +457,7 @@ int rt_hw_serial_init(void)
rt_hw_interrupt_mask(uart4.irq);
/* register UART4 device */
rt_hw_serial_register(&serial4, "uart4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart4);
#endif
@@ -470,9 +468,9 @@ int rt_hw_serial_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial5.ops = &am33xx_uart_ops;
serial5.int_rx = &uart5_int_rx;
serial5.config = config;
/* enable RX interrupt */
UART_IER_REG(uart5.base) = 0x01;
@@ -482,7 +480,7 @@ int rt_hw_serial_init(void)
rt_hw_interrupt_mask(uart5.irq);
/* register UART4 device */
rt_hw_serial_register(&serial5, "uart5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart5);
#endif
bsp/bf533/startup.c
-3
View File
@@ -62,9 +62,6 @@ void rtthread_startup(void)
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
/* init all device */
rt_device_init_all();
rt_console_set_device("uart0");
#endif
bsp/dev3210/SConscript
-13
View File
@@ -1,13 +0,0 @@
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c']
if GetDepend('RT_USING_NEWLIB'):
src_bsp = src_bsp + ['newlib_stub.c']
src_drv = ['uart.c', 'lnn800x480.c']
src = File(src_bsp + src_drv)
CPPPATH = [GetCurrentDir()]
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/dev3210/application.c
-119
View File
@@ -1,119 +0,0 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rtthread.h>
#include <soc3210.h>
#ifdef RT_USING_DFS
#include <dfs.h>
#include <dfs_elm.h>
#ifdef RT_USING_DFS_ROMFS
#include <dfs_romfs.h>
#endif
#ifdef RT_USING_DFS_DEVFS
#include <devfs.h>
#endif
#endif
#ifdef RT_USING_RTGUI
#include <rtgui/rtgui.h>
#include <rtgui/event.h>
#include <rtgui/rtgui_server.h>
#endif
void rt_init_thread_entry(void *parameter)
{
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
/* init the device filesystem */
dfs_init();
#if defined(RT_USING_DFS_ROMFS)
dfs_romfs_init();
if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) == 0)
{
rt_kprintf("ROM File System initialized!\n");
}
else
rt_kprintf("ROM File System initialzation failed!\n");
#endif
#if defined(RT_USING_DFS_ELMFAT)
/* init the elm chan FatFs filesystam*/
elm_init();
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/sd", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
rt_kprintf("File System initialzation failed!\n");
#endif
#if defined(RT_USING_DFS_DEVFS)
devfs_init();
if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
rt_kprintf("Device File System initialized!\n");
else
rt_kprintf("Device File System initialzation failed!\n");
#ifdef RT_USING_NEWLIB
/* init libc */
libc_system_init("uart");
rt_kprintf("libc init done\n");
#endif
#endif
}
#endif
#ifdef RT_USING_RTGUI
{
rtgui_rect_t rect;
rtgui_system_server_init();
/* register dock panel */
rect.x1 = 0;
rect.y1 = 0;
rect.x2 = 400;
rect.y2 = 480;
// rtgui_panel_register("panel", &rect);
/* register main panel */
rect.x1 = 400;
rect.y1 = 0;
rect.x2 = 800;
rect.y2 = 480;
// rtgui_panel_register("main", &rect);
// rtgui_panel_set_default_focused("main");
rt_hw_lcd_init();
}
#endif
}
int rt_application_init(void)
{
rt_thread_t tid;
/* create initialization thread */
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
4096, 8, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
bsp/dev3210/board.c
-103
View File
@@ -1,103 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "uart.h"
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
}
/**
* This function will initial sam7s64 board.
*/
void rt_hw_board_init(void)
{
#ifdef RT_USING_UART
/* init hardware UART device */
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device("uart");
#endif
/* init operating system timer */
rt_hw_timer_init();
rt_kprintf("current sr: 0x%08x\n", read_c0_status());
}
/*@}*/
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_console_output(const char *ptr)
{
/* stream mode */
while (*ptr)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(UART0_BASE) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(UART0_BASE) = *ptr;
ptr ++;
}
}
bsp/dev3210/board.h
-24
View File
@@ -1,24 +0,0 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2010, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_init(void);
/* 32M SDRAM */
#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
#define CPU_HZ (250 * 1000000)
#endif
bsp/dev3210/dev3210_ram.lds
-119
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@@ -1,119 +0,0 @@
/*
* File : jz47xx_ram.lds
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard move the beginning entry to 0x80200000
*/
OUTPUT_ARCH(mips)
GROUP(-lgcc -lc)
ENTRY(_start)
SECTIONS
{
. = 0x80200000 ;
.start :
{
*(.start);
}
. = ALIGN(4);
.text :
{
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.rodata1)
*(.rodata1.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
}
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
}
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/dev3210/dw.txt
-11
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@@ -1,11 +0,0 @@
# download script for boot loader
ifaddr dmfe0 192.168.1.100
load tftp://192.168.1.5/boot_3210 0x80200000
# download script for RT-Thread
ifaddr dmfe0 192.168.1.100
load tftp://192.168.1.5/rtthread.elf
# burn script for RT-Thread
ifaddr dmfe0 192.168.1.100
devcp tftp://192.168.1.5/rtthread.elf /dev/mtd0
bsp/dev3210/lnn800x480.c
-102
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@@ -1,102 +0,0 @@
/*
* File : lnn800x480.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-01 bernard first version from QiuYi's driver
*/
#include <rtthread.h>
#include <soc3210.h>
/* LCD driver for 800x480 16bit */
#define RT_HW_LCD_WIDTH 800
#define RT_HW_LCD_HEIGHT 480
#define K1BASE 0xA0000000
#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
#define HW_FB_ADDR KSEG1(_rt_framebuffer)
#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * RT_HW_LCD_WIDTH * 2) + x * 2)
ALIGN(4)
volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
static struct rt_device_graphic_info _lcd_info;
static rt_err_t rt_lcd_init (rt_device_t dev)
{
/* disable LCD controller */
LCD_CTRL = LCD_CTRL & 0xfffe;
/* set LCD clock */
HSB_MISC_REG = (HSB_MISC_REG & 0xFFFD01FF) |
(0x01 << 17) | /* enable LCD */
(0x05 << 9); /* clock */
LCD_VBARA = (rt_uint32_t)_rt_framebuffer - 0x80000000;
LCD_VBARB = (rt_uint32_t)_rt_framebuffer - 0x80000000;
LCD_HTIM = 0x12c031f;
LCD_VTIM = 0x11501df;
LCD_HVLEN = 0x41e0279;
LCD_CTRL = 0x8709;
rt_kprintf("VBARA 0x%08x\n", LCD_VBARA);
rt_kprintf("CTRL 0x%08x\n", LCD_CTRL);
rt_kprintf("HTIM 0x%08x\n", LCD_HTIM);
rt_kprintf("VTIM 0x%08x\n", LCD_VTIM);
rt_kprintf("HVLEN 0x%08x\n", LCD_HVLEN);
rt_kprintf("HSB_MISC 0x%08x\n", HSB_MISC_REG);
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, rt_uint8_t cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
}
void rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Graphic;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
bsp/dev3210/newlib_stub.c
-43
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@@ -1,43 +0,0 @@
/*
* File : newlib_stub.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
/* some newlib leaked function in CodeSourcery G++ Lite for MIPS version */
int getpid(void)
{
return 0;
}
int gettimeofday(struct timeval *__tp, void *__tzp)
{
struct timespec tp;
if (libc_get_time(&tp) == 0)
{
if (__tp != RT_NULL)
{
__tp->tv_sec = tp.tv_sec;
__tp->tv_usec = tp.tv_nsec * 1000UL;
}
return tp.tv_sec;
}
return 0;
}
bsp/dev3210/rtconfig.h
-169
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@@ -1,169 +0,0 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 10
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 256
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_INTERRUPT_INFO
/* Using Hook */
#define RT_USING_HOOK
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
/* Using Semaphore */
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
#define RT_USING_MAILBOX
/* Using Message Queue */
#define RT_USING_MESSAGEQUEUE
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Using Dynamic Heap Management */
#define RT_USING_HEAP
/* Using SLAB MM */
#define RT_USING_SLAB
/* #define RT_USING_SMALL_MEM */
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
#define RT_USING_UART
#define RT_USING_UART1
#define RT_UART_RX_BUFFER_SIZE 64
/* SECTION: Console options */
/* the buffer size of console */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: the runtime libc library */
/* the runtime libc library */
/* #define RT_USING_NEWLIB */
/* #define RT_USING_PTHREADS */
/* SECTION: finsh, a C-Express shell */
/* Using FinSH as Shell*/
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_DEVICE_NAME "uart"
/* SECTION: device filesystem support */
#define RT_USING_DFS
/* #define RT_USING_DFS_ELMFAT */
#define RT_USING_DFS_ROMFS
/* #define RT_USING_DFS_DEVFS */
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 4
/* Using working directory */
#define DFS_USING_WORKDIR
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* #define RT_USING_LWIP */
#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
/* Enable UDP protocol*/
#define RT_LWIP_UDP
/* Enable TCP protocol*/
#define RT_LWIP_TCP
/* Enable DNS */
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* SECTION: RT-Thread/GUI */
// #define RT_USING_RTGUI
#ifdef RT_USING_RTGUI
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 12
/* support 16 weight font */
#define RTGUI_USING_FONT16
/* support 12 weight font */
#define RTGUI_USING_FONT12
/* support Chinese font */
#define RTGUI_USING_FONTHZ
/* use DFS as file interface */
#define RTGUI_USING_DFS_FILERW
/* use bmp font as Chinese font */
#define RTGUI_USING_HZ_BMP
/* use small size in RTGUI */
#define RTGUI_USING_SMALL_SIZE
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* default font size in RTGUI */
#define RTGUI_DEFAULT_FONT_SIZE 16
#endif // RT_USING_RTGUI
#endif
bsp/dev3210/rtconfig.py
-59
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@@ -1,59 +0,0 @@
import os
# CPU options
ARCH='mips'
CPU ='loongson'
# toolchains options
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_MIPS_ELF/bin'
elif CROSS_TOOL == 'keil':
print '================ERROR============================'
print 'Not support keil yet!'
print '================================================='
exit(0)
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support iar yet!'
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
PREFIX = 'mips-sde-elf-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -mips2'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -EL -Wl,--gc-sections,-Map=rtthread-3210.map,-cref,-u,Reset_Handler -T dev3210_ram.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
bsp/dev3210/startup.c
-92
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@@ -1,92 +0,0 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <cache.h>
#include "board.h"
#define A_K0BASE 0x80000000
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
extern unsigned char __bss_start;
extern unsigned char __bss_end;
extern int rt_application_init(void);
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init cache */
rt_hw_cache_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
/* copy vector */
memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
/* init board */
rt_hw_board_init();
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* init all device */
rt_device_init_all();
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device(FINSH_DEVICE_NAME);
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
/*@}*/
bsp/dev3210/uart.c
-295
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@@ -1,295 +0,0 @@
/*
* File : uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
struct rt_uart_soc3210
{
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irq;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int irqno, void *param)
{
rt_ubase_t level;
rt_uint8_t isr;
struct rt_uart_soc3210* uart = &uart_device;
/* read interrupt status and clear it */
isr = UART_IIR(uart->hw_base);
isr = (isr >> 1) & 0x3;
if (isr & 0x02) /* receive data available */
{
/* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if (uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init (rt_device_t dev)
{
rt_uint32_t baud_div;
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
RT_ASSERT(uart != RT_NULL);
#if 0
/* init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
/* enable UART clock */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = 0x3;
/* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE;
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_LSB(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
/* Enable UART unit, enable and clear FIFO */
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
#endif
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= UARTIER_IRXE;
/* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
rt_hw_interrupt_umask(uart->irq);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_uint8_t *ptr;
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210 *)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
char *ptr;
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210 *)dev;
RT_ASSERT(uart != RT_NULL);
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size != 0)
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr++;
size--;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_soc3210 *uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART1)
uart->hw_base = UART0_BASE;
uart->irq = IRQ_UART0;
#elif defined(RT_USING_UART2)
uart->hw_base = UART1_BASE;
uart->irq = IRQ_UART1;
#endif
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/
bsp/efm32/startup.c
-3
View File
@@ -114,9 +114,6 @@ void rtthread_startup(void)
/* init scheduler system */
rt_system_scheduler_init();
/* init all devices */
rt_device_init_all();
/* init finsh */
#ifdef RT_USING_FINSH
finsh_system_init();
bsp/frdm-k64f/K64FN1M0xxx12.ld
+177
View File
@@ -0,0 +1,177 @@
/*
* K64F ARM GCC linker script file
*/
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410
RAM (rwx) : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
. = ALIGN(4);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
. = ALIGN(4);
} > FLASH_PROTECTION
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
__bss_start = .;
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
__bss_end = .;
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
bsp/frdm-k64f/MK64F.sct
+14
View File
@@ -0,0 +1,14 @@
LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
ER_IROM1 0x00000000 0x100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
; 0x40000 - 0x198 = 0x3FE68
RW_IRAM1 0x1FFF0198 0x3FE68 {
.ANY (+RW +ZI)
}
}
bsp/K60Fxxxx/SConscript → bsp/frdm-k64f/SConscript
View File
bsp/K60Fxxxx/SConstruct → bsp/frdm-k64f/SConstruct
+1 -1
View File
@@ -10,7 +10,7 @@ else:
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-k60.' + rtconfig.TARGET_EXT
TARGET = 'rtthread-k64f.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
bsp/K60Fxxxx/applications/SConscript → bsp/frdm-k64f/applications/SConscript
View File
bsp/K60Fxxxx/applications/application.c → bsp/frdm-k64f/applications/application.c
+5 -7
View File
@@ -9,18 +9,17 @@
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
/**
* @addtogroup k60
* @addtogroup k64
*/
/*@{*/
#include <stdio.h>
#include "MK60F12.h"
#include "MK64F12.h"
#include <board.h>
#include <rtthread.h>
@@ -70,7 +69,7 @@ static void rt_thread_entry_led1(void* parameter)
{
int n = 0;
rt_hw_led_init();
while (1)
{
//rt_kprintf("LED\t%d\tis shining\r\n",n);
@@ -82,9 +81,8 @@ static void rt_thread_entry_led1(void* parameter)
n++;
if(n > LED_MAX-1)
if (n == LED_MAX)
n = 0;
}
}
bsp/K60Fxxxx/applications/startup.c → bsp/frdm-k64f/applications/startup.c
+41 -44
View File
@@ -9,18 +9,16 @@
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
#include <rthw.h>
#include <rtthread.h>
#include <MK60F12.H>
#include "board.h"
#include <board.h>
/**
* @addtogroup k60
* @addtogroup k64
*/
/*@{*/
@@ -33,13 +31,13 @@ extern void finsh_set_device(const char* device);
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define k60_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#define K64_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define k60_SRAM_BEGIN (__segment_end("HEAP"))
#define K64_SRAM_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define k60_SRAM_BEGIN (&__bss_end)
#define K64_SRAM_BEGIN (&__bss_end)
#endif
/*******************************************************************************
@@ -53,11 +51,11 @@ extern int __bss_end;
*******************************************************************************/
void assert_failed(rt_uint8_t* file, rt_uint32_t line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
while (1) ;
}
/**
@@ -65,61 +63,60 @@ void assert_failed(rt_uint8_t* file, rt_uint32_t line)
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
/* init timer system */
rt_system_timer_init();
rt_system_heap_init((void*)k60_SRAM_BEGIN, (void*)k60_SRAM_END);
rt_system_heap_init((void*)K64_SRAM_BEGIN, (void*)K64_SRAM_END);
/* init scheduler system */
rt_system_scheduler_init();
/* init scheduler system */
rt_system_scheduler_init();
/* init all device */
rt_device_init_all();
/* init all device */
rt_device_init_all();
/* init application */
rt_application_init();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device( FINSH_DEVICE_NAME );
/* init finsh */
finsh_system_init();
finsh_set_device( FINSH_DEVICE_NAME );
#endif
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
return 0;
}
/*@}*/
bsp/frdm-k64f/board/SConscript
+12
View File
@@ -0,0 +1,12 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'board')
src = Glob('*.c')
src += Glob('*.s')
CPPPATH = [cwd]
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/K60Fxxxx/drivers/board.c → bsp/frdm-k64f/board/board.c
+2 -3
View File
@@ -9,20 +9,19 @@
*
* Change Logs:
* Date Author Notes
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
#include <rthw.h>
#include <rtthread.h>
#include <MK60F12.H>
#include "board.h"
#include "drv_uart.h"
/**
* @addtogroup K60
* @addtogroup K64
*/
/*@{*/
bsp/K60Fxxxx/drivers/board.h → bsp/frdm-k64f/board/board.h
+13 -13
View File
@@ -9,44 +9,44 @@
*
* Change Logs:
* Date Author Notes
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef __BOARD_H__
#define __BOARD_H__
#include <MK60F12.H>
#include <MK64F12.h>
/* board configuration */
// <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64
#define k60_SRAM_SIZE 128
#define k60_SRAM_END (0x20000000 + (k60_SRAM_SIZE * 1024)/2)
#define K64_SRAM_SIZE 256
#define K64_SRAM_END (0x1FFF0000 + (K64_SRAM_SIZE * 1024))
//#define RT_USING_UART1
#define RT_USING_UART5
#define RT_USING_UART0
//#define RT_USING_UART3
// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
// <i>Default: 1
#define k60_CONSOLE_USART 5
#define K64_CONSOLE_USART 0
void rt_hw_board_init(void);
#if k60_CONSOLE_USART == 0
#define CONSOLE_DEVICE "no"
#elif k60_CONSOLE_USART == 1
#if K64_CONSOLE_USART == 0
#define CONSOLE_DEVICE "uart0"
#elif K64_CONSOLE_USART == 1
#define CONSOLE_DEVICE "uart1"
#elif k60_CONSOLE_USART == 2
#elif K64_CONSOLE_USART == 2
#define CONSOLE_DEVICE "uart2"
#elif k60_CONSOLE_USART == 3
#elif K64_CONSOLE_USART == 3
#define CONSOLE_DEVICE "uart3"
#elif k60_CONSOLE_USART == 4
#elif K64_CONSOLE_USART == 4
#define CONSOLE_DEVICE "uart4"
#elif k60_CONSOLE_USART == 5
#elif K64_CONSOLE_USART == 5
#define CONSOLE_DEVICE "uart5"
#endif
bsp/K60Fxxxx/drivers/drv_uart.c → bsp/frdm-k64f/board/drv_uart.c
+63 -52
View File
@@ -9,16 +9,15 @@
*
* Change Logs:
* Date Author Notes
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
#include "drv_uart.h"
static struct rt_serial_device _k60_serial; //abstracted serial for RTT
static struct serial_ringbuffer _k60_int_rx; //UART send buffer area
static struct rt_serial_device _k64_serial; //abstracted serial for RTT
struct k60_serial_device
struct k64_serial_device
{
/* UART base address */
UART_Type *baseAddress;
@@ -31,34 +30,22 @@ struct k60_serial_device
};
//hardware abstract device
static struct k60_serial_device _k60_node =
static struct k64_serial_device _k64_node =
{
(UART_Type *)UART5,
k60_uasrt_irq_num,
(UART_Type *)UART0,
UART0_RX_TX_IRQn,
};
static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2,reg_BRFA=0;
unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2 = 0,reg_BRFA=0;
unsigned int cal_SBR = 0;
UART_Type *uart_reg;
/* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
* calculate baud_rate
*/
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
/* calc SBR */
cal_SBR = 60000000 / (16 * cfg->baud_rate);
/* calc baud_rate */
reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
reg_BDL = cal_SBR & 0x00FF;
/* fractional divider */
reg_BRFA = ((60000*32000)/(cfg->baud_rate * 16)) - (cal_SBR * 32);
reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
/*
* set bit order
@@ -87,7 +74,7 @@ static rt_err_t _configure(struct rt_serial_device *serial, struct serial_config
{
/* first ,set parity enable bit */
reg_C1 |= (UART_C1_PE_MASK);
/* second ,determine parity odd or even*/
if (cfg->parity == PARITY_ODD)
reg_C1 |= UART_C1_PT_MASK;
@@ -95,39 +82,63 @@ static rt_err_t _configure(struct rt_serial_device *serial, struct serial_config
reg_C1 &= ~(UART_C1_PT_MASK);
}
/*
* set stop bit
* not supported on Tower? need ur help!
*/
/*
* set NZR mode
* not tested
*/
if(cfg->invert != NRZ_NORMAL)
if (cfg->invert != NRZ_NORMAL)
{
/* not in normal mode ,set inverted polarity */
reg_C3 |= UART_C3_TXINV_MASK;
}
switch( (int)uart_reg)
switch ((unsigned int)uart_reg)
{
/* Tower board use UART5 for communication
/*
* if you're using other board
* set clock and pin map for UARTx
*/
case UART5_BASE:
case UART0_BASE:
/* calc SBR */
cal_SBR = SystemCoreClock / (16 * cfg->baud_rate);
//set UART5 clock
SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;//Enable UART gate clocking
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;//Enable PORTE gate clocking
/* check to see if sbr is out of range of register bits */
if ((cal_SBR > 0x1FFF) || (cal_SBR < 1))
{
/* unsupported baud rate for given source clock input*/
return -RT_ERROR;
}
//set UART5 pin
PORTE->PCR[ 8] = (3UL << 8); //Pin mux configured as ALT3
PORTE->PCR[ 9] = (3UL << 8); //Pin mux configured as ALT3
/* calc baud_rate */
reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
reg_BDL = cal_SBR & 0x00FF;
/* fractional divider */
reg_BRFA = ((SystemCoreClock * 32) / (cfg->baud_rate * 16)) - (cal_SBR * 32);
reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
SIM_SOPT5 &= ~ SIM_SOPT5_UART0RXSRC(0);
SIM_SOPT5 |= SIM_SOPT5_UART0RXSRC(0);
SIM_SOPT5 &= ~ SIM_SOPT5_UART0TXSRC(0);
SIM_SOPT5 |= SIM_SOPT5_UART0TXSRC(0);
// set UART0 clock
// Enable UART gate clocking
// Enable PORTE gate clocking
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
// set UART0 pin
PORTB->PCR[16] &= ~(3UL << 8);
PORTB->PCR[16] |= (3UL << 8); // Pin mux configured as ALT3
PORTB->PCR[17] &= ~(3UL << 8);
PORTB->PCR[17] |= (3UL << 8); // Pin mux configured as ALT3
break;
default:
break;
return -RT_ERROR;
}
uart_reg->BDH = reg_BDH;
@@ -153,8 +164,8 @@ static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
UART_Type *uart_reg;
int uart_irq_num = 0;
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
uart_irq_num = ((struct k60_serial_device *)serial->parent.user_data)->irq_num;
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
uart_irq_num = ((struct k64_serial_device *)serial->parent.user_data)->irq_num;
switch (cmd)
{
@@ -189,7 +200,7 @@ static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
static int _putc(struct rt_serial_device *serial, char c)
{
UART_Type *uart_reg;
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
uart_reg->D = (c & 0xFF);
@@ -199,7 +210,7 @@ static int _putc(struct rt_serial_device *serial, char c)
static int _getc(struct rt_serial_device *serial)
{
UART_Type *uart_reg;
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
if (uart_reg->S1 & UART_S1_RDRF_MASK)
return (uart_reg->D);
@@ -207,7 +218,7 @@ static int _getc(struct rt_serial_device *serial)
return -1;
}
static const struct rt_uart_ops _k60_ops =
static const struct rt_uart_ops _k64_ops =
{
_configure,
_control,
@@ -216,10 +227,10 @@ static const struct rt_uart_ops _k60_ops =
};
void UART5_RX_TX_IRQHandler(void)
void UART0_RX_TX_IRQHandler(void)
{
rt_interrupt_enter();
rt_hw_serial_isr((struct rt_serial_device*)&_k60_serial);
rt_hw_serial_isr((struct rt_serial_device*)&_k64_serial, RT_SERIAL_EVENT_RX_IND);
rt_interrupt_leave();
}
@@ -235,14 +246,14 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
_k60_serial.ops = &_k60_ops;
_k60_serial.int_rx = &_k60_int_rx;
_k60_serial.config = config;
_k64_serial.ops = &_k64_ops;
_k64_serial.config = config;
rt_hw_serial_register(&_k60_serial, "uart5",
rt_hw_serial_register(&_k64_serial, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void*)&_k60_node);
(void*)&_k64_node);
}
void rt_hw_console_output(const char *str)
@@ -250,8 +261,8 @@ void rt_hw_console_output(const char *str)
while(*str != '\0')
{
if (*str == '\n')
_putc(&_k60_serial,'\r');
_putc(&_k60_serial,*str);
_putc(&_k64_serial,'\r');
_putc(&_k64_serial,*str);
str++;
}
}
bsp/K60Fxxxx/drivers/drv_uart.h → bsp/frdm-k64f/board/drv_uart.h
+2 -5
View File
@@ -9,7 +9,7 @@
*
* Change Logs:
* Date Author Notes
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
#ifndef DRV_UART_H
@@ -19,13 +19,10 @@
#include <rtthread.h>
#include <rtdevice.h>
#include <MK60F12.H>
#include <MK64F12.h>
#include <drivers/serial.h>
#define k60_uasrt_irq_num (55)
void rt_hw_uart_init(void);
//for kernel debug when console not registered
bsp/frdm-k64f/board/led.c
+74
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@@ -0,0 +1,74 @@
/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*
*/
#include <MK64F12.h>
#include "led.h"
const rt_uint32_t led_mask[] = {1 << 21, 1 << 22, 1 << 26};
void rt_hw_led_init(void)
{
SIM_SCGC5 |= (1 << SIM_SCGC5_PORTB_SHIFT);
SIM_SCGC5 |= (1 << SIM_SCGC5_PORTE_SHIFT);
PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
PORTB->PCR[21] |= PORT_PCR_MUX(1); //PTB21 is GPIO pin
PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
PORTB->PCR[22] |= PORT_PCR_MUX(1); //PTB22 is GPIO pin
PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
PORTE->PCR[26] |= PORT_PCR_MUX(1); //PTE26 is GPIO pin
/* Switch LEDs off and enable output*/
PTB->PDDR |= GPIO_PDDR_PDD(led_mask[1] | led_mask[0]);
PTE->PDDR |= GPIO_PDDR_PDD(led_mask[2]);
rt_hw_led_off(LED_RED);
rt_hw_led_off(LED_GREEN);
rt_hw_led_off(LED_BLUE);
}
void rt_hw_led_uninit(void)
{
PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
}
void rt_hw_led_on(rt_uint32_t n)
{
if (n != LED_GREEN)
{
PTB->PCOR |= led_mask[n];
}
else
{
PTE->PCOR |= led_mask[n];
}
}
void rt_hw_led_off(rt_uint32_t n)
{
if (n != LED_GREEN)
{
PTB->PSOR |= led_mask[n];
}
else
{
PTE->PSOR |= led_mask[n];
}
}
bsp/K60Fxxxx/drivers/led.h → bsp/frdm-k64f/board/led.h
+8 -2
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@@ -9,7 +9,7 @@
*
* Change Logs:
* Date Author Notes
* 2013-07-11 reynolds port to TWR-K60F120M
*
*/
#ifndef __LED_H__
@@ -17,7 +17,13 @@
#include <rtthread.h>
#define LED_MAX 4
enum LED_NUM
{
LED_BLUE,
LED_RED,
LED_GREEN,
LED_MAX
};
void rt_hw_led_init(void);
void rt_hw_led_uninit(void);
bsp/frdm-k64f/device/MK64F12/MK64F12.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_adc.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_aips.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_axbs.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_can.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_cau.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_cmp.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_cmt.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_crc.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_dac.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_dma.h
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bsp/frdm-k64f/device/MK64F12/MK64F12_dmamux.h
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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_DMAMUX_REGISTERS_H__
#define __HW_DMAMUX_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 DMAMUX
*
* DMA channel multiplexor
*
* Registers defined in this header file:
* - HW_DMAMUX_CHCFGn - Channel Configuration register
*
* - hw_dmamux_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_DMAMUX_BASE
#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
//! @brief Table of base addresses for DMAMUX instances.
static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
REGS_DMAMUX0_BASE,
};
//! @brief Get the base address of DMAMUX by instance number.
//! @param x DMAMUX instance number, from 0 through 0.
#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of DMAMUX.
#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DMAMUX_CHCFGn - Channel Configuration register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
*
* Reset value: 0x00U
*
* Each of the DMA channels can be independently enabled/disabled and associated
* with one of the DMA slots (peripheral slots or always-on slots) in the
* system. Setting multiple CHCFG registers with the same source value will result in
* unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
* Before changing the trigger or source settings, a DMA channel must be disabled
* via CHCFGn[ENBL].
*/
typedef union _hw_dmamux_chcfgn
{
uint8_t U;
struct _hw_dmamux_chcfgn_bitfields
{
uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
uint8_t ENBL : 1; //!< [7] DMA Channel Enable
} B;
} hw_dmamux_chcfgn_t;
#endif
/*!
* @name Constants and macros for entire DMAMUX_CHCFGn register
*/
//@{
#define HW_DMAMUX_CHCFGn_COUNT (16U)
#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
#ifndef __LANGUAGE_ASM__
#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DMAMUX_CHCFGn bitfields
*/
/*!
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
*
* Specifies which DMA source, if any, is routed to a particular DMA channel.
* See your device's chip configuration details for information about the
* peripherals and their slot numbers.
*/
//@{
#define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
#define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
#endif
//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SOURCE field to a new value.
#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
#endif
//@}
/*!
* @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
*
* Enables the periodic trigger capability for the triggered DMA channel.
*
* Values:
* - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
* DMA Channel will simply route the specified source to the DMA channel.
* (Normal mode)
* - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
* DMAMUX is in Periodic Trigger mode.
*/
//@{
#define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
#define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
#define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
#endif
//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TRIG field to a new value.
#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
#endif
//@}
/*!
* @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
*
* Enables the DMA channel.
*
* Values:
* - 0 - DMA channel is disabled. This mode is primarily used during
* configuration of the DMAMux. The DMA has separate channel enables/disables, which
* should be used to disable or reconfigure a DMA channel.
* - 1 - DMA channel is enabled
*/
//@{
#define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
#define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
#define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
#endif
//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ENBL field to a new value.
#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_dmamux_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All DMAMUX module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_dmamux
{
__IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
} hw_dmamux_t;
#pragma pack()
//! @brief Macro to access all DMAMUX registers.
//! @param x DMAMUX instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
#define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
#endif
#endif // __HW_DMAMUX_REGISTERS_H__
// v22/130726/0.9
// EOF
bsp/frdm-k64f/device/MK64F12/MK64F12_enet.h
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