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update the xplorer4330 bsp.

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This commit is contained in:
nongxiaoming
2014-07-13 15:17:26 +08:00
parent e152b68e33
commit 5995b7a2a1
188 changed files with 58683 additions and 30804 deletions
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bsp/xplorer4330/Libraries/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */
bsp/xplorer4330/Libraries/CMSIS/Include/arm_math.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cm0plus.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cm3.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cm4_simd.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cmFunc.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_cmInstr.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_sc000.h
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bsp/xplorer4330/Libraries/CMSIS/Include/core_sc300.h
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bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
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bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
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/***********************************************************************
* $Id: fpu_enable.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_ENABLE_H
#define __FPU_ENABLE_H
#if defined(__ARMCC_VERSION)
void fpuEnable(void) __attribute__ ((section("BOOTSTRAP_CODE")));
#else
extern void fpuEnable(void);
#endif
#endif /* __FPU_ENABLE_H */
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
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/***********************************************************************
* $Id: fpu_init.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_INIT_H
#define __FPU_INIT_H
void fpuInit(void);
#endif /* __FPU_INIT_H */
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
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/**********************************************************************
* $Id$ system_lpc43xx.h 2011-06-02
*//**
* @file system_lpc43xx.h
* @brief Cortex-M3 Device System Header File for NXP lpc43xx Series.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SYSTEM_lpc43xx_H
#define __SYSTEM_lpc43xx_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_lpc43xx_H */
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
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;/***********************************************************************
; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
; *
; * Project: LPC43xx CMSIS Package
; *
; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; * modified by KEIL
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 M0 Core
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD EZH_IRQHandler ; 19 EZH/EDM
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD M0s_IRQHandler ; 66 M0s
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0CORE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT EZH_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT M0s_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
EZH_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WDT_IRQHandler
M0s_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
AREA |.text|,CODE, READONLY
getPC PROC
EXPORT getPC
MOV R0,LR
BX LR
ENDP
END
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
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;/***********************************************************************
; * $Id: startup_LPC43xx_M0.s 6473 2011-02-16 17:40:54Z nxp27266 $
; *
; * Project: LPC43xx CMSIS Package
; *
; * Description: Cortex-M0 Core Device Startup File for the NXP LPC43xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; * modified by KEIL
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD 0 ; 4 Reserved
DCD 0 ; 5 Reserved
DCD 0 ; 6 Reserved
DCD 0 ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD RTC_IRQHandler ; 16 RTC
DCD M4CORE_IRQHandler ; 17 M4 Core
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD 0 ; 19 Reserved
DCD FLASHEEPROMAT_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM, Atimer
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_OR_WWDT_IRQHandler ; 27 Repetitive Interrupt Timer or WWDT
DCD TIMER0_IRQHandler ; 28 Timer0
DCD GINT1_IRQHandler ; 29 GPIO global interrupt 1
DCD PIN_INT4_IRQHandler ; 30 GPIO pin interrupt 4
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor control PWM
DCD ADC0_IRQHandler ; 33 ADC0
DCD I2C0_OR_I2C1_IRQHandler ; 34 I2C or I2C1
DCD SGPIO_IRQHandler ; 35 Serial GPIO
DCD SPI_OR_DAC_IRQHandler ; 36 SPI or DAC
DCD ADC1_IRQHandler ; 37 ADC1
DCD SSP0_OR_SSP1_IRQHandler ; 38 SSP0 or SSP1
DCD EVENTROUTER_IRQHandler ; 39 Event router
DCD USART0_IRQHandler ; 40 USART0
DCD UART1_IRQHandler ; 41 UART1/Modem
DCD USART2_OR_C_CAN1_IRQHandler ; 42 USART2 or C CAN1
DCD USART3_IRQHandler ; 43 USART3
DCD I2S0_OR_I2S1_OR_QEI_IRQHandler ; 44 I2S0 or I2S1 or QEI
DCD C_CAN0_IRQHandler ; 45 C CAN0
DCD 0 ; 46 Reserved
DCD 0 ; 47 Reserved
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler\
PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT RTC_IRQHandler [WEAK]
EXPORT M4CORE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROMAT_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_OR_WWDT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_OR_I2C1_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT SPI_OR_DAC_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_OR_SSP1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_OR_C_CAN1_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_OR_I2S1_OR_QEI_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
RTC_IRQHandler
M4CORE_IRQHandler
DMA_IRQHandler
FLASHEEPROMAT_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_OR_WWDT_IRQHandler
TIMER0_IRQHandler
GINT1_IRQHandler
PIN_INT4_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_OR_I2C1_IRQHandler
SGPIO_IRQHandler
SPI_OR_DAC_IRQHandler
ADC1_IRQHandler
SSP0_OR_SSP1_IRQHandler
EVENTROUTER_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_OR_C_CAN1_IRQHandler
USART3_IRQHandler
I2S0_OR_I2S1_OR_QEI_IRQHandler
C_CAN0_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
AREA |.text|,CODE, READONLY
getPC PROC
EXPORT getPC
MOV R0,LR
BX LR
ENDP
END
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
+502
View File
File diff suppressed because it is too large Load Diff
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
+463
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@@ -0,0 +1,463 @@
//*****************************************************************************
// LPC43xx (Cortex M0 SUB) Startup code for use with LPCXpresso IDE
//
// Version : 131115
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2013
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
void SystemInit(void);
#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
#if defined (__USE_LPCOPEN)
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
#else
WEAK void M0S_NMI_Handler(void);
WEAK void M0S_HardFault_Handler (void);
WEAK void M0S_SVC_Handler(void);
WEAK void M0S_PendSV_Handler(void);
WEAK void M0S_SysTick_Handler(void);
WEAK void M0S_IntDefaultHandler(void);
#endif
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
#if defined (__USE_LPCOPEN)
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
void M4_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void SGPIO_INPUT_IRQHandler(void) ALIAS(IntDefaultHandler);
void SGPIO_MATCH_IRQHandler(void) ALIAS(IntDefaultHandler);
void SGPIO_SHIFT_IRQHandler(void) ALIAS(IntDefaultHandler);
void SGPIO_POS_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S0_I2S1_QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPIFI_ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void M0S_DAC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_M4CORE_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_DMA_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SGPIO_INPUT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SGPIO_MATCH_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SGPIO_SHIFT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SGPIO_POS_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_USB0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_USB1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SCT_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_RITIMER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_GINT1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_TIMER1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_TIMER2_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_PIN_INT5_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_ADC0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_MCPWM_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_I2C0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_I2C1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SPI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_ADC1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SSP0_OR_SSP1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_EVENTROUTER_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_USART0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_UART1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_USART2_OR_C_CAN1_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_USART3_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_C_CAN0_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_SPIFI_OR_VADC_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
void M0S_M0APP_IRQHandler(void) ALIAS(M0S_IntDefaultHandler);
#endif
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
#if defined (__USE_LPCOPEN)
// Core Level - CM0
&_vStackTop, // The initial stack pointer
ResetISR, // 1 The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // 4 Reserved
0, // 5 Reserved
0, // 6 Reserved
0, // 7 Reserved
0, // 8 Reserved
0, // 9 Reserved
0, // 10 Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - 43xx M0SUB core
DAC_IRQHandler, // 16
M4_IRQHandler, // 17 Interrupt from M4 Core
DMA_IRQHandler, // 18 General Purpose DMA
0, // 19 Reserved
SGPIO_INPUT_IRQHandler, // 20
SGPIO_MATCH_IRQHandler, // 21
SGPIO_SHIFT_IRQHandler, // 22
SGPIO_POS_IRQHandler, // 23
USB0_IRQHandler, // 24 USB0
USB1_IRQHandler, // 25 USB1
SCT_IRQHandler , // 26 State Configurable Timer
RIT_IRQHandler, // 27 Repetitive Interrupt Timer
GINT1_IRQHandler, // 28 GINT1
TIMER1_IRQHandler, // 29 Timer1
TIMER2_IRQHandler, // 30 Timer2
GPIO5_IRQHandler, // 31
MCPWM_IRQHandler, // 32 Motor Control PWM
ADC0_IRQHandler, // 33 ADC0
I2C0_IRQHandler, // 34
I2C1_IRQHandler, // 35
SPI_IRQHandler, // 36
ADC1_IRQHandler, // 37
SSP0_SSP1_IRQHandler, // 38
EVRT_IRQHandler, // 39 Event Router
UART0_IRQHandler, // 41 USART0
UART1_IRQHandler, // 41 UART1
UART2_CAN1_IRQHandler, // 42 USART2 or C CAN1
UART3_IRQHandler, // 43 USART3
I2S0_I2S1_QEI_IRQHandler, // 35 I2C0 or I2C1 or I2S1 or QEI
CAN0_IRQHandler, // 45 C CAN0
SPIFI_ADCHS_IRQHandler, // 46
M0APP_IRQHandler, // 47 Interrupt from M0APP
};
#else
// Core Level - CM0
&_vStackTop, // The initial stack pointer
ResetISR, // 1 The reset handler
M0S_NMI_Handler, // 2 The NMI handler
M0S_HardFault_Handler, // 3 The hard fault handler
0, // 4 Reserved
0, // 5 Reserved
0, // 6 Reserved
0, // 7 Reserved
0, // 8 Reserved
0, // 9 Reserved
0, // 10 Reserved
M0S_SVC_Handler, // 11 SVCall handler
M0S_DebugMon_Handler, // 12 Debug monitor handler
0, // 13 Reserved
M0S_PendSV_Handler, // 14 The PendSV handler
M0S_SysTick_Handler, // 15 The SysTick handler
// Chip Level - LPC43 (CM0 SUB)
M0S_DAC_IRQHandler, // 16
M0S_M4CORE_IRQHandler, // 17 Interrupt from M4 Core
M0S_DMA_IRQHandler, // 18 General Purpose DMA
0, // 19 Reserved
M0S_SGPIO_INPUT_IRQHandler, // 20
M0S_SGPIO_MATCH_IRQHandler, // 21
M0S_SGPIO_SHIFT_IRQHandler, // 22
M0S_SGPIO_POS_IRQHandler, // 23
M0S_USB0_IRQHandler, // 24 USB0
M0S_USB1_IRQHandler, // 25 USB1
M0S_SCT_IRQHandler , // 26 State Configurable Timer
M0S_RITIMER_IRQHandler, // 27 Repetitive Interrupt Timer
M0S_GINT1_IRQHandler, // 28 GINT1
M0S_TIMER1_IRQHandler, // 29 Timer1
M0S_TIMER2_IRQHandler, // 30 Timer2
M0S_PIN_INT5_IRQHandler, // 31
M0S_MCPWM_IRQHandler, // 32 Motor Control PWM
M0S_ADC0_IRQHandler, // 33 ADC0
M0S_I2C0_IRQHandler, // 34
M0S_I2C1_IRQHandler, // 35
M0S_SPI_IRQHandler, // 36
M0S_ADC1_IRQHandler, // 37
M0S_SSP0_OR_SSP1_IRQHandler, // 38
M0S_EVENTROUTER_IRQHandler, // 39 Event Router
M0S_USART0_IRQHandler, // 41 USART0
M0S_UART1_IRQHandler, // 41 UART1
M0S_USART2_OR_C_CAN1_IRQHandler, // 42 USART2 or C CAN1
M0S_USART3_IRQHandler, // 43 USART3
M0S_I2C0_OR_I2C1_OR_I2S1_OR_QEI_IRQHandler,
// 35 I2C0 or I2C1 or I2S1 or QEI
M0S_C_CAN0_IRQHandler, // 45 C CAN0
M0S_SPIFI_OR_VADC_IRQHandler, // 46
M0S_M0APP_IRQHandler, // 47 Interrupt from M0APP
};
#endif
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
//*****************************************************************************
void
ResetISR(void) {
// ******************************
// Modify CREG->M0SUBMEMMAP so that M0 looks in correct place
// for its vector table when an exception is triggered.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int *pCREG_M0SUBMEMMAP = (unsigned int *) 0x40043308;
// CMSIS : CREG->M0SUBMEMMAP = <address of vector table>
*pCREG_M0SUBMEMMAP = (unsigned int)g_pfnVectors;
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
// **********************************************************
// No need to call SystemInit() here, as master CM4 cpu will
// have done the main system set up before enabling CM0.
// **********************************************************
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
#if defined (__USE_LPCOPEN)
void NMI_Handler(void)
#else
void M0S_NMI_Handler(void)
#endif
{ while(1) { }
}
__attribute__ ((section(".after_vectors")))
#if defined (__USE_LPCOPEN)
void HardFault_Handler(void)
#else
void M0S_HardFault_Handler(void)
#endif
{ while(1) { }
}
__attribute__ ((section(".after_vectors")))
#if defined (__USE_LPCOPEN)
void SVC_Handler(void)
#else
void M0S_SVC_Handler(void)
#endif
{ while(1) { }
}
__attribute__ ((section(".after_vectors")))
#if defined (__USE_LPCOPEN)
void PendSV_Handler(void)
#else
void M0S_PendSV_Handler(void)
#endif
{ while(1) { }
}
__attribute__ ((section(".after_vectors")))
#if defined (__USE_LPCOPEN)
void SysTick_Handler(void)
#else
void M0S_SysTick_Handler(void)
#endif
{ while(1) { }
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
#if defined (__USE_LPCOPEN)
void IntDefaultHandler(void)
#else
void M0S_IntDefaultHandler(void)
#endif
{ while(1) { }
}
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
+431
View File
@@ -0,0 +1,431 @@
;/*****************************************************************************
; * @file: startup_LPC18xx.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC18xx Device Series
; * @version: V1.00
; * @date: 24. May. 2011
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
Sign_Value EQU 0x5A5A5A5A
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD Sign_Value
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD 0 ; 17 Event Router
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD 0 ; 19 Reserved
DCD 0 ; 20 Reserved
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD 0 ; 36 Reserved
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD 0 ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD 0 ; 66 M0s
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
DAC_IRQHandler
B DAC_IRQHandler
PUBWEAK EVRT_IRQHandler
SECTION .text:CODE:REORDER(1)
EVRT_IRQHandler
B EVRT_IRQHandler
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK USB0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB0_IRQHandler
B USB0_IRQHandler
PUBWEAK USB1_IRQHandler
SECTION .text:CODE:REORDER(1)
USB1_IRQHandler
B USB1_IRQHandler
PUBWEAK SCT_IRQHandler
SECTION .text:CODE:REORDER(1)
SCT_IRQHandler
B SCT_IRQHandler
PUBWEAK RIT_IRQHandler
SECTION .text:CODE:REORDER(1)
RIT_IRQHandler
B RIT_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK MCPWM_IRQHandler
SECTION .text:CODE:REORDER(1)
MCPWM_IRQHandler
B MCPWM_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK SSP0_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP0_IRQHandler
B SSP0_IRQHandler
PUBWEAK SSP1_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP1_IRQHandler
B SSP1_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK UART2_IRQHandler
SECTION .text:CODE:REORDER(1)
UART2_IRQHandler
B UART2_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK I2S0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2S0_IRQHandler
B I2S0_IRQHandler
PUBWEAK I2S1_IRQHandler
SECTION .text:CODE:REORDER(1)
I2S1_IRQHandler
B I2S1_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK SPIFI_IRQHandler
SECTION .text:CODE:REORDER(1)
SPIFI_IRQHandler
B SPIFI_IRQHandler
PUBWEAK SGPIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SGPIO_IRQHandler
B SGPIO_IRQHandler
PUBWEAK GPIO0_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO0_IRQHandler
B GPIO0_IRQHandler
PUBWEAK GPIO1_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO1_IRQHandler
B GPIO1_IRQHandler
PUBWEAK GPIO2_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO2_IRQHandler
B GPIO2_IRQHandler
PUBWEAK GPIO3_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO3_IRQHandler
B GPIO3_IRQHandler
PUBWEAK GPIO4_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO4_IRQHandler
B GPIO4_IRQHandler
PUBWEAK GPIO5_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO5_IRQHandler
B GPIO5_IRQHandler
PUBWEAK GPIO6_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO6_IRQHandler
B GPIO6_IRQHandler
PUBWEAK GPIO7_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO7_IRQHandler
B GPIO7_IRQHandler
PUBWEAK GINT0_IRQHandler
SECTION .text:CODE:REORDER(1)
GINT0_IRQHandler
B GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
SECTION .text:CODE:REORDER(1)
GINT1_IRQHandler
B GINT1_IRQHandler
PUBWEAK CAN1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_IRQHandler
B CAN1_IRQHandler
PUBWEAK ATIMER_IRQHandler
SECTION .text:CODE:REORDER(1)
ATIMER_IRQHandler
B ATIMER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER(1)
WDT_IRQHandler
B WDT_IRQHandler
PUBWEAK CAN0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN0_IRQHandler
B CAN0_IRQHandler
PUBWEAK QEI_IRQHandler
SECTION .text:CODE:REORDER(1)
QEI_IRQHandler
B QEI_IRQHandler
PUBWEAK getPC
SECTION .text:CODE:REORDER(2)
getPC
MOV R0,LR
BX LR
END
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
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/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2011 IAR Systems. All rights reserved.
*
* $Revision: 47876 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD DAC_IRQHandler
DCD M4_IRQHandler
DCD DMA_IRQHandler
DCD 0
DCD SGPIO_INPUT_IRQHandler
DCD SGPIO_MATCH_IRQHandler
DCD SGPIO_SHIFT_IRQHandler
DCD SGPIO_POS_IRQHandler
DCD USB0_IRQHandler
DCD USB1_IRQHandler
DCD SCT_IRQHandler
DCD RIT_IRQHandler
DCD GINT1_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD GPIO5_IRQHandler
DCD MCPWM_IRQHandler
DCD ADC0_IRQHandler
DCD I2C0_IRQHandler
DCD I2C1_IRQHandler
DCD SPI_IRQHandler
DCD ADC1_IRQHandler
DCD SSP0_SSP1_IRQHandler
DCD EVRT_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD UART2_CAN1_IRQHandler
DCD UART3_IRQHandler
DCD I2S0_I2S1_QEI_IRQHandler
DCD CAN0_IRQHandler
DCD SPIFI_ADCHS_IRQHandler
DCD M0APP_IRQHandler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK DAC_IRQHandler
PUBWEAK M4_IRQHandler
PUBWEAK DMA_IRQHandler
PUBWEAK UnHandled_Vector
PUBWEAK SGPIO_INPUT_IRQHandler
PUBWEAK SGPIO_MATCH_IRQHandler
PUBWEAK SGPIO_SHIFT_IRQHandler
PUBWEAK SGPIO_POS_IRQHandler
PUBWEAK USB0_IRQHandler
PUBWEAK USB1_IRQHandler
PUBWEAK SCT_IRQHandler
PUBWEAK RIT_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
PUBWEAK GPIO5_IRQHandler
PUBWEAK MCPWM_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK SPI_IRQHandler
PUBWEAK ADC1_IRQHandler
PUBWEAK SSP0_SSP1_IRQHandler
PUBWEAK EVRT_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_CAN1_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK I2S0_I2S1_QEI_IRQHandler
PUBWEAK CAN0_IRQHandler
PUBWEAK SPIFI_ADCHS_IRQHandler
PUBWEAK M0APP_IRQHandler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B .
SVC_Handler
B .
DebugMon_Handler
B .
PendSV_Handler
B .
SysTick_Handler
B .
HardFault_Handler
B .
MemManage_Handler
B .
BusFault_Handler
B .
UsageFault_Handler
DAC_IRQHandler
M4_IRQHandler
DMA_IRQHandler
UnHandled_Vector
SGPIO_INPUT_IRQHandler
SGPIO_MATCH_IRQHandler
SGPIO_SHIFT_IRQHandler
SGPIO_POS_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
GINT1_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
GPIO5_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_SSP1_IRQHandler
EVRT_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_CAN1_IRQHandler
UART3_IRQHandler
I2S0_I2S1_QEI_IRQHandler
CAN0_IRQHandler
SPIFI_ADCHS_IRQHandler
M0APP_IRQHandler
Default_IRQHandler
B .
/* CRP Section - not needed for flashless devices */
;;; SECTION .crp:CODE:ROOT(2)
;;; DATA
/* Code Read Protection
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
- Copy RAM to flash command can not write to Sector 0.
- Erase command can erase Sector 0 only when all sectors
are selected for erase.
- Compare command is disabled.
- Read Memory command is disabled.
CRP2 0x87654321 - Read Memory is disabled.
- Write to RAM is disabled.
- "Go" command is disabled.
- Copy RAM to flash is disabled.
- Compare is disabled.
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
by pulling PIO0_1 LOW is disabled if a valid user code is
present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
;;; DCD 0xFFFFFFFF
;;;
END
bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
+892
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bsp/xplorer4330/Libraries/Device/SConscript
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# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Split('''
NXP/LPC43xx/Source/Templates/system_LPC43xx.c
''')
CPPPATH = [cwd + '/NXP/LPC43xx/Include', cwd + '/../CMSIS/Include']
CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
# add for startup script
if rtconfig.USE_CORE =='CORE_M4':
if rtconfig.CROSS_TOOL == 'gcc':
src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s']
else:
if rtconfig.CROSS_TOOL == 'gcc':
src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s']
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/xplorer4330/M0/SConscript
+13
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from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(os.path.join(cwd, '..'))
for d in list:
if (d != 'M4' and d != 'M0'):
path = os.path.join(cwd, '..', d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(path, 'SConscript'))
Return('objs')
bsp/xplorer4330/M0/SConstruct
+29
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@@ -0,0 +1,29 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# do building
DoBuilding(TARGET, objs)
bsp/xplorer4330/M0/rtconfig.h
+230
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/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 8
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 1000
// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
#define IDLE_THREAD_STACK_SIZE 512
// <bool name="RT_USING_MODULE" description="Using Application Module" default="true" />
//#define RT_USING_MODULE
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
#define RT_DEBUG_INIT 0
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
#define RT_USING_OVERFLOW_CHECK
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
#define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 100
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
#define RT_USING_SEMAPHORE
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
#define RT_USING_MUTEX
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
#define RT_USING_EVENT
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
#define RT_USING_MAILBOX
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
#define RT_USING_MESSAGEQUEUE
// </section>
// <section name="MM" description="Memory Management" default="always" >
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
#define RT_USING_MEMPOOL
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
#define RT_USING_MEMHEAP
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
#define RT_USING_HEAP
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
#define RT_USING_SMALL_MEM
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
// #define RT_USING_SLAB
// </section>
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
#define RT_USING_DEVICE
// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
#define RT_USING_DEVICE_IPC
// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
#define RT_USING_SERIAL
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 256
// <bool name="RT_USING_MTD_NAND" description="Using MTD NAND Framework" default="true" />
//#define RT_USING_MTD_NAND
// <bool name="RT_MTD_NAND_DEBUG" description="Enable MTD NAND Framework Debug" default="true" />
//#define RT_MTD_NAND_DEBUG
// <bool name="RT_USING_NFTL" description="Using NFTL layer" default="true" />
//#define RT_USING_NFTL
// <bool name="RT_USING_SPI" description="Using SPI Device Driver Framework" default="true" />
//#define RT_USING_SPI
// <bool name="RT_USING_I2C" description="Using I2C Device Driver Framework" default="true" />
//#define RT_USING_I2C
// <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" />
//#define RT_USING_RTC
// <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" />
#define RT_MMCSD_THREAD_PREORITY 15
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
//#define RT_USING_COMPONENTS_INIT
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
#define RT_USING_FINSH
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
#define FINSH_USING_SYMTAB
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
// <bool name="FINSH_USING_MSH" description="Using module shell in finsh" default="true" />
//#define FINSH_USING_MSH
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
// #define RT_USING_NEWLIB
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
//#define RT_USING_PTHREADS
// </section>
// <section name="RT_USING_DFS" description="Device file system" default="true" >
//#define RT_USING_DFS
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
//#define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
#define DFS_FILESYSTEM_TYPES_MAX 4
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 4
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 16
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" />
#define RT_DFS_ELM_DRIVES 4
// <bool name="RT_DFS_ELM_REENTRANT" description="Support reentrant" default="true" />
#define RT_DFS_ELM_REENTRANT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN with static LFN working buffer">1</item>
// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 3
// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
#define RT_DFS_ELM_CODE_PAGE 936
// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
#define RT_DFS_ELM_CODE_PAGE_FILE
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
#define RT_DFS_ELM_MAX_LFN 256
// <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" />
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
// <bool name="RT_DFS_ELM_USE_ERASE" description="Enable erase feature for flash" default="true" />
#define RT_DFS_ELM_USE_ERASE
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
// #define RT_USING_DFS_UFFS
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
#define RT_USING_DFS_DEVFS
// <bool name="RT_USING_DFS_ROMFS" description="Using ROMFS" default="false" />
//#define RT_USING_DFS_ROMFS
// <bool name="RT_USING_DFS_NFS" description="Using NFS" default="false" />
//#define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="The exported NFS host path" default="192.168.1.10:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.20:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
//#define RT_USING_LWIP
// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
#define RT_USING_LWIP141
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
#define RT_LWIP_ICMP
// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
// #define RT_LWIP_IGMP
// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
#define RT_LWIP_UDP
// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
#define RT_LWIP_TCP
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF 4086
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
#define RT_LWIP_TCP_SEG_NUM 8
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
// </section>
// </RDTConfigurator>
#endif
bsp/xplorer4330/M0/rtconfig.py
+139
View File
@@ -0,0 +1,139 @@
import os
# core to be use
USE_CORE = 'CORE_M0'
#USE_CORE = 'CORE_M4'
# toolchains options
ARCH='arm'
if USE_CORE == 'CORE_M4':
CPU = 'cortex-m4'
else:
CPU = 'cortex-m0'
CROSS_TOOL='keil'
# get setting from environment.
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'D:/Keil'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
#
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
if USE_CORE == 'CORE_M4':
DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMSTM'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
CFLAGS = ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
if USE_CORE == 'CORE_M4':
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' --fpu=None'
else:
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
if USE_CORE == 'CORE_M4':
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu None'
else:
AFLAGS += ' --cpu Cortex-M0'
LFLAGS = ' --config lpc43xx_flash.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = IAR_PATH + '/arm/bin/'
POST_ACTION = ''
bsp/xplorer4330/M0/template.uvproj
+777
View File
File diff suppressed because it is too large Load Diff
bsp/xplorer4330/applications/SConscript
+3 -3
View File
@@ -2,10 +2,10 @@ Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('applications', src, depend = [''], CPPPATH = CPPPATH)
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/xplorer4330/applications/application.c
+58 -36
View File
@@ -1,7 +1,7 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -9,54 +9,76 @@
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2014-07-13 xiaonong port for lpc43xx
*/
/**
* @addtogroup LPC4330
*/
/*@{*/
#include <rtthread.h>
#ifdef RT_USING_COMPONENTS_INIT
#include <components.h>
#include <board.h>
#include <rtdevice.h>
#include "drv_led.h"
#ifdef RT_USING_FINSH
#include <finsh.h>
#include <shell.h>
#endif
#include "board_ngx_xplorer_18304330.h"
static void rt_init_thread_entry(void *parameter)
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
Board_LED_Init();
#ifdef RT_USING_COMPONENTS_INIT
/* initialization RT-Thread Components */
rt_components_init();
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/*the led thread*/
ALIGN(RT_ALIGN_SIZE)
static rt_uint8_t led_stack[ 512 ];
static struct rt_thread led_thread;
static void led_thread_entry(void *parameter)
{
rt_uint8_t led_value = 0;
rt_device_t led_dev;
rt_led_hw_init();
led_dev = rt_device_find("led");
if (led_dev == RT_NULL)
{
rt_kprintf("can not find the led device!\n");
return;
}
while (1)
{
Board_LED_Set(0, 1);
rt_thread_delay(50);
Board_LED_Set(0, 0);
rt_thread_delay(50);
/* led0 on */
led_value = 1;
led_dev->write(led_dev, 0, &led_value, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
/* led0 off */
led_value = 0;
led_dev->write(led_dev, 0, &led_value, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2);
}
}
void rt_application_init(void)
int rt_application_init(void)
{
rt_thread_t tid;
rt_err_t result;
tid = rt_thread_create("init",
rt_init_thread_entry,
RT_NULL,
2048,
RT_THREAD_PRIORITY_MAX / 3,
20);
if (tid != RT_NULL)
rt_thread_startup(tid);
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX / 3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
/* init led thread */
result = rt_thread_init(&led_thread,
"led",
led_thread_entry,
RT_NULL,
(rt_uint8_t *)&led_stack[0],
sizeof(led_stack),
20,
5);
if (result == RT_EOK)
{
rt_thread_startup(&led_thread);
}
return 0;
}
/*@}*/
bsp/xplorer4330/applications/startup.c
+18 -38
View File
@@ -1,7 +1,7 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -10,67 +10,49 @@
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2012-12-11 lgnq modified for LPC4330
* 2014-07-13 xiaonong for LPC43xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "platform.h"
#include "board.h"
/**
* @addtogroup LPC4330
*/
/*@{*/
extern int rt_application_init(void);
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define LPC4300_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define LPC4300_SRAM_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define LPC4300_SRAM_BEGIN (&__bss_end)
#endif
extern int rt_application_init(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_system_heap_init((void *)LPC4300_SRAM_BEGIN, (void *)(0x10000000 + 1024*128));
#if LPC_EXT_SDRAM
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#endif
/* init scheduler system */
/* initialize scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* init all device */
rt_device_init_all();
#endif
/* init application */
rt_application_init();
/* initialize timer */
/* initialize system timer*/
rt_system_timer_init();
/* init timer thread */
/* initialize application */
rt_application_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* init idle thread */
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
@@ -90,5 +72,3 @@ int main(void)
return 0;
}
/*@}*/
bsp/xplorer4330/drivers/SConscript
+3 -5
View File
@@ -1,16 +1,14 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_SERIAL') == False:
SrcRemove(src, 'usart.c')
if GetDepend('RT_USING_LWIP') == False:
SrcRemove(src, 'drv_emac.c')
CPPPATH = [cwd]
group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH)
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/xplorer4330/drivers/board.c
+77
View File
@@ -0,0 +1,77 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2014-06-20 xiaonong ported to LPC43xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
extern void SystemCoreClockUpdate(void);
/**
* This function will initial LPC43xx board.
*/
void rt_hw_board_init()
{
#ifdef CORE_M4
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
#endif
/* update the core clock */
SystemCoreClockUpdate();
/* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
/* init uart device */
rt_hw_uart_init();
/* setup the console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#if LPC_EXT_SDRAM == 1
lpc_sdram_hw_init();
mpu_init();
#endif
}
bsp/xplorer4330/drivers/board.h
+60
View File
@@ -0,0 +1,60 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
* 2010-02-04 Magicoe add board.h to LPC176x bsp
* 2013-12-18 Bernard porting to LPC4088 bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "LPC43xx.h"
#include <rtthread.h>
/* disable SDRAM in default */
#ifndef LPC_EXT_SDRAM
#define LPC_EXT_SDRAM 0
#endif
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
//#define RT_USING_UART2
// </RDTConfigurator>
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (void*)(0x10000000 + 0x20000)
void rt_hw_board_init(void);
int rt_hw_board_heap_init(void);
#endif
bsp/xplorer4330/drivers/drv_led.c
+162
View File
@@ -0,0 +1,162 @@
#include <rtthread.h>
#include "board.h"
#include "drv_led.h"
/**
*
* LED1 <==> GPIO1[11]
* LED2 <==> GPIO1[12]
*
**/
#define LED_NUM 2
#define LED1_PIN 11
#define LED1_PORT 1
#define LED2_PIN 12
#define LED2_PORT 1
struct led_ctrl
{
uint8_t num;
uint8_t port;
};
struct lpc_led
{
/* inherit from rt_device */
struct rt_device parent;
struct led_ctrl ctrl[LED_NUM];
};
static struct lpc_led led;
static rt_err_t rt_led_init(rt_device_t dev)
{
/* Enable clock and init GPIO outputs */
LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
/* set GPIO1[11] GPIO1[12] as GPIO. */
LPC_SCU->SFSP2_11 = 0; /* GPIO1[11] */
LPC_SCU->SFSP2_12 = 0; /* GPIO1[12] */
/* set GPIO1[11] GPIO1[12] output. */
LPC_GPIO_PORT->DIR[LED1_PORT] |= 0x01 << LED1_PIN;
LPC_GPIO_PORT->DIR[LED2_PORT] |= 0x01 << LED2_PIN;
/* turn off all the led */
LPC_GPIO_PORT->SET[LED1_PORT] |= 0x01 << LED1_PIN;
LPC_GPIO_PORT->SET[LED2_PORT] |= 0x01 << LED2_PIN;
led.ctrl[0].num = LED1_PIN;
led.ctrl[0].port = LED1_PORT;
led.ctrl[1].num = LED2_PIN;
led.ctrl[1].port = LED2_PORT;
return RT_EOK;
}
static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_led_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
rt_size_t size)
{
rt_ubase_t index = 0;
rt_ubase_t nr = size;
rt_uint8_t *value = buffer;
RT_ASSERT(dev == &led.parent);
RT_ASSERT((pos + size) <= LED_NUM);
for (index = 0; index < nr; index++)
{
if ((LPC_GPIO_PORT->PIN[led.ctrl[pos + index].port] & (1 << led.ctrl[pos + index].num)) != 0)
{
*value = 0;
}
else
{
*value = 1;
}
value++;
}
return index;
}
static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
const void *buffer, rt_size_t size)
{
rt_ubase_t index = 0;
rt_ubase_t nw = size;
const rt_uint8_t *value = buffer;
RT_ASSERT(dev == &led.parent);
RT_ASSERT((pos + size) <= LED_NUM);
for (index = 0; index < nw; index++)
{
if (*value++)
{
LPC_GPIO_PORT->CLR[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
}
else
{
LPC_GPIO_PORT->SET[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
}
}
return index;
}
static rt_err_t rt_led_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
RT_ASSERT(dev == &led.parent);
if (cmd == LED_DEVICE_CTRL)
{
rt_uint32_t *led_num = args;
*led_num = LED_NUM;
}
return RT_EOK;
}
int rt_led_hw_init(void)
{
led.parent.type = RT_Device_Class_Char;
led.parent.rx_indicate = RT_NULL;
led.parent.tx_complete = RT_NULL;
led.parent.init = rt_led_init;
led.parent.open = rt_led_open;
led.parent.close = rt_led_close;
led.parent.read = rt_led_read;
led.parent.write = rt_led_write;
led.parent.control = rt_led_control;
led.parent.user_data = RT_NULL;
/* register a character device */
rt_device_register(&led.parent, "led", RT_DEVICE_FLAG_RDWR);
/* init led device */
rt_led_init(&led.parent);
return 0;
}
INIT_DEVICE_EXPORT(rt_led_hw_init);
#ifdef RT_USING_FINSH
#include <finsh.h>
void led_test(rt_uint32_t led_num, rt_uint32_t value)
{
rt_uint8_t led_value = value;
rt_led_write(&led.parent, led_num, &led_value, 1);
}
FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 100).)
#endif
bsp/xplorer4330/drivers/drv_led.h
+12
View File
@@ -0,0 +1,12 @@
#ifndef __DRV_LED_H
#define __DRV_LED_H
/* Clock Control Unit register bits */
#define CCU_CLK_CFG_RUN (1 << 0)
#define CCU_CLK_CFG_AUTO (1 << 1)
#define CCU_CLK_STAT_RUN (1 << 0)
#define LED_DEVICE_CTRL 0x81 /*LED control command*/
int rt_led_hw_init(void);
#endif
bsp/xplorer4330/drivers/drv_uart.c
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/*
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-05-18 Bernard The first version for LPC40xx
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_uart.h"
struct lpc_uart
{
LPC_USARTn_Type *USART;
IRQn_Type USART_IRQn;
};
static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
// struct lpc_uart *uart;
RT_ASSERT(serial != RT_NULL);
// uart = (struct lpc_uart *)serial->parent.user_data;
// Initialize FIFO for UART0 peripheral
// UART_FIFOConfig(uart->USART, &UARTFIFOConfigStruct);
// UART_TxCmd(uart->USART, ENABLE);
return RT_EOK;
}
static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct lpc_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
uart->USART->IER &= ~UART_IER_RBRINT_EN;
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
uart->USART->IER |= UART_IER_RBRINT_EN;
break;
}
return RT_EOK;
}
static int lpc_putc(struct rt_serial_device *serial, char c)
{
struct lpc_uart *uart;
uart = (struct lpc_uart *)serial->parent.user_data;
while (!(uart->USART->LSR & 0x20));
uart->USART->THR = c;
return 1;
}
static int lpc_getc(struct rt_serial_device *serial)
{
struct lpc_uart *uart;
uart = (struct lpc_uart *)serial->parent.user_data;
if (uart->USART->LSR & 0x01)
{
return (uart->USART->RBR);
}
return -1;
}
static const struct rt_uart_ops lpc_uart_ops =
{
lpc_configure,
lpc_control,
lpc_putc,
lpc_getc,
};
#if defined(RT_USING_UART0)
/* UART0 device driver structure */
struct serial_ringbuffer uart0_int_rx;
struct lpc_uart uart0 =
{
LPC_USART0,
USART0_IRQn,
};
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
struct lpc_uart *uart;
volatile uint32_t intsrc, temp;
uart = &uart0;
/* enter interrupt */
rt_interrupt_enter();
/* Determine the interrupt source */
intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
switch (intsrc)
{
case UART_IIR_INTID_RLS: /* Receive Line Status interrupt*/
/* read the line status */
intsrc = uart->USART->LSR;
/* Receive an error data */
if (intsrc & UART_LSR_PE)
{
temp = LPC_USART0->RBR;
}
break;
case UART_IIR_INTID_RDA: /* Receive data */
case UART_IIR_INTID_CTI: /* Receive data timeout */
/* read the data to buffer */
while (uart->USART->LSR & UART_LSR_RDR)
{
rt_hw_serial_isr(&serial0);
}
break;
default:
break;
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(RT_USING_UART2)
/* UART2 device driver structure */
struct serial_ringbuffer uart2_int_rx;
struct lpc_uart uart2 =
{
LPC_USART2,
USART2_IRQn,
};
struct rt_serial_device serial2;
void UART2_IRQHandler(void)
{
struct lpc_uart *uart;
uint32_t intsrc, temp;
uart = &uart2;
/* enter interrupt */
rt_interrupt_enter();
/* Determine the interrupt source */
intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
switch (intsrc)
{
case UART_IIR_INTID_RLS: /* Receive Line Status interrupt*/
/* read the line status */
intsrc = uart->USART->LSR;
/* Receive an error data */
if (intsrc & UART_LSR_PE)
{
temp = LPC_USART0->RBR;
}
break;
case UART_IIR_INTID_RDA: /* Receive data */
case UART_IIR_INTID_CTI: /* Receive data timeout */
/* read the data to buffer */
while (uart->USART->LSR & UART_LSR_RDR)
{
rt_hw_serial_isr(&serial0);
}
break;
default:
break;
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
void rt_hw_uart_init(void)
{
struct lpc_uart *uart;
struct serial_configure config;
#ifdef RT_USING_UART0
uart = &uart0;
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial0.ops = &lpc_uart_ops;
serial0.int_rx = &uart0_int_rx;
serial0.config = config;
/* Enable GPIO register interface clock */
LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01));
/* Enable USART1 peripheral clock */
LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
while (!(LPC_CCU2->CLK_APB0_USART0_STAT & 0x01));
/* Enable USART1 register interface clock */
LPC_CCU1->CLK_M4_USART0_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_USART0_STAT & 0x01));
/* Init GPIO pins */
LPC_SCU->SFSP6_4 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */
(2 << 0) ; /* Pin P6_4 used as U0_TXD */
LPC_SCU->SFSP6_5 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */
(2 << 0) ; /* Pin P6_5 used as U0_RXD */
/* Init USART0 */
LPC_USART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
LPC_USART0->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */
LPC_USART0->DLM = 0x00;
LPC_USART0->FDR = 0xC1;
LPC_USART0->LCR = 0x03; /* DLAB = 0 */
/* enable the receive interrupt */
LPC_USART0->IER |= UART_IER_RBRINT_EN;
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->USART_IRQn);
/* register UART1 device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
uart);
#endif
#ifdef RT_USING_UART2
uart = &uart2;
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial2.ops = &lpc_uart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config = config;
/* Enable GPIO register interface clock */
LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01));
/* Enable USART1 peripheral clock */
LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
while (!(LPC_CCU2->CLK_APB2_USART2_STAT & 0x01));
/* Enable USART2 register interface clock */
LPC_CCU1->CLK_M4_USART0_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_USART2_STAT & 0x01));
/* Init GPIO pins */
LPC_SCU->SFSP1_15 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */
(1 << 0) ; /* Pin P1_15 used as U2_TXD */
LPC_SCU->SFSP1_16 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */
(1 << 0) ; /* Pin P1_16 used as U2_RXD */
/* Init USART2 */
LPC_USART2->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
LPC_USART2->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */
LPC_USART2->DLM = 0x00;
LPC_USART2->FDR = 0xC1;
LPC_USART2->LCR = 0x03; /* DLAB = 0 */
/* enable the receive interrupt */
LPC_USART2->IER |= UART_IER_RBRINT_EN;
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->USART_IRQn);
/* register UART1 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
uart);
#endif
}
bsp/xplorer4330/drivers/drv_uart.h
+228
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#ifndef __UART_H__
#define __UART_H__
/* Accepted Error baud rate value (in percent unit) */
#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Receiver Buffer Register
**********************************************************************/
#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Transmit Holding Register
**********************************************************************/
#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch LSB register
**********************************************************************/
#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch MSB register
**********************************************************************/
#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt enable register
**********************************************************************/
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt identification register
**********************************************************************/
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO control register
**********************************************************************/
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
#define UART_TX_FIFO_SIZE (16)
/*********************************************************************//**
* Macro defines for Macro defines for UART line control register
**********************************************************************/
#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 Modem Control Register
**********************************************************************/
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART line status register
**********************************************************************/
#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Modem (UART1 only) status register
**********************************************************************/
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART Scratch Pad Register
**********************************************************************/
#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Auto baudrate control register
**********************************************************************/
#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART IrDA control register
**********************************************************************/
#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART half duplex register
**********************************************************************/
#define UART_HDEN_HDEN ((uint32_t)(1<<0)) /**< enable half-duplex mode*/
/*********************************************************************//**
* Macro defines for Macro defines for UART smart card interface control register
**********************************************************************/
#define UART_SCICTRL_SCIEN ((uint32_t)(1<<0)) /**< enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_NACKDIS ((uint32_t)(1<<1)) /**< NACK response is inhibited*/
#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2)) /**< ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /**< number of retransmission*/
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /**< Extra guard time*/
/*********************************************************************//**
* Macro defines for Macro defines for UART synchronous control register
**********************************************************************/
#define UART_SYNCCTRL_SYNC ((uint32_t)(1<<0)) /**< enable synchronous mode*/
#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(1<<1)) /**< synchronous master mode*/
#define UART_SYNCCTRL_FES ((uint32_t)(1<<2)) /**< sample on falling edge*/
#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(1<<3)) /**< to be defined*/
#define UART_SYNCCTRL_CSCEN ((uint32_t)(1<<4)) /**< continuous running clock enable (master mode only)*/
#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t)(1<<5)) /**< do not send start/stop bit*/
#define UART_SYNCCTRL_CCCLR ((uint32_t)(1<<6)) /**< stop continuous clock*/
/*********************************************************************//**
* Macro defines for Macro defines for UART Fractional divider register
**********************************************************************/
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
#define UART1_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
#define UART1_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
#define UART0_2_3_TER_TXEN ((uint8_t)(1<<0)) /*!< Transmit enable bit */
#define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /**< UART Transmit Enable Register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS485 Control register
**********************************************************************/
#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
is disabled */
#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
(bit DCTRL = 1), pin DTR is used for direction control */
#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin. The direction control pin
will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Address Match register
**********************************************************************/
#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Delay value register
**********************************************************************/
/* Macro defines for UART1 RS-485 Delay value register */
#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO Level register
**********************************************************************/
#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
void rt_hw_uart_init(void);
#endif
bsp/xplorer4330/drivers/platform.c
-64
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@@ -1,64 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-12-13 lgnq first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "cmsis.h"
#ifdef RT_USING_SERIAL
#include "usart.h"
#endif
/**
* @addtogroup LPC4330
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initialize the LPC4330 Xplorer board.
*/
void rt_hw_board_init(void)
{
Board_Init();
/* Configure the SysTick - Generate interrupt @ 100 Hz*/
SysTick_Config(Chip_Clock_GetRate(CLK_MX_MXCORE) / 100);
#ifdef RT_USING_SERIAL
rt_hw_serial_init();
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#endif
}
/*@}*/
bsp/xplorer4330/drivers/platform.h
-19
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@@ -1,19 +0,0 @@
/*
* File : platform.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#ifndef __PLATFORM_H__
#define __PLATFORM_H__
void rt_hw_board_init(void);
#endif
bsp/xplorer4330/drivers/usart.c
-394
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@@ -1,394 +0,0 @@
/*
* File : usart.c
* mb9bf506r uart driver
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-11-30 lgnq first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "usart.h"
#include "uart_18xx_43xx.h"
#include "scu_18xx_43xx.h"
#if defined(RT_USING_UART0)
/* UART0 device driver structure */
struct serial_ringbuffer uart0_int_rx;
struct uart_device uart0 =
{
LPC_USART0,
USART0_IRQn,
};
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
UART_Int_Status status;
/* enter interrupt */
rt_interrupt_enter();
status = Chip_UART_GetIntStatus(LPC_USART0);
/* error */
if (status == UART_ERROR)
{
return;
}
/* ready for Read Data */
if (status & READY_TO_RECEIVE)
{
rt_hw_serial_isr(&serial0);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(RT_USING_UART1)
/* UART1 device driver structure */
struct serial_ringbuffer uart1_int_rx;
struct uart_device uart1 =
{
LPC_UART1,
USART1_IRQn,
};
struct rt_serial_device serial1;
void UART1_IRQHandler(void)
{
UART_Int_Status status;
/* enter interrupt */
rt_interrupt_enter();
status = Chip_UART_GetIntStatus(LPC_UART1);
/* error */
if (status == UART_ERROR)
{
return;
}
/* ready for Read Data */
if (status & READY_TO_RECEIVE)
{
rt_hw_serial_isr(&serial1);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(RT_USING_UART2)
/* UART2 device driver structure */
struct serial_ringbuffer uart2_int_rx;
struct uart_device uart2 =
{
LPC_USART2,
USART2_IRQn,
};
struct rt_serial_device serial2;
void UART2_IRQHandler(void)
{
UART_Int_Status status;
/* enter interrupt */
rt_interrupt_enter();
status = Chip_UART_GetIntStatus(LPC_USART2);
/* error */
if (status == UART_ERROR)
{
return;
}
/* ready for Read Data */
if (status & READY_TO_RECEIVE)
{
rt_hw_serial_isr(&serial2);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(RT_USING_UART3)
/* UART3 device driver structure */
struct serial_ringbuffer uart3_int_rx;
struct uart_device uart3 =
{
LPC_USART3,
USART3_IRQn,
};
struct rt_serial_device serial3;
void UART3_IRQHandler(void)
{
UART_Int_Status status;
/* enter interrupt */
rt_interrupt_enter();
status = Chip_UART_GetIntStatus(LPC_USART3);
/* error */
if (status == UART_ERROR)
{
return;
}
/* ready for Read Data */
if (status & READY_TO_RECEIVE)
{
rt_hw_serial_isr(&serial3);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
void uart_pin_setup(void)
{
#if defined(RT_USING_UART0)
Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2); /* P6.5 : UART0_TXD */
Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P6.4 : UART0_RXD */
#endif
#if defined(RT_USING_UART1)
Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2); /* P1.13 : UART1_TXD */
Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P1.14 : UART1_RX */
#endif
}
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct uart_device *uart;
UART_DATABIT_Type databit;
UART_STOPBIT_Type stopbit;
UART_PARITY_Type parity;
/* UART FIFO configuration Struct variable */
UART_FIFO_CFG_Type UARTFIFOConfigStruct;
RT_ASSERT(serial != RT_NULL);
uart = (struct uart_device *)serial->parent.user_data;
Chip_UART_Init(uart->uart_regs);
Chip_UART_SetBaud(uart->uart_regs, cfg->baud_rate);
/* set stop bits */
switch (cfg->stop_bits)
{
case STOP_BITS_1:
stopbit = UART_STOPBIT_1;
break;
case STOP_BITS_2:
stopbit = UART_STOPBIT_2;
break;
default:
return RT_ERROR;
}
/* set data bits */
switch (cfg->data_bits)
{
case DATA_BITS_5:
databit = UART_DATABIT_5;
break;
case DATA_BITS_6:
databit = UART_DATABIT_6;
break;
case DATA_BITS_7:
databit = UART_DATABIT_7;
break;
case DATA_BITS_8:
databit = UART_DATABIT_8;
break;
default:
return RT_ERROR;
}
/* set parity */
switch (cfg->parity)
{
case PARITY_NONE:
parity = UART_PARITY_NONE;
break;
case PARITY_EVEN:
parity = UART_PARITY_EVEN;
break;
case PARITY_ODD:
parity = UART_PARITY_ODD;
break;
default:
return RT_ERROR;
}
Chip_UART_ConfigData(uart->uart_regs, databit, parity, stopbit);
/* Enable UART Transmit */
Chip_UART_TxCmd(uart->uart_regs, ENABLE);
Chip_UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
/* Enable DMA mode in UART */
UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE;
/* Initialize FIFO for UART0 peripheral */
Chip_UART_FIFOConfig(uart->uart_regs, &UARTFIFOConfigStruct);
/* Enable UART Rx interrupt */
Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RBR, ENABLE);
/* Enable UART line status interrupt */
Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RLS, ENABLE);
/* Enable Interrupt for UART channel */
/* Priority = 1 */
NVIC_SetPriority(uart->irq_num, 1);
return RT_EOK;
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct uart_device *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_DISABLE_IRQ(uart->irq_num);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_ENABLE_IRQ(uart->irq_num);
break;
}
return (RT_EOK);
}
static int uart_putc(struct rt_serial_device *serial, char c)
{
struct uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct uart_device *)serial->parent.user_data;
/* wait send buffer is empty */
while (!(uart->uart_regs->LSR & UART_LSR_THRE))
;
/* write to send buffer */
uart->uart_regs->THR = c & UART_THR_MASKBIT;
return (1);
}
static int uart_getc(struct rt_serial_device *serial)
{
struct uart_device *uart;
uint8_t ch;
RT_ASSERT(serial != RT_NULL);
uart = (struct uart_device *)serial->parent.user_data;
/* receive buffer is full */
if (uart->uart_regs->LSR & UART_LSR_RDR)
{
ch = uart->uart_regs->RBR & UART_RBR_MASKBIT;
return (ch);
}
else
return (-1);
}
static struct rt_uart_ops uart_ops =
{
uart_configure,
uart_control,
uart_putc,
uart_getc,
};
void rt_hw_serial_init(void)
{
struct serial_configure config;
config.baud_rate = BAUD_RATE_115200;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
uart_pin_setup();
#if defined(RT_USING_UART0)
serial0.ops = &uart_ops;
serial0.int_rx = &uart0_int_rx;
serial0.config = config;
/* register UART0 device */
rt_hw_serial_register(&serial0,
"uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
#endif
#if defined(RT_USING_UART1)
serial1.ops = &uart_ops;
serial1.int_rx = &uart1_int_rx;
serial1.config = config;
/* register UART1 device */
rt_hw_serial_register(&serial1,
"uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart1);
#endif
#if defined(RT_USING_UART2)
serial2.ops = &uart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config = config;
/* register UART2 device */
rt_hw_serial_register(&serial2,
"uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart2);
#endif
#if defined(RT_USING_UART3)
serial3.ops = &uart_ops;
serial3.int_rx = &uart3_int_rx;
serial3.config = config;
/* register UART3 device */
rt_hw_serial_register(&serial3,
"uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart3);
#endif
}
bsp/xplorer4330/drivers/usart.h
-39
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@@ -1,39 +0,0 @@
/*
* File : usart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-05-15 lgnq modified according bernard's implementaion.
*/
#ifndef __USART_H__
#define __USART_H__
#include <rtthread.h>
#include "chip_lpc43xx.h"
#include "cmsis.h"
/**
* Enable/DISABLE Interrupt Controller
*/
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
struct uart_device
{
LPC_USART_Type *uart_regs;
/* irq number */
IRQn_Type irq_num;
};
void rt_hw_serial_init(void);
#endif
bsp/xplorer4330/libraries/SConscript
+3 -2
View File
@@ -1,8 +1,9 @@
# for module compiling
# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
bsp/xplorer4330/libraries/lpc_board/SConscript
-44
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@@ -1,44 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
#src = Glob('board_common/*.c')
src = []
path = [cwd + '/board_common']
if rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_4330':
src += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330']
elif rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_1830':
src += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c',
'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c']
path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330',
cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830']
elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_4357':
src += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357']
elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_1857':
src += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c',
'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c']
path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357',
cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857']
elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_4350':
src += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350']
elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_1850':
src += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c',
'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c']
path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350',
cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850']
group = DefineGroup('lpc_board', src, depend = [''], CPPPATH = path)
Return('group')
bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h
-176
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@@ -1,176 +0,0 @@
/*
* @brief Common board API functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __BOARD_API_H_
#define __BOARD_API_H_
#include "lpc_types.h"
#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup BOARD_COMMON_API BOARD: Common board functions
* @ingroup BOARD_Common
* This file contains common board definitions that are shared across
* boards and devices. All of these functions do not need to be
* impemented for a specific board, but if they are implemented, they
* should use this API standard.
* @{
*/
/**
* @brief Set up and initialize all required blocks and functions related to the board hardware.
* @return None
*/
void Board_Init(void);
/**
* @brief Initializes board UART for output, required for printf redirection
* @return None
*/
void Board_Debug_Init(void);
/**
* @brief Sends a single character on the UART, required for printf redirection
* @param ch : character to send
* @return None
*/
void Board_UARTPutChar(char ch);
/**
* @brief Get a single character from the UART, required for scanf input
* @return EOF if not character was received, or character value
*/
int Board_UARTGetChar(void);
/**
* @brief Prints a string to the UART
* @param str : Terminated string to output
* @return None
*/
void Board_UARTPutSTR(char *str);
/**
* @brief Initializes board LED(s)
* @return None
*/
void Board_LED_Init(void);
/**
* @brief Sets the state of a board LED to on or off
* @param LEDNumber : LED number to set state for
* @param State : true for on, false for off
* @return None
*/
void Board_LED_Set(uint8_t LEDNumber, bool State);
/**
* @brief Returns the current state of a board LED
* @param LEDNumber : LED number to set state for
* @return true if the LED is on, otherwise false
*/
bool Board_LED_Test(uint8_t LEDNumber);
/**
* @brief Toggles the current state of a board LED
* @param LEDNumber : LED number to change state for
* @return None
*/
STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)
{
Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));
}
/**
* @brief Current system clock rate, mainly used for sysTick
*/
extern uint32_t SystemCoreClock;
/**
* @brief Update system core clock rate, should be called if the
* system has a clock rate change
* @return None
*/
void SystemCoreClockUpdate(void);
/**
* @brief Turn on Board LCD Backlight
* @param Intensity : Backlight intensity (0 = off, >=1 = on)
* @return None
* On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
* value will turn off or on the backlight. On some boards, a non-0 value will
* control backlight intensity via a PWN. For PWM systems, the intensity value
* is a percentage value between 0 and 100%.
*/
void Board_LCD_Set_Backlight(uint8_t Intensity);
/**
* @brief Function prototype for a MS delay function. Board layers or example code may
* define this function as needed.
*/
typedef void (*p_msDelay_func_t)(uint32_t);
/* The DEBUG* functions are selected based on system configuration.
Code that uses the DEBUG* functions will have their I/O routed to
the UART, semihosting, or nowhere. */
#if defined(DEBUG)
#if defined(DEBUG_SEMIHOSTING)
#define DEBUGINIT()
#define DEBUGOUT(...) printf(__VA_ARGS__)
#define DEBUGSTR(str) printf(str)
#define DEBUGIN() (int) EOF
#else
#define DEBUGINIT() Board_Debug_Init()
#define DEBUGOUT(...) printf(__VA_ARGS__)
#define DEBUGSTR(str) Board_UARTPutSTR(str)
#define DEBUGIN() Board_UARTGetChar()
#endif /* defined(DEBUG_SEMIHOSTING) */
#else
#define DEBUGINIT()
#define DEBUGOUT(...)
#define DEBUGSTR(str)
#define DEBUGIN() (int) EOF
#endif /* defined(DEBUG) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_API_H_ */
bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h
-90
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@@ -1,90 +0,0 @@
/*
* @brief Common PHY functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_PHY_H_
#define __LPC_PHY_H_
#include "board.h"
#include "chip.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers
* @ingroup BOARD_Common
* The simple PHY function API provides simple non-blocking PHY status
* monitoring and initialization support for various Ethernet PHYs.
* To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires
* several standard functions from the MAC driver for interfacing to the
* PHY via a MII link (Chip_ENET_Start_MII_Write(), Chip_ENET_Is_MII_Busy(),
* Chip_ENET_Start_MII_Read(), and Chip_ENET_Read_MII_Data()).
*
* Once initialized, just preiodically call the lpcPHYStsPoll() function
* from the background loop or a thread and monitor the returned status
* to determine if the PHY state has changed and the current PHY state.
* @{
*/
#define PHY_LINK_ERROR (1 << 0) /*!< PHY status bit for link error */
#define PHY_LINK_BUSY (1 << 1) /*!< PHY status bit for MII link busy */
#define PHY_LINK_CHANGED (1 << 2) /*!< PHY status bit for changed state (not persistent) */
#define PHY_LINK_CONNECTED (1 << 3) /*!< PHY status bit for connected state */
#define PHY_LINK_SPEED100 (1 << 4) /*!< PHY status bit for 100Mbps mode */
#define PHY_LINK_FULLDUPLX (1 << 5) /*!< PHY status bit for full duplex mode */
/**
* @brief Phy status update state machine
* @return An Or'ed value of PHY_LINK_* statuses
* This function can be called at any rate and will poll the the PHY status. Multiple
* calls may be needed to determine PHY status.
*/
uint32_t lpcPHYStsPoll(void);
/**
* @brief Initialize the PHY
* @param rmii : Initializes PHY for RMII mode if true, MII if false
* @param pDelayMsFunc : Delay function (in mS) used for this driver
* @return PHY_LINK_ERROR or 0 on success
* This function initializes the PHY. It will block until complete. It will not
* wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to
* detect cable insertion.
*/
uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_PHY_H_ */
bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c
-281
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@@ -1,281 +0,0 @@
/*
* @brief Mational DP83848 simple PHY driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#include "lpc_phy.h"
/** @defgroup DP83848_PHY BOARD: PHY status and control driver for the DP83848
* @ingroup BOARD_PHY
* Various functions for controlling and monitoring the status of the
* DP83848 PHY.
* @{
*/
/** @brief DP83848 PHY register offsets */
#define DP8_BMCR_REG 0x0 /*!< Basic Mode Control Register */
#define DP8_BMSR_REG 0x1 /*!< Basic Mode Status Reg */
#define DP8_ANADV_REG 0x4 /*!< Auto_Neg Advt Reg */
#define DP8_ANLPA_REG 0x5 /*!< Auto_neg Link Partner Ability Reg */
#define DP8_ANEEXP_REG 0x6 /*!< Auto-neg Expansion Reg */
#define DP8_PHY_STAT_REG 0x10/*!< PHY Status Register */
#define DP8_PHY_INT_CTL_REG 0x11/*!< PHY Interrupt Control Register */
#define DP8_PHY_RBR_REG 0x17/*!< PHY RMII and Bypass Register */
#define DP8_PHY_STS_REG 0x19/*!< PHY Status Register */
/* DP83848 Control register definitions */
#define DP8_RESET (1 << 15) /*!< 1= S/W Reset */
#define DP8_LOOPBACK (1 << 14) /*!< 1=loopback Enabled */
#define DP8_SPEED_SELECT (1 << 13) /*!< 1=Select 100MBps */
#define DP8_AUTONEG (1 << 12) /*!< 1=Enable auto-negotiation */
#define DP8_POWER_DOWN (1 << 11) /*!< 1=Power down PHY */
#define DP8_ISOLATE (1 << 10) /*!< 1=Isolate PHY */
#define DP8_RESTART_AUTONEG (1 << 9) /*!< 1=Restart auto-negoatiation */
#define DP8_DUPLEX_MODE (1 << 8) /*!< 1=Full duplex mode */
#define DP8_COLLISION_TEST (1 << 7) /*!< 1=Perform collsion test */
/* DP83848 Status register definitions */
#define DP8_100BASE_T4 (1 << 15) /*!< T4 mode */
#define DP8_100BASE_TX_FD (1 << 14) /*!< 100MBps full duplex */
#define DP8_100BASE_TX_HD (1 << 13) /*!< 100MBps half duplex */
#define DP8_10BASE_T_FD (1 << 12) /*!< 100Bps full duplex */
#define DP8_10BASE_T_HD (1 << 11) /*!< 10MBps half duplex */
#define DP8_MF_PREAMB_SUPPR (1 << 6) /*!< Preamble suppress */
#define DP8_AUTONEG_COMP (1 << 5) /*!< Auto-negotation complete */
#define DP8_RMT_FAULT (1 << 4) /*!< Fault */
#define DP8_AUTONEG_ABILITY (1 << 3) /*!< Auto-negotation supported */
#define DP8_LINK_STATUS (1 << 2) /*!< 1=Link active */
#define DP8_JABBER_DETECT (1 << 1) /*!< Jabber detect */
#define DP8_EXTEND_CAPAB (1 << 0) /*!< Supports extended capabilities */
/* DP83848 PHY RBR MII dode definitions */
#define DP8_RBR_RMII_MODE (1 << 5) /*!< Use RMII mode */
/* DP83848 PHY status definitions */
#define DP8_REMOTEFAULT (1 << 6) /*!< Remote fault */
#define DP8_FULLDUPLEX (1 << 2) /*!< 1=full duplex */
#define DP8_SPEED10MBPS (1 << 1) /*!< 1=10MBps speed */
#define DP8_VALID_LINK (1 << 0) /*!< 1=Link active */
/* DP83848 PHY ID register definitions */
#define DP8_PHYID1_OUI 0x2000 /*!< Expected PHY ID1 */
#define DP8_PHYID2_OUI 0x5c90 /*!< Expected PHY ID2 */
/* DP83848 PHY update flags */
static uint32_t physts, olddphysts;
/* PHY update counter for state machine */
static int32_t phyustate;
/* Pointer to delay function used for this driver */
static p_msDelay_func_t pDelayMs;
/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
true on success, or false on failure */
static Status lpc_mii_write(uint8_t reg, uint16_t data)
{
Status sts = ERROR;
int32_t mst = 250;
/* Write value for register */
Chip_ENET_Start_MII_Write(reg, data);
/* Wait for unbusy status */
while (mst > 0) {
if (Chip_ENET_Is_MII_Busy()) {
mst--;
pDelayMs(1);
}
else {
mst = 0;
sts = SUCCESS;
}
}
return sts;
}
/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
true on success, or false on failure */
static Status lpc_mii_read(uint8_t reg, uint16_t *data)
{
Status sts = ERROR;
int32_t mst = 250;
/* Start register read */
Chip_ENET_Start_MII_Read(reg);
/* Wait for unbusy status */
while (mst > 0) {
if (!Chip_ENET_Is_MII_Busy()) {
mst = 0;
*data = Chip_ENET_Read_MII_Data();
sts = SUCCESS;
}
else {
mst--;
pDelayMs(1);
}
}
return sts;
}
/* Update PHY status from passed value */
static void lpc_update_phy_sts(uint16_t linksts)
{
/* Update link active status */
if (linksts & DP8_VALID_LINK) {
physts |= PHY_LINK_CONNECTED;
}
else {
physts &= ~PHY_LINK_CONNECTED;
}
/* Full or half duplex */
if (linksts & DP8_FULLDUPLEX) {
physts |= PHY_LINK_FULLDUPLX;
}
else {
physts &= ~PHY_LINK_FULLDUPLX;
}
/* Configure 100MBit/10MBit mode. */
if (linksts & DP8_SPEED10MBPS) {
physts &= ~PHY_LINK_SPEED100;
}
else {
physts |= PHY_LINK_SPEED100;
}
/* If the status has changed, indicate via change flag */
if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
olddphysts = physts;
physts |= PHY_LINK_CHANGED;
}
}
/* Initialize the DP83848 PHY */
uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
{
uint16_t tmp;
int32_t i;
pDelayMs = pDelayMsFunc;
/* Initial states for PHY status and state machine */
olddphysts = physts = phyustate = 0;
/* Only first read and write are checked for failure */
/* Put the DP83848C in reset mode and wait for completion */
if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != SUCCESS) {
return ERROR;
}
i = 400;
while (i > 0) {
pDelayMs(1);
if (lpc_mii_read(DP8_BMCR_REG, &tmp) != SUCCESS) {
return ERROR;
}
if (!(tmp & (DP8_RESET | DP8_POWER_DOWN))) {
i = -1;
}
else {
i--;
}
}
/* Timeout? */
if (i == 0) {
return ERROR;
}
#if 0
/* Setup link based on configuration options */
#if PHY_USE_AUTONEG == 1
tmp = DP8_AUTONEG;
#else
tmp = 0;
#endif
#if PHY_USE_100MBS == 1
tmp |= DP8_SPEED_SELECT;
#endif
#if PHY_USE_FULL_DUPLEX == 1
tmp |= DP8_DUPLEX_MODE;
#endif
#else
tmp = DP8_AUTONEG;
#endif
lpc_mii_write(DP8_BMCR_REG, tmp);
/* Enable RMII mode for PHY */
if (rmii) {
lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
}
/* The link is not set active at this point, but will be detected
later */
return SUCCESS;
}
/* Phy status update state machine */
uint32_t lpcPHYStsPoll(void)
{
switch (phyustate) {
default:
case 0:
/* Read BMSR to clear faults */
Chip_ENET_Start_MII_Read(DP8_PHY_STAT_REG);
physts &= ~PHY_LINK_CHANGED;
physts = physts | PHY_LINK_BUSY;
phyustate = 1;
break;
case 1:
/* Wait for read status state */
if (!Chip_ENET_Is_MII_Busy()) {
/* Update PHY status */
physts &= ~PHY_LINK_BUSY;
lpc_update_phy_sts(Chip_ENET_Read_MII_Data());
phyustate = 0;
}
break;
}
return physts;
}
/**
* @}
*/
bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c
-270
View File
@@ -1,270 +0,0 @@
/*
* @brief SMSC 87x0 simple PHY driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#include "lpc_phy.h"
/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0
* @ingroup BOARD_PHY
* Various functions for controlling and monitoring the status of the
* SMSC 87x0 PHY.
* @{
*/
/* LAN8720 PHY register offsets */
#define LAN8_BCR_REG 0x0 /*!< Basic Control Register */
#define LAN8_BSR_REG 0x1 /*!< Basic Status Reg */
#define LAN8_PHYID1_REG 0x2 /*!< PHY ID 1 Reg */
#define LAN8_PHYID2_REG 0x3 /*!< PHY ID 2 Reg */
#define LAN8_PHYSPLCTL_REG 0x1F/*!< PHY special control/status Reg */
/* LAN8720 BCR register definitions */
#define LAN8_RESET (1 << 15) /*!< 1= S/W Reset */
#define LAN8_LOOPBACK (1 << 14) /*!< 1=loopback Enabled */
#define LAN8_SPEED_SELECT (1 << 13) /*!< 1=Select 100MBps */
#define LAN8_AUTONEG (1 << 12) /*!< 1=Enable auto-negotiation */
#define LAN8_POWER_DOWN (1 << 11) /*!< 1=Power down PHY */
#define LAN8_ISOLATE (1 << 10) /*!< 1=Isolate PHY */
#define LAN8_RESTART_AUTONEG (1 << 9) /*!< 1=Restart auto-negoatiation */
#define LAN8_DUPLEX_MODE (1 << 8) /*!< 1=Full duplex mode */
/* LAN8720 BSR register definitions */
#define LAN8_100BASE_T4 (1 << 15) /*!< T4 mode */
#define LAN8_100BASE_TX_FD (1 << 14) /*!< 100MBps full duplex */
#define LAN8_100BASE_TX_HD (1 << 13) /*!< 100MBps half duplex */
#define LAN8_10BASE_T_FD (1 << 12) /*!< 100Bps full duplex */
#define LAN8_10BASE_T_HD (1 << 11) /*!< 10MBps half duplex */
#define LAN8_AUTONEG_COMP (1 << 5) /*!< Auto-negotation complete */
#define LAN8_RMT_FAULT (1 << 4) /*!< Fault */
#define LAN8_AUTONEG_ABILITY (1 << 3) /*!< Auto-negotation supported */
#define LAN8_LINK_STATUS (1 << 2) /*!< 1=Link active */
#define LAN8_JABBER_DETECT (1 << 1) /*!< Jabber detect */
#define LAN8_EXTEND_CAPAB (1 << 0) /*!< Supports extended capabilities */
/* LAN8720 PHYSPLCTL status definitions */
#define LAN8_SPEEDMASK (7 << 2) /*!< Speed and duplex mask */
#define LAN8_SPEED100F (6 << 2) /*!< 100BT full duplex */
#define LAN8_SPEED10F (5 << 2) /*!< 10BT full duplex */
#define LAN8_SPEED100H (2 << 2) /*!< 100BT half duplex */
#define LAN8_SPEED10H (1 << 2) /*!< 10BT half duplex */
/* LAN8720 PHY ID 1/2 register definitions */
#define LAN8_PHYID1_OUI 0x0007 /*!< Expected PHY ID1 */
#define LAN8_PHYID2_OUI 0xC0F0 /*!< Expected PHY ID2, except last 4 bits */
/* DP83848 PHY update flags */
static uint32_t physts, olddphysts;
/* PHY update counter for state machine */
static int32_t phyustate;
/* Pointer to delay function used for this driver */
static p_msDelay_func_t pDelayMs;
/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
true on success, or false on failure */
static Status lpc_mii_write(uint8_t reg, uint16_t data)
{
Status sts = ERROR;
int32_t mst = 250;
/* Write value for register */
Chip_ENET_Start_MII_Write(reg, data);
/* Wait for unbusy status */
while (mst > 0) {
if (Chip_ENET_Is_MII_Busy()) {
mst--;
pDelayMs(1);
}
else {
mst = 0;
sts = SUCCESS;
}
}
return sts;
}
/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
true on success, or false on failure */
static Status lpc_mii_read(uint8_t reg, uint16_t *data)
{
Status sts = ERROR;
int32_t mst = 250;
/* Start register read */
Chip_ENET_Start_MII_Read(reg);
/* Wait for unbusy status */
while (mst > 0) {
if (!Chip_ENET_Is_MII_Busy()) {
mst = 0;
*data = Chip_ENET_Read_MII_Data();
sts = SUCCESS;
}
else {
mst--;
pDelayMs(1);
}
}
return sts;
}
/* Update PHY status from passed value */
static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts)
{
/* Update link active status */
if (linksts & LAN8_LINK_STATUS) {
physts |= PHY_LINK_CONNECTED;
}
else {
physts &= ~PHY_LINK_CONNECTED;
}
switch (sdsts & LAN8_SPEEDMASK) {
case LAN8_SPEED100F:
default:
physts |= PHY_LINK_SPEED100;
physts |= PHY_LINK_FULLDUPLX;
break;
case LAN8_SPEED10F:
physts &= ~PHY_LINK_SPEED100;
physts |= PHY_LINK_FULLDUPLX;
break;
case LAN8_SPEED100H:
physts |= PHY_LINK_SPEED100;
physts &= ~PHY_LINK_FULLDUPLX;
break;
case LAN8_SPEED10H:
physts &= ~PHY_LINK_SPEED100;
physts &= ~PHY_LINK_FULLDUPLX;
break;
}
/* If the status has changed, indicate via change flag */
if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
olddphysts = physts;
physts |= PHY_LINK_CHANGED;
}
}
/* Initialize the SMSC 87x0 PHY */
uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
{
uint16_t tmp;
int32_t i;
pDelayMs = pDelayMsFunc;
/* Initial states for PHY status and state machine */
olddphysts = physts = phyustate = 0;
/* Only first read and write are checked for failure */
/* Put the DP83848C in reset mode and wait for completion */
if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) {
return ERROR;
}
i = 400;
while (i > 0) {
pDelayMs(1);
if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) {
return ERROR;
}
if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) {
i = -1;
}
else {
i--;
}
}
/* Timeout? */
if (i == 0) {
return ERROR;
}
/* Setup link */
lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG);
/* The link is not set active at this point, but will be detected
later */
return SUCCESS;
}
/* Phy status update state machine */
uint32_t lpcPHYStsPoll(void)
{
static uint16_t sts;
switch (phyustate) {
default:
case 0:
/* Read BMSR to clear faults */
Chip_ENET_Start_MII_Read(LAN8_BSR_REG);
physts &= ~PHY_LINK_CHANGED;
physts = physts | PHY_LINK_BUSY;
phyustate = 1;
break;
case 1:
/* Wait for read status state */
if (!Chip_ENET_Is_MII_Busy()) {
/* Get PHY status with link state */
sts = Chip_ENET_Read_MII_Data();
Chip_ENET_Start_MII_Read(LAN8_PHYSPLCTL_REG);
phyustate = 2;
}
break;
case 2:
/* Wait for read status state */
if (!Chip_ENET_Is_MII_Busy()) {
/* Update PHY status */
physts &= ~PHY_LINK_BUSY;
smsc_update_phy_sts(sts, Chip_ENET_Read_MII_Data());
phyustate = 0;
}
break;
}
return physts;
}
/**
* @}
*/
bsp/xplorer4330/libraries/lpc_board/board_common/retarget.c
-253
View File
@@ -1,253 +0,0 @@
/*
* @brief IO redirection support
*
* This file adds re-direction support to the library for various
* projects. It can be configured in one of 3 ways - no redirection,
* redirection via a UART, or redirection via semihosting. If DEBUG
* is not defined, all printf statements will do nothing with the
* output being throw away. If DEBUG is defined, then the choice of
* output is selected by the DEBUG_SEMIHOSTING define. If the
* DEBUG_SEMIHOSTING is not defined, then output is redirected via
* the UART. If DEBUG_SEMIHOSTING is defined, then output will be
* attempted to be redirected via semihosting. If the UART method
* is used, then the Board_UARTPutChar and Board_UARTGetChar
* functions must be defined to be used by this driver and the UART
* must already be initialized to the correct settings.
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "sys_config.h"
#include "board.h"
/* Keil (Realview) support */
#if defined(__CC_ARM)
#include <stdio.h>
#include <rt_misc.h>
#if defined(DEBUG)
#if defined(DEBUG_SEMIHOSTING)
#define ITM_Port8(n) (*((volatile unsigned char *) (0xE0000000 + 4 * n)))
#define ITM_Port16(n) (*((volatile unsigned short *) (0xE0000000 + 4 * n)))
#define ITM_Port32(n) (*((volatile unsigned long *) (0xE0000000 + 4 * n)))
#define DEMCR (*((volatile unsigned long *) (0xE000EDFC)))
#define TRCENA 0x01000000
/* Write to SWO */
void _ttywrch(int ch)
{
if (DEMCR & TRCENA) {
while (ITM_Port32(0) == 0) {}
ITM_Port8(0) = ch;
}
}
#else
static INLINE void BoardOutChar(char ch)
{
Board_UARTPutChar(ch);
}
#endif /* defined(DEBUG_SEMIHOSTING) */
#endif /* defined(DEBUG) */
struct __FILE {
int handle;
};
FILE __stdout;
FILE __stdin;
FILE __stderr;
void *_sys_open(const char *name, int openmode)
{
return 0;
}
int fputc(int c, FILE *f)
{
#if defined(DEBUG)
#if defined(DEBUG_SEMIHOSTING)
_ttywrch(c);
#else
BoardOutChar((char) c);
#endif
#endif
return 0;
}
int fgetc(FILE *f)
{
#if defined(DEBUG) && !defined(DEBUG_SEMIHOSTING)
return Board_UARTGetChar();
#else
return 0;
#endif
}
int ferror(FILE *f)
{
return EOF;
}
void _sys_exit(int return_code)
{
label: goto label; /* endless loop */
}
#endif /* defined (__CC_ARM) */
/* IAR support */
#if defined(__ICCARM__)
/*******************
*
* Copyright 1998-2003 IAR Systems. All rights reserved.
*
* $Revision: 30870 $
*
* This is a template implementation of the "__write" function used by
* the standard library. Replace it with a system-specific
* implementation.
*
* The "__write" function should output "size" number of bytes from
* "buffer" in some application-specific way. It should return the
* number of characters written, or _LLIO_ERROR on failure.
*
* If "buffer" is zero then __write should perform flushing of
* internal buffers, if any. In this case "handle" can be -1 to
* indicate that all handles should be flushed.
*
* The template implementation below assumes that the application
* provides the function "MyLowLevelPutchar". It should return the
* character written, or -1 on failure.
*
********************/
#include <yfuns.h>
_STD_BEGIN
#pragma module_name = "?__write"
#if defined(DEBUG)
#if defined(DEBUG_SEMIHOSTING)
#error Semihosting support not yet working on IAR
#endif /* defined(DEBUG_SEMIHOSTING) */
#endif /* defined(DEBUG) */
/*
If the __write implementation uses internal buffering, uncomment
the following line to ensure that we are called with "buffer" as 0
(i.e. flush) when the application terminates. */
size_t __write(int handle, const unsigned char *buffer, size_t size)
{
#if defined(DEBUG)
size_t nChars = 0;
if (buffer == 0) {
/*
This means that we should flush internal buffers. Since we
don't we just return. (Remember, "handle" == -1 means that all
handles should be flushed.)
*/
return 0;
}
/* This template only writes to "standard out" and "standard err",
for all other file handles it returns failure. */
if (( handle != _LLIO_STDOUT) && ( handle != _LLIO_STDERR) ) {
return _LLIO_ERROR;
}
for ( /* Empty */; size != 0; --size) {
Board_UARTPutChar(*buffer++);
++nChars;
}
return nChars;
#else
return size;
#endif /* defined(DEBUG) */
}
_STD_END
#endif /* defined (__ICCARM__) */
#if defined( __GNUC__ )
/* Include stdio.h to pull in __REDLIB_INTERFACE_VERSION__ */
#include <stdio.h>
#if (__REDLIB_INTERFACE_VERSION__ >= 20000)
/* We are using new Redlib_v2 semihosting interface */
#define WRITEFUNC __sys_write
#define READFUNC __sys_readc
#else
/* We are using original Redlib semihosting interface */
#define WRITEFUNC __write
#define READFUNC __readc
#endif
#if defined(DEBUG)
#if defined(DEBUG_SEMIHOSTING)
/* Do nothing, semihosting is enabled by default in LPCXpresso */
#endif /* defined(DEBUG_SEMIHOSTING) */
#endif /* defined(DEBUG) */
#if !defined(DEBUG_SEMIHOSTING)
int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength)
{
#if defined(DEBUG)
unsigned int i;
for (i = 0; i < iLength; i++) {
Board_UARTPutChar(pcBuffer[i]);
}
#endif
return iLength;
}
/* Called by bottom level of scanf routine within RedLib C library to read
a character. With the default semihosting stub, this would read the character
from the debugger console window (which acts as stdin). But this version reads
the character from the LPC1768/RDB1768 UART. */
int READFUNC(void)
{
#if defined(DEBUG)
char c = Board_UARTGetChar();
return (int) c;
#else
return (int) -1;
#endif
}
#endif /* !defined(DEBUG_SEMIHOSTING) */
#endif /* defined ( __GNUC__ ) */
bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox
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/*
* @brief LPCOpen 18xx/43xx board support page
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @defgroup BOARDS_18XX_43XX BOARD: LPC18XX and LPC43XX boards
* @ingroup Board_Layer
* @{
*/
/**
* @}
*/
/*!
* @page LPCOPEN_BSP_18XX43XX Supported 18xx/43xx platforms
*
* <b>Device Support</b><br/>
* All LPC18xx and LPC43xx device variants are supported.<br/><br/>
* <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=103">LPC18xx documentation links</a><br/>
* <a href="http://www.lpcware.com/gfiles/docs?tid_1[]=104">LPC43xx documentation links</a><br/><br/>
* <b>Board Support</b><br/>
* Hitex, Keil, and NGX boards for both 18xx and 43xx variants are supported.
* Click <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco">here</a> for LPCOpen build procedures and default jumper configuration for supported boards.<br/><br/>
* <a href="http://www.hitex.com/index.php?id=3455/">Hitex LPC1857 and LPC4357 evaluation boards </a><br/>
* <a href="http://www.keil.com/mcb1800/">Keil MCB1800</a> and <a href="http://www.keil.com/mcb4300/">Keil MCB4300 boards</a><br/>
* <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC1830-Xplorer_Quick_Start_Guide">NGX LPC1830 Xplorer</a> and
* <a href="http://ngxtech.com/knowledgebase/index.php?title=LPC4330-Xplorer_Quick_Start_Guide">NGX LPC4330 Xplorer boards</a><br/>
*
* <b>Toolchain Support</b><br/>
* Code Red Xpresso, IAR EWARM, and Keil MDK are all supported. See the <a href="http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-build-procedures/lpc18xx/43xx-lpco#Supported_toolchains">build support pages</a>
* for information on specific versions of the toolchains tested with the LPCOpen platform.<br/><br/>
* <a href="http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/">IAR EWARM</a><br/>
* <a href="http://www.keil.com/arm/mdk.asp">ARM MDK-ARM</a><br/>
* <a href="http://code-red-tech.com/lpcxpresso">LPCXpresso</a>
*/

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