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add the lpc43xx bsp support.

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nongxiaoming committed 2014-07-13 14:13:39 +08:00
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bsp/lpc43xx/Libraries/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */
bsp/lpc43xx/Libraries/CMSIS/Include/arm_math.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cm0plus.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cm3.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cm4_simd.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cmFunc.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_cmInstr.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_sc000.h
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bsp/lpc43xx/Libraries/CMSIS/Include/core_sc300.h
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/LPC43xx.h
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_enable.h
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/***********************************************************************
* $Id: fpu_enable.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_ENABLE_H
#define __FPU_ENABLE_H
#if defined(__ARMCC_VERSION)
void fpuEnable(void) __attribute__ ((section("BOOTSTRAP_CODE")));
#else
extern void fpuEnable(void);
#endif
#endif /* __FPU_ENABLE_H */
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/fpu_init.h
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/***********************************************************************
* $Id: fpu_init.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_INIT_H
#define __FPU_INIT_H
void fpuInit(void);
#endif /* __FPU_INIT_H */
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Include/system_LPC43xx.h
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/**********************************************************************
* $Id$ system_lpc43xx.h 2011-06-02
*//**
* @file system_lpc43xx.h
* @brief Cortex-M3 Device System Header File for NXP lpc43xx Series.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SYSTEM_lpc43xx_H
#define __SYSTEM_lpc43xx_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_lpc43xx_H */
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx.c
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/cr_startup_lpc43xx_m0sub.c
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/IAR/startup_lpc43xx_m0sub.s
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bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
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bsp/lpc43xx/Libraries/Device/SConscript
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# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Split('''
NXP/LPC43xx/Source/Templates/system_LPC43xx.c
''')
CPPPATH = [cwd + '/NXP/LPC43xx/Include', cwd + '/../CMSIS/Include']
CPPDEFINES = [rtconfig.USE_CORE + ' USE_SPIFI']
# add for startup script
if rtconfig.USE_CORE =='CORE_M4':
if rtconfig.CROSS_TOOL == 'gcc':
src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx.s']
else:
if rtconfig.CROSS_TOOL == 'gcc':
src += ['NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['NXP/LPC43xx/Source/Templates/IAR/startup_LPC43xx_M0.s']
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/lpc43xx/Libraries/SConscript
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# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/lpc43xx/M0/SConscript
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from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(os.path.join(cwd, '..'))
for d in list:
if (d != 'M4' and d != 'M0'):
path = os.path.join(cwd, '..', d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(path, 'SConscript'))
Return('objs')
bsp/lpc43xx/M0/SConstruct
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# do building
DoBuilding(TARGET, objs)
bsp/lpc43xx/M0/rtconfig.h
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bsp/lpc43xx/M0/rtconfig.py
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import os
# core to be use
USE_CORE = 'CORE_M0'
#USE_CORE = 'CORE_M4'
# toolchains options
ARCH='arm'
if USE_CORE == 'CORE_M4':
CPU = 'cortex-m4'
else:
CPU = 'cortex-m0'
CROSS_TOOL='keil'
# get setting from environment.
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'D:/Keil'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
#
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
if USE_CORE == 'CORE_M4':
DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMSTM'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
CFLAGS = ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
if USE_CORE == 'CORE_M4':
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' --fpu=None'
else:
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
if USE_CORE == 'CORE_M4':
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu None'
else:
AFLAGS += ' --cpu Cortex-M0'
LFLAGS = ' --config lpc43xx_flash.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = IAR_PATH + '/arm/bin/'
POST_ACTION = ''
bsp/lpc43xx/M0/template.uvopt
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bsp/lpc43xx/M0/template.uvproj
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bsp/lpc43xx/M4/SConscript
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from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(os.path.join(cwd, '..'))
for d in list:
if (d != 'M4' and d != 'M0'):
path = os.path.join(cwd, '..', d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(path, 'SConscript'))
Return('objs')
bsp/lpc43xx/M4/SConstruct
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# do building
DoBuilding(TARGET, objs)
bsp/lpc43xx/M4/rtconfig.h
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bsp/lpc43xx/M4/rtconfig.py
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import os
# core to be use
#USE_CORE = 'CORE_M0'
USE_CORE = 'CORE_M4'
# toolchains options
ARCH='arm'
if USE_CORE == 'CORE_M4':
CPU = 'cortex-m4'
else:
CPU = 'cortex-m0'
CROSS_TOOL='keil'
# get setting from environment.
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:/Program Files/CodeSourcery/arm-none-eabi/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'D:/Keil'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
#
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
if USE_CORE == 'CORE_M4':
DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T lpc43xx_spifi.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMSTM'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lpc43xx.map --scatter rtthread-lpc43xx_spifi.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
CFLAGS = ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
if USE_CORE == 'CORE_M4':
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' --fpu=None'
else:
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
if USE_CORE == 'CORE_M4':
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu None'
else:
AFLAGS += ' --cpu Cortex-M0'
LFLAGS = ' --config lpc43xx_flash.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = IAR_PATH + '/arm/bin/'
POST_ACTION = ''
bsp/lpc43xx/M4/template.uvopt
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bsp/lpc43xx/M4/template.uvproj
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bsp/lpc43xx/applications/SConscript
+11
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/lpc43xx/applications/application.c
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-07-13 xiaonong port for lpc43xx
*/
#include <rtthread.h>
#include <board.h>
#include <rtdevice.h>
#include "drv_led.h"
#ifdef RT_USING_FINSH
#include <finsh.h>
#include <shell.h>
#endif
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/*the led thread*/
ALIGN(RT_ALIGN_SIZE)
static rt_uint8_t led_stack[ 512 ];
static struct rt_thread led_thread;
static void led_thread_entry(void *parameter)
{
rt_uint8_t led_value = 0;
rt_device_t led_dev;
rt_led_hw_init();
led_dev = rt_device_find("led");
if (led_dev == RT_NULL)
{
rt_kprintf("can not find the led device!\n");
return;
}
while (1)
{
/* led0 on */
led_value = 1;
led_dev->write(led_dev, 0, &led_value, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
/* led0 off */
led_value = 0;
led_dev->write(led_dev, 0, &led_value, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2);
}
}
int rt_application_init(void)
{
rt_thread_t tid;
rt_err_t result;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX / 3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
/* init led thread */
result = rt_thread_init(&led_thread,
"led",
led_thread_entry,
RT_NULL,
(rt_uint8_t *)&led_stack[0],
sizeof(led_stack),
20,
5);
if (result == RT_EOK)
{
rt_thread_startup(&led_thread);
}
return 0;
}
bsp/lpc43xx/applications/startup.c
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/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2014-07-13 xiaonong for LPC43xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
extern int rt_application_init(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
#if LPC_EXT_SDRAM
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize system timer*/
rt_system_timer_init();
/* initialize application */
rt_application_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
bsp/lpc43xx/drivers/SConscript
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_LWIP') == False:
SrcRemove(src, 'drv_emac.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/lpc43xx/drivers/board.c
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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2014-06-20 xiaonong ported to LPC43xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
extern void SystemCoreClockUpdate(void);
/**
* This function will initial LPC43xx board.
*/
void rt_hw_board_init()
{
#ifdef CORE_M4
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
#endif
/* update the core clock */
SystemCoreClockUpdate();
/* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
/* init uart device */
rt_hw_uart_init();
/* setup the console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#if LPC_EXT_SDRAM == 1
lpc_sdram_hw_init();
mpu_init();
#endif
}
bsp/lpc43xx/drivers/board.h
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
* 2010-02-04 Magicoe add board.h to LPC176x bsp
* 2013-12-18 Bernard porting to LPC4088 bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "LPC43xx.h"
#include <rtthread.h>
/* disable SDRAM in default */
#ifndef LPC_EXT_SDRAM
#define LPC_EXT_SDRAM 0
#endif
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
//#define RT_USING_UART2
// </RDTConfigurator>
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (void*)(0x10000000 + 0x8000)
void rt_hw_board_init(void);
int rt_hw_board_heap_init(void);
#endif
bsp/lpc43xx/drivers/drv_emac.c
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bsp/lpc43xx/drivers/drv_emac.h
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bsp/lpc43xx/drivers/drv_led.c
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#include <rtthread.h>
#include "board.h"
#include "drv_led.h"
/**
*
* LED1 <==> GPIO4[12]
* LED2 <==> GPIO4[13]
*
**/
#define LED_NUM 8
#define LED1_PIN 12
#define LED1_PORT 4
#define LED2_PIN 13
#define LED2_PORT 4
struct led_ctrl
{
uint8_t num;
uint8_t port;
};
struct lpc_led
{
/* inherit from rt_device */
struct rt_device parent;
struct led_ctrl ctrl[LED_NUM];
};
static struct lpc_led led;
static rt_err_t rt_led_init(rt_device_t dev)
{
/* Enable clock and init GPIO outputs */
LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
/* set GPIO4[12] GPIO4[13] as GPIO. */
LPC_SCU->SFSP9_0 = 0; /* GPIO4[12] */
LPC_SCU->SFSP9_1 = 0; /* GPIO4[13] */
/* set GPIO4[12] GPIO4[13] output. */
LPC_GPIO_PORT->DIR[LED1_PORT] |= 0x01 << LED1_PIN;
LPC_GPIO_PORT->DIR[LED2_PORT] |= 0x01 << LED2_PIN;
/* turn off all the led */
LPC_GPIO_PORT->CLR[LED1_PORT] |= 0x01 << LED1_PIN;
LPC_GPIO_PORT->CLR[LED2_PORT] |= 0x01 << LED2_PIN;
led.ctrl[0].num = LED1_PIN;
led.ctrl[0].port = LED1_PORT;
led.ctrl[1].num = LED2_PIN;
led.ctrl[1].port = LED2_PORT;
return RT_EOK;
}
static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_led_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
rt_size_t size)
{
rt_ubase_t index = 0;
rt_ubase_t nr = size;
rt_uint8_t *value = buffer;
RT_ASSERT(dev == &led.parent);
RT_ASSERT((pos + size) <= LED_NUM);
for (index = 0; index < nr; index++)
{
if ((LPC_GPIO_PORT->PIN[led.ctrl[pos + index].port] & (1 << led.ctrl[pos + index].num)) != 0)
{
*value = 0;
}
else
{
*value = 1;
}
value++;
}
return index;
}
static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
const void *buffer, rt_size_t size)
{
rt_ubase_t index = 0;
rt_ubase_t nw = size;
const rt_uint8_t *value = buffer;
RT_ASSERT(dev == &led.parent);
RT_ASSERT((pos + size) <= LED_NUM);
for (index = 0; index < nw; index++)
{
if (*value++)
{
LPC_GPIO_PORT->CLR[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
}
else
{
LPC_GPIO_PORT->SET[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num);
}
}
return index;
}
static rt_err_t rt_led_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
RT_ASSERT(dev == &led.parent);
if (cmd == LED_DEVICE_CTRL)
{
rt_uint32_t *led_num = args;
*led_num = LED_NUM;
}
return RT_EOK;
}
int rt_led_hw_init(void)
{
led.parent.type = RT_Device_Class_Char;
led.parent.rx_indicate = RT_NULL;
led.parent.tx_complete = RT_NULL;
led.parent.init = rt_led_init;
led.parent.open = rt_led_open;
led.parent.close = rt_led_close;
led.parent.read = rt_led_read;
led.parent.write = rt_led_write;
led.parent.control = rt_led_control;
led.parent.user_data = RT_NULL;
/* register a character device */
rt_device_register(&led.parent, "led", RT_DEVICE_FLAG_RDWR);
/* init led device */
rt_led_init(&led.parent);
return 0;
}
INIT_DEVICE_EXPORT(rt_led_hw_init);
#ifdef RT_USING_FINSH
#include <finsh.h>
void led_test(rt_uint32_t led_num, rt_uint32_t value)
{
rt_uint8_t led_value = value;
rt_led_write(&led.parent, led_num, &led_value, 1);
}
FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 100).)
#endif
bsp/lpc43xx/drivers/drv_led.h
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#ifndef __DRV_LED_H
#define __DRV_LED_H
/* Clock Control Unit register bits */
#define CCU_CLK_CFG_RUN (1 << 0)
#define CCU_CLK_CFG_AUTO (1 << 1)
#define CCU_CLK_STAT_RUN (1 << 0)
#define LED_DEVICE_CTRL 0x81 /*LED control command*/
int rt_led_hw_init(void);
#endif
bsp/lpc43xx/drivers/drv_uart.c
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bsp/lpc43xx/drivers/drv_uart.h
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