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Merge branch 'master' into master

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This commit is contained in:
supperthomas
2020-05-02 09:43:50 +08:00
committed by GitHub
parent 1ea7a3f519 664bc4e9d8
commit 4f87edbd35
158 changed files with 21480 additions and 2976 deletions
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1
.travis.yml
View File

@@ -107,6 +107,7 @@ env:
- RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32h747-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'

2
README.md
View File

@@ -86,7 +86,7 @@ RT-Thread supports many architectures, and has covered the major architectures i
- **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
- **ARM11**：manufacturers like Fullhan
- **MIPS32**：manufacturers like loongson、Ingenic
- **RISC-V**：manufacturers like Hifive、Kendryte
- **RISC-V**：manufacturers like Hifive、Kendryte、[Nuclei](https://nucleisys.com/)
- **ARC**：manufacturers like SYNOPSYS
- **DSP**：manufacturers like TI
- **C-Sky**

2
README_zh.md
View File

@@ -89,7 +89,7 @@ RT-Thread RTOS 支持许多架构，并且已经涵盖了当前应用中的主
- MIPS32：如芯片制造商loongson、Ingenic
- RISC-V：如芯片制造商Hifive、Kendryte
- RISC-V：如芯片制造商Hifive、Kendryte、[芯来Nuclei](https://nucleisys.com/)
- ARC：如芯片制造商SYNOPSYS

3
bsp/at32/at32f403a-start/Kconfig
View File

@@ -17,6 +17,5 @@ config PKGS_DIR
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "../Libraries/Kconfig"
source "board/Kconfig"

13
bsp/at32/at32f403a-start/rtconfig.py
View File

@@ -1,4 +1,5 @@
import os
import sys
# toolchains options
ARCH='arm'
@@ -57,7 +58,7 @@ if PLATFORM == 'gcc':
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
@@ -88,7 +89,7 @@ elif PLATFORM == 'armcc':
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
@@ -136,8 +137,14 @@ elif PLATFORM == 'iar':
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)

19
bsp/at32/tools/sdk_dist.py Normal file
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@@ -0,0 +1,19 @@
import os
import sys
import shutil
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
# BSP dist function
def dist_do_building(BSP_ROOT):
from mkdist import bsp_copy_files
import rtconfig
dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT))
library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries')
library_dir = os.path.join(dist_dir, 'Libraries')
print("=> copy bsp drivers")
bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers'))
print("=> copy bsp library")
bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))

41
bsp/k210/driver/Kconfig
View File

@@ -2,17 +2,44 @@ config BSP_USING_UART_HS
bool "Enable High Speed UART"
default y
config BSP_USING_UART1
bool "Enable UART1 (GPIO0/1)"
default n
menu "General Purpose UARTs"
config BSP_USING_UART2
bool "Enable UART2 (GPIO0/1)"
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_TXD_PIN
int "uart1 TXD pin number"
default 20
config BSP_UART1_RXD_PIN
int "uart1 RXD pin number"
default 21
endif
config BSP_USING_UART3
bool "Enable UART3 (GPIO0/1)"
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_TXD_PIN
int "uart2 TXD pin number"
default 28
config BSP_UART2_RXD_PIN
int "uart2 RXD pin number"
default 27
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_TXD_PIN
int "uart3 TXD pin number"
default 22
config BSP_UART3_RXD_PIN
int "uart3 RXD pin number"
default 23
endif
endmenu
config BSP_USING_I2C1
bool "Enable I2C1 (GPIO0/1)"

22
bsp/k210/driver/drv_io_config.c
View File

@@ -63,6 +63,18 @@ static struct io_config
#endif
#endif
#ifdef BSP_USING_UART1
IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX),
IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX),
#endif
#ifdef BSP_USING_UART2
IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),
IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),
#endif
#ifdef BSP_USING_UART3
IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX),
IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX),
#endif
};
static int print_io_config()
@@ -89,7 +101,15 @@ int io_config_init(void)
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
#ifdef BSP_USING_UART2
// for IO-27/28
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
#endif
#if defined(BSP_USING_UART1) || defined(BSP_USING_UART3)
// for IO-20~23
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
#endif
for(i = 0; i < count; i++)
{
fpioa_set_function(io_config[i].io_num, io_config[i].func);

302
bsp/k210/driver/drv_uart.c
View File

@@ -17,10 +17,12 @@
#include <stdio.h>
#include <sysctl.h>
// #include "uart.h"
#include "uart.h"
#include "uarths.h"
#include "plic.h"
#define UART_DEFAULT_BAUDRATE 115200
static volatile uarths_t *const _uarths = (volatile uarths_t *)UARTHS_BASE_ADDR;
struct device_uart
@@ -29,22 +31,71 @@ struct device_uart
rt_uint32_t irqno;
};
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
static rt_err_t rt_uarths_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
static rt_err_t uarths_control(struct rt_serial_device *serial, int cmd, void *arg);
static int drv_uarths_putc(struct rt_serial_device *serial, char c);
static int drv_uarths_getc(struct rt_serial_device *serial);
static void uarths_irq_handler(int irqno, void *param);
static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg);
static int drv_uart_putc(struct rt_serial_device *serial, char c);
static int drv_uart_getc(struct rt_serial_device *serial);
static void uart_irq_handler(int irqno, void *param);
const struct rt_uart_ops _uart_hs_ops =
{
rt_uarths_configure,
uarths_control,
drv_uarths_putc,
drv_uarths_getc,
RT_NULL
};
const struct rt_uart_ops _uart_ops =
{
uart_configure,
rt_uart_configure,
uart_control,
drv_uart_putc,
drv_uart_getc,
//TODO: add DMA support
RT_NULL
};
/* START ported from kendryte standalone sdk uart.c */
#define __UART_BRATE_CONST 16
volatile uart_t* const _uart[3] =
{
(volatile uart_t*)UART1_BASE_ADDR,
(volatile uart_t*)UART2_BASE_ADDR,
(volatile uart_t*)UART3_BASE_ADDR
};
void uart_init(uart_device_number_t channel)
{
sysctl_clock_enable(SYSCTL_CLOCK_UART1 + channel);
sysctl_reset(SYSCTL_RESET_UART1 + channel);
}
/* END ported from kendryte standalone sdk uart.c */
static inline uart_device_number_t _get_uart_channel(rt_uint32_t addr)
{
switch (addr)
{
case UART1_BASE_ADDR:
return UART_DEVICE_1;
case UART2_BASE_ADDR:
return UART_DEVICE_2;
case UART3_BASE_ADDR:
return UART_DEVICE_3;
default:
return UART_DEVICE_MAX;
}
}
/*
* UART Initiation
*/
@@ -62,7 +113,7 @@ int rt_hw_uart_init(void)
serial = &serial_hs;
uart = &uart_hs;
serial->ops = &_uart_ops;
serial->ops = &_uart_hs_ops;
serial->config = config;
serial->config.baud_rate = 115200;
@@ -86,36 +137,79 @@ int rt_hw_uart_init(void)
serial->ops = &_uart_ops;
serial->config = config;
serial->config.baud_rate = 115200;
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
uart->hw_base = UART1_BASE_ADDR;
uart->irqno = IRQN_UART1_INTERRUPT;
uart_init(UART_DEVICE_1);
rt_hw_serial_register(serial,
"uarths",
"uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
}
#endif
#ifdef BSP_USING_UART2
{
static struct rt_serial_device serial2;
static struct device_uart uart2;
serial = &serial2;
uart = &uart2;
serial->ops = &_uart_ops;
serial->config = config;
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
uart->hw_base = UART2_BASE_ADDR;
uart->irqno = IRQN_UART2_INTERRUPT;
uart_init(UART_DEVICE_2);
rt_hw_serial_register(serial,
"uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
}
#endif
#ifdef BSP_USING_UART3
{
static struct rt_serial_device serial3;
static struct device_uart uart3;
serial = &serial3;
uart = &uart3;
serial->ops = &_uart_ops;
serial->config = config;
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
uart->hw_base = UART3_BASE_ADDR;
uart->irqno = IRQN_UART3_INTERRUPT;
uart_init(UART_DEVICE_3);
rt_hw_serial_register(serial,
"uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
}
#endif
return 0;
}
/*
* UART interface
* UARTHS interface
*/
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
static rt_err_t rt_uarths_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
rt_uint32_t baud_div;
struct device_uart *uart;
uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
uint16_t div = freq / cfg->baud_rate - 1;
uint32_t freq_hs = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
uint16_t div_hs = freq_hs / cfg->baud_rate - 1;
RT_ASSERT(serial != RT_NULL);
serial->config = *cfg;
@@ -125,7 +219,7 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
if (uart->hw_base == UARTHS_BASE_ADDR)
{
_uarths->div.div = div;
_uarths->div.div = div_hs;
_uarths->txctrl.txen = 1;
_uarths->rxctrl.rxen = 1;
_uarths->txctrl.txcnt = 0;
@@ -137,13 +231,14 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
}
else
{
return (-1);
/* other uart */
}
return (RT_EOK);
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
static rt_err_t uarths_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct device_uart *uart;
@@ -160,7 +255,7 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
case RT_DEVICE_CTRL_SET_INT:
/* install interrupt */
rt_hw_interrupt_install(uart->irqno, uart_irq_handler,
rt_hw_interrupt_install(uart->irqno, uarths_irq_handler,
serial, serial->parent.parent.name);
rt_hw_interrupt_umask(uart->irqno);
break;
@@ -169,38 +264,168 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
return (RT_EOK);
}
static int drv_uart_putc(struct rt_serial_device *serial, char c)
static int drv_uarths_putc(struct rt_serial_device *serial, char c)
{
struct device_uart *uart = serial->parent.user_data;
RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR);
while (_uarths->txdata.full);
_uarths->txdata.data = (uint8_t)c;
return (1);
}
static int drv_uarths_getc(struct rt_serial_device *serial)
{
struct device_uart *uart = serial->parent.user_data;
RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR);
uarths_rxdata_t recv = _uarths->rxdata;
if (recv.empty)
return EOF;
else
return (recv.data & 0xff);
/* Receive Data Available */
return (-1);
}
/* UARTHS ISR */
static void uarths_irq_handler(int irqno, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device *)param;
struct device_uart *uart = serial->parent.user_data;
RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR);
/* read interrupt status and clear it */
if (_uarths->ip.rxwm)
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/*
* UART interface
*/
static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct device_uart *uart;
uart_bitwidth_t data_width = (uart_bitwidth_t)cfg->data_bits ;
uart_stopbit_t stopbit = (uart_stopbit_t)cfg->stop_bits;
uart_parity_t parity = (uart_parity_t)cfg->parity;
uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
uint32_t divisor = freq / (uint32_t)cfg->baud_rate;
uint8_t dlh = divisor >> 12;
uint8_t dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
uint8_t dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
RT_ASSERT(serial != RT_NULL);
serial->config = *cfg;
uart = serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
uart_device_number_t channel = _get_uart_channel(uart->hw_base);
RT_ASSERT(channel != UART_DEVICE_MAX);
RT_ASSERT(data_width >= 5 && data_width <= 8);
if (data_width == 5)
{
RT_ASSERT(stopbit != UART_STOP_2);
}
else
{
RT_ASSERT(stopbit != UART_STOP_1_5);
}
uint32_t stopbit_val = stopbit == UART_STOP_1 ? 0 : 1;
uint32_t parity_val;
switch (parity)
{
case UART_PARITY_NONE:
parity_val = 0;
break;
case UART_PARITY_ODD:
parity_val = 1;
break;
case UART_PARITY_EVEN:
parity_val = 3;
break;
default:
RT_ASSERT(!"Invalid parity");
break;
}
_uart[channel]->LCR |= 1u << 7;
_uart[channel]->DLH = dlh;
_uart[channel]->DLL = dll;
_uart[channel]->DLF = dlf;
_uart[channel]->LCR = 0;
_uart[channel]->LCR = (data_width - 5) |
(stopbit_val << 2) |
(parity_val << 3);
_uart[channel]->LCR &= ~(1u << 7);
_uart[channel]->IER |= 0x80; /* THRE */
_uart[channel]->FCR = UART_RECEIVE_FIFO_1 << 6 |
UART_SEND_FIFO_8 << 4 |
0x1 << 3 |
0x1;
return (RT_EOK);
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct device_uart *uart;
uart = serial->parent.user_data;
if (uart->hw_base == UARTHS_BASE_ADDR)
uart_device_number_t channel = _get_uart_channel(uart->hw_base);
RT_ASSERT(uart != RT_NULL);
RT_ASSERT(channel != UART_DEVICE_MAX);
switch (cmd)
{
while (_uarths->txdata.full);
_uarths->txdata.data = (uint8_t)c;
}
else
{
/* other uart */
case RT_DEVICE_CTRL_CLR_INT:
/* Disable the UART Interrupt */
rt_hw_interrupt_mask(uart->irqno);
_uart[channel]->IER &= ~0x1;
break;
case RT_DEVICE_CTRL_SET_INT:
/* install interrupt */
rt_hw_interrupt_install(uart->irqno, uart_irq_handler,
serial, serial->parent.parent.name);
rt_hw_interrupt_umask(uart->irqno);
_uart[channel]->IER |= 0x1;
break;
}
return (RT_EOK);
}
static int drv_uart_putc(struct rt_serial_device *serial, char c)
{
struct device_uart *uart = serial->parent.user_data;
uart_device_number_t channel = _get_uart_channel(uart->hw_base);
RT_ASSERT(channel != UART_DEVICE_MAX);
while (_uart[channel]->LSR & (1u << 5));
_uart[channel]->THR = c;
return (1);
}
static int drv_uart_getc(struct rt_serial_device *serial)
{
int ret = -1;
struct device_uart *uart = serial->parent.user_data;
uart_device_number_t channel = _get_uart_channel(uart->hw_base);
RT_ASSERT(channel != UART_DEVICE_MAX);
if (uart->hw_base == UARTHS_BASE_ADDR)
{
uarths_rxdata_t recv = _uarths->rxdata;
if (recv.empty)
return EOF;
else
return (recv.data & 0xff);
}
if (_uart[channel]->LSR & 1)
return (char)(_uart[channel]->RBR & 0xff);
else
return EOF;
/* Receive Data Available */
return (-1);
@@ -209,21 +434,20 @@ static int drv_uart_getc(struct rt_serial_device *serial)
/* UART ISR */
static void uart_irq_handler(int irqno, void *param)
{
rt_ubase_t isr;
struct rt_serial_device *serial = (struct rt_serial_device *)param;
struct device_uart *uart = serial->parent.user_data;
uart_device_number_t channel = _get_uart_channel(uart->hw_base);
RT_ASSERT(channel != UART_DEVICE_MAX);
/* read interrupt status and clear it */
if (uart->hw_base == UARTHS_BASE_ADDR)
{
if (_uarths->ip.rxwm)
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
if (_uart[channel]->LSR)
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/* WEAK for SDK 0.5.6 */
RT_WEAK void uart_debug_init(int uart_channel)
RT_WEAK void uart_debug_init(uart_device_number_t uart_channel)
{
}

8
bsp/lpc54608-LPCXpresso/project.ewp
View File

@@ -2148,16 +2148,16 @@
<group>
<name>CPlusPlus</name>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/Mutex.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_Mutex.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/Semaphore.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_Semaphore.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/Thread.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_Thread.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/crt.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_crt.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/crt_init.c</name>

8
bsp/lpc54608-LPCXpresso/project.ewt
View File

@@ -2355,19 +2355,19 @@
<group>
<name>CPlusPlus</name>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\crt.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_crt.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\crt_init.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\Mutex.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Mutex.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\Semaphore.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Semaphore.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\Thread.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Thread.cpp</name>
</file>
</group>
<group>

1743
bsp/lpc54608-LPCXpresso/project.uvprojx
View File

File diff suppressed because it is too large Load Diff

8
bsp/mini2440/.config
View File

@@ -161,7 +161,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=512
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=1024
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set

23
bsp/mini2440/Kconfig
View File

@@ -16,12 +16,33 @@ config PKGS_DIR
default "packages"
config BOARD_MINI2440
bool "mini2440"
bool
select ARCH_ARM_ARM9
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
choice
prompt "Lcd for mini2440"
default RT_MINI2440_LCD_T35
depends on PKG_USING_GUIENGINE
config RT_MINI2440_LCD_A70
bool "A70"
config RT_MINI2440_LCD_T43
bool "T43"
config RT_MINI2440_LCD_N35
bool "N35"
config RT_MINI2440_LCD_T35
bool "T35"
config RT_MINI2440_LCD_X35
bool "X35"
endchoice
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"

15
bsp/mini2440/applications/main.c
View File

@@ -5,10 +5,25 @@
#include "led.h"
#ifdef PKG_USING_GUIENGINE
#include <rtgui/driver.h>
#endif
int main(void)
{
rt_device_t device;
printf("hello rt-thread\n");
#ifdef PKG_USING_GUIENGINE
device = rt_device_find("lcd");
if (device)
{
rtgui_graphic_set_device(device);
}
#endif
while (1)
{
/* light on leds for one second */

33
bsp/mini2440/applications/mnt.c
View File

@@ -6,16 +6,29 @@
int mnt_init(void)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
{
rt_kprintf("File System initialzation failed!\n");
}
return RT_EOK;
rt_uint32_t tryCnt = 5;
rt_device_t dev;
while(tryCnt--)
{
dev = rt_device_find("sd0");
if(dev != RT_NULL)
{
break;
}
rt_thread_mdelay(500);
}
if(dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
{
rt_kprintf("File System initialzation failed!\n");
}
return RT_EOK;
}
INIT_ENV_EXPORT(mnt_init);
#endif

32
bsp/mini2440/drivers/SConscript
View File

@@ -8,30 +8,30 @@ cwd = os.path.join(str(Dir('#')), 'drivers')
src = Split("""
board.c
led.c
key.c
uart.c
""")
if GetDepend('RT_USING_DFS'):
src += ['sdcard.c']
if GetDepend('RT_USING_LWIP'):
src += ['dm9000.c']
if GetDepend('PKG_USING_GUIENGINE'):
src += ['touch.c', 'key.c']
if GetDepend('RT_MINI2440_LCD_A70'):
src += ['lcd_a70.c']
if GetDepend('RT_MINI2440_LCD_T43'):
src += ['lcd_t43.c']
if GetDepend('RT_MINI2440_LCD_N35'):
src += ['lcd_n35.c']
if GetDepend('RT_MINI2440_LCD_T35'):
src += ['lcd_t35.c']
if GetDepend('RT_MINI2440_LCD_X35'):
src += ['lcd_x35.c']
if GetDepend('RT_USING_RTI'):
src += ['rti_stub.c']
if GetDepend('PKG_USING_GUIENGINE'):
if rtconfig.RT_USING_LCD_TYPE == 'PNL_A70':
src += ['lcd_a70.c']
elif rtconfig.RT_USING_LCD_TYPE == 'PNL_N35':
src += ['lcd_n35.c']
elif rtconfig.RT_USING_LCD_TYPE == 'PNL_T35':
src += ['lcd_t35.c']
elif rtconfig.RT_USING_LCD_TYPE == 'PNL_X35':
src += ['lcd_x35.c']
src += ['touch.c']
if GetDepend('RT_USING_SDIO'):
src += ['s3cmci.c']
CPPPATH = [cwd]

21
bsp/mini2440/drivers/lcd.h
View File

@@ -1,21 +0,0 @@
/*
* File : lcd.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-03-29 Yi.Qiu
*/
#ifndef __LCD_H__
#define __LCD_H__
#include <rtthread.h>
void rt_hw_lcd_init(void);
#endif

247
bsp/mini2440/drivers/lcd_a70.c
View File

@@ -15,7 +15,6 @@
#include <rtthread.h>
#include <s3c24x0.h>
#include "lcd.h"
/* LCD driver for A7' */
#define LCD_WIDTH 800
@@ -35,81 +34,81 @@
#define SCR_XSIZE LCD_WIDTH
#define SCR_YSIZE LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDINT_FRSYNC (1<<1)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDINT_FRSYNC (1<<1)
static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
//static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -128,121 +127,123 @@ static void lcd_power_enable(int invpwren, int pwren)
static void lcd_envid_on_off(int onoff)
{
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
}
//********************** BOARD LCD backlight ****************************
static void LcdBkLtSet(rt_uint32_t HiRatio)
{
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1ÉèÖÃΪoutput
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ;
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
if( HiRatio > 100 ) HiRatio = 100 ;
if( HiRatio > 100 ) HiRatio = 100 ;
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
}
/* RT-Thread Device Interface */
static rt_err_t rt_lcd_init (rt_device_t dev)
{
GPB1_TO_OUT();
GPB1_TO_1();
{
GPB1_TO_OUT();
GPB1_TO_1();
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
#define M5D(n) ((n)&0x1fffff)
#define M5D(n) ((n)&0x1fffff)
#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
#if !defined(LCD_CON5)
#define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0))
#endif
LCDCON5 = LCD_CON5;
LCDCON5 = LCD_CON5;
LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0);
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0);
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
return RT_EOK;
}
void rt_hw_lcd_init(void)
int rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL) return; /* no memory yet */
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return -RT_ERROR; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
INIT_BOARD_EXPORT(rt_hw_lcd_init);

239
bsp/mini2440/drivers/lcd_n35.c
View File

@@ -15,7 +15,6 @@
#include <rtthread.h>
#include <s3c24x0.h>
#include "lcd.h"
/* LCD driver for N3'5 */
#define LCD_WIDTH 240
@@ -35,82 +34,82 @@
#define SCR_XSIZE LCD_WIDTH
#define SCR_YSIZE LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDINT_FRSYNC (1<<1)
#define S3C2410_LCDINT_FRSYNC (1<<1)
static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
//static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -129,61 +128,61 @@ static void lcd_power_enable(int invpwren, int pwren)
static void lcd_envid_on_off(int onoff)
{
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
}
//********************** BOARD LCD backlight ****************************
static void LcdBkLtSet(rt_uint32_t HiRatio)
{
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1ÉèÖÃΪoutput
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ;
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
if( HiRatio > 100 ) HiRatio = 100 ;
if( HiRatio > 100 ) HiRatio = 100 ;
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
}
/* RT-Thread Device Interface */
static rt_err_t rt_lcd_init (rt_device_t dev)
{
GPB1_TO_OUT();
GPB1_TO_1();
{
GPB1_TO_OUT();
GPB1_TO_1();
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
#define M5D(n) ((n)&0x1fffff)
#define M5D(n) ((n)&0x1fffff)
#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
#if !defined(LCD_CON5)
#define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0))
#endif
@@ -193,57 +192,59 @@ static rt_err_t rt_lcd_init (rt_device_t dev)
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
return RT_EOK;
}
void rt_hw_lcd_init(void)
int rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL) return; /* no memory yet */
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return -RT_ERROR; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
INIT_BOARD_EXPORT(rt_hw_lcd_init);

247
bsp/mini2440/drivers/lcd_t35.c
View File

@@ -15,7 +15,6 @@
#include <rtthread.h>
#include <s3c24x0.h>
#include "lcd.h"
/* LCD driver for T3'5 */
#define LCD_WIDTH 240
@@ -35,82 +34,82 @@
#define SCR_XSIZE LCD_WIDTH
#define SCR_YSIZE LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDINT_FRSYNC (1<<1)
#define S3C2410_LCDINT_FRSYNC (1<<1)
volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
//volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -129,122 +128,124 @@ static void lcd_power_enable(int invpwren, int pwren)
static void lcd_envid_on_off(int onoff)
{
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
}
//********************** BOARD LCD backlight ****************************
static void LcdBkLtSet(rt_uint32_t HiRatio)
{
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1ÉèÖÃΪoutput
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ;
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
if( HiRatio > 100 ) HiRatio = 100 ;
if( HiRatio > 100 ) HiRatio = 100 ;
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
}
/* RT-Thread Device Interface */
static rt_err_t rt_lcd_init (rt_device_t dev)
{
GPB1_TO_OUT();
GPB1_TO_1();
{
GPB1_TO_OUT();
GPB1_TO_1();
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
#define M5D(n) ((n)&0x1fffff)
#define M5D(n) ((n)&0x1fffff)
#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
#if !defined(LCD_CON5)
#define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0))
#endif
LCDCON5 = LCD_CON5;
LCDCON5 = LCD_CON5;
LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0);
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0);
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
return RT_EOK;
}
void rt_hw_lcd_init(void)
int rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL) return; /* no memory yet */
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return -RT_ERROR; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
INIT_BOARD_EXPORT(rt_hw_lcd_init);

244
bsp/mini2440/drivers/lcd_t43.c Normal file
View File

@@ -0,0 +1,244 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-12 Jonne first version from 4.3 inch lcd(480x272)
*/
#include <rtthread.h>
#include <s3c24x0.h>
/* LCD driver for N3'5 */
#define LCD_WIDTH 480
#define LCD_HEIGHT 272
#define LCD_PIXCLOCK 4
#define LCD_RIGHT_MARGIN 2
#define LCD_LEFT_MARGIN 2
#define LCD_HSYNC_LEN 41
#define LCD_UPPER_MARGIN 2
#define LCD_LOWER_MARGIN 2
#define LCD_VSYNC_LEN 10
#define LCD_XSIZE LCD_WIDTH
#define LCD_YSIZE LCD_HEIGHT
#define SCR_XSIZE LCD_WIDTH
#define SCR_YSIZE LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDINT_FRSYNC (1<<1)
static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
//static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
static struct rt_device_graphic_info _lcd_info;
static void lcd_power_enable(int invpwren, int pwren)
{
//GPG4 is setted as LCD_PWREN
GPGUP = GPGUP | (1<<4); // Pull-up disable
GPGCON = GPGCON | (3<<8); //GPG4=LCD_PWREN
//Enable LCD POWER ENABLE Function
LCDCON5 = LCDCON5&(~(1<<3))|(pwren<<3); // PWREN
LCDCON5 = LCDCON5&(~(1<<5))|(invpwren<<5); // INVPWREN
}
static void lcd_envid_on_off(int onoff)
{
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
}
//********************** BOARD LCD backlight ****************************
static void LcdBkLtSet(rt_uint32_t HiRatio)
{
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ;
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
if( HiRatio > 100 ) HiRatio = 100 ;
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
}
/* RT-Thread Device Interface */
static rt_err_t rt_lcd_init (rt_device_t dev)
{
GPB1_TO_OUT();
GPB1_TO_1();
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
#define M5D(n) ((n)&0x1fffff)
#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = ((LCD_UPPER_MARGIN - 1) << 24) | ((LCD_HEIGHT - 1) << 14) | ((LCD_LOWER_MARGIN - 1) << 6) | ((LCD_VSYNC_LEN - 1) << 0);
LCDCON3 = ((LCD_RIGHT_MARGIN - 1) << 19) | ((LCD_WIDTH - 1) << 8) | ((LCD_LEFT_MARGIN - 1) << 0);
LCDCON4 = (13 << 8) | ((LCD_HSYNC_LEN - 1) << 0);
#if !defined(LCD_CON5)
#define LCD_CON5 ((1<<11) | (0<<10) | (1<<9) | (1<<8) | (1<<0))
#endif
LCDCON5 = LCD_CON5;
LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0);
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
}
int rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return -RT_ERROR; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
INIT_BOARD_EXPORT(rt_hw_lcd_init);

239
bsp/mini2440/drivers/lcd_x35.c
View File

@@ -17,7 +17,6 @@
#include <rtthread.h>
#include <s3c24x0.h>
#include "lcd.h"
/* LCD driver for X3'5 */
#define LCD_WIDTH 240 // xres
@@ -37,82 +36,82 @@
#define SCR_XSIZE LCD_WIDTH
#define SCR_YSIZE LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define RT_HW_LCD_WIDTH LCD_WIDTH
#define RT_HW_LCD_HEIGHT LCD_HEIGHT
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define MVAL (13)
#define MVAL_USED (0) //0=each frame 1=rate by MVAL
#define INVVDEN (1) //0=normal 1=inverted
#define BSWP (0) //Byte swap control
#define HWSWP (1) //Half word swap control
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
#define GPB1_TO_1() (GPBDAT |= 0x0002)
#define GPB1_TO_0() (GPBDAT &= 0xfffd)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
#define S3C2410_LCDINT_FRSYNC (1<<1)
#define S3C2410_LCDINT_FRSYNC (1<<1)
static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
//static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -131,61 +130,61 @@ static void lcd_power_enable(int invpwren, int pwren)
static void lcd_envid_on_off(int onoff)
{
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
if(onoff==1)
/*ENVID=ON*/
LCDCON1|=1;
else
/*ENVID Off*/
LCDCON1 =LCDCON1 & 0x3fffe;
}
//********************** BOARD LCD backlight ****************************
static void LcdBkLtSet(rt_uint32_t HiRatio)
{
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1ÉèÖÃΪoutput
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
#define FREQ_PWM1 1000
if(!HiRatio)
{
GPBCON = GPBCON & (~(3<<2)) | (1<<2) ;
GPBDAT &= ~(1<<1);
return;
}
GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
if( HiRatio > 100 ) HiRatio = 100 ;
if( HiRatio > 100 ) HiRatio = 100 ;
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0
TCFG0 |= 15; //prescaler = 15+1
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16
TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
}
/* RT-Thread Device Interface */
static rt_err_t rt_lcd_init (rt_device_t dev)
{
GPB1_TO_OUT();
GPB1_TO_1();
{
GPB1_TO_OUT();
GPB1_TO_1();
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPCUP = 0x00000000;
GPCCON = 0xaaaa02a9;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
GPDUP = 0x00000000;
GPDCON = 0xaaaaaaaa;
#define M5D(n) ((n)&0x1fffff)
#define M5D(n) ((n)&0x1fffff)
#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1);
LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0);
LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0);
#define LCD_CON5 (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_INVVDEN | S3C2410_LCDCON5_INVVFRAME | \
S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2410_LCDCON5_HWSWP)
@@ -199,57 +198,59 @@ S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2
LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
LCDSADDR3 = LCD_WIDTH;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LCDINTMSK |= (3);
LPCSEL &= (~7) ;
TPAL=0;
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
LcdBkLtSet(70) ;
lcd_power_enable(0, 1);
lcd_envid_on_off(1);
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
return RT_EOK;
}
void rt_hw_lcd_init(void)
int rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL) return; /* no memory yet */
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return -RT_ERROR; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = LCD_WIDTH;
_lcd_info.height = LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
/* init device structure */
lcd->type = RT_Device_Class_Unknown;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
INIT_BOARD_EXPORT(rt_hw_lcd_init);

327
bsp/mini2440/drivers/s3cmci.c Normal file
View File

@@ -0,0 +1,327 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-15 Jonne first version for s3c2440 mmc controller
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <drivers/mmcsd_core.h>
#include <s3c24x0.h>
#define S3C_PCLK 50000000
static void s3c_mmc_set_clk(struct rt_mmcsd_host *host, rt_uint32_t clock)
{
rt_uint32_t prescale;
rt_uint32_t realClk;
for(prescale = 0; prescale < 256; ++prescale)
{
realClk = S3C_PCLK / (1 + prescale);
if(realClk <= clock)
{
break;
}
}
SDIPRE = prescale;
host->io_cfg.clock = realClk;
}
static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
{
rt_uint32_t ccon;
rt_uint32_t cmdSta;
SDICARG = cmd->arg;
ccon = cmd->cmd_code & 0x3f;
ccon |= (0 << 7) | (1 << 6); /* two start bits*/
ccon |= (1 << 8);/* command start*/
if(cmd->flags & 0xF)
{
// Need response
ccon |= (1 << 9);
}
if((cmd->flags & 0xF) == RESP_R2)
{
// R2 need 136bit response
ccon |= (1 << 10);
}
SDICCON = ccon; /* start cmd */
if(cmd->flags & 0xF)
{
cmdSta = SDICSTA;
while((cmdSta & 0x200) != 0x200 && (cmdSta & 0x400) != 0x400)
{
cmdSta = SDICSTA;
}
if((cmdSta & 0x1000) == 0x1000 && (cmd->flags & 0xF) != RESP_R3 && (cmd->flags & 0xF) != RESP_R4)
{
// crc error, but R3 R4 ignore it
SDICSTA = cmdSta;
return -RT_ERROR;
}
if((cmdSta & 0xF00) != 0xa00)
{
SDICSTA = cmdSta;
return -RT_ERROR;
}
cmd->resp[0] = SDIRSP0;
if((cmd->flags & 0xF) == RESP_R2)
{
cmd->resp[1] = SDIRSP1;
cmd->resp[2] = SDIRSP2;
cmd->resp[3] = SDIRSP3;
}
}
else
{
cmdSta = SDICSTA;
while((cmdSta & 0x800) != 0x800)
{
cmdSta = SDICSTA;
}
}
SDICSTA = cmdSta; // clear current status
return RT_EOK;
}
static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data)
{
rt_uint32_t status;
rt_uint32_t xfer_size;
rt_uint32_t handled_size = 0;
rt_uint32_t *pBuf = RT_NULL;
if(data == RT_NULL)
{
return -RT_ERROR;
}
xfer_size = data->blks * data->blksize;
pBuf = data->buf;
if(data->flags & DATA_DIR_READ)
{
while(handled_size < xfer_size)
{
if ((SDIDSTA & 0x20) == 0x20)
{
SDIDSTA = (0x1 << 0x5);
break;
}
status = SDIFSTA;
if ((status & 0x1000) == 0x1000)
{
*pBuf++ = SDIDAT;
handled_size += 4;
}
}
}
else
{
while(handled_size < xfer_size)
{
status = SDIFSTA;
if ((status & 0x2000) == 0x2000)
{
SDIDAT = *pBuf++;
handled_size += 4;
}
}
}
// wait for end
status = SDIDSTA;
while((status & 0x30) == 0)
{
status = SDIDSTA;
}
SDIDSTA = status;
if ((status & 0xfc) != 0x10)
{
return -RT_ERROR;
}
SDIDCON = SDIDCON & ~(7<<12);
SDIFSTA = SDIFSTA & 0x200;
SDIDSTA = 0x10;
return RT_EOK;
}
static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
rt_uint32_t ret;
struct rt_mmcsd_cmd *cmd;
struct rt_mmcsd_data *data;
rt_uint32_t val;
rt_uint32_t tryCnt = 0;
if(req->cmd == RT_NULL)
{
goto out;
}
cmd = req->cmd;
/* prepare for data transfer*/
if(req->data != RT_NULL)
{
SDIFSTA = SDIFSTA | (1<<16); // reset fifo
while(SDIDSTA & 0x03)
{
if(tryCnt++ > 500)
{
break;
SDIDSTA = SDIDSTA;
}
}
data = req->data;
if((data->blksize & 0x3) != 0)
{
goto out;
}
val = (2 << 22) //word transfer
| (1 << 20) // transmet after response
| (1 << 19) // reciveve after command sent
| (1 << 17) // block data transfer
| (1 << 14); // data start
if(host->io_cfg.bus_width == MMCSD_BUS_WIDTH_4)
{
val |= (1 << 16); // wide bus mode(4bit data)
}
if(data->flags & DATA_DIR_READ)
{
// for data read
val |= (2 << 12);
}
else
{
val |= (3 << 12);
}
val |= (data->blks & 0xFFF);
SDIDCON = val;
SDIBSIZE = data->blksize;
SDIDTIMER = 0x7fffff;
}
ret = s3c_mmc_send_cmd(host,req->cmd);
if(ret != RT_EOK) {
cmd->err = ret;
goto out;
}
if(req->data != RT_NULL)
{
/*do transfer data*/
ret = s3c_mmc_xfer_data(data);
if(ret != RT_EOK)
{
data->err = ret;
goto out;
}
}
out:
mmcsd_req_complete(host);
}
static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
switch (io_cfg->power_mode) {
case MMCSD_POWER_ON:
case MMCSD_POWER_UP:
/* Enable PCLK into SDI Block */
CLKCON |= 1 << 9;
/* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */
GPEUP = GPEUP & (~(0x3f << 5)) | (0x01 << 5);
GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10);
break;
case MMCSD_POWER_OFF:
default:
break;
}
s3c_mmc_set_clk(host, io_cfg->clock);
SDICON = 1;
}
static rt_int32_t mmc_get_card_status(struct rt_mmcsd_host *host)
{
return RT_EOK;
}
static void mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
{
}
static const struct rt_mmcsd_host_ops ops =
{
mmc_request,
mmc_set_iocfg,
mmc_get_card_status,
mmc_enable_sdio_irq
};
int s3c_sdio_init(void)
{
struct rt_mmcsd_host * host = RT_NULL;
host = mmcsd_alloc_host();
if (!host)
{
goto err;
}
host->ops = &ops;
host->freq_min = 300000;
host->freq_max = 50000000;
host->valid_ocr = VDD_32_33 | VDD_33_34;
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
host->max_seg_size = 2048;
host->max_dma_segs = 10;
host->max_blk_size = 512;
host->max_blk_count = 4096;
mmcsd_change(host);
return RT_EOK;
err:
if(host) rt_free(host);
return -RT_EIO;
}
INIT_DEVICE_EXPORT(s3c_sdio_init);

651
bsp/mini2440/drivers/sdcard.c
View File

File diff suppressed because it is too large Load Diff

11
bsp/mini2440/drivers/sdcard.h
View File

@@ -1,11 +0,0 @@
#ifndef __SDCARD_H
#define __SDCARD_H
#include <s3c24x0.h>
#define INICLK 300000
#define SDCLK 24000000 //PCLK=49.392MHz
#define MMCCLK 15000000 //PCLK=49.392MHz
#endif

725
bsp/mini2440/drivers/touch.c
View File

File diff suppressed because it is too large Load Diff

18
bsp/mini2440/drivers/touch.h
View File

@@ -3,30 +3,30 @@
#include <rtthread.h>
#define RT_TOUCH_NORMAL 0
#define RT_TOUCH_CALIBRATION_DATA 1
#define RT_TOUCH_CALIBRATION 2
#define RT_TOUCH_NORMAL 0
#define RT_TOUCH_CALIBRATION_DATA 1
#define RT_TOUCH_CALIBRATION 2
#define RT_TOUCH_EVENTPOST 3
#define RT_TOUCH_EVENTPOST_PARAM 4
struct calibration_data
{
rt_uint16_t min_x, max_x;
rt_uint16_t min_y, max_y;
rt_uint16_t min_x, max_x;
rt_uint16_t min_y, max_y;
};
struct rt_touch_event
{
rt_uint16_t x;
rt_uint16_t y;
int pressed;
rt_uint16_t x;
rt_uint16_t y;
int pressed;
};
typedef void (*rt_touch_calibration_func_t)(rt_uint16_t x, rt_uint16_t y);
typedef void (*rt_touch_eventpost_func_t)(void *, struct rt_touch_event *);
void rtgui_touch_hw_init(void);
int rtgui_touch_hw_init(void);
#endif

6
bsp/mini2440/rtconfig.h
View File

@@ -107,6 +107,12 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 512
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 1024
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */

4
bsp/mini2440/rtconfig.py
View File

@@ -1,9 +1,5 @@
import os
# panel options
# 'PNL_A70','PNL_N35', 'PNL_T35' , 'PNL_X35'
RT_USING_LCD_TYPE = 'PNL_T35'
# toolchains options
ARCH = 'arm'
CPU = 's3c24x0'

129
bsp/nrf5x/libraries/drivers/drv_uart.c
View File

@@ -1,59 +1,83 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-28 xckhmf Modify for <nrfx>
*
*/
#include <rtdevice.h>
#include <nrfx_uart.h>
#include "drv_uart.h"
static struct rt_serial_device _serial0_0;
static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context);
#ifdef BSP_USING_UART
typedef struct
{
struct rt_serial_device *serial;
nrfx_uart_t uart;
uint8_t rx_byte;
uint16_t rx_length;
uint32_t rx_pin;
uint32_t tx_pin;
nrfx_uart_event_handler_t event_handler;
} UART_CFG_T;
} drv_uart_cfg_t;
UART_CFG_T uart0 = {
#ifdef BSP_USING_UART0
static struct rt_serial_device _serial_0;
static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context);
drv_uart_cfg_t m_uart0_cfg = {
.uart = NRFX_UART_INSTANCE(0),
#ifdef RT_USING_CONSOLE
.rx_pin = 8,
.tx_pin = 6,
.event_handler = uart_event_hander,
#else
.rx_pin = 19,
.tx_pin = 20
#endif
.rx_byte = 0,
.rx_length = 0,
.rx_pin = BSP_UART0_RX_PIN,
.tx_pin = BSP_UART0_TX_PIN,
.event_handler = uart0_event_hander
};
UART_CFG_T *working_cfg = RT_NULL;
#endif /* BSP_USING_UART0 */
static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
{
#ifdef BSP_USING_UART1
#error <nrfx_uart> not support UART1. Use UART0 instead.
#endif /* BSP_USING_UART1 */
#ifdef BSP_USING_UART0
static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
{
if (p_event->type == NRFX_UART_EVT_RX_DONE)
{
rt_hw_serial_isr(working_cfg->serial, RT_SERIAL_EVENT_RX_IND);
if(p_event->data.rxtx.bytes == 1)
{
m_uart0_cfg.rx_length = p_event->data.rxtx.bytes;
/* rx_byte equal p_data */
//m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data);
rt_hw_serial_isr(m_uart0_cfg.serial, RT_SERIAL_EVENT_RX_IND);
}
nrfx_uart_rx(&(m_uart0_cfg.uart),&m_uart0_cfg.rx_byte,1);
}
if (p_event->type == NRFX_UART_EVT_TX_DONE)
{
/* @TODO:[RT_DEVICE_FLAG_INT_TX]*/
}
}
#endif /* BSP_USING_UART0 */
static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
{
nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(uart0.tx_pin,uart0.rx_pin);
UART_CFG_T *instance = &uart0;
nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(BSP_UART0_TX_PIN,BSP_UART0_RX_PIN);
drv_uart_cfg_t *instance = RT_NULL;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
if (serial->parent.user_data != RT_NULL)
if (serial->parent.user_data == RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
return -RT_ERROR;
}
instance = (drv_uart_cfg_t*)serial->parent.user_data;
nrfx_uart_uninit(&(instance->uart));
switch (cfg->baud_rate)
@@ -83,28 +107,23 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED;
config.pselrxd = instance->rx_pin;
config.pseltxd = instance->tx_pin;
nrfx_uart_init(&(instance->uart), &config, instance->event_handler);
nrf_uart_int_enable(instance->uart.p_reg, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_RXTO | NRF_UART_INT_MASK_ERROR);
nrfx_uart_rx(&(instance->uart),&(instance->rx_byte),1);
nrf_uart_int_disable(instance->uart.p_reg, NRF_UART_INT_MASK_TXDRDY);
nrfx_uart_rx_enable(&(instance->uart));
working_cfg = instance;
return RT_EOK;
}
static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
{
UART_CFG_T *instance = working_cfg;
drv_uart_cfg_t *instance = NULL;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
if (serial->parent.user_data == RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
return -RT_ERROR;
}
instance = (drv_uart_cfg_t*)serial->parent.user_data;
switch (cmd)
{
@@ -129,10 +148,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
break;
case RT_DEVICE_CTRL_PIN:
if (working_cfg != instance)
{
_uart_cfg(instance->serial, &(instance->serial->config));
}
_uart_cfg(instance->serial, &(instance->serial->config));
break;
case RT_DEVICE_POWERSAVE:
@@ -152,13 +168,13 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
static int _uart_putc(struct rt_serial_device *serial, char c)
{
UART_CFG_T *instance = working_cfg;
drv_uart_cfg_t *instance = NULL;
int rtn = 1;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
instance = (drv_uart_cfg_t*)serial->parent.user_data;
}
nrf_uart_event_clear(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY);
@@ -171,23 +187,21 @@ static int _uart_putc(struct rt_serial_device *serial, char c)
return rtn;
}
/*
@note: this function is invaild ,the cause of the problem is [nrfx_uart.c - line 340]
*/
static int _uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
UART_CFG_T *instance = working_cfg;
drv_uart_cfg_t *instance = NULL;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
instance = (drv_uart_cfg_t*)serial->parent.user_data;
}
if(instance->rx_length)
{
ch = instance->rx_byte;
instance->rx_length--;
}
ch = (int)(nrf_uart_rxd_get(instance->uart.p_reg));
return ch;
}
@@ -202,11 +216,14 @@ void rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
config.bufsz = RT_SERIAL_RB_BUFSZ;
_serial0_0.config = config;
_serial0_0.ops = &_uart_ops;
uart0.serial = &_serial0_0;
#ifdef BSP_USING_UART0
_serial_0.config = config;
_serial_0.ops = &_uart_ops;
m_uart0_cfg.serial = &_serial_0;
rt_hw_serial_register(&_serial_0, "uart0", \
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &m_uart0_cfg);
#endif /* BSP_USING_UART0 */
rt_hw_serial_register(&_serial0_0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart0);
}
#endif /* BSP_USING_UART */

3
bsp/nrf5x/nrf52840/rtconfig.h
View File

@@ -155,10 +155,13 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_JLINK_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_PIN 8
#define BSP_UART0_TX_PIN 6
#endif

26
bsp/nuclei/.gitignore vendored Normal file
View File

@@ -0,0 +1,26 @@
*.i
*.o
*.d
*.elf
*.diss
*.map
*.bin
*.log
.vscode
*.dump
*.verilog
*.swp
*.swo
prebuilt_tools/
setup_config.sh
setup_config.bat
tags
TAGS
TAG
CTAGS
Makefile.local
Makefile.global

453
bsp/nuclei/gd32vf103_rvstar/.config Normal file
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@@ -0,0 +1,453 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=396
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV32=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
CONFIG_PKG_USING_NUCLEI_SDK=y
CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk"
# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set
CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y
CONFIG_PKG_NUCLEI_SDK_VER="latest"
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_GD32VF103V=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_UART_CONSOLE=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART0 is not set
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
CONFIG_BSP_USING_UART4=y
#
# Board extended module Drivers
#
CONFIG_SOC_GD32VF103=y

28
bsp/nuclei/gd32vf103_rvstar/Kconfig Normal file
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@@ -0,0 +1,28 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"
config SOC_GD32VF103
bool
select ARCH_RISCV32
select PKG_USING_NUCLEI_SDK
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y

209
bsp/nuclei/gd32vf103_rvstar/README.md Normal file
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@@ -0,0 +1,209 @@
# 芯来科技RVSTAR开发板 #
## 简介
**RVSTAR开发板** 是由芯来科技公司推出的基于采用芯来科技RISC-V架构处理器芯片的GD32VF103的开发板。
更多关于 **RVSTAR开发板** 开发板的详细资料请参见 [RVSTAR开发板快速入门](https://www.rvmcu.com/quickstart-quickstart-index-u-RV_STAR.html)
### 板载资源
| 硬件 | 描述 |
| --- | --- |
| 内核 | Nuclei N205 |
| 架构 | 32-bit RV32IMAC |
| 主频 | 108 MHz |
## 工具安装
### 安装工具链
请根据[安装Nuclei RISC-V GCC Toolchain和OpenOCD](https://doc.nucleisys.com/nuclei_sdk/quickstart.html#setup-tools-and-environment) 来安装依赖的工具。
### 添加环境变量
将Nuclei RISC-V GCC Toolchain和OpenOCD的环境变量进行设置。
#### Windows
假设工具安装在 **D:\Software\Nuclei**目录下, 则可以修改系统环境变量**PATH**,
将**D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;**增加到**PATH**中。
或者在ENV工具命令行中运行
~~~cmd
set PATH=D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;%PATH%
~~~
#### Linux
假设工具安装在 **~/Software/Nuclei**目录下, 通过在Linux的``.bashrc``增加如下一行代码
来添加环境变量。
~~~bash
export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
~~~
或者在ENV工具命令行中运行
~~~bash
export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
~~~
**注意**: 对应的RISC-V GCC和OPENOCD的路径请替换成自己安装的路径。
## 烧写及执行
### [驱动设置](https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html#on-board-debugger-driver)
### 编译程序
下载好[RT-Thread](https://github.com/RT-Thread/rt-thread)的代码和[ENV工具](https://www.rt-thread.org/document/site/tutorial/env-video/)以后。
按照ENV工具的教程, 在**rt-thread\bsp\nuclei\gd32vf103_rvstar**目录打开ENV工具命令行。
**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
2. **可选**: 运行 ``menuconfig``来进行内核配置
3. 运行 ``scons -c``清理之前的编译结果
4. 运行 ``scons``来进行代码的编译
### 下载程序
在保证程序能够正常编译后, 在相同ENV终端执行``scons --run upload``进行代码的下载。
正常下载的输出如下:
~~~
scons: Reading SConscript files ...
Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
Upload application rtthread.elf using openocd and gdb
riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240" -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg" --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" -ex "monitor resume" -ex "monitor shutdown" -ex "quit"
D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:251
251 if (idle_hook_list[i] != RT_NULL)
cleared protection for sectors 0 through 127 on flash bank 0
Loading section .init, size 0x264 lma 0x8000000
Loading section .text, size 0x140de lma 0x8000280
Loading section .rodata, size 0x37c0 lma 0x8014360
Loading section .data, size 0x404 lma 0x8017b20
Start address 0x800015c, load size 98054
Transfer rate: 8 KB/sec, 10894 bytes/write.
shutdown command invoked
A debugging session is active.
Inferior 1 [Remote target] will be detached.
Quit anyway? (y or n) [answered Y; input not from terminal]
Remote communication error. Target disconnected.: Success.
~~~
下载程序之后, 连接串口(115200-N-8-1), 可以看到 RT-Thread 的输出信息：
```
initialize rti_board_start:0 done
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Apr 9 2020
2006 - 2020 Copyright by rt-thread team
do components initialization.
initialize rti_board_end:0 done
initialize dfs_init:0 done
initialize libc_system_init:0 done
initialize finsh_system_init:0 done
msh />
```
在串口终端(我这里使用的是TeraTerm)输入``ps``即可查看当前线程工作情况:
~~~
msh />ps
thread pri status sp stack size max used left tick error
-------- --- ------- ---------- ---------- ------ ---------- ---
thread01 19 suspend 0x00000158 0x0000018c 87% 0x00000005 000
thread00 19 suspend 0x00000158 0x0000018c 87% 0x00000005 000
tshell 20 running 0x00000258 0x00001000 18% 0x00000004 000
tidle0 31 ready 0x000000a8 0x0000018c 59% 0x0000000e 000
timer 4 suspend 0x000000f8 0x00000200 49% 0x00000009 000
main 10 suspend 0x00000168 0x00000800 36% 0x00000006 000
msh />
~~~
### 调试程序
在保证程序编译成功后, 在相同ENV终端执行``scons --run debug``进行代码在命令行下进行GDB调试。
正常的调试输出如下：
~~~
scons: Reading SConscript files ...
Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
Debug application rtthread.elf using openocd and gdb
riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240" -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"
D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
GNU gdb (GDB) 8.3.0.20190516-git
Copyright (C) 2019 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=i686-w64-mingw32 --target=riscv-nuclei-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from rtthread.elf...
Remote debugging using | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:249
249 for (i = 0; i < RT_IDLE_HOOK_LIST_SIZE; i++)
(gdb)
(gdb) b main.c:35
Breakpoint 1 at 0x8000290: file applications\main.c, line 35.
(gdb) c
Continuing.
Note: automatically using hardware breakpoints for read-only addresses.
Breakpoint 1, thread_entry (parameter=0x0) at applications\main.c:35
35 rt_thread_mdelay(500);
(gdb)
~~~
调试例子参见如下文档:
* https://doc.nucleisys.com/nuclei_sdk/quickstart.html#debug-application
为了更方便的进行调试, 也可以下载**Nuclei Studio**集成开发环境, 创建一个Debug Configuration, 选择编译好的
ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nuclei\gd32vf103_rvstar\packages\nuclei_sdk-latest\SoC\gd32vf103\Board\gd32vf103v_rvstar\openocd_gd32vf103.cfg**
## 驱动支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | RV-STAR板载串口是UART4 |
**注:**
- 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。
- 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。
## 联系人信息
维护人：
- [fanghuaqi](https://github.com/fanghuaqi)

17
bsp/nuclei/gd32vf103_rvstar/SConscript Normal file
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@@ -0,0 +1,17 @@
# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
ASFLAGS = ' -I' + cwd
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

85
bsp/nuclei/gd32vf103_rvstar/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
AddOption('--run',
dest = 'run',
type='string',
nargs=1,
action = 'store',
default = "",
help = 'Upload or debug application using openocd')
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
GDB = rtconfig.GDB
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
bsp_library_type = rtconfig.NUCLEI_SDK_SOC
rtconfig.BSP_LIBRARY_TYPE = bsp_library_type
openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/')
# include hal drivers
hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript')
if os.path.isfile(hal_sconscript):
objs.extend(SConscript(hal_sconscript))
# make a building
DoBuilding(TARGET, objs)
# Run upload or debug if --run=upload or --upload=debug
run_target = GetOption('run')
SUPPORT_RUN_TARGETS = ["upload", "debug"]
if run_target in SUPPORT_RUN_TARGETS:
if os.path.isfile(TARGET):
if run_target == "upload":
upload_cmd = '{} {} -ex "set remotetimeout 240" \
-ex "target remote | openocd --pipe -f {}" \
--batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" \
-ex "monitor resume" -ex "monitor shutdown" -ex "quit"'.format(GDB, TARGET, openocd_cfg)
print("Upload application {} using openocd and gdb".format(TARGET))
print(upload_cmd)
os.system(upload_cmd)
elif run_target == "debug":
debug_cmd = '{} {} -ex "set remotetimeout 240" \
-ex "target remote | openocd --pipe -f {}"'.format(GDB, TARGET, openocd_cfg)
print("Debug application {} using openocd and gdb".format(TARGET))
print(debug_cmd)
os.system(debug_cmd)
else:
print(TARGET + ' not exist, please run scons first!!')
exit(0)

11
bsp/nuclei/gd32vf103_rvstar/applications/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, ]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

19
bsp/nuclei/gd32vf103_rvstar/applications/main.c Normal file
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@@ -0,0 +1,19 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-15 hqfang first version
*/
#include <rtthread.h>
#include <rtdevice.h>
int main(int argc, char *argv[])
{
return RT_EOK;
}
/******************** end of file *******************/

47
bsp/nuclei/gd32vf103_rvstar/board/Kconfig Normal file
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@@ -0,0 +1,47 @@
menu "Hardware Drivers Config"
config SOC_GD32VF103V
bool
select SOC_SERIES_GD32VF103V
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_UART_CONSOLE
bool "Enable UART CONSOLE"
select BSP_USING_UART
select BSP_USING_UART4
default y
endmenu
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default n
config BSP_USING_UART1
bool "Enable UART1"
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_USING_UART4
bool "Enable UART4"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

11
bsp/nuclei/gd32vf103_rvstar/board/SConscript Normal file
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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

67
bsp/nuclei/gd32vf103_rvstar/board/board.c Normal file
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@@ -0,0 +1,67 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-02 hqfang first version
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "cpuport.h"
#ifdef RT_USING_SERIAL
#include <drv_usart.h>
#endif
/** _end symbol defined in linker script of Nuclei SDK */
extern void *_end;
/** _heap_end symbol defined in linker script of Nuclei SDK */
extern void *_heap_end;
#define HEAP_BEGIN &_end
#define HEAP_END &_heap_end
/*
* - Implemented and defined in Nuclei SDK system_<Device>.c file
* - Required macro NUCLEI_BANNER set to 0
*/
extern void _init(void);
/**
* @brief Setup hardware board for rt-thread
*
*/
void rt_hw_board_init(void)
{
/* OS Tick Configuration */
rt_hw_ticksetup();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
#endif
_init(); // __libc_init_array is not used in RT-Thread
/* USART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif
/* Set the shell console output device */
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
/******************** end of file *******************/

21
bsp/nuclei/gd32vf103_rvstar/board/board.h Normal file
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@@ -0,0 +1,21 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-02 hqfang first version
*
*/
#ifndef __BOARD__
#define __BOARD__
#include "nuclei_sdk_hal.h"
void rt_hw_board_init(void);
#endif /* __BOARD__ */
/******************** end of file *******************/

181
bsp/nuclei/gd32vf103_rvstar/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 396
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart4"
#define RT_VER_NUM 0x40003
#define ARCH_RISCV
#define ARCH_RISCV32
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_POSIX
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
#define PKG_USING_NUCLEI_SDK
#define PKG_USING_NUCLEI_SDK_LATEST_VERSION
/* miscellaneous packages */
/* samples: kernel and components samples */
/* Hardware Drivers Config */
#define SOC_GD32VF103V
/* Onboard Peripheral Drivers */
#define BSP_USING_UART_CONSOLE
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART4
/* Board extended module Drivers */
#define SOC_GD32VF103
#endif

58
bsp/nuclei/gd32vf103_rvstar/rtconfig.py Normal file
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@@ -0,0 +1,58 @@
import os
# toolchains options
ARCH='risc-v'
CPU='nuclei'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'D:/Software/Nuclei/gcc/bin'
else:
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
# if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
# Fixed configurations below
NUCLEI_SDK_SOC = "gd32vf103"
NUCLEI_SDK_BOARD = "gd32vf103v_rvstar"
NUCLEI_SDK_DOWNLOAD = "flashxip"
NUCLEI_SDK_CORE = "n205"
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'riscv-nuclei-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
GDB = PREFIX + 'gdb'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
CFLAGS = ' -ffunction-sections -fdata-sections -fno-common '
AFLAGS = CFLAGS
LFLAGS = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections '
LFLAGS += ' -Wl,-cref,-Map=rtthread.map'
LFLAGS += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek '
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -O2 -Os'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

21
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript Normal file
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@@ -0,0 +1,21 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_usart.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

26
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h Normal file
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@@ -0,0 +1,26 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-08 hqfang first version
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__
#include <board.h>
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

520
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c Normal file
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51
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h Normal file
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@@ -0,0 +1,51 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 balanceTWK first version
* 2020-04-15 hqfang Modify for gd32vf103
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include <drv_config.h>
#define __GD32_PORT(port) GPIO##port
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN)
#define __GD32_PIN(index, gpio, gpio_index) \
{ \
index, GPIO##gpio, GPIO_PIN_##gpio_index \
}
#define __GD32_PIN_RESERVE \
{ \
-1, 0, 0 \
}
/* GD32 GPIO driver */
struct pin_index
{
int index;
uint32_t gpio;
uint32_t pin;
};
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
};
int rt_hw_pin_init(void);
#endif /* __DRV_GPIO_H__ */

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