From 36eb783fc7b28cea1f00a7876af253eb49c7f57a Mon Sep 17 00:00:00 2001 From: xupenghu_huaweipc Date: Fri, 10 Apr 2020 09:36:53 +0800 Subject: [PATCH 01/27] add bsp/stm32/stm32l010-st-nucleo --- bsp/stm32/README.md | 2 + bsp/stm32/stm32l010-st-nucleo/.config | 364 +++ bsp/stm32/stm32l010-st-nucleo/.gitignore | 42 + bsp/stm32/stm32l010-st-nucleo/Kconfig | 21 + bsp/stm32/stm32l010-st-nucleo/README.md | 120 + bsp/stm32/stm32l010-st-nucleo/SConscript | 15 + bsp/stm32/stm32l010-st-nucleo/SConstruct | 60 + .../applications/SConscript | 11 + .../stm32l010-st-nucleo/applications/main.c | 33 + .../board/CubeMX_Config/.mxproject | 14 + .../board/CubeMX_Config/CubeMX_Config.ioc | 114 + .../board/CubeMX_Config/Inc/main.h | 71 + .../CubeMX_Config/Inc/stm32l0xx_hal_conf.h | 302 ++ .../board/CubeMX_Config/Inc/stm32l0xx_it.h | 65 + .../board/CubeMX_Config/Src/main.c | 238 ++ .../CubeMX_Config/Src/stm32l0xx_hal_msp.c | 149 + .../board/CubeMX_Config/Src/stm32l0xx_it.c | 145 + .../CubeMX_Config/Src/system_stm32l0xx.c | 279 ++ bsp/stm32/stm32l010-st-nucleo/board/Kconfig | 48 + .../stm32l010-st-nucleo/board/SConscript | 34 + bsp/stm32/stm32l010-st-nucleo/board/board.c | 69 + bsp/stm32/stm32l010-st-nucleo/board/board.h | 50 + .../board/linker_scripts/link.icf | 29 + .../board/linker_scripts/link.lds | 157 + .../board/linker_scripts/link.sct | 16 + .../stm32l010-st-nucleo/figures/board.jpg | Bin 0 -> 161179 bytes bsp/stm32/stm32l010-st-nucleo/project.ewd | 2834 +++++++++++++++++ bsp/stm32/stm32l010-st-nucleo/project.ewp | 2259 +++++++++++++ bsp/stm32/stm32l010-st-nucleo/project.eww | 10 + bsp/stm32/stm32l010-st-nucleo/project.uvoptx | 932 ++++++ bsp/stm32/stm32l010-st-nucleo/project.uvprojx | 717 +++++ bsp/stm32/stm32l010-st-nucleo/rtconfig.h | 170 + bsp/stm32/stm32l010-st-nucleo/rtconfig.py | 143 + bsp/stm32/stm32l010-st-nucleo/template.ewp | 2031 ++++++++++++ bsp/stm32/stm32l010-st-nucleo/template.eww | 10 + bsp/stm32/stm32l010-st-nucleo/template.uvoptx | 192 ++ .../stm32l010-st-nucleo/template.uvprojx | 395 +++ 37 files changed, 12141 insertions(+) create mode 100644 bsp/stm32/stm32l010-st-nucleo/.config create mode 100644 bsp/stm32/stm32l010-st-nucleo/.gitignore create mode 100644 bsp/stm32/stm32l010-st-nucleo/Kconfig create mode 100644 bsp/stm32/stm32l010-st-nucleo/README.md create mode 100644 bsp/stm32/stm32l010-st-nucleo/SConscript create mode 100644 bsp/stm32/stm32l010-st-nucleo/SConstruct create mode 100644 bsp/stm32/stm32l010-st-nucleo/applications/SConscript create mode 100644 bsp/stm32/stm32l010-st-nucleo/applications/main.c create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/.mxproject create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/main.h create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_hal_conf.h create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_it.h create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/main.c create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_it.c create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/system_stm32l0xx.c create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/Kconfig create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/SConscript create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/board.c create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/board.h create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds create mode 100644 bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.sct create mode 100644 bsp/stm32/stm32l010-st-nucleo/figures/board.jpg create mode 100644 bsp/stm32/stm32l010-st-nucleo/project.ewd create mode 100644 bsp/stm32/stm32l010-st-nucleo/project.ewp create mode 100644 bsp/stm32/stm32l010-st-nucleo/project.eww create mode 100644 bsp/stm32/stm32l010-st-nucleo/project.uvoptx create mode 100644 bsp/stm32/stm32l010-st-nucleo/project.uvprojx create mode 100644 bsp/stm32/stm32l010-st-nucleo/rtconfig.h create mode 100644 bsp/stm32/stm32l010-st-nucleo/rtconfig.py create mode 100644 bsp/stm32/stm32l010-st-nucleo/template.ewp create mode 100644 bsp/stm32/stm32l010-st-nucleo/template.eww create mode 100644 bsp/stm32/stm32l010-st-nucleo/template.uvoptx create mode 100644 bsp/stm32/stm32l010-st-nucleo/template.uvprojx diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index a414e4a4c0..942e040b18 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -1,3 +1,4 @@ + # STM32 BSP 说明 STM32 系列 BSP 目前支持情况如下表所示： @@ -43,6 +44,7 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32h743-st-nucleo](stm32h743-st-nucleo) | ST 官方 STM32H743-nucleo 开发板 | | [stm32h747-st-discovery](stm32h747-st-discovery) | ST 官方 STM32H747I-discovery 开发板 | | **L0 系列** | | +| [stm32l010-st-nucleo](stm32l010-st-nucleo) | ST 官方 STM32L010-nucleo 开发板 | | [stm32l053-st-nucleo](stm32l053-st-nucleo) | ST 官方 STM32L053-nucleo 开发板 | | **L4 系列** | | | [stm32l4r9-st-eval](stm32l4r9-st-eval) | ST 官方 STM32L4R9I-EVAL 开发板 | diff --git a/bsp/stm32/stm32l010-st-nucleo/.config b/bsp/stm32/stm32l010-st-nucleo/.config new file mode 100644 index 0000000000..1b8152d27b --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/.config @@ -0,0 +1,364 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_QSDK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AT24CXX is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32L0=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32L010RB=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_USB_TO_USART is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_UART2_RX_USING_DMA is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32l010-st-nucleo/.gitignore b/bsp/stm32/stm32l010-st-nucleo/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32l010-st-nucleo/Kconfig b/bsp/stm32/stm32l010-st-nucleo/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32l010-st-nucleo/README.md b/bsp/stm32/stm32l010-st-nucleo/README.md new file mode 100644 index 0000000000..6b8613bb36 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/README.md @@ -0,0 +1,120 @@ + +# NUCLEO-L010RB 开发板 BSP 说明 + +## 简介 + +本文档为ST官方 NUCLEO-L010RB 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-L010RB 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，该开发板具有丰富的扩展接口，且与Arduino™ nano 接口兼容，可以方便验证 STM32L010RB 芯片的性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L010RB + - 主频 32MHz + - 128KB FLASH + - 20KB RAM + - 512 byte EEPROM +- 常用外设 + - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 黄色) + - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET） +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等 +- 调试接口：标准 SWD + +开发板更多详细信息请参考[STMicroelectronics NUCLEO-L010RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l010rb.html#overview)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | UART2 | +| SPI | 暂不支持 | | +| I2C | 暂不支持 | | +| RTC | 暂不支持 | | +| PWM | 暂不支持 | | +| USB Device | 暂不支持 | | +| IWG | 暂不支持 | | +| **扩展模块** | **支持情况** | **备注** | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LED1 和 LED3 常亮、黄色 LED2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 9 2020 + 2006 - 2020 Copyright by rt-thread team +msh > + +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 + +## 联系人信息 + +- 维护人: [xph](https://github.com/xupenghu) +- 邮箱： diff --git a/bsp/stm32/stm32l010-st-nucleo/SConscript b/bsp/stm32/stm32l010-st-nucleo/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32l010-st-nucleo/SConstruct b/bsp/stm32/stm32l010-st-nucleo/SConstruct new file mode 100644 index 0000000000..5fcb889bc2 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32L0xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32l010-st-nucleo/applications/SConscript b/bsp/stm32/stm32l010-st-nucleo/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32l010-st-nucleo/applications/main.c b/bsp/stm32/stm32l010-st-nucleo/applications/main.c new file mode 100644 index 0000000000..8541bd3b9f --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift change to new framework + */ + +#include +#include +#include + +/* defined the LED pin: PA5 */ +#define LED0_PIN GET_PIN(A, 5) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..8450d50e58 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/.mxproject @@ -0,0 +1,14 @@ +[PreviousGenFiles] +HeaderPath=D:/GitHub/rt-thread/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc +HeaderFiles=stm32l0xx_it.h;stm32l0xx_hal_conf.h;main.h; +SourcePath=D:/GitHub/rt-thread/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src +SourceFiles=stm32l0xx_it.c;stm32l0xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32l0xx_it.c;..\Src\stm32l0xx_hal_msp.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;../\Src/system_stm32l0xx.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;../\Src/system_stm32l0xx.c;../Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;null; +HeaderPath=..\Drivers\STM32L0xx_HAL_Driver\Inc;..\Drivers\STM32L0xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L0xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32L010xB;USE_HAL_DRIVER;STM32L010xB; + diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..fd1de238ea --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,114 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32L0 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IP3=USART2 +Mcu.IPNb=4 +Mcu.Name=STM32L010RBTx +Mcu.Package=LQFP64 +Mcu.Pin0=PC14-OSC32_IN +Mcu.Pin1=PC15-OSC32_OUT +Mcu.Pin2=PH0-OSC_IN +Mcu.Pin3=PH1-OSC_OUT +Mcu.Pin4=PA2 +Mcu.Pin5=PA3 +Mcu.Pin6=VP_SYS_VS_Systick +Mcu.PinsNb=7 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32L010RBTx +MxCube.Version=5.3.0 +MxDb.Version=DB.5.0.30 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PCC.Checker=true +PCC.Line=STM32L0x0 Value Line +PCC.MCU=STM32L010RBTx +PCC.PartNumber=STM32L010RBTx +PCC.Seq0=0 +PCC.Series=STM32L0 +PCC.Temperature=25 +PCC.Vdd=3.0 +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32L010RBTx +ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.11.2 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STM32L010RB_Test.ioc +ProjectManager.ProjectName=STM32L010RB_Test +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_Init-USART2-false-HAL-true +RCC.AHBFreq_Value=32000000 +RCC.APB1Freq_Value=32000000 +RCC.APB1TimFreq_Value=32000000 +RCC.APB2Freq_Value=32000000 +RCC.APB2TimFreq_Value=32000000 +RCC.FCLKCortexFreq_Value=32000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=32000000 +RCC.HSE_VALUE=8000000 +RCC.HSI16_VALUE=16000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=32000000 +RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLMUL,PLLSourceVirtual,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,WatchDogFreq_Value +RCC.LPTIMFreq_Value=32000000 +RCC.LPUARTFreq_Value=32000000 +RCC.LSI_VALUE=37000 +RCC.MCOPinFreq_Value=32000000 +RCC.MSI_VALUE=2097000 +RCC.PLLCLKFreq_Value=32000000 +RCC.PLLMUL=RCC_PLLMUL_8 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.PWRFreq_Value=32000000 +RCC.RTCFreq_Value=37000 +RCC.RTCHSEDivFreq_Value=4000000 +RCC.SYSCLKFreq_VALUE=32000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TIMFreq_Value=32000000 +RCC.TimerFreq_Value=32000000 +RCC.USART2Freq_Value=32000000 +RCC.VCOInputFreq_Value=8000000 +RCC.VCOOutputFreq_Value=64000000 +RCC.WatchDogFreq_Value=37000 +USART2.IPParameters=VirtualMode-Asynchronous +USART2.VirtualMode-Asynchronous=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..dd129ce7c3 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_hal_conf.h b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_hal_conf.h new file mode 100644 index 0000000000..224365aeb3 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_hal_conf.h @@ -0,0 +1,302 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l0xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_HAL_CONF_H +#define __STM32L0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_FIREWALL_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define PREREAD_ENABLE 1U +#define BUFFER_CACHE_DISABLE 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l0xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l0xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32l0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l0xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32l0xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l0xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l0xx_hal_rtc.h" + +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_it.h b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_it.h new file mode 100644 index 0000000000..e75e56bd0b --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_it.h @@ -0,0 +1,65 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_IT_H +#define __STM32L0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..0cb4860658 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/main.c @@ -0,0 +1,238 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART2_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c new file mode 100644 index 0000000000..3570c90a39 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c @@ -0,0 +1,149 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32l0xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_it.c b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_it.c new file mode 100644 index 0000000000..52e4aa9e44 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_it.c @@ -0,0 +1,145 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32l0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0+ Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable Interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32L0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32l0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/system_stm32l0xx.c b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/system_stm32l0xx.c new file mode 100644 index 0000000000..814b0c752e --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/system_stm32l0xx.c @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file system_stm32l0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx_system + * @{ + */ + +/** @addtogroup STM32L0xx_System_Private_Includes + * @{ + */ + +#include "stm32l0xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Defines + * @{ + */ +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */ + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit (void) +{ +/*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100U; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t) 0x88FF400CU; + + /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFF6U; + + /*!< Reset HSI48ON bit */ + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFFU; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFFU; + + /*!< Disable all interrupts */ + RCC->CIER = 0x00000000U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); + break; + case 0x04U: /* HSI used as system clock */ + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + { + SystemCoreClock = HSI_VALUE / 4U; + } + else + { + SystemCoreClock = HSI_VALUE; + } + break; + case 0x08U: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + default: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)]; + plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00U) + { + /* HSI oscillator clock selected as PLL clock entry */ + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + { + SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv); + } + else + { + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/Kconfig b/bsp/stm32/stm32l010-st-nucleo/board/Kconfig new file mode 100644 index 0000000000..13ef4ec408 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/Kconfig @@ -0,0 +1,48 @@ +menu "Hardware Drivers Config" + +config SOC_STM32L010RB + bool + select SOC_SERIES_STM32L0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable USB TO USART (uart2)" + select BSP_USING_UART2 + default y + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART2 + bool "Enable UART2" + default y + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + endif + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32l010-st-nucleo/board/SConscript b/bsp/stm32/stm32l010-st-nucleo/board/SConscript new file mode 100644 index 0000000000..74f501ff9b --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/SConscript @@ -0,0 +1,34 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32l0xx_hal_msp.c +''') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s'] + +# STM32L052xx || STM32L053xx || STM32L062xx +# STM32L063xx || STM32L072xx || STM32L073xx +# STM32L082xx || STM32L083xx +# You can select chips from the list above +CPPDEFINES = ['STM32L053xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.c b/bsp/stm32/stm32l010-st-nucleo/board/board.c new file mode 100644 index 0000000000..858d59660f --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/board.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInit; + + /**Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.h b/bsp/stm32/stm32l010-st-nucleo/board/board.h new file mode 100644 index 0000000000..9ca68af470 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (128 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 36 */ +#define STM32_SRAM_SIZE 20 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf new file mode 100644 index 0000000000..24d6f5275c --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf @@ -0,0 +1,29 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds new file mode 100644 index 0000000000..2280d5e461 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32L4XX with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 20KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } > RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } > RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.sct new file mode 100644 index 0000000000..418dc4b9fe --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load 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0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 7 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + + + STM32_HAL + 0 + 0 + 0 + 0 + + 8 + 40 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\system_stm32l0xx.c + system_stm32l0xx.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal.c + stm32l0xx_hal.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_comp.c + stm32l0xx_hal_comp.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_cortex.c + stm32l0xx_hal_cortex.c + 0 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_crc.c + stm32l0xx_hal_crc.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_crc_ex.c + stm32l0xx_hal_crc_ex.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_cryp.c + stm32l0xx_hal_cryp.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_cryp_ex.c + stm32l0xx_hal_cryp_ex.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_dma.c + stm32l0xx_hal_dma.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_pwr.c + stm32l0xx_hal_pwr.c + 0 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_pwr_ex.c + stm32l0xx_hal_pwr_ex.c + 0 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rcc.c + stm32l0xx_hal_rcc.c + 0 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rcc_ex.c + stm32l0xx_hal_rcc_ex.c + 0 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rng.c + stm32l0xx_hal_rng.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_gpio.c + stm32l0xx_hal_gpio.c + 0 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_uart.c + stm32l0xx_hal_uart.c + 0 + 0 + + + 8 + 56 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_uart_ex.c + stm32l0xx_hal_uart_ex.c + 0 + 0 + + + 8 + 57 + 1 + 0 + 0 + 0 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_usart.c + stm32l0xx_hal_usart.c + 0 + 0 + + + + diff --git a/bsp/stm32/stm32l010-st-nucleo/project.uvprojx b/bsp/stm32/stm32l010-st-nucleo/project.uvprojx new file mode 100644 index 0000000000..0e71514be5 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/project.uvprojx @@ -0,0 +1,717 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32L010RBTx + STMicroelectronics + Keil.STM32L0xx_DFP.2.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00000800) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32L010RBTx$CMSIS\Flash\STM32L0xx_128.FLM)) + 0 + $$Device:STM32L010RBTx$Drivers\CMSIS\Device\ST\STM32L0xx\Include\stm32l0xx.h + + + + + + + + + + $$Device:STM32L010RBTx$CMSIS\SVD\STM32L0x0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x800 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x800 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + STM32L010xB,USE_HAL_DRIVER + + .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Inc;..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Include;..\libraries\STM32L0xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32l0xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l0xx_hal_msp.c + + + startup_stm32l053xx.s + 2 + ..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\arm\startup_stm32l053xx.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + system_stm32l0xx.c + 1 + ..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\system_stm32l0xx.c + + + stm32l0xx_hal.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal.c + + + stm32l0xx_hal_comp.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_comp.c + + + stm32l0xx_hal_cortex.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_cortex.c + + + stm32l0xx_hal_crc.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_crc.c + + + stm32l0xx_hal_crc_ex.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_crc_ex.c + + + stm32l0xx_hal_cryp.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_cryp.c + + + stm32l0xx_hal_cryp_ex.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_cryp_ex.c + + + stm32l0xx_hal_dma.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_dma.c + + + stm32l0xx_hal_pwr.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_pwr.c + + + stm32l0xx_hal_pwr_ex.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_pwr_ex.c + + + stm32l0xx_hal_rcc.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rcc.c + + + stm32l0xx_hal_rcc_ex.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rcc_ex.c + + + stm32l0xx_hal_rng.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_rng.c + + + stm32l0xx_hal_gpio.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_gpio.c + + + stm32l0xx_hal_uart.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_uart.c + + + stm32l0xx_hal_uart_ex.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_uart_ex.c + + + stm32l0xx_hal_usart.c + 1 + ..\libraries\STM32L0xx_HAL\STM32L0xx_HAL_Driver\Src\stm32l0xx_hal_usart.c + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32l010-st-nucleo/rtconfig.h b/bsp/stm32/stm32l010-st-nucleo/rtconfig.h new file mode 100644 index 0000000000..4d177a0aaf --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/rtconfig.h @@ -0,0 +1,170 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32L0 + +/* Hardware Drivers Config */ + +#define SOC_STM32L010RB + +/* Onboard Peripheral Drivers */ + + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32l010-st-nucleo/rtconfig.py b/bsp/stm32/stm32l010-st-nucleo/rtconfig.py new file mode 100644 index 0000000000..39d6af6879 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/rtconfig.py @@ -0,0 +1,143 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0plus -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/stm32/stm32l010-st-nucleo/template.ewp b/bsp/stm32/stm32l010-st-nucleo/template.ewp new file mode 100644 index 0000000000..f390ad7bc1 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32l010-st-nucleo/template.eww b/bsp/stm32/stm32l010-st-nucleo/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32l010-st-nucleo/template.uvoptx b/bsp/stm32/stm32l010-st-nucleo/template.uvoptx new file mode 100644 index 0000000000..7f4a45a0e7 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/template.uvoptx @@ -0,0 +1,192 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC800 -FD20000000 -FF0STM32L0xx_128 -FL020000 -FS08000000 -FP0($$Device:STM32L010RBTx$CMSIS\Flash\STM32L0xx_128.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("") -D00(00000000) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32L010RBTx$CMSIS\Flash\STM32L0xx_128.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32l010-st-nucleo/template.uvprojx b/bsp/stm32/stm32l010-st-nucleo/template.uvprojx new file mode 100644 index 0000000000..74da7a4e37 --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/template.uvprojx @@ -0,0 +1,395 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060300::V5.06 update 3 (build 300)::ARMCC + 0 + + + STM32L010RBTx + STMicroelectronics + Keil.STM32L0xx_DFP.2.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00000800) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0STM32L0xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32L010RBTx$CMSIS\Flash\STM32L0xx_128.FLM)) + 0 + $$Device:STM32L010RBTx$Drivers\CMSIS\Device\ST\STM32L0xx\Include\stm32l0xx.h + + + + + + + + + + $$Device:STM32L010RBTx$CMSIS\SVD\STM32L0x0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x800 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x800 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + From c0947d443a11175d1c33d805b0dbf03e7f3f708c Mon Sep 17 00:00:00 2001 From: Jonne Date: Sat, 11 Apr 2020 12:06:40 +0800 Subject: [PATCH 02/27] 1. Add 4.3 inch lcd(480x272) support for mini2440 2. Add choice menu for lcd configure 3. Remove origin sdcard driver and add new mmc driver that use kernel mmc stack for s3c2440 --- bsp/mini2440/.config | 8 +- bsp/mini2440/Kconfig | 23 +- bsp/mini2440/applications/main.c | 17 +- bsp/mini2440/applications/mnt.c | 19 +- bsp/mini2440/drivers/SConscript | 32 +- bsp/mini2440/drivers/lcd.h | 21 - bsp/mini2440/drivers/lcd_a70.c | 7 +- bsp/mini2440/drivers/lcd_n35.c | 7 +- bsp/mini2440/drivers/lcd_t35.c | 7 +- bsp/mini2440/drivers/lcd_t43.c | 249 ++++++++++++ bsp/mini2440/drivers/lcd_x35.c | 7 +- bsp/mini2440/drivers/s3cmci.c | 332 ++++++++++++++++ bsp/mini2440/drivers/sdcard.c | 651 ------------------------------- bsp/mini2440/drivers/sdcard.h | 11 - bsp/mini2440/drivers/touch.c | 33 +- bsp/mini2440/drivers/touch.h | 2 +- bsp/mini2440/rtconfig.h | 6 + bsp/mini2440/rtconfig.py | 4 - 18 files changed, 704 insertions(+), 732 deletions(-) delete mode 100644 bsp/mini2440/drivers/lcd.h create mode 100644 bsp/mini2440/drivers/lcd_t43.c create mode 100644 bsp/mini2440/drivers/s3cmci.c delete mode 100644 bsp/mini2440/drivers/sdcard.c delete mode 100644 bsp/mini2440/drivers/sdcard.h diff --git a/bsp/mini2440/.config b/bsp/mini2440/.config index e10689caa8..1e1372162c 100644 --- a/bsp/mini2440/.config +++ b/bsp/mini2440/.config @@ -161,7 +161,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set diff --git a/bsp/mini2440/Kconfig b/bsp/mini2440/Kconfig index 44da5183eb..48e4f26a38 100644 --- a/bsp/mini2440/Kconfig +++ b/bsp/mini2440/Kconfig @@ -16,12 +16,33 @@ config PKGS_DIR default "packages" config BOARD_MINI2440 - bool "mini2440" + bool select ARCH_ARM_ARM9 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y +choice + prompt "Lcd for mini2440" + default RT_MINI2440_LCD_T35 + depends on PKG_USING_GUIENGINE + + config RT_MINI2440_LCD_A70 + bool "A70" + + config RT_MINI2440_LCD_T43 + bool "T43" + + config RT_MINI2440_LCD_N35 + bool "N35" + + config RT_MINI2440_LCD_T35 + bool "T35" + + config RT_MINI2440_LCD_X35 + bool "X35" +endchoice + source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" diff --git a/bsp/mini2440/applications/main.c b/bsp/mini2440/applications/main.c index a67ff93f7a..923f014469 100644 --- a/bsp/mini2440/applications/main.c +++ b/bsp/mini2440/applications/main.c @@ -5,9 +5,24 @@ #include "led.h" +#ifdef PKG_USING_GUIENGINE +#include +#endif + int main(void) { - printf("hello rt-thread\n"); + rt_device_t device; + + printf("hello rt-thread\n"); + +#ifdef PKG_USING_GUIENGINE + device = rt_device_find("lcd"); + if (device) + { + rtgui_graphic_set_device(device); + } +#endif + while (1) { diff --git a/bsp/mini2440/applications/mnt.c b/bsp/mini2440/applications/mnt.c index 50ade3a3eb..2e1ae80692 100644 --- a/bsp/mini2440/applications/mnt.c +++ b/bsp/mini2440/applications/mnt.c @@ -6,15 +6,28 @@ int mnt_init(void) { - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + rt_uint32_t tryCnt = 5; + rt_device_t dev; + + while(tryCnt--) { - rt_kprintf("File System initialized!\n"); + dev = rt_device_find("sd0"); + if(dev != RT_NULL) + { + break; + } + rt_thread_mdelay(500); + } + + if(dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); } else { rt_kprintf("File System initialzation failed!\n"); } - + return RT_EOK; } INIT_ENV_EXPORT(mnt_init); diff --git a/bsp/mini2440/drivers/SConscript b/bsp/mini2440/drivers/SConscript index 2c81f19e33..902b48320d 100644 --- a/bsp/mini2440/drivers/SConscript +++ b/bsp/mini2440/drivers/SConscript @@ -8,30 +8,30 @@ cwd = os.path.join(str(Dir('#')), 'drivers') src = Split(""" board.c led.c +key.c uart.c """) -if GetDepend('RT_USING_DFS'): - src += ['sdcard.c'] - if GetDepend('RT_USING_LWIP'): src += ['dm9000.c'] -if GetDepend('PKG_USING_GUIENGINE'): - src += ['touch.c', 'key.c'] +if GetDepend('RT_MINI2440_LCD_A70'): + src += ['lcd_a70.c'] +if GetDepend('RT_MINI2440_LCD_T43'): + src += ['lcd_t43.c'] +if GetDepend('RT_MINI2440_LCD_N35'): + src += ['lcd_n35.c'] +if GetDepend('RT_MINI2440_LCD_T35'): + src += ['lcd_t35.c'] +if GetDepend('RT_MINI2440_LCD_X35'): + src += ['lcd_x35.c'] -if GetDepend('RT_USING_RTI'): - src += ['rti_stub.c'] - if GetDepend('PKG_USING_GUIENGINE'): - if rtconfig.RT_USING_LCD_TYPE == 'PNL_A70': - src += ['lcd_a70.c'] - elif rtconfig.RT_USING_LCD_TYPE == 'PNL_N35': - src += ['lcd_n35.c'] - elif rtconfig.RT_USING_LCD_TYPE == 'PNL_T35': - src += ['lcd_t35.c'] - elif rtconfig.RT_USING_LCD_TYPE == 'PNL_X35': - src += ['lcd_x35.c'] + src += ['touch.c'] + +if GetDepend('RT_USING_SDIO'): + src += ['s3cmci.c'] + CPPPATH = [cwd] diff --git a/bsp/mini2440/drivers/lcd.h b/bsp/mini2440/drivers/lcd.h deleted file mode 100644 index f733b5593c..0000000000 --- a/bsp/mini2440/drivers/lcd.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * File : lcd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-03-29 Yi.Qiu - */ -#ifndef __LCD_H__ -#define __LCD_H__ - -#include - -void rt_hw_lcd_init(void); - -#endif diff --git a/bsp/mini2440/drivers/lcd_a70.c b/bsp/mini2440/drivers/lcd_a70.c index 02a89b9d47..7ebcf6a047 100644 --- a/bsp/mini2440/drivers/lcd_a70.c +++ b/bsp/mini2440/drivers/lcd_a70.c @@ -15,7 +15,6 @@ #include #include -#include "lcd.h" /* LCD driver for A7' */ #define LCD_WIDTH 800 @@ -223,10 +222,11 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) return RT_EOK; } -void rt_hw_lcd_init(void) +int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ + if (lcd == RT_NULL) + return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; @@ -246,3 +246,4 @@ void rt_hw_lcd_init(void) rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } +INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_n35.c b/bsp/mini2440/drivers/lcd_n35.c index bcd3b85b8a..57d792ea39 100644 --- a/bsp/mini2440/drivers/lcd_n35.c +++ b/bsp/mini2440/drivers/lcd_n35.c @@ -15,7 +15,6 @@ #include #include -#include "lcd.h" /* LCD driver for N3'5 */ #define LCD_WIDTH 240 @@ -224,10 +223,11 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) return RT_EOK; } -void rt_hw_lcd_init(void) +int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ + if (lcd == RT_NULL) + return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; @@ -247,3 +247,4 @@ void rt_hw_lcd_init(void) rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } +INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_t35.c b/bsp/mini2440/drivers/lcd_t35.c index ef424a7bf7..fdcab887f5 100644 --- a/bsp/mini2440/drivers/lcd_t35.c +++ b/bsp/mini2440/drivers/lcd_t35.c @@ -15,7 +15,6 @@ #include #include -#include "lcd.h" /* LCD driver for T3'5 */ #define LCD_WIDTH 240 @@ -225,10 +224,11 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) return RT_EOK; } -void rt_hw_lcd_init(void) +int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ + if (lcd == RT_NULL) + return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; @@ -248,3 +248,4 @@ void rt_hw_lcd_init(void) rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } +INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_t43.c b/bsp/mini2440/drivers/lcd_t43.c new file mode 100644 index 0000000000..54abc12f3e --- /dev/null +++ b/bsp/mini2440/drivers/lcd_t43.c @@ -0,0 +1,249 @@ +/* + * File : lcd_t43.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2020-04-12 Jonne first version from 4.3 inch lcd(480x272) + */ + +#include +#include + +/* LCD driver for N3'5 */ +#define LCD_WIDTH 480 +#define LCD_HEIGHT 272 +#define LCD_PIXCLOCK 4 + +#define LCD_RIGHT_MARGIN 2 +#define LCD_LEFT_MARGIN 2 +#define LCD_HSYNC_LEN 41 + +#define LCD_UPPER_MARGIN 2 +#define LCD_LOWER_MARGIN 2 +#define LCD_VSYNC_LEN 10 + +#define LCD_XSIZE LCD_WIDTH +#define LCD_YSIZE LCD_HEIGHT +#define SCR_XSIZE LCD_WIDTH +#define SCR_YSIZE LCD_HEIGHT + +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT + +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control + +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) + +#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) + +#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN2GREY (1<<1) +#define S3C2410_LCDCON1_STN4GREY (2<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN12BPP (4<<1) + +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT16BPP (12<<1) +#define S3C2410_LCDCON1_TFT24BPP (13<<1) + +#define S3C2410_LCDCON1_ENVID (1) + +#define S3C2410_LCDCON1_MODEMASK 0x1E + +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) + +#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) +#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) +#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) + +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) + +#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) +#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) + +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) + +#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) + +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_INVVLINE (1<<9) +#define S3C2410_LCDCON5_INVVFRAME (1<<8) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVPWREN (1<<5) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) + +#define S3C2410_LCDINT_FRSYNC (1<<1) + +static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; +//static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; +static struct rt_device_graphic_info _lcd_info; + +static void lcd_power_enable(int invpwren, int pwren) +{ + //GPG4 is setted as LCD_PWREN + GPGUP = GPGUP | (1<<4); // Pull-up disable + GPGCON = GPGCON | (3<<8); //GPG4=LCD_PWREN + + //Enable LCD POWER ENABLE Function + LCDCON5 = LCDCON5&(~(1<<3))|(pwren<<3); // PWREN + LCDCON5 = LCDCON5&(~(1<<5))|(invpwren<<5); // INVPWREN +} + +static void lcd_envid_on_off(int onoff) +{ + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; +} + +//********************** BOARD LCD backlight **************************** +static void LcdBkLtSet(rt_uint32_t HiRatio) +{ +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; + + if( HiRatio > 100 ) HiRatio = 100 ; + + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 + + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; +} + +/* RT-Thread Device Interface */ +static rt_err_t rt_lcd_init (rt_device_t dev) +{ + GPB1_TO_OUT(); + GPB1_TO_1(); + + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; + + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; + +#define M5D(n) ((n)&0x1fffff) +#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = ((LCD_UPPER_MARGIN - 1) << 24) | ((LCD_HEIGHT - 1) << 14) | ((LCD_LOWER_MARGIN - 1) << 6) | ((LCD_VSYNC_LEN - 1) << 0); + LCDCON3 = ((LCD_RIGHT_MARGIN - 1) << 19) | ((LCD_WIDTH - 1) << 8) | ((LCD_LEFT_MARGIN - 1) << 0); + LCDCON4 = (13 << 8) | ((LCD_HSYNC_LEN - 1) << 0); +#if !defined(LCD_CON5) + #define LCD_CON5 ((1<<11) | (0<<10) | (1<<9) | (1<<8) | (1<<0)) +#endif + LCDCON5 = LCD_CON5; + + LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); + LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); + LCDSADDR3 = LCD_WIDTH; + + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; + + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); + + return RT_EOK; +} + +static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; +} + +int rt_hw_lcd_init(void) +{ + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) + return -RT_ERROR; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); +} + +INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_x35.c b/bsp/mini2440/drivers/lcd_x35.c index 679d433f9b..e625905130 100644 --- a/bsp/mini2440/drivers/lcd_x35.c +++ b/bsp/mini2440/drivers/lcd_x35.c @@ -17,7 +17,6 @@ #include #include -#include "lcd.h" /* LCD driver for X3'5 */ #define LCD_WIDTH 240 // xres @@ -230,10 +229,11 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) return RT_EOK; } -void rt_hw_lcd_init(void) +int rt_hw_lcd_init(void) { rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ + if (lcd == RT_NULL) + return -RT_ERROR; /* no memory yet */ _lcd_info.bits_per_pixel = 16; _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; @@ -253,3 +253,4 @@ void rt_hw_lcd_init(void) rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } +INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/s3cmci.c b/bsp/mini2440/drivers/s3cmci.c new file mode 100644 index 0000000000..2333c74495 --- /dev/null +++ b/bsp/mini2440/drivers/s3cmci.c @@ -0,0 +1,332 @@ +/* + * File : s3cmci.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2020-04-15 Jonne first version for s3c2440 mmc controller + */ + +#include +#include +#include +#include +#include + +#define S3C_PCLK 50000000 + + +static void s3c_mmc_set_clk(struct rt_mmcsd_host *host, rt_uint32_t clock) +{ + rt_uint32_t prescale; + rt_uint32_t realClk; + + for(prescale = 0; prescale < 256; ++prescale) + { + realClk = S3C_PCLK / (1 + prescale); + if(realClk <= clock) + { + break; + } + } + + SDIPRE = prescale; + host->io_cfg.clock = realClk; +} + +static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) +{ + rt_uint32_t ccon; + rt_uint32_t cmdSta; + + SDICARG = cmd->arg; + + ccon = cmd->cmd_code & 0x3f; + ccon |= (0 << 7) | (1 << 6); /* two start bits*/ + ccon |= (1 << 8);/* command start*/ + + if(cmd->flags & 0xF) + { + // Need response + ccon |= (1 << 9); + } + + if((cmd->flags & 0xF) == RESP_R2) + { + // R2 need 136bit response + ccon |= (1 << 10); + } + + SDICCON = ccon; /* start cmd */ + + if(cmd->flags & 0xF) + { + cmdSta = SDICSTA; + while((cmdSta & 0x200) != 0x200 && (cmdSta & 0x400) != 0x400) + { + cmdSta = SDICSTA; + } + + if((cmdSta & 0x1000) == 0x1000 && (cmd->flags & 0xF) != RESP_R3 && (cmd->flags & 0xF) != RESP_R4) + { + // crc error, but R3 R4 ignore it + SDICSTA = cmdSta; + return -RT_ERROR; + } + + if((cmdSta & 0xF00) != 0xa00) + { + SDICSTA = cmdSta; + return -RT_ERROR; + } + + cmd->resp[0] = SDIRSP0; + if((cmd->flags & 0xF) == RESP_R2) + { + cmd->resp[1] = SDIRSP1; + cmd->resp[2] = SDIRSP2; + cmd->resp[3] = SDIRSP3; + } + } + else + { + cmdSta = SDICSTA; + while((cmdSta & 0x800) != 0x800) + { + cmdSta = SDICSTA; + } + } + + SDICSTA = cmdSta; // clear current status + + return RT_EOK; + +} + +static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data) +{ + rt_uint32_t status; + rt_uint32_t xfer_size; + rt_uint32_t handled_size = 0; + rt_uint32_t *pBuf = RT_NULL; + + + if(data == RT_NULL) + { + return -RT_ERROR; + } + + xfer_size = data->blks * data->blksize; + + pBuf = data->buf; + if(data->flags & DATA_DIR_READ) + { + while(handled_size < xfer_size) + { + if ((SDIDSTA & 0x20) == 0x20) + { + SDIDSTA = (0x1 << 0x5); + break; + } + + status = SDIFSTA; + if ((status & 0x1000) == 0x1000) + { + *pBuf++ = SDIDAT; + handled_size += 4; + } + } + } + else + { + while(handled_size < xfer_size) + { + status = SDIFSTA; + if ((status & 0x2000) == 0x2000) + { + SDIDAT = *pBuf++; + handled_size += 4; + } + } + } + + // wait for end + status = SDIDSTA; + while((status & 0x30) == 0) + { + status = SDIDSTA; + } + SDIDSTA = status; + + if ((status & 0xfc) != 0x10) + { + return -RT_ERROR; + } + + SDIDCON = SDIDCON & ~(7<<12); + SDIFSTA = SDIFSTA & 0x200; + SDIDSTA = 0x10; + + return RT_EOK; +} +static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + rt_uint32_t ret; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t val; + rt_uint32_t tryCnt = 0; + + if(req->cmd == RT_NULL) + { + goto out; + } + cmd = req->cmd; + + /* prepare for data transfer*/ + if(req->data != RT_NULL) + { + SDIFSTA = SDIFSTA | (1<<16); // reset fifo + + while(SDIDSTA & 0x03) + { + if(tryCnt++ > 500) + { + break; + SDIDSTA = SDIDSTA; + } + } + + data = req->data; + + if((data->blksize & 0x3) != 0) + { + goto out; + } + + val = (2 << 22) //word transfer + | (1 << 20) // transmet after response + | (1 << 19) // reciveve after command sent + | (1 << 17) // block data transfer + | (1 << 14); // data start + + if(host->io_cfg.bus_width == MMCSD_BUS_WIDTH_4) + { + val |= (1 << 16); // wide bus mode(4bit data) + } + + if(data->flags & DATA_DIR_READ) + { + // for data read + val |= (2 << 12); + } + else + { + val |= (3 << 12); + } + + val |= (data->blks & 0xFFF); + + SDIDCON = val; + + SDIBSIZE = data->blksize; + SDIDTIMER = 0x7fffff; + } + + ret = s3c_mmc_send_cmd(host,req->cmd); + if(ret != RT_EOK) { + cmd->err = ret; + goto out; + } + + if(req->data != RT_NULL) + { + /*do transfer data*/ + ret = s3c_mmc_xfer_data(data); + if(ret != RT_EOK) + { + data->err = ret; + goto out; + } + } + +out: + mmcsd_req_complete(host); +} +static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + switch (io_cfg->power_mode) { + case MMCSD_POWER_ON: + case MMCSD_POWER_UP: + /* Enable PCLK into SDI Block */ + CLKCON |= 1 << 9; + + /* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */ + GPEUP = GPEUP & (~(0x3f << 5)) | (0x01 << 5); + GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10); + break; + + case MMCSD_POWER_OFF: + default: + break; + } + + s3c_mmc_set_clk(host, io_cfg->clock); + + SDICON = 1; +} + +static rt_int32_t mmc_get_card_status(struct rt_mmcsd_host *host) +{ + return RT_EOK; +} +static void mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en) +{ +} + +static const struct rt_mmcsd_host_ops ops = +{ + mmc_request, + mmc_set_iocfg, + mmc_get_card_status, + mmc_enable_sdio_irq +}; + +int s3c_sdio_init(void) +{ + struct rt_mmcsd_host * host = RT_NULL; + + + host = mmcsd_alloc_host(); + if (!host) + { + goto err; + } + + host->ops = &ops; + host->freq_min = 300000; + host->freq_max = 50000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; + host->max_seg_size = 2048; + host->max_dma_segs = 10; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + + mmcsd_change(host); + + return RT_EOK; + +err: + if(host) rt_free(host); + + return -RT_EIO; +} + +INIT_DEVICE_EXPORT(s3c_sdio_init); diff --git a/bsp/mini2440/drivers/sdcard.c b/bsp/mini2440/drivers/sdcard.c deleted file mode 100644 index 9815770bab..0000000000 --- a/bsp/mini2440/drivers/sdcard.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - * File : sd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2007, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2007-12-02 Yi.Qiu the first version - * 2010-01-01 Bernard Modify for mini2440 - * 2012-12-15 amr168 support SDHC - * 2017-11-20 kuangdazzidd add csd cmd support - */ - -#include "sdcard.h" -#include "rtdef.h" - -extern rt_uint32_t PCLK; -volatile rt_uint32_t rd_cnt; -volatile rt_uint32_t wt_cnt; -volatile rt_int32_t RCA; -volatile rt_int32_t sd_type; - -struct sd_csd { - rt_uint16_t bsize; - rt_uint32_t nblks; -}g_sd_csd; - -static void sd_delay(rt_uint32_t ms) -{ - ms *= 7326; - while(--ms); -} - -static int sd_cmd_end(int cmd, int be_resp) -{ - int finish0; - - if (!be_resp) - { - finish0 = SDICSTA; - - while ((finish0&0x800) != 0x800) - finish0 = SDICSTA; - - SDICSTA = finish0; - - return RT_EOK; - } - else - { - finish0 = SDICSTA; - - while (!(((finish0&0x200)==0x200) | ((finish0&0x400) == 0x400))) - finish0=SDICSTA; - - if (cmd == 1 || cmd == 41) - { - if ((finish0 & 0xf00) != 0xa00) - { - SDICSTA = finish0; - if ((finish0&0x400) == 0x400) - return RT_ERROR; - } - SDICSTA = finish0; - } - else - { - if ((finish0 & 0x1f00) != 0xa00) - { - /* rt_kprintf("CMD%d:SDICSTA=0x%x, SDIRSP0=0x%x\n", cmd, SDICSTA, SDIRSP0); */ - SDICSTA = finish0; - if ((finish0 & 0x400) == 0x400) - return RT_ERROR; - } - SDICSTA = finish0; - } - return RT_EOK; - } -} - -static int sd_data_end(void) -{ - int finish; - - finish = SDIDSTA; - - while (!(((finish & 0x10) == 0x10) | ((finish & 0x20) == 0x20))) - { - finish = SDIDSTA; - } - - if ((finish & 0xfc) != 0x10) - { - SDIDSTA = 0xec; - - return RT_ERROR; - } - - return RT_EOK; -} - -static void sd_cmd0(void) -{ - SDICARG = 0x0; - SDICCON = (1<<8) | 0x40; - - sd_cmd_end(0, 0); - SDICSTA = 0x800; /* Clear cmd_end(no rsp) */ -} - -static int sd_cmd55(void) -{ - SDICARG = RCA << 16; - SDICCON = (0x1 << 9) | (0x1 << 8) | 0x77; - - if (sd_cmd_end(55, 1) == RT_ERROR) - { - /* rt_kprintf("CMD55 error\n"); */ - return RT_ERROR; - } - - SDICSTA = 0xa00; - - - return RT_EOK; -} - -static int sd_cmd9(void *p_rsp) -{ -SDICARG = RCA << 16; -SDICCON = (1 << 10) | (1 << 9) | (0x1<<8) | (0x40 | 0x09); - -sd_cmd_end(9, 1); - - ((rt_uint32_t *)p_rsp)[0] = SDIRSP3; - ((rt_uint32_t *)p_rsp)[1] = SDIRSP2; - ((rt_uint32_t *)p_rsp)[2] = SDIRSP1; - ((rt_uint32_t *)p_rsp)[3] = SDIRSP0; - -return RT_EOK; -} - -static void sd_sel_desel(char sel_desel) -{ - if (sel_desel) - { -RECMDS7: - SDICARG = RCA << 16; - SDICCON = (0x1 << 9) | (0x1 << 8) | 0x47; - if (sd_cmd_end(7, 1) == RT_ERROR) - goto RECMDS7; - - SDICSTA = 0xa00; - - if (SDIRSP0 & 0x1e00 != 0x800) - goto RECMDS7; - } - else - { -RECMDD7: - SDICARG = 0 << 16; - SDICCON = (0x1 << 8) | 0x47; - - if (sd_cmd_end(7, 0) == RT_ERROR) - goto RECMDD7; - SDICSTA = 0x800; - } -} - -static void sd_setbus(void) -{ - do - { - sd_cmd55(); - - SDICARG = 1 << 1; /* 4bit bus */ - SDICCON = (0x1<<9) | (0x1<<8) | 0x46; /* sht_resp, wait_resp, start, CMD55 */ - }while (sd_cmd_end(6, 1) == RT_ERROR); - - SDICSTA=0xa00; /* Clear cmd_end(with rsp) */ -} - - -static rt_uint32_t bits_str (rt_uint32_t *str, rt_uint32_t start, rt_uint8_t len) -{ - rt_uint32_t mask; - rt_uint32_t index; - rt_uint8_t shift; - rt_uint32_t value; - - mask = (int)((len < 32) ? (1 << len) : 0) - 1; - index = start / 32; - shift = start & 31; - value = str[index] >> shift; - - if ((len + shift) > 32) { - value |= str[index + 1] << (32 - shift); - } - value &= mask; - return value; -} - - -static int sd_decode_csd (rt_uint32_t *p_csd) -{ - rt_uint32_t e, m, r; - rt_uint8_t structure; - - structure = bits_str(p_csd, 126, 2); - - switch (structure) { - case 0: - m = bits_str(p_csd, 99, 4); - e = bits_str(p_csd, 96, 3); - g_sd_csd.bsize = 512; - m = bits_str(p_csd, 62, 12); - e = bits_str(p_csd, 47, 3); - r = bits_str(p_csd, 80, 4); - g_sd_csd.nblks = ((1 + m) << (e + r - 7)); - break; - - case 1: - m = bits_str(p_csd, 99, 4); - e = bits_str(p_csd, 96, 3); - g_sd_csd.bsize = 512; - m = bits_str(p_csd, 48, 22); - g_sd_csd.nblks = (1 + m) << 10; - break; - - default: - return RT_ERROR; - } - return RT_EOK; -} - - -static int sd_send_csd(rt_uint32_t *p_csd) -{ - int ret; - rt_uint32_t rsp[4]; - - ret = sd_cmd9((void*)&rsp); - - if (ret != 0) { - return ret; - } - - rt_memcpy((void*)p_csd, (void*)rsp, 16); - return RT_EOK; -} - -static int sd_ocr(void) -{ - int i, ver=0; - - /* Negotiate operating condition for SD, it makes card ready state */ - for (i = 0; i < 50; i ++) - { - sd_cmd55(); - - SDICARG = 0x40ff8000; /* HCS=1, compatible v1.x and v2.0 */ - SDICCON = (0x1<<9) | (0x1<<8) | 0x69; - - /* if using real board, should replace code here. need to modify qemu in near future*/ - /* Check end of ACMD41 */ - if (sd_cmd_end(41, 1) == RT_EOK) - { - if (SDIRSP0 == 0x80ff8000) - { - ver = 1; /* SD V1.x, CCS=0 */ - break; - } - else if (SDIRSP0 == 0xc0ff8000) - { - ver = 2; /* SD V2.0, CCS=1 */ - break; - } - } - - sd_delay(200); - } - SDICSTA = 0xa00; - - return ver; -} - -rt_err_t sd_cmd8(void) -{ - SDICARG = 0x000001AA; - SDICCON = (0x1<<9) | (0x1<<8) | 0x48; //sht_resp, wait_resp, start - if (sd_cmd_end(8, 1) == RT_ERROR) - return RT_ERROR; - SDICSTA = 0xa00; - - if ((SDIRSP0&0x1aa) == 0x1aa) - return RT_EOK; - else - return RT_ERROR; -} - -static rt_uint8_t sd_init(void) -{ - //-- SD controller & card initialize - int i; - rt_uint32_t csd[4]; - /* Important notice for MMC test condition */ - /* Cmd & Data lines must be enabled by pull up resister */ - SDIPRE = PCLK / (INICLK) - 1; - SDICON = (0<<4) | 1; // Type A, clk enable - SDIFSTA = SDIFSTA | (1<<16); - SDIBSIZE = 0x200; /* 512byte per one block */ - SDIDTIMER = 0x7fffff; /* timeout count */ - - /* Wait 74SDCLK for MMC card */ - for (i = 0; i < 0x1000; i ++); - - sd_cmd0(); - sd_cmd8(); /* Must be use it, Host shall supports high capacity */ - - /* Check SD card OCR */ - sd_type = sd_ocr(); - if (sd_type > 0) - { - rt_kprintf("In SD ready\n"); - } - else - { - rt_kprintf("Initialize fail\nNo Card assertion\n"); - - return RT_ERROR; - } - -RECMD2: - SDICARG = 0x0; - SDICCON = (0x1<<10)|(0x1<<9)|(0x1<<8)|0x42; /* lng_resp, wait_resp, start, CMD2 */ - if (sd_cmd_end(2, 1) == RT_ERROR) - goto RECMD2; - - SDICSTA = 0xa00; /* Clear cmd_end(with rsp) */ - -RECMD3: - SDICARG = 0<<16; /* CMD3(MMC:Set RCA, SD:Ask RCA-->SBZ) */ - SDICCON = (0x1<<9)|(0x1<<8)|0x43; /* sht_resp, wait_resp, start, CMD3 */ - if (sd_cmd_end(3, 1) == RT_ERROR) - goto RECMD3; - SDICSTA=0xa00; /* Clear cmd_end(with rsp) */ - - sd_send_csd(csd); - sd_decode_csd(csd); - - RCA = (SDIRSP0 & 0xffff0000) >> 16; - SDIPRE = PCLK / (SDCLK) - 1; /* Normal clock=25MHz */ - if (SDIRSP0 & 0x1e00 != 0x600) - goto RECMD3; - - sd_sel_desel(1); - sd_delay(200); - sd_setbus(); - - return RT_EOK; -} - -static rt_uint8_t sd_readblock(rt_uint32_t address, rt_uint8_t *buf) -{ - rt_uint32_t status, tmp; - - rd_cnt = 0; - SDIFSTA = SDIFSTA | (1<<16); - - SDIDCON = (2 << 22) | (1 << 19) | (1 << 17) | (1 << 16) | (1 << 14) | (2 << 12) | (1 << 0); - SDICARG = address; - -RERDCMD: - SDICCON = (0x1 << 9 ) | (0x1 << 8) | 0x51; - if (sd_cmd_end(17, 1) == RT_ERROR) - { - rt_kprintf("Read CMD Error\n"); - goto RERDCMD; - } - - SDICSTA = 0xa00; - - while (rd_cnt < 128) - { - if ((SDIDSTA & 0x20) == 0x20) - { - SDIDSTA = (0x1 << 0x5); - break; - } - status = SDIFSTA; - if ((status & 0x1000) == 0x1000) - { - tmp = SDIDAT; - rt_memcpy(buf, &tmp, sizeof(rt_uint32_t)); - rd_cnt ++; - buf += 4; - } - } - if (sd_data_end() == RT_ERROR) - { - rt_kprintf("Dat error\n"); - - return RT_ERROR; - } - - SDIDCON = SDIDCON &~ (7<<12); - SDIFSTA = SDIFSTA & 0x200; - SDIDSTA = 0x10; - - return RT_EOK; -} - -static rt_uint8_t sd_writeblock(rt_uint32_t address, rt_uint8_t *buf) -{ - rt_uint32_t status, tmp; - - wt_cnt = 0; - SDIFSTA = SDIFSTA | (1 << 16); - - SDIDCON = (2 << 22) | (1 << 20) | (1 << 17) | (1 << 16) | (1 << 14) | (3 << 12) | (1 << 0); - SDICARG = address; - -REWTCMD: - SDICCON = (0x1 << 9) | (0x1 << 8) |0x58; - - if (sd_cmd_end(24, 1) == RT_ERROR) - goto REWTCMD; - - SDICSTA = 0xa00; - - while (wt_cnt < 128) - { - status = SDIFSTA; - if ((status & 0x2000) == 0x2000) - { - rt_memcpy(&tmp, buf, sizeof(rt_uint32_t)); - SDIDAT = tmp; - wt_cnt ++; - buf += 4; - } - } - if (sd_data_end() == RT_ERROR) - { - rt_kprintf("Data Error\n"); - - return RT_ERROR; - } - SDIDCON = SDIDCON &~ (7<<12); - SDIDSTA = 0x10; - - return RT_EOK; -} - -#ifdef RT_USING_DFS -/* RT-Thread Device Driver Interface */ -#include - -#include - -struct rt_device sdcard_device[4]; -struct dfs_partition part[4]; - -static rt_err_t rt_sdcard_init(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_sdcard_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) -{ -struct rt_device_blk_geometry *p_geometry = (struct rt_device_blk_geometry *)args; -p_geometry->block_size = g_sd_csd.bsize; -p_geometry->sector_count = g_sd_csd.nblks; -p_geometry->bytes_per_sector = 512; - return RT_EOK; -} - -static rt_size_t rt_sdcard_read(rt_device_t dev, - rt_off_t pos, - void *buffer, - rt_size_t size) -{ - int i, addr; - struct dfs_partition *part = (struct dfs_partition *)dev->user_data; - - if (dev == RT_NULL) - { - rt_set_errno(-EINVAL); - - return 0; - } - - /* read all sectors */ - for (i = 0; i < size; i ++) - { - rt_sem_take(part->lock, RT_WAITING_FOREVER); - if (sd_type == 1) - addr = (part->offset + i + pos)*SECTOR_SIZE; - else - addr = (part->offset + i + pos); - sd_readblock(addr, (rt_uint8_t *)((rt_uint8_t *)buffer + i * SECTOR_SIZE)); - rt_sem_release(part->lock); - } - - /* the length of reading must align to SECTOR SIZE */ - return size; -} - -static rt_size_t rt_sdcard_write(rt_device_t dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) -{ - int i, addr; - struct dfs_partition *part = (struct dfs_partition *)dev->user_data; - - if (dev == RT_NULL) - { - rt_set_errno(-EINVAL); - - return 0; - } - - /* read all sectors */ - for (i = 0; i < size; i++) - { - rt_sem_take(part->lock, RT_WAITING_FOREVER); - if (sd_type == 1) - addr = (part->offset + i + pos)*SECTOR_SIZE; - else - addr = (part->offset + i + pos); - sd_writeblock(addr, (rt_uint8_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE)); - rt_sem_release(part->lock); - } - - /* the length of reading must align to SECTOR SIZE */ - return size; -} - -int rt_hw_sdcard_init(void) -{ - rt_uint8_t i, status; - rt_uint8_t *sector; - char dname[4]; - char sname[8]; - - /* Enable PCLK into SDI Block */ - CLKCON |= 1 << 9; - - /* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */ - GPEUP = GPEUP & (~(0x3f << 5)) | (0x01 << 5); - GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10); - - RCA = 0; - - if (sd_init() == RT_EOK) - { - /* get the first sector to read partition table */ - sector = (rt_uint8_t*) rt_malloc (512); - if (sector == RT_NULL) - { - rt_kprintf("allocate partition sector buffer failed\n"); - - return -RT_ERROR; - } - status = sd_readblock(0, sector); - if (status == RT_EOK) - { - for (i = 0; i < 4; i ++) - { - /* get the first partition */ - status = dfs_filesystem_get_partition(&part[i], sector, i); - if (status == RT_EOK) - { - rt_snprintf(dname, 4, "sd%d", i); - rt_snprintf(sname, 8, "sem_sd%d", i); - part[i].lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - - /* register sdcard device */ - sdcard_device[i].type = RT_Device_Class_Block; - sdcard_device[i].init = rt_sdcard_init; - sdcard_device[i].open = rt_sdcard_open; - sdcard_device[i].close = rt_sdcard_close; - sdcard_device[i].read = rt_sdcard_read; - sdcard_device[i].write = rt_sdcard_write; - sdcard_device[i].control = rt_sdcard_control; - sdcard_device[i].user_data = &part[i]; - - rt_device_register(&sdcard_device[i], dname, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - } - else - { - if (i == 0) - { - /* there is no partition table */ - part[0].offset = 0; - part[0].size = 0; - part[0].lock = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO); - - /* register sdcard device */ - sdcard_device[0].type = RT_Device_Class_Block; - sdcard_device[0].init = rt_sdcard_init; - sdcard_device[0].open = rt_sdcard_open; - sdcard_device[0].close = rt_sdcard_close; - sdcard_device[0].read = rt_sdcard_read; - sdcard_device[0].write = rt_sdcard_write; - sdcard_device[0].control = rt_sdcard_control; - sdcard_device[0].user_data = &part[0]; - - rt_device_register(&sdcard_device[0], "sd0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - - break; - } - } - } - } - else - { - rt_kprintf("read sdcard first sector failed\n"); - } - - /* release sector buffer */ - rt_free(sector); - - return -RT_ERROR; - } - else - { - rt_kprintf("sdcard init failed\n"); - } - - return RT_EOK; -} - -INIT_BOARD_EXPORT(rt_hw_sdcard_init); -#endif diff --git a/bsp/mini2440/drivers/sdcard.h b/bsp/mini2440/drivers/sdcard.h deleted file mode 100644 index f9aa52e818..0000000000 --- a/bsp/mini2440/drivers/sdcard.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __SDCARD_H -#define __SDCARD_H - -#include - -#define INICLK 300000 -#define SDCLK 24000000 //PCLK=49.392MHz -#define MMCCLK 15000000 //PCLK=49.392MHz - -#endif - diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c index e584c379e3..b2d09ff7a5 100644 --- a/bsp/mini2440/drivers/touch.c +++ b/bsp/mini2440/drivers/touch.c @@ -16,13 +16,14 @@ #include #include -#ifdef RT_USING_RTGUI +#ifdef PKG_USING_GUIENGINE #include #include #include #endif -#include "lcd.h" +#define TOUCH_SWAP_XY + #include "touch.h" /* ADCCON Register Bits */ @@ -108,7 +109,7 @@ struct rtgui_touch_device }; static struct rtgui_touch_device *touch = RT_NULL; -#ifdef RT_USING_RTGUI +#ifdef PKG_USING_GUIENGINE static void report_touch_input(int updown) { struct rtgui_event_mouse emouse; @@ -125,6 +126,12 @@ static void report_touch_input(int updown) ts.xp = ts.xp / ts.count; ts.yp = ts.yp / ts.count;; + #ifdef TOUCH_SWAP_XY + ts.xp = ts.xp + ts.yp; + ts.yp = ts.xp - ts.yp; + ts.xp = ts.xp - ts.yp; + #endif + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) { touch->x = ts.xp; @@ -446,7 +453,7 @@ static rt_err_t rtgui_touch_control(rt_device_t dev, int cmd, void *args) return RT_EOK; } -void rtgui_touch_hw_init(void) +int rtgui_touch_hw_init(void) { rt_err_t result = RT_FALSE; rt_device_t device = RT_NULL; @@ -454,7 +461,7 @@ void rtgui_touch_hw_init(void) touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device)); if (touch == RT_NULL) - return; /* no memory yet */ + return -RT_ERROR; /* no memory yet */ /* clear device structure */ rt_memset(&(touch->parent), 0, sizeof(struct rt_device)); @@ -473,17 +480,19 @@ void rtgui_touch_hw_init(void) touch->parent.user_data = RT_NULL; device = rt_device_find("lcd"); - if (device == RT_NULL) - return; /* no this device */ + if (device == RT_NULL) + { + rt_kprintf("No lcd found\n"); + return -RT_ERROR; /* no this device */ + } /* get graphic device info */ result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info); if (result != RT_EOK) { - /* get device information failed */ - - return; + rt_kprintf("Get graphic device info failed\n"); + return -RT_ERROR; } touch->width = info.width; @@ -495,4 +504,8 @@ void rtgui_touch_hw_init(void) /* register touch device to RT-Thread */ rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); + + return RT_EOK; } + +INIT_PREV_EXPORT(rtgui_touch_hw_init); diff --git a/bsp/mini2440/drivers/touch.h b/bsp/mini2440/drivers/touch.h index 854f274782..c0e1238148 100644 --- a/bsp/mini2440/drivers/touch.h +++ b/bsp/mini2440/drivers/touch.h @@ -26,7 +26,7 @@ typedef void (*rt_touch_calibration_func_t)(rt_uint16_t x, rt_uint16_t y); typedef void (*rt_touch_eventpost_func_t)(void *, struct rt_touch_event *); -void rtgui_touch_hw_init(void); +int rtgui_touch_hw_init(void); #endif diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h index 5d65b46148..37c215bdd0 100644 --- a/bsp/mini2440/rtconfig.h +++ b/bsp/mini2440/rtconfig.h @@ -107,6 +107,12 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 /* Using USB */ diff --git a/bsp/mini2440/rtconfig.py b/bsp/mini2440/rtconfig.py index 106597711a..f8332f1e6c 100644 --- a/bsp/mini2440/rtconfig.py +++ b/bsp/mini2440/rtconfig.py @@ -1,9 +1,5 @@ import os -# panel options -# 'PNL_A70','PNL_N35', 'PNL_T35' , 'PNL_X35' -RT_USING_LCD_TYPE = 'PNL_T35' - # toolchains options ARCH = 'arm' CPU = 's3c24x0' From 4b035622ce411ce53455eba96ba3d0835b3e2997 Mon Sep 17 00:00:00 2001 From: Jonne Date: Wed, 15 Apr 2020 21:03:43 +0800 Subject: [PATCH 03/27] 1. Modify the file indention 2. Modify the license head --- bsp/mini2440/applications/main.c | 14 +- bsp/mini2440/applications/mnt.c | 40 +- bsp/mini2440/drivers/SConscript | 2 +- bsp/mini2440/drivers/lcd_a70.c | 242 +++++------ bsp/mini2440/drivers/lcd_n35.c | 234 +++++----- bsp/mini2440/drivers/lcd_t35.c | 244 +++++------ bsp/mini2440/drivers/lcd_t43.c | 239 +++++----- bsp/mini2440/drivers/lcd_x35.c | 234 +++++----- bsp/mini2440/drivers/s3cmci.c | 9 +- bsp/mini2440/drivers/touch.c | 722 +++++++++++++++---------------- bsp/mini2440/drivers/touch.h | 16 +- 11 files changed, 993 insertions(+), 1003 deletions(-) diff --git a/bsp/mini2440/applications/main.c b/bsp/mini2440/applications/main.c index 923f014469..94a3f4ccea 100644 --- a/bsp/mini2440/applications/main.c +++ b/bsp/mini2440/applications/main.c @@ -11,16 +11,16 @@ int main(void) { - rt_device_t device; + rt_device_t device; - printf("hello rt-thread\n"); + printf("hello rt-thread\n"); #ifdef PKG_USING_GUIENGINE - device = rt_device_find("lcd"); - if (device) - { - rtgui_graphic_set_device(device); - } + device = rt_device_find("lcd"); + if (device) + { + rtgui_graphic_set_device(device); + } #endif diff --git a/bsp/mini2440/applications/mnt.c b/bsp/mini2440/applications/mnt.c index 2e1ae80692..14949abff4 100644 --- a/bsp/mini2440/applications/mnt.c +++ b/bsp/mini2440/applications/mnt.c @@ -6,29 +6,29 @@ int mnt_init(void) { - rt_uint32_t tryCnt = 5; - rt_device_t dev; + rt_uint32_t tryCnt = 5; + rt_device_t dev; - while(tryCnt--) - { - dev = rt_device_find("sd0"); - if(dev != RT_NULL) - { - break; - } - rt_thread_mdelay(500); - } + while(tryCnt--) + { + dev = rt_device_find("sd0"); + if(dev != RT_NULL) + { + break; + } + rt_thread_mdelay(500); + } - if(dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - { - rt_kprintf("File System initialzation failed!\n"); - } + if(dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + { + rt_kprintf("File System initialzation failed!\n"); + } - return RT_EOK; + return RT_EOK; } INIT_ENV_EXPORT(mnt_init); #endif diff --git a/bsp/mini2440/drivers/SConscript b/bsp/mini2440/drivers/SConscript index 902b48320d..2ea54187ed 100644 --- a/bsp/mini2440/drivers/SConscript +++ b/bsp/mini2440/drivers/SConscript @@ -27,7 +27,7 @@ if GetDepend('RT_MINI2440_LCD_X35'): src += ['lcd_x35.c'] if GetDepend('PKG_USING_GUIENGINE'): - src += ['touch.c'] + src += ['touch.c'] if GetDepend('RT_USING_SDIO'): src += ['s3cmci.c'] diff --git a/bsp/mini2440/drivers/lcd_a70.c b/bsp/mini2440/drivers/lcd_a70.c index 7ebcf6a047..5020012b2f 100644 --- a/bsp/mini2440/drivers/lcd_a70.c +++ b/bsp/mini2440/drivers/lcd_a70.c @@ -34,81 +34,81 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -127,123 +127,123 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1Ϊoutput - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0)) #endif - LCDCON5 = LCD_CON5; + LCDCON5 = LCD_CON5; - LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); - LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); - LCDSADDR3 = LCD_WIDTH; + LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); + LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); + LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } - return RT_EOK; + return RT_EOK; } int rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_n35.c b/bsp/mini2440/drivers/lcd_n35.c index 57d792ea39..1a3af23c09 100644 --- a/bsp/mini2440/drivers/lcd_n35.c +++ b/bsp/mini2440/drivers/lcd_n35.c @@ -34,82 +34,82 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -128,61 +128,61 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1Ϊoutput - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0)) #endif @@ -192,59 +192,59 @@ static rt_err_t rt_lcd_init (rt_device_t dev) LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } - return RT_EOK; + return RT_EOK; } int rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_t35.c b/bsp/mini2440/drivers/lcd_t35.c index fdcab887f5..c13a3c030f 100644 --- a/bsp/mini2440/drivers/lcd_t35.c +++ b/bsp/mini2440/drivers/lcd_t35.c @@ -34,82 +34,82 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -128,124 +128,124 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1Ϊoutput - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0)) #endif - LCDCON5 = LCD_CON5; + LCDCON5 = LCD_CON5; - LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); - LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); - LCDSADDR3 = LCD_WIDTH; + LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) << 0); + LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); + LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } - return RT_EOK; + return RT_EOK; } int rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) - return -RT_ERROR; /* no memory yet */ + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) + return -RT_ERROR; /* no memory yet */ - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_t43.c b/bsp/mini2440/drivers/lcd_t43.c index 54abc12f3e..42b22c36c2 100644 --- a/bsp/mini2440/drivers/lcd_t43.c +++ b/bsp/mini2440/drivers/lcd_t43.c @@ -1,17 +1,12 @@ /* - * File : lcd_t43.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2020-04-12 Jonne first version from 4.3 inch lcd(480x272) */ - #include #include @@ -36,79 +31,79 @@ #define RT_HW_LCD_WIDTH LCD_WIDTH #define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -127,61 +122,61 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = ((LCD_UPPER_MARGIN - 1) << 24) | ((LCD_HEIGHT - 1) << 14) | ((LCD_LOWER_MARGIN - 1) << 6) | ((LCD_VSYNC_LEN - 1) << 0); - LCDCON3 = ((LCD_RIGHT_MARGIN - 1) << 19) | ((LCD_WIDTH - 1) << 8) | ((LCD_LEFT_MARGIN - 1) << 0); - LCDCON4 = (13 << 8) | ((LCD_HSYNC_LEN - 1) << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = ((LCD_UPPER_MARGIN - 1) << 24) | ((LCD_HEIGHT - 1) << 14) | ((LCD_LOWER_MARGIN - 1) << 6) | ((LCD_VSYNC_LEN - 1) << 0); + LCDCON3 = ((LCD_RIGHT_MARGIN - 1) << 19) | ((LCD_WIDTH - 1) << 8) | ((LCD_LEFT_MARGIN - 1) << 0); + LCDCON4 = (13 << 8) | ((LCD_HSYNC_LEN - 1) << 0); #if !defined(LCD_CON5) #define LCD_CON5 ((1<<11) | (0<<10) | (1<<9) | (1<<8) | (1<<0)) #endif @@ -191,59 +186,59 @@ static rt_err_t rt_lcd_init (rt_device_t dev) LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } - return RT_EOK; + return RT_EOK; } int rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/lcd_x35.c b/bsp/mini2440/drivers/lcd_x35.c index e625905130..b4a8fda23c 100644 --- a/bsp/mini2440/drivers/lcd_x35.c +++ b/bsp/mini2440/drivers/lcd_x35.c @@ -36,82 +36,82 @@ #define SCR_XSIZE LCD_WIDTH #define SCR_YSIZE LCD_HEIGHT -#define RT_HW_LCD_WIDTH LCD_WIDTH -#define RT_HW_LCD_HEIGHT LCD_HEIGHT +#define RT_HW_LCD_WIDTH LCD_WIDTH +#define RT_HW_LCD_HEIGHT LCD_HEIGHT -#define MVAL (13) -#define MVAL_USED (0) //0=each frame 1=rate by MVAL -#define INVVDEN (1) //0=normal 1=inverted -#define BSWP (0) //Byte swap control -#define HWSWP (1) //Half word swap control +#define MVAL (13) +#define MVAL_USED (0) //0=each frame 1=rate by MVAL +#define INVVDEN (1) //0=normal 1=inverted +#define BSWP (0) //Byte swap control +#define HWSWP (1) //Half word swap control -#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) -#define GPB1_TO_1() (GPBDAT |= 0x0002) -#define GPB1_TO_0() (GPBDAT &= 0xfffd) +#define GPB1_TO_OUT() (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004) +#define GPB1_TO_1() (GPBDAT |= 0x0002) +#define GPB1_TO_0() (GPBDAT &= 0xfffd) #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) +#define S3C2410_LCDCON1_MMODE (1<<7) +#define S3C2410_LCDCON1_DSCAN4 (0<<5) +#define S3C2410_LCDCON1_STN4 (1<<5) +#define S3C2410_LCDCON1_STN8 (2<<5) +#define S3C2410_LCDCON1_TFT (3<<5) -#define S3C2410_LCDCON1_STN1BPP (0<<1) +#define S3C2410_LCDCON1_STN1BPP (0<<1) #define S3C2410_LCDCON1_STN2GREY (1<<1) #define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) +#define S3C2410_LCDCON1_STN8BPP (3<<1) #define S3C2410_LCDCON1_STN12BPP (4<<1) -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) +#define S3C2410_LCDCON1_TFT1BPP (8<<1) +#define S3C2410_LCDCON1_TFT2BPP (9<<1) +#define S3C2410_LCDCON1_TFT4BPP (10<<1) +#define S3C2410_LCDCON1_TFT8BPP (11<<1) #define S3C2410_LCDCON1_TFT16BPP (12<<1) #define S3C2410_LCDCON1_TFT24BPP (13<<1) -#define S3C2410_LCDCON1_ENVID (1) +#define S3C2410_LCDCON1_ENVID (1) #define S3C2410_LCDCON1_MODEMASK 0x1E -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) +#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) +#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) +#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) +#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) +#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) +#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) +#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) +#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) +#define S3C2410_LCDCON4_WLH(x) ((x) << 0) #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) +#define S3C2410_LCDCON5_BPP24BL (1<<12) +#define S3C2410_LCDCON5_FRM565 (1<<11) +#define S3C2410_LCDCON5_INVVCLK (1<<10) #define S3C2410_LCDCON5_INVVLINE (1<<9) #define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) +#define S3C2410_LCDCON5_INVVD (1<<7) +#define S3C2410_LCDCON5_INVVDEN (1<<6) #define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) +#define S3C2410_LCDCON5_INVLEND (1<<4) +#define S3C2410_LCDCON5_PWREN (1<<3) +#define S3C2410_LCDCON5_ENLEND (1<<2) +#define S3C2410_LCDCON5_BSWP (1<<1) +#define S3C2410_LCDCON5_HWSWP (1<<0) -#define S3C2410_LCDINT_FRSYNC (1<<1) +#define S3C2410_LCDINT_FRSYNC (1<<1) static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH]; @@ -130,61 +130,61 @@ static void lcd_power_enable(int invpwren, int pwren) static void lcd_envid_on_off(int onoff) { - if(onoff==1) - /*ENVID=ON*/ - LCDCON1|=1; - else - /*ENVID Off*/ - LCDCON1 =LCDCON1 & 0x3fffe; + if(onoff==1) + /*ENVID=ON*/ + LCDCON1|=1; + else + /*ENVID Off*/ + LCDCON1 =LCDCON1 & 0x3fffe; } //********************** BOARD LCD backlight **************************** static void LcdBkLtSet(rt_uint32_t HiRatio) { -#define FREQ_PWM1 1000 - if(!HiRatio) - { - GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; //GPB1Ϊoutput - GPBDAT &= ~(1<<1); - return; - } - GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; +#define FREQ_PWM1 1000 + if(!HiRatio) + { + GPBCON = GPBCON & (~(3<<2)) | (1<<2) ; + GPBDAT &= ~(1<<1); + return; + } + GPBCON = GPBCON & (~(3<<2)) | (2<<2) ; - if( HiRatio > 100 ) HiRatio = 100 ; + if( HiRatio > 100 ) HiRatio = 100 ; - TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 + TCON = TCON & (~(0xf<<8)) ; // clear manual update bit, stop Timer1 - TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 - TCFG0 |= 15; //prescaler = 15+1 + TCFG0 &= 0xffffff00; // set Timer 0&1 prescaler 0 + TCFG0 |= 15; //prescaler = 15+1 - TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 - TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 + TCFG1 &= 0xffffff0f; // set Timer 1 MUX 1/16 + TCFG1 |= 0x00000030; // set Timer 1 MUX 1/16 - TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low - TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high + TCNTB1 = ( 100000000>>8 )/FREQ_PWM1; //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low + TCMPB1 = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on, when TCNT2<=TCMP2, TOUT is low, TCNT2>TCMP2, TOUT is high - TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; - TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ; + TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ; } /* RT-Thread Device Interface */ static rt_err_t rt_lcd_init (rt_device_t dev) -{ - GPB1_TO_OUT(); - GPB1_TO_1(); +{ + GPB1_TO_OUT(); + GPB1_TO_1(); - GPCUP = 0x00000000; - GPCCON = 0xaaaa02a9; + GPCUP = 0x00000000; + GPCCON = 0xaaaa02a9; - GPDUP = 0x00000000; - GPDCON = 0xaaaaaaaa; + GPDUP = 0x00000000; + GPDCON = 0xaaaaaaaa; -#define M5D(n) ((n)&0x1fffff) +#define M5D(n) ((n)&0x1fffff) #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer) - LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); - LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); - LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); - LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); + LCDCON1 = (LCD_PIXCLOCK << 8) | (3 << 5) | (12 << 1); + LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0); + LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH - 1) << 8) | (LCD_LEFT_MARGIN << 0); + LCDCON4 = (13 << 8) | (LCD_HSYNC_LEN << 0); #define LCD_CON5 (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_INVVDEN | S3C2410_LCDCON5_INVVFRAME | \ S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2410_LCDCON5_HWSWP) @@ -198,59 +198,59 @@ S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2 LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1); LCDSADDR3 = LCD_WIDTH; - LCDINTMSK |= (3); - LPCSEL &= (~7) ; - TPAL=0; + LCDINTMSK |= (3); + LPCSEL &= (~7) ; + TPAL=0; - LcdBkLtSet(70) ; - lcd_power_enable(0, 1); - lcd_envid_on_off(1); + LcdBkLtSet(70) ; + lcd_power_enable(0, 1); + lcd_envid_on_off(1); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } - return RT_EOK; + return RT_EOK; } int rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return -RT_ERROR; /* no memory yet */ - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; - lcd->user_data = (void*)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; + lcd->user_data = (void*)&_lcd_info; + + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/mini2440/drivers/s3cmci.c b/bsp/mini2440/drivers/s3cmci.c index 2333c74495..b5b6f58414 100644 --- a/bsp/mini2440/drivers/s3cmci.c +++ b/bsp/mini2440/drivers/s3cmci.c @@ -1,17 +1,12 @@ /* - * File : s3cmci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2020-04-15 Jonne first version for s3c2440 mmc controller */ - #include #include #include diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c index b2d09ff7a5..404169a43f 100644 --- a/bsp/mini2440/drivers/touch.c +++ b/bsp/mini2440/drivers/touch.c @@ -27,485 +27,485 @@ #include "touch.h" /* ADCCON Register Bits */ -#define S3C2410_ADCCON_ECFLG (1<<15) -#define S3C2410_ADCCON_PRSCEN (1<<14) -#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) -#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) -#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) -#define S3C2410_ADCCON_MUXMASK (0x7<<3) -#define S3C2410_ADCCON_STDBM (1<<2) -#define S3C2410_ADCCON_READ_START (1<<1) -#define S3C2410_ADCCON_ENABLE_START (1<<0) -#define S3C2410_ADCCON_STARTMASK (0x3<<0) +#define S3C2410_ADCCON_ECFLG (1<<15) +#define S3C2410_ADCCON_PRSCEN (1<<14) +#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C2410_ADCCON_MUXMASK (0x7<<3) +#define S3C2410_ADCCON_STDBM (1<<2) +#define S3C2410_ADCCON_READ_START (1<<1) +#define S3C2410_ADCCON_ENABLE_START (1<<0) +#define S3C2410_ADCCON_STARTMASK (0x3<<0) /* ADCTSC Register Bits */ -#define S3C2410_ADCTSC_UD_SEN (1<<8) /* ghcstop add for s3c2440a */ -#define S3C2410_ADCTSC_YM_SEN (1<<7) -#define S3C2410_ADCTSC_YP_SEN (1<<6) -#define S3C2410_ADCTSC_XM_SEN (1<<5) -#define S3C2410_ADCTSC_XP_SEN (1<<4) -#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) -#define S3C2410_ADCTSC_AUTO_PST (1<<2) -#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) +#define S3C2410_ADCTSC_UD_SEN (1<<8) /* ghcstop add for s3c2440a */ +#define S3C2410_ADCTSC_YM_SEN (1<<7) +#define S3C2410_ADCTSC_YP_SEN (1<<6) +#define S3C2410_ADCTSC_XM_SEN (1<<5) +#define S3C2410_ADCTSC_XP_SEN (1<<4) +#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C2410_ADCTSC_AUTO_PST (1<<2) +#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) /* ADCDAT0 Bits */ -#define S3C2410_ADCDAT0_UPDOWN (1<<15) -#define S3C2410_ADCDAT0_AUTO_PST (1<<14) -#define S3C2410_ADCDAT0_XY_PST (0x3<<12) -#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) +#define S3C2410_ADCDAT0_UPDOWN (1<<15) +#define S3C2410_ADCDAT0_AUTO_PST (1<<14) +#define S3C2410_ADCDAT0_XY_PST (0x3<<12) +#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) /* ADCDAT1 Bits */ -#define S3C2410_ADCDAT1_UPDOWN (1<<15) -#define S3C2410_ADCDAT1_AUTO_PST (1<<14) -#define S3C2410_ADCDAT1_XY_PST (0x3<<12) -#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) +#define S3C2410_ADCDAT1_UPDOWN (1<<15) +#define S3C2410_ADCDAT1_AUTO_PST (1<<14) +#define S3C2410_ADCDAT1_XY_PST (0x3<<12) +#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) #define WAIT4INT(x) (((x)<<8) | \ - S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ - S3C2410_ADCTSC_XY_PST(3)) + S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ + S3C2410_ADCTSC_XY_PST(3)) -#define AUTOPST (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ - S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0)) +#define AUTOPST (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \ + S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0)) -#define X_MIN 74 -#define X_MAX 934 -#define Y_MIN 920 -#define Y_MAX 89 +#define X_MIN 74 +#define X_MAX 934 +#define Y_MIN 920 +#define Y_MAX 89 struct s3c2410ts { - long xp; - long yp; - int count; - int shift; + long xp; + long yp; + int count; + int shift; - int delay; - int presc; + int delay; + int presc; - char phys[32]; + char phys[32]; }; static struct s3c2410ts ts; struct rtgui_touch_device { - struct rt_device parent; + struct rt_device parent; - rt_timer_t poll_timer; - rt_uint16_t x, y; + rt_timer_t poll_timer; + rt_uint16_t x, y; - rt_bool_t calibrating; - rt_touch_calibration_func_t calibration_func; + rt_bool_t calibrating; + rt_touch_calibration_func_t calibration_func; - rt_touch_eventpost_func_t eventpost_func; - void *eventpost_param; + rt_touch_eventpost_func_t eventpost_func; + void *eventpost_param; - rt_uint16_t min_x, max_x; - rt_uint16_t min_y, max_y; + rt_uint16_t min_x, max_x; + rt_uint16_t min_y, max_y; - rt_uint16_t width; - rt_uint16_t height; - - rt_bool_t first_down_report; + rt_uint16_t width; + rt_uint16_t height; + + rt_bool_t first_down_report; }; static struct rtgui_touch_device *touch = RT_NULL; #ifdef PKG_USING_GUIENGINE static void report_touch_input(int updown) { - struct rtgui_event_mouse emouse; + struct rtgui_event_mouse emouse; - RTGUI_EVENT_MOUSE_BUTTON_INIT(&emouse); - emouse.wid = RT_NULL; + RTGUI_EVENT_MOUSE_BUTTON_INIT(&emouse); + emouse.wid = RT_NULL; - /* set emouse button */ - emouse.button = RTGUI_MOUSE_BUTTON_LEFT; - emouse.parent.sender = RT_NULL; - - if (updown) - { - ts.xp = ts.xp / ts.count; - ts.yp = ts.yp / ts.count;; + /* set emouse button */ + emouse.button = RTGUI_MOUSE_BUTTON_LEFT; + emouse.parent.sender = RT_NULL; + + if (updown) + { + ts.xp = ts.xp / ts.count; + ts.yp = ts.yp / ts.count;; - #ifdef TOUCH_SWAP_XY - ts.xp = ts.xp + ts.yp; - ts.yp = ts.xp - ts.yp; - ts.xp = ts.xp - ts.yp; - #endif + #ifdef TOUCH_SWAP_XY + ts.xp = ts.xp + ts.yp; + ts.yp = ts.xp - ts.yp; + ts.xp = ts.xp - ts.yp; + #endif - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - touch->x = ts.xp; - touch->y = ts.yp; - } - else - { - if (touch->max_x > touch->min_x) - { - touch->x = touch->width * (ts.xp-touch->min_x)/(touch->max_x-touch->min_x); - } - else - { - touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); - } + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + touch->x = ts.xp; + touch->y = ts.yp; + } + else + { + if (touch->max_x > touch->min_x) + { + touch->x = touch->width * (ts.xp-touch->min_x)/(touch->max_x-touch->min_x); + } + else + { + touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); + } - if (touch->max_y > touch->min_y) - { - touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); - } - else - { - touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); - } - } + if (touch->max_y > touch->min_y) + { + touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); + } + else + { + touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); + } + } - emouse.x = touch->x; - emouse.y = touch->y; - if (touch->first_down_report == RT_TRUE) - { - emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; - emouse.button |= RTGUI_MOUSE_BUTTON_DOWN; - } - else - { - emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; - emouse.button = 0; - } - } - else - { - emouse.x = touch->x; - emouse.y = touch->y; - emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; - emouse.button |= RTGUI_MOUSE_BUTTON_UP; - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - /* callback function */ - touch->calibration_func(emouse.x, emouse.y); - } - } + emouse.x = touch->x; + emouse.y = touch->y; + if (touch->first_down_report == RT_TRUE) + { + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button |= RTGUI_MOUSE_BUTTON_DOWN; + } + else + { + emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; + emouse.button = 0; + } + } + else + { + emouse.x = touch->x; + emouse.y = touch->y; + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button |= RTGUI_MOUSE_BUTTON_UP; + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + /* callback function */ + touch->calibration_func(emouse.x, emouse.y); + } + } - /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up", - touch->x, touch->y); */ - - /* send event to server */ - if (touch->calibrating != RT_TRUE) - { - rtgui_server_post_event((&emouse.parent), sizeof(emouse)); - } + /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up", + touch->x, touch->y); */ + + /* send event to server */ + if (touch->calibrating != RT_TRUE) + { + rtgui_server_post_event((&emouse.parent), sizeof(emouse)); + } } #else static void report_touch_input(int updown) { - struct rt_touch_event touch_event; + struct rt_touch_event touch_event; - if (updown) - { - ts.xp = ts.xp / ts.count; - ts.yp = ts.yp / ts.count; + if (updown) + { + ts.xp = ts.xp / ts.count; + ts.yp = ts.yp / ts.count; - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - touch->x = ts.xp; - touch->y = ts.yp; - } - else - { - if (touch->max_x > touch->min_x) - { - touch->x = touch->width * ( ts.xp - touch->min_x ) / (touch->max_x-touch->min_x); - } - else - { - touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); - } + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + touch->x = ts.xp; + touch->y = ts.yp; + } + else + { + if (touch->max_x > touch->min_x) + { + touch->x = touch->width * ( ts.xp - touch->min_x ) / (touch->max_x-touch->min_x); + } + else + { + touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x); + } - if (touch->max_y > touch->min_y) - { - touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); - } - else - { - touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); - } - } + if (touch->max_y > touch->min_y) + { + touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y); + } + else + { + touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y); + } + } - touch_event.x = touch->x; - touch_event.y = touch->y; - touch_event.pressed = 1; + touch_event.x = touch->x; + touch_event.y = touch->y; + touch_event.pressed = 1; - if (touch->first_down_report == RT_TRUE) - { - if (touch->calibrating != RT_TRUE && touch->eventpost_func) - { - touch->eventpost_func(touch->eventpost_param, &touch_event); - } - } - } - else - { - touch_event.x = touch->x; - touch_event.y = touch->y; - touch_event.pressed = 0; - - if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) - { - /* callback function */ - touch->calibration_func(touch_event.x, touch_event.y); - } + if (touch->first_down_report == RT_TRUE) + { + if (touch->calibrating != RT_TRUE && touch->eventpost_func) + { + touch->eventpost_func(touch->eventpost_param, &touch_event); + } + } + } + else + { + touch_event.x = touch->x; + touch_event.y = touch->y; + touch_event.pressed = 0; + + if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) + { + /* callback function */ + touch->calibration_func(touch_event.x, touch_event.y); + } - if (touch->calibrating != RT_TRUE && touch->eventpost_func) - { - touch->eventpost_func(touch->eventpost_param, &touch_event); - } - } + if (touch->calibrating != RT_TRUE && touch->eventpost_func) + { + touch->eventpost_func(touch->eventpost_param, &touch_event); + } + } } #endif static void touch_timer_fire(void *parameter) { - rt_uint32_t data0; - rt_uint32_t data1; - int updown; + rt_uint32_t data0; + rt_uint32_t data1; + int updown; - data0 = ADCDAT0; - data1 = ADCDAT1; + data0 = ADCDAT0; + data1 = ADCDAT1; - updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); + updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); - if (updown) - { - if (ts.count != 0) - { - report_touch_input(updown); - } + if (updown) + { + if (ts.count != 0) + { + report_touch_input(updown); + } - ts.xp = 0; - ts.yp = 0; - ts.count = 0; + ts.xp = 0; + ts.yp = 0; + ts.count = 0; - ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST; - ADCCON |= S3C2410_ADCCON_ENABLE_START; - } + ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST; + ADCCON |= S3C2410_ADCCON_ENABLE_START; + } } static void s3c2410_adc_stylus_action(void) { - rt_uint32_t data0; - rt_uint32_t data1; + rt_uint32_t data0; + rt_uint32_t data1; - data0 = ADCDAT0; - data1 = ADCDAT1; - - ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK; - ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK; - ts.count ++; + data0 = ADCDAT0; + data1 = ADCDAT1; + + ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK; + ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK; + ts.count ++; - if (ts.count < (1<first_down_report) - { - report_touch_input(1); - ts.xp = 0; - ts.yp = 0; - ts.count = 0; - touch->first_down_report = 0; - } - /* start timer */ - rt_timer_start(touch->poll_timer); - ADCTSC = WAIT4INT(1); - } + if (ts.count < (1<first_down_report) + { + report_touch_input(1); + ts.xp = 0; + ts.yp = 0; + ts.count = 0; + touch->first_down_report = 0; + } + /* start timer */ + rt_timer_start(touch->poll_timer); + ADCTSC = WAIT4INT(1); + } - SUBSRCPND |= BIT_SUB_ADC; + SUBSRCPND |= BIT_SUB_ADC; } static void s3c2410_intc_stylus_updown(void) { - rt_uint32_t data0; - rt_uint32_t data1; - int updown; + rt_uint32_t data0; + rt_uint32_t data1; + int updown; - data0 = ADCDAT0; - data1 = ADCDAT1; + data0 = ADCDAT0; + data1 = ADCDAT1; - updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); + updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN)); - /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */ + /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */ - if (updown) - { - touch_timer_fire(0); - } - else - { - /* stop timer */ - rt_timer_stop(touch->poll_timer); - touch->first_down_report = RT_TRUE; - if (ts.xp >= 0 && ts.yp >= 0) - { - report_touch_input(updown); - } - ts.count = 0; - ADCTSC = WAIT4INT(0); - } + if (updown) + { + touch_timer_fire(0); + } + else + { + /* stop timer */ + rt_timer_stop(touch->poll_timer); + touch->first_down_report = RT_TRUE; + if (ts.xp >= 0 && ts.yp >= 0) + { + report_touch_input(updown); + } + ts.count = 0; + ADCTSC = WAIT4INT(0); + } - SUBSRCPND |= BIT_SUB_TC; + SUBSRCPND |= BIT_SUB_TC; } static void rt_touch_handler(int irqno, void *param) { - if (SUBSRCPND & BIT_SUB_ADC) - { - /* INT_SUB_ADC */ - s3c2410_adc_stylus_action(); - } + if (SUBSRCPND & BIT_SUB_ADC) + { + /* INT_SUB_ADC */ + s3c2410_adc_stylus_action(); + } - if (SUBSRCPND & BIT_SUB_TC) - { - /* INT_SUB_TC */ - s3c2410_intc_stylus_updown(); - } + if (SUBSRCPND & BIT_SUB_TC) + { + /* INT_SUB_TC */ + s3c2410_intc_stylus_updown(); + } - /* clear interrupt */ - INTPND |= (1ul << INTADC); + /* clear interrupt */ + INTPND |= (1ul << INTADC); } /* RT-Thread Device Interface */ static rt_err_t rtgui_touch_init(rt_device_t dev) { - /* init touch screen structure */ - rt_memset(&ts, 0, sizeof(struct s3c2410ts)); + /* init touch screen structure */ + rt_memset(&ts, 0, sizeof(struct s3c2410ts)); - ts.delay = 50000; - ts.presc = 9; - ts.shift = 2; - ts.count = 0; - ts.xp = ts.yp = 0; + ts.delay = 50000; + ts.presc = 9; + ts.shift = 2; + ts.count = 0; + ts.xp = ts.yp = 0; - ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc); - ADCDLY = ts.delay; + ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc); + ADCDLY = ts.delay; - ADCTSC = WAIT4INT(0); + ADCTSC = WAIT4INT(0); - rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL , "INTADC"); - rt_hw_interrupt_umask(INTADC); + rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL , "INTADC"); + rt_hw_interrupt_umask(INTADC); - /* clear interrupt */ - INTPND |= (1ul << INTADC); + /* clear interrupt */ + INTPND |= (1ul << INTADC); - SUBSRCPND |= BIT_SUB_TC; - SUBSRCPND |= BIT_SUB_ADC; + SUBSRCPND |= BIT_SUB_TC; + SUBSRCPND |= BIT_SUB_ADC; - /* install interrupt handler */ - INTSUBMSK &= ~BIT_SUB_ADC; - INTSUBMSK &= ~BIT_SUB_TC; + /* install interrupt handler */ + INTSUBMSK &= ~BIT_SUB_ADC; + INTSUBMSK &= ~BIT_SUB_TC; - touch->first_down_report = RT_TRUE; + touch->first_down_report = RT_TRUE; - return RT_EOK; + return RT_EOK; } static rt_err_t rtgui_touch_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RT_TOUCH_CALIBRATION: - touch->calibrating = RT_TRUE; - touch->calibration_func = (rt_touch_calibration_func_t)args; - break; + switch (cmd) + { + case RT_TOUCH_CALIBRATION: + touch->calibrating = RT_TRUE; + touch->calibration_func = (rt_touch_calibration_func_t)args; + break; - case RT_TOUCH_NORMAL: - touch->calibrating = RT_FALSE; - break; + case RT_TOUCH_NORMAL: + touch->calibrating = RT_FALSE; + break; - case RT_TOUCH_CALIBRATION_DATA: - { - struct calibration_data *data; + case RT_TOUCH_CALIBRATION_DATA: + { + struct calibration_data *data; - data = (struct calibration_data *)args; + data = (struct calibration_data *)args; - /* update */ - touch->min_x = data->min_x; - touch->max_x = data->max_x; - touch->min_y = data->min_y; - touch->max_y = data->max_y; + /* update */ + touch->min_x = data->min_x; + touch->max_x = data->max_x; + touch->min_y = data->min_y; + touch->max_y = data->max_y; - /* - rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n", - touch->min_x, touch->max_x, touch->min_y, touch->max_y); - */ - } - break; + /* + rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n", + touch->min_x, touch->max_x, touch->min_y, touch->max_y); + */ + } + break; - case RT_TOUCH_EVENTPOST: - touch->eventpost_func = (rt_touch_eventpost_func_t)args; - break; + case RT_TOUCH_EVENTPOST: + touch->eventpost_func = (rt_touch_eventpost_func_t)args; + break; - case RT_TOUCH_EVENTPOST_PARAM: - touch->eventpost_param = args; - break; - } + case RT_TOUCH_EVENTPOST_PARAM: + touch->eventpost_param = args; + break; + } - return RT_EOK; + return RT_EOK; } int rtgui_touch_hw_init(void) { - rt_err_t result = RT_FALSE; - rt_device_t device = RT_NULL; - struct rt_device_graphic_info info; + rt_err_t result = RT_FALSE; + rt_device_t device = RT_NULL; + struct rt_device_graphic_info info; - touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device)); - if (touch == RT_NULL) - return -RT_ERROR; /* no memory yet */ + touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device)); + if (touch == RT_NULL) + return -RT_ERROR; /* no memory yet */ - /* clear device structure */ - rt_memset(&(touch->parent), 0, sizeof(struct rt_device)); - touch->calibrating = RT_FALSE; - touch->min_x = X_MIN; - touch->max_x = X_MAX; - touch->min_y = Y_MIN; - touch->max_y = Y_MAX; - touch->eventpost_func = RT_NULL; - touch->eventpost_param = RT_NULL; + /* clear device structure */ + rt_memset(&(touch->parent), 0, sizeof(struct rt_device)); + touch->calibrating = RT_FALSE; + touch->min_x = X_MIN; + touch->max_x = X_MAX; + touch->min_y = Y_MIN; + touch->max_y = Y_MAX; + touch->eventpost_func = RT_NULL; + touch->eventpost_param = RT_NULL; - /* init device structure */ - touch->parent.type = RT_Device_Class_Unknown; - touch->parent.init = rtgui_touch_init; - touch->parent.control = rtgui_touch_control; - touch->parent.user_data = RT_NULL; + /* init device structure */ + touch->parent.type = RT_Device_Class_Unknown; + touch->parent.init = rtgui_touch_init; + touch->parent.control = rtgui_touch_control; + touch->parent.user_data = RT_NULL; - device = rt_device_find("lcd"); - if (device == RT_NULL) - { - rt_kprintf("No lcd found\n"); - return -RT_ERROR; /* no this device */ - } + device = rt_device_find("lcd"); + if (device == RT_NULL) + { + rt_kprintf("No lcd found\n"); + return -RT_ERROR; /* no this device */ + } - /* get graphic device info */ - result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info); - if (result != RT_EOK) - { - /* get device information failed */ - rt_kprintf("Get graphic device info failed\n"); - return -RT_ERROR; - } + /* get graphic device info */ + result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info); + if (result != RT_EOK) + { + /* get device information failed */ + rt_kprintf("Get graphic device info failed\n"); + return -RT_ERROR; + } - touch->width = info.width; - touch->height = info.height; - - /* create 1/8 second timer */ - touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL, - RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC); + touch->width = info.width; + touch->height = info.height; + + /* create 1/8 second timer */ + touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL, + RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC); - /* register touch device to RT-Thread */ - rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); + /* register touch device to RT-Thread */ + rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); - return RT_EOK; + return RT_EOK; } INIT_PREV_EXPORT(rtgui_touch_hw_init); diff --git a/bsp/mini2440/drivers/touch.h b/bsp/mini2440/drivers/touch.h index c0e1238148..19d10bf36d 100644 --- a/bsp/mini2440/drivers/touch.h +++ b/bsp/mini2440/drivers/touch.h @@ -3,23 +3,23 @@ #include -#define RT_TOUCH_NORMAL 0 -#define RT_TOUCH_CALIBRATION_DATA 1 -#define RT_TOUCH_CALIBRATION 2 +#define RT_TOUCH_NORMAL 0 +#define RT_TOUCH_CALIBRATION_DATA 1 +#define RT_TOUCH_CALIBRATION 2 #define RT_TOUCH_EVENTPOST 3 #define RT_TOUCH_EVENTPOST_PARAM 4 struct calibration_data { - rt_uint16_t min_x, max_x; - rt_uint16_t min_y, max_y; + rt_uint16_t min_x, max_x; + rt_uint16_t min_y, max_y; }; struct rt_touch_event { - rt_uint16_t x; - rt_uint16_t y; - int pressed; + rt_uint16_t x; + rt_uint16_t y; + int pressed; }; typedef void (*rt_touch_calibration_func_t)(rt_uint16_t x, rt_uint16_t y); From fb8c7829a8a861f9837912ecf926899f48349967 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Thu, 16 Apr 2020 16:10:57 +0800 Subject: [PATCH 04/27] add raspi4 bsp --- bsp/raspberry-pi/raspi4/.config | 455 ++++++++++++++++++ bsp/raspberry-pi/raspi4/Kconfig | 29 ++ bsp/raspberry-pi/raspi4/README.md | 100 ++++ bsp/raspberry-pi/raspi4/SConscript | 14 + bsp/raspberry-pi/raspi4/SConstruct | 30 ++ .../raspi4/applications/SConscript | 9 + bsp/raspberry-pi/raspi4/applications/main.c | 19 + bsp/raspberry-pi/raspi4/driver/Kconfig | 97 ++++ bsp/raspberry-pi/raspi4/driver/SConscript | 9 + bsp/raspberry-pi/raspi4/driver/board.c | 98 ++++ bsp/raspberry-pi/raspi4/driver/board.h | 25 + bsp/raspberry-pi/raspi4/driver/drv_gpio.c | 117 +++++ bsp/raspberry-pi/raspi4/driver/drv_gpio.h | 79 +++ bsp/raspberry-pi/raspi4/driver/drv_uart.c | 158 ++++++ bsp/raspberry-pi/raspi4/driver/drv_uart.h | 84 ++++ bsp/raspberry-pi/raspi4/driver/iomap.h | 13 + bsp/raspberry-pi/raspi4/link.lds | 153 ++++++ bsp/raspberry-pi/raspi4/rtconfig.h | 179 +++++++ bsp/raspberry-pi/raspi4/rtconfig.py | 51 ++ libcpu/aarch64/SConscript | 3 + libcpu/aarch64/common/SConscript | 24 + libcpu/aarch64/{cortex-a53 => common}/armv8.h | 0 libcpu/aarch64/{cortex-a53 => common}/cache.S | 0 .../{cortex-a53 => common}/context_gcc.S | 0 libcpu/aarch64/{cortex-a53 => common}/cp15.h | 0 libcpu/aarch64/{cortex-a53 => common}/cpu.c | 0 .../aarch64/{cortex-a53 => common}/cpu_gcc.S | 0 libcpu/aarch64/common/gic/SConscript | 24 + libcpu/aarch64/common/gic/gic_pl400.c | 368 ++++++++++++++ libcpu/aarch64/common/gic/gic_pl400.h | 35 ++ libcpu/aarch64/{cortex-a53 => common}/mmu.c | 0 libcpu/aarch64/{cortex-a53 => common}/mmu.h | 0 .../{cortex-a53 => common}/startup_gcc.S | 0 .../{cortex-a53 => common}/vector_gcc.S | 0 libcpu/aarch64/cortex-a53/SConscript | 15 +- libcpu/aarch64/cortex-a53/interrupt.h | 6 +- libcpu/aarch64/cortex-a57/SConscript | 13 + libcpu/aarch64/cortex-a57/entry_point.S | 111 +++++ libcpu/aarch64/cortex-a57/interrupt.c | 73 +++ libcpu/aarch64/cortex-a57/interrupt.h | 27 ++ libcpu/aarch64/cortex-a57/stack.c | 90 ++++ libcpu/aarch64/cortex-a57/trap.c | 98 ++++ 42 files changed, 2593 insertions(+), 13 deletions(-) create mode 100644 bsp/raspberry-pi/raspi4/.config create mode 100644 bsp/raspberry-pi/raspi4/Kconfig create mode 100644 bsp/raspberry-pi/raspi4/README.md create mode 100644 bsp/raspberry-pi/raspi4/SConscript create mode 100644 bsp/raspberry-pi/raspi4/SConstruct create mode 100644 bsp/raspberry-pi/raspi4/applications/SConscript create mode 100644 bsp/raspberry-pi/raspi4/applications/main.c create mode 100644 bsp/raspberry-pi/raspi4/driver/Kconfig create mode 100644 bsp/raspberry-pi/raspi4/driver/SConscript create mode 100644 bsp/raspberry-pi/raspi4/driver/board.c create mode 100644 bsp/raspberry-pi/raspi4/driver/board.h create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.c create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.h create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.c create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.h create mode 100644 bsp/raspberry-pi/raspi4/driver/iomap.h create mode 100644 bsp/raspberry-pi/raspi4/link.lds create mode 100644 bsp/raspberry-pi/raspi4/rtconfig.h create mode 100644 bsp/raspberry-pi/raspi4/rtconfig.py create mode 100644 libcpu/aarch64/common/SConscript rename libcpu/aarch64/{cortex-a53 => common}/armv8.h (100%) rename libcpu/aarch64/{cortex-a53 => common}/cache.S (100%) rename libcpu/aarch64/{cortex-a53 => common}/context_gcc.S (100%) rename libcpu/aarch64/{cortex-a53 => common}/cp15.h (100%) rename libcpu/aarch64/{cortex-a53 => common}/cpu.c (100%) rename libcpu/aarch64/{cortex-a53 => common}/cpu_gcc.S (100%) create mode 100644 libcpu/aarch64/common/gic/SConscript create mode 100644 libcpu/aarch64/common/gic/gic_pl400.c create mode 100644 libcpu/aarch64/common/gic/gic_pl400.h rename libcpu/aarch64/{cortex-a53 => common}/mmu.c (100%) rename libcpu/aarch64/{cortex-a53 => common}/mmu.h (100%) rename libcpu/aarch64/{cortex-a53 => common}/startup_gcc.S (100%) rename libcpu/aarch64/{cortex-a53 => common}/vector_gcc.S (100%) create mode 100644 libcpu/aarch64/cortex-a57/SConscript create mode 100644 libcpu/aarch64/cortex-a57/entry_point.S create mode 100644 libcpu/aarch64/cortex-a57/interrupt.c create mode 100644 libcpu/aarch64/cortex-a57/interrupt.h create mode 100644 libcpu/aarch64/cortex-a57/stack.c create mode 100644 libcpu/aarch64/cortex-a57/trap.c diff --git a/bsp/raspberry-pi/raspi4/.config b/bsp/raspberry-pi/raspi4/.config new file mode 100644 index 0000000000..e300d0217b --- /dev/null +++ b/bsp/raspberry-pi/raspi4/.config @@ -0,0 +1,455 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_CPU_64BIT=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +CONFIG_BCM2711_SOC=y +# CONFIG_BSP_SUPPORT_FPU is not set + +# +# Hardware Drivers Config +# + +# +# BCM Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART0=y +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GIC400=y +# CONFIG_BSP_USING_GIC500 is not set +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_CORETIMER=y +# CONFIG_BSP_USING_SYSTIMER is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set + +# +# Board Peripheral Drivers +# +# CONFIG_BSP_USING_HDMI is not set diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig new file mode 100644 index 0000000000..e71ed3d54b --- /dev/null +++ b/bsp/raspberry-pi/raspi4/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BCM2711_SOC + bool + select ARCH_ARM_CORTEX_A57 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select ARCH_CPU_64BIT + default y + +source "driver/Kconfig" diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md new file mode 100644 index 0000000000..28e00f96c0 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/README.md @@ -0,0 +1,100 @@ +# Raspberry PI 3-64板级支持包说明 + +## 1. 简介 + +树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本： + +* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet +* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0 +* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM + +这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。 + + +## 2. 编译说明 + +### 2.1 Window上的环境搭建 + +Windows环境下推荐使用[env工具][1]进行编译。 + +首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。 + +将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。 + +接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py` + +修改路径： + +``` +EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin' +``` + +然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。 + +### 2.2 Linux上的环境搭建 + +Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。 + +直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。 + + +## 3. 执行 + +### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡 + +Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具 + +解开下载的镜像文件, linux下使用如下的命令 + +``` +unzip 2018-06-27-raspbian-stretch-lite.zip +``` + +准备一张空SD卡，linux环境下，插入电脑并执行 + +``` +sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync +``` + +**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。** + +Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。 + +最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。 + +### 3.2 准备好串口线 + +目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)： + +![raspi2](figures/raspi_uart.png) + +串口参数： 115200 8N1 ，硬件和软件流控为关。 + +按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息： + +```text + heap: 0x00020b20 - 0x00400000 + + \ | / +- RT - Thread Operating System + / | \ 3.1.0 build Aug 23 2019 + 2006 - 2019 Copyright by rt-thread team +Hello RT-Thread! +msh > +``` + +## 4. 支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0| + +## 5. 联系人信息 + +维护人：[bernard][5] + +[1]: https://www.rt-thread.org/page/download.html +[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads +[3]: https://downloads.raspberrypi.org/raspbian_lite_latest +[4]: https://etcher.io +[5]: https://github.com/BernardXiong diff --git a/bsp/raspberry-pi/raspi4/SConscript b/bsp/raspberry-pi/raspi4/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/raspberry-pi/raspi4/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/raspberry-pi/raspi4/SConstruct b/bsp/raspberry-pi/raspi4/SConstruct new file mode 100644 index 0000000000..93f349aab8 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/SConstruct @@ -0,0 +1,30 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +# make a building +DoBuilding(TARGET, objs) + diff --git a/bsp/raspberry-pi/raspi4/applications/SConscript b/bsp/raspberry-pi/raspi4/applications/SConscript new file mode 100644 index 0000000000..533df8ac31 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi4/applications/main.c b/bsp/raspberry-pi/raspi4/applications/main.c new file mode 100644 index 0000000000..9664e67d01 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include +#include +#include + +int main(int argc, char** argv) +{ + rt_kprintf("Hi, this is RT-Thread!!\n"); + return 0; +} diff --git a/bsp/raspberry-pi/raspi4/driver/Kconfig b/bsp/raspberry-pi/raspi4/driver/Kconfig new file mode 100644 index 0000000000..208b4b4300 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/Kconfig @@ -0,0 +1,97 @@ + +config BSP_SUPPORT_FPU + bool "Using Float" + default n + +menu "Hardware Drivers Config" + menu "BCM Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config RT_USING_UART0 + bool "Enabel UART 0" + default y + endif + + menuconfig BSP_USING_GIC + bool "Enable GIC" + select RT_USING_GIC + default y + if BSP_USING_GIC + config BSP_USING_GIC400 + bool "Enable GIC400" + default y + config BSP_USING_GIC500 + bool "Enable GIC500" + default n + endif + + config BSP_USING_PIN + bool "Using PIN" + select RT_USING_PIN + default y + + config BSP_USING_CORETIMER + bool "Using core timer" + select RT_USING_CORETIMER + default y + + menuconfig BSP_USING_SYSTIMER + bool "Enable SYSTIMER" + select BSP_USING_SYSTIMER + default n + + if BSP_USING_SYSTIMER + config RT_USING_SYSTIMER1 + bool "Enable sys timer1" + default n + config RT_USING_SYSTIMER3 + bool "Enable sys timer3" + default n + endif + + config BSP_USING_WDT + bool "Enable WDT" + select RT_USING_WDT + default n + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + if BSP_USING_RTC + config BSP_USING_ALARM + bool "Enable Alarm" + select RT_USING_ALARM + default n + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + default n + + if BSP_USING_SDIO + config BSP_USING_SDIO0 + bool "Enable SDIO0" + select RT_USING_SDIO + default n + endif + endmenu + + menu "Board Peripheral Drivers" + menuconfig BSP_USING_HDMI + bool "Enable HDMI" + default n + + if BSP_USING_HDMI + config BSP_USING_HDMI_DISPLAY + bool "HDMI DISPLAY" + default n + endif + endmenu +endmenu diff --git a/bsp/raspberry-pi/raspi4/driver/SConscript b/bsp/raspberry-pi/raspi4/driver/SConscript new file mode 100644 index 0000000000..533df8ac31 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c new file mode 100644 index 0000000000..9716755b72 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/board.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include "cp15.h" +#include "mmu.h" + +static rt_uint64_t timerStep; +// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control +#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040) +#define TIMER_IRQ 30 +#define NON_SECURE_TIMER_IRQ (1 << 1) + +int rt_hw_get_gtimer_frq(void); +void rt_hw_set_gtimer_val(rt_uint64_t value); +int rt_hw_get_gtimer_val(void); +int rt_hw_get_cntpct_val(void); +void rt_hw_gtimer_enable(void); + +void core0_timer_enable_interrupt_controller() +{ + CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ; +} + +void rt_hw_timer_isr(int vector, void *parameter) +{ + rt_hw_set_gtimer_val(timerStep); + rt_tick_increase(); +} + +void rt_hw_timer_init(void) +{ + rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(TIMER_IRQ); + __ISB(); + timerStep = rt_hw_get_gtimer_frq(); + __DSB(); + timerStep /= RT_TICK_PER_SECOND; + + rt_hw_gtimer_enable(); + rt_hw_set_gtimer_val(timerStep); + core0_timer_enable_interrupt_controller(); +} + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +/** + * Initialize the Hardware related stuffs. Called from rtthread_startup() + * after interrupt disabled. + */ +void rt_hw_board_init(void) +{ + mmu_init(); + armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY); + armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio + armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer + mmu_enable(); + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device + rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors); + + /* initialize timer for os tick */ + rt_hw_timer_init(); + rt_thread_idle_sethook(idle_wfi); + + /* initialize uart */ + rt_hw_uart_init(); // driver/drv_uart.c +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} \ No newline at end of file diff --git a/bsp/raspberry-pi/raspi4/driver/board.h b/bsp/raspberry-pi/raspi4/driver/board.h new file mode 100644 index 0000000000..66805464f2 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/board.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include + +extern unsigned char __bss_start; +extern unsigned char __bss_end; + +#define RT_HW_HEAP_BEGIN (void*)&__bss_end +#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c new file mode 100644 index 0000000000..4317a358e0 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include "drv_gpio.h" + +#ifdef BSP_USING_PIN + +static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) +{ + uint32_t fselnum = pin / 10; + uint32_t fselrest = pin % 10; + + uint32_t gpfsel = 0; + gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3))); + gpfsel |= (uint32_t)(mode << (fselrest * 3)); + + switch (fselnum) + { + case 0: + GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel; + break; + case 1: + GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; + break; + case 2: + GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel; + break; + case 3: + GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel; + break; + case 4: + GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel; + break; + case 5: + GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel; + break; + default: + break; + } +} + +static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) +{ + uint32_t num = pin / 32; + + if(num == 0) + { + if(value == 0) + { + GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); + } + } + else + { + if(value == 0) + { + GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); + } + + } +} + +static int raspi_pin_read(struct rt_device *device, rt_base_t pin) +{ + return 0; +} + +static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + return RT_EOK; +} + +static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + return RT_EOK; +} + +rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + return RT_EOK; +} + +static const struct rt_pin_ops ops = +{ + raspi_pin_mode, + raspi_pin_write, + raspi_pin_read, + raspi_pin_attach_irq, + raspi_pin_detach_irq, + raspi_pin_irq_enable, +}; +#endif + +int rt_hw_gpio_init(void) +{ +#ifdef BSP_USING_PIN + rt_device_pin_register("gpio", &ops, RT_NULL); +#endif + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_gpio_init); diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h new file mode 100644 index 0000000000..ebc9452cec --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#include "board.h" +#include "interrupt.h" + +#define GPIO_BASE (0xFE000000 + 0x00200000) + +#define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) +#define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) +#define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) +#define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C) +#define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10) +#define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14) +#define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18) +#define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C) +#define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20) +#define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24) +#define GPIO_REG_GPCLR0(BASE) HWREG32(BASE + 0x28) +#define GPIO_REG_GPCLR1(BASE) HWREG32(BASE + 0x2C) +#define GPIO_REG_REV2(BASE) HWREG32(BASE + 0x30) +#define GPIO_REG_GPLEV0(BASE) HWREG32(BASE + 0x34) +#define GPIO_REG_GPLEV1(BASE) HWREG32(BASE + 0x38) +#define GPIO_REG_REV3(BASE) HWREG32(BASE + 0x3C) +#define GPIO_REG_GPEDS0(BASE) HWREG32(BASE + 0x40) +#define GPIO_REG_GPEDS1(BASE) HWREG32(BASE + 0x44) +#define GPIO_REG_REV4(BASE) HWREG32(BASE + 0x48) +#define GPIO_REG_GPREN0(BASE) HWREG32(BASE + 0x4C) +#define GPIO_REG_GPREN1(BASE) HWREG32(BASE + 0x50) +#define GPIO_REG_REV5(BASE) HWREG32(BASE + 0x54) +#define GPIO_REG_GPFEN0(BASE) HWREG32(BASE + 0x58) +#define GPIO_REG_GPFEN1(BASE) HWREG32(BASE + 0x5C) +#define GPIO_REG_REV6(BASE) HWREG32(BASE + 0x60) +#define GPIO_REG_GPHEN0(BASE) HWREG32(BASE + 0x64) +#define GPIO_REG_GPHEN1(BASE) HWREG32(BASE + 0x68) +#define GPIO_REG_REV7(BASE) HWREG32(BASE + 0x6C) +#define GPIO_REG_GPLEN0(BASE) HWREG32(BASE + 0x70) +#define GPIO_REG_GPLEN1(BASE) HWREG32(BASE + 0x74) +#define GPIO_REG_REV8(BASE) HWREG32(BASE + 0x78) +#define GPIO_REG_GPAREN0(BASE) HWREG32(BASE + 0x7C) +#define GPIO_REG_GPAREN1(BASE) HWREG32(BASE + 0x80) +#define GPIO_REG_REV11(BASE) HWREG32(BASE + 0x84) +#define GPIO_REG_GPAFEN0(BASE) HWREG32(BASE + 0x88) +#define GPIO_REG_GPAFEN1(BASE) HWREG32(BASE + 0x8C) +#define GPIO_REG_REV10(BASE) HWREG32(BASE + 0x90) +#define GPIO_REG_GPPUD(BASE) HWREG32(BASE + 0x94) +#define GPIO_REG_GPPUDCLK0(BASE) HWREG32(BASE + 0x98) +#define GPIO_REG_GPPUDCLK1(BASE) HWREG32(BASE + 0x9C) +#define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0) +#define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4) + +typedef enum { + INPUT = 0b000, + OUTPUT = 0b001, + ALT0 = 0b100, + ALT1 = 0b101, + ALT2 = 0b110, + ALT3 = 0b111, + ALT4 = 0b011, + ALT5 = 0b010 +} GPIO_FUNC; + + +int rt_hw_gpio_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.c b/bsp/raspberry-pi/raspi4/driver/drv_uart.c new file mode 100644 index 0000000000..a7ac1b5892 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" + +#define UART0_BASE (0xFE000000 + 0x00201000) +#define PL011_BASE UART0_BASE +#define IRQ_PL011 (121 + 32) + +#define UART_REFERENCE_CLOCK 48000000 + +struct hw_uart_device +{ + rt_ubase_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart; + uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16; + uint32_t ibrd = bauddiv / 1000; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + if(uart->hw_base == PL011_BASE) + { + uint32_t gpfsel = 0; + + gpfsel &= ~((uint32_t)(0x07 << (4 * 3))); + gpfsel |= (uint32_t)(ALT0 << (4 * 3)); + GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; + + gpfsel &= ~((uint32_t)(0x07 << (5 * 3))); + gpfsel |= (uint32_t)(ALT0 << (5 * 3)); + GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; + + PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/ + PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/ + PL011_REG_IBRD(uart->hw_base) = ibrd; + PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000); + PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/ + PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/ + } + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM); + rt_hw_interrupt_mask(uart->irqno); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM; + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF)); + PL011_REG_DR(uart->hw_base) = (uint8_t)c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0) + { + ch = PL011_REG_DR(uart->hw_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device*)param; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; +} + + +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + PL011_BASE, + IRQ_PL011, +}; + +static struct rt_serial_device _serial0; + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart"); + + return 0; +} diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.h b/bsp/raspberry-pi/raspi4/driver/drv_uart.h new file mode 100644 index 0000000000..4f23d7b46e --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +// register's bit +#define PL011_FR_RI (1 << 8) +#define PL011_FR_TXFE (1 << 7) +#define PL011_FR_RXFF (1 << 6) +#define PL011_FR_TXFF (1 << 5) +#define PL011_FR_RXFE (1 << 4) +#define PL011_FR_BUSY (1 << 3) +#define PL011_FR_DCD (1 << 2) +#define PL011_FR_DSR (1 << 1) +#define PL011_FR_CTS (1 << 0) + +#define PL011_LCRH_SPS (1 << 7) +#define PL011_LCRH_WLEN_8 (3 << 5) +#define PL011_LCRH_WLEN_7 (2 << 5) +#define PL011_LCRH_WLEN_6 (1 << 5) +#define PL011_LCRH_WLEN_5 (0 << 5) +#define PL011_LCRH_FEN (1 << 4) +#define PL011_LCRH_STP2 (1 << 3) +#define PL011_LCRH_EPS (1 << 2) +#define PL011_LCRH_PEN (1 << 1) +#define PL011_LCRH_BRK (1 << 0) + +#define PL011_CR_CTSEN (1 << 15) +#define PL011_CR_RTSEN (1 << 14) +#define PL011_CR_RTS (1 << 11) +#define PL011_CR_DTR (1 << 10) +#define PL011_CR_RXE (1 << 9) +#define PL011_CR_TXE (1 << 8) +#define PL011_CR_LBE (1 << 7) +#define PL011_CR_SIRLP (1 << 2) +#define PL011_CR_SIREN (1 << 1) +#define PL011_CR_UARTEN (1 << 0) + +#define PL011_IMSC_TXIM (1 << 5) +#define PL011_IMSC_RXIM (1 << 4) + +#define PL011_INTERRUPT_OVERRUN_ERROR (1 << 10) +#define PL011_INTERRUPT_BREAK_ERROR (1 << 9) +#define PL011_INTERRUPT_PARITY_ERROR (1 << 8) +#define PL011_INTERRUPT_FRAMING_ERROR (1 << 7) +#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6) +#define PL011_INTERRUPT_TRANSMIT (1 << 5) +#define PL011_INTERRUPT_RECEIVE (1 << 4) +#define PL011_INTERRUPT_nUARTCTS (1 << 1) + +#define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) +#define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) +#define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) +#define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) +#define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) +#define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) +#define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) +#define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) +#define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) +#define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) +#define PL011_REG_IFLS(BASE) HWREG32(BASE + 0x34) +#define PL011_REG_IMSC(BASE) HWREG32(BASE + 0x38) +#define PL011_REG_RIS(BASE) HWREG32(BASE + 0x3C) +#define PL011_REG_MIS(BASE) HWREG32(BASE + 0x40) +#define PL011_REG_ICR(BASE) HWREG32(BASE + 0x44) +#define PL011_REG_DMACR(BASE) HWREG32(BASE + 0x48) +#define PL011_REG_RESERVED2(BASE) HWREG32(BASE + 0x4C) +#define PL011_REG_ITCR(BASE) HWREG32(BASE + 0x80) +#define PL011_REG_ITIP(BASE) HWREG32(BASE + 0x84) +#define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88) +#define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C) + +int rt_hw_uart_init(void); + +#endif /* DRV_UART_H__ */ + diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h new file mode 100644 index 0000000000..00fc2025d9 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/driver/iomap.h @@ -0,0 +1,13 @@ +#ifndef __RASPI4_H__ +#define __RASPI4_H__ + +#define INTC_BASE 0xff800000 +#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000) +#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000) +#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000) +#define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000) + +#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE +#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE + +#endif \ No newline at end of file diff --git a/bsp/raspberry-pi/raspi4/link.lds b/bsp/raspberry-pi/raspi4/link.lds new file mode 100644 index 0000000000..b7b2dcc32c --- /dev/null +++ b/bsp/raspberry-pi/raspi4/link.lds @@ -0,0 +1,153 @@ +/* + * File : link.lds + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * 2017-5-30 bernard first version + */ + +/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */ + +SECTIONS +{ + . = 0x80000; + . = ALIGN(4096); + .text : + { + KEEP(*(.text.entrypoint)) /* The entry point */ + *(.vectors) + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + *(COMMON) + + /* section information for finsh shell */ + . = ALIGN(16); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(16); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(16); + + /* section information for initial. */ + . = ALIGN(16); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(16); + + . = ALIGN(16); + _etext = .; + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(16); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(16); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + . = ALIGN(16); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(16); + .bss : + { + PROVIDE(__bss_start = .); + *(.bss) + *(.bss.*) + *(.dynbss) + + PROVIDE(__bss_end = .); + } + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + +__bss_size = (__bss_end - __bss_start)>>3; diff --git a/bsp/raspberry-pi/raspi4/rtconfig.h b/bsp/raspberry-pi/raspi4/rtconfig.h new file mode 100644 index 0000000000..049e117559 --- /dev/null +++ b/bsp/raspberry-pi/raspi4/rtconfig.h @@ -0,0 +1,179 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 2048 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40003 +#define ARCH_CPU_64BIT + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + +#define BCM2711_SOC + +/* Hardware Drivers Config */ + +/* BCM Peripheral Drivers */ + +#define BSP_USING_UART +#define RT_USING_UART0 +#define BSP_USING_GIC +#define BSP_USING_GIC400 +#define BSP_USING_PIN +#define BSP_USING_CORETIMER + +/* Board Peripheral Drivers */ + + +#endif diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py new file mode 100644 index 0000000000..228ec0176a --- /dev/null +++ b/bsp/raspberry-pi/raspi4/rtconfig.py @@ -0,0 +1,51 @@ +import os + +# toolchains options +ARCH ='aarch64' +CPU ='cortex-a57' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = r'../../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +PLATFORM = 'gcc' +EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + # PREFIX = 'arm-none-eabi-' + PREFIX = 'aarch64-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv8-a -mtune=cortex-a57' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript index 453afe4b3e..5fca2b473b 100644 --- a/libcpu/aarch64/SConscript +++ b/libcpu/aarch64/SConscript @@ -9,6 +9,9 @@ cwd = GetCurrentDir() group = [] list = os.listdir(cwd) +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + # cpu porting code files if rtconfig.CPU != 'common': group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript new file mode 100644 index 0000000000..72fb8e26c3 --- /dev/null +++ b/libcpu/aarch64/common/SConscript @@ -0,0 +1,24 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) + +# build for sub-directory +list = os.listdir(cwd) +objs = [] + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +group = group + objs + + +Return('group') diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/common/armv8.h similarity index 100% rename from libcpu/aarch64/cortex-a53/armv8.h rename to libcpu/aarch64/common/armv8.h diff --git a/libcpu/aarch64/cortex-a53/cache.S b/libcpu/aarch64/common/cache.S similarity index 100% rename from libcpu/aarch64/cortex-a53/cache.S rename to libcpu/aarch64/common/cache.S diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/common/context_gcc.S similarity index 100% rename from libcpu/aarch64/cortex-a53/context_gcc.S rename to libcpu/aarch64/common/context_gcc.S diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/common/cp15.h similarity index 100% rename from libcpu/aarch64/cortex-a53/cp15.h rename to libcpu/aarch64/common/cp15.h diff --git a/libcpu/aarch64/cortex-a53/cpu.c b/libcpu/aarch64/common/cpu.c similarity index 100% rename from libcpu/aarch64/cortex-a53/cpu.c rename to libcpu/aarch64/common/cpu.c diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/common/cpu_gcc.S similarity index 100% rename from libcpu/aarch64/cortex-a53/cpu_gcc.S rename to libcpu/aarch64/common/cpu_gcc.S diff --git a/libcpu/aarch64/common/gic/SConscript b/libcpu/aarch64/common/gic/SConscript new file mode 100644 index 0000000000..b114ba7678 --- /dev/null +++ b/libcpu/aarch64/common/gic/SConscript @@ -0,0 +1,24 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd] + +gic400_group = Split(''' +gic_pl400.c +''') + +gic500_group = Split(''' +gic_pl500.c +''') + +src = () +if GetDepend('BSP_USING_GIC400'): + src = gic400_group +if GetDepend('BSP_USING_GIC500'): + src = gic500_group + +group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c new file mode 100644 index 0000000000..eb35c5b2a4 --- /dev/null +++ b/libcpu/aarch64/common/gic/gic_pl400.c @@ -0,0 +1,368 @@ +/* + * Copyright 2014, General Dynamics C4 Systems + * + * This software may be distributed and modified according to the terms of + * the GNU General Public License version 2. Note that NO WARRANTY is provided. + * See "LICENSE_GPLv2.txt" for details. + * + * @TAG(GD_GPL) + */ + +#include "gic_pl400.h" +#include "iomap.h" + +#define BIT(n) (1ul<<(n)) +#define MASK(n) (BIT(n)-1ul) + +/* Setters/getters helpers */ +#define IRQ_REG(IRQ) ((IRQ) / 32) +#define IRQ_BIT(IRQ) BIT((IRQ) % 32) +#define IRQ_MASK MASK(10) +#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START) + +#define CPU(X) (1<<(X)) +#define TARGET_CPU_ALLINT(CPU) ( \ + ( ((CPU)&0xff)<<0 ) |\ + ( ((CPU)&0xff)<<8 ) |\ + ( ((CPU)&0xff)<<16 ) |\ + ( ((CPU)&0xff)<<24 ) \ + ) +#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0)) + + +#define IRQ_SET_ALL 0xffffffff; + +/* Special IRQ's */ +#define SPECIAL_IRQ_START 1020 +#define IRQ_NONE 1023 + +/* Memory map for GIC distributor */ +struct gic_dist_map { + uint32_t enable; /* 0x000 */ + uint32_t ic_type; /* 0x004 */ + uint32_t dist_ident; /* 0x008 */ + uint32_t res1[29]; /* [0x00C, 0x080) */ + + uint32_t group[32]; /* [0x080, 0x100) */ + + uint32_t enable_set[32]; /* [0x100, 0x180) */ + uint32_t enable_clr[32]; /* [0x180, 0x200) */ + uint32_t pending_set[32]; /* [0x200, 0x280) */ + uint32_t pending_clr[32]; /* [0x280, 0x300) */ + uint32_t active[32]; /* [0x300, 0x380) */ + uint32_t active_clr[32]; /* [0x380, 0x400) */ + + uint32_t priority[255]; /* [0x400, 0x7FC) */ + uint32_t res2; /* 0x7FC */ + + uint32_t targets[255]; /* [0x800, 0xBFC) */ + uint32_t res3; /* 0xBFC */ + + uint32_t config[64]; /* [0xC00, 0xD00) */ + + uint32_t ppi_status; /* [0xD00, 0xD04) */ + uint32_t spi_status[15]; /* [0xD04, 0xD40) */ + uint32_t res4[112]; /* [0xD40, 0xF00) */ + + uint32_t sgi_control; /* 0xF00 */ + uint32_t res5[3]; /* [0xF04, 0xF10) */ + uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */ + uint32_t sgi_pending_set[4]; /* [0xF20, 0xF30) */ + uint32_t res10[40]; /* [0xF30, 0xFD0) */ + + uint32_t periph_id[8]; /* [0xFD0, 0xFF0) */ + uint32_t component_id[4]; /* [0xFF0, 0xFFF] */ +}; + + +/* Memory map for GIC cpu interface */ +struct gic_cpu_iface_map { + uint32_t icontrol; /* 0x000 */ + uint32_t pri_msk_c; /* 0x004 */ + uint32_t bp_c; /* 0x008 */ + uint32_t int_ack; /* 0x00C */ + uint32_t eoi; /* 0x010 */ + uint32_t run_priority; /* 0x014 */ + uint32_t hi_pend; /* 0x018 */ + uint32_t ns_alias_bp_c; /* 0x01C */ + uint32_t ns_alias_ack; /* 0x020 GIC_PL400 only */ + uint32_t ns_alias_eoi; /* 0x024 GIC_PL400 only */ + uint32_t ns_alias_hi_pend; /* 0x028 GIC_PL400 only */ + + uint32_t res1[41]; /* [0x02C, 0x0D0) */ + uint32_t active_priority[4]; /* [0x0D0, 0xC0] GIC_PL400 only */ + uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */ + uint32_t res4[3]; /* [0xF0, 0xFC] */ + + uint32_t cpu_if_ident; /* 0x0FC */ + uint32_t deactive; /* [0x1000] */ +}; + +volatile struct gic_dist_map *gic_dist = + (volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR); + +volatile struct gic_cpu_iface_map *gic_cpuiface = + (volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR); + +/* Helpers */ +static inline int +is_irq_pending(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + return !!(gic_dist->pending_set[word] & BIT(bit)); +} + +static inline int +is_irq_active(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + return !!(gic_dist->active[word] & BIT(bit)); +} + +static inline int +is_irq_enabled(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + return !!(gic_dist->enable_set[word] & BIT(bit)); +} + +static inline int +is_irq_edge_triggered(irq_t irq) +{ + int word = irq / 16; + int bit = ((irq & 0xf) * 2); + return !!(gic_dist->config[word] & BIT(bit + 1)); +} + +static inline int +is_irq_1_N(irq_t irq) +{ + int word = irq / 16; + int bit = ((irq & 0xf) * 2); + return !!(gic_dist->config[word] & BIT(bit + 0)); +} + +static inline int +is_irq_N_N(irq_t irq) +{ + return !(is_irq_1_N(irq)); +} + +static inline void +dist_pending_clr(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + /* Using |= here is detrimental to your health */ + gic_dist->pending_clr[word] = BIT(bit); +} + +static inline void +dist_pending_set(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + gic_dist->pending_set[word] = BIT(bit); +} + +static inline void +dist_enable_clr(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + /* Using |= here is detrimental to your health */ + gic_dist->enable_clr[word] = BIT(bit); +} + +static inline void +dist_enable_set(irq_t irq) +{ + int word = irq / 32; + int bit = irq & 0x1f; + gic_dist->enable_set[word] = BIT(bit); +} + +/** + DONT_TRANSLATE + */ +static void dist_init(void) +{ + int i; + int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1); + gic_dist->enable = 0; + +#if 0 + /* configure to group 0 for security */ + for (i = 0; i < nirqs; i += 32) { + gic_dist->group[i / 32] = 0xffffffff; + } +#endif + + for (i = 0; i < nirqs; i += 32) { + /* disable */ + gic_dist->enable_clr[i / 32] = IRQ_SET_ALL; + /* clear pending */ + gic_dist->pending_clr[i / 32] = IRQ_SET_ALL; + } + + /* reset interrupts priority */ + for (i = 32; i < nirqs; i += 4) { + gic_dist->priority[i / 4] = 0x0; + } + + /* + * reset int target to cpu 0 + * (Should really query which processor we're running on and use that) + */ + for (i = 0; i < nirqs; i += 4) { + gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT; + } + + /* level-triggered, 1-N */ + for (i = 64; i < nirqs; i += 32) { + gic_dist->config[i / 32] = 0; + //gic_dist->config[i / 32] = 0x55555555; + } + /* enable the int controller */ + gic_dist->enable = 1; +} + +/** + DONT_TRANSLATE + */ +static void cpu_iface_init(void) +{ + uint32_t i; + + /* For non-Exynos4, the registers are banked per CPU, need to clear them */ + gic_dist->enable_clr[0] = IRQ_SET_ALL; + gic_dist->pending_clr[0] = IRQ_SET_ALL; + gic_dist->priority[0] = 0x00; + /* put everything in group 0 */ + + /* clear any software generated interrupts */ + for (i = 0; i < 16; i += 4) { + gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL; + } + + gic_cpuiface->icontrol = 0; + gic_cpuiface->pri_msk_c = 0x000000f0; + gic_cpuiface->bp_c = 0x00000003; + + while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) { + gic_cpuiface->eoi = i; + } + gic_cpuiface->icontrol = 0x1; +} + +/** + DONT_TRANSLATE + */ +void initIRQController(void) +{ + dist_init(); + cpu_iface_init(); +} + + + +/* + * The only sane way to get an GIC IRQ number that can be properly + * ACKED later is through the int_ack register. Unfortunately, reading + * this register changes the interrupt state to pending so future + * reads will not return the same value For this reason, we have a + * global variable to store the IRQ number. + */ +static uint32_t active_irq = IRQ_NONE; + +/** + DONT_TRANSLATE + */ +interrupt_t +getActiveIRQ(void) +{ + uint32_t irq; + if (!IS_IRQ_VALID(active_irq)) { + active_irq = gic_cpuiface->int_ack; + } + + if (IS_IRQ_VALID(active_irq)) { + irq = active_irq & IRQ_MASK; + } else { + irq = 1023; + } + + return irq; +} + +/* + * GIC has 4 states: pending->active(+pending)->inactive + * seL4 expects two states: active->inactive. + * We ignore the active state in GIC to conform + */ +/** + DONT_TRANSLATE + */ +bool_t +isIRQPending(void) +{ + return IS_IRQ_VALID(gic_cpuiface->hi_pend); +} + + +/** + DONT_TRANSLATE + */ +void +maskInterrupt(bool_t disable, interrupt_t irq) +{ + if (disable) { + dist_enable_clr(irq); + } else { + dist_enable_set(irq); + } +} + +/** + DONT_TRANSLATE + */ +void +ackInterrupt(irq_t irq) +{ + if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) { + return; + } + if (is_irq_edge_triggered(irq)) { + dist_pending_clr(irq); + } + gic_cpuiface->eoi = active_irq; + active_irq = IRQ_NONE; +} + +void +handleSpuriousIRQ(void) +{ +} + +void rt_hw_interrupt_mask(int vector) +{ + maskInterrupt(1, vector); +} + +void rt_hw_interrupt_umask(int vector) +{ + maskInterrupt(0, vector); +} + +int rt_hw_interrupt_get_irq(void) +{ + return getActiveIRQ(); +} + +void rt_hw_interrupt_ack(int fiq_irq) +{ + return ackInterrupt(fiq_irq); +} diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h new file mode 100644 index 0000000000..a43583bd7c --- /dev/null +++ b/libcpu/aarch64/common/gic/gic_pl400.h @@ -0,0 +1,35 @@ + +#ifndef __ARCH_MACHINE_GIC_PL400_H +#define __ARCH_MACHINE_GIC_PL400_H + +#include + +typedef uint16_t interrupt_t; +typedef uint16_t irq_t; +typedef uint64_t bool_t; + +/** MODIFIES: [*] */ +interrupt_t getActiveIRQ(void); +/** MODIFIES: [*] */ +interrupt_t getPendingIRQ(void); +/** MODIFIES: [*] */ +bool_t isIRQPending(void); +/** MODIFIES: [*] */ +void maskInterrupt(bool_t disable, interrupt_t irq); +/** MODIFIES: [*] */ +void ackInterrupt(irq_t irq); +/** MODIFIES: [*] */ +static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { } + +/** MODIFIES: [*] */ +void initIRQController(void); + +void handleSpuriousIRQ(void); + +void rt_hw_interrupt_umask(int vector); + +int rt_hw_interrupt_get_irq(void); + +void rt_hw_interrupt_ack(int fiq_irq); +#endif /* !__ARCH_MACHINE_GIC400_H */ + diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/common/mmu.c similarity index 100% rename from libcpu/aarch64/cortex-a53/mmu.c rename to libcpu/aarch64/common/mmu.c diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/common/mmu.h similarity index 100% rename from libcpu/aarch64/cortex-a53/mmu.h rename to libcpu/aarch64/common/mmu.h diff --git a/libcpu/aarch64/cortex-a53/startup_gcc.S b/libcpu/aarch64/common/startup_gcc.S similarity index 100% rename from libcpu/aarch64/cortex-a53/startup_gcc.S rename to libcpu/aarch64/common/startup_gcc.S diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S similarity index 100% rename from libcpu/aarch64/cortex-a53/vector_gcc.S rename to libcpu/aarch64/common/vector_gcc.S diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript index 75e170a0cf..c6a4817802 100644 --- a/libcpu/aarch64/cortex-a53/SConscript +++ b/libcpu/aarch64/cortex-a53/SConscript @@ -1,16 +1,13 @@ +# RT-Thread building script for component + from building import * +Import('rtconfig') + cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -asm_src = Split(''' -context_gcc.S -vector_gcc.S -entry_point.S -cpu_gcc.S -cache.S -''') +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h index 3533d3818c..8e741ed4e6 100644 --- a/libcpu/aarch64/cortex-a53/interrupt.h +++ b/libcpu/aarch64/cortex-a53/interrupt.h @@ -1,11 +1,11 @@ - /* * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes + * 2020-04-16 bigmagic first version */ #ifndef __INTERRUPT_H__ @@ -19,8 +19,6 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -//void rt_hw_vector_init(void); - void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int vector); void rt_hw_interrupt_umask(int vector); diff --git a/libcpu/aarch64/cortex-a57/SConscript b/libcpu/aarch64/cortex-a57/SConscript new file mode 100644 index 0000000000..c6a4817802 --- /dev/null +++ b/libcpu/aarch64/cortex-a57/SConscript @@ -0,0 +1,13 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/aarch64/cortex-a57/entry_point.S b/libcpu/aarch64/cortex-a57/entry_point.S new file mode 100644 index 0000000000..6d2c69226b --- /dev/null +++ b/libcpu/aarch64/cortex-a57/entry_point.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2020-01-15 bigmagic the first version + */ + +.section ".text.entrypoint" + +.set EL1_stack, __el1_stack + +.global _start + +// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware +// loads 'kernel8.img' file in. +_start: + // read cpu id, stop slave cores + mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register + and x1, x1, #3 + cbz x1, .L__cpu_0 // .L prefix is the local label in ELF + + // cpu id > 0, stop + // cpu id == 0 will also goto here after returned from entry() if possible +.L__current_cpu_idle: + wfe + b .L__current_cpu_idle + +.L__cpu_0: // cpu id == 0 + + // set stack before our code + + /* Define stack pointer for current exception level */ + // ldr x2, =EL1_stack + // mov sp, x2 + + ldr x1, =_start + + // set up EL1 + mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved + and x0, x0, #12 // clear reserved bits + + // running at EL3? + cmp x0, #12 // 1100b. So, EL3 + bne .L__not_in_el3 // 11? !EL3 -> 5: + + // should never be executed, just for completeness. (EL3) + mov x2, #0x5b1 + msr scr_el3, x2 // SCR_ELn Secure Configuration Register + mov x2, #0x3c9 + msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001 + adr x2, .L__not_in_el3 + msr elr_el3, x2 + eret // Exception Return: from EL3, continue from .L__not_in_el3 + + // running at EL2 or EL1 +.L__not_in_el3: + cmp x0, #4 // 0x04 0100 EL1 + beq .L__in_el1 // EL1 -> 5: + + // in EL2 + msr sp_el1, x1 // Set sp of EL1 to _start + + // enable CNTP for EL1 + mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register + orr x0, x0, #3 + msr cnthctl_el2, x0 + msr cntvoff_el2, xzr + + // enable AArch64 in EL1 + mov x0, #(1 << 31) // AArch64 + orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3 + msr hcr_el2, x0 + mrs x0, hcr_el2 + + // change execution level to EL1 + mov x2, #0x3c4 + msr spsr_el2, x2 // 1111000100 + adr x2, .L__in_el1 + msr elr_el2, x2 + eret // exception return. from EL2. continue from .L__in_el1 + +.L__in_el1: + mov sp, x1 // in EL1. Set sp to _start + + // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction + mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1 + msr cpacr_el1, x1 + + mrs x1, sctlr_el1 + orr x1, x1, #(1 << 12) + bic x1, x1, #(3 << 3) + bic x1, x1, #(1 << 1) + msr sctlr_el1, x1 + + // clear bss + ldr x1, =__bss_start + ldr w2, =__bss_size + +.L__clean_bss_loop: + cbz w2, .L__jump_to_entry + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, .L__clean_bss_loop + + // jump to C code, should not return +.L__jump_to_entry: + bl entry + // for failsafe, halt this core too + b .L__current_cpu_idle diff --git a/libcpu/aarch64/cortex-a57/interrupt.c b/libcpu/aarch64/cortex-a57/interrupt.c new file mode 100644 index 0000000000..d770259d61 --- /dev/null +++ b/libcpu/aarch64/cortex-a57/interrupt.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include +#include +#include +#include +#include + +#define MAX_HANDLERS 256 + +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +extern int system_vectors; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; + +void rt_hw_vector_init(void) +{ + rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + initIRQController(); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} \ No newline at end of file diff --git a/libcpu/aarch64/cortex-a57/interrupt.h b/libcpu/aarch64/cortex-a57/interrupt.h new file mode 100644 index 0000000000..0d2d4867c7 --- /dev/null +++ b/libcpu/aarch64/cortex-a57/interrupt.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/aarch64/cortex-a57/stack.c b/libcpu/aarch64/cortex-a57/stack.c new file mode 100644 index 0000000000..68222c2c67 --- /dev/null +++ b/libcpu/aarch64/cortex-a57/stack.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include + +#include + +#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) +#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) +#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_ubase_t *stk; + rt_ubase_t current_el; + + stk = (rt_ubase_t*)stack_addr; + + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + + current_el = rt_hw_get_current_el(); + + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } + + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/aarch64/cortex-a57/trap.c b/libcpu/aarch64/cortex-a57/trap.c new file mode 100644 index 0000000000..d93aa18fd6 --- /dev/null +++ b/libcpu/aarch64/cortex-a57/trap.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +#include +#include + +#include "interrupt.h" +#include "armv8.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); + rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_error(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("error exception:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK 0x000003ff + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int fiq_irq); + +void rt_hw_trap_irq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); + +} + +void rt_hw_trap_fiq(void) +{ +} From a120c914bb003646010d1d385be36b5260284132 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Thu, 16 Apr 2020 16:42:07 +0800 Subject: [PATCH 05/27] add bsp/raspi4 readme --- bsp/raspberry-pi/raspi3-64/README.md | 2 +- bsp/raspberry-pi/raspi4/Kconfig | 2 +- bsp/raspberry-pi/raspi4/README.md | 89 ++++++++----------- bsp/raspberry-pi/raspi4/rtconfig.py | 2 +- .../{cortex-a57 => cortex-a72}/SConscript | 0 .../{cortex-a57 => cortex-a72}/entry_point.S | 0 .../{cortex-a57 => cortex-a72}/interrupt.c | 0 .../{cortex-a57 => cortex-a72}/interrupt.h | 0 .../{cortex-a57 => cortex-a72}/stack.c | 0 .../aarch64/{cortex-a57 => cortex-a72}/trap.c | 0 10 files changed, 38 insertions(+), 57 deletions(-) rename libcpu/aarch64/{cortex-a57 => cortex-a72}/SConscript (100%) rename libcpu/aarch64/{cortex-a57 => cortex-a72}/entry_point.S (100%) rename libcpu/aarch64/{cortex-a57 => cortex-a72}/interrupt.c (100%) rename libcpu/aarch64/{cortex-a57 => cortex-a72}/interrupt.h (100%) rename libcpu/aarch64/{cortex-a57 => cortex-a72}/stack.c (100%) rename libcpu/aarch64/{cortex-a57 => cortex-a72}/trap.c (100%) diff --git a/bsp/raspberry-pi/raspi3-64/README.md b/bsp/raspberry-pi/raspi3-64/README.md index 28e00f96c0..576b13ed0e 100644 --- a/bsp/raspberry-pi/raspi3-64/README.md +++ b/bsp/raspberry-pi/raspi3-64/README.md @@ -17,7 +17,7 @@ Windows环境下推荐使用[env工具][1]进行编译。 -首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。 +首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。 将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。 diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig index e71ed3d54b..075a5d81aa 100644 --- a/bsp/raspberry-pi/raspi4/Kconfig +++ b/bsp/raspberry-pi/raspi4/Kconfig @@ -20,7 +20,7 @@ source "$PKGS_DIR/Kconfig" config BCM2711_SOC bool - select ARCH_ARM_CORTEX_A57 + select ARCH_ARM_CORTEX_A72 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN select ARCH_CPU_64BIT diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md index 28e00f96c0..1e7411894e 100644 --- a/bsp/raspberry-pi/raspi4/README.md +++ b/bsp/raspberry-pi/raspi4/README.md @@ -1,86 +1,67 @@ -# Raspberry PI 3-64板级支持包说明 +# Raspberry PI 4板级支持包说明 ## 1. 简介 -树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本： +树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。 -* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet -* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0 -* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM +外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。 -这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。 +这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。 ## 2. 编译说明 -### 2.1 Window上的环境搭建 - -Windows环境下推荐使用[env工具][1]进行编译。 - -首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。 - -将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。 - -接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py` - -修改路径： - -``` -EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin' -``` - -然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。 - -### 2.2 Linux上的环境搭建 - Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。 -直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。 +将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。 + +``` +PLATFORM = 'gcc' +EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' +``` + +直接进入`bsp\raspberry-pi\raspi4`，输入scons编译即可。 ## 3. 执行 -### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡 +### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡 -Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具 +首先下载镜像 -解开下载的镜像文件, linux下使用如下的命令 - -``` -unzip 2018-06-27-raspbian-stretch-lite.zip -``` - -准备一张空SD卡，linux环境下，插入电脑并执行 - -``` -sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync -``` - -**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。** - -Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。 - -最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。 +* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb) +* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe) +* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg) ### 3.2 准备好串口线 -目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)： +目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示： -![raspi2](figures/raspi_uart.png) +![raspi2](../raspi3-32/figures/raspberrypi-console.png) 串口参数： 115200 8N1 ，硬件和软件流控为关。 -按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息： +### 3.3 程序下载 + +当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下： + +``` +enable_uart=1 +arm_64bit=1 +kernel=rtthread.bin +``` + +按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息： ```text - heap: 0x00020b20 - 0x00400000 +heap: 0x000c9350 - 0x040c9350 \ | / - RT - Thread Operating System - / | \ 3.1.0 build Aug 23 2019 - 2006 - 2019 Copyright by rt-thread team -Hello RT-Thread! -msh > + / | \ 4.0.3 build Apr 16 2020 + 2006 - 2020 Copyright by rt-thread team +Hi, this is RT-Thread!! +msh /> ``` ## 4. 支持情况 diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py index 228ec0176a..9265b016be 100644 --- a/bsp/raspberry-pi/raspi4/rtconfig.py +++ b/bsp/raspberry-pi/raspi4/rtconfig.py @@ -2,7 +2,7 @@ import os # toolchains options ARCH ='aarch64' -CPU ='cortex-a57' +CPU ='cortex-a72' CROSS_TOOL ='gcc' if os.getenv('RTT_ROOT'): diff --git a/libcpu/aarch64/cortex-a57/SConscript b/libcpu/aarch64/cortex-a72/SConscript similarity index 100% rename from libcpu/aarch64/cortex-a57/SConscript rename to libcpu/aarch64/cortex-a72/SConscript diff --git a/libcpu/aarch64/cortex-a57/entry_point.S b/libcpu/aarch64/cortex-a72/entry_point.S similarity index 100% rename from libcpu/aarch64/cortex-a57/entry_point.S rename to libcpu/aarch64/cortex-a72/entry_point.S diff --git a/libcpu/aarch64/cortex-a57/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c similarity index 100% rename from libcpu/aarch64/cortex-a57/interrupt.c rename to libcpu/aarch64/cortex-a72/interrupt.c diff --git a/libcpu/aarch64/cortex-a57/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h similarity index 100% rename from libcpu/aarch64/cortex-a57/interrupt.h rename to libcpu/aarch64/cortex-a72/interrupt.h diff --git a/libcpu/aarch64/cortex-a57/stack.c b/libcpu/aarch64/cortex-a72/stack.c similarity index 100% rename from libcpu/aarch64/cortex-a57/stack.c rename to libcpu/aarch64/cortex-a72/stack.c diff --git a/libcpu/aarch64/cortex-a57/trap.c b/libcpu/aarch64/cortex-a72/trap.c similarity index 100% rename from libcpu/aarch64/cortex-a57/trap.c rename to libcpu/aarch64/cortex-a72/trap.c From 709e0d5799a57e9904d856fd94a935bd1deb153d Mon Sep 17 00:00:00 2001 From: bigmagic Date: Thu, 16 Apr 2020 18:48:27 +0800 Subject: [PATCH 06/27] add bsp/raspi4 gicv2 --- bsp/raspberry-pi/raspi4/driver/board.c | 7 +- bsp/raspberry-pi/raspi4/driver/iomap.h | 1 + bsp/raspberry-pi/raspi4/rtconfig.py | 2 +- libcpu/aarch64/common/gic/gic_pl400.c | 578 ++++++++++--------------- libcpu/aarch64/common/gic/gic_pl400.h | 76 ++-- libcpu/aarch64/cortex-a72/interrupt.c | 50 ++- 6 files changed, 340 insertions(+), 374 deletions(-) diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c index 9716755b72..46d629a35d 100644 --- a/bsp/raspberry-pi/raspi4/driver/board.c +++ b/bsp/raspberry-pi/raspi4/driver/board.c @@ -75,10 +75,6 @@ void rt_hw_board_init(void) rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors); - /* initialize timer for os tick */ - rt_hw_timer_init(); - rt_thread_idle_sethook(idle_wfi); - /* initialize uart */ rt_hw_uart_init(); // driver/drv_uart.c #ifdef RT_USING_CONSOLE @@ -91,6 +87,9 @@ void rt_hw_board_init(void) rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); #endif + /* initialize timer for os tick */ + rt_hw_timer_init(); + rt_thread_idle_sethook(idle_wfi); #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h index 00fc2025d9..675cd147e3 100644 --- a/bsp/raspberry-pi/raspi4/driver/iomap.h +++ b/bsp/raspberry-pi/raspi4/driver/iomap.h @@ -1,6 +1,7 @@ #ifndef __RASPI4_H__ #define __RASPI4_H__ +#define ARM_GIC_NR_IRQS 512 #define INTC_BASE 0xff800000 #define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000) #define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000) diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py index 9265b016be..a1dd168d3d 100644 --- a/bsp/raspberry-pi/raspi4/rtconfig.py +++ b/bsp/raspberry-pi/raspi4/rtconfig.py @@ -32,7 +32,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -march=armv8-a -mtune=cortex-a57' + DEVICE = ' -march=armv8-a -mtune=cortex-a72' CFLAGS = DEVICE + ' -Wall' AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c index eb35c5b2a4..4d003a9dcd 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.c +++ b/libcpu/aarch64/common/gic/gic_pl400.c @@ -1,368 +1,262 @@ /* - * Copyright 2014, General Dynamics C4 Systems + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This software may be distributed and modified according to the terms of - * the GNU General Public License version 2. Note that NO WARRANTY is provided. - * See "LICENSE_GPLv2.txt" for details. + * SPDX-License-Identifier: Apache-2.0 * - * @TAG(GD_GPL) + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() */ +#include #include "gic_pl400.h" +#include "cp15.h" #include "iomap.h" -#define BIT(n) (1ul<<(n)) -#define MASK(n) (BIT(n)-1ul) +#define ARM_GIC_MAX_NR 1 +struct arm_gic +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ -/* Setters/getters helpers */ -#define IRQ_REG(IRQ) ((IRQ) / 32) -#define IRQ_BIT(IRQ) BIT((IRQ) % 32) -#define IRQ_MASK MASK(10) -#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START) - -#define CPU(X) (1<<(X)) -#define TARGET_CPU_ALLINT(CPU) ( \ - ( ((CPU)&0xff)<<0 ) |\ - ( ((CPU)&0xff)<<8 ) |\ - ( ((CPU)&0xff)<<16 ) |\ - ( ((CPU)&0xff)<<24 ) \ - ) -#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0)) - - -#define IRQ_SET_ALL 0xffffffff; - -/* Special IRQ's */ -#define SPECIAL_IRQ_START 1020 -#define IRQ_NONE 1023 - -/* Memory map for GIC distributor */ -struct gic_dist_map { - uint32_t enable; /* 0x000 */ - uint32_t ic_type; /* 0x004 */ - uint32_t dist_ident; /* 0x008 */ - uint32_t res1[29]; /* [0x00C, 0x080) */ - - uint32_t group[32]; /* [0x080, 0x100) */ - - uint32_t enable_set[32]; /* [0x100, 0x180) */ - uint32_t enable_clr[32]; /* [0x180, 0x200) */ - uint32_t pending_set[32]; /* [0x200, 0x280) */ - uint32_t pending_clr[32]; /* [0x280, 0x300) */ - uint32_t active[32]; /* [0x300, 0x380) */ - uint32_t active_clr[32]; /* [0x380, 0x400) */ - - uint32_t priority[255]; /* [0x400, 0x7FC) */ - uint32_t res2; /* 0x7FC */ - - uint32_t targets[255]; /* [0x800, 0xBFC) */ - uint32_t res3; /* 0xBFC */ - - uint32_t config[64]; /* [0xC00, 0xD00) */ - - uint32_t ppi_status; /* [0xD00, 0xD04) */ - uint32_t spi_status[15]; /* [0xD04, 0xD40) */ - uint32_t res4[112]; /* [0xD40, 0xF00) */ - - uint32_t sgi_control; /* 0xF00 */ - uint32_t res5[3]; /* [0xF04, 0xF10) */ - uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */ - uint32_t sgi_pending_set[4]; /* [0xF20, 0xF30) */ - uint32_t res10[40]; /* [0xF30, 0xFD0) */ - - uint32_t periph_id[8]; /* [0xFD0, 0xFF0) */ - uint32_t component_id[4]; /* [0xFF0, 0xFFF] */ + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ }; +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; -/* Memory map for GIC cpu interface */ -struct gic_cpu_iface_map { - uint32_t icontrol; /* 0x000 */ - uint32_t pri_msk_c; /* 0x004 */ - uint32_t bp_c; /* 0x008 */ - uint32_t int_ack; /* 0x00C */ - uint32_t eoi; /* 0x010 */ - uint32_t run_priority; /* 0x014 */ - uint32_t hi_pend; /* 0x018 */ - uint32_t ns_alias_bp_c; /* 0x01C */ - uint32_t ns_alias_ack; /* 0x020 GIC_PL400 only */ - uint32_t ns_alias_eoi; /* 0x024 GIC_PL400 only */ - uint32_t ns_alias_hi_pend; /* 0x028 GIC_PL400 only */ +static unsigned int _gic_max_irq; - uint32_t res1[41]; /* [0x02C, 0x0D0) */ - uint32_t active_priority[4]; /* [0x0D0, 0xC0] GIC_PL400 only */ - uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */ - uint32_t res4[3]; /* [0xF0, 0xFC] */ - - uint32_t cpu_if_ident; /* 0x0FC */ - uint32_t deactive; /* [0x1000] */ -}; - -volatile struct gic_dist_map *gic_dist = - (volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR); - -volatile struct gic_cpu_iface_map *gic_cpuiface = - (volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR); - -/* Helpers */ -static inline int -is_irq_pending(irq_t irq) +int arm_gic_get_active_irq(rt_uint32_t index) { - int word = irq / 32; - int bit = irq & 0x1f; - return !!(gic_dist->pending_set[word] & BIT(bit)); -} + int irq; -static inline int -is_irq_active(irq_t irq) -{ - int word = irq / 32; - int bit = irq & 0x1f; - return !!(gic_dist->active[word] & BIT(bit)); -} - -static inline int -is_irq_enabled(irq_t irq) -{ - int word = irq / 32; - int bit = irq & 0x1f; - return !!(gic_dist->enable_set[word] & BIT(bit)); -} - -static inline int -is_irq_edge_triggered(irq_t irq) -{ - int word = irq / 16; - int bit = ((irq & 0xf) * 2); - return !!(gic_dist->config[word] & BIT(bit + 1)); -} - -static inline int -is_irq_1_N(irq_t irq) -{ - int word = irq / 16; - int bit = ((irq & 0xf) * 2); - return !!(gic_dist->config[word] & BIT(bit + 0)); -} - -static inline int -is_irq_N_N(irq_t irq) -{ - return !(is_irq_1_N(irq)); -} - -static inline void -dist_pending_clr(irq_t irq) -{ - int word = irq / 32; - int bit = irq & 0x1f; - /* Using |= here is detrimental to your health */ - gic_dist->pending_clr[word] = BIT(bit); -} - -static inline void -dist_pending_set(irq_t irq) -{ - int word = irq / 32; - int bit = irq & 0x1f; - gic_dist->pending_set[word] = BIT(bit); -} - -static inline void -dist_enable_clr(irq_t irq) -{ - int word = irq / 32; - int bit = irq & 0x1f; - /* Using |= here is detrimental to your health */ - gic_dist->enable_clr[word] = BIT(bit); -} - -static inline void -dist_enable_set(irq_t irq) -{ - int word = irq / 32; - int bit = irq & 0x1f; - gic_dist->enable_set[word] = BIT(bit); -} - -/** - DONT_TRANSLATE - */ -static void dist_init(void) -{ - int i; - int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1); - gic_dist->enable = 0; - -#if 0 - /* configure to group 0 for security */ - for (i = 0; i < nirqs; i += 32) { - gic_dist->group[i / 32] = 0xffffffff; - } -#endif - - for (i = 0; i < nirqs; i += 32) { - /* disable */ - gic_dist->enable_clr[i / 32] = IRQ_SET_ALL; - /* clear pending */ - gic_dist->pending_clr[i / 32] = IRQ_SET_ALL; - } - - /* reset interrupts priority */ - for (i = 32; i < nirqs; i += 4) { - gic_dist->priority[i / 4] = 0x0; - } - - /* - * reset int target to cpu 0 - * (Should really query which processor we're running on and use that) - */ - for (i = 0; i < nirqs; i += 4) { - gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT; - } - - /* level-triggered, 1-N */ - for (i = 64; i < nirqs; i += 32) { - gic_dist->config[i / 32] = 0; - //gic_dist->config[i / 32] = 0x55555555; - } - /* enable the int controller */ - gic_dist->enable = 1; -} - -/** - DONT_TRANSLATE - */ -static void cpu_iface_init(void) -{ - uint32_t i; - - /* For non-Exynos4, the registers are banked per CPU, need to clear them */ - gic_dist->enable_clr[0] = IRQ_SET_ALL; - gic_dist->pending_clr[0] = IRQ_SET_ALL; - gic_dist->priority[0] = 0x00; - /* put everything in group 0 */ - - /* clear any software generated interrupts */ - for (i = 0; i < 16; i += 4) { - gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL; - } - - gic_cpuiface->icontrol = 0; - gic_cpuiface->pri_msk_c = 0x000000f0; - gic_cpuiface->bp_c = 0x00000003; - - while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) { - gic_cpuiface->eoi = i; - } - gic_cpuiface->icontrol = 0x1; -} - -/** - DONT_TRANSLATE - */ -void initIRQController(void) -{ - dist_init(); - cpu_iface_init(); -} - - - -/* - * The only sane way to get an GIC IRQ number that can be properly - * ACKED later is through the int_ack register. Unfortunately, reading - * this register changes the interrupt state to pending so future - * reads will not return the same value For this reason, we have a - * global variable to store the IRQ number. - */ -static uint32_t active_irq = IRQ_NONE; - -/** - DONT_TRANSLATE - */ -interrupt_t -getActiveIRQ(void) -{ - uint32_t irq; - if (!IS_IRQ_VALID(active_irq)) { - active_irq = gic_cpuiface->int_ack; - } - - if (IS_IRQ_VALID(active_irq)) { - irq = active_irq & IRQ_MASK; - } else { - irq = 1023; - } + RT_ASSERT(index < ARM_GIC_MAX_NR); + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; return irq; } -/* - * GIC has 4 states: pending->active(+pending)->inactive - * seL4 expects two states: active->inactive. - * We ignore the active state in GIC to conform - */ -/** - DONT_TRANSLATE - */ -bool_t -isIRQPending(void) +void arm_gic_ack(rt_uint32_t index, int irq) { - return IS_IRQ_VALID(gic_cpuiface->hi_pend); + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } - -/** - DONT_TRANSLATE - */ -void -maskInterrupt(bool_t disable, interrupt_t irq) +void arm_gic_mask(rt_uint32_t index, int irq) { - if (disable) { - dist_enable_clr(irq); - } else { - dist_enable_set(irq); + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_pending(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n"); +} +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); +#endif + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + cpumask |= cpumask << 24; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + +#if 0 + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; +#endif + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0; + + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x01; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + GIC_CPU_BINPOINT(cpu_base) = 0x7; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_set_group(rt_uint32_t index, int vector, int group) +{ + /* As for GICv2, there are only group0 and group1. */ + RT_ASSERT(group <= 1); + RT_ASSERT(vector < _gic_max_irq); + + if (group == 0) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) &= ~(1 << (vector % 32)); + } + else if (group == 1) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) |= (1 << (vector % 32)); } } -/** - DONT_TRANSLATE - */ -void -ackInterrupt(irq_t irq) -{ - if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) { - return; - } - if (is_irq_edge_triggered(irq)) { - dist_pending_clr(irq); - } - gic_cpuiface->eoi = active_irq; - active_irq = IRQ_NONE; -} - -void -handleSpuriousIRQ(void) -{ -} - -void rt_hw_interrupt_mask(int vector) -{ - maskInterrupt(1, vector); -} - -void rt_hw_interrupt_umask(int vector) -{ - maskInterrupt(0, vector); -} - -int rt_hw_interrupt_get_irq(void) -{ - return getActiveIRQ(); -} - -void rt_hw_interrupt_ack(int fiq_irq) -{ - return ackInterrupt(fiq_irq); -} diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h index a43583bd7c..fa20846ea2 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.h +++ b/libcpu/aarch64/common/gic/gic_pl400.h @@ -1,35 +1,61 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ -#ifndef __ARCH_MACHINE_GIC_PL400_H -#define __ARCH_MACHINE_GIC_PL400_H +#ifndef __GIC_PL400_H__ +#define __GIC_PL400_H__ -#include +#include +#include -typedef uint16_t interrupt_t; -typedef uint16_t irq_t; -typedef uint64_t bool_t; +#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x))) -/** MODIFIES: [*] */ -interrupt_t getActiveIRQ(void); -/** MODIFIES: [*] */ -interrupt_t getPendingIRQ(void); -/** MODIFIES: [*] */ -bool_t isIRQPending(void); -/** MODIFIES: [*] */ -void maskInterrupt(bool_t disable, interrupt_t irq); -/** MODIFIES: [*] */ -void ackInterrupt(irq_t irq); -/** MODIFIES: [*] */ -static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { } +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) -/** MODIFIES: [*] */ -void initIRQController(void); +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) -void handleSpuriousIRQ(void); +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); -void rt_hw_interrupt_umask(int vector); +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +void arm_gic_set_group(rt_uint32_t index, int vector, int group); -int rt_hw_interrupt_get_irq(void); +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); -void rt_hw_interrupt_ack(int fiq_irq); -#endif /* !__ARCH_MACHINE_GIC400_H */ +void arm_gic_clear_active(rt_uint32_t index, int irq); +void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +#endif diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c index d770259d61..6fec968dc2 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.c +++ b/libcpu/aarch64/cortex-a72/interrupt.c @@ -13,8 +13,10 @@ #include #include #include +#include "iomap.h" #define MAX_HANDLERS 256 +#define GIC_ACK_INTID_MASK 0x000003ff #ifdef RT_USING_SMP #define rt_interrupt_nest rt_cpu_self()->irq_nest @@ -41,7 +43,15 @@ void rt_hw_vector_init(void) */ void rt_hw_interrupt_init(void) { - initIRQController(); + + rt_uint32_t gic_cpu_base = 0; + rt_uint32_t gic_dist_base = 0; + + /* initialize ARM GIC */ + gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR; + gic_cpu_base = GIC_PL400_CONTROLLER_PPTR; + arm_gic_dist_init(0, gic_dist_base, 0); + arm_gic_cpu_init(0, gic_cpu_base); } /** @@ -70,4 +80,40 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, } return old_handler; -} \ No newline at end of file +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} From 8a965bce46293b5e8dacaba58dd65976f988c3a7 Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 17 Apr 2020 17:09:57 +0800 Subject: [PATCH 07/27] Update kernel.h thead -> thread --- documentation/doxygen/kernel.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/documentation/doxygen/kernel.h b/documentation/doxygen/kernel.h index b54144780b..527ce835f0 100644 --- a/documentation/doxygen/kernel.h +++ b/documentation/doxygen/kernel.h @@ -87,7 +87,7 @@ * priority would get the resource. * * RT-Thread operating systems supports event/fast event, mail box and message queue. - * - The event mechanism is used to awake a thead by setting one or more corresponding + * - The event mechanism is used to awake a thread by setting one or more corresponding * bit of a binary number when an event ocurs. * - The fast event supports event thread queue. Once a one bit event occurs, the corresponding * blocked thread can be found out timing accurately, then will be waked up. From 8e57dcb723071b37e09a06decddc16569ae79a77 Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 17 Apr 2020 18:39:04 +0800 Subject: [PATCH 08/27] Update tcpsendpacket.c --- examples/network/tcpsendpacket.c | 37 +++++++++++++++++++------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/examples/network/tcpsendpacket.c b/examples/network/tcpsendpacket.c index 75134c19a2..462de6000d 100644 --- a/examples/network/tcpsendpacket.c +++ b/examples/network/tcpsendpacket.c @@ -1,7 +1,7 @@ #include -#include /* Ϊ˽Ҫnetdb.hͷļ */ -#include /* ʹBSD socketҪsocket.hͷļ */ +#include /* 为了解析主机名，需要包含netdb.h头文件 */ +#include /* 使用BSD socket，需要包含socket.h头文件 */ void tcp_senddata(const char *url, int port, int length) { @@ -10,45 +10,52 @@ void tcp_senddata(const char *url, int port, int length) struct sockaddr_in server_addr; rt_uint8_t *buffer_ptr; - /* ͨڲurlhostַ */ + /* 通过函数入口参数url获得host地址（如果是域名，会做域名解析） */ host = gethostbyname(url); - /* һsocketSOCKET_STREAMTCP */ + /* 创建一个socket，类型是SOCKET_STREAM，TCP类型 */ if ((sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) == -1) { - /* socketʧ */ + /* 创建socket失败 */ rt_kprintf("Socket error\n"); return; } - /* ڴ */ + /* 申请内存 */ buffer_ptr = rt_malloc(length); - /* 췢 */ + if(RT_NULL == buffer_ptr) + { + /* 申请内存失败 */ + rt_kprintf("Not enough memory\n"); + return; + } + + /* 构造发送数据 */ for (index = 0; index < length; index ++) buffer_ptr[index] = index & 0xff; timeout = 100; - /* ÷ͳʱʱ100ms */ + /* 设置发送超时时间100ms */ setsockopt(sock, SOL_SOCKET, SO_SNDTIMEO, &timeout, sizeof(timeout)); - /* ʼԤӵķ˵ַ */ + /* 初始化预连接的服务端地址 */ server_addr.sin_family = AF_INET; server_addr.sin_port = htons(port); server_addr.sin_addr = *((struct in_addr *)host->h_addr); rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero)); - /* ӵ */ + /* 连接到服务端 */ err = connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)); rt_kprintf("TCP thread connect error code: %d\n", err); while (1) { - /* ݵsock */ + /* 发送数据到sock连接 */ result = send(sock, buffer_ptr, length, MSG_DONTWAIT); - if (result < 0) //ݷʹ + if (result < 0) //数据发送错误处理 { rt_kprintf("TCP thread send error: %d\n", result); closesocket(sock); - /* رӣ´ */ + /* 关闭连接，重新创建连接 */ rt_thread_delay(10); if ((sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) == -1) @@ -59,7 +66,7 @@ void tcp_senddata(const char *url, int port, int length) } else if (result == 0) { - /* ӡsendֵΪ0ľϢ */ + /* 打印send函数返回值为0的警告信息 */ rt_kprintf("\n Send warning,send function return 0.\r\n"); } } @@ -67,7 +74,7 @@ void tcp_senddata(const char *url, int port, int length) #ifdef RT_USING_FINSH #include -/* tcpclientfinsh shell */ +/* 输出tcpclient函数到finsh shell中 */ FINSH_FUNCTION_EXPORT(tcp_senddata, send a packet through tcp connection); #endif From 993835b5ed834e1ab49e637bcac22019b9bc461b Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 17 Apr 2020 18:44:15 +0800 Subject: [PATCH 09/27] Update tcpsendpacket.c --- examples/network/tcpsendpacket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/network/tcpsendpacket.c b/examples/network/tcpsendpacket.c index 462de6000d..47bb562506 100644 --- a/examples/network/tcpsendpacket.c +++ b/examples/network/tcpsendpacket.c @@ -25,7 +25,7 @@ void tcp_senddata(const char *url, int port, int length) if(RT_NULL == buffer_ptr) { /* 申请内存失败 */ - rt_kprintf("Not enough memory\n"); + rt_kprintf("No memory\n"); return; } From 90f41ef8a2a9e7f71343be12d2f73122e17b1fc2 Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 17 Apr 2020 19:12:18 +0800 Subject: [PATCH 10/27] Update start_gcc.S --- libcpu/arm/s3c24x0/start_gcc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/arm/s3c24x0/start_gcc.S b/libcpu/arm/s3c24x0/start_gcc.S index 4adc458094..cc2b2f6310 100644 --- a/libcpu/arm/s3c24x0/start_gcc.S +++ b/libcpu/arm/s3c24x0/start_gcc.S @@ -191,7 +191,7 @@ reset: copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop /* setup stack */ From 5e507448ee71499aa1fbaa1f273372318f569331 Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 17 Apr 2020 19:18:52 +0800 Subject: [PATCH 11/27] Update start_gcc.S --- libcpu/arm/s3c44b0/start_gcc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S index 65b3d422dd..4c448a344f 100644 --- a/libcpu/arm/s3c44b0/start_gcc.S +++ b/libcpu/arm/s3c44b0/start_gcc.S @@ -107,7 +107,7 @@ reset: copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop #endif From ee4cabe69f90cd2bde042d7d8d114e420b09319f Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 17 Apr 2020 21:07:29 +0800 Subject: [PATCH 12/27] [BSP][Nuclei] Add Nuclei RISC-V Processor support * Nuclei RISC-V Processor support is added both RV32 and RV64 * Nuclei RVSTAR BSP is added, UART driver is added * MSH works well in RVSTAR board --------------------------- Squashed commit of the following: commit b7368bc2ed725c42f9adc297d0e9cf3ed706a520 Author: Huaqi Fang <578567190@qq.com> Date: Fri Apr 17 14:38:54 2020 +0800 [BSP][Nuclei] Pretty source code Signed-off-by: Huaqi Fang <578567190@qq.com> commit 2c42a997f7b5d8aa53bdaf19ccb30596091a112d Author: Huaqi Fang <578567190@qq.com> Date: Thu Apr 16 15:51:03 2020 +0800 [libcpu] Remove ARCH_NUCLEI in libcpu kconfig Signed-off-by: Huaqi Fang <578567190@qq.com> commit 915ad4c076ff3d7cebda896537605e7f7939b7af Author: Huaqi Fang <578567190@qq.com> Date: Thu Apr 16 15:50:00 2020 +0800 [BSP][Nuclei] Remove ARCH_NUCLEI in bsp KConfig Signed-off-by: Huaqi Fang <578567190@qq.com> commit fe43869c79675a25669447d57ea5d77385e07ca5 Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 15 12:43:20 2020 +0800 [BSP][NUCLEI] Simply application main.c Remove previous complicated application of gd32vf103_rvstar Signed-off-by: Huaqi Fang <578567190@qq.com> commit 8fd31727bc7ff51c83a3c47840cff1bfb100c0ba Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 15 12:38:04 2020 +0800 [BSP][NUCLEI] Format application and board source code Signed-off-by: Huaqi Fang <578567190@qq.com> commit b432308b20cdf24dfcc1398511d1d83bce6a9df2 Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 15 11:58:28 2020 +0800 [BSP][Nuclei] Format source code of drivers of gd32vf103 Signed-off-by: Huaqi Fang <578567190@qq.com> commit 7366173d749d8a51ed8d48eca09007d27aee8ad8 Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 15 11:54:02 2020 +0800 [LIBCPU][NUCLEI] Optimize nuclei cpu portable code Signed-off-by: Huaqi Fang <578567190@qq.com> commit 8c2cd4745b7279a6721946d119441bbf7fd1a9c2 Author: Huaqi Fang <578567190@qq.com> Date: Tue Apr 14 15:45:42 2020 +0800 nuclei: Update README.md Signed-off-by: Huaqi Fang <578567190@qq.com> commit fa8a2f24ea5e4dbce714ffda16c1ce558e5b5ddb Author: Huaqi Fang <578567190@qq.com> Date: Tue Apr 14 14:06:54 2020 +0800 nuclei: Add gpio driver not tested Signed-off-by: Huaqi Fang <578567190@qq.com> commit 1be40bc50be43dfcdd105291bd24355498f9fef3 Author: Huaqi Fang <578567190@qq.com> Date: Thu Apr 9 14:55:22 2020 +0800 Nuclei: Update README.md Signed-off-by: Huaqi Fang <578567190@qq.com> commit 4c8beb204b7ee3e38c04e1f23a1f7e4ce48aa196 Author: Huaqi Fang <578567190@qq.com> Date: Thu Apr 9 10:20:25 2020 +0800 Nuclei: Change idle stack size from 256 to 396 bytes If changed to 396 bytes, then debug optimization level changed from O2 to O0, and the application can run successfully without stack overflow issue of tidle0 task warning: tidle0 stack is close to end of stack address. Signed-off-by: Huaqi Fang <578567190@qq.com> commit da2bcf5c56ef32b611405a8e591ecd3f1e598b11 Author: Huaqi Fang <578567190@qq.com> Date: Thu Apr 9 10:11:40 2020 +0800 nuclei: Remove unused kconfig Signed-off-by: Huaqi Fang <578567190@qq.com> commit 0b932c677a7934d60e70da141744790aec202ef6 Author: Huaqi Fang <578567190@qq.com> Date: Thu Apr 9 09:32:22 2020 +0800 nuclei: optimize drivers support Signed-off-by: Huaqi Fang <578567190@qq.com> commit 0431f6f01f6efab2900de552abede83639415431 Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 8 19:28:02 2020 +0800 tools: Update mkdist.py for nuclei bsp Signed-off-by: Huaqi Fang <578567190@qq.com> commit 0e1f502edfddff93a4a66c041be68560ef4828eb Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 8 18:46:58 2020 +0800 nuclei: optimize rvstar support directory Signed-off-by: Huaqi Fang <578567190@qq.com> commit 1131f6e6483d8f2fbafe07f4e598fc8f802ee85d Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 8 18:37:24 2020 +0800 nuclei: update kconfig Signed-off-by: Huaqi Fang <578567190@qq.com> commit ad81c1d3bf9d80d2b561c94e903e7ce4ca2c68c6 Author: Huaqi Fang <578567190@qq.com> Date: Wed Apr 8 15:43:00 2020 +0800 nuclei: Rename board name Signed-off-by: Huaqi Fang <578567190@qq.com> commit d780138a1abf5da5097cc89e6a428ebeae06f284 Author: Huaqi Fang <578567190@qq.com> Date: Tue Apr 7 09:36:19 2020 +0800 libcpu: Add Nuclei arch option in KConfig Signed-off-by: Huaqi Fang <578567190@qq.com> commit 60320d34b1d88315efe1b566fd6bc75c69851f06 Author: Huaqi Fang <578567190@qq.com> Date: Fri Apr 3 16:51:01 2020 +0800 nuclei: Update nuclei sdk of rt-thread support Signed-off-by: Huaqi Fang <578567190@qq.com> commit a042b806efe0ea3bc9dba80ebc7696e5941ba35f Author: Huaqi Fang <578567190@qq.com> Date: Fri Apr 3 11:34:09 2020 +0800 nuclei: modify application for not print anything Signed-off-by: Huaqi Fang <578567190@qq.com> commit 2a9603adcb584b29886a2b93ded2473f4e8bffb1 Author: Huaqi Fang <578567190@qq.com> Date: Fri Apr 3 11:31:01 2020 +0800 nuclei: Add .gitignore for nuclei bsp Signed-off-by: Huaqi Fang <578567190@qq.com> commit 34aaf6aebae75c3ee9d38cc17e6bdb826ed9e357 Author: Huaqi Fang <578567190@qq.com> Date: Fri Apr 3 11:28:06 2020 +0800 nuclei_sdk: update link script of rvstar to contain rt-thread needed sections /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) __fsymtab_end = .; . = ALIGN(4); __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; The above code placed in rodata section Signed-off-by: Huaqi Fang <578567190@qq.com> commit 3451466e9d8da3c3c8a631be69f3c7a5e6220c21 Author: Huaqi Fang <578567190@qq.com> Date: Fri Apr 3 10:04:42 2020 +0800 bsp: Add initial commit of nuclei rvstar board bsp Signed-off-by: Huaqi Fang <578567190@qq.com> Signed-off-by: Huaqi Fang <578567190@qq.com> --- bsp/nuclei/.gitignore | 26 + bsp/nuclei/gd32vf103_rvstar/.config | 453 +++++++++++++++ bsp/nuclei/gd32vf103_rvstar/Kconfig | 28 + bsp/nuclei/gd32vf103_rvstar/README.md | 209 +++++++ bsp/nuclei/gd32vf103_rvstar/SConscript | 17 + bsp/nuclei/gd32vf103_rvstar/SConstruct | 85 +++ .../gd32vf103_rvstar/applications/SConscript | 11 + .../gd32vf103_rvstar/applications/main.c | 19 + bsp/nuclei/gd32vf103_rvstar/board/Kconfig | 47 ++ bsp/nuclei/gd32vf103_rvstar/board/SConscript | 11 + bsp/nuclei/gd32vf103_rvstar/board/board.c | 67 +++ bsp/nuclei/gd32vf103_rvstar/board/board.h | 21 + bsp/nuclei/gd32vf103_rvstar/rtconfig.h | 181 ++++++ bsp/nuclei/gd32vf103_rvstar/rtconfig.py | 58 ++ .../gd32vf103/HAL_Drivers/SConscript | 21 + .../gd32vf103/HAL_Drivers/drv_config.h | 26 + .../gd32vf103/HAL_Drivers/drv_gpio.c | 520 ++++++++++++++++++ .../gd32vf103/HAL_Drivers/drv_gpio.h | 51 ++ .../gd32vf103/HAL_Drivers/drv_usart.c | 347 ++++++++++++ .../gd32vf103/HAL_Drivers/drv_usart.h | 36 ++ libcpu/risc-v/SConscript | 3 +- libcpu/risc-v/nuclei/SConscript | 14 + libcpu/risc-v/nuclei/context_gcc.S | 188 +++++++ libcpu/risc-v/nuclei/cpuport.c | 259 +++++++++ libcpu/risc-v/nuclei/cpuport.h | 40 ++ libcpu/risc-v/nuclei/interrupt_gcc.S | 218 ++++++++ tools/mkdist.py | 7 + 27 files changed, 2962 insertions(+), 1 deletion(-) create mode 100644 bsp/nuclei/.gitignore create mode 100644 bsp/nuclei/gd32vf103_rvstar/.config create mode 100644 bsp/nuclei/gd32vf103_rvstar/Kconfig create mode 100644 bsp/nuclei/gd32vf103_rvstar/README.md create mode 100644 bsp/nuclei/gd32vf103_rvstar/SConscript create mode 100644 bsp/nuclei/gd32vf103_rvstar/SConstruct create mode 100644 bsp/nuclei/gd32vf103_rvstar/applications/SConscript create mode 100644 bsp/nuclei/gd32vf103_rvstar/applications/main.c create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/Kconfig create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/SConscript create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/board.c create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/board.h create mode 100644 bsp/nuclei/gd32vf103_rvstar/rtconfig.h create mode 100644 bsp/nuclei/gd32vf103_rvstar/rtconfig.py create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h create mode 100644 libcpu/risc-v/nuclei/SConscript create mode 100644 libcpu/risc-v/nuclei/context_gcc.S create mode 100644 libcpu/risc-v/nuclei/cpuport.c create mode 100644 libcpu/risc-v/nuclei/cpuport.h create mode 100644 libcpu/risc-v/nuclei/interrupt_gcc.S diff --git a/bsp/nuclei/.gitignore b/bsp/nuclei/.gitignore new file mode 100644 index 0000000000..975dcc6995 --- /dev/null +++ b/bsp/nuclei/.gitignore @@ -0,0 +1,26 @@ +*.i +*.o +*.d +*.elf +*.diss +*.map +*.bin +*.log +.vscode + +*.dump +*.verilog + +*.swp +*.swo + +prebuilt_tools/ +setup_config.sh +setup_config.bat + +tags +TAGS +TAG +CTAGS +Makefile.local +Makefile.global diff --git a/bsp/nuclei/gd32vf103_rvstar/.config b/bsp/nuclei/gd32vf103_rvstar/.config new file mode 100644 index 0000000000..c68135acc4 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/.config @@ -0,0 +1,453 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=396 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +CONFIG_PKG_USING_NUCLEI_SDK=y +CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk" +# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set +CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y +CONFIG_PKG_NUCLEI_SDK_VER="latest" + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_GD32VF103V=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_UART_CONSOLE=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_UART4=y + +# +# Board extended module Drivers +# +CONFIG_SOC_GD32VF103=y diff --git a/bsp/nuclei/gd32vf103_rvstar/Kconfig b/bsp/nuclei/gd32vf103_rvstar/Kconfig new file mode 100644 index 0000000000..fb1ab0ffd5 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/Kconfig @@ -0,0 +1,28 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + +config SOC_GD32VF103 + bool + select ARCH_RISCV32 + select PKG_USING_NUCLEI_SDK + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/nuclei/gd32vf103_rvstar/README.md b/bsp/nuclei/gd32vf103_rvstar/README.md new file mode 100644 index 0000000000..f9575aa2ee --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/README.md @@ -0,0 +1,209 @@ +# 芯来科技RVSTAR开发板 # + +## 简介 + +**RVSTAR开发板** 是由芯来科技公司推出的基于采用芯来科技RISC-V架构处理器芯片的GD32VF103的开发板。 + +更多关于 **RVSTAR开发板** 开发板的详细资料请参见 [RVSTAR开发板快速入门](https://www.rvmcu.com/quickstart-quickstart-index-u-RV_STAR.html) + +### 板载资源 + +| 硬件 | 描述 | +| --- | --- | +| 内核 | Nuclei N205 | +| 架构 | 32-bit RV32IMAC | +| 主频 | 108 MHz | + +## 工具安装 + +### 安装工具链 + +请根据[安装Nuclei RISC-V GCC Toolchain和OpenOCD](https://doc.nucleisys.com/nuclei_sdk/quickstart.html#setup-tools-and-environment) 来安装依赖的工具。 + +### 添加环境变量 + +将Nuclei RISC-V GCC Toolchain和OpenOCD的环境变量进行设置。 + +#### Windows + +假设工具安装在 **D:\Software\Nuclei**目录下, 则可以修改系统环境变量**PATH**, +将**D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;**增加到**PATH**中。 + +或者在ENV工具命令行中运行 + +~~~cmd +set PATH=D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;%PATH% +~~~ + +#### Linux + +假设工具安装在 **~/Software/Nuclei**目录下, 通过在Linux的``.bashrc``增加如下一行代码 +来添加环境变量。 + +~~~bash +export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH +~~~ + +或者在ENV工具命令行中运行 + +~~~bash +export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH +~~~ + +**注意**: 对应的RISC-V GCC和OPENOCD的路径请替换成自己安装的路径。 + +## 烧写及执行 + +### [驱动设置](https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html#on-board-debugger-driver) + +### 编译程序 + +下载好[RT-Thread](https://github.com/RT-Thread/rt-thread)的代码和[ENV工具](https://www.rt-thread.org/document/site/tutorial/env-video/)以后。 + +按照ENV工具的教程, 在**rt-thread\bsp\nuclei\gd32vf103_rvstar**目录打开ENV工具命令行。 + +**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。 + +1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包 +2. **可选**: 运行 ``menuconfig``来进行内核配置 +3. 运行 ``scons -c``清理之前的编译结果 +4. 运行 ``scons``来进行代码的编译 + +### 下载程序 + +在保证程序能够正常编译后, 在相同ENV终端执行``scons --run upload``进行代码的下载。 + +正常下载的输出如下: + +~~~ +scons: Reading SConscript files ... +Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip +Upload application rtthread.elf using openocd and gdb +riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240" -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg" --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" -ex "monitor resume" -ex "monitor shutdown" -ex "quit" +D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory. + +Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:251 +251 if (idle_hook_list[i] != RT_NULL) +cleared protection for sectors 0 through 127 on flash bank 0 + +Loading section .init, size 0x264 lma 0x8000000 +Loading section .text, size 0x140de lma 0x8000280 +Loading section .rodata, size 0x37c0 lma 0x8014360 +Loading section .data, size 0x404 lma 0x8017b20 +Start address 0x800015c, load size 98054 +Transfer rate: 8 KB/sec, 10894 bytes/write. +shutdown command invoked +A debugging session is active. + + Inferior 1 [Remote target] will be detached. + +Quit anyway? (y or n) [answered Y; input not from terminal] +Remote communication error. Target disconnected.: Success. +~~~ + +下载程序之后, 连接串口(115200-N-8-1), 可以看到 RT-Thread 的输出信息： + +``` +initialize rti_board_start:0 done + + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 9 2020 + 2006 - 2020 Copyright by rt-thread team +do components initialization. +initialize rti_board_end:0 done +initialize dfs_init:0 done +initialize libc_system_init:0 done +initialize finsh_system_init:0 done +msh /> +``` + +在串口终端(我这里使用的是TeraTerm)输入``ps``即可查看当前线程工作情况: + +~~~ +msh />ps +thread pri status sp stack size max used left tick error +-------- --- ------- ---------- ---------- ------ ---------- --- +thread01 19 suspend 0x00000158 0x0000018c 87% 0x00000005 000 +thread00 19 suspend 0x00000158 0x0000018c 87% 0x00000005 000 +tshell 20 running 0x00000258 0x00001000 18% 0x00000004 000 +tidle0 31 ready 0x000000a8 0x0000018c 59% 0x0000000e 000 +timer 4 suspend 0x000000f8 0x00000200 49% 0x00000009 000 +main 10 suspend 0x00000168 0x00000800 36% 0x00000006 000 +msh /> +~~~ + +### 调试程序 + +在保证程序编译成功后, 在相同ENV终端执行``scons --run debug``进行代码在命令行下进行GDB调试。 + +正常的调试输出如下： + +~~~ +scons: Reading SConscript files ... +Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip +Debug application rtthread.elf using openocd and gdb +riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240" -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg" +D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory. +GNU gdb (GDB) 8.3.0.20190516-git +Copyright (C) 2019 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "--host=i686-w64-mingw32 --target=riscv-nuclei-elf". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word"... +Reading symbols from rtthread.elf... +Remote debugging using | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:249 +249 for (i = 0; i < RT_IDLE_HOOK_LIST_SIZE; i++) +(gdb) +(gdb) b main.c:35 +Breakpoint 1 at 0x8000290: file applications\main.c, line 35. +(gdb) c +Continuing. +Note: automatically using hardware breakpoints for read-only addresses. + +Breakpoint 1, thread_entry (parameter=0x0) at applications\main.c:35 +35 rt_thread_mdelay(500); +(gdb) +~~~ + +调试例子参见如下文档: + +* https://doc.nucleisys.com/nuclei_sdk/quickstart.html#debug-application + +为了更方便的进行调试, 也可以下载**Nuclei Studio**集成开发环境, 创建一个Debug Configuration, 选择编译好的 +ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nuclei\gd32vf103_rvstar\packages\nuclei_sdk-latest\SoC\gd32vf103\Board\gd32vf103v_rvstar\openocd_gd32vf103.cfg** + + +## 驱动支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | RV-STAR板载串口是UART4 | + +**注:** + +- 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。 +- 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。 + +## 联系人信息 + +维护人： +- [fanghuaqi](https://github.com/fanghuaqi) + diff --git a/bsp/nuclei/gd32vf103_rvstar/SConscript b/bsp/nuclei/gd32vf103_rvstar/SConscript new file mode 100644 index 0000000000..014c428d0a --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuclei/gd32vf103_rvstar/SConstruct b/bsp/nuclei/gd32vf103_rvstar/SConstruct new file mode 100644 index 0000000000..7adcd69070 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/SConstruct @@ -0,0 +1,85 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +bsp_library_type = rtconfig.NUCLEI_SDK_SOC +rtconfig.BSP_LIBRARY_TYPE = bsp_library_type + +openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/') + +# include hal drivers +hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript') + +if os.path.isfile(hal_sconscript): + objs.extend(SConscript(hal_sconscript)) + +# make a building +DoBuilding(TARGET, objs) + +# Run upload or debug if --run=upload or --upload=debug +run_target = GetOption('run') +SUPPORT_RUN_TARGETS = ["upload", "debug"] +if run_target in SUPPORT_RUN_TARGETS: + if os.path.isfile(TARGET): + if run_target == "upload": + upload_cmd = '{} {} -ex "set remotetimeout 240" \ + -ex "target remote | openocd --pipe -f {}" \ + --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" \ + -ex "monitor resume" -ex "monitor shutdown" -ex "quit"'.format(GDB, TARGET, openocd_cfg) + print("Upload application {} using openocd and gdb".format(TARGET)) + print(upload_cmd) + os.system(upload_cmd) + elif run_target == "debug": + debug_cmd = '{} {} -ex "set remotetimeout 240" \ + -ex "target remote | openocd --pipe -f {}"'.format(GDB, TARGET, openocd_cfg) + print("Debug application {} using openocd and gdb".format(TARGET)) + print(debug_cmd) + os.system(debug_cmd) + else: + print(TARGET + ' not exist, please run scons first!!') + exit(0) diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/SConscript b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript new file mode 100644 index 0000000000..ef1c39fd83 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, ] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/main.c b/bsp/nuclei/gd32vf103_rvstar/applications/main.c new file mode 100644 index 0000000000..7da5f0da45 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-15 hqfang first version + */ + +#include +#include + +int main(int argc, char *argv[]) +{ + return RT_EOK; +} + +/******************** end of file *******************/ \ No newline at end of file diff --git a/bsp/nuclei/gd32vf103_rvstar/board/Kconfig b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig new file mode 100644 index 0000000000..5165ac7629 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig @@ -0,0 +1,47 @@ +menu "Hardware Drivers Config" + +config SOC_GD32VF103V + bool + select SOC_SERIES_GD32VF103V + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_UART_CONSOLE + bool "Enable UART CONSOLE" + select BSP_USING_UART + select BSP_USING_UART4 + default y +endmenu + +menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + config BSP_USING_UART1 + bool "Enable UART1" + default n + config BSP_USING_UART2 + bool "Enable UART2" + default n + config BSP_USING_UART3 + bool "Enable UART3" + default n + config BSP_USING_UART4 + bool "Enable UART4" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nuclei/gd32vf103_rvstar/board/SConscript b/bsp/nuclei/gd32vf103_rvstar/board/SConscript new file mode 100644 index 0000000000..148c99f42c --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.c b/bsp/nuclei/gd32vf103_rvstar/board/board.c new file mode 100644 index 0000000000..7dad875006 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/board.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-02 hqfang first version + * + */ + +#include +#include +#include "board.h" +#include "cpuport.h" + +#ifdef RT_USING_SERIAL + #include +#endif + +/** _end symbol defined in linker script of Nuclei SDK */ +extern void *_end; + +/** _heap_end symbol defined in linker script of Nuclei SDK */ +extern void *_heap_end; +#define HEAP_BEGIN &_end +#define HEAP_END &_heap_end + +/* + * - Implemented and defined in Nuclei SDK system_.c file + * - Required macro NUCLEI_BANNER set to 0 + */ +extern void _init(void); + +/** + * @brief Setup hardware board for rt-thread + * + */ +void rt_hw_board_init(void) +{ + /* OS Tick Configuration */ + rt_hw_ticksetup(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END); +#endif + + _init(); // __libc_init_array is not used in RT-Thread + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/******************** end of file *******************/ + diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.h b/bsp/nuclei/gd32vf103_rvstar/board/board.h new file mode 100644 index 0000000000..4e571e3ee2 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/board.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-02 hqfang first version + * + */ + +#ifndef __BOARD__ +#define __BOARD__ + +#include "nuclei_sdk_hal.h" + +void rt_hw_board_init(void); + +#endif /* __BOARD__ */ + +/******************** end of file *******************/ diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.h b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h new file mode 100644 index 0000000000..2498e39e9d --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h @@ -0,0 +1,181 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 396 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_DEBUG_INIT_CONFIG +#define RT_DEBUG_INIT 1 + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40003 +#define ARCH_RISCV +#define ARCH_RISCV32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + +#define PKG_USING_NUCLEI_SDK +#define PKG_USING_NUCLEI_SDK_LATEST_VERSION + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* Hardware Drivers Config */ + +#define SOC_GD32VF103V + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_UART_CONSOLE + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART4 + +/* Board extended module Drivers */ + +#define SOC_GD32VF103 + +#endif diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.py b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py new file mode 100644 index 0000000000..8136b392f8 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py @@ -0,0 +1,58 @@ +import os + +# toolchains options +ARCH='risc-v' +CPU='nuclei' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'D:/Software/Nuclei/gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +# if os.getenv('RTT_EXEC_PATH'): +# EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# Fixed configurations below +NUCLEI_SDK_SOC = "gd32vf103" +NUCLEI_SDK_BOARD = "gd32vf103v_rvstar" +NUCLEI_SDK_DOWNLOAD = "flashxip" +NUCLEI_SDK_CORE = "n205" + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv-nuclei-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + CFLAGS = ' -ffunction-sections -fdata-sections -fno-common ' + AFLAGS = CFLAGS + LFLAGS = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' + LFLAGS += ' -Wl,-cref,-Map=rtthread.map' + LFLAGS += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek ' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + AFLAGS += ' -ggdb' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript new file mode 100644 index 0000000000..4761127102 --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript @@ -0,0 +1,21 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h new file mode 100644 index 0000000000..bb24afa19e --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-08 hqfang first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c new file mode 100644 index 0000000000..75ab81f18e --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c @@ -0,0 +1,520 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-09 hqfang first version + */ + +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +static const struct pin_index pins[] = +{ + + __GD32_PIN(0, A, 0), + __GD32_PIN(1, A, 1), + __GD32_PIN(2, A, 2), + __GD32_PIN(3, A, 3), + __GD32_PIN(4, A, 4), + __GD32_PIN(5, A, 5), + __GD32_PIN(6, A, 6), + __GD32_PIN(7, A, 7), + __GD32_PIN(8, A, 8), + __GD32_PIN(9, A, 9), + __GD32_PIN(10, A, 10), + __GD32_PIN(11, A, 11), + __GD32_PIN(12, A, 12), + __GD32_PIN(13, A, 13), + __GD32_PIN(14, A, 14), + __GD32_PIN(15, A, 15), + + __GD32_PIN(16, B, 0), + __GD32_PIN(17, B, 1), + __GD32_PIN(18, B, 2), + __GD32_PIN(19, B, 3), + __GD32_PIN(20, B, 4), + __GD32_PIN(21, B, 5), + __GD32_PIN(22, B, 6), + __GD32_PIN(23, B, 7), + __GD32_PIN(24, B, 8), + __GD32_PIN(25, B, 9), + __GD32_PIN(26, B, 10), + __GD32_PIN(27, B, 11), + __GD32_PIN(28, B, 12), + __GD32_PIN(29, B, 13), + __GD32_PIN(30, B, 14), + __GD32_PIN(31, B, 15), + + __GD32_PIN(32, C, 0), + __GD32_PIN(33, C, 1), + __GD32_PIN(34, C, 2), + __GD32_PIN(35, C, 3), + __GD32_PIN(36, C, 4), + __GD32_PIN(37, C, 5), + __GD32_PIN(38, C, 6), + __GD32_PIN(39, C, 7), + __GD32_PIN(40, C, 8), + __GD32_PIN(41, C, 9), + __GD32_PIN(42, C, 10), + __GD32_PIN(43, C, 11), + __GD32_PIN(44, C, 12), + __GD32_PIN(45, C, 13), + __GD32_PIN(46, C, 14), + __GD32_PIN(47, C, 15), + + __GD32_PIN(48, D, 0), + __GD32_PIN(49, D, 1), + __GD32_PIN(50, D, 2), + __GD32_PIN(51, D, 3), + __GD32_PIN(52, D, 4), + __GD32_PIN(53, D, 5), + __GD32_PIN(54, D, 6), + __GD32_PIN(55, D, 7), + __GD32_PIN(56, D, 8), + __GD32_PIN(57, D, 9), + __GD32_PIN(58, D, 10), + __GD32_PIN(59, D, 11), + __GD32_PIN(60, D, 12), + __GD32_PIN(61, D, 13), + __GD32_PIN(62, D, 14), + __GD32_PIN(63, D, 15), + + __GD32_PIN(64, E, 0), + __GD32_PIN(65, E, 1), + __GD32_PIN(66, E, 2), + __GD32_PIN(67, E, 3), + __GD32_PIN(68, E, 4), + __GD32_PIN(69, E, 5), + __GD32_PIN(70, E, 6), + __GD32_PIN(71, E, 7), + __GD32_PIN(72, E, 8), + __GD32_PIN(73, E, 9), + __GD32_PIN(74, E, 10), + __GD32_PIN(75, E, 11), + __GD32_PIN(76, E, 12), + __GD32_PIN(77, E, 13), + __GD32_PIN(78, E, 14), + __GD32_PIN(79, E, 15), +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_9_IRQn}, + {GPIO_PIN_6, EXTI5_9_IRQn}, + {GPIO_PIN_7, EXTI5_9_IRQn}, + {GPIO_PIN_8, EXTI5_9_IRQn}, + {GPIO_PIN_9, EXTI5_9_IRQn}, + {GPIO_PIN_10, EXTI10_15_IRQn}, + {GPIO_PIN_11, EXTI10_15_IRQn}, + {GPIO_PIN_12, EXTI10_15_IRQn}, + {GPIO_PIN_13, EXTI10_15_IRQn}, + {GPIO_PIN_14, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + gpio_bit_write(index->gpio, index->pin, (bit_status)value); +} + +static int gd32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = gpio_input_bit_get(index->gpio, index->pin); + + return value; +} + +static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + rt_uint32_t pin_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + pin_mode = GPIO_MODE_OUT_PP; + + switch (mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + pin_mode = GPIO_MODE_OUT_PP; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + pin_mode = GPIO_MODE_OUT_OD; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + pin_mode = GPIO_MODE_IN_FLOATING; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + pin_mode = GPIO_MODE_IPU; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + pin_mode = GPIO_MODE_IPD; + break; + default: + break; + } + + gpio_init(index->gpio, pin_mode, GPIO_OSPEED_50MHZ, index->pin); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + exti_trig_type_enum trigger_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + /* connect EXTI line to GPIO pin */ + gpio_exti_source_select(index->gpio, index->pin); + + /* configure EXTI line */ + exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); + exti_interrupt_flag_clear((exti_line_enum)(index->pin)); + + /* enable and set interrupt priority */ + ECLIC_SetShvIRQ(irqmap->irqno, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(irqmap->irqno, 1); + ECLIC_EnableIRQ(irqmap->irqno); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_EINVAL; + } + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { + ECLIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + ECLIC_DisableIRQ(irqmap->irqno); + } + } + else + { + ECLIC_DisableIRQ(irqmap->irqno); + } + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _gd32_pin_ops = +{ + gd32_pin_mode, + gd32_pin_write, + gd32_pin_read, + gd32_pin_attach_irq, + gd32_pin_dettach_irq, + gd32_pin_irq_enable, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) +{ + if (RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) + { + pin_irq_hdr(exti_line); + exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); + } +} + +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(0); + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(1); + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(2); + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(3); + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(4); + rt_interrupt_leave(); +} +void EXTI5_9_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(5); + GD32_GPIO_EXTI_IRQHandler(6); + GD32_GPIO_EXTI_IRQHandler(7); + GD32_GPIO_EXTI_IRQHandler(8); + GD32_GPIO_EXTI_IRQHandler(9); + rt_interrupt_leave(); +} +void EXTI10_15_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(10); + GD32_GPIO_EXTI_IRQHandler(11); + GD32_GPIO_EXTI_IRQHandler(12); + GD32_GPIO_EXTI_IRQHandler(13); + GD32_GPIO_EXTI_IRQHandler(14); + GD32_GPIO_EXTI_IRQHandler(15); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + rcu_periph_clock_enable(RCU_AF); + return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h new file mode 100644 index 0000000000..93d24a8317 --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 balanceTWK first version + * 2020-04-15 hqfang Modify for gd32vf103 + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include +#include + +#define __GD32_PORT(port) GPIO##port + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN) + +#define __GD32_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ + } + +#define __GD32_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + +/* GD32 GPIO driver */ +struct pin_index +{ + int index; + uint32_t gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +int rt_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c new file mode 100644 index 0000000000..00fac33b3e --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 tyustli first version + * 2020-04-02 hqfang modified for Nuclei + */ + +#include + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \ + && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum +{ +#ifdef BSP_USING_UART0 + GDUART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + GDUART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + GDUART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + GDUART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + GDUART4_INDEX, +#endif +}; + +static struct gd32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART0 + { + "uart0", + USART0, + USART0_IRQn, + }, +#endif +#ifdef BSP_USING_UART1 + { + "uart1", + USART1, + USART1_IRQn, + }, +#endif +#ifdef BSP_USING_UART2 + { + "uart2", + USART2, + USART2_IRQn, + }, +#endif +#ifdef BSP_USING_UART3 + { + "uart3", + USART3, + USART3_IRQn, + }, +#endif +#ifdef BSP_USING_UART4 + { + "uart4", + UART4, + UART4_IRQn, + }, +#endif +}; + +static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static rt_err_t gd32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + usart_deinit(usart->uart_base); + usart_baudrate_set(usart->uart_base, cfg->baud_rate); + + switch (cfg->data_bits) + { + case DATA_BITS_8: + usart_word_length_set(usart->uart_base, USART_WL_8BIT); + break; + + case DATA_BITS_9: + usart_word_length_set(usart->uart_base, USART_WL_9BIT); + break; + default: + usart_word_length_set(usart->uart_base, USART_WL_8BIT); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + usart_stop_bit_set(usart->uart_base, USART_STB_1BIT); + break; + case STOP_BITS_2: + usart_stop_bit_set(usart->uart_base, USART_STB_2BIT); + break; + default: + usart_stop_bit_set(usart->uart_base, USART_STB_1BIT); + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + usart_parity_config(usart->uart_base, USART_PM_NONE); + break; + case PARITY_ODD: + usart_parity_config(usart->uart_base, USART_PM_ODD); + break; + case PARITY_EVEN: + usart_parity_config(usart->uart_base, USART_PM_EVEN); + break; + default: + usart_parity_config(usart->uart_base, USART_PM_NONE); + break; + } + usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(usart->uart_base, USART_RTS_DISABLE); + usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE); + usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE); + usart_enable(usart->uart_base); + + return RT_EOK; +} + +static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, + void *arg) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + ECLIC_DisableIRQ(usart->irqn); + usart_interrupt_disable(usart->uart_base, USART_INT_RBNE); + break; + case RT_DEVICE_CTRL_SET_INT: + ECLIC_EnableIRQ(usart->irqn); + /* enable USART0 receive interrupt */ + usart_interrupt_enable(usart->uart_base, USART_INT_RBNE); + break; + } + + return RT_EOK; +} + +static int gd32_putc(struct rt_serial_device *serial, char ch) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + usart_data_transmit(usart->uart_base, (uint8_t) ch); + while (usart_flag_get(usart->uart_base, USART_FLAG_TBE) == RESET); + + return 1; +} + +static int gd32_getc(struct rt_serial_device *serial) +{ + int ch; + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + ch = -1; + if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)) + { + ch = usart_data_receive(usart->uart_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control, + gd32_putc, gd32_getc, + RT_NULL +}; + +static void usart_isr(struct rt_serial_device *serial) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE) + != RESET) + && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE); + usart_flag_clear(usart->uart_base, USART_FLAG_RBNE); + } + else + { + if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET) + { + usart_flag_clear(usart->uart_base, USART_FLAG_CTSF); + } + + if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET) + { + usart_flag_clear(usart->uart_base, USART_FLAG_LBDF); + } + + if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET) + { + usart_flag_clear(usart->uart_base, USART_FLAG_TC); + } + } +} + +#ifdef BSP_USING_UART0 + +void USART0_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART0_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART1 + +void USART1_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART1_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART2 + +void USART2_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART2_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART3 + +void UART3_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART3_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART4 + +void UART4_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART4_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num; + int index; + + obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (index = 0; index < obj_num; index++) + { + /* init UART object */ + uart_obj[index].config = &uart_config[index]; + uart_obj[index].serial.ops = &gd32_uart_ops; + uart_obj[index].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[index].serial, + uart_obj[index].config->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ + +/******************** end of file *******************/ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h new file mode 100644 index 0000000000..176720c4a2 --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-15 hqfang first version + */ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include +#include +#include + +/* gd32 config class */ +struct gd32_uart_config +{ + const char *name; + uint32_t uart_base; + IRQn_Type irqn; +}; + +/* gd32 uart dirver class */ +struct gd32_uart +{ + struct gd32_uart_config *config; + struct rt_serial_device serial; +}; + +int rt_hw_usart_init(void); + +#endif /* __DRV_USART_H__ */ + +/******************* end of file *******************/ diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 640e46a4fb..024cc5ba44 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -10,7 +10,8 @@ group = [] list = os.listdir(cwd) # add common code files -group = group + SConscript(os.path.join('common', 'SConscript')) +if rtconfig.CPU != "nuclei": + group = group + SConscript(os.path.join('common', 'SConscript')) # cpu porting code files group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/risc-v/nuclei/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/nuclei/context_gcc.S b/libcpu/risc-v/nuclei/context_gcc.S new file mode 100644 index 0000000000..fda453940d --- /dev/null +++ b/libcpu/risc-v/nuclei/context_gcc.S @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 Huaqi First Nuclei RISC-V porting implementation + */ + +#include "riscv_encoding.h" + +#ifndef __riscv_32e +#define RT_SAVED_REGNUM 30 +#else +#define RT_SAVED_REGNUM 14 +#endif + +#define RT_CONTEXT_SIZE (RT_SAVED_REGNUM * REGBYTES) + + .extern rt_interrupt_from_thread + .extern rt_interrupt_to_thread + + +.section .text + + +/* + * void rt_hw_context_switch_to(rt_ubase_t to); + * a0 --> to_thread + */ + .globl rt_hw_context_switch_to + +/* Start the first task. This also clears the bit that indicates the FPU is + in use in case the FPU was used before the scheduler was started - which + would otherwise result in the unnecessary leaving of space in the stack + for lazy saving of FPU registers. */ +.align 3 +rt_hw_context_switch_to: + /* Setup Interrupt Stack using + The stack that was used by main() + before the scheduler is started is + no longer required after the scheduler is started. + Interrupt stack pointer is stored in CSR_MSCRATCH */ + la t0, _sp + csrw CSR_MSCRATCH, t0 + LOAD sp, 0x0(a0) /* Read sp from first TCB member(a0) */ + + /* Pop PC from stack and set MEPC */ + LOAD t0, 0 * REGBYTES(sp) + csrw CSR_MEPC, t0 + /* Pop mstatus from stack and set it */ + LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + csrw CSR_MSTATUS, t0 + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + LOAD x1, 1 * REGBYTES(sp) /* RA */ + LOAD x5, 2 * REGBYTES(sp) + LOAD x6, 3 * REGBYTES(sp) + LOAD x7, 4 * REGBYTES(sp) + LOAD x8, 5 * REGBYTES(sp) + LOAD x9, 6 * REGBYTES(sp) + LOAD x10, 7 * REGBYTES(sp) + LOAD x11, 8 * REGBYTES(sp) + LOAD x12, 9 * REGBYTES(sp) + LOAD x13, 10 * REGBYTES(sp) + LOAD x14, 11 * REGBYTES(sp) + LOAD x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 13 * REGBYTES(sp) + LOAD x17, 14 * REGBYTES(sp) + LOAD x18, 15 * REGBYTES(sp) + LOAD x19, 16 * REGBYTES(sp) + LOAD x20, 17 * REGBYTES(sp) + LOAD x21, 18 * REGBYTES(sp) + LOAD x22, 19 * REGBYTES(sp) + LOAD x23, 20 * REGBYTES(sp) + LOAD x24, 21 * REGBYTES(sp) + LOAD x25, 22 * REGBYTES(sp) + LOAD x26, 23 * REGBYTES(sp) + LOAD x27, 24 * REGBYTES(sp) + LOAD x28, 25 * REGBYTES(sp) + LOAD x29, 26 * REGBYTES(sp) + LOAD x30, 27 * REGBYTES(sp) + LOAD x31, 28 * REGBYTES(sp) +#endif + + addi sp, sp, RT_CONTEXT_SIZE + + mret + +.align 2 +.global eclic_msip_handler +eclic_msip_handler: + addi sp, sp, -RT_CONTEXT_SIZE + STORE x1, 1 * REGBYTES(sp) /* RA */ + STORE x5, 2 * REGBYTES(sp) + STORE x6, 3 * REGBYTES(sp) + STORE x7, 4 * REGBYTES(sp) + STORE x8, 5 * REGBYTES(sp) + STORE x9, 6 * REGBYTES(sp) + STORE x10, 7 * REGBYTES(sp) + STORE x11, 8 * REGBYTES(sp) + STORE x12, 9 * REGBYTES(sp) + STORE x13, 10 * REGBYTES(sp) + STORE x14, 11 * REGBYTES(sp) + STORE x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 13 * REGBYTES(sp) + STORE x17, 14 * REGBYTES(sp) + STORE x18, 15 * REGBYTES(sp) + STORE x19, 16 * REGBYTES(sp) + STORE x20, 17 * REGBYTES(sp) + STORE x21, 18 * REGBYTES(sp) + STORE x22, 19 * REGBYTES(sp) + STORE x23, 20 * REGBYTES(sp) + STORE x24, 21 * REGBYTES(sp) + STORE x25, 22 * REGBYTES(sp) + STORE x26, 23 * REGBYTES(sp) + STORE x27, 24 * REGBYTES(sp) + STORE x28, 25 * REGBYTES(sp) + STORE x29, 26 * REGBYTES(sp) + STORE x30, 27 * REGBYTES(sp) + STORE x31, 28 * REGBYTES(sp) +#endif + /* Push mstatus to stack */ + csrr t0, CSR_MSTATUS + STORE t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + + /* Push additional registers */ + + /* Store sp to task stack */ + LOAD t0, rt_interrupt_from_thread + STORE sp, 0(t0) + + csrr t0, CSR_MEPC + STORE t0, 0(sp) + + jal rt_hw_taskswitch + + /* Switch task context */ + LOAD t0, rt_interrupt_to_thread + LOAD sp, 0x0(t0) + + /* Pop PC from stack and set MEPC */ + LOAD t0, 0 * REGBYTES(sp) + csrw CSR_MEPC, t0 + + /* Pop additional registers */ + + /* Pop mstatus from stack and set it */ + LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + csrw CSR_MSTATUS, t0 + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + LOAD x1, 1 * REGBYTES(sp) /* RA */ + LOAD x5, 2 * REGBYTES(sp) + LOAD x6, 3 * REGBYTES(sp) + LOAD x7, 4 * REGBYTES(sp) + LOAD x8, 5 * REGBYTES(sp) + LOAD x9, 6 * REGBYTES(sp) + LOAD x10, 7 * REGBYTES(sp) + LOAD x11, 8 * REGBYTES(sp) + LOAD x12, 9 * REGBYTES(sp) + LOAD x13, 10 * REGBYTES(sp) + LOAD x14, 11 * REGBYTES(sp) + LOAD x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 13 * REGBYTES(sp) + LOAD x17, 14 * REGBYTES(sp) + LOAD x18, 15 * REGBYTES(sp) + LOAD x19, 16 * REGBYTES(sp) + LOAD x20, 17 * REGBYTES(sp) + LOAD x21, 18 * REGBYTES(sp) + LOAD x22, 19 * REGBYTES(sp) + LOAD x23, 20 * REGBYTES(sp) + LOAD x24, 21 * REGBYTES(sp) + LOAD x25, 22 * REGBYTES(sp) + LOAD x26, 23 * REGBYTES(sp) + LOAD x27, 24 * REGBYTES(sp) + LOAD x28, 25 * REGBYTES(sp) + LOAD x29, 26 * REGBYTES(sp) + LOAD x30, 27 * REGBYTES(sp) + LOAD x31, 28 * REGBYTES(sp) +#endif + + addi sp, sp, RT_CONTEXT_SIZE + mret diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c new file mode 100644 index 0000000000..fad9afdf4c --- /dev/null +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 Huaqi Nuclei RISC-V Core porting code. + */ + +#include +#include +#include +#include + +#include "cpuport.h" + +#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND) + +/* Interrupt level for kernel systimer interrupt and software timer interrupt */ +#define RT_KERNEL_INTERRUPT_LEVEL 1 + +/* Initial CSR MSTATUS value when thread created */ +#define RT_INITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL) + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + +/** + * @brief thread stack frame of saved context + * + */ +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /*!< epc - epc - program counter */ + rt_ubase_t ra; /*!< x1 - ra - return address for jumps */ + rt_ubase_t t0; /*!< x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /*!< x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /*!< x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /*!< x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /*!< x9 - s1 - saved register 1 */ + rt_ubase_t a0; /*!< x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /*!< x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /*!< x12 - a2 - function argument 2 */ + rt_ubase_t a3; /*!< x13 - a3 - function argument 3 */ + rt_ubase_t a4; /*!< x14 - a4 - function argument 4 */ + rt_ubase_t a5; /*!< x15 - a5 - function argument 5 */ +#ifndef __riscv_32e + rt_ubase_t a6; /*!< x16 - a6 - function argument 6 */ + rt_ubase_t a7; /*!< x17 - s7 - function argument 7 */ + rt_ubase_t s2; /*!< x18 - s2 - saved register 2 */ + rt_ubase_t s3; /*!< x19 - s3 - saved register 3 */ + rt_ubase_t s4; /*!< x20 - s4 - saved register 4 */ + rt_ubase_t s5; /*!< x21 - s5 - saved register 5 */ + rt_ubase_t s6; /*!< x22 - s6 - saved register 6 */ + rt_ubase_t s7; /*!< x23 - s7 - saved register 7 */ + rt_ubase_t s8; /*!< x24 - s8 - saved register 8 */ + rt_ubase_t s9; /*!< x25 - s9 - saved register 9 */ + rt_ubase_t s10; /*!< x26 - s10 - saved register 10 */ + rt_ubase_t s11; /*!< x27 - s11 - saved register 11 */ + rt_ubase_t t3; /*!< x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /*!< x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /*!< x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /*!< x31 - t6 - temporary register 6 */ +#endif + rt_ubase_t mstatus; /*!< - machine status register */ +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + frame->mstatus = RT_INITIAL_MSTATUS; + + return stk; +} + +/** + * @brief Do rt-thread context switch in interrupt context + * + * @param from thread sp of from thread + * @param to thread sp of to thread + */ +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + RT_YIELD(); +} + +/** + * @brief Do rt-thread context switch in task context + * + * @param from thread sp of from thread + * @param to thread sp of to thread + */ +void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + RT_YIELD(); +} + +/** + * @brief shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/** + * @brief Do extra task switch code + * + * @details + * + * - Clear software timer interrupt request flag + * - clear rt_thread_switch_interrupt_flag to 0 + */ +void rt_hw_taskswitch(void) +{ + /* Clear Software IRQ, A MUST */ + SysTimer_ClearSWIRQ(); + rt_thread_switch_interrupt_flag = 0; +} + +/** + * @brief Setup systimer and software timer interrupt + * + * @details + * + * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level + * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level + * - Enable these two interrupts + */ +void rt_hw_ticksetup(void) +{ + uint64_t ticks = SYSTICK_TICK_CONST; + + /* Make SWI and SysTick the lowest priority interrupts. */ + /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */ + SysTick_Config(ticks); + ECLIC_DisableIRQ(SysTimer_IRQn); + ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL); + ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_EnableIRQ(SysTimer_IRQn); + + /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */ + ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL); + ECLIC_EnableIRQ(SysTimerSW_IRQn); +} + +/** + * systimer interrupt handler eclic_mtip_handler + * is hard coded in startup_.S + * We define SysTick_Handler as eclic_mtip_handler + * for easy understanding + */ +#define SysTick_Handler eclic_mtip_handler + +/** + * @brief This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* Reload systimer */ + SysTick_Reload(SYSTICK_TICK_CONST); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* tick increase */ + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * @brief Disable cpu interrupt + * + * @details + * + * - Disable cpu interrupt by clear MIE bit in MSTATUS + * - Return the previous value in MSTATUS before clear MIE bit + * + * @return the previous value in MSTATUS before clear MIE bit + */ +rt_base_t rt_hw_interrupt_disable(void) +{ + return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE); +} + +/** + * @brief Restore previous saved interrupt status + * + * @param level previous saved MSTATUS value + */ +void rt_hw_interrupt_enable(rt_base_t level) +{ + __RV_CSR_WRITE(CSR_MSTATUS, level); +} diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h new file mode 100644 index 0000000000..3736f0078a --- /dev/null +++ b/libcpu/risc-v/nuclei/cpuport.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 hqfang Nuclei RISC-V Core porting code. + */ + +#ifndef __CPUPORT_H__ +#define __CPUPORT_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Scheduler utilities. */ +#define RT_YIELD() \ +{ \ + /* Set a software interrupt(SWI) request to request a context switch. */ \ + SysTimer_SetSWIRQ(); \ + /* Barriers are normally not required but do ensure the code is completely \ + within the specified behaviour for the architecture. */ \ + __RWMB(); \ + __FENCE_I(); \ +} + +extern void rt_hw_ticksetup(void); +extern void rt_hw_taskswitch(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libcpu/risc-v/nuclei/interrupt_gcc.S b/libcpu/risc-v/nuclei/interrupt_gcc.S new file mode 100644 index 0000000000..02a3e3e760 --- /dev/null +++ b/libcpu/risc-v/nuclei/interrupt_gcc.S @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 hqfang First Nuclei RISC-V porting implementation + */ + +#include "riscv_encoding.h" + +.section .text.entry +.align 8 + +/** + * \brief Global interrupt disabled + * \details + * This function disable global interrupt. + * \remarks + * - All the interrupt requests will be ignored by CPU. + */ +.macro DISABLE_MIE + csrc CSR_MSTATUS, MSTATUS_MIE +.endm + +/** + * \brief Macro for context save + * \details + * This macro save ABI defined caller saved registers in the stack. + * \remarks + * - This Macro could use to save context when you enter to interrupt + * or exception +*/ +/* Save caller registers */ +.macro SAVE_CONTEXT + csrrw sp, CSR_MSCRATCHCSWL, sp + /* Allocate stack space for context saving */ +#ifndef __riscv_32e + addi sp, sp, -20*REGBYTES +#else + addi sp, sp, -14*REGBYTES +#endif /* __riscv_32e */ + + STORE x1, 0*REGBYTES(sp) + STORE x4, 1*REGBYTES(sp) + STORE x5, 2*REGBYTES(sp) + STORE x6, 3*REGBYTES(sp) + STORE x7, 4*REGBYTES(sp) + STORE x10, 5*REGBYTES(sp) + STORE x11, 6*REGBYTES(sp) + STORE x12, 7*REGBYTES(sp) + STORE x13, 8*REGBYTES(sp) + STORE x14, 9*REGBYTES(sp) + STORE x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 14*REGBYTES(sp) + STORE x17, 15*REGBYTES(sp) + STORE x28, 16*REGBYTES(sp) + STORE x29, 17*REGBYTES(sp) + STORE x30, 18*REGBYTES(sp) + STORE x31, 19*REGBYTES(sp) +#endif /* __riscv_32e */ +.endm + +/** + * \brief Macro for restore caller registers + * \details + * This macro restore ABI defined caller saved registers from stack. + * \remarks + * - You could use this macro to restore context before you want return + * from interrupt or exeception + */ +/* Restore caller registers */ +.macro RESTORE_CONTEXT + LOAD x1, 0*REGBYTES(sp) + LOAD x4, 1*REGBYTES(sp) + LOAD x5, 2*REGBYTES(sp) + LOAD x6, 3*REGBYTES(sp) + LOAD x7, 4*REGBYTES(sp) + LOAD x10, 5*REGBYTES(sp) + LOAD x11, 6*REGBYTES(sp) + LOAD x12, 7*REGBYTES(sp) + LOAD x13, 8*REGBYTES(sp) + LOAD x14, 9*REGBYTES(sp) + LOAD x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 14*REGBYTES(sp) + LOAD x17, 15*REGBYTES(sp) + LOAD x28, 16*REGBYTES(sp) + LOAD x29, 17*REGBYTES(sp) + LOAD x30, 18*REGBYTES(sp) + LOAD x31, 19*REGBYTES(sp) + + /* De-allocate the stack space */ + addi sp, sp, 20*REGBYTES +#else + /* De-allocate the stack space */ + addi sp, sp, 14*REGBYTES +#endif /* __riscv_32e */ + csrrw sp, CSR_MSCRATCHCSWL, sp +.endm + +/** + * \brief Macro for save necessary CSRs to stack + * \details + * This macro store MCAUSE, MEPC, MSUBM to stack. + */ +.macro SAVE_CSR_CONTEXT + /* Store CSR mcause to stack using pushmcause */ + csrrwi x0, CSR_PUSHMCAUSE, 11 + /* Store CSR mepc to stack using pushmepc */ + csrrwi x0, CSR_PUSHMEPC, 12 + /* Store CSR msub to stack using pushmsub */ + csrrwi x0, CSR_PUSHMSUBM, 13 +.endm + +/** + * \brief Macro for restore necessary CSRs from stack + * \details + * This macro restore MSUBM, MEPC, MCAUSE from stack. + */ +.macro RESTORE_CSR_CONTEXT + LOAD x5, 13*REGBYTES(sp) + csrw CSR_MSUBM, x5 + LOAD x5, 12*REGBYTES(sp) + csrw CSR_MEPC, x5 + LOAD x5, 11*REGBYTES(sp) + csrw CSR_MCAUSE, x5 +.endm + +/** + * \brief Exception/NMI Entry + * \details + * This function provide common entry functions for exception/nmi. + * \remarks + * This function provide a default exception/nmi entry. + * ABI defined caller save register and some CSR registers + * to be saved before enter interrupt handler and be restored before return. + */ +.section .text.trap +/* In CLIC mode, the exeception entry must be 64bytes aligned */ +.align 6 +.global exc_entry +exc_entry: + /* Save the caller saving registers (context) */ + SAVE_CONTEXT + /* Save the necessary CSR registers */ + SAVE_CSR_CONTEXT + + /* + * Set the exception handler function arguments + * argument 1: mcause value + * argument 2: current stack point(SP) value + */ + csrr a0, mcause + mv a1, sp + /* + * TODO: Call the exception handler function + * By default, the function template is provided in + * system_Device.c, you can adjust it as you want + */ + call core_exception_handler + + /* Restore the necessary CSR registers */ + RESTORE_CSR_CONTEXT + /* Restore the caller saving registers (context) */ + RESTORE_CONTEXT + + /* Return to regular code */ + mret + +/** + * \brief Non-Vector Interrupt Entry + * \details + * This function provide common entry functions for handling + * non-vector interrupts + * \remarks + * This function provide a default non-vector interrupt entry. + * ABI defined caller save register and some CSR registers need + * to be saved before enter interrupt handler and be restored before return. + */ +.section .text.irq +/* In CLIC mode, the interrupt entry must be 4bytes aligned */ +.align 2 +.global irq_entry +/* This label will be set to MTVT2 register */ +irq_entry: + /* Save the caller saving registers (context) */ + SAVE_CONTEXT + /* Save the necessary CSR registers */ + SAVE_CSR_CONTEXT + + /* This special CSR read/write operation, which is actually + * claim the CLIC to find its pending highest ID, if the ID + * is not 0, then automatically enable the mstatus.MIE, and + * jump to its vector-entry-label, and update the link register + */ + csrrw ra, CSR_JALMNXTI, ra + + /* Critical section with interrupts disabled */ + DISABLE_MIE + + /* Restore the necessary CSR registers */ + RESTORE_CSR_CONTEXT + /* Restore the caller saving registers (context) */ + RESTORE_CONTEXT + + /* Return to regular code */ + mret + +/* Default Handler for Exceptions / Interrupts */ +.global default_intexc_handler +Undef_Handler: +default_intexc_handler: +1: + j 1b + diff --git a/tools/mkdist.py b/tools/mkdist.py index 7e4b9a8bbe..ec527d87e1 100644 --- a/tools/mkdist.py +++ b/tools/mkdist.py @@ -345,6 +345,13 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None): bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + # copy nuclei bsp libiary files + if os.path.basename(os.path.dirname(BSP_ROOT)) == 'nuclei': + print("=> copy nuclei bsp library") + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + library_dir = os.path.join(dist_dir, 'libraries') + bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) + # do bsp special dist handle if 'dist_handle' in Env: print("=> start dist handle") From 3b2fa472096d41287ee8cb542e8c1d119a5a8b76 Mon Sep 17 00:00:00 2001 From: luhuadong Date: Fri, 17 Apr 2020 22:14:37 +0800 Subject: [PATCH 13/27] [BSP] add Libraries when scons --dist --- bsp/at32/at32f403a-start/rtconfig.py | 6 +++--- tools/mkdist.py | 26 ++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/bsp/at32/at32f403a-start/rtconfig.py b/bsp/at32/at32f403a-start/rtconfig.py index 1d63cabb96..4800f9a871 100644 --- a/bsp/at32/at32f403a-start/rtconfig.py +++ b/bsp/at32/at32f403a-start/rtconfig.py @@ -57,7 +57,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -88,7 +88,7 @@ elif PLATFORM == 'armcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' @@ -136,7 +136,7 @@ elif PLATFORM == 'iar': LFLAGS = ' --config "board/linker_scripts/link.icf"' LFLAGS += ' --entry __iar_program_start' - + CXXFLAGS = CFLAGS EXEC_PATH = EXEC_PATH + '/arm/bin/' diff --git a/tools/mkdist.py b/tools/mkdist.py index 7e4b9a8bbe..e71d767446 100644 --- a/tools/mkdist.py +++ b/tools/mkdist.py @@ -122,7 +122,7 @@ def bsp_update_kconfig(dist_dir): line = line[0:position] + 'default "rt-thread"\n' found = 0 f.write(line) - + def bsp_update_kconfig_library(dist_dir): # change RTT_ROOT in Kconfig if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')): @@ -141,7 +141,7 @@ def bsp_update_kconfig_library(dist_dir): found = 0 f.write(line) - # change board/kconfig path + # change board/kconfig path if not os.path.isfile(os.path.join(dist_dir, 'board/Kconfig')): return @@ -214,12 +214,21 @@ def MkDist_Strip(program, BSP_ROOT, RTT_ROOT, Env): bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + # copy at32 bsp libiary files + if os.path.basename(os.path.dirname(BSP_ROOT)) == 'at32': + print("=> copy at32 bsp library") + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') + library_dir = os.path.join(dist_dir, 'Libraries') + bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) + bsp_copy_files(os.path.join(library_path, 'AT32_Std_Driver'), os.path.join(library_dir, 'AT32_Std_Driver')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + # do bsp special dist handle - if 'dist_handle' in Env: + if 'dist_handle' in Env: print("=> start dist handle") dist_handle = Env['dist_handle'] dist_handle(BSP_ROOT) - + # get all source files from program for item in program: walk_children(item) @@ -345,6 +354,15 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None): bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + # copy at32 bsp libiary files + if os.path.basename(os.path.dirname(BSP_ROOT)) == 'at32': + print("=> copy at32 bsp library") + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') + library_dir = os.path.join(dist_dir, 'Libraries') + bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) + bsp_copy_files(os.path.join(library_path, 'AT32_Std_Driver'), os.path.join(library_dir, 'AT32_Std_Driver')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + # do bsp special dist handle if 'dist_handle' in Env: print("=> start dist handle") From 098eccc05729b06f8e4af060d702308f6596b9c8 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 17 Apr 2020 22:16:34 +0800 Subject: [PATCH 14/27] add raspi3-64 readme note --- bsp/raspberry-pi/raspi3-64/README.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/bsp/raspberry-pi/raspi3-64/README.md b/bsp/raspberry-pi/raspi3-64/README.md index 576b13ed0e..a8558d809e 100644 --- a/bsp/raspberry-pi/raspi3-64/README.md +++ b/bsp/raspberry-pi/raspi3-64/README.md @@ -31,6 +31,16 @@ EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.0 然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。 +**window环境搭建注意** + +下载完成`gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf.tar.xz`交叉编译工具链后，最好采用7-zip解压工具进行两次解压。 +确保解压目录下的`/bin/aarch64-elf-ld.exe`文件的size不为0。 +否则编译会出现如下错误: + +``` +collect2.exe:fatal error:CreateProcess:No such file or directory +``` + ### 2.2 Linux上的环境搭建 Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。 From bcae19654162c80a8f2380794189c7b4ec242c90 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 17 Apr 2020 22:19:54 +0800 Subject: [PATCH 15/27] [bsp\raspi4]move io to `iomap.h` --- bsp/raspberry-pi/raspi4/driver/board.c | 8 ++------ bsp/raspberry-pi/raspi4/driver/board.h | 2 +- bsp/raspberry-pi/raspi4/driver/drv_gpio.h | 2 -- bsp/raspberry-pi/raspi4/driver/drv_uart.c | 6 ------ bsp/raspberry-pi/raspi4/driver/drv_uart.h | 1 - bsp/raspberry-pi/raspi4/driver/iomap.h | 21 ++++++++++++++++++--- 6 files changed, 21 insertions(+), 19 deletions(-) diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c index 46d629a35d..79a24d184f 100644 --- a/bsp/raspberry-pi/raspi4/driver/board.c +++ b/bsp/raspberry-pi/raspi4/driver/board.c @@ -18,10 +18,6 @@ #include "mmu.h" static rt_uint64_t timerStep; -// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control -#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040) -#define TIMER_IRQ 30 -#define NON_SECURE_TIMER_IRQ (1 << 1) int rt_hw_get_gtimer_frq(void); void rt_hw_set_gtimer_val(rt_uint64_t value); @@ -29,7 +25,7 @@ int rt_hw_get_gtimer_val(void); int rt_hw_get_cntpct_val(void); void rt_hw_gtimer_enable(void); -void core0_timer_enable_interrupt_controller() +void core0_timer_enable_interrupt_controller(void) { CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ; } @@ -94,4 +90,4 @@ void rt_hw_board_init(void) #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif -} \ No newline at end of file +} diff --git a/bsp/raspberry-pi/raspi4/driver/board.h b/bsp/raspberry-pi/raspi4/driver/board.h index 66805464f2..a7c96b3276 100644 --- a/bsp/raspberry-pi/raspi4/driver/board.h +++ b/bsp/raspberry-pi/raspi4/driver/board.h @@ -12,6 +12,7 @@ #define BOARD_H__ #include +#include "iomap.h" extern unsigned char __bss_start; extern unsigned char __bss_end; @@ -22,4 +23,3 @@ extern unsigned char __bss_end; void rt_hw_board_init(void); #endif - diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h index ebc9452cec..c4658fcebb 100644 --- a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h @@ -17,8 +17,6 @@ #include "board.h" #include "interrupt.h" -#define GPIO_BASE (0xFE000000 + 0x00200000) - #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.c b/bsp/raspberry-pi/raspi4/driver/drv_uart.c index a7ac1b5892..6a70cdfb3a 100644 --- a/bsp/raspberry-pi/raspi4/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.c @@ -16,12 +16,6 @@ #include "drv_uart.h" #include "drv_gpio.h" -#define UART0_BASE (0xFE000000 + 0x00201000) -#define PL011_BASE UART0_BASE -#define IRQ_PL011 (121 + 32) - -#define UART_REFERENCE_CLOCK 48000000 - struct hw_uart_device { rt_ubase_t hw_base; diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.h b/bsp/raspberry-pi/raspi4/driver/drv_uart.h index 4f23d7b46e..714043efd3 100644 --- a/bsp/raspberry-pi/raspi4/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.h @@ -81,4 +81,3 @@ int rt_hw_uart_init(void); #endif /* DRV_UART_H__ */ - diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h index 675cd147e3..3f18353904 100644 --- a/bsp/raspberry-pi/raspi4/driver/iomap.h +++ b/bsp/raspberry-pi/raspi4/driver/iomap.h @@ -1,8 +1,23 @@ #ifndef __RASPI4_H__ #define __RASPI4_H__ -#define ARM_GIC_NR_IRQS 512 -#define INTC_BASE 0xff800000 +//gpio +#define GPIO_BASE (0xFE000000 + 0x00200000) + +//uart +#define UART0_BASE (0xFE000000 + 0x00201000) +#define PL011_BASE UART0_BASE +#define IRQ_PL011 (121 + 32) +#define UART_REFERENCE_CLOCK (48000000) + +// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control +#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040) +#define TIMER_IRQ 30 +#define NON_SECURE_TIMER_IRQ (1 << 1) + +//gic max +#define ARM_GIC_NR_IRQS (512) +#define INTC_BASE (0xff800000) #define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000) #define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000) #define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000) @@ -11,4 +26,4 @@ #define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE #define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE -#endif \ No newline at end of file +#endif From 3afb24f4c1f7530887a9f3f981bc0fdd3961c44c Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 17 Apr 2020 22:30:41 +0800 Subject: [PATCH 16/27] fix aarch64 compiler warning --- components/finsh/finsh.h | 4 ++-- components/finsh/finsh_compiler.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h index eb38682c4f..7276ea7ce1 100644 --- a/components/finsh/finsh.h +++ b/components/finsh/finsh.h @@ -27,8 +27,8 @@ #define HEAP_ALIGNMENT 4 /* heap alignment */ #define FINSH_GET16(x) (*(x)) | (*((x)+1) << 8) -#define FINSH_GET32(x) (rt_uint32_t)(*(x)) | ((rt_uint32_t)*((x)+1) << 8) | \ - ((rt_uint32_t)*((x)+2) << 16) | ((rt_uint32_t)*((x)+3) << 24) +#define FINSH_GET32(x) (rt_ubase_t)(*(x)) | ((rt_ubase_t)*((x)+1) << 8) | \ + ((rt_ubase_t)*((x)+2) << 16) | ((rt_ubase_t)*((x)+3) << 24) #define FINSH_SET16(x, v) \ do \ diff --git a/components/finsh/finsh_compiler.c b/components/finsh/finsh_compiler.c index 8d33e0e567..f81409bf9a 100644 --- a/components/finsh/finsh_compiler.c +++ b/components/finsh/finsh_compiler.c @@ -191,7 +191,7 @@ static int finsh_compile(struct finsh_node* node) case FINSH_NODE_VALUE_NULL: case FINSH_NODE_VALUE_STRING: finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((uint32_t)node->value.ptr); + finsh_code_dword((rt_ubase_t)node->value.ptr); break; /* arithmetic operation */ From bcda77bc438fdb20e4a8410fcf4825794ab0148c Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 20 Apr 2020 10:33:32 +0800 Subject: [PATCH 17/27] [DOC] Add Nuclei to main README.md Mainly display Nuclei processor support Signed-off-by: Huaqi Fang <578567190@qq.com> --- README.md | 2 +- README_zh.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 09156b6ca4..d0ca35c957 100644 --- a/README.md +++ b/README.md @@ -86,7 +86,7 @@ RT-Thread supports many architectures, and has covered the major architectures i - **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE - **ARM11**：manufacturers like Fullhan - **MIPS32**：manufacturers like loongson、Ingenic -- **RISC-V**：manufacturers like Hifive、Kendryte +- **RISC-V**：manufacturers like Hifive、Kendryte、[Nuclei](https://nucleisys.com/) - **ARC**：manufacturers like SYNOPSYS - **DSP**：manufacturers like TI - **C-Sky** diff --git a/README_zh.md b/README_zh.md index 4d1cc3e9e5..9cdfa30722 100644 --- a/README_zh.md +++ b/README_zh.md @@ -89,7 +89,7 @@ RT-Thread RTOS 支持许多架构，并且已经涵盖了当前应用中的主 - MIPS32：如芯片制造商loongson、Ingenic -- RISC-V：如芯片制造商Hifive、Kendryte +- RISC-V：如芯片制造商Hifive、Kendryte、[芯来Nuclei](https://nucleisys.com/) - ARC：如芯片制造商SYNOPSYS From 3b20282e13ec4d369238141f9bf980f38a742e1f Mon Sep 17 00:00:00 2001 From: xupenghu_huaweipc Date: Mon, 20 Apr 2020 19:20:56 +0800 Subject: [PATCH 18/27] add bsp/stm32l010rb-nucleo, fix some pr suggest. --- .travis.yml | 1 + bsp/stm32/stm32l010-st-nucleo/README.md | 2 +- bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 82421e993c..8b4f03006a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -107,6 +107,7 @@ env: - RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32h747-st-discovery' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm' diff --git a/bsp/stm32/stm32l010-st-nucleo/README.md b/bsp/stm32/stm32l010-st-nucleo/README.md index 6b8613bb36..c69bbe14fa 100644 --- a/bsp/stm32/stm32l010-st-nucleo/README.md +++ b/bsp/stm32/stm32l010-st-nucleo/README.md @@ -29,7 +29,7 @@ NUCLEO-L010RB 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核 - 20KB RAM - 512 byte EEPROM - 常用外设 - - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 黄色) + - LED：3个，USB communication(LD1 双色)，power LED(LD3 红色)，user LED(LD2 黄色) - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET） - 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等 - 调试接口：标准 SWD diff --git a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf index 24d6f5275c..1d998fe063 100644 --- a/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf @@ -26,4 +26,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file +place in RAM_region { readwrite, last block CSTACK}; From e1bd3673fd428ffbfd04d2f51a1a9be6fbfe832d Mon Sep 17 00:00:00 2001 From: luhuadong Date: Wed, 22 Apr 2020 16:58:10 +0800 Subject: [PATCH 19/27] [AT32 BSP] do bsp special dist handle --- bsp/at32/at32f403a-start/Kconfig | 3 +-- bsp/at32/at32f403a-start/rtconfig.py | 7 +++++++ bsp/at32/tools/sdk_dist.py | 19 +++++++++++++++++++ tools/mkdist.py | 18 ------------------ 4 files changed, 27 insertions(+), 20 deletions(-) create mode 100644 bsp/at32/tools/sdk_dist.py diff --git a/bsp/at32/at32f403a-start/Kconfig b/bsp/at32/at32f403a-start/Kconfig index 7a400db91f..1a3b4b75bc 100644 --- a/bsp/at32/at32f403a-start/Kconfig +++ b/bsp/at32/at32f403a-start/Kconfig @@ -17,6 +17,5 @@ config PKGS_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" -source "../libraries/Kconfig" +source "../Libraries/Kconfig" source "board/Kconfig" - diff --git a/bsp/at32/at32f403a-start/rtconfig.py b/bsp/at32/at32f403a-start/rtconfig.py index 4800f9a871..5f2f01ca76 100644 --- a/bsp/at32/at32f403a-start/rtconfig.py +++ b/bsp/at32/at32f403a-start/rtconfig.py @@ -1,4 +1,5 @@ import os +import sys # toolchains options ARCH='arm' @@ -141,3 +142,9 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/at32/tools/sdk_dist.py b/bsp/at32/tools/sdk_dist.py new file mode 100644 index 0000000000..01ff930b20 --- /dev/null +++ b/bsp/at32/tools/sdk_dist.py @@ -0,0 +1,19 @@ +import os +import sys +import shutil +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +# BSP dist function +def dist_do_building(BSP_ROOT): + from mkdist import bsp_copy_files + import rtconfig + + dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT)) + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') + library_dir = os.path.join(dist_dir, 'Libraries') + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) + print("=> copy bsp library") + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) diff --git a/tools/mkdist.py b/tools/mkdist.py index 2f12ad8f12..d83020f755 100644 --- a/tools/mkdist.py +++ b/tools/mkdist.py @@ -214,15 +214,6 @@ def MkDist_Strip(program, BSP_ROOT, RTT_ROOT, Env): bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) - # copy at32 bsp libiary files - if os.path.basename(os.path.dirname(BSP_ROOT)) == 'at32': - print("=> copy at32 bsp library") - library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') - library_dir = os.path.join(dist_dir, 'Libraries') - bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) - bsp_copy_files(os.path.join(library_path, 'AT32_Std_Driver'), os.path.join(library_dir, 'AT32_Std_Driver')) - shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) - # do bsp special dist handle if 'dist_handle' in Env: print("=> start dist handle") @@ -354,15 +345,6 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None): bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) - # copy at32 bsp libiary files - if os.path.basename(os.path.dirname(BSP_ROOT)) == 'at32': - print("=> copy at32 bsp library") - library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') - library_dir = os.path.join(dist_dir, 'Libraries') - bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) - bsp_copy_files(os.path.join(library_path, 'AT32_Std_Driver'), os.path.join(library_dir, 'AT32_Std_Driver')) - shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) - # copy nuclei bsp libiary files if os.path.basename(os.path.dirname(BSP_ROOT)) == 'nuclei': print("=> copy nuclei bsp library") From ef00e50ad5603573346a3a1ba8497550af66a26a Mon Sep 17 00:00:00 2001 From: yangjie Date: Thu, 23 Apr 2020 16:21:01 +0800 Subject: [PATCH 20/27] =?UTF-8?q?[bsp][stm32l475-atk-pandora]=E5=B0=86SPI3?= =?UTF-8?q?=E9=85=8D=E7=BD=AE=E4=B8=BA=20transmit=20only=20master=20?= =?UTF-8?q?=E6=A8=A1=E5=BC=8F=EF=BC=8C=E9=98=B2=E6=AD=A2LCD=E6=A8=A1?= =?UTF-8?q?=E5=9D=97=E4=BD=BF=E7=94=A8=E7=9A=84PIN=E8=84=9A=E8=A2=ABSPI3?= =?UTF-8?q?=5FMISO=E5=8D=A0=E7=94=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../board/CubeMX_Config/.mxproject | 8 +- .../board/CubeMX_Config/STM32L475VE.ioc | 695 +++++++++--------- .../CubeMX_Config/Src/stm32l4xx_hal_msp.c | 6 +- 3 files changed, 352 insertions(+), 357 deletions(-) diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject index b2abade8d0..f56464c131 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject @@ -1,14 +1,14 @@ [PreviousGenFiles] -HeaderPath=E:/1-thread-source/rt-thread-h/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc +HeaderPath=E:/1-thread-source/rt-thread_f/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; -SourcePath=E:/1-thread-source/rt-thread-h/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src +SourcePath=E:/1-thread-source/rt-thread_f/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/ST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[PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;..\\Src/system_stm32l4xx.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;..\\Src/system_stm32l4xx.c;..\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;; +SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;..\\Src/system_stm32l4xx.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;..\\Src/system_stm32l4xx.c;..\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;; HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32L475xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc index 13064b21c0..5b1083a232 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc @@ -1,366 +1,363 @@ #MicroXplorer Configuration settings - do not modify -ADC1.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_14 -ADC1.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,OffsetNumber-15\#ChannelRegularConversion,NbrOfConversionFlag,master -ADC1.NbrOfConversionFlag=1 -ADC1.OffsetNumber-15\#ChannelRegularConversion=ADC_OFFSET_NONE -ADC1.Rank-15\#ChannelRegularConversion=1 -ADC1.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -ADC1.master=1 -File.Version=6 -KeepUserPlacement=false Mcu.Family=STM32L4 -Mcu.IP0=ADC1 -Mcu.IP1=IWDG -Mcu.IP10=SPI2 -Mcu.IP11=SPI3 -Mcu.IP12=SYS -Mcu.IP13=TIM1 -Mcu.IP14=TIM2 -Mcu.IP15=TIM4 -Mcu.IP16=TIM15 -Mcu.IP17=TIM16 -Mcu.IP18=TIM17 -Mcu.IP19=USART1 -Mcu.IP2=LPTIM1 -Mcu.IP20=USART2 -Mcu.IP21=USB_OTG_FS -Mcu.IP3=NVIC +ProjectManager.MainLocation=Src +PA6.Mode=Full_Duplex_Master +SH.S_TIM4_CH2.ConfNb=1 +RCC.USART1Freq_Value=80000000 +RCC.SAI1Freq_Value=13714285.714285715 +USART2.IPParameters=VirtualMode-Asynchronous +RCC.CortexFreq_Value=80000000 +SPI3.Direction=SPI_DIRECTION_2LINES +VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +SPI3.VirtualType=VM_MASTER +ProjectManager.KeepUserCode=true +Mcu.UserName=STM32L475VETx +SPI1.VirtualType=VM_MASTER +SPI2.VirtualType=VM_MASTER +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +TIM1.IPParameters=Channel-PWM Generation1 CH1 +PC10.Signal=SDMMC1_D2 +PC12.Signal=SDMMC1_CK +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +RCC.PLLSAI1RoutputFreq_Value=48000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true,11-MX_TIM17_Init-TIM17-false-HAL-true,12-MX_TIM16_Init-TIM16-false-HAL-true,13-MX_TIM15_Init-TIM15-false-HAL-true,14-MX_TIM4_Init-TIM4-false-HAL-true,15-MX_TIM1_Init-TIM1-false-HAL-true,16-MX_SAI1_Init-SAI1-false-HAL-true,17-MX_SPI3_Init-SPI3-false-HAL-true,18-MX_TIM2_Init-TIM2-false-HAL-true,19-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true +SAI1.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A +PA11.Mode=Device_Only +RCC.RTCFreq_Value=32768 +RCC.USART2Freq_Value=80000000 +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +SH.S_TIM1_CH1.ConfNb=1 +USART1.IPParameters=VirtualMode-Asynchronous +PB11.Signal=S_TIM2_CH4 +PB13.Signal=SPI2_SCK +PB15.Signal=SPI2_MOSI +PinOutPanel.RotationAngle=0 +RCC.MCO1PinFreq_Value=80000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +ProjectManager.StackSize=0x400 +PB3\ (JTDO-TRACESWO).Signal=SPI3_SCK +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK +RCC.I2C3Freq_Value=80000000 +RCC.LPTIM1Freq_Value=80000000 Mcu.IP4=QUADSPI Mcu.IP5=RCC -Mcu.IP6=RTC -Mcu.IP7=SAI1 -Mcu.IP8=SDMMC1 -Mcu.IP9=SPI1 -Mcu.IPNb=22 -Mcu.Name=STM32L475V(C-E-G)Tx -Mcu.Package=LQFP100 -Mcu.Pin0=PE2 -Mcu.Pin1=PE3 -Mcu.Pin10=PA3 -Mcu.Pin11=PA5 -Mcu.Pin12=PA6 -Mcu.Pin13=PA7 -Mcu.Pin14=PC5 -Mcu.Pin15=PE9 -Mcu.Pin16=PE10 -Mcu.Pin17=PE11 -Mcu.Pin18=PE12 -Mcu.Pin19=PE13 -Mcu.Pin2=PE4 -Mcu.Pin20=PE14 -Mcu.Pin21=PE15 -Mcu.Pin22=PB10 -Mcu.Pin23=PB11 -Mcu.Pin24=PB13 -Mcu.Pin25=PB14 -Mcu.Pin26=PB15 -Mcu.Pin27=PC8 -Mcu.Pin28=PC9 -Mcu.Pin29=PA9 -Mcu.Pin3=PE5 -Mcu.Pin30=PA10 -Mcu.Pin31=PA11 -Mcu.Pin32=PA12 -Mcu.Pin33=PA13 (JTMS-SWDIO) -Mcu.Pin34=PA14 (JTCK-SWCLK) -Mcu.Pin35=PC10 -Mcu.Pin36=PC11 -Mcu.Pin37=PC12 -Mcu.Pin38=PD2 -Mcu.Pin39=PB3 (JTDO-TRACESWO) -Mcu.Pin4=PE6 -Mcu.Pin40=PB4 (NJTRST) -Mcu.Pin41=PB5 -Mcu.Pin42=PB7 -Mcu.Pin43=PB8 -Mcu.Pin44=VP_IWDG_VS_IWDG -Mcu.Pin45=VP_LPTIM1_VS_LPTIM_counterModeInternalClock -Mcu.Pin46=VP_RTC_VS_RTC_Activate -Mcu.Pin47=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC -Mcu.Pin48=VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC -Mcu.Pin49=VP_SYS_VS_Systick -Mcu.Pin5=PC14-OSC32_IN (PC14) -Mcu.Pin50=VP_TIM1_VS_ClockSourceINT -Mcu.Pin51=VP_TIM2_VS_ClockSourceINT -Mcu.Pin52=VP_TIM4_VS_ClockSourceINT -Mcu.Pin53=VP_TIM15_VS_ClockSourceINT -Mcu.Pin54=VP_TIM16_VS_ClockSourceINT -Mcu.Pin55=VP_TIM17_VS_ClockSourceINT -Mcu.Pin6=PC15-OSC32_OUT (PC15) -Mcu.Pin7=PH0-OSC_IN (PH0) -Mcu.Pin8=PH1-OSC_OUT (PH1) -Mcu.Pin9=PA2 -Mcu.PinsNb=56 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32L475VETx -MxCube.Version=5.6.0 -MxDb.Version=DB.5.0.60 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +RCC.FCLKCortexFreq_Value=80000000 +Mcu.IP2=LPTIM1 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.Mode=Device_Only +Mcu.IP3=NVIC +Mcu.IP0=ADC1 +Mcu.IP1=IWDG PA12.Signal=USB_OTG_FS_DP -PA13\ (JTMS-SWDIO).Mode=Serial_Wire +Mcu.UserConstants= +PE11.Mode=Single Bank +RCC.VCOSAI1OutputFreq_Value=96000000 +SAI1.VirtualMode-SAI_B_SyncSlave=VM_SLAVE +RCC.SDMMCFreq_Value=48000000 +Mcu.ThirdPartyNb=0 +SPI1.Direction=SPI_DIRECTION_2LINES +RCC.HCLKFreq_Value=80000000 +PE2.Mode=SAI_A_MasterWithClock +Mcu.IPNb=22 +TIM2.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 +ProjectManager.PreviousToolchain= +RCC.APB2TimFreq_Value=80000000 +VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIB_SAI_BASIC +SPI1.CalculateBaudRate=40.0 MBits/s +Mcu.Pin6=PC15-OSC32_OUT (PC15) +RCC.SAI2Freq_Value=13714285.714285715 +Mcu.Pin7=PH0-OSC_IN (PH0) +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +Mcu.Pin8=PH1-OSC_OUT (PH1) +PE5.Signal=SAI1_SCK_A +Mcu.Pin9=PA2 +RCC.AHBFreq_Value=80000000 +PB13.Locked=true +Mcu.Pin0=PE2 +PE14.Locked=true +Mcu.Pin1=PE3 +Mcu.Pin2=PE4 +Mcu.Pin3=PE5 +RCC.USART3Freq_Value=80000000 +Mcu.Pin4=PE6 +Mcu.Pin5=PC14-OSC32_IN (PC14) +ProjectManager.ProjectBuild=false +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +RCC.HSE_VALUE=8000000 +TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +SH.ADCx_IN14.ConfNb=1 +Mcu.IP10=SPI2 +USART2.VirtualMode-Asynchronous=VM_ASYNC +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE +Mcu.IP12=SYS +Mcu.IP11=SPI3 +ADC1.OffsetNumber-15\#ChannelRegularConversion=ADC_OFFSET_NONE +Mcu.IP18=TIM17 +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1 +Mcu.IP17=TIM16 +MxDb.Version=DB.5.0.60 +PE15.Locked=true +Mcu.IP19=USART1 +Mcu.IP14=TIM2 +Mcu.IP13=TIM1 +PE13.Signal=QUADSPI_BK1_IO1 +Mcu.IP16=TIM15 +ProjectManager.BackupPrevious=false +Mcu.IP15=TIM4 +RCC.VCOInputFreq_Value=8000000 +TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +PE9.Signal=S_TIM1_CH1 +PB14.Mode=Full_Duplex_Master +PB5.Mode=TX_Only_Simplex_Unidirect_Master +File.Version=6 +PC9.Mode=SD_4_bits_Wide_bus +SPI2.CalculateBaudRate=40.0 MBits/s +SAI1.InitProtocol-SAI_A_MasterWithClock=Enable +SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 +PE2.Signal=SAI1_MCLK_A +PB7.Signal=S_TIM4_CH2 +Mcu.IP21=USB_OTG_FS +PB8.Locked=true +Mcu.IP20=USART2 +RCC.PLLRCLKFreq_Value=80000000 +PE13.Mode=Single Bank +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PE4.Mode=SAI_A_MasterWithClock +ADC1.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_14 +PE4.Signal=SAI1_FS_A +PE10.Signal=QUADSPI_CLK +VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT +ProjectManager.HalAssertFull=false +VP_TIM1_VS_ClockSourceINT.Mode=Internal +ProjectManager.ProjectName=STM32L475VE +ADC1.Rank-15\#ChannelRegularConversion=1 +SAI1.OutputDrive-SAI_A_MasterWithClock=SAI_OUTPUTDRIVE_ENABLE +Mcu.Package=LQFP100 +SAI1.AudioFrequency-SAI_A_MasterWithClock=SAI_AUDIO_FREQUENCY_44K +PA6.Signal=SPI1_MISO +SPI2.Mode=SPI_MODE_MASTER +SPI3.Mode=SPI_MODE_MASTER +SH.ADCx_IN14.0=ADC1_IN14,IN14-Single-Ended +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true +ProjectManager.ToolChainLocation= +RCC.LSI_VALUE=32000 +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +RCC.LSCOPinFreq_Value=32000 +PA10.Signal=USART1_RX +USB_OTG_FS.VirtualMode=Device_Only +RCC.DFSDMFreq_Value=80000000 +PC11.Mode=SD_4_bits_Wide_bus +ADC1.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 +RCC.PLLPoutputFreq_Value=22857142.85714286 +RCC.APB1TimFreq_Value=80000000 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +RCC.LPUART1Freq_Value=80000000 +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Direction=SPI_DIRECTION_2LINES +PC5.Signal=ADCx_IN14 +USB_OTG_FS.IPParameters=VirtualMode +PB13.Mode=Full_Duplex_Master +SH.S_TIM2_CH4.ConfNb=1 PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO -PA14\ (JTCK-SWCLK).Mode=Serial_Wire -PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK -PA2.Mode=Asynchronous -PA2.Signal=USART2_TX -PA3.Mode=Asynchronous +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PE12.Locked=true +PE3.Mode=SAI_B_SyncSlave +ProjectManager.CustomerFirmwarePackage= +PB15.Locked=true +PB3\ (JTDO-TRACESWO).Locked=true +RCC.PLLSAI1N=12 PA3.Signal=USART2_RX PA5.Mode=Full_Duplex_Master -PA5.Signal=SPI1_SCK -PA6.Mode=Full_Duplex_Master -PA6.Signal=SPI1_MISO -PA7.Mode=Full_Duplex_Master -PA7.Signal=SPI1_MOSI -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB10.Signal=S_TIM2_CH3 -PB11.Signal=S_TIM2_CH4 -PB13.Locked=true -PB13.Mode=Full_Duplex_Master -PB13.Signal=SPI2_SCK -PB14.Locked=true -PB14.Mode=Full_Duplex_Master -PB14.Signal=SPI2_MISO -PB15.Locked=true -PB15.Mode=Full_Duplex_Master -PB15.Signal=SPI2_MOSI -PB3\ (JTDO-TRACESWO).Locked=true -PB3\ (JTDO-TRACESWO).Mode=Full_Duplex_Master -PB3\ (JTDO-TRACESWO).Signal=SPI3_SCK -PB4\ (NJTRST).Mode=Full_Duplex_Master -PB4\ (NJTRST).Signal=SPI3_MISO -PB5.Locked=true -PB5.Mode=Full_Duplex_Master -PB5.Signal=SPI3_MOSI -PB7.Locked=true -PB7.Signal=S_TIM4_CH2 -PB8.Locked=true -PB8.Signal=S_TIM4_CH3 -PC10.Mode=SD_4_bits_Wide_bus -PC10.Signal=SDMMC1_D2 -PC11.Mode=SD_4_bits_Wide_bus -PC11.Signal=SDMMC1_D3 -PC12.Mode=SD_4_bits_Wide_bus -PC12.Signal=SDMMC1_CK -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PC5.Signal=ADCx_IN14 -PC8.Mode=SD_4_bits_Wide_bus -PC8.Signal=SDMMC1_D0 -PC9.Mode=SD_4_bits_Wide_bus -PC9.Signal=SDMMC1_D1 -PD2.Mode=SD_4_bits_Wide_bus -PD2.Signal=SDMMC1_CMD -PE10.Mode=Single Bank -PE10.Signal=QUADSPI_CLK -PE11.Mode=Single Bank -PE11.Signal=QUADSPI_NCS -PE12.Locked=true PE12.Mode=Single Bank -PE12.Signal=QUADSPI_BK1_IO0 -PE13.Locked=true -PE13.Mode=Single Bank -PE13.Signal=QUADSPI_BK1_IO1 -PE14.Locked=true -PE14.Mode=Single Bank -PE14.Signal=QUADSPI_BK1_IO2 -PE15.Locked=true -PE15.Mode=Single Bank -PE15.Signal=QUADSPI_BK1_IO3 -PE2.Mode=SAI_A_MasterWithClock -PE2.Signal=SAI1_MCLK_A -PE3.Mode=SAI_B_SyncSlave -PE3.Signal=SAI1_SD_B -PE4.Mode=SAI_A_MasterWithClock -PE4.Signal=SAI1_FS_A -PE5.Mode=SAI_A_MasterWithClock -PE5.Signal=SAI1_SCK_A -PE6.Mode=SAI_A_MasterWithClock -PE6.Signal=SAI1_SD_A -PE9.Signal=S_TIM1_CH1 -PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator -PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN -PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator -PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32L475VETx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=STM32L475VE.ioc -ProjectManager.ProjectName=STM32L475VE -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5 -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true,11-MX_TIM17_Init-TIM17-false-HAL-true,12-MX_TIM16_Init-TIM16-false-HAL-true,13-MX_TIM15_Init-TIM15-false-HAL-true,14-MX_TIM4_Init-TIM4-false-HAL-true,15-MX_TIM1_Init-TIM1-false-HAL-true,16-MX_SAI1_Init-SAI1-false-HAL-true,17-MX_SPI3_Init-SPI3-false-HAL-true,18-MX_TIM2_Init-TIM2-false-HAL-true,19-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true -RCC.ADCFreq_Value=48000000 -RCC.AHBFreq_Value=80000000 -RCC.APB1Freq_Value=80000000 -RCC.APB1TimFreq_Value=80000000 -RCC.APB2Freq_Value=80000000 -RCC.APB2TimFreq_Value=80000000 -RCC.CortexFreq_Value=80000000 -RCC.DFSDMFreq_Value=80000000 -RCC.FCLKCortexFreq_Value=80000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=80000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=80000000 -RCC.I2C2Freq_Value=80000000 -RCC.I2C3Freq_Value=80000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value -RCC.LPTIM1Freq_Value=80000000 -RCC.LPTIM2Freq_Value=80000000 -RCC.LPUART1Freq_Value=80000000 -RCC.LSCOPinFreq_Value=32000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=80000000 -RCC.MSI_VALUE=4000000 -RCC.PLLN=20 -RCC.PLLPoutputFreq_Value=22857142.85714286 -RCC.PLLQoutputFreq_Value=80000000 -RCC.PLLRCLKFreq_Value=80000000 -RCC.PLLSAI1N=12 -RCC.PLLSAI1PoutputFreq_Value=13714285.714285715 -RCC.PLLSAI1QoutputFreq_Value=48000000 -RCC.PLLSAI1RoutputFreq_Value=48000000 -RCC.PLLSAI2PoutputFreq_Value=9142857.142857144 -RCC.PLLSAI2RoutputFreq_Value=32000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.PWRFreq_Value=80000000 -RCC.RNGFreq_Value=48000000 -RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE -RCC.RTCFreq_Value=32768 -RCC.SAI1Freq_Value=13714285.714285715 -RCC.SAI2Freq_Value=13714285.714285715 -RCC.SDMMCFreq_Value=48000000 -RCC.SWPMI1Freq_Value=80000000 -RCC.SYSCLKFreq_VALUE=80000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=80000000 -RCC.UART5Freq_Value=80000000 -RCC.USART1Freq_Value=80000000 -RCC.USART2Freq_Value=80000000 -RCC.USART3Freq_Value=80000000 -RCC.USBFreq_Value=48000000 -RCC.VCOInputFreq_Value=8000000 -RCC.VCOOutputFreq_Value=160000000 -RCC.VCOSAI1OutputFreq_Value=96000000 -RCC.VCOSAI2OutputFreq_Value=64000000 -SAI1.AudioFrequency-SAI_A_MasterWithClock=SAI_AUDIO_FREQUENCY_44K -SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-72.09 % -SAI1.IPParameters=Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock,InitProtocol-SAI_A_MasterWithClock,VirtualProtocol-SAI_A_BASIC,AudioFrequency-SAI_A_MasterWithClock,OutputDrive-SAI_A_MasterWithClock,Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,InitProtocol-SAI_B_SyncSlave,VirtualProtocol-SAI_B_BASIC -SAI1.InitProtocol-SAI_A_MasterWithClock=Enable -SAI1.InitProtocol-SAI_B_SyncSlave=Enable -SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A -SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B -SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE -SAI1.OutputDrive-SAI_A_MasterWithClock=SAI_OUTPUTDRIVE_ENABLE -SAI1.RealAudioFreq-SAI_A_MasterWithClock=53.571 KHz -SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER -SAI1.VirtualMode-SAI_B_SyncSlave=VM_SLAVE -SAI1.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL -SAI1.VirtualProtocol-SAI_B_BASIC=VM_BASIC_PROTOCOL -SH.ADCx_IN14.0=ADC1_IN14,IN14-Single-Ended -SH.ADCx_IN14.ConfNb=1 -SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 -SH.S_TIM1_CH1.ConfNb=1 -SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3 -SH.S_TIM2_CH3.ConfNb=1 -SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 -SH.S_TIM2_CH4.ConfNb=1 -SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 -SH.S_TIM4_CH2.ConfNb=1 -SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 -SH.S_TIM4_CH3.ConfNb=1 -SPI1.CalculateBaudRate=40.0 MBits/s -SPI1.Direction=SPI_DIRECTION_2LINES -SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -SPI1.Mode=SPI_MODE_MASTER -SPI1.VirtualType=VM_MASTER -SPI2.CalculateBaudRate=40.0 MBits/s -SPI2.Direction=SPI_DIRECTION_2LINES -SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -SPI2.Mode=SPI_MODE_MASTER -SPI2.VirtualType=VM_MASTER -SPI3.CalculateBaudRate=40.0 MBits/s -SPI3.Direction=SPI_DIRECTION_2LINES -SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -SPI3.Mode=SPI_MODE_MASTER -SPI3.VirtualType=VM_MASTER -TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 -TIM1.IPParameters=Channel-PWM Generation1 CH1 -TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 -TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -TIM2.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 -TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 -TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 -TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation2 CH2 -USART1.IPParameters=VirtualMode-Asynchronous -USART1.VirtualMode-Asynchronous=VM_ASYNC -USART2.IPParameters=VirtualMode-Asynchronous -USART2.VirtualMode-Asynchronous=VM_ASYNC -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_IWDG_VS_IWDG.Mode=IWDG_Activate -VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG -VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 -VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock -VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +RCC.MSI_VALUE=4000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +PA14\ (JTCK-SWCLK).Mode=Serial_Wire +RCC.PLLQoutputFreq_Value=80000000 +ProjectManager.ProjectFileName=STM32L475VE.ioc +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +PA7.Mode=Full_Duplex_Master +PA10.Mode=Asynchronous +Mcu.PinsNb=55 VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Mode=SAI_A_BASIC +ProjectManager.NoMain=false +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +ADC1.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,OffsetNumber-15\#ChannelRegularConversion,NbrOfConversionFlag,master +SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE +PC11.Signal=SDMMC1_D3 +RCC.SWPMI1Freq_Value=80000000 +PC8.Signal=SDMMC1_D0 +PE10.Mode=Single Bank +PC10.Mode=SD_4_bits_Wide_bus VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIA_SAI_BASIC -VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Mode=SAI_B_BASIC -VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIB_SAI_BASIC -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -VP_TIM15_VS_ClockSourceINT.Mode=Internal -VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT +ProjectManager.DefaultFWLocation=true +SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-72.09 % +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer -VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT -VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +ProjectManager.DeletePrevious=true +PB14.Locked=true +RCC.VCOSAI2OutputFreq_Value=64000000 VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT -VP_TIM1_VS_ClockSourceINT.Mode=Internal -VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT -VP_TIM2_VS_ClockSourceINT.Mode=Internal -VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT -VP_TIM4_VS_ClockSourceINT.Mode=Internal +RCC.FamilyName=M +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +USART1.VirtualMode-Asynchronous=VM_ASYNC +PA3.Mode=Asynchronous +SAI1.RealAudioFreq-SAI_A_MasterWithClock=53.571 KHz +PA9.Mode=Asynchronous +SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT +ProjectManager.TargetToolchain=MDK-ARM V5 +TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation2 CH2 +Mcu.Pin51=VP_TIM4_VS_ClockSourceINT +Mcu.Pin52=VP_TIM15_VS_ClockSourceINT +Mcu.Pin50=VP_TIM2_VS_ClockSourceINT +SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 +Mcu.Pin53=VP_TIM16_VS_ClockSourceINT +Mcu.Pin54=VP_TIM17_VS_ClockSourceINT +PA9.Signal=USART1_TX +VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT +PB5.Locked=true +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +RCC.USBFreq_Value=48000000 +PE11.Signal=QUADSPI_NCS +Mcu.Pin48=VP_SYS_VS_Systick +Mcu.Pin49=VP_TIM1_VS_ClockSourceINT +RCC.PLLSAI1PoutputFreq_Value=13714285.714285715 +Mcu.Pin46=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC +Mcu.Pin47=VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC +PB10.Signal=S_TIM2_CH3 +SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER +SH.S_TIM4_CH3.ConfNb=1 +VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Mode=SAI_B_BASIC +PB14.Signal=SPI2_MISO +PD2.Mode=SD_4_bits_Wide_bus +RCC.PLLSAI2RoutputFreq_Value=32000000 +PA5.Signal=SPI1_SCK +Mcu.Pin40=PB5 +Mcu.Pin41=PB7 +PC12.Mode=SD_4_bits_Wide_bus +Mcu.Pin44=VP_LPTIM1_VS_LPTIM_counterModeInternalClock +Mcu.Pin45=VP_RTC_VS_RTC_Activate +Mcu.Pin42=PB8 board=custom +Mcu.Pin43=VP_IWDG_VS_IWDG +SAI1.IPParameters=Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock,InitProtocol-SAI_A_MasterWithClock,VirtualProtocol-SAI_A_BASIC,AudioFrequency-SAI_A_MasterWithClock,OutputDrive-SAI_A_MasterWithClock,Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,InitProtocol-SAI_B_SyncSlave,VirtualProtocol-SAI_B_BASIC +RCC.VCOOutputFreq_Value=160000000 +ProjectManager.LastFirmware=true +PB15.Mode=Full_Duplex_Master +TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +RCC.APB2Freq_Value=80000000 +PE14.Signal=QUADSPI_BK1_IO2 +RCC.UART4Freq_Value=80000000 +SPI3.CalculateBaudRate=40.0 MBits/s +PE6.Mode=SAI_A_MasterWithClock +PE15.Signal=QUADSPI_BK1_IO3 +MxCube.Version=5.6.0 +Mcu.Pin37=PC12 +Mcu.Pin38=PD2 +Mcu.Pin35=PC10 +VP_TIM2_VS_ClockSourceINT.Mode=Internal +RCC.I2C1Freq_Value=80000000 +SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3 +Mcu.Pin36=PC11 +SPI1.Mode=SPI_MODE_MASTER +Mcu.Pin39=PB3 (JTDO-TRACESWO) +PE14.Mode=Single Bank +PB3\ (JTDO-TRACESWO).Mode=TX_Only_Simplex_Unidirect_Master +RCC.RNGFreq_Value=48000000 +PE5.Mode=SAI_A_MasterWithClock +RCC.PLLSAI1QoutputFreq_Value=48000000 +Mcu.Pin30=PA10 +RCC.ADCFreq_Value=48000000 +VP_SYS_VS_Systick.Mode=SysTick +TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +Mcu.Pin33=PA13 (JTMS-SWDIO) +Mcu.Pin34=PA14 (JTCK-SWCLK) +Mcu.Pin31=PA11 +Mcu.Pin32=PA12 +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +SH.S_TIM2_CH3.ConfNb=1 +PE6.Signal=SAI1_SD_A +RCC.UART5Freq_Value=80000000 +ProjectManager.FreePins=false +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value +ProjectManager.AskForMigrate=true +Mcu.Name=STM32L475V(C-E-G)Tx +RCC.LPTIM2Freq_Value=80000000 +Mcu.Pin26=PB15 +PE12.Signal=QUADSPI_BK1_IO0 +Mcu.Pin27=PC8 +PA2.Signal=USART2_TX +Mcu.Pin24=PB13 +ProjectManager.UnderRoot=false +Mcu.Pin25=PB14 +PE13.Locked=true +Mcu.IP8=SDMMC1 +Mcu.IP9=SPI1 +Mcu.Pin28=PC9 +Mcu.IP6=RTC +PC8.Mode=SD_4_bits_Wide_bus +Mcu.Pin29=PA9 +Mcu.IP7=SAI1 +ProjectManager.CoupleFile=false +PA13\ (JTMS-SWDIO).Mode=Serial_Wire +RCC.SYSCLKFreq_VALUE=80000000 +Mcu.Pin22=PB10 +PB5.Signal=SPI3_MOSI +Mcu.Pin23=PB11 +Mcu.Pin20=PE14 +ADC1.master=1 +Mcu.Pin21=PE15 +PA12.Mode=Device_Only +NVIC.ForceEnableDMAVector=true +RCC.PLLSAI2PoutputFreq_Value=9142857.142857144 +KeepUserPlacement=false +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +ProjectManager.CompilerOptimize=6 +SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B +PA11.Signal=USB_OTG_FS_DM +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_TIM15_VS_ClockSourceINT.Mode=Internal +ProjectManager.HeapSize=0x200 +Mcu.Pin15=PE9 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.Pin16=PE10 +Mcu.Pin13=PA7 +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +Mcu.Pin14=PC5 +Mcu.Pin19=PE13 +ProjectManager.ComputerToolchain=false +Mcu.Pin17=PE11 +RCC.HSI_VALUE=16000000 +Mcu.Pin18=PE12 +VP_TIM4_VS_ClockSourceINT.Mode=Internal +SAI1.VirtualProtocol-SAI_B_BASIC=VM_BASIC_PROTOCOL +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +ADC1.NbrOfConversionFlag=1 +Mcu.Pin11=PA5 +Mcu.Pin12=PA6 +RCC.PLLN=20 +Mcu.Pin10=PA3 +PB7.Locked=true +PE3.Signal=SAI1_SD_B +PA2.Mode=Asynchronous +PB8.Signal=S_TIM4_CH3 +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock +RCC.PWRFreq_Value=80000000 +PC9.Signal=SDMMC1_D1 +PD2.Signal=SDMMC1_CMD +RCC.I2C2Freq_Value=80000000 +RCC.APB1Freq_Value=80000000 +SAI1.InitProtocol-SAI_B_SyncSlave=Enable +ProjectManager.DeviceId=STM32L475VETx +ProjectManager.LibraryCopy=0 +PE15.Mode=Single Bank +PA7.Signal=SPI1_MOSI diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 1b25bb7567..7dc7cc3ad7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -478,10 +478,9 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) __HAL_RCC_GPIOB_CLK_ENABLE(); /**SPI3 GPIO Configuration PB3 (JTDO-TRACESWO) ------> SPI3_SCK - PB4 (NJTRST) ------> SPI3_MISO PB5 ------> SPI3_MOSI */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; @@ -551,10 +550,9 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /**SPI3 GPIO Configuration PB3 (JTDO-TRACESWO) ------> SPI3_SCK - PB4 (NJTRST) ------> SPI3_MISO PB5 ------> SPI3_MOSI */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_5); /* USER CODE BEGIN SPI3_MspDeInit 1 */ From 03eb616ff6f5227efd6bb786f33294283bf96246 Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Fri, 24 Apr 2020 08:46:56 +0800 Subject: [PATCH 21/27] [tools] fix c99/siginfo_t issue caused by gcc_version --- tools/utils.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/utils.py b/tools/utils.py index 9459396544..67ce098ccd 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -273,7 +273,7 @@ def VersionCmp(ver1, ver2): def GCCC99Patch(cflags): import building - gcc_version = building.GetDepend('GCC_VERSION') + gcc_version = building.GetDepend('GCC_VERSION_STR') if gcc_version: gcc_version = gcc_version.replace('"', '') if VersionCmp(gcc_version, "4.8.0") == 1: From 2099924e20fab8529cbd31487833a03368d23125 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Sun, 26 Apr 2020 09:52:31 +0800 Subject: [PATCH 22/27] add raspi3 mbox option --- bsp/raspberry-pi/raspi3-64/driver/mbox.c | 401 +++++++++++++++++++++++ bsp/raspberry-pi/raspi3-64/driver/mbox.h | 64 +++- 2 files changed, 464 insertions(+), 1 deletion(-) diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.c b/bsp/raspberry-pi/raspi3-64/driver/mbox.c index 1d995340d6..dc09ecab4b 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/mbox.c +++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.c @@ -47,3 +47,404 @@ int mbox_call(unsigned char ch, int mmu_enable) } return 0; } + +int bcm283x_mbox_hardware_get_model(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + return mbox[5]; +} + +int bcm283x_mbox_hardware_get_revison(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_REV; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + return mbox[5]; +} + +int bcm283x_mbox_hardware_get_mac_address(uint8_t * mac) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS; + mbox[3] = 6; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + char * mac_str = (char *)&mbox[5]; + mac[0] = mac_str[0]; + mac[1] = mac_str[1]; + mac[2] = mac_str[2]; + mac[3] = mac_str[3]; + mac[4] = mac_str[4]; + mac[5] = mac_str[5]; + return 0; +} + + +int bcm283x_mbox_hardware_get_serial(rt_uint64_t* sn) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL; + mbox[3] = 8; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + sn = (rt_uint64_t *)&mbox[5]; + + return 0; +} + +int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY; + mbox[3] = 8; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + *base = mbox[5]; + *size = mbox[6]; + + return 0; + +} + +int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY; + mbox[3] = 8; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + *base = mbox[5]; + *size = mbox[6]; + + return 0; +} + +int bcm283x_mbox_clock_get_turbo(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = 0; // id + mbox[6] = 0; // val + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_clock_set_turbo(int level) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_TURBO; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = 0; // id + mbox[6] = level ? 1 : 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_clock_get_state(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm283x_mbox_clock_set_state(int id, int state) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = id; // id + mbox[6] = state & 0x3; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm283x_mbox_clock_get_rate(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_clock_set_rate(int id, int rate) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = id; // id + mbox[6] = rate; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_clock_get_max_rate(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_clock_get_min_rate(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_power_get_state(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_POWER_GET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm283x_mbox_power_set_state(int id, int state) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_POWER_SET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = id; // id + mbox[6] = state & 0x3; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm283x_mbox_temp_get(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_TEMP_GET; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = 0; //id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} + +int bcm283x_mbox_temp_get_max(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_TEMP_GET_MAX; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.h b/bsp/raspberry-pi/raspi3-64/driver/mbox.h index eb7eb0318c..f235691d7b 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/mbox.h +++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.h @@ -12,7 +12,7 @@ #ifndef __MBOX_H__ #define __MBOX_H__ - +#include /* a properly aligned buffer */ extern volatile unsigned int* mbox; @@ -56,7 +56,69 @@ extern volatile unsigned int* mbox; #define MMU_ENABLE 1 #define MMU_DISABLE 0 +/* + * raspi hardware info + */ +enum { + MBOX_TAG_HARDWARE_GET_MODEL = 0x00010001, + MBOX_TAG_HARDWARE_GET_REV = 0x00010002, + MBOX_TAG_HARDWARE_GET_MAC_ADDRESS = 0x00010003, + MBOX_TAG_HARDWARE_GET_SERIAL = 0x00010004, + MBOX_TAG_HARDWARE_GET_ARM_MEMORY = 0x00010005, + MBOX_TAG_HARDWARE_GET_VC_MEMORY = 0x00010006, + MBOX_TAG_HARDWARE_GET_CLOCKS = 0x00010007, +}; + +/* + * raspi clock + */ +enum { + MBOX_TAG_CLOCK_GET_TURBO = 0x00030009, + MBOX_TAG_CLOCK_SET_TURBO = 0x00038009, + MBOX_TAG_CLOCK_GET_STATE = 0x00030001, + MBOX_TAG_CLOCK_SET_STATE = 0x00038001, + MBOX_TAG_CLOCK_GET_RATE = 0x00030002, + MBOX_TAG_CLOCK_SET_RATE = 0x00038002, + MBOX_TAG_CLOCK_GET_MAX_RATE = 0x00030004, + MBOX_TAG_CLOCK_GET_MIN_RATE = 0x00030007, +}; + +/* + * raspi power + */ +enum { + MBOX_TAG_POWER_GET_STATE = 0x00020001, + MBOX_TAG_POWER_SET_STATE = 0x00028001, +}; + +/* + * raspi temperature + */ +enum { + MBOX_TAG_TEMP_GET = 0x00030006, + MBOX_TAG_TEMP_GET_MAX = 0x0003000A, +}; + #define MBOX_ADDR 0xc00000 int mbox_call(unsigned char ch, int mmu_enable); +int bcm283x_mbox_hardware_get_model(void); +int bcm283x_mbox_hardware_get_revison(void); +int bcm283x_mbox_hardware_get_mac_address(uint8_t * mac); +int bcm283x_mbox_hardware_get_serial(rt_uint64_t* sn); +int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size); +int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size); +int bcm283x_mbox_clock_get_turbo(void); +int bcm283x_mbox_clock_set_turbo(int level); +int bcm283x_mbox_clock_get_state(int id); +int bcm283x_mbox_clock_set_state(int id, int state); +int bcm283x_mbox_clock_get_rate(int id); +int bcm283x_mbox_clock_set_rate(int id, int rate); +int bcm283x_mbox_clock_get_max_rate(int id); +int bcm283x_mbox_clock_get_min_rate(int id); +int bcm283x_mbox_power_get_state(int id); +int bcm283x_mbox_power_set_state(int id, int state); +int bcm283x_mbox_temp_get(void); +int bcm283x_mbox_temp_get_max(void); + #endif From 6251fc93b6e8be24391bd17db9f1540d740491f2 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Sun, 26 Apr 2020 09:53:41 +0800 Subject: [PATCH 23/27] [bsp/raspi]fix hdmi driver --- bsp/raspberry-pi/raspi3-64/driver/drv_fb.c | 164 ++++++++++++++++++--- 1 file changed, 145 insertions(+), 19 deletions(-) diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c index d4abc4fd60..cabaded5fd 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c @@ -15,9 +15,10 @@ #include "drv_fb.h" #include "mmu.h" -#define LCD_WIDTH (640) +#define LCD_WIDTH (800) #define LCD_HEIGHT (480) #define LCD_DEPTH (32) +#define LCD_BPP (32) #define TAG_ALLOCATE_BUFFER 0x00040001 #define TAG_SET_PHYS_WIDTH_HEIGHT 0x00048003 @@ -28,6 +29,39 @@ #define TAG_SET_VIRT_OFFSET 0x00048009 #define TAG_END 0x00000000 + +enum { + MBOX_TAG_FB_GET_GPIOVIRT = 0x00040010, + MBOX_TAG_FB_ALLOCATE_BUFFER = 0x00040001, + MBOX_TAG_FB_RELEASE_BUFFER = 0x00048001, + MBOX_TAG_FB_BLANK_SCREEN = 0x00040002, + MBOX_TAG_FB_GET_PHYS_WH = 0x00040003, + MBOX_TAG_FB_TEST_PHYS_WH = 0x00044003, + MBOX_TAG_FB_SET_PHYS_WH = 0x00048003, + MBOX_TAG_FB_GET_VIRT_WH = 0x00040004, + MBOX_TAG_FB_TEST_VIRT_WH = 0x00044004, + MBOX_TAG_FB_SET_VIRT_WH = 0x00048004, + MBOX_TAG_FB_GET_DEPTH = 0x00040005, + MBOX_TAG_FB_TEST_DEPTH = 0x00044005, + MBOX_TAG_FB_SET_DEPTH = 0x00048005, + MBOX_TAG_FB_GET_PIXEL_ORDER = 0x00040006, + MBOX_TAG_FB_TEST_PIXEL_ORDER = 0x00044006, + MBOX_TAG_FB_SET_PIXEL_ORDER = 0x00048006, + MBOX_TAG_FB_GET_ALPHA_MODE = 0x00040007, + MBOX_TAG_FB_TEST_ALPHA_MODE = 0x00044007, + MBOX_TAG_FB_SET_ALPHA_MODE = 0x00048007, + MBOX_TAG_FB_GET_PITCH = 0x00040008, + MBOX_TAG_FB_GET_VIRT_OFFSET = 0x00040009, + MBOX_TAG_FB_TEST_VIRT_OFFSET = 0x00044009, + MBOX_TAG_FB_SET_VIRT_OFFSET = 0x00048009, + MBOX_TAG_FB_GET_OVERSCAN = 0x0004000a, + MBOX_TAG_FB_TEST_OVERSCAN = 0x0004400a, + MBOX_TAG_FB_SET_OVERSCAN = 0x0004800a, + MBOX_TAG_FB_GET_PALETTE = 0x0004000b, + MBOX_TAG_FB_TEST_PALETTE = 0x0004400b, + MBOX_TAG_FB_SET_PALETTE = 0x0004800b, +}; + #define LCD_DEVICE(dev) (struct rt_hdmi_fb_device*)(dev) static struct rt_hdmi_fb_device _hdmi; @@ -75,7 +109,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) info->bits_per_pixel= LCD_DEPTH; info->width = lcd->width; info->height = lcd->height; - info->framebuffer = lcd->fb;//(rt_uint8_t *)lcd->fb; + info->framebuffer = lcd->fb; } break; } @@ -119,38 +153,122 @@ rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *n return RT_EOK; } -int hdmi_fb_init(void) +rt_uint32_t bcm283x_mbox_fb_get_gpiovirt(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return (mbox[5] & 0x3fffffff); +} + +rt_uint32_t bcm283x_mbox_fb_get_pitch(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_GET_PITCH; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return mbox[5]; +} + +void bcm283x_mbox_fb_set_porder(int rgb) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER; + mbox[3] = 4; // buffer size + mbox[4] = 4; // len + + mbox[5] = rgb; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + +void bcm283x_mbox_fb_setoffset(int xoffset, int yoffset) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = xoffset; // id + mbox[6] = yoffset; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + + +void bcm283x_mbox_fb_setalpha(int alpha) +{ + + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE; + mbox[3] = 4; // buffer size + mbox[4] = 4; // len + + mbox[5] = alpha; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + +void *bcm283x_mbox_fb_alloc(int width, int height, int bpp, int nrender) { mbox[0] = 4 * 35; mbox[1] = MBOX_REQUEST; mbox[2] = TAG_ALLOCATE_BUFFER;//get framebuffer, gets alignment on request - mbox[3] = 8; - mbox[4] = 0; - mbox[5] = 4096; //FrameBufferInfo.pointer - mbox[6] = 0; //FrameBufferInfo.size + mbox[3] = 8; //size + mbox[4] = 4; //len + mbox[5] = 4096; //The design of MBOX driver forces us to give the virtual address 0x3C100000 + mbox[6] = 0; //FrameBufferInfo.size mbox[7] = TAG_SET_PHYS_WIDTH_HEIGHT; mbox[8] = 8; - mbox[9] = 0; - mbox[10] = LCD_WIDTH; - mbox[11] = LCD_HEIGHT; + mbox[9] = 8; + mbox[10] = width; + mbox[11] = height; mbox[12] = TAG_SET_VIRT_WIDTH_HEIGHT; mbox[13] = 8; - mbox[14] = 0; - mbox[15] = LCD_WIDTH; - mbox[16] = LCD_HEIGHT; + mbox[14] = 8; + mbox[15] = width; + mbox[16] = height * nrender; mbox[17] = TAG_SET_DEPTH; mbox[18] = 4; - mbox[19] = 0; - mbox[20] = 16; //FrameBufferInfo.depth RGB 565 + mbox[19] = 4; + mbox[20] = bpp; mbox[21] = TAG_SET_PIXEL_ORDER; mbox[22] = 4; mbox[23] = 0; - mbox[24] = 1; //RGB, not BGR preferably + mbox[24] = 0; //RGB, not BGR preferably mbox[25] = TAG_GET_PITCH; mbox[26] = 4; @@ -167,17 +285,25 @@ int hdmi_fb_init(void) mbox_call(MBOX_CH_PROP, MMU_DISABLE); - _hdmi.fb = (rt_uint8_t *)(uintptr_t)(mbox[5] & 0x3FFFFFFF); + return (void *)((rt_uint64_t)(mbox[5] & 0x3fffffff)); +} +int hdmi_fb_init(void) +{ + _hdmi.fb = (rt_uint8_t *)bcm283x_mbox_fb_alloc(LCD_WIDTH, LCD_HEIGHT, LCD_BPP, 1); + bcm283x_mbox_fb_setoffset(0, 0); + bcm283x_mbox_fb_set_porder(0); _hdmi.width = LCD_WIDTH; _hdmi.height = LCD_HEIGHT; _hdmi.depth = LCD_DEPTH; _hdmi.pitch = 0; _hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; - armv8_map((unsigned long)_hdmi.fb, (unsigned long)_hdmi.fb, 0x200000, MEM_ATTR_MEMORY); + armv8_map((unsigned long)_hdmi.fb, (unsigned long)_hdmi.fb, 0x200000, MEM_ATTR_IO); - rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb); + rt_hw_dcache_invalidate_range((unsigned long)_hdmi.fb,LCD_WIDTH * LCD_HEIGHT * 3); + + //rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb); rt_hdmi_fb_device_init(&_hdmi, "lcd"); return 0; From 609911bee9c1235151f5328e7dcae9880d6861f6 Mon Sep 17 00:00:00 2001 From: Fu Wei Date: Tue, 14 Apr 2020 14:53:39 +0800 Subject: [PATCH 24/27] [RISC-V:K210]Add UART1~3 support for K210 This patch adds UART1~3 support for K210, and separates the rt_uart_ops of UARTHS from UART. This patch add configs in Kconfig for configuring the pins of UARTx, please check the sysctl_set_power_mode for the pins in the io_config_init of bsp/k210/driver/drv_io_config.c Signed-off-by: Fu Wei --- bsp/k210/driver/Kconfig | 41 ++++- bsp/k210/driver/drv_io_config.c | 22 ++- bsp/k210/driver/drv_uart.c | 302 +++++++++++++++++++++++++++----- 3 files changed, 318 insertions(+), 47 deletions(-) diff --git a/bsp/k210/driver/Kconfig b/bsp/k210/driver/Kconfig index 4d38a7c9b2..8acbf5202c 100644 --- a/bsp/k210/driver/Kconfig +++ b/bsp/k210/driver/Kconfig @@ -2,17 +2,44 @@ config BSP_USING_UART_HS bool "Enable High Speed UART" default y -config BSP_USING_UART1 - bool "Enable UART1 (GPIO0/1)" - default n +menu "General Purpose UARTs" -config BSP_USING_UART2 - bool "Enable UART2 (GPIO0/1)" +menuconfig BSP_USING_UART1 + bool "Enable UART1" default n + if BSP_USING_UART1 + config BSP_UART1_TXD_PIN + int "uart1 TXD pin number" + default 20 + config BSP_UART1_RXD_PIN + int "uart1 RXD pin number" + default 21 + endif -config BSP_USING_UART3 - bool "Enable UART3 (GPIO0/1)" +menuconfig BSP_USING_UART2 + bool "Enable UART2" default n + if BSP_USING_UART2 + config BSP_UART2_TXD_PIN + int "uart2 TXD pin number" + default 28 + config BSP_UART2_RXD_PIN + int "uart2 RXD pin number" + default 27 + endif + +menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_TXD_PIN + int "uart3 TXD pin number" + default 22 + config BSP_UART3_RXD_PIN + int "uart3 RXD pin number" + default 23 + endif +endmenu config BSP_USING_I2C1 bool "Enable I2C1 (GPIO0/1)" diff --git a/bsp/k210/driver/drv_io_config.c b/bsp/k210/driver/drv_io_config.c index cd0e8f27f6..3098537eae 100644 --- a/bsp/k210/driver/drv_io_config.c +++ b/bsp/k210/driver/drv_io_config.c @@ -63,6 +63,18 @@ static struct io_config #endif #endif +#ifdef BSP_USING_UART1 + IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX), + IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX), +#endif +#ifdef BSP_USING_UART2 + IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX), + IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX), +#endif +#ifdef BSP_USING_UART3 + IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX), + IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX), +#endif }; static int print_io_config() @@ -89,7 +101,15 @@ int io_config_init(void) sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18); sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18); sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18); - +#ifdef BSP_USING_UART2 + // for IO-27/28 + sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33); +#endif +#if defined(BSP_USING_UART1) || defined(BSP_USING_UART3) + // for IO-20~23 + sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33); +#endif + for(i = 0; i < count; i++) { fpioa_set_function(io_config[i].io_num, io_config[i].func); diff --git a/bsp/k210/driver/drv_uart.c b/bsp/k210/driver/drv_uart.c index 7e22d40c5d..830b14cbbc 100644 --- a/bsp/k210/driver/drv_uart.c +++ b/bsp/k210/driver/drv_uart.c @@ -17,10 +17,12 @@ #include #include -// #include "uart.h" +#include "uart.h" #include "uarths.h" #include "plic.h" +#define UART_DEFAULT_BAUDRATE 115200 + static volatile uarths_t *const _uarths = (volatile uarths_t *)UARTHS_BASE_ADDR; struct device_uart @@ -29,22 +31,71 @@ struct device_uart rt_uint32_t irqno; }; -static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t rt_uarths_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t uarths_control(struct rt_serial_device *serial, int cmd, void *arg); +static int drv_uarths_putc(struct rt_serial_device *serial, char c); +static int drv_uarths_getc(struct rt_serial_device *serial); + +static void uarths_irq_handler(int irqno, void *param); + +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg); static int drv_uart_putc(struct rt_serial_device *serial, char c); static int drv_uart_getc(struct rt_serial_device *serial); static void uart_irq_handler(int irqno, void *param); +const struct rt_uart_ops _uart_hs_ops = +{ + rt_uarths_configure, + uarths_control, + drv_uarths_putc, + drv_uarths_getc, + RT_NULL +}; + const struct rt_uart_ops _uart_ops = { - uart_configure, + rt_uart_configure, uart_control, drv_uart_putc, drv_uart_getc, + //TODO: add DMA support RT_NULL }; +/* START ported from kendryte standalone sdk uart.c */ +#define __UART_BRATE_CONST 16 + +volatile uart_t* const _uart[3] = +{ + (volatile uart_t*)UART1_BASE_ADDR, + (volatile uart_t*)UART2_BASE_ADDR, + (volatile uart_t*)UART3_BASE_ADDR +}; + +void uart_init(uart_device_number_t channel) +{ + sysctl_clock_enable(SYSCTL_CLOCK_UART1 + channel); + sysctl_reset(SYSCTL_RESET_UART1 + channel); +} + +/* END ported from kendryte standalone sdk uart.c */ +static inline uart_device_number_t _get_uart_channel(rt_uint32_t addr) +{ + switch (addr) + { + case UART1_BASE_ADDR: + return UART_DEVICE_1; + case UART2_BASE_ADDR: + return UART_DEVICE_2; + case UART3_BASE_ADDR: + return UART_DEVICE_3; + default: + return UART_DEVICE_MAX; + } +} + /* * UART Initiation */ @@ -62,7 +113,7 @@ int rt_hw_uart_init(void) serial = &serial_hs; uart = &uart_hs; - serial->ops = &_uart_ops; + serial->ops = &_uart_hs_ops; serial->config = config; serial->config.baud_rate = 115200; @@ -86,36 +137,79 @@ int rt_hw_uart_init(void) serial->ops = &_uart_ops; serial->config = config; - serial->config.baud_rate = 115200; + serial->config.baud_rate = UART_DEFAULT_BAUDRATE; uart->hw_base = UART1_BASE_ADDR; uart->irqno = IRQN_UART1_INTERRUPT; + uart_init(UART_DEVICE_1); + rt_hw_serial_register(serial, - "uarths", + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); } #endif #ifdef BSP_USING_UART2 + { + static struct rt_serial_device serial2; + static struct device_uart uart2; + + serial = &serial2; + uart = &uart2; + + serial->ops = &_uart_ops; + serial->config = config; + serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + uart->hw_base = UART2_BASE_ADDR; + uart->irqno = IRQN_UART2_INTERRUPT; + + uart_init(UART_DEVICE_2); + + rt_hw_serial_register(serial, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + } #endif #ifdef BSP_USING_UART3 + { + static struct rt_serial_device serial3; + static struct device_uart uart3; + + serial = &serial3; + uart = &uart3; + + serial->ops = &_uart_ops; + serial->config = config; + serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + uart->hw_base = UART3_BASE_ADDR; + uart->irqno = IRQN_UART3_INTERRUPT; + + uart_init(UART_DEVICE_3); + + rt_hw_serial_register(serial, + "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + } #endif return 0; } /* - * UART interface + * UARTHS interface */ -static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +static rt_err_t rt_uarths_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - rt_uint32_t baud_div; struct device_uart *uart; - uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); - uint16_t div = freq / cfg->baud_rate - 1; + uint32_t freq_hs = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); + uint16_t div_hs = freq_hs / cfg->baud_rate - 1; RT_ASSERT(serial != RT_NULL); serial->config = *cfg; @@ -125,7 +219,7 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co if (uart->hw_base == UARTHS_BASE_ADDR) { - _uarths->div.div = div; + _uarths->div.div = div_hs; _uarths->txctrl.txen = 1; _uarths->rxctrl.rxen = 1; _uarths->txctrl.txcnt = 0; @@ -137,13 +231,14 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co } else { + return (-1); /* other uart */ } return (RT_EOK); } -static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +static rt_err_t uarths_control(struct rt_serial_device *serial, int cmd, void *arg) { struct device_uart *uart; @@ -160,7 +255,7 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CTRL_SET_INT: /* install interrupt */ - rt_hw_interrupt_install(uart->irqno, uart_irq_handler, + rt_hw_interrupt_install(uart->irqno, uarths_irq_handler, serial, serial->parent.parent.name); rt_hw_interrupt_umask(uart->irqno); break; @@ -169,38 +264,168 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg return (RT_EOK); } -static int drv_uart_putc(struct rt_serial_device *serial, char c) + +static int drv_uarths_putc(struct rt_serial_device *serial, char c) +{ + struct device_uart *uart = serial->parent.user_data; + RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR); + + while (_uarths->txdata.full); + _uarths->txdata.data = (uint8_t)c; + + return (1); +} + +static int drv_uarths_getc(struct rt_serial_device *serial) +{ + struct device_uart *uart = serial->parent.user_data; + RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR); + + uarths_rxdata_t recv = _uarths->rxdata; + if (recv.empty) + return EOF; + else + return (recv.data & 0xff); + /* Receive Data Available */ + + return (-1); +} + +/* UARTHS ISR */ +static void uarths_irq_handler(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + struct device_uart *uart = serial->parent.user_data; + RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR); + + /* read interrupt status and clear it */ + if (_uarths->ip.rxwm) + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +/* + * UART interface + */ +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct device_uart *uart; + uart_bitwidth_t data_width = (uart_bitwidth_t)cfg->data_bits ; + uart_stopbit_t stopbit = (uart_stopbit_t)cfg->stop_bits; + uart_parity_t parity = (uart_parity_t)cfg->parity; + + uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + uint32_t divisor = freq / (uint32_t)cfg->baud_rate; + uint8_t dlh = divisor >> 12; + uint8_t dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; + uint8_t dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; + + RT_ASSERT(serial != RT_NULL); + serial->config = *cfg; + + uart = serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + uart_device_number_t channel = _get_uart_channel(uart->hw_base); + RT_ASSERT(channel != UART_DEVICE_MAX); + + RT_ASSERT(data_width >= 5 && data_width <= 8); + if (data_width == 5) + { + RT_ASSERT(stopbit != UART_STOP_2); + } + else + { + RT_ASSERT(stopbit != UART_STOP_1_5); + } + + uint32_t stopbit_val = stopbit == UART_STOP_1 ? 0 : 1; + uint32_t parity_val; + switch (parity) + { + case UART_PARITY_NONE: + parity_val = 0; + break; + case UART_PARITY_ODD: + parity_val = 1; + break; + case UART_PARITY_EVEN: + parity_val = 3; + break; + default: + RT_ASSERT(!"Invalid parity"); + break; + } + + _uart[channel]->LCR |= 1u << 7; + _uart[channel]->DLH = dlh; + _uart[channel]->DLL = dll; + _uart[channel]->DLF = dlf; + _uart[channel]->LCR = 0; + _uart[channel]->LCR = (data_width - 5) | + (stopbit_val << 2) | + (parity_val << 3); + _uart[channel]->LCR &= ~(1u << 7); + _uart[channel]->IER |= 0x80; /* THRE */ + _uart[channel]->FCR = UART_RECEIVE_FIFO_1 << 6 | + UART_SEND_FIFO_8 << 4 | + 0x1 << 3 | + 0x1; + + return (RT_EOK); +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) { struct device_uart *uart; uart = serial->parent.user_data; - if (uart->hw_base == UARTHS_BASE_ADDR) + uart_device_number_t channel = _get_uart_channel(uart->hw_base); + + RT_ASSERT(uart != RT_NULL); + RT_ASSERT(channel != UART_DEVICE_MAX); + + switch (cmd) { - while (_uarths->txdata.full); - _uarths->txdata.data = (uint8_t)c; - } - else - { - /* other uart */ + case RT_DEVICE_CTRL_CLR_INT: + /* Disable the UART Interrupt */ + rt_hw_interrupt_mask(uart->irqno); + _uart[channel]->IER &= ~0x1; + break; + + case RT_DEVICE_CTRL_SET_INT: + /* install interrupt */ + rt_hw_interrupt_install(uart->irqno, uart_irq_handler, + serial, serial->parent.parent.name); + rt_hw_interrupt_umask(uart->irqno); + _uart[channel]->IER |= 0x1; + break; } + return (RT_EOK); +} + +static int drv_uart_putc(struct rt_serial_device *serial, char c) +{ + struct device_uart *uart = serial->parent.user_data; + uart_device_number_t channel = _get_uart_channel(uart->hw_base); + RT_ASSERT(channel != UART_DEVICE_MAX); + + while (_uart[channel]->LSR & (1u << 5)); + _uart[channel]->THR = c; + return (1); } static int drv_uart_getc(struct rt_serial_device *serial) { - int ret = -1; struct device_uart *uart = serial->parent.user_data; + uart_device_number_t channel = _get_uart_channel(uart->hw_base); + RT_ASSERT(channel != UART_DEVICE_MAX); - if (uart->hw_base == UARTHS_BASE_ADDR) - { - uarths_rxdata_t recv = _uarths->rxdata; - if (recv.empty) - return EOF; - else - return (recv.data & 0xff); - } - + if (_uart[channel]->LSR & 1) + return (char)(_uart[channel]->RBR & 0xff); + else + return EOF; /* Receive Data Available */ return (-1); @@ -209,21 +434,20 @@ static int drv_uart_getc(struct rt_serial_device *serial) /* UART ISR */ static void uart_irq_handler(int irqno, void *param) { - rt_ubase_t isr; struct rt_serial_device *serial = (struct rt_serial_device *)param; struct device_uart *uart = serial->parent.user_data; + uart_device_number_t channel = _get_uart_channel(uart->hw_base); + RT_ASSERT(channel != UART_DEVICE_MAX); /* read interrupt status and clear it */ - if (uart->hw_base == UARTHS_BASE_ADDR) - { - if (_uarths->ip.rxwm) - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - } + if (_uart[channel]->LSR) + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } /* WEAK for SDK 0.5.6 */ -RT_WEAK void uart_debug_init(int uart_channel) +RT_WEAK void uart_debug_init(uart_device_number_t uart_channel) { } + From 9d374f873cc9d3f0ee1af5f463fcaeee75d5f6e8 Mon Sep 17 00:00:00 2001 From: hphuang Date: Tue, 28 Apr 2020 19:07:08 +0800 Subject: [PATCH 25/27] mstorage.c: fix the issue that _read_capacity() returns the wrong last valid address of storage medium --- components/drivers/usb/usbdevice/class/mstorage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/drivers/usb/usbdevice/class/mstorage.c b/components/drivers/usb/usbdevice/class/mstorage.c index 43fb25afe4..a681b8212f 100644 --- a/components/drivers/usb/usbdevice/class/mstorage.c +++ b/components/drivers/usb/usbdevice/class/mstorage.c @@ -426,7 +426,7 @@ static rt_size_t _read_capacity(ufunction_t func, ustorage_cbw_t cbw) data = (struct mstorage*)func->user_data; buf = data->ep_in->buffer; - sector_count = data->geometry.sector_count; + sector_count = data->geometry.sector_count - 1; /* Last Logical Block Address */ sector_size = data->geometry.bytes_per_sector; buf[0] = sector_count >> 24; From 79b44d29ad2c03b0634635797fb60b810b29eba3 Mon Sep 17 00:00:00 2001 From: Maofeng Date: Tue, 28 Apr 2020 03:23:09 +0800 Subject: [PATCH 26/27] [bsp\nrf5x]Support BSP UART0 --- bsp/nrf5x/libraries/drivers/drv_uart.c | 129 ++++++++++++++----------- bsp/nrf5x/nrf52840/board/Kconfig | 17 +++- bsp/nrf5x/nrf52840/rtconfig.h | 3 + 3 files changed, 89 insertions(+), 60 deletions(-) diff --git a/bsp/nrf5x/libraries/drivers/drv_uart.c b/bsp/nrf5x/libraries/drivers/drv_uart.c index b310fa57a4..08c7148353 100644 --- a/bsp/nrf5x/libraries/drivers/drv_uart.c +++ b/bsp/nrf5x/libraries/drivers/drv_uart.c @@ -1,59 +1,83 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-28 xckhmf Modify for + * + */ #include #include #include "drv_uart.h" -static struct rt_serial_device _serial0_0; -static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context); +#ifdef BSP_USING_UART typedef struct { struct rt_serial_device *serial; nrfx_uart_t uart; + uint8_t rx_byte; + uint16_t rx_length; uint32_t rx_pin; uint32_t tx_pin; nrfx_uart_event_handler_t event_handler; -} UART_CFG_T; +} drv_uart_cfg_t; - -UART_CFG_T uart0 = { +#ifdef BSP_USING_UART0 +static struct rt_serial_device _serial_0; +static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context); +drv_uart_cfg_t m_uart0_cfg = { .uart = NRFX_UART_INSTANCE(0), -#ifdef RT_USING_CONSOLE - .rx_pin = 8, - .tx_pin = 6, - .event_handler = uart_event_hander, -#else - .rx_pin = 19, - .tx_pin = 20 -#endif + .rx_byte = 0, + .rx_length = 0, + .rx_pin = BSP_UART0_RX_PIN, + .tx_pin = BSP_UART0_TX_PIN, + .event_handler = uart0_event_hander }; -UART_CFG_T *working_cfg = RT_NULL; +#endif /* BSP_USING_UART0 */ -static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context) -{ - +#ifdef BSP_USING_UART1 + #error not support UART1. Use UART0 instead. +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART0 +static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context) +{ if (p_event->type == NRFX_UART_EVT_RX_DONE) { - rt_hw_serial_isr(working_cfg->serial, RT_SERIAL_EVENT_RX_IND); + if(p_event->data.rxtx.bytes == 1) + { + m_uart0_cfg.rx_length = p_event->data.rxtx.bytes; + + /* rx_byte equal p_data */ + //m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data); + + rt_hw_serial_isr(m_uart0_cfg.serial, RT_SERIAL_EVENT_RX_IND); + } + nrfx_uart_rx(&(m_uart0_cfg.uart),&m_uart0_cfg.rx_byte,1); } if (p_event->type == NRFX_UART_EVT_TX_DONE) { - + /* @TODO:[RT_DEVICE_FLAG_INT_TX]*/ } } +#endif /* BSP_USING_UART0 */ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg) { - nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(uart0.tx_pin,uart0.rx_pin); - UART_CFG_T *instance = &uart0; + nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(BSP_UART0_TX_PIN,BSP_UART0_RX_PIN); + drv_uart_cfg_t *instance = RT_NULL; RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - - if (serial->parent.user_data != RT_NULL) + + if (serial->parent.user_data == RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + return -RT_ERROR; } - + instance = (drv_uart_cfg_t*)serial->parent.user_data; nrfx_uart_uninit(&(instance->uart)); switch (cfg->baud_rate) @@ -83,28 +107,23 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED; config.pselrxd = instance->rx_pin; config.pseltxd = instance->tx_pin; - + nrfx_uart_init(&(instance->uart), &config, instance->event_handler); - - nrf_uart_int_enable(instance->uart.p_reg, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_RXTO | NRF_UART_INT_MASK_ERROR); + nrfx_uart_rx(&(instance->uart),&(instance->rx_byte),1); nrf_uart_int_disable(instance->uart.p_reg, NRF_UART_INT_MASK_TXDRDY); - - nrfx_uart_rx_enable(&(instance->uart)); - - working_cfg = instance; return RT_EOK; } static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) { - UART_CFG_T *instance = working_cfg; - + drv_uart_cfg_t *instance = NULL; RT_ASSERT(serial != RT_NULL); - if (serial->parent.user_data != RT_NULL) + if (serial->parent.user_data == RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + return -RT_ERROR; } + instance = (drv_uart_cfg_t*)serial->parent.user_data; switch (cmd) { @@ -129,10 +148,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) break; case RT_DEVICE_CTRL_PIN: - if (working_cfg != instance) - { - _uart_cfg(instance->serial, &(instance->serial->config)); - } + _uart_cfg(instance->serial, &(instance->serial->config)); break; case RT_DEVICE_POWERSAVE: @@ -152,13 +168,13 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) static int _uart_putc(struct rt_serial_device *serial, char c) { - UART_CFG_T *instance = working_cfg; + drv_uart_cfg_t *instance = NULL; int rtn = 1; RT_ASSERT(serial != RT_NULL); if (serial->parent.user_data != RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + instance = (drv_uart_cfg_t*)serial->parent.user_data; } nrf_uart_event_clear(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY); @@ -171,23 +187,21 @@ static int _uart_putc(struct rt_serial_device *serial, char c) return rtn; } -/* - @note: this function is invaild ,the cause of the problem is [nrfx_uart.c - line 340] -*/ static int _uart_getc(struct rt_serial_device *serial) { int ch = -1; - UART_CFG_T *instance = working_cfg; - + drv_uart_cfg_t *instance = NULL; RT_ASSERT(serial != RT_NULL); if (serial->parent.user_data != RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + instance = (drv_uart_cfg_t*)serial->parent.user_data; + } + if(instance->rx_length) + { + ch = instance->rx_byte; + instance->rx_length--; } - - ch = (int)(nrf_uart_rxd_get(instance->uart.p_reg)); - return ch; } @@ -202,11 +216,14 @@ void rt_hw_uart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - config.bufsz = RT_SERIAL_RB_BUFSZ; - _serial0_0.config = config; - _serial0_0.ops = &_uart_ops; - uart0.serial = &_serial0_0; +#ifdef BSP_USING_UART0 + _serial_0.config = config; + _serial_0.ops = &_uart_ops; + m_uart0_cfg.serial = &_serial_0; + rt_hw_serial_register(&_serial_0, "uart0", \ + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &m_uart0_cfg); +#endif /* BSP_USING_UART0 */ - rt_hw_serial_register(&_serial0_0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart0); } +#endif /* BSP_USING_UART */ diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index b7edace9e8..e05787c775 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -2,14 +2,14 @@ menu "Hardware Drivers Config" config SOC_NRF52840 bool - config SOC_NRF52840 + config SOC_NRF52840 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y menu "Onboard Peripheral Drivers" config BSP_USING_JLINK_TO_USART - bool "Enable JLINK TO USART (uart0)" + bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)" select BSP_USING_UART select BSP_USING_UART0 default y @@ -30,11 +30,20 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART0 bool "Enable UART0" default y - + if BSP_USING_UART0 + config BSP_UART0_RX_PIN + int "uart0 rx pin number" + range 0 31 + default 8 + config BSP_UART0_TX_PIN + int "uart0 tx pin number" + range 0 31 + default 6 + endif config BSP_USING_UART1 bool "Enable UART1" default n - endif + endif endmenu endmenu diff --git a/bsp/nrf5x/nrf52840/rtconfig.h b/bsp/nrf5x/nrf52840/rtconfig.h index 1741c7dd7b..c63c401e68 100644 --- a/bsp/nrf5x/nrf52840/rtconfig.h +++ b/bsp/nrf5x/nrf52840/rtconfig.h @@ -155,10 +155,13 @@ /* Onboard Peripheral Drivers */ +#define BSP_USING_JLINK_TO_USART /* On-chip Peripheral Drivers */ #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_UART0_RX_PIN 8 +#define BSP_UART0_TX_PIN 6 #endif From 786eb5ae9c77970f25f662d57a83276d09c9a72d Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Thu, 30 Apr 2020 21:08:04 +0800 Subject: [PATCH 27/27] [C++] rename the Thread/Mutex to cxx_Thread/Mutex to avoid same name issue --- bsp/lpc54608-LPCXpresso/project.ewp | 8 +- bsp/lpc54608-LPCXpresso/project.ewt | 8 +- bsp/lpc54608-LPCXpresso/project.uvprojx | 1743 ++++++++--------- components/cplusplus/crt_init.c | 0 .../cplusplus/{Mutex.cpp => cxx_Mutex.cpp} | 0 .../{Semaphore.cpp => cxx_Semaphore.cpp} | 0 .../cplusplus/{Thread.cpp => cxx_Thread.cpp} | 0 components/cplusplus/{crt.cpp => cxx_crt.cpp} | 0 8 files changed, 876 insertions(+), 883 deletions(-) mode change 100755 => 100644 components/cplusplus/crt_init.c rename components/cplusplus/{Mutex.cpp => cxx_Mutex.cpp} (100%) rename components/cplusplus/{Semaphore.cpp => cxx_Semaphore.cpp} (100%) rename components/cplusplus/{Thread.cpp => cxx_Thread.cpp} (100%) rename components/cplusplus/{crt.cpp => cxx_crt.cpp} (100%) diff --git a/bsp/lpc54608-LPCXpresso/project.ewp b/bsp/lpc54608-LPCXpresso/project.ewp index 22154af07d..d16ead5d2c 100644 --- a/bsp/lpc54608-LPCXpresso/project.ewp +++ b/bsp/lpc54608-LPCXpresso/project.ewp @@ -2148,16 +2148,16 @@ CPlusPlus - $PROJ_DIR$\../../components/cplusplus/Mutex.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_Mutex.cpp - $PROJ_DIR$\../../components/cplusplus/Semaphore.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_Semaphore.cpp - $PROJ_DIR$\../../components/cplusplus/Thread.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_Thread.cpp - $PROJ_DIR$\../../components/cplusplus/crt.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_crt.cpp $PROJ_DIR$\../../components/cplusplus/crt_init.c diff --git a/bsp/lpc54608-LPCXpresso/project.ewt b/bsp/lpc54608-LPCXpresso/project.ewt index de78292e60..a1d63d5e4b 100644 --- a/bsp/lpc54608-LPCXpresso/project.ewt +++ b/bsp/lpc54608-LPCXpresso/project.ewt @@ -2355,19 +2355,19 @@ CPlusPlus - $PROJ_DIR$\..\..\components\cplusplus\crt.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_crt.cpp $PROJ_DIR$\..\..\components\cplusplus\crt_init.c - $PROJ_DIR$\..\..\components\cplusplus\Mutex.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_Mutex.cpp - $PROJ_DIR$\..\..\components\cplusplus\Semaphore.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_Semaphore.cpp - $PROJ_DIR$\..\..\components\cplusplus\Thread.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_Thread.cpp diff --git a/bsp/lpc54608-LPCXpresso/project.uvprojx b/bsp/lpc54608-LPCXpresso/project.uvprojx index ad2e225b2e..e7978224d2 100644 --- a/bsp/lpc54608-LPCXpresso/project.uvprojx +++ b/bsp/lpc54608-LPCXpresso/project.uvprojx @@ -330,9 +330,9 @@ 0 --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 - CPU_LPC54608J512ET180=1, CPU_LPC54608, CORE_M4, SDK_DEBUGCONSOLE=0, RT_USING_ARM_LIBC + SDK_DEBUGCONSOLE=0, CPU_LPC54608, CORE_M4, CPU_LPC54608J512ET180=1, RT_USING_ARM_LIBC - .;..\..\include;applications;.;drivers;SDK_2.2_LPCXpresso54608\CMSIS\Include;SDK_2.2_LPCXpresso54608\devices\LPC54608;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\cplusplus;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\netdev\include;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + .;../../include;applications;.;drivers;SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc;SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src;SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers;SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities;SDK_2.2_LPCXpresso54608/CMSIS/Include;SDK_2.2_LPCXpresso54608/devices/LPC54608;../../libcpu/arm/common;../../libcpu/arm/cortex-m4;../../components/finsh;../../components/dfs/include;../../components/dfs/filesystems/elmfat;../../components/dfs/filesystems/devfs;../../components/net/lwip-2.0.2/src;../../components/net/lwip-2.0.2/src/include;../../components/net/lwip-2.0.2/src/include/ipv4;../../components/net/lwip-2.0.2/src/arch/include;../../components/net/lwip-2.0.2/src/include/netif;../../components/net/netdev/include;../../components/net/sal_socket/include;../../components/net/sal_socket/include/socket;../../components/net/sal_socket/impl;../../components/net/sal_socket/include/dfs_net;../../components/net/sal_socket/include/dfs_net/sys_select;../../components/net/sal_socket/include/socket/sys_socket;../../components/drivers/include;../../components/drivers/include;../../components/drivers/spi;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/cplusplus;../../components/libc/compilers/armlibc;../../components/libc/compilers/common;../../components/libc/pthreads;../../components/libc/time @@ -379,112 +379,105 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c components.c 1 - ..\..\src\components.c - - - - - cpu.c - 1 - ..\..\src\cpu.c + ../../src/components.c device.c 1 - ..\..\src\device.c + ../../src/device.c idle.c 1 - ..\..\src\idle.c + ../../src/idle.c ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c irq.c 1 - ..\..\src\irq.c + ../../src/irq.c kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c mem.c 1 - ..\..\src\mem.c + ../../src/mem.c memheap.c 1 - ..\..\src\memheap.c + ../../src/memheap.c mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c object.c 1 - ..\..\src\object.c + ../../src/object.c scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c signal.c 1 - ..\..\src\signal.c + ../../src/signal.c thread.c 1 - ..\..\src\thread.c + ../../src/thread.c timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -494,21 +487,21 @@ application.c 1 - applications\application.c + applications/application.c mnt.c 1 - applications\mnt.c + applications/mnt.c startup.c 1 - applications\startup.c + applications/startup.c @@ -518,84 +511,395 @@ board.c 1 - drivers\board.c + drivers/board.c clock_config.c 1 - drivers\clock_config.c + drivers/clock_config.c drt_mpu.c 1 - drivers\drt_mpu.c + drivers/drt_mpu.c drv_emac.c 1 - drivers\drv_emac.c + drivers/drv_emac.c drv_ft5406.c 1 - drivers\drv_ft5406.c + drivers/drv_ft5406.c drv_i2c.c 1 - drivers\drv_i2c.c + drivers/drv_i2c.c drv_lcd.c 1 - drivers\drv_lcd.c + drivers/drv_lcd.c drv_sd.c 1 - drivers\drv_sd.c + drivers/drv_sd.c drv_sdram.c 1 - drivers\drv_sdram.c + drivers/drv_sdram.c drv_sram.c 1 - drivers\drv_sram.c + drivers/drv_sram.c drv_uart.c 1 - drivers\drv_uart.c + drivers/drv_uart.c fsl_phy.c 1 - drivers\fsl_phy.c + drivers/fsl_phy.c + + + + + Libraries + + + fsl_sd.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd.c + + + + + fsl_sdmmc.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdmmc.c + + + + + fsl_host.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_host.c + + + + + fsl_sd_event.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd_event.c + + + + + fsl_adc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.c + + + + + fsl_clock.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.c + + + + + fsl_common.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.c + + + + + fsl_crc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.c + + + + + fsl_ctimer.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.c + + + + + fsl_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.c + + + + + fsl_dmic.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.c + + + + + fsl_dmic_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.c + + + + + fsl_eeprom.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.c + + + + + fsl_emc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.c + + + + + fsl_enet.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.c + + + + + fsl_flashiap.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.c + + + + + fsl_flexcomm.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.c + + + + + fsl_fmc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.c + + + + + fsl_fmeas.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.c + + + + + fsl_gint.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.c + + + + + fsl_gpio.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.c + + + + + fsl_i2c.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.c + + + + + fsl_i2c_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.c + + + + + fsl_i2s.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.c + + + + + fsl_i2s_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.c + + + + + fsl_inputmux.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.c + + + + + fsl_lcdc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.c + + + + + fsl_mcan.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.c + + + + + fsl_mrt.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.c + + + + + fsl_pint.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.c + + + + + fsl_power.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.c + + + + + fsl_reset.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.c + + + + + fsl_rit.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.c + + + + + fsl_rtc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.c + + + + + fsl_sctimer.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.c + + + + + fsl_sdif.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.c + + + + + fsl_spi.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.c + + + + + fsl_spi_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.c + + + + + fsl_spifi.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.c + + + + + fsl_spifi_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.c + + + + + fsl_usart.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.c + + + + + fsl_usart_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.c + + + + + fsl_utick.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.c + + + + + fsl_wwdt.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.c @@ -605,332 +909,21 @@ startup_LPC54608.s 2 - SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\startup_LPC54608.s + SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/startup_LPC54608.s system_LPC54608.c 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\system_LPC54608.c + SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.c keil_lib_power.lib 4 - SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\keil_lib_power.lib - - - - - Libraries - - - fsl_adc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_adc.c - - - - - fsl_clock.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_clock.c - - - - - fsl_common.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_common.c - - - - - fsl_crc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_crc.c - - - - - fsl_ctimer.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_ctimer.c - - - - - fsl_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dma.c - - - - - fsl_dmic.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic.c - - - - - fsl_dmic_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic_dma.c - - - - - fsl_eeprom.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_eeprom.c - - - - - fsl_emc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_emc.c - - - - - fsl_enet.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_enet.c - - - - - fsl_flashiap.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flashiap.c - - - - - fsl_flexcomm.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flexcomm.c - - - - - fsl_fmc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmc.c - - - - - fsl_fmeas.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmeas.c - - - - - fsl_gint.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gint.c - - - - - fsl_gpio.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gpio.c - - - - - fsl_i2c.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c.c - - - - - fsl_i2c_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c_dma.c - - - - - fsl_i2s.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s.c - - - - - fsl_i2s_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s_dma.c - - - - - fsl_inputmux.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_inputmux.c - - - - - fsl_lcdc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_lcdc.c - - - - - fsl_mcan.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mcan.c - - - - - fsl_mrt.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mrt.c - - - - - fsl_pint.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_pint.c - - - - - fsl_power.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_power.c - - - - - fsl_reset.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_reset.c - - - - - fsl_rit.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rit.c - - - - - fsl_rtc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rtc.c - - - - - fsl_sctimer.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sctimer.c - - - - - fsl_sdif.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sdif.c - - - - - fsl_spi.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi.c - - - - - fsl_spi_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi_dma.c - - - - - fsl_spifi.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi.c - - - - - fsl_spifi_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi_dma.c - - - - - fsl_usart.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart.c - - - - - fsl_usart_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart_dma.c - - - - - fsl_utick.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_utick.c - - - - - fsl_wwdt.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_wwdt.c - - - - - fsl_sd.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd.c - - - - - fsl_sdmmc.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sdmmc.c - - - - - fsl_host.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_host.c - - - - - fsl_sd_event.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd_event.c + SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/keil_lib_power.lib @@ -940,73 +933,136 @@ backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c cpuport.c 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c + ../../libcpu/arm/cortex-m4/cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S + ../../libcpu/arm/cortex-m4/context_rvds.S - CPlusPlus + finsh - Mutex.cpp - 8 - ..\..\components\cplusplus\Mutex.cpp - - - - - Semaphore.cpp - 8 - ..\..\components\cplusplus\Semaphore.cpp - - - - - Thread.cpp - 8 - ..\..\components\cplusplus\Thread.cpp - - - - - crt.cpp - 8 - ..\..\components\cplusplus\crt.cpp - - - - - crt_init.c + shell.c 1 - ..\..\components\cplusplus\crt_init.c + ../../components/finsh/shell.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + msh.c + 1 + ../../components/finsh/msh.c + + + + + msh_file.c + 1 + ../../components/finsh/msh_file.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c @@ -1016,213 +1072,530 @@ dfs.c 1 - ..\..\components\dfs\src\dfs.c + ../../components/dfs/src/dfs.c dfs_file.c 1 - ..\..\components\dfs\src\dfs_file.c + ../../components/dfs/src/dfs_file.c dfs_fs.c 1 - ..\..\components\dfs\src\dfs_fs.c + ../../components/dfs/src/dfs_fs.c dfs_posix.c 1 - ..\..\components\dfs\src\dfs_posix.c + ../../components/dfs/src/dfs_posix.c poll.c 1 - ..\..\components\dfs\src\poll.c + ../../components/dfs/src/poll.c select.c 1 - ..\..\components\dfs\src\select.c - - - - - devfs.c - 1 - ..\..\components\dfs\filesystems\devfs\devfs.c + ../../components/dfs/src/select.c dfs_elm.c 1 - ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + ../../components/dfs/filesystems/elmfat/dfs_elm.c ff.c 1 - ..\..\components\dfs\filesystems\elmfat\ff.c + ../../components/dfs/filesystems/elmfat/ff.c + + + + + devfs.c + 1 + ../../components/dfs/filesystems/devfs/devfs.c + + + + + lwIP + + + sys_arch.c + 1 + ../../components/net/lwip-2.0.2/src/arch/sys_arch.c + + + + + api_lib.c + 1 + ../../components/net/lwip-2.0.2/src/api/api_lib.c + + + + + api_msg.c + 1 + ../../components/net/lwip-2.0.2/src/api/api_msg.c + + + + + err.c + 1 + ../../components/net/lwip-2.0.2/src/api/err.c + + + + + netbuf.c + 1 + ../../components/net/lwip-2.0.2/src/api/netbuf.c + + + + + netdb.c + 1 + ../../components/net/lwip-2.0.2/src/api/netdb.c + + + + + netifapi.c + 1 + ../../components/net/lwip-2.0.2/src/api/netifapi.c + + + + + sockets.c + 1 + ../../components/net/lwip-2.0.2/src/api/sockets.c + + + + + tcpip.c + 1 + ../../components/net/lwip-2.0.2/src/api/tcpip.c + + + + + def.c + 1 + ../../components/net/lwip-2.0.2/src/core/def.c + + + + + dns.c + 1 + ../../components/net/lwip-2.0.2/src/core/dns.c + + + + + inet_chksum.c + 1 + ../../components/net/lwip-2.0.2/src/core/inet_chksum.c + + + + + init.c + 1 + ../../components/net/lwip-2.0.2/src/core/init.c + + + + + ip.c + 1 + ../../components/net/lwip-2.0.2/src/core/ip.c + + + + + memp.c + 1 + ../../components/net/lwip-2.0.2/src/core/memp.c + + + + + netif.c + 1 + ../../components/net/lwip-2.0.2/src/core/netif.c + + + + + pbuf.c + 1 + ../../components/net/lwip-2.0.2/src/core/pbuf.c + + + + + raw.c + 1 + ../../components/net/lwip-2.0.2/src/core/raw.c + + + + + stats.c + 1 + ../../components/net/lwip-2.0.2/src/core/stats.c + + + + + sys.c + 1 + ../../components/net/lwip-2.0.2/src/core/sys.c + + + + + tcp.c + 1 + ../../components/net/lwip-2.0.2/src/core/tcp.c + + + + + tcp_in.c + 1 + ../../components/net/lwip-2.0.2/src/core/tcp_in.c + + + + + tcp_out.c + 1 + ../../components/net/lwip-2.0.2/src/core/tcp_out.c + + + + + timeouts.c + 1 + ../../components/net/lwip-2.0.2/src/core/timeouts.c + + + + + udp.c + 1 + ../../components/net/lwip-2.0.2/src/core/udp.c + + + + + ethernet.c + 1 + ../../components/net/lwip-2.0.2/src/netif/ethernet.c + + + + + ethernetif.c + 1 + ../../components/net/lwip-2.0.2/src/netif/ethernetif.c + + + + + lowpan6.c + 1 + ../../components/net/lwip-2.0.2/src/netif/lowpan6.c + + + + + autoip.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/autoip.c + + + + + dhcp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/dhcp.c + + + + + etharp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/etharp.c + + + + + icmp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/icmp.c + + + + + igmp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/igmp.c + + + + + ip4.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/ip4.c + + + + + ip4_addr.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_addr.c + + + + + ip4_frag.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_frag.c + + + + + ping.c + 1 + ../../components/net/lwip-2.0.2/src/apps/ping/ping.c + + + + + netdev + + + netdev.c + 1 + ../../components/net/netdev/src/netdev.c + + + + + netdev_ipaddr.c + 1 + ../../components/net/netdev/src/netdev_ipaddr.c + + + + + SAL + + + sal_socket.c + 1 + ../../components/net/sal_socket/src/sal_socket.c + + + + + net_netdb.c + 1 + ../../components/net/sal_socket/socket/net_netdb.c + + + + + af_inet_lwip.c + 1 + ../../components/net/sal_socket/impl/af_inet_lwip.c + + + + + net_sockets.c + 1 + ../../components/net/sal_socket/socket/net_sockets.c + + + + + dfs_net.c + 1 + ../../components/net/sal_socket/dfs_net/dfs_net.c DeviceDrivers - - - i2c_core.c - 1 - ..\..\components\drivers\i2c\i2c_core.c - - - - - i2c_dev.c - 1 - ..\..\components\drivers\i2c\i2c_dev.c - - - - - i2c-bit-ops.c - 1 - ..\..\components\drivers\i2c\i2c-bit-ops.c - - - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - - - - - mtd_nand.c - 1 - ..\..\components\drivers\mtd\mtd_nand.c - - - - - rtc.c - 1 - ..\..\components\drivers\rtc\rtc.c - - block_dev.c 1 - ..\..\components\drivers\sdio\block_dev.c + ../../components/drivers/sdio/block_dev.c mmcsd_core.c 1 - ..\..\components\drivers\sdio\mmcsd_core.c + ../../components/drivers/sdio/mmcsd_core.c sd.c 1 - ..\..\components\drivers\sdio\sd.c + ../../components/drivers/sdio/sd.c sdio.c 1 - ..\..\components\drivers\sdio\sdio.c + ../../components/drivers/sdio/sdio.c mmc.c 1 - ..\..\components\drivers\sdio\mmc.c + ../../components/drivers/sdio/mmc.c - serial.c + rtc.c 1 - ..\..\components\drivers\serial\serial.c + ../../components/drivers/rtc/rtc.c spi_core.c 1 - ..\..\components\drivers\spi\spi_core.c + ../../components/drivers/spi/spi_core.c spi_dev.c 1 - ..\..\components\drivers\spi\spi_dev.c + ../../components/drivers/spi/spi_dev.c + + + + + i2c_core.c + 1 + ../../components/drivers/i2c/i2c_core.c + + + + + i2c_dev.c + 1 + ../../components/drivers/i2c/i2c_dev.c + + + + + i2c-bit-ops.c + 1 + ../../components/drivers/i2c/i2c-bit-ops.c + + + + + serial.c + 1 + ../../components/drivers/serial/serial.c completion.c 1 - ..\..\components\drivers\src\completion.c + ../../components/drivers/src/completion.c dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ../../components/drivers/src/dataqueue.c pipe.c 1 - ..\..\components\drivers\src\pipe.c + ../../components/drivers/src/pipe.c ringblk_buf.c 1 - ..\..\components\drivers\src\ringblk_buf.c + ../../components/drivers/src/ringblk_buf.c ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ../../components/drivers/src/ringbuffer.c waitqueue.c 1 - ..\..\components\drivers\src\waitqueue.c + ../../components/drivers/src/waitqueue.c workqueue.c 1 - ..\..\components\drivers\src\workqueue.c + ../../components/drivers/src/workqueue.c + + + + + mtd_nand.c + 1 + ../../components/drivers/mtd/mtd_nand.c + + + + + pin.c + 1 + ../../components/drivers/misc/pin.c @@ -1239,103 +1612,40 @@ - finsh + CPlusPlus - shell.c - 1 - ..\..\components\finsh\shell.c + cxx_Mutex.cpp + 8 + ../../components/cplusplus/cxx_Mutex.cpp - cmd.c - 1 - ..\..\components\finsh\cmd.c + cxx_Semaphore.cpp + 8 + ../../components/cplusplus/cxx_Semaphore.cpp - msh.c - 1 - ..\..\components\finsh\msh.c + cxx_Thread.cpp + 8 + ../../components/cplusplus/cxx_Thread.cpp - msh_file.c - 1 - ..\..\components\finsh\msh_file.c + cxx_crt.cpp + 8 + ../../components/cplusplus/cxx_crt.cpp - finsh_compiler.c + crt_init.c 1 - ..\..\components\finsh\finsh_compiler.c - - - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - - - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c + ../../components/cplusplus/crt_init.c @@ -1345,35 +1655,35 @@ libc.c 1 - ..\..\components\libc\compilers\armlibc\libc.c + ../../components/libc/compilers/armlibc/libc.c mem_std.c 1 - ..\..\components\libc\compilers\armlibc\mem_std.c + ../../components/libc/compilers/armlibc/mem_std.c stdio.c 1 - ..\..\components\libc\compilers\armlibc\stdio.c + ../../components/libc/compilers/armlibc/stdio.c stubs.c 1 - ..\..\components\libc\compilers\armlibc\stubs.c + ../../components/libc/compilers/armlibc/stubs.c time.c 1 - ..\..\components\libc\compilers\common\time.c + ../../components/libc/compilers/common/time.c @@ -1383,408 +1693,91 @@ mqueue.c 1 - ..\..\components\libc\pthreads\mqueue.c + ../../components/libc/pthreads/mqueue.c pthread.c 1 - ..\..\components\libc\pthreads\pthread.c + ../../components/libc/pthreads/pthread.c pthread_attr.c 1 - ..\..\components\libc\pthreads\pthread_attr.c + ../../components/libc/pthreads/pthread_attr.c pthread_barrier.c 1 - ..\..\components\libc\pthreads\pthread_barrier.c + ../../components/libc/pthreads/pthread_barrier.c pthread_cond.c 1 - ..\..\components\libc\pthreads\pthread_cond.c + ../../components/libc/pthreads/pthread_cond.c pthread_mutex.c 1 - ..\..\components\libc\pthreads\pthread_mutex.c + ../../components/libc/pthreads/pthread_mutex.c pthread_rwlock.c 1 - ..\..\components\libc\pthreads\pthread_rwlock.c + ../../components/libc/pthreads/pthread_rwlock.c pthread_spin.c 1 - ..\..\components\libc\pthreads\pthread_spin.c + ../../components/libc/pthreads/pthread_spin.c pthread_tls.c 1 - ..\..\components\libc\pthreads\pthread_tls.c + ../../components/libc/pthreads/pthread_tls.c sched.c 1 - ..\..\components\libc\pthreads\sched.c + ../../components/libc/pthreads/sched.c semaphore.c 1 - ..\..\components\libc\pthreads\semaphore.c + ../../components/libc/pthreads/semaphore.c clock_time.c 1 - ..\..\components\libc\time\clock_time.c + ../../components/libc/time/clock_time.c posix_sleep.c 1 - ..\..\components\libc\time\posix_sleep.c - - - - - lwIP - - - sys_arch.c - 1 - ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - - - api_lib.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - - - - api_msg.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - - - - err.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\err.c - - - - - netbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - - - - netdb.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - - - - netifapi.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - - - - sockets.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - - - - tcpip.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - - - - def.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\def.c - - - - - dns.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\dns.c - - - - - inet_chksum.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - - - init.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\init.c - - - - - ip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ip.c - - - - - memp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\memp.c - - - - - netif.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\netif.c - - - - - pbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - - - autoip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - - - dhcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - - - etharp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - - - icmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - - - igmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - - - ip4.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - - - ip4_addr.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - - - ip4_frag.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - - - - - ping.c - 1 - ..\..\components\net\lwip-2.0.2\src\apps\ping\ping.c - - - - - netdev - - - netdev.c - 1 - ..\..\components\net\netdev\src\netdev.c - - - - - netdev_ipaddr.c - 1 - ..\..\components\net\netdev\src\netdev_ipaddr.c - - - - - SAL - - - sal_socket.c - 1 - ..\..\components\net\sal_socket\src\sal_socket.c - - - - - net_netdb.c - 1 - ..\..\components\net\sal_socket\socket\net_netdb.c - - - - - af_inet_lwip.c - 1 - ..\..\components\net\sal_socket\impl\af_inet_lwip.c - - - - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - - - - - dfs_net.c - 1 - ..\..\components\net\sal_socket\dfs_net\dfs_net.c + ../../components/libc/time/posix_sleep.c diff --git a/components/cplusplus/crt_init.c b/components/cplusplus/crt_init.c old mode 100755 new mode 100644 diff --git a/components/cplusplus/Mutex.cpp b/components/cplusplus/cxx_Mutex.cpp similarity index 100% rename from components/cplusplus/Mutex.cpp rename to components/cplusplus/cxx_Mutex.cpp diff --git a/components/cplusplus/Semaphore.cpp b/components/cplusplus/cxx_Semaphore.cpp similarity index 100% rename from components/cplusplus/Semaphore.cpp rename to components/cplusplus/cxx_Semaphore.cpp diff --git a/components/cplusplus/Thread.cpp b/components/cplusplus/cxx_Thread.cpp similarity index 100% rename from components/cplusplus/Thread.cpp rename to components/cplusplus/cxx_Thread.cpp diff --git a/components/cplusplus/crt.cpp b/components/cplusplus/cxx_crt.cpp similarity index 100% rename from components/cplusplus/crt.cpp rename to components/cplusplus/cxx_crt.cpp