Merge remote-tracking branch 'remotes/rtt_github/master'

2026-11-07 08:39:40 +08:00 · 2021-09-17 15:03:14 +08:00
commit 4b3df6010f
@@ -29,6 +29,7 @@ jobs:
      fail-fast: false
      matrix:
       legs:
+         - {RTT_BSP: "acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -134,6 +135,8 @@ jobs:
         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "raspberry-pi/raspi4-32", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tae32f5300", RTT_TOOL_CHAIN: "sourcery-arm"}
    steps:
      - uses: actions/checkout@v2
      - name: Set up Python
@@ -25,6 +25,7 @@ documentation/html
 tools/kconfig-frontends/kconfig-mconf
 packages
 dist
+dist_ide_project
 cconfig.h
 GPUCache

@@ -23,4 +23,3 @@ dir_path:
 - bsp/stm32/libraries/STM32MPxx_HAL
 - bsp/stm32/libraries/STM32WBxx_HAL
 - bsp/stm32/libraries/STM32H7xx_HAL
- bsp/hk32/libraries
@@ -10,6 +10,16 @@ The peripheral library or firmware library of the chip manufacturer is authorize

 ## BSP's License and Coyright:

+### acm32f0x0-nucleo
+
+License:  bsd-new
+
+Copyright: Copyright (c) 2021, AisinoChip
+
+Path:
+
+- bsp/acm32f0x0-nucleo/libraries
+
 ### apollo2

 License:  bsd-new
@@ -216,6 +226,28 @@ Path:
 - bsp/hc32f4a0/Libraries/CMSIS
 - bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver

+### hc32f460
+
+License: bsd-new
+
+Copyright: Copyright (c) 2020, Huada Semiconductor Co., Ltd.
+
+Path:
+
+- bsp/hc32f460/Libraries/CMSIS
+- bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver
+
+### hc32l196
+
+License: bsd-new
+
+Copyright: Copyright (c) 2020, Huada Semiconductor Co., Ltd.
+
+Path:
+
+- bsp/hc32l196/Libraries/CMSIS
+- bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver
+
 ### hk32

 License: free-unknown
@@ -697,6 +729,16 @@ Path:
 - bsp/swm320/libraries/CMSIS
 - bsp/swm320-lq100/Libraries/CMSIS/CoreSupport

+### tae32f5300
+
+License: BSD 3-Clause
+
+Copyright (c) 2020 Tai-Action.
+
+Path:
+
+- bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver
+
 ### tm4c

 License: unknown-license-reference(bsd-new)
@@ -748,3 +790,20 @@ Path:

 - bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver

+### n32
+
+License: 未注明
+
+Copyright: Copyright (c) 2019, Nations Technologies Inc.
+
+Path:
+
+- bsp/n32g452xx/n32g452xx-mini-system/board/msp
+
+License: bsd-new
+
+Copyright: Copyright (c) 2010-2015 ARM Limited
+
+Path:
+
+- bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS
@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries
@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_SERIES_ACM32F0
+    bool
+    select ARCH_ARM_CORTEX_M0
+    default y
+
+source "$BSP_DIR/drivers/Kconfig"
+
@@ -0,0 +1,58 @@
+# acm32f0x0板级支持包
+
+## 1. 简介
+
+ACM32F0x0芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
+
+|--------------------------|--------------------|
+|         硬件             |         描述       |
+| -------------------------|--------------------|
+|芯片型号                  | ACM32F0X0系列      |
+|CPU                       | ARM Cortex-M0      |
+|主频                      | 64MHz              |
+|片内SRAM                  | 32K                |
+|片内Flash                 | 128K               |
+|--------------------------|--------------------|
+
+具体型号及资源请参考上海航芯官方网站[ACM32F0](www.aisinochip.com/index.php/product/child1/id/217.html)。
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f0x0-nucleo`目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+也可以通过`scons --target=iar`或`scons --target=mdk5`生成IAR或是keil工程，再使用相应的工具进行编译。
+
+## 3. 烧写及执行
+
+开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| ------------- | ------------ | ------------------------------------- |
+| GPIO          |     支持     | PA0, PA1... PD15 ---> PIN: 0, 1...63  |
+| UART          |     支持     |              UART1/UART2              |
+| LED           |     支持     |              LED1                     |
+| WDT           |     支持     |              WDT/IWDT                 |
+| ADC           |     支持     |                                       |
+
+## 5. 联系人信息
+
+维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
+
+## 6. 参考
+
+* 板子[数据手册][2]
+* 芯片[数据手册][3]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: www.aisinochip.com/index.php/product/detail/id/32.html
+  [3]: www.aisinochip.com/index.php/product/detail/id/32.html
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
+
@@ -0,0 +1,52 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
+
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <drivers/pin.h>
+
+#define LED_PIN_NUM    1     /* PA1 */
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while(1)
+    {
+        rt_pin_write(LED_PIN_NUM, PIN_LOW);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+        rt_pin_write(LED_PIN_NUM, PIN_HIGH);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+    }
+}
+
@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
+
+
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-25     AisinoChip   first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "rtconfig.h"
+#include "board.h"
+#include <rtdevice.h>
+
+#define SOC_SRAM_END_ADDR   (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
+
+extern int  rt_application_init(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+    #pragma section="HEAP"
+#else
+    extern int __bss_end;
+#endif
+
+extern void rt_hw_uart_init(void);
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial EVB board.
+ */
+void rt_hw_board_init(void)
+{
+    /* system init, clock, NVIC */
+    System_Init();
+
+    /* Configure the SysTick */
+    SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_HEAP
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
+#endif
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-27     AisinoCip    add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtconfig.h>
+#include "ACM32Fxx_HAL.h"
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+  *
+  * STEP 1, define macro define related to the serial port opening based on the serial port number
+  *                 such as     #define BSP_USING_UATR1
+  *
+  * STEP 2, according to the corresponding pin of serial port, modify the related serial port information
+  *                 such as     #define UART1_TX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_RX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_TX_PIN        GPIO_PIN_X   ->   GPIO_PIN_9
+  *                             #define UART1_RX_PIN        GPIO_PIN_X   ->   GPIO_PIN_10
+  *
+  * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+  *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+  *
+  * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+  *                 such as     #define BSP_UART1_RX_USING_DMA
+  *
+  */
+
+#if defined(BSP_USING_UART1)
+    #define UART1_TX_PORT           GPIOA
+    #define UART1_RX_PORT           GPIOA
+    #define UART1_TX_PIN            GPIO_PIN_9
+    #define UART1_RX_PIN            GPIO_PIN_10
+
+    #if defined(BSP_UART1_RX_USING_DMA)
+        #define UART1_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART1_RX_DMA_RCC        BIT12
+        #define UART1_RX_DMA_IRQ        DMA_IRQn
+        #define UART1_RX_DMA_CHANNEL    0
+        #define UART1_RX_DMA_REQUEST    REQ6_UART1_RECV
+    #endif /* BSP_UART1_RX_USING_DMA */
+
+    #if defined(BSP_UART1_TX_USING_DMA)
+        #define UART1_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART1_TX_DMA_RCC        BIT12
+        #define UART1_TX_DMA_IRQ        DMA_IRQn
+        #define UART1_TX_DMA_CHANNEL    1
+        #define UART1_TX_DMA_REQUEST    REQ5_UART1_SEND
+    #endif /* BSP_UART1_TX_USING_DMA */
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+    #define UART2_TX_PORT           GPIOA
+    #define UART2_RX_PORT           GPIOA
+    #define UART2_TX_PIN            GPIO_PIN_2
+    #define UART2_RX_PIN            GPIO_PIN_3
+
+    #if defined(BSP_UART2_RX_USING_DMA)
+        #define UART2_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART2_RX_DMA_RCC        BIT12
+        #define UART2_RX_DMA_IRQ        DMA_IRQn
+        #define UART2_RX_DMA_CHANNEL    0
+        #define UART2_RX_DMA_REQUEST    REQ8_UART2_RECV
+    #endif /* BSP_UART2_RX_USING_DMA */
+
+    #if defined(BSP_UART2_TX_USING_DMA)
+        #define UART2_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART2_TX_DMA_RCC        BIT12
+        #define UART2_TX_DMA_IRQ        DMA_IRQn
+        #define UART2_TX_DMA_CHANNEL    1
+        #define UART2_TX_DMA_REQUEST    REQ7_UART2_SEND
+    #endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+    #define UART3_TX_PORT           GPIOB
+    #define UART3_RX_PORT           GPIOB
+    #define UART3_TX_PIN            GPIO_PIN_10
+    #define UART3_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART3_RX_USING_DMA)
+        #define UART3_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART3_RX_DMA_RCC        BIT12
+        #define UART3_RX_DMA_IRQ        DMA_IRQn
+        #define UART3_RX_DMA_CHANNEL    2
+        #define UART3_RX_DMA_REQUEST    REQ29_UART3_RECV
+    #endif /* BSP_UART3_RX_USING_DMA */
+
+    #if defined(BSP_UART3_TX_USING_DMA)
+        #define UART3_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART3_TX_DMA_RCC        BIT12
+        #define UART3_TX_DMA_IRQ        DMA_IRQn
+        #define UART3_TX_DMA_CHANNEL    3
+        #define UART3_TX_DMA_REQUEST    REQ27_UART3_SEND
+    #endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+/*-------------------------- UART CONFIG END --------------------------*/
+
+/* board configuration */
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   first implementation
+ */
+
+#include <board.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define     ADC_NAME        "adc"
+
+#if defined(BSP_USING_ADC)
+
+struct acm32_adc
+{
+    ADC_HandleTypeDef       handle;
+    struct rt_adc_device    acm32_adc_device;
+};
+
+static struct acm32_adc acm32_adc_obj = {0};
+
+static rt_err_t acm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    struct acm32_adc *adcObj = RT_NULL;
+
+    RT_ASSERT(device != RT_NULL);
+
+    adcObj = rt_container_of(device, struct acm32_adc, acm32_adc_device);
+
+    if (enabled)
+    {
+        /* channel enabled */
+        if (0 != (adcObj->handle.Init.ChannelEn & (1 << channel)))
+        {
+            return RT_EOK;
+        }
+
+        adcObj->handle.Instance = ADC;
+        adcObj->handle.Init.ClockDiv = ADC_CLOCK_DIV8;
+        adcObj->handle.Init.ConConvMode = ADC_CONCONVMODE_DISABLE;
+        adcObj->handle.Init.JChannelMode = ADC_JCHANNELMODE_DISABLE;
+        adcObj->handle.Init.DiffMode = ADC_DIFFMODE_DISABLE;
+        adcObj->handle.Init.DMAMode = ADC_DMAMODE_DISABLE;
+        adcObj->handle.Init.OverMode = ADC_OVERMODE_DISABLE;
+        adcObj->handle.Init.OverSampMode = ADC_OVERSAMPMODE_DISABLE;
+        adcObj->handle.Init.AnalogWDGEn = ADC_ANALOGWDGEN_DISABLE;
+        adcObj->handle.Init.ExTrigMode.ExTrigSel = ADC_SOFTWARE_START;
+        adcObj->handle.Init.ChannelEn |= 1 << channel;
+
+        HAL_ADC_Init(&adcObj->handle);
+
+        adcObj->handle.ChannelNum ++;
+    }
+    else
+    {
+        /* channel disabled */
+        if (0 == (adcObj->handle.Init.ChannelEn & (1 << channel)))
+        {
+            return RT_EOK;
+        }
+        adcObj->handle.Init.ChannelEn &= ~(1 << channel);
+        adcObj->handle.ChannelNum --;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t acm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    struct acm32_adc *adcObj = RT_NULL;
+    ADC_ChannelConfTypeDef channelConf = {0};
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+    if (channel > ADC_CHANNEL_15)
+    {
+        return -RT_ERROR;
+    }
+    *value = RT_UINT32_MAX;
+    adcObj = rt_container_of(device, struct acm32_adc, acm32_adc_device);
+
+    /* channel disabled */
+    if (0 == (adcObj->handle.Init.ChannelEn & (1 << channel)))
+    {
+        return -RT_ERROR;
+    }
+
+    channelConf.Channel = channel;
+    channelConf.RjMode = 0;
+    channelConf.Sq = ADC_SEQUENCE_SQ1;
+    channelConf.Smp = ADC_SMP_CLOCK_320;
+    HAL_ADC_ConfigChannel(&adcObj->handle, &channelConf);
+
+    if (HAL_OK != HAL_ADC_Polling(&adcObj->handle, (uint32_t *)value, 1, 100))
+    {
+        return -RT_ERROR;
+    }
+    *value &= ~(HAL_ADC_EOC_FLAG);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops acm_adc_ops =
+{
+    .enabled = acm32_adc_enabled,
+    .convert = acm32_get_adc_value,
+};
+
+static int acm32_adc_init(void)
+{
+    return rt_hw_adc_register(&acm32_adc_obj.acm32_adc_device,
+                              ADC_NAME,
+                              &acm_adc_ops,
+                              RT_NULL);
+}
+INIT_BOARD_EXPORT(acm32_adc_init);
+
+#endif /* BSP_USING_ADC */
+
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
@@ -0,0 +1,155 @@
+/*
+ * linker script for ACM32F030 with GNU ld
+ */
+
+/* describes the location and size of blocks of memory in the target. */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 128k /* 128KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 32k  /* 32KB sram */
+}
+/* Program Entry, set to mark it as "used" and avoid gc */
+ENTRY(Reset_Handler)
+_system_stack_size = 0x800;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > ROM = 8
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } > RAM
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(8);
+        _estack = .;
+    } > RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-26     AisinoChip   first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM1
+#ifndef TIM1_CONFIG
+#define TIM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .tim_irqn                = TIM1_BRK_UP_TRG_COM_IRQn,    \
+       .name                    = "timer1",     \
+    }
+#endif /* TIM1_CONFIG */
+#endif /* BSP_USING_TIM1 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM6
+#ifndef TIM6_CONFIG
+#define TIM6_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM6,         \
+       .tim_irqn                = TIM6_IRQn,    \
+       .name                    = "timer6",     \
+    }
+#endif /* TIM6_CONFIG */
+#endif /* BSP_USING_TIM6 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM14,         \
+       .tim_irqn                = TIM14_IRQn,    \
+       .name                    = "timer14",     \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM15,         \
+       .tim_irqn                = TIM15_IRQn,    \
+       .name                    = "timer15",     \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM16,         \
+       .tim_irqn                = TIM16_IRQn,    \
+       .name                    = "timer16",     \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM17,         \
+       .tim_irqn                = TIM17_IRQn,    \
+       .name                    = "timer17",     \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_SERIAL)
+
+#if defined(BSP_USING_UART1)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                          \
+        .irq_type = UART1_IRQn,                                     \
+        .enable_id = EN_UART1,                                      \
+        .tx_port  = UART1_TX_PORT,                                  \
+        .rx_port  = UART1_RX_PORT,                                  \
+        .tx_pin   = UART1_TX_PIN,                                   \
+        .rx_pin   = UART1_RX_PIN,                                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+        .channel  = UART2_RX_DMA_CHANNEL,                           \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+        .channel  = UART2_TX_DMA_CHANNEL,                           \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                          \
+        .irq_type = UART2_IRQn,                                     \
+        .enable_id = EN_UART2,                                      \
+        .tx_port  = UART2_TX_PORT,                                  \
+        .rx_port  = UART2_RX_PORT,                                  \
+        .tx_pin   = UART2_TX_PIN,                                   \
+        .rx_pin   = UART2_RX_PIN,                                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+        .channel  = UART3_RX_DMA_CHANNEL,                           \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+        .channel  = UART3_TX_DMA_CHANNEL,                           \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                          \
+        .irq_type = UART3_IRQn,                                     \
+        .enable_id = EN_UART3,                                      \
+        .tx_port  = UART3_TX_PORT,                                  \
+        .rx_port  = UART3_RX_PORT,                                  \
+        .tx_pin   = UART3_TX_PIN,                                   \
+        .rx_pin   = UART3_RX_PIN,                                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_SERIAL */
+
+#endif /* __UART_CONFIG_H__ */
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
@@ -0,0 +1,170 @@
+/*
+  ******************************************************************************
+  * @file    ACM32Fxx_HAL.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   HAL Config header file.
+  ******************************************************************************
+*/
+#ifndef __ACM32FXX_HAL_H__
+#define __ACM32FXX_HAL_H__
+#ifdef __GNUC__
+#define  __weak __attribute__((weak))
+#endif
+/*
+    Uncomment the line below according to the target device used in your application
+*/
+   #define ACM32F0X0       /*!< ACM32F0x0xx */
+/* #define ACM32FP0X */    /*!< ACM32FP0xxx */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(ACM32F0X0)
+    #include "ACM32F0x0.h"
+#elif defined(ACM32FP0X)
+    #include "ACM32FP0X.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+/**
+  * @}
+  */
+
+
+/*
+ * @brief  HAL Status structures definition
+ */
+typedef enum
+{
+    HAL_OK       = 0x00U,
+    HAL_ERROR    = 0x01U,
+    HAL_BUSY     = 0x02U,
+    HAL_TIMEOUT  = 0x03U
+}HAL_StatusTypeDef;
+
+/* USE FULL ASSERT */
+#define USE_FULL_ASSERT    (1)
+
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDT_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_EFLASH_MODULE_ENABLED
+#define HAL_OPA_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_LPUART_MODULE_ENABLED
+#define HAL_WDT_MODULE_ENABLED
+#define HAL_FSUSB_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+//#define HAL_SYSTICK_ENABLED
+#define HAL_CRC_ENABLED
+#define HAL_TKEY_MODULE_ENABLED
+#define HAL_AES_ENABLED
+#define HAL_HRNG_ENABLED
+#define HAL_DIV_ENABLED
+
+#include "System_ACM32F0x0.h"
+
+#ifdef HAL_DMA_MODULE_ENABLED
+    #include "HAL_DMA.h"
+#endif
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+    #include "HAL_GPIO.h"
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+    #include "HAL_UART.h"
+    #include "HAL_UART_EX.h"
+#endif
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    #include "HAL_ADC.h"
+#endif
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+    #include "HAL_EXTI.h"
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+    #include "HAL_I2C.h"
+#endif
+
+
+#ifdef HAL_RTC_MODULE_ENABLED
+    #include "HAL_RTC.h"
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+    #include "HAL_SPI.h"
+#endif
+
+#ifdef HAL_IWDT_MODULE_ENABLED
+    #include "HAL_IWDT.h"
+#endif
+
+#ifdef HAL_EFLASH_MODULE_ENABLED
+    #include "HAL_EFLASH.h"
+    #include "HAL_EFlash_EX.h"
+#endif
+
+#ifdef HAL_OPA_MODULE_ENABLED
+    #include "HAL_OPA.h"
+#endif
+
+#ifdef HAL_COMP_MODULE_ENABLED
+    #include "HAL_COMP.h"
+#endif
+
+#ifdef HAL_CAN_MODULE_ENABLED
+    #include "HAL_CAN.h"
+#endif
+
+#ifdef HAL_LPUART_MODULE_ENABLED
+    #include "HAL_LPUART.h"
+#endif
+
+#ifdef HAL_WDT_MODULE_ENABLED
+    #include "HAL_WDT.h"
+#endif
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+    #include "HAL_TIMER.h"
+    #include "HAL_TIMER_EX.h"
+#endif
+#ifdef HAL_LCD_MODULE_ENABLED
+    #include "HAL_LCD.h"
+#endif
+
+
+#ifdef HAL_TKEY_MODULE_ENABLED
+    #include "HAL_TKEY.h"
+#endif
+#ifdef HAL_CRC_ENABLED
+#include  "HAL_CRC.h"
+#endif
+
+#ifdef  HAL_AES_ENABLED
+#include  "HAL_AES.h"
+#endif
+
+#ifdef HAL_HRNG_ENABLED
+#include "HAL_HRNG.h"
+#endif
+
+#ifdef HAL_DIV_ENABLED
+#include "HAL_DIV.h"
+#endif
+
+
+#endif
@@ -0,0 +1,83 @@
+/***********************************************************************
+ * Copyright (c)  2008 - 2016, Shanghai AisinoChip Co.,Ltd .
+ * All rights reserved.
+ * Filename    : aes.h
+ * Description : aes driver header file
+ * Author(s)   : Eric
+ * version     : V1.0
+ * Modify date : 2016-03-24
+ ***********************************************************************/
+#ifndef __AES_H__
+#define __AES_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define AES_ENCRYPTION          1
+#define AES_DECRYPTION          0
+#define AES_ECB_MODE            0
+#define AES_CBC_MODE            1
+#define AES_SWAP_ENABLE         1
+#define AES_SWAP_DISABLE        0
+
+#define AES_NORMAL_MODE     0x12345678
+#define AES_SECURITY_MODE   0
+
+#define AES_KEY_128     0
+#define AES_KEY_192     1
+#define AES_KEY_256     2
+
+#define AES_FAIL   0x00
+#define AES_PASS   0xa59ada68
+
+/******************************************************************************
+Name:      HAL_AES_Set_Key
+Function:  set aes key for encryption and decryption
+Input:
+           keyin     --    pointer to buffer of key
+           swap_en   --    AES_SWAP_ENABLE, AES_SWAP_DISABLE
+Return:    None
+*******************************************************************************/
+void HAL_AES_Set_Key(UINT32 *keyin, UINT8 key_len, UINT8 swap_en);
+void HAL_AES_Set_Key_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en);
+
+
+/******************************************************************************
+
+Name:        HAL_Aes_Crypt
+Function:    Function for des encryption and decryption
+Input:
+             indata            --  pointer to buffer of input
+             outdata           --  pointer to buffer of result
+             block_len         --  block(128bit) length for des cryption
+             operation         --  AES_ENCRYPTION,AES_DECRYPTION
+             mode              --  AES_ECB_MODE, AES_CBC_MODE,
+             iv                --  initial vector for CBC mode
+             security_mode     --  AES_NORMAL_MODE, AES_SECURITY_MDOE，
+Return:      None
+
+*******************************************************************************/
+UINT32 HAL_AES_Crypt(
+    UINT32 *indata,
+    UINT32 *outdata,
+    UINT32 block_len,
+    UINT8  operation,
+    UINT8  mode,
+    UINT32 *iv,
+    UINT32 security_mode
+);
+
+
+UINT32 HAL_AES_Crypt_U8(
+    UINT8 *indata,
+    UINT8 *outdata,
+    UINT32 block_len,
+    UINT8  operation,
+    UINT8  mode,
+    UINT8 *iv,
+    UINT32 security_mode
+);
+
+#endif
+/******************************************************************************
+ * end of file
+*******************************************************************************/
@@ -0,0 +1,154 @@
+/*
+  ******************************************************************************
+  * @file    HAL_CRC.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CRC_H__
+#define __HAL_CRC_H__
+#include  "ACM32Fxx_HAL.h"
+
+/** @defgroup CRC POLY Reverse
+  * @{
+  */
+ #define CRC_POLY_REV_EN                    (0x00000400U)    /*!< Poly Reverse Enable */
+ #define CRC_POLY_REV_DIS                   (0x00000000U)    /*!< Poly Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC OUTXOR Reverse
+  * @{
+  */
+ #define CRC_OUTXOR_REV_EN                   (0x00000200U)    /*!< OUTXOR Reverse Enable */
+ #define CRC_OUTXOR_REV_DIS                  (0x00000000U)    /*!< OUTXOR Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC INIT Reverse
+  * @{
+  */
+ #define CRC_INIT_REV_EN                     (0x00000100U)    /*!< INIT Reverse Enable */
+ #define CRC_INIT_REV_DIS                    (0x00000000U)    /*!< INIT Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC RSLT Reverse
+  * @{
+  */
+ #define CRC_RSLT_REV_EN                     (0x00000080U)    /*!< RSLT Reverse Enable */
+ #define CRC_RSLT_REV_DIS                    (0x00000000U)    /*!< RSLT Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC DATA Reverse
+  * @{
+  */
+ #define CRC_DATA_REV_DISABLE                (0x00000000U)    /*!< DATA Reverse Disable */
+ #define CRC_DATA_REV_BY_BYTE                (0x00000020U)    /*!< DATA Reverse By Byte */
+ #define CRC_DATA_REV_BY_HALFWORD            (0x00000040U)    /*!< DATA Reverse By HalfWord */
+ #define CRC_DATA_REV_BY_WORD                (0x00000060U)    /*!< DATA Reverse By Word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Poly Len
+  * @{
+  */
+ #define CRC_POLTY_LEN_32                    (0x00000000U)    /*!< POLY len = 32bit */
+ #define CRC_POLTY_LEN_16                    (0x00000008U)    /*!< POLY len = 16bit */
+ #define CRC_POLTY_LEN_8                     (0x00000010U)    /*!< POLY len = 8bit  */
+ #define CRC_POLTY_LEN_7                     (0x00000018U)    /*!< POLY len = 7bit  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Data Len
+  * @{
+  */
+ #define CRC_DATA_LEN_1B                    (0x00000000U)    /*!< DATA len = 1 Byte */
+ #define CRC_DATA_LEN_2B                    (0x00000002U)    /*!< DATA len = 2 Byte */
+ #define CRC_DATA_LEN_3B                    (0x00000004U)    /*!< DATA len = 3 Byte */
+ #define CRC_DATA_LEN_4B                    (0x00000006U)    /*!< DATA len = 4 Byte */
+/**
+  * @}
+  */
+
+/** @defgroup CRC RST
+  * @{
+  */
+ #define CRC_RST_EN                          (0x00000001U)    /*!< RST CRC_DATA To CRC_INIT */
+ #define CRC_RST_DIS                         (0x00000000U)    /*!< RST CRC_DATA To CRC_INIT */
+
+/**
+  * @}
+  */
+
+/*
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+    uint32_t PolyRev;                  /*!< Specifies if the Poly is reversed in CRC
+                                            This parameter can be a value of @ref CRC POLY Reverse. */
+    uint32_t OutxorRev;                /*!< Specifies if the Outxor is reversed in CRC
+                                            This parameter can be a value of @ref CRC OUTXOR Reverse. */
+    uint32_t InitRev;                  /*!< Specifies if the Init is reversed in CRC
+                                            This parameter can be a value of @ref CRC INIT Reverse. */
+    uint32_t RsltRev;                  /*!< Specifies if the Result is reversed in CRC
+                                            This parameter can be a value of @ref CRC RSLT Reverse. */
+    uint32_t DataRev;                  /*!< Specifies if the Data is reversed in CRC
+                                            This parameter can be a value of @ref CRC DATA Reverse. */
+    uint32_t PolyLen;                  /*!< Specifies the Poly Len in CRC
+                                            This parameter can be a value of @ref CRC Poly Len. */
+    uint32_t DataLen;                  /*!< Specifies the Data Len in CRC
+                                            This parameter can be a value of @ref CRC Data Len. */
+    uint32_t RST;                      /*!< Specifies if CRC is reset
+                                            This parameter can be a value of @ref CRC RST. */
+
+    uint32_t InitData;                 /*!< This member configures the InitData. */
+
+    uint32_t OutXorData;               /*!< This member configures the OutXorData. */
+
+    uint32_t PolyData;                 /*!< This member configures the PolyData. */
+
+    uint32_t FData;                    /*!< This member configures the FData. */
+
+}CRC_InitTypeDef;
+
+/*
+ * @brief  UART handle Structure definition
+ */
+typedef struct
+{
+    CRC_TypeDef           *Instance;                /*!< CRC registers base address  */
+
+    CRC_InitTypeDef        Init;                    /*!< CRC calculate parameters  */
+
+    uint8_t* CRC_Data_Buff;                         /*!< CRC databuff base address */
+
+    uint32_t CRC_Data_Len;                          /*!< amount of CRC data to be calculated */
+
+}CRC_HandleTypeDef;
+
+
+/*********************************************************************************
+* Function    : HAL_CRC_Calculate
+* Description : Calculate the crc calue of input data.
+* Input       : hcrc: CRC handle.
+* Output      : CRC value
+* Author      : cl                        Data : 2021
+**********************************************************************************/
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc);
+
+
+#endif
+
+
+
+
@@ -0,0 +1,24 @@
+#ifndef _HAL_DIV_H_
+#define _HAL_DIV_H_
+
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************
+* function   : hardwareNN_Div_q32
+* Description: Computes q = b div c and a = b mod c.
+               cDigits must be 1, and *c < 0xffffffff
+* input :      UINT32 *b -- input b databuffer
+               UINT32 *c -- input c databuffer
+* output:      UINT32 *q -- quotient of result
+               UINT32 *a -- remainder of result
+
+* return:      none
+************************************************************************/
+void HAL_DIV_Q32(UINT32 *q,UINT32 *a,UINT32 *b,UINT32 bDigits,UINT32 *c,UINT32 cDigits);
+
+
+
+#endif
+
+
+
@@ -0,0 +1,41 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EFlash HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_H__
+#define __HAL_EFlash_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define EFLASH_PAGE_SIZE    (512UL)
+
+#define HAL_EFLASH_READ_WORD(Addr)        (*(volatile uint32_t *)(Addr))    // Read By Word
+#define HAL_EFLASH_READ_HALFWORD(Addr)    (*(volatile uint16_t *)(Addr))    // Read By Half Word
+#define HAL_EFLASH_READ_BYTE(Addr)        (*(volatile uint8_t *)(Addr))     // Read By Byte
+
+/********************  Bit definition for EFC_CTRL register  ******************/
+#define EFC_CTRL_CHIP_ERASE_MODE        (1 << 2)
+#define EFC_CTRL_PAGE_ERASE_MODE        (1 << 1)
+#define EFC_CTRL_PROGRAM_MODE           (1 << 0)
+
+#define EFLASH_RD_WAIT_POS   7
+/********************  Bit definition for EFC_STATUS register  ***************/
+#define EFC_STATUS_EFLASH_RDY           (1 << 0)
+
+#define SET_EFC_RD_WAIT(wait)     {EFC->CTRL   = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);}
+
+/* Exported functions --------------------------------------------------------*/
+
+/* HAL_EFlash_Init */
+void HAL_EFlash_Init(uint32_t fu32_freq);
+/* HAL_EFlash_ErasePage */
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word */
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif
@@ -0,0 +1,26 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash_EX.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of EFlash extention module
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_EX_H__
+#define __HAL_EFlash_EX_H__
+
+#include "stdint.h"
+
+/* HAL_EFlash_Return_To_Boot */
+void HAL_EFlash_Return_to_Boot(void);
+
+/* HAL_EFlash_Init_Para */
+void HAL_EFlash_Init_Para(uint32_t fu32_freq);
+
+/* HAL_EFlash_ErasePage_EX */
+void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word_EX */
+void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif
@@ -0,0 +1,166 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EXTI.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EXTI_H__
+#define __HAL_EXTI_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                (0x000001)
+#define EXTI_LINE_1                (0x000002)
+#define EXTI_LINE_2                (0x000004)
+#define EXTI_LINE_3                (0x000008)
+#define EXTI_LINE_4                (0x000010)
+#define EXTI_LINE_5                (0x000020)
+#define EXTI_LINE_6                (0x000040)
+#define EXTI_LINE_7                (0x000080)
+#define EXTI_LINE_8                (0x000100)
+#define EXTI_LINE_9                (0x000200)
+#define EXTI_LINE_10               (0x000300)
+#define EXTI_LINE_11               (0x000400)
+#define EXTI_LINE_12               (0x001000)
+#define EXTI_LINE_13               (0x002000)
+#define EXTI_LINE_14               (0x004000)
+#define EXTI_LINE_15               (0x008000)
+#define EXTI_LINE_16               (0x010000)
+#define EXTI_LINE_17               (0x020000)
+#define EXTI_LINE_18               (0x040000)
+#define EXTI_LINE_19               (0x080000)
+#define EXTI_LINE_20               (0x100000)
+#define EXTI_LINE_21               (0x200000)
+#define EXTI_LINE_22               (0x400000)
+#define EXTI_LINE_23               (0x800000)
+#define EXTI_LINE_MASK             (0xFFFFFFU)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_INTERRUPT         (0x00000001)
+#define EXTI_MODE_EVENT             (0x00000002)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_RISING                 (0x00000001)
+#define EXTI_TRIGGER_FALLING                (0x00000002)
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#define EXTI_GPIOD                          0x00000003u
+#define EXTI_GPIOE                          0x00000004u
+#define EXTI_GPIOF                          0x00000005u
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+    uint32_t u32_Line;        /*!< The Exti line to be configured. This parameter
+                                   can be a value of @ref EXTI_Line */
+    uint32_t u32_Mode;        /*!< The Exit Mode to be configured for a core.
+                                   This parameter can be a combination of @ref EXTI_Mode */
+    uint32_t u32_Trigger;     /*!< The Exti Trigger to be configured. This parameter
+                                   can be a value of @ref EXTI_Trigger */
+    uint32_t u32_GPIOSel;     /*!< The Exti GPIO multiplexer selection to be configured.
+                                   This parameter is only possible for line 0 to 15. It
+                                   can be a value of @ref EXTI_GPIOSel */
+}EXTI_HandleTypeDef;
+
+
+/** @defgroup  EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_ALL_LINE(LINE)    ( (LINE) | (EXTI_LINE_MASK) )
+
+#define IS_EXTI_MODE(__MODE__)     (((__MODE__) == EXTI_MODE_INTERRUPT) || \
+                                    ((__MODE__) == EXTI_MODE_EVENT))
+
+#define IS_EXTI_TRIGGER(__TRIGGER__)     (((__TRIGGER__) == EXTI_TRIGGER_RISING)  || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_GPIOSEL(__GPIOSEL__)     (((__GPIOSEL__) == EXTI_GPIOA) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOB) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOC) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOD) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOE) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOF))
+/**
+  * @}
+  */
+
+/** @brief  __HAL_EXTI_LINE_IT_ENABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__)    (EXTI->IENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_IT_DISABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__)    (EXTI->IENR &= ~(__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_ENABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__)    (EXTI->EENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_DISABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__)    (EXTI->EENR &= ~(__LINE__))
+
+
+/* HAL_EXTI_IRQHandler */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart);
+
+/* HAL_EXTI_SetConfigLine */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_SoftTrigger */
+void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_GetPending */
+bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_ClearPending */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_ClearAllPending */
+void HAL_EXTI_ClearAllPending(void);
+
+#endif
+
@@ -0,0 +1,45 @@
+/***********************************************************************
+ * Copyright (c)  2008 - 2016, Shanghai AisinoChip Co.,Ltd .
+ * All rights reserved.
+ * Filename    : HAL_HRNG.h
+ * Description : hrng header file
+ * Author(s)   : Eric
+ * version     : V1.0
+ * Modify date : 2021-03-24
+ ***********************************************************************/
+#ifndef __HAL_HRNG_H__
+#define __HAL_HRNG_H__
+#include "ACM32Fxx_HAL.h"
+
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_Initial
+* Description    : intial hrng module
+* Input          : None
+* Output         : None
+* Return         : None
+*********************************************************************************/
+void HAL_HRNG_Initial(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_Source_Disable
+* Description    : disable hrng source
+* Input          : None
+* Output         : None
+* Return         : None
+*********************************************************************************/
+void HAL_HRNG_Source_Disable(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng
+* Description    : get random number
+* Input          : byte_len :  the byte length of random number
+* Output         : *hdata   :  the start address of random number the size must be 16bytes
+* Return         : 0: hrng data is ok; 1: hrng data is bad
+*********************************************************************************/
+UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len);
+
+#endif
+
+
+
@@ -0,0 +1,57 @@
+
+/***********************************************************************
+ * Filename    : HAL_IWDT.h
+ * Description : IHAL WDT driver header file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17
+ ***********************************************************************/
+
+#ifndef __HAL_IWDT_H__
+#define __HAL_IWDT_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+/****************  Bit definition for IWDT register  ***********************/
+
+
+/*----------------------macro definition------------------------*/
+#define IWDT_ENABLE_COMMAND  (0xCCCCU)
+#define IWDT_DISABLE_COMMAND (0xEF01ABCD)
+#define IWDT_WRITE_ENABLE_COMMAND  (0x5555U)
+#define IWDT_WAKEUP_ENABLE_COMMAND  (0x6666U)
+#define IWDT_WAKEUP_DISABLE_COMMAND  (0x9999U)
+#define IWDT_RELOAD_COMMAND  (0xAAAAU)
+
+#define IWDT_RELOAD_MAX_VALUE  (0x0FFFU)
+
+/*----------------------type definition------------------------*/
+typedef enum _IWDT_CLOCK_PRESCALER{
+    IWDT_CLOCK_PRESCALER_4   = 0,
+    IWDT_CLOCK_PRESCALER_8   = 1,
+    IWDT_CLOCK_PRESCALER_16  = 2,
+    IWDT_CLOCK_PRESCALER_32  = 3,
+    IWDT_CLOCK_PRESCALER_64  = 4,
+    IWDT_CLOCK_PRESCALER_128 = 5,
+    IWDT_CLOCK_PRESCALER_256 = 6,
+}IWDT_CLOCK_PRESCALER;
+
+typedef struct
+{
+    uint32_t Prescaler;
+    uint32_t Reload;
+    uint32_t Window;
+    uint32_t Wakeup;
+} IWDT_InitTypeDef;
+
+typedef struct
+{
+    IWDT_TypeDef                 *Instance;  /*!< Register base address    */
+    IWDT_InitTypeDef             Init;       /*!< IWDT required parameters */
+} IWDT_HandleTypeDef;
+
+
+ HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt);
+ HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt);
+#endif
@@ -0,0 +1,173 @@
+/*
+  ******************************************************************************
+  * @file    HAL_LPUART.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_LPUART_H__
+#define __HAL_LPUART_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+#define IS_LPUART_INSTANCE(INSTANCE)          ((INSTANCE) == LPUART)
+
+#define LPUART_PEN_INDEX  0
+#define LPUART_SPS_INDEX  1
+#define LPUART_EPS_INDEX  2
+
+#define LPUART_IE_RX_INDEX         0  //has wakeup function
+#define LPUART_IE_TX_FINISH_INDEX  1
+#define LPUART_IE_TX_EMPTY_INDEX   2
+
+#define LPUART_SR_RX_INDEX         0
+#define LPUART_SR_TX_FINISH_INDEX  1
+#define LPUART_SR_TX_EMPTY_INDEX   2
+#define LPUART_SR_RX_FULL_INDEX    6
+#define LPUART_SR_MATCH_INDEX      8  //has wakeup function
+#define LPUART_SR_START_INDEX      9  //has wakeup function
+#define LPUART_SR_BITS_ALL         0x1FFU
+
+#define LPUART_WAKEUP_RX_BIT       BIT0
+#define LPUART_WAKEUP_MATCH_BIT    BIT8
+#define LPUART_WAKEUP_START_BIT    BIT9
+
+#define LPUART_CR_RXE_INDEX  0
+#define LPUART_CR_TXE_INDEX  1
+#define LPUART_CR_DMA_EN_INDEX  2
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+typedef enum
+{
+    LPUART_RXWKS_START = 0x00,
+    LPUART_RXWKS_OneByte = 0x01,
+    LPUART_RXWKS_DataCompare = 0x02,
+    LPUART_RXWKS_NoWake = 0x03,
+} LPUART_RXWKS;
+
+typedef enum
+{
+    LPUART_WKCK_Check = 0x00,
+    LPUART_WKCK_NoCheck = 0x01,
+} LPUART_WKCK ;
+
+/**
+  * @}
+  */
+
+
+
+/*
+ * @brief  LPUART DATABITS  definition
+ */
+typedef enum
+{
+    LPUART_DATABITS_8 = 0x00,
+    LPUART_DATABITS_7 = 0x01,
+} LPUART_DATABITS;
+
+/*
+ * @brief  LPUART STOPBITS  definition
+ */
+typedef enum
+{
+    LPUART_STOPBITS_ONE = 0x00U,
+    LPUART_STOPBITS_TWO = 0x01U,
+}LPUART_STOPBITS;
+
+/*
+ * @brief  LPUART CLOCK_SOURCE  definition
+ */
+typedef enum
+{
+    LPUART_CLOCK_SOURCE_RC32K = 0x00U,
+    LPUART_CLOCK_SOURCE_XTAL = 0x01U,
+    LPUART_CLOCK_SOURCE_PLL_DIV = 0x02U,
+}LPUART_CLOCK_SOURCE;
+
+/*
+ * @brief  LPUART PARITY  definition
+ */
+typedef enum
+{
+    LPUART_PARITY_NONE = 0x00U,
+    LPUART_PARITY_SELECT_ODD = 0x01U,
+    LPUART_PARITY_SELECT_EVEN = 0x02U,
+    LPUART_PARITY_SELECT_ONE = 0x03U,
+    LPUART_PARITY_SELECT_ZERO = 0x04U,
+}LPUART_PARITY_SELECT;
+
+/**
+  * @brief  LPUART  Config structure definition
+  */
+typedef struct
+{
+    uint8_t  WordLength;  // LPUART_DATABITS
+    uint8_t  StopBits;    // LPUART_STOPBITS
+    uint8_t  Parity;     // LPUART_PARITY_SELECT
+    uint8_t  ClockSrc;   // LPUART_CLOCK_SOURCE
+    uint32_t BaudRate;
+}LPUART_ConfigParam;
+
+/**
+  * @brief  LPUART  Config structure definition
+  */
+typedef struct
+{
+    uint8_t  Wakeup_Source;  // Wakeup_Source
+    uint8_t  Wakeup_Check;  // Wakeup_Check
+    uint8_t  Wakeup_Addr;  // Wakeup_Addr
+
+}LPUART_StopWakeupDef;
+
+
+
+/**
+  * @brief  LPUART  init structure definition
+  */
+typedef struct
+{
+    LPUART_TypeDef *Instance;
+    LPUART_ConfigParam ConfigParam;
+    LPUART_StopWakeupDef StopWakeup;
+    volatile uint8_t *rx_buffer;
+    volatile uint16_t rx_buffer_size;
+    volatile uint16_t rx_write_index;
+    volatile uint16_t rx_read_index;
+    volatile uint16_t tx_busy;
+    DMA_HandleTypeDef *dma_rx_handler;
+    DMA_HandleTypeDef *dma_tx_handler;
+}LPUART_HandleTypeDef;
+
+/* HAL_LPUART_Init */
+HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart);
+
+HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart);
+
+void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart);
+
+void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart);
+
+/* HAL_LPUART_Send_Bytes */
+void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);
+
+/* HAL_LPUART_IRQHander */
+void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart);
+
+/* HAL_LPUART_Receive_Bytes_Timeout */
+uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms);
+
+/* HAL_LPUART_Receive_Bytes */
+uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length);
+
+/* HAL_LPUART_DMA_Send_Bytes */
+void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);
+
+/* HAL_LPUART_Clear_Wakeup_Flags */
+void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits);
+
+#endif
@@ -0,0 +1,116 @@
+/*
+  ******************************************************************************
+  * @file    HAL_OPA.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of OPA HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_OPA_H__
+#define __HAL_OPA_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup OPAx Index
+  * @{
+  */
+#define OPA1        (0x01)
+#define OPA2        (0x02)
+#define OPA3        (0x03)
+
+/****************  Bit definition for OPA_CR1 and OPA_CR2 register  **************************/
+#define OPA_CSR_VINPSEL_POS                    (20U)
+#define OPA_CSR_VINPSEL_MASK                   (BIT23|BIT22|BIT21|BIT20)
+#define OPA_CSR_VINMSEL_POS                    (16U)
+#define OPA_CSR_VINMSEL_MASK                   (BIT19|BIT18|BIT17|BIT16)
+#define OPA_CSR_TRIM_HIGH_POS                  (9U)
+#define OPA_CSR_TRIM_HIGH_MASK                 (BIT13|BIT12|BIT11|BIT10|BIT9)
+#define OPA_CSR_TRIM_LOW_POS                   (4U)
+#define OPA_CSR_TRIM_LOW_MASK                  (BIT8|BIT7|BIT6|BIT5|BIT4)
+#define OPA_CSR_CAL_OUT                        (BIT3)
+#define OPA_CSR_CAL_H                          (BIT2)
+#define OPA_CSR_CAL_L                          (BIT1)
+#define OPA_CSR_EN                             (BIT0)
+
+/**
+  * @brief  OPA Configuration Structure definition
+  */
+typedef struct
+{
+    uint8_t            OpaX;        /*!< Specify witch opa be selected */
+    uint8_t            VinPSel;     /*!< Specify the opa VINP vin p select */
+    uint8_t            VinMSel;     /*!< Specify the opa VINM vin m select */
+    uint8_t            TrimEn;      /*!< Specify if the opa auto trim */
+}OPA_InitTypeDef;
+
+/**
+  * @brief  OPA handle Structure definition
+  */
+typedef struct
+{
+  OPA_TypeDef       *Instance;       /*!< Register base address    */
+  OPA_InitTypeDef   Init;            /*!< OPA required parameters */
+} OPA_HandleTypeDef;
+
+
+#define OPA_CSR_VINPSEL_0               (0U)
+#define OPA_CSR_VINPSEL_1               (1U)
+
+#define OPA_CSR_VINMSEL_0               (0U)
+#define OPA_CSR_VINMSEL_1               (1U)
+
+#define OPA_CSR1_VINPSEL_PA4            (0U)
+#define OPA_CSR1_VINPSEL_PB6            (1U)
+
+#define OPA_CSR1_VINMSEL_PB5            (0U)
+#define OPA_CSR1_VINMSEL_PD5            (1U)
+
+#define OPA_CSR2_VINPSEL_PB3            (0U)
+#define OPA_CSR2_VINPSEL_PB4            (1U)
+
+#define OPA_CSR2_VINMSEL_PB1            (0U)
+#define OPA_CSR2_VINMSEL_PD4            (1U)
+
+#define OPA_CSR3_VINPSEL_PA7            (0U)
+#define OPA_CSR3_VINPSEL_PB2            (1U)
+
+#define OPA_CSR3_VINMSEL_PA5            (0U)
+#define OPA_CSR3_VINMSEL_PC4            (1U)
+
+#define OPA_CSR_TRIM_DISABLE           (0U)
+#define OPA_CSR_TRIM_ENABLE            (1U)
+
+/******************************** OPA Instances *******************************/
+#define IS_OPA_ALL_INSTANCE(INSTANCE)      (((INSTANCE) == OPA))
+
+/******************************** OPA OPAX definition*******************************/
+#define IS_OPA_ALL_OPAX(_OPAX)             (((_OPAX) == OPA1) || \
+                                            ((_OPAX) == OPA2) || \
+                                            ((_OPAX) == OPA3))
+
+/******************************** OPA VINP select definition*******************************/
+#define IS_OPA_ALL_VINP(VINPSEL)           (((VINPSEL) == OPA_CSR_VINPSEL_0) || \
+                                            ((VINPSEL) == OPA_CSR_VINPSEL_1))
+
+/******************************** OPA VINM select definition*******************************/
+#define IS_OPA_ALL_VINM(VINMSEL)           (((VINMSEL) == OPA_CSR_VINMSEL_0) || \
+                                            ((VINMSEL) == OPA_CSR_VINMSEL_1))
+
+/******************************** OPA trim enable definition*******************************/
+#define IS_OPA_ALL_TRIM(_TRIM)             (((_TRIM) == OPA_CSR_TRIM_DISABLE) || \
+                                            ((_TRIM) == OPA_CSR_TRIM_ENABLE))
+
+/* Function : HAL_OPA */
+void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa);
+void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_DeInit(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Enable(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa);
+
+#endif
+
+
+
+
+
@@ -0,0 +1,128 @@
+/***********************************************************************
+ * Filename    : hal_timer_ex.h
+ * Description : timer driver header file
+ * Author(s)   : xwl
+ * version     : V1.0
+ * Modify date : 2021-03-24
+ ***********************************************************************/
+#ifndef __HAL_TIMER_EX_H__
+#define __HAL_TIMER_EX_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk
+
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#ifdef HAL_COMP_MODULE_ENABLED
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#endif /* COMP1 && COMP2 */
+
+#define TIM_BREAKINPUT_BRK     0x00000001U
+
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk
+
+
+typedef struct
+{
+  uint32_t OffStateRunMode;           // TIM off state in run mode
+  uint32_t OffStateIDLEMode;          // TIM off state in IDLE mode
+  uint32_t LockLevel;                 // TIM Lock level
+  uint32_t DeadTime;                  // TIM dead Time
+  uint32_t BreakState;                // TIM Break State
+  uint32_t BreakPolarity;             // TIM Break input polarity
+  uint32_t BreakFilter;               // Specifies the break input filter.
+  uint32_t AutomaticOutput;           // TIM Automatic Output Enable state
+} TIM_BreakDeadTimeConfigTypeDef;
+
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
+
+
+#endif
+
+
+
+
@@ -0,0 +1,36 @@
+/*
+  ******************************************************************************
+  * @file    HAL_UART_EX.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of UART EX HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_UART_EX_H__
+#define __HAL_UART_EX_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Bit definition for UART IE register  ***********************/
+#define UART_EX_IE_BCNTI                    BIT12
+#define UART_EX_IE_LBDI                     BIT11
+
+/****************  Bit definition for UART RIS register  ***********************/
+#define UART_EX_RIS_BCNTI                   BIT12
+#define UART_EX_RIS_LBDI                    BIT11
+
+/****************  Bit definition for UART BCNT register  ***********************/
+#define UART_EX_BCNT_START                   BIT8
+#define UART_EX_BCNT_VALUE_POS              (0U)
+#define UART_EX_BCNT_VALUE_MASK             (0xFFU)
+
+/****************  Definition of LIN BUS VERSION  ***********************/
+#define UART_LIN_V1D3         0    //Lin bus version 1.3
+#define UART_LIN_V2DX         1    //Lin bus version 2.0/2.1/2.2
+
+void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size);
+void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size);
+uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout);
+uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout);
+
+#endif
@@ -0,0 +1,118 @@
+
+/***********************************************************************
+ * Filename    : HAL_WDT.h
+ * Description : HAL WDT driver header file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17
+ ***********************************************************************/
+
+#ifndef __HAL_WDT_H__
+#define __HAL_WDT_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+/****************  Bit definition for WDT CTRL register  ********************/
+#define WDT_CTRL_EN                         BIT7
+#define WDT_CTRL_MODE                       BIT6
+#define WDT_CTRL_INTEN                      BIT4
+#define WDT_CTRL_DIVISOR                    (BIT0|BIT1|BIT2)
+
+/****************  Bit definition for WDTRIS register  ********************/
+#define WDT_WDTRIS                          BIT0
+
+typedef enum
+{
+    WDT_MODE_RST = 0x00U,
+    WDT_MODE_INT = 0x01U,
+} WDT_MODE;
+
+typedef enum
+{
+    WDT_DIVISOR_NONE = 0x00U,
+    WDT_DIVISOR_2 = 0x01U,
+    WDT_DIVISOR_4 = 0x02U,
+    WDT_DIVISOR_8 = 0x03U,
+    WDT_DIVISOR_16 = 0x04U,
+    WDT_DIVISOR_32 = 0x05U,
+    WDT_DIVISOR_64 = 0x06U,
+    WDT_DIVISOR_128 = 0x07U,
+} WDT_DIVISOR;
+
+typedef struct
+{
+    WDT_DIVISOR WDTDivisor;
+    WDT_MODE WDTMode;
+    uint32_t WDTLoad;
+    uint32_t WDTINTCLRTIME;
+} WDT_InitTypeDef;
+
+typedef struct
+{
+    WDT_TypeDef            *Instance;                /*!< WDT registers base address        */
+    WDT_InitTypeDef         Init;                    /*!< WDT communication parameters      */
+}WDT_HandleTypeDef;
+
+#define WDT_ENABLE                      (0x01 << 7)
+#define WDT_DISABLE                     (~WDT_ENABLE)
+#define WDT_INT_ENABLE                  (0x01 << 4)
+#define WDT_INT_DISABLE                 (~WDT_INT_ENABLE)
+/************************************************************************
+ * function   : HAL_WDT_Feed
+ * Description: WDT feed.
+ * input :
+ *         none
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_IRQHandler
+ * Description: WDT interrupt service routine.
+ * input :
+ *         none
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : HAL_WDT_Init
+ * Description: WDT initiation.
+ * input :
+ *         pinit initiation parameters
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Init(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Start
+ * Description: WDT start
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Start(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Stop
+ * Description: WDT stop
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Int_Enable
+ * Description: WDT int enable
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Int_Disable
+ * Description: WDT int disable
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt);
+
+#endif
@@ -0,0 +1,54 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Crc.c
+  * @author  Firmware Team
+  * @version V1.0.0
+  * @date    2020
+  * @brief   CRC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include  "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_CRC_Init
+* Description : Initialize the CRC MSP.
+* Input       : hcrc: CRC handle.
+* Output      :
+* Author      : cl                         Data : 2021
+**********************************************************************************/
+void HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+    System_Module_Enable(EN_CRC);
+    hcrc->Instance->CTRL = hcrc->Init.PolyRev | hcrc->Init.OutxorRev | hcrc->Init.InitRev | hcrc->Init.RsltRev |
+                           hcrc->Init.DataRev | hcrc->Init.PolyLen   | hcrc->Init.DataLen;
+
+    hcrc->Instance->INIT = hcrc->Init.InitData;
+    hcrc->Instance->OUTXOR = hcrc->Init.OutXorData;
+    hcrc->Instance->POLY = hcrc->Init.PolyData;
+}
+
+/*********************************************************************************
+* Function    : HAL_CRC_Calculate
+* Description : Calculate the crc calue of input data.
+* Input       : hcrc:         CRC handle.
+* Output      : CRC value
+* Author      : cl                        Data : 2021
+**********************************************************************************/
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc)
+{
+    HAL_CRC_Init(hcrc);
+
+    while(hcrc->CRC_Data_Len--)
+    {
+        hcrc->Instance->DATA = *hcrc->CRC_Data_Buff++;
+    }
+
+    return (hcrc->Instance->DATA);
+}
+
+
@@ -0,0 +1,22 @@
+#include "HAL_DIV.h"
+
+//Computes q = b div c and a = b mod c
+//cDigits must be 1, and *c < 0xffffffff
+void hardwareNN_Div_q32(UINT32 *q,UINT32 *a,UINT32 *b,UINT32 bDigits,UINT32 *c,UINT32 cDigits)
+{
+    UINT32 * p;
+    int i;
+
+    DIV->REMAIN = 0;
+    DIV->DIVISOR = *c;
+    for(i = (bDigits-1); i >= 0 ; i -- )
+    {
+        p = (UINT32*) (b + i);
+        DIV->DIVIDENED = *p;
+
+        while((DIV->STATUS&0x01)!=0x01);
+        DIV->STATUS = 0x01;
+        (*(q+i)) = (UINT32)DIV->QUOTIENT;
+    }
+    (*a) = DIV->REMAIN;
+}
@@ -0,0 +1,77 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   EFlash HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           @ Program operations functions
+  *           @ Erase   operations functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_EFlash_Init
+* Description : Configure eflash parameter as system clock
+* Input       : system clock frequency
+* Output      : None
+* Author      : Chris_Kyle
+**********************************************************************************/
+void HAL_EFlash_Init(uint32_t fu32_freq)
+{
+    HAL_EFlash_Init_Para(fu32_freq);
+}
+
+/*
+* Function    : HAL_EFlash_Erase_Page
+* Description : Erase a Page, TERASE has been configured in System_Clock_Init()
+* Input       :
+* Outpu       : false: FAIL
+                true:  SUCCESS
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr)
+{
+    EFC->CTRL |= EFC_CTRL_PAGE_ERASE_MODE;
+
+    EFC->SEC = 0x55AAAA55;
+
+    *((volatile uint32_t *)fu32_Addr) = 0;
+
+    while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY));
+
+    EFC->CTRL &= ~EFC_CTRL_PAGE_ERASE_MODE;
+
+    return true;
+}
+
+/*********************************************************************************
+* Function    : HAL_EFlash_Programe
+* Description : Program a word, TPROG has been configured in System_Clock_Init()
+* Input       :
+* Outpu       : false: FAIL
+                true:  SUCCESS
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data)
+{
+    if (fu32_Addr % 4)
+    {
+        return false;
+    }
+
+    EFC->CTRL |= EFC_CTRL_PROGRAM_MODE;
+
+    EFC->SEC = 0x55AAAA55;
+
+    *((volatile uint32_t *)fu32_Addr) = fu32_Data;
+
+    while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY));
+
+    EFC->CTRL &= ~EFC_CTRL_PROGRAM_MODE;
+
+    return true;
+}
+
@@ -0,0 +1,184 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EXTI.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization functions
+  *           + IO operation functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_EXTI_IRQHandler
+* Description : Handle EXTI interrupt request.
+* Input       : huart: EXTI handle.
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020��
+**********************************************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+    if (EXTI->PDR & hexti->u32_Line)
+    {
+        EXTI->PDR = hexti->u32_Line;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_SetConfigLine
+* Description :
+* Input       :
+* Outpu       :
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti)
+{
+    uint32_t lu32_IndexLine;
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))      return HAL_ERROR;
+    if (!IS_EXTI_MODE(hexti->u32_Mode))          return HAL_ERROR;
+    if (!IS_EXTI_TRIGGER(hexti->u32_Trigger))    return HAL_ERROR;
+
+    /* Line0 ~ 15 trigger from GPIO */
+    if (!(hexti->u32_Line >> 16))
+    {
+        if (!IS_EXTI_GPIOSEL(hexti->u32_GPIOSel))    return HAL_ERROR;
+    }
+#endif
+
+    lu32_IndexLine = hexti->u32_Line;
+
+    /* Interrupt Mode */
+    if (hexti->u32_Mode == EXTI_MODE_INTERRUPT)
+    {
+        EXTI->IENR |=  lu32_IndexLine;
+        EXTI->EENR &= ~lu32_IndexLine;
+
+        NVIC_ClearPendingIRQ(EXTI_IRQn);
+        NVIC_EnableIRQ(EXTI_IRQn);
+    }
+    /* Event Mode */
+    else if (hexti->u32_Mode == EXTI_MODE_EVENT)
+    {
+        EXTI->EENR |=  lu32_IndexLine;
+        EXTI->IENR &= ~lu32_IndexLine;
+    }
+
+
+    if (hexti->u32_Trigger == EXTI_TRIGGER_RISING)
+    {
+        EXTI->RTENR |=  lu32_IndexLine;
+        EXTI->FTENR &= ~lu32_IndexLine;
+    }
+    else if (hexti->u32_Trigger == EXTI_TRIGGER_FALLING)
+    {
+        EXTI->FTENR |=  lu32_IndexLine;
+        EXTI->RTENR &= ~lu32_IndexLine;
+    }
+    else
+    {
+        EXTI->FTENR |= lu32_IndexLine;
+        EXTI->RTENR |= lu32_IndexLine;
+    }
+
+    /* Line0 ~ 15 trigger from GPIO */
+    if (!(hexti->u32_Line >> 16))
+    {
+        lu32_IndexLine = 0;
+
+        while(hexti->u32_Line >> lu32_IndexLine != 0x01)
+        {
+            lu32_IndexLine++;
+        }
+
+        /* Line0 ~ 7 */
+        if (lu32_IndexLine < 8)
+        {
+            EXTI->EXTICR1 = (EXTI->EXTICR1 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4);
+        }
+        /* Line8 ~ 15 */
+        else
+        {
+            lu32_IndexLine -= 8;
+
+            EXTI->EXTICR2 = (EXTI->EXTICR2 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4);
+        }
+    }
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_SoftTrigger
+* Description : Software trigger EXTI
+* Input       :
+* Outpu       :
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))    return;
+#endif
+
+    /* Set pending BIT */
+    EXTI->SWIER |= hexti->u32_Line;
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_GetPending
+* Description : Get interrupt pending bit of a dedicated line.
+* Input       :
+* Outpu       :
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))    return HAL_ERROR;
+#endif
+
+    if (hexti->u32_Line & EXTI->PDR)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_ClearPending
+* Description : Clear interrupt pending bit of a dedicated line.
+* Input       :
+* Outpu       :
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))    return;
+#endif
+
+    /* Clear pending status */
+    EXTI->PDR |= hexti->u32_Line;
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_ClearAllPending
+* Description : Clear all interrupt pending bit.
+* Input       :
+* Outpu       :
+* Author      : xwl                         Data : 2021年
+**********************************************************************************/
+void HAL_EXTI_ClearAllPending(void)
+{
+    /* Clear pending status */
+    EXTI->PDR |= EXTI_LINE_MASK;
+}
+
@@ -0,0 +1,71 @@
+/***********************************************************************
+ * Filename    : HAL_IWDT.c
+ * Description : HAL IWDT driver source file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17
+ ***********************************************************************/
+#include  "ACM32Fxx_HAL.h"
+
+
+HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt)
+{
+    if (hidt == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    System_Delay(1);
+
+    System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);
+    System_Enable_RC32K();
+    System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_IWDT, FUNC_ENABLE);
+    /*Enable IWDT  */
+    hidt->Instance->CMDR = IWDT_ENABLE_COMMAND;
+    System_Delay(10);
+    /*Enable Write  */
+    hidt->Instance->CMDR = IWDT_WRITE_ENABLE_COMMAND;
+    System_Delay(10);
+
+    hidt->Instance->PR = hidt->Init.Prescaler;
+    hidt->Instance->RLR = hidt->Init.Reload;
+    hidt->Instance->WINR = hidt->Init.Window;
+    hidt->Instance->WUTR = hidt->Init.Wakeup;
+    System_Delay(1);
+    while(hidt->Instance->SR & (0x0F)){}; // wait for configuration done
+
+    if (hidt->Init.Reload > hidt->Init.Wakeup)
+    {
+        /*Enable Wake up  */
+        hidt->Instance->CMDR = IWDT_WAKEUP_ENABLE_COMMAND;
+    }
+
+    hidt->Instance->CMDR = IWDT_RELOAD_COMMAND;
+    System_Delay(1);
+    while(hidt->Instance->SR & (1 << 4)){};
+
+    return HAL_OK;
+
+}
+
+HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt)
+{
+    hidt->Instance->CMDR = IWDT_RELOAD_COMMAND;
+    System_Delay(1);
+    while(hidt->Instance->SR & (1 << 4)){};  //wait for kick watchdog done
+
+    return HAL_OK;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -0,0 +1,117 @@
+/***********************************************************************
+ * Filename    : HAL_WDT.c
+ * Description : HAL WDT driver source file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17
+ ***********************************************************************/
+#include  "ACM32Fxx_HAL.h"
+
+/************************************************************************
+ * function   : HAL_WDT_Feed
+ * Description: WDT feed.
+ * input :
+ *         none
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->FEED = 0xAA55A55A;
+}
+/************************************************************************
+ * function   : HAL_WDT_IRQHandler
+ * Description: WDT interrupt service routine.
+ * input :
+ *         none
+ * return: none
+ ************************************************************************/
+void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt)
+{
+#ifdef __GNUC__
+    #pragma GCC diagnostic push   
+    #pragma GCC diagnostic ignored "-Wunused-but-set-variable"
+#endif
+    volatile uint32_t wdt_ris = 0;
+    wdt_ris = hwdt->Instance->RIS;
+    HAL_WDT_Feed(hwdt);
+    NVIC_ClearPendingIRQ(WDT_IRQn);
+#ifdef __GNUC__
+    #pragma GCC diagnostic pop
+#endif
+}
+
+/************************************************************************
+ * function   : HAL_WDT_Init
+ * Description: WDT initiation.
+ * input :
+ *         pinit initiation parameters
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Init(WDT_HandleTypeDef* hwdt)
+{
+    System_Module_Enable(EN_WDT);
+    System_Delay(1);
+    System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);
+    System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_WDT, FUNC_ENABLE);
+
+    hwdt->Instance->LOAD = hwdt->Init.WDTLoad;
+    hwdt->Instance->CTRL = (hwdt->Instance->CTRL & ~0x47) | (hwdt->Init.WDTDivisor) | (hwdt->Init.WDTMode << 6);
+
+    if (WDT_MODE_INT == hwdt->Init.WDTMode)
+    {
+        hwdt->Instance->INTCLRTIME = hwdt->Init.WDTINTCLRTIME;
+        HAL_WDT_Int_Enable(hwdt);
+    }
+}
+
+/************************************************************************
+ * function   : HAL_WDT_Start
+ * Description: WDT start
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Start(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL |= WDT_ENABLE;
+}
+
+/************************************************************************
+ * function   : WDT_Stop
+ * Description: WDT stop
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL &= WDT_DISABLE;
+}
+
+/************************************************************************
+ * function   : WDT_Int_Enable
+ * Description: WDT int enable
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL |= WDT_INT_ENABLE;
+    NVIC_ClearPendingIRQ(WDT_IRQn);
+    NVIC_EnableIRQ(WDT_IRQn);
+}
+
+/************************************************************************
+ * function   : WDT_Int_Disable
+ * Description: WDT int disable
+ * input : none
+ *
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL &= WDT_INT_DISABLE;
+}
+
+
@@ -0,0 +1,34 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+Device/System_ACM32F0x0.c
+HAL_Driver/Src/HAL_DMA.c
+HAL_Driver/Src/HAL_ADC.c
+HAL_Driver/Src/HAL_GPIO.c
+HAL_Driver/Src/HAL_WDT.c
+HAL_Driver/Src/HAL_IWDT.c
+HAL_Driver/Src/HAL_UART.c
+HAL_Driver/Src/HAL_TIMER.c
+HAL_Driver/Src/HAL_EXTI.c
+""")
+
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src = src + ['Device/Startup_ACM32F0x0_gcc.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src = src + ['Device/Startup_ACM32F0x0.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['Device/Startup_ACM32F0x0_iar.s']
+
+path = [cwd + '/HAL_Driver/Inc',
+    cwd + '/Device',
+    cwd + '/CMSIS']
+
+group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'D:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iar'
+    EXEC_PATH   = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -g -Wall'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -Os -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu ' + CPU
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' --c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=' + CPU
+    CFLAGS += ' -e'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu ' + CPU
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    CXXFLAGS = CFLAGS
+    LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
+
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
@@ -0,0 +1,182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ACM32F0x0</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>1</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F0x0 -FS00 -FL020000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
@@ -413,7 +413,6 @@ void list_irq(void)
 }

 #include <finsh.h>
-FINSH_FUNCTION_EXPORT(list_irq, list system irq);

 #ifdef FINSH_USING_MSH
 int cmd_list_irq(int argc, char** argv)
@@ -421,8 +420,7 @@ int cmd_list_irq(int argc, char** argv)
    list_irq();
    return 0;
 }
-FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
-
+MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq);
 #endif
 #endif
 #endif
@@ -38,15 +38,14 @@ int cmd_reset(int argc, char** argv)
    rt_hw_cpu_reset();
    return 0;
 }
+MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system);

 int cmd_shutdown(int argc, char** argv)
 {
    rt_hw_cpu_shutdown();
    return 0;
 }
-
-FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
-FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
+MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system);

 #endif
 #endif
@@ -445,7 +445,6 @@ void list_irq(void)
 }

 #include <finsh.h>
-FINSH_FUNCTION_EXPORT(list_irq, list system irq);

 #ifdef FINSH_USING_MSH
 int cmd_list_irq(int argc, char** argv)
@@ -453,8 +452,7 @@ int cmd_list_irq(int argc, char** argv)
    list_irq();
    return 0;
 }
-FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
-
+MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq);
 #endif
 #endif
 #endif
@@ -30,7 +30,6 @@ void machine_shutdown(void)
 #ifdef RT_USING_FINSH

 #include <finsh.h>
-FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);

 #ifdef FINSH_USING_MSH
 int cmd_reset(int argc, char** argv)
@@ -38,15 +37,14 @@ int cmd_reset(int argc, char** argv)
    rt_hw_cpu_reset();
    return 0;
 }
+MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system);

 int cmd_shutdown(int argc, char** argv)
 {
    rt_hw_cpu_shutdown();
    return 0;
 }
-
-FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
-FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
+MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system);

 #endif
 #endif
@@ -163,5 +163,4 @@ void rt_hw_cpu_reset(void)
    REG32(PRM_DEVICE(prcm_base)) = 0x1;
    RT_ASSERT(0);
 }
-FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);
-FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, __cmd_reboot, reboot the cpu);
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);