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Merge branch 'master' of https://github.com/RT-Thread/rt-thread into bsp-to-apache

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This commit is contained in:
yangjie
2021-04-09 18:38:40 +08:00
parent 75e4c9dd0a e99448c313
commit 3755427ff1
27 changed files with 1298 additions and 391 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/bluetrum/ab32vg1-ab-prougen/.config
+45 -11
View File
@@ -23,6 +23,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=512
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=256
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -258,8 +259,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
@@ -274,6 +273,12 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
@@ -332,6 +337,13 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
#
# system packages
@@ -339,7 +351,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
@@ -349,6 +360,9 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
@@ -370,12 +384,13 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_PRINTF is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
#
# peripheral libraries and drivers
@@ -438,6 +453,24 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
@@ -469,25 +502,24 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
#
# Hardware Drivers Config
@@ -496,14 +528,16 @@ CONFIG_RT_USING_LIBC=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_AUDIO is not set
# CONFIG_BSP_USING_SDCARD is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_PWM is not set
bsp/bluetrum/ab32vg1-ab-prougen/.cproject
+154 -155
View File
File diff suppressed because one or more lines are too long
bsp/bluetrum/ab32vg1-ab-prougen/README.md
+25 -11
View File
@@ -35,19 +35,20 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
| USB 转串口 | 支持 | |
| SD卡 | 支持 | |
| IRDA | 即将支持 | |
| 音频接口 | 支持 | |
| 音频接口 | 支持 | 支持音频输出 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA PB PE PF |
| UART | 支持 | UART0/1/2 |
| SDIO | 支持 | |
| ADC | 即将支持 | |
| ADC | 支持 | 10bit ADC |
| SPI | 即将支持 | 软件 SPI |
| I2C | 支持 | 软件 I2C |
| RTC | 即将支持 | |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 即将支持 | |
| FLASH | 即将支持 | 对接 FAL |
| TIMER | 支持 | |
| PWM | 支持 | LPWM 的 G1 G2 G3 之间是互斥的，只能三选一 |
| FM receive | 即将支持 | |
| USB Device | 暂不支持 | |
| USB Host | 暂不支持 | |
@@ -68,8 +69,6 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
本 BSP 为开发者提供 GCC 开发环境。下面介绍如何将系统运行起来。
教学视频：https://www.bilibili.com/video/BV1RV411v75P/
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
@@ -96,11 +95,12 @@ msh >
此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons` 命令重新编译工程。
更多细节请参见使用指南：https://ab32vg1-example.readthedocs.io/zh/latest/introduction.html
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons` 命令重新编译工程。
## 注意事项
@@ -110,12 +110,26 @@ msh >
编译报错的时候，如果出现重复定义的报错，可能需要在 `cconfig.h` 中手动添加以下配置
```
``` c
#define HAVE_SIGEVENT 1
#define HAVE_SIGINFO 1
#define HAVE_SIGVAL 1
```
所有在中断中使用的函数或数据需要放在 RAM 中，否则会导致系统运行报错。具体做法可以参考下面
``` c
RT_SECTION(".irq.example.str")
static const char example_info[] = "example 0x%x";
RT_SECTION(".irq.example")
void example_isr(void)
{
rt_kprintf(example_info, 11);
...
}
```
## 维护人信息
- [greedyhao](https://github.com/greedyhao)
bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c
+6
View File
@@ -8,6 +8,12 @@
* 2020/12/10 greedyhao The first version
*/
/**
* Notice!
* All functions or data that are called during an interrupt need to be in RAM.
* You can do it the way exception_isr() does.
*/
#include <rtthread.h>
#include "board.h"
bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig
+8 -8
View File
@@ -90,16 +90,16 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_T4_PWM
config BSP_USING_T4_PWM1
bool "Enable Timer4 PWM1 (PA6)(Confit with uart0 rx)"
default n
default y
endif
menuconfig BSP_USING_T5_PWM
bool "Enable Timer5 PWM"
default n
default y
if BSP_USING_T5_PWM
config BSP_USING_T5_PWM0
bool "Enable Timer5 PWM2 (PE1)"
default n
default y
endif
menuconfig BSP_USING_LPWM0
@@ -109,7 +109,7 @@ menu "On-chip Peripheral Drivers"
comment "G1, G2 and G3 are mutually exclusive"
config BSP_USING_LPWM0_G1
bool "Enable LPWM0 G1 (PE4)"
default n
default y
endif
menuconfig BSP_USING_LPWM1
@@ -119,7 +119,7 @@ menu "On-chip Peripheral Drivers"
comment "G1, G2 and G3 are mutually exclusive"
config BSP_USING_LPWM1_G3
bool "Enable LPWM1 G3 (PA1)"
default n
default y
endif
menuconfig BSP_USING_LPWM2
@@ -129,7 +129,7 @@ menu "On-chip Peripheral Drivers"
comment "G1, G2 and G3 are mutually exclusive"
config BSP_USING_LPWM2_G2
bool "Enable LPWM2 G2 (PE0)"
default n
default y
config BSP_USING_LPWM2_G3
bool "Enable LPWM2 G3 (PA2)"
default n
@@ -148,7 +148,7 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_TIM
config BSP_USING_TIM1
bool "Enable TIM1"
default n
default y
config BSP_USING_TIM2
bool "Enable TIM2"
@@ -189,7 +189,7 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
default y
endif
endmenu
bsp/bluetrum/ab32vg1-ab-prougen/board/board.c
+61
View File
@@ -13,10 +13,21 @@
int rt_hw_usart_init(void);
void my_printf(const char *format, ...);
void my_print_r(const void *buf, uint16_t cnt);
void timer0_cfg(uint32_t ticks);
void rt_soft_isr(int vector, void *param);
void cpu_irq_comm(void);
void set_cpu_irq_comm(void (*irq_hook)(void));
void load_cache();
void sys_error_hook(uint8_t err_no);
typedef void (*os_cache_setfunc_func)(void *load_cache_func, void *io_read);
typedef void (*spiflash_init_func)(uint8_t sf_read, uint8_t dummy);
#define os_cache_setfunc ((os_cache_setfunc_func) 0x84024)
static struct rt_mutex mutex_spiflash = {0};
extern volatile rt_uint8_t rt_interrupt_nest;
extern uint32_t __heap_start, __heap_end;
void hal_printf(const char *fmt, ...)
@@ -55,6 +66,7 @@ void hal_printf(const char *fmt, ...)
va_end(args);
}
RT_SECTION(".irq.timer")
void timer0_isr(int vector, void *param)
{
rt_interrupt_enter();
@@ -132,3 +144,52 @@ void rt_hw_us_delay(rt_uint32_t us)
{
}
RT_SECTION(".irq.cache")
void cache_init(void)
{
os_cache_setfunc(load_cache, NULL);
rt_mutex_init(&mutex_spiflash, "flash_mutex", RT_IPC_FLAG_FIFO);
}
RT_SECTION(".irq.cache")
void os_spiflash_lock(void)
{
// if (rt_thread_self()->stat == RT_THREAD_RUNNING) {
if ((rt_thread_self() != RT_NULL) && (rt_interrupt_nest == 0)) {
rt_mutex_take(&mutex_spiflash, RT_WAITING_FOREVER);
}
}
RT_SECTION(".irq.cache")
void os_spiflash_unlock(void)
{
// if (rt_thread_self()->stat == RT_THREAD_RUNNING) {
if ((rt_thread_self() != RT_NULL) && (rt_interrupt_nest == 0)) {
rt_mutex_release(&mutex_spiflash);
}
}
RT_SECTION(".irq.err.str")
static const char stack_info[] = "thread sp=0x%x name=%s";
void rt_hw_console_output(const char *str)
{
my_printf(str);
}
/**
* @brief print exception error
* @note Every message needed to print, must put in .comm exction.
*/
RT_SECTION(".irq.err")
void exception_isr(void)
{
extern long list_thread(void);
sys_error_hook(1);
rt_console_set_device(RT_NULL);
rt_kprintf(stack_info, rt_thread_self()->sp, rt_thread_self()->name);
while(1);
}
bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c
+56 -6
View File
@@ -15,15 +15,17 @@
#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100u)
#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000u)
#define TX_FIFO_SIZE (1024)
#define TX_FIFO_SIZE (1024)
struct sound_device
{
struct rt_audio_device audio;
struct rt_audio_configure replay_config;
rt_sem_t semaphore;
rt_thread_t thread;
rt_uint8_t *tx_fifo;
rt_uint8_t *rx_fifo;
rt_uint8_t volume;
rt_uint8_t volume;
};
static struct sound_device snd_dev = {0};
@@ -105,6 +107,17 @@ void dac_start(void)
//AUANGCON1 |= BIT(3); // pa mute
}
RT_SECTION(".irq.audio")
void audio_sem_post(void)
{
rt_sem_release(snd_dev.semaphore);
}
void audio_sem_pend(void)
{
rt_sem_take(snd_dev.semaphore, RT_WAITING_FOREVER);
}
void saia_frequency_set(uint32_t frequency)
{
if (frequency == SAI_AUDIO_FREQUENCY_48K) {
@@ -359,7 +372,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
DACVOLCON = 0x7fff; // -60DB
DACVOLCON |= BIT(20);
AUBUFCON |= BIT(1) | BIT(4);
AUBUFCON |= BIT(1);
}
return RT_EOK;
@@ -391,7 +404,10 @@ rt_size_t sound_transmit(struct rt_audio_device *audio, const void *writeBuf, vo
snd_dev = (struct sound_device *)audio->parent.user_data;
while (tmp_size-- > 0) {
while(AUBUFCON & BIT(8)); // aubuf full
if (AUBUFCON & BIT(8)) { // aubuf full
AUBUFCON |= BIT(1) | BIT(4);
audio_sem_pend();
}
AUBUFDATA = ((const uint32_t *)writeBuf)[count++];
}
@@ -429,18 +445,32 @@ static struct rt_audio_ops ops =
.buffer_info = sound_buffer_info,
};
void audio_isr(int vector, void *param)
RT_SECTION(".irq.audio")
static void audio_isr(int vector, void *param)
{
rt_interrupt_enter();
//Audio buffer pend
if (AUBUFCON & BIT(5)) {
AUBUFCON |= BIT(1); //Audio Buffer Pend Clear
rt_audio_tx_complete(&snd_dev.audio);
AUBUFCON &= ~BIT(4);
audio_sem_post();
}
rt_interrupt_leave();
}
static void audio_thread_entry(void *parameter)
{
while (1)
{
if (snd_dev.audio.replay->activated == RT_TRUE) {
rt_audio_tx_complete(&snd_dev.audio);
} else {
rt_thread_mdelay(50);
}
}
}
static int rt_hw_sound_init(void)
{
rt_uint8_t *tx_fifo = RT_NULL;
@@ -464,6 +494,26 @@ static int rt_hw_sound_init(void)
snd_dev.rx_fifo = rx_fifo;
snd_dev.semaphore = rt_sem_create("snd", 0, RT_IPC_FLAG_FIFO);
if (snd_dev.semaphore == RT_NULL)
{
return -RT_ENOMEM;
}
snd_dev.thread = rt_thread_create(
"audio",
audio_thread_entry,
RT_NULL,
1024,
20, // must equal or lower than tshell priority
5
);
if (snd_dev.thread != RT_NULL)
{
rt_thread_startup(snd_dev.thread);
}
/* init default configuration */
{
snd_dev.replay_config.samplerate = 48000;
bsp/bluetrum/ab32vg1-ab-prougen/link.lds
+33 -16
View File
@@ -3,8 +3,8 @@ __max_flash_size = 1024k;
__data_ram_size = 8k;
__stack_ram_size = 4k;
__comm_ram_size = 83k;
__heap_ram_size = 29k;
__comm_ram_size = 42k;
__heap_ram_size = 70k;
__base = 0x10000000;
@@ -47,26 +47,43 @@ SECTIONS
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
*components*drivers**.o (.text*)
*components.o (.text*)
*save-restore.o (.text* .rodata*)
*libcpu*cpu*context_gcc.o (.text* .rodata*)
*libcpu*cpu*interrupt.o (.text* .rodata*)
*libcpu**.o (.rodata*)
*components*drivers*misc*pin.o(.text*)
*components*drivers*misc*adc.o(.text*)
. = ALIGN(4);
*src*ipc.o (.text* .rodata*)
*src*irq.o (.text* .rodata*)
*src*object.o (.text* .rodata*)
*src*thread.o (.text* .rodata*)
*src*timer.o (.text* .rodata*)
*src*mempool.o (.text* .rodata*)
*src*scheduler.o (.text* .rodata*)
*src*clock.o (.text* .rodata*)
*src*kservice.o (.text* .rodata*)
*src*device.o (.text* .rodata*)
*src*idle.o (.text* .rodata*)
*src*components.o (.text* .rodata*)
} > ram1 AT > flash
.comm __comm_vma : {
. = ALIGN(4);
KEEP(*(.vector))
EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o
*romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o
*letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o
*trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o
*fixdfsi.o *addsf3.o *divsf3.o *eqsf2.o *gesf2.o *float*.o
*lesf2.o *mulsf3.o *subsf3.o *fixsfsi.o *fixunssfsi.o) *(.text)
*finsh*shell.o (.text*)
*(.irq*)
/*applications**.o (.text .rodata)*/
*hal_libraries*ab32vg1_hal**.o (.text .rodata)
*(.text.unlikely)
*(.text.startup)
EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o
*cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)
*(.rodata.name)
EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4)
*hal_drivers**.o (.rodata)
*audio*drv_sound.o (.rodata)
*system_ab32vgx.o (.rodata)
EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o
*src*mem.o *src*memheap.o *dfs**.o *components.o *drivers*sdio**.o *cmd.o *msh_file.o
*drv_sdio.o *drv_wdt.o) *(.rodata.str1.4)
EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)
*(.rela*)
*(.data*)
@@ -98,7 +115,6 @@ SECTIONS
} > heap
.flash : {
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -109,6 +125,7 @@ SECTIONS
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
*(.text*)
*(.rodata*)
*(.srodata*)
bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h
+5 -2
View File
@@ -145,23 +145,26 @@
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* games: games run on RT-Thread console */
/* entertainment: terminal games and other interesting software packages */
/* Hardware Drivers Config */
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
/* Board extended module Drivers */
bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py
+2 -2
View File
@@ -15,7 +15,7 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'D:/Softwares/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin'
EXEC_PATH = r'D:/program_files/programming/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
@@ -39,7 +39,7 @@ if PLATFORM == 'gcc':
OBJCPY = PREFIX + 'objcopy'
# DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -msave-restore'
# CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c
+39 -5
View File
@@ -68,6 +68,37 @@ static struct ab32_hwtimer ab32_hwtimer_obj[] =
#endif
};
RT_SECTION(".irq.timer")
static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer)
{
RT_ASSERT(timer != RT_NULL);
timer->overflow ++;
if (timer->cycles != 0)
{
timer->cycles --;
}
if (timer->cycles == 0)
{
timer->cycles = timer->reload;
if (timer->mode == HWTIMER_MODE_ONESHOT)
{
if (timer->ops->stop != RT_NULL)
{
timer->ops->stop(timer);
}
}
if (timer->parent.rx_indicate != RT_NULL)
{
timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval));
}
}
}
static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
uint32_t prescaler_value = 0;
@@ -185,25 +216,26 @@ static const struct rt_hwtimer_ops _ops =
};
#if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5)
RT_SECTION(".irq.timer")
void timer2_4_5_isr(int vector, void *param)
{
rt_interrupt_enter();
#ifdef BSP_USING_TIM2
if (ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) {
ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device);
_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device);
}
#endif
#ifdef BSP_USING_TIM4
if (ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) {
ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device);
_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device);
}
#endif
#ifdef BSP_USING_TIM5
if (ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) {
ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device);
_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device);
}
#endif
rt_interrupt_leave();
@@ -211,21 +243,23 @@ void timer2_4_5_isr(int vector, void *param)
#endif
#ifdef BSP_USING_TIM3
RT_SECTION(".irq.timer")
void timer3_isr(int vector, void *param)
{
rt_interrupt_enter();
ab32_hwtimer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device);
_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIM1
RT_SECTION(".irq.timer")
void timer1_isr(int vector, void *param)
{
rt_interrupt_enter();
ab32_hwtimer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device);
_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device);
rt_interrupt_leave();
}
#endif
bsp/bluetrum/libraries/hal_drivers/drv_rtc.c
+1
View File
@@ -253,6 +253,7 @@ static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint
}
#ifdef RT_USING_ALARM
RT_SECTION(".irq.rtc")
static void rtc_isr(int vector, void *param)
{
rt_interrupt_enter();
bsp/bluetrum/libraries/hal_drivers/drv_sdio.c
+2
View File
@@ -496,6 +496,7 @@ static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
* @param host rt_mmcsd_host
* @retval None
*/
RT_SECTION(".irq.sdio")
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
{
int complete = 0;
@@ -616,6 +617,7 @@ static rt_err_t _dma_rxconfig(rt_uint32_t *dst, int Size)
return RT_EOK;
}
RT_SECTION(".irq.sdio")
void sdio_isr(int vector, void *param)
{
/* enter interrupt */
bsp/bluetrum/libraries/hal_drivers/drv_usart.c
+71 -3
View File
@@ -10,6 +10,7 @@
#include "board.h"
#include "drv_usart.h"
#include <shell.h>
#ifdef RT_USING_SERIAL
@@ -147,6 +148,7 @@ static int ab32_putc(struct rt_serial_device *serial, char ch)
return 1;
}
RT_SECTION(".irq.usart")
static int ab32_getc(struct rt_serial_device *serial)
{
int ch;
@@ -168,6 +170,72 @@ static rt_size_t ab32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *
return -1;
}
extern struct finsh_shell *shell;
RT_SECTION(".irq.usart")
static rt_err_t shell_rx_ind(void)
{
RT_ASSERT(shell != RT_NULL);
/* release semaphore to let finsh thread rx data */
rt_sem_release(&shell->rx_sem);
return RT_EOK;
}
RT_SECTION(".irq.usart")
void uart_irq_process(struct rt_serial_device *serial)
{
int ch = -1;
rt_base_t level;
struct rt_serial_rx_fifo* rx_fifo;
/* interrupt mode receive */
rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx;
RT_ASSERT(rx_fifo != RT_NULL);
while (1)
{
ch = serial->ops->getc(serial);
if (ch == -1) break;
/* disable interrupt */
level = rt_hw_interrupt_disable();
rx_fifo->buffer[rx_fifo->put_index] = ch;
rx_fifo->put_index += 1;
if (rx_fifo->put_index >= serial->config.bufsz) rx_fifo->put_index = 0;
/* if the next position is read index, discard this 'read char' */
if (rx_fifo->put_index == rx_fifo->get_index)
{
rx_fifo->get_index += 1;
rx_fifo->is_full = RT_TRUE;
if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0;
// _serial_check_buffer_size();
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
rt_size_t rx_length;
/* get rx length */
level = rt_hw_interrupt_disable();
rx_length = (rx_fifo->put_index >= rx_fifo->get_index)? (rx_fifo->put_index - rx_fifo->get_index):
(serial->config.bufsz - (rx_fifo->get_index - rx_fifo->put_index));
rt_hw_interrupt_enable(level);
if (rx_length)
{
shell_rx_ind();
}
}
RT_SECTION(".irq.usart")
static void uart_isr(int vector, void *param)
{
rt_interrupt_enter();
@@ -175,19 +243,19 @@ static void uart_isr(int vector, void *param)
#ifdef BSP_USING_UART0
if(hal_uart_getflag(UART0_BASE, UART_FLAG_RXPND)) //RX one byte finish
{
rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
uart_irq_process(&(uart_obj[UART0_INDEX].serial));
}
#endif
#ifdef BSP_USING_UART1
if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish
{
rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
uart_irq_process(&(uart_obj[UART1_INDEX].serial));
}
#endif
#ifdef BSP_USING_UART2
if(hal_uart_getflag(UART2_BASE, UART_FLAG_RXPND)) //RX one byte finish
{
rt_hw_serial_isr(&(uart_obj[UART2_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
uart_irq_process(&(uart_obj[UART2_INDEX].serial));
}
#endif
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h
+16 -16
View File
@@ -13,22 +13,22 @@
* @defgroup ADC_channels
* @{
*/
#define ADC_CHANNEL_0 (1u << 0)
#define ADC_CHANNEL_1 (1u << 1)
#define ADC_CHANNEL_2 (1u << 2)
#define ADC_CHANNEL_3 (1u << 3)
#define ADC_CHANNEL_4 (1u << 4)
#define ADC_CHANNEL_5 (1u << 5)
#define ADC_CHANNEL_6 (1u << 6)
#define ADC_CHANNEL_7 (1u << 7)
#define ADC_CHANNEL_8 (1u << 8)
#define ADC_CHANNEL_9 (1u << 9)
#define ADC_CHANNEL_10 (1u << 10)
#define ADC_CHANNEL_11 (1u << 11)
#define ADC_CHANNEL_12 (1u << 12)
#define ADC_CHANNEL_13 (1u << 13)
#define ADC_CHANNEL_14 (1u << 14)
#define ADC_CHANNEL_15 (1u << 15)
#define ADC_CHANNEL_0 (1u << 0) /* PA5 */
#define ADC_CHANNEL_1 (1u << 1) /* PA6 */
#define ADC_CHANNEL_2 (1u << 2) /* PA7 */
#define ADC_CHANNEL_3 (1u << 3) /* PB1 */
#define ADC_CHANNEL_4 (1u << 4) /* PB2 */
#define ADC_CHANNEL_5 (1u << 5) /* PB3 */
#define ADC_CHANNEL_6 (1u << 6) /* PB4 */
#define ADC_CHANNEL_7 (1u << 7) /* PE5 */
#define ADC_CHANNEL_8 (1u << 8) /* PE6 */
#define ADC_CHANNEL_9 (1u << 9) /* PE7 */
#define ADC_CHANNEL_10 (1u << 10) /* PF2 */
#define ADC_CHANNEL_11 (1u << 11) /* VRTC */
#define ADC_CHANNEL_12 (1u << 12) /* WKO */
#define ADC_CHANNEL_13 (1u << 13) /* BGOP */
#define ADC_CHANNEL_14 (1u << 14) /* VBAT */
#define ADC_CHANNEL_15 (1u << 15) /* VUSB */
/**
* @}
*
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h
+1 -1
View File
@@ -34,7 +34,7 @@ enum
// RTCCPND
#define RTC_CPND_1S (0x1u << 18) /*!< Clear RTC 1S pending */
#define RTC_CPND_ALM (0x1u << 17) /*!< Clear RTC alarm pendind */
#define RTC_CPND_ALM (0x1u << 17) /*!< Clear RTC alarm pendind */
// RTCCON0
#define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */
bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S
+10 -8
View File
@@ -37,20 +37,22 @@ _start:
la a2, __bss_size
call memset
call cache_init
la a0, __comm_vma
sw a0, PICADR(zero)
call entry
// la ra, __exception
// jr ra
la ra, __exception
jr ra
.section .vector, "ax"
// .org 0x10
//__exception:
// li sp, 0x10600 //出错后，不破坏错误点的堆栈数据
// jal exception_isr
// 1: j 1b
// mret
.org 0x10
__exception:
li sp, 0x10600 //出错后，不破坏错误点的堆栈数据
jal exception_isr
1: j 1b
mret
.org 0x40
jal x0, low_prio_irq
libcpu/arm/cortex-a/cp15.h
+5
View File
@@ -10,6 +10,11 @@
#ifndef __CP15_H__
#define __CP15_H__
#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
unsigned long rt_cpu_get_smp_id(void);
void rt_cpu_mmu_disable(void);
libcpu/arm/cortex-a/gic.c
+321 -126
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/cortex-a/gic.h
+36 -9
View File
@@ -14,19 +14,46 @@
#include <rthw.h>
#include <board.h>
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
void arm_gic_mask(rt_uint32_t index, int irq);
void arm_gic_umask(rt_uint32_t index, int irq);
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
void arm_gic_set_group(rt_uint32_t index, int vector, int group);
int arm_gic_get_active_irq(rt_uint32_t index);
void arm_gic_ack(rt_uint32_t index, int irq);
void arm_gic_mask(rt_uint32_t index, int irq);
void arm_gic_umask(rt_uint32_t index, int irq);
rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config);
rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
void arm_gic_clear_active(rt_uint32_t index, int irq);
void arm_gic_clear_pending(rt_uint32_t index, int irq);
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq);
void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq);
void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index);
void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point);
rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq);
void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list);
rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index);
rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group);
rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq);
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
void arm_gic_dump_type(rt_uint32_t index);
void arm_gic_dump(rt_uint32_t index);
libcpu/arm/cortex-a/gtimer.c
+171
View File
@@ -0,0 +1,171 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-03-30 huijie.feng first version
*/
#include "cp15.h"
#include <rtdef.h>
/** Set CNTFRQ
* This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
* @param value: CNTFRQ Register value to set
*/
static inline void __set_cntfrq(rt_uint32_t value)
{
__set_cp(15, 0, value, 14, 0, 0);
}
/** Get CNTFRQ
* This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
* return CNTFRQ Register value
*/
static inline rt_uint32_t __get_cntfrq(void)
{
rt_uint32_t result;
__get_cp(15, 0, result, 14, 0 , 0);
return result;
}
/** Set CNTP_TVAL
* This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
* param value: CNTP_TVAL Register value to set
*/
static inline void __set_cntp_tval(rt_uint32_t value)
{
__set_cp(15, 0, value, 14, 2, 0);
}
/** Get CNTP_TVAL
* This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
* return CNTP_TVAL Register value
*/
static inline rt_uint32_t __get_cntp_tval(void)
{
rt_uint32_t result;
__get_cp(15, 0, result, 14, 2, 0);
return result;
}
/** Get CNTPCT
* This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
* return CNTPCT Register value
*/
static inline rt_uint64_t __get_cntpct(void)
{
rt_uint64_t result;
__get_cp64(15, 0, result, 14);
return result;
}
/** Set CNTP_CVAL
* This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
* param value: CNTP_CVAL Register value to set
*/
static inline void __set_cntp_cval(rt_uint64_t value)
{
__set_cp64(15, 2, value, 14);
}
/** Get CNTP_CVAL
* This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
* return CNTP_CVAL Register value
*/
static inline rt_uint64_t __get_cntp_cval(void)
{
rt_uint64_t result;
__get_cp64(15, 2, result, 14);
return result;
}
/** Set CNTP_CTL
* This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
* param value: CNTP_CTL Register value to set
*/
static inline void __set_cntp_ctl(uint32_t value)
{
__set_cp(15, 0, value, 14, 2, 1);
}
/** Get CNTP_CTL register
* return CNTP_CTL Register value
*/
static inline rt_uint32_t __get_cntp_ctl(void)
{
rt_uint32_t result;
__get_cp(15, 0, result, 14, 2, 1);
return result;
}
/** Configures the frequency the timer shall run at.
* param value The timer frequency in Hz.
*/
void gtimer_set_counter_frequency(rt_uint32_t value)
{
__set_cntfrq(value);
__asm__ volatile ("isb 0xF":::"memory");
}
/** Sets the reset value of the timer.
* param value: The value the timer is loaded with.
*/
void gtimer_set_load_value(rt_uint32_t value)
{
__set_cntp_tval(value);
__asm__ volatile ("isb 0xF":::"memory");
}
/** Get the current counter value.
* return Current counter value.
*/
rt_uint32_t gtimer_get_current_value(void)
{
return(__get_cntp_tval());
}
/** Get the current physical counter value.
* return Current physical counter value.
*/
rt_uint64_t gtimer_get_current_physical_value(void)
{
return(__get_cntpct());
}
/** Set the physical compare value.
* param value: New physical timer compare value.
*/
void gtimer_set_physical_compare_value(rt_uint64_t value)
{
__set_cntp_cval(value);
__asm__ volatile ("isb 0xF":::"memory");
}
/** Get the physical compare value.
* return Physical compare value.
*/
rt_uint64_t gtimer_get_physical_compare_value(void)
{
return(__get_cntp_cval());
}
/** Configure the timer by setting the control value.
* param value: New timer control value.
*/
void gtimer_set_control(rt_uint32_t value)
{
__set_cntp_ctl(value);
__asm__ volatile ("isb 0xF":::"memory");
}
/** Get the control value.
* return Control value.
*/
rt_uint32_t gtimer_get_control(void)
{
return(__get_cntp_ctl());
}
libcpu/arm/cortex-a/gtimer.h
+26
View File
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-03-30 huijie.feng first version
*/
#ifndef __GTIMER_H__
#define __GTIMER_H__
#include <rtdef.h>
void gtimer_set_counter_frequency(rt_uint32_t value);
void gtimer_set_load_value(rt_uint32_t value);
rt_uint32_t gtimer_get_current_value(void);
rt_uint64_t gtimer_get_current_physical_value(void);
void gtimer_set_physical_compare_value(rt_uint64_t value);
rt_uint64_t gtimer_get_physical_compare_value(void);
void gtimer_set_control(rt_uint32_t value);
rt_uint32_t gtimer_get_control(void);
#endif
libcpu/arm/cortex-a/interrupt.c
+159 -1
View File
@@ -83,7 +83,7 @@ void rt_hw_interrupt_umask(int vector)
*/
int rt_hw_interrupt_get_irq(void)
{
return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
return arm_gic_get_active_irq(0);
}
/**
@@ -94,6 +94,150 @@ void rt_hw_interrupt_ack(int vector)
{
arm_gic_ack(0, vector);
}
/**
* This function set interrupt CPU targets.
* @param vector: the interrupt number
* cpu_mask: target cpus mask, one bit for one core
*/
void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask)
{
arm_gic_set_cpu(0, vector, cpu_mask);
}
/**
* This function get interrupt CPU targets.
* @param vector: the interrupt number
* @return target cpus mask, one bit for one core
*/
unsigned int rt_hw_interrupt_get_target_cpus(int vector)
{
return arm_gic_get_target_cpu(0, vector);
}
/**
* This function set interrupt triger mode.
* @param vector: the interrupt number
* mode: interrupt triger mode; 0: level triger, 1: edge triger
*/
void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode)
{
arm_gic_set_configuration(0, vector, mode);
}
/**
* This function get interrupt triger mode.
* @param vector: the interrupt number
* @return interrupt triger mode; 0: level triger, 1: edge triger
*/
unsigned int rt_hw_interrupt_get_triger_mode(int vector)
{
return arm_gic_get_configuration(0, vector);
}
/**
* This function set interrupt pending flag.
* @param vector: the interrupt number
*/
void rt_hw_interrupt_set_pending(int vector)
{
arm_gic_set_pending_irq(0, vector);
}
/**
* This function get interrupt pending flag.
* @param vector: the interrupt number
* @return interrupt pending flag, 0: not pending; 1: pending
*/
unsigned int rt_hw_interrupt_get_pending(int vector)
{
return arm_gic_get_pending_irq(0, vector);
}
/**
* This function clear interrupt pending flag.
* @param vector: the interrupt number
*/
void rt_hw_interrupt_clear_pending(int vector)
{
arm_gic_clear_pending_irq(0, vector);
}
/**
* This function set interrupt priority value.
* @param vector: the interrupt number
* priority: the priority of interrupt to set
*/
void rt_hw_interrupt_set_priority(int vector, unsigned int priority)
{
arm_gic_set_priority(0, vector, priority);
}
/**
* This function get interrupt priority.
* @param vector: the interrupt number
* @return interrupt priority value
*/
unsigned int rt_hw_interrupt_get_priority(int vector)
{
return arm_gic_get_priority(0, vector);
}
/**
* This function set priority masking threshold.
* @param priority: priority masking threshold
*/
void rt_hw_interrupt_set_priority_mask(unsigned int priority)
{
arm_gic_set_interface_prior_mask(0, priority);
}
/**
* This function get priority masking threshold.
* @param none
* @return priority masking threshold
*/
unsigned int rt_hw_interrupt_get_priority_mask(void)
{
return arm_gic_get_interface_prior_mask(0);
}
/**
* This function set priority grouping field split point.
* @param bits: priority grouping field split point
* @return 0: success; -1: failed
*/
int rt_hw_interrupt_set_prior_group_bits(unsigned int bits)
{
int status;
if (bits < 8)
{
arm_gic_set_binary_point(0, (7 - bits));
status = 0;
}
else
{
status = -1;
}
return (status);
}
/**
* This function get priority grouping field split point.
* @param none
* @return priority grouping field split point
*/
unsigned int rt_hw_interrupt_get_prior_group_bits(void)
{
unsigned int bp;
bp = arm_gic_get_binary_point(0) & 0x07;
return (7 - bp);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
@@ -121,3 +265,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
return old_handler;
}
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
{
arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
}
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
}
#endif
libcpu/arm/cortex-a/interrupt.h
+28 -2
View File
@@ -17,9 +17,10 @@
#define INT_IRQ 0x00
#define INT_FIQ 0x01
void rt_hw_vector_init(void);
#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */
#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */
void rt_hw_interrupt_control(int vector, int priority, int route);
void rt_hw_vector_init(void);
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
@@ -28,7 +29,32 @@ void rt_hw_interrupt_umask(int vector);
int rt_hw_interrupt_get_irq(void);
void rt_hw_interrupt_ack(int vector);
void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask);
unsigned int rt_hw_interrupt_get_target_cpus(int vector);
void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode);
unsigned int rt_hw_interrupt_get_triger_mode(int vector);
void rt_hw_interrupt_set_pending(int vector);
unsigned int rt_hw_interrupt_get_pending(int vector);
void rt_hw_interrupt_clear_pending(int vector);
void rt_hw_interrupt_set_priority(int vector, unsigned int priority);
unsigned int rt_hw_interrupt_get_priority(int vector);
void rt_hw_interrupt_set_priority_mask(unsigned int priority);
unsigned int rt_hw_interrupt_get_priority_mask(void);
int rt_hw_interrupt_set_prior_group_bits(unsigned int bits);
unsigned int rt_hw_interrupt_get_prior_group_bits(void);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask);
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
#endif
#endif
src/Kconfig
+8
View File
@@ -116,10 +116,18 @@ config RT_TIMER_THREAD_STACK_SIZE
endif
menu "kservice optimization"
config RT_KSERVICE_USING_STDLIB
bool "Enable kservice to use standard C library"
default n
config RT_KSERVICE_USING_TINY_SIZE
bool "Enable kservice to use tiny size"
default n
endmenu
menuconfig RT_DEBUG
bool "Enable debugging features"
default y
src/kservice.c
+2 -2
View File
@@ -126,7 +126,7 @@ RTM_EXPORT(_rt_errno);
*/
RT_WEAK void *rt_memset(void *s, int c, rt_ubase_t count)
{
#ifdef RT_USING_TINY_SIZE
#ifdef RT_KSERVICE_USING_TINY_SIZE
char *xs = (char *)s;
while (count--)
@@ -210,7 +210,7 @@ RTM_EXPORT(rt_memset);
*/
RT_WEAK void *rt_memcpy(void *dst, const void *src, rt_ubase_t count)
{
#ifdef RT_USING_TINY_SIZE
#ifdef RT_KSERVICE_USING_TINY_SIZE
char *tmp = (char *)dst, *s = (char *)src;
rt_ubase_t len;
tools/file_check.py
+7 -7
View File
@@ -80,9 +80,9 @@ class CheckOut:
def get_new_file(self):
file_list = list()
try:
os.system('git remote add rtt_repo {} 1>/dev/null'.format(self.rtt_repo))
os.system('git fetch rtt_repo 1>/dev/null')
os.system('git reset rtt_repo/{} --soft 1>/dev/null'.format(self.rtt_branch))
os.system('git remote add rtt_repo {}'.format(self.rtt_repo))
os.system('git fetch rtt_repo')
os.system('git reset rtt_repo/{} --soft'.format(self.rtt_branch))
os.system('git status > git.txt')
except Exception as e:
logging.error(e)
@@ -119,7 +119,7 @@ class FormatCheck:
def __check_file(self, file_lines, file_path):
line_num = 1
check_result = False
check_result = True
for line in file_lines:
# check line start
line_start = line.replace(' ', '')
@@ -140,7 +140,7 @@ class FormatCheck:
logging.info("Start to check files format.")
if len(self.file_list) == 0:
logging.warning("There are no files to check license.")
return 0
return True
encoding_check_result = True
format_check_result = True
for file_path in self.file_list:
@@ -156,13 +156,13 @@ class FormatCheck:
else:
continue
if code != 'utf-8':
if code != 'utf-8' and code != 'ascii':
logging.error("[{0}]: encoding not utf-8, please format it.".format(file_path))
encoding_check_result = False
else:
logging.info('[{0}]: encoding check success.'.format(file_path))
with open(file_path, 'r') as f:
with open(file_path, 'r', encoding = "utf-8") as f:
file_lines = f.readlines()
format_check_result = self.__check_file(file_lines, file_path)