[bsp/essemi]增加rsicv芯片bsp：es32vf2264. (#7463)

bsp/essemi/es32vf2264/.ignore_format.yml

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+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- libraries

bsp/essemi/es32vf2264/Kconfig

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+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ES32VF2264
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "drivers/Kconfig"

bsp/essemi/es32vf2264/README.md

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+# ES-PDS-ES32VF2264 开发板 BSP 说明
+标签： EastSoft、国产MCU、RISCV、ES32VF2264
+
+## 1. 简介
+
+本文档为上海东软载波微电子开发团队为 ES-PDS-ES32VF2264 开发板提供的 BSP (板级支持包) 说明。
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+主要内容如下：
+ES-PDS-ES32VF2264 是东软载波微电子官方推出的一款基于 RISCV E902 内核的开发板，最高主频为 72MHz，可满足基础功能测试及高端功能扩展等开发需求。
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：ES32VF2264LT，主频 72MHz，32KB SRAM，256KB FLASH，51 GPIOs
+- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
+- 常用外设
+  - 可调电阻：1个(PC02)
+  - LED：4个，(PC12/PC13/PC14/PA15)
+  - 按键：6个，PD02、PB06、PB07、PB08、PB09、RESET(MRST)
+- 常用接口：GPIO、UART、SPI、I2C、USB
+- 调试接口，ESLinkⅡOB(EastSoft 官方推出的开发工具，自带 CDC 串口功能) SWD 下载
+
+外设支持:
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注**            |
+| :----------- | :----------: | :------------------ |
+| SPI FLASH    |     支持     | SPI0                |
+| **片上外设** | **支持情况** | **备注**            |
+| GPIO         |     支持     | 51 GPIOs            |
+| UART         |     支持     | EUART0/1,CUART0/1/2 |
+| SPI          |     支持     | SPI0/1              |
+| I2C          |     支持     | I2C0/1              |
+| PWM          |     支持     | PWM0/1/2/3          |
+| TIMER        |     支持     | TIMER0/1/2/3/4      |
+| ADC          |     支持     | ADC0                |
+
+### 1.2  注意事项
+
+更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
+
+## 2. 快速上手
+
+本 BSP 为开发者提供 CDK 工程。下面以 CDK 开发环境为例，介绍如何将系统运行起来。
+
+### 硬件连接
+
+使用 ESLinkⅡOB (自带 CDC 串口)或 CKlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 CUART1_TX(PA02)、CUART1_RX(PA03)、GND 接到串口工具上。
+
+### 编译下载
+
+双击 project.uvprojx 文件，打开 CDK 工程，工程默认配置使用ESLinkⅡOB，连接正常后即可编译并下载程序到开发板。
+
+### 运行结果
+
+下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build May  8 2023 19:32:03
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+## 3. 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 cuart1 的功能，如果需使用更多高级功能，可以使用ES-CodeMaker进行更多的芯片配置。然后利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+    a）如果需要使用内核用例，先配置rt-thread内核，然后配置内核用例。
+
+    b）如果需要使用驱动用例：先使能驱动，然后配置驱动用例。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=cdk。
+
+更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+## 4. 联系人信息
+
+- [liuhongyan](https://gitee.com/liuhongyan98) 
+
+## 5. 参考
+
+- [ EastSoft 官网](http://www.essemi.com)
+

bsp/essemi/es32vf2264/SConscript

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+# for module compiling
+import os
+Import('RTT_ROOT')
+
+objs = []
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/essemi/es32vf2264/SConstruct

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+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'project.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/essemi/es32vf2264/applications/SConscript

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+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/essemi/es32vf2264/applications/main.c

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+/*
+ * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2023-05-08     liuhy          the first version
+ */
+
+#include "board.h"
+
+#ifdef ES_RTT_APP_LED_PIN
+#define LED_PIN    ES_RTT_APP_LED_PIN
+#else
+#define LED_PIN    GET_PIN( C , 12 )
+#endif
+
+int main(void)
+{
+    int count = 1;
+    /* set pin mode to output */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}
+

bsp/essemi/es32vf2264/drivers/ES/Kconfig

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+menu "UART Drivers"
+
+    config BSP_USING_EUART0
+        bool "Register EUART0 "
+        select RT_USING_SERIAL
+        default y
+
+    if BSP_USING_EUART0
+        config BSP_EUART0_TX_USING_DMA
+            bool "EUART0 using DMA TX"
+            select RT_SERIAL_USING_DMA
+            default n
+        config BSP_EUART0_RX_USING_DMA
+            bool "EUART0 using DMA RX"
+            select RT_SERIAL_USING_DMA
+            default n
+    endif
+
+    config BSP_USING_EUART1
+        bool "Register EUART1 "
+        select RT_USING_SERIAL
+        default n
+
+    if BSP_USING_EUART1
+        config BSP_EUART1_TX_USING_DMA
+            bool "EUART1 using DMA TX"
+            select RT_SERIAL_USING_DMA
+            default n
+        config BSP_EUART1_RX_USING_DMA
+            bool "EUART1 using DMA RX"
+            select RT_SERIAL_USING_DMA
+            default n
+    endif
+
+    config BSP_USING_CUART0
+        bool "Register CUART0 "
+        select RT_USING_SERIAL
+        default y
+
+    if BSP_USING_CUART0
+        config BSP_CUART0_TX_USING_DMA
+            bool "CUART0 using DMA TX"
+            select RT_SERIAL_USING_DMA
+            default n
+        config BSP_CUART0_RX_USING_DMA
+            bool "CUART0 using DMA RX"
+            select RT_SERIAL_USING_DMA
+            default n
+    endif
+
+    config BSP_USING_CUART1
+        bool "Register CUART1 "
+        select RT_USING_SERIAL
+        default n
+
+    if BSP_USING_CUART1
+        config BSP_CUART1_TX_USING_DMA
+            bool "CUART1 using DMA TX"
+            select RT_SERIAL_USING_DMA
+            default n
+        config BSP_CUART1_RX_USING_DMA
+            bool "CUART1 using DMA RX"
+            select RT_SERIAL_USING_DMA
+            default n
+    endif
+
+    config BSP_USING_CUART2
+        bool "Register CUART2 "
+        select RT_USING_SERIAL
+        default n
+
+    if BSP_USING_CUART2
+        config BSP_CUART2_TX_USING_DMA
+            bool "CUART2 using DMA TX"
+            select RT_SERIAL_USING_DMA
+            default n
+        config BSP_CUART2_RX_USING_DMA
+            bool "CUART2 using DMA RX"
+            select RT_SERIAL_USING_DMA
+            default n
+    endif
+
+endmenu
+
+menu "SPI Drivers"
+
+    config BSP_USING_SPI0
+        bool "Register SPI0 "
+        select RT_USING_SPI
+        select RT_USING_PIN
+        default n
+
+    config BSP_USING_SPI1
+        bool "Register SPI1 "
+        select RT_USING_SPI
+        select RT_USING_PIN
+        default n
+
+endmenu
+
+menu "I2C Drivers"
+
+    config BSP_USING_I2C0
+        bool "Register I2C0 "
+        select RT_USING_I2C
+        default n
+
+    config BSP_USING_I2C1
+        bool "Register I2C1 "
+        select RT_USING_I2C
+        default n
+
+endmenu
+
+menu "ADC Drivers"
+
+    config BSP_USING_ADC0
+        bool "Register ADC0 "
+        select RT_USING_ADC
+        default n
+
+endmenu
+
+menu "HWTIMER Drivers"
+
+    config BSP_USING_AD16C4T0_HWTIMER
+        bool "Register HWTIMER0 "
+        select RT_USING_HWTIMER
+        default n
+
+    config BSP_USING_GP16C4T0_HWTIMER
+        bool "Register HWTIMER1 "
+        select RT_USING_HWTIMER
+        default n
+
+    config BSP_USING_GP16C4T1_HWTIMER
+        bool "Register HWTIMER2 "
+        select RT_USING_HWTIMER
+        default n
+
+    config BSP_USING_GP16C4T2_HWTIMER
+        bool "Register HWTIMER3 "
+        select RT_USING_HWTIMER
+        default n
+
+    config BSP_USING_BS16T0_HWTIMER
+        bool "Register HWTIMER4 "
+        select RT_USING_HWTIMER
+        default n
+
+endmenu
+
+menu "PWM Drivers"
+
+    config BSP_USING_AD16C4T0_PWM
+        bool "Register PWM0 "
+        select RT_USING_PWM
+        default n
+        depends on !BSP_USING_AD16C4T0_HWTIMER
+
+    config BSP_USING_GP16C4T0_PWM
+        bool "Register PWM1 "
+        select RT_USING_PWM
+        default n
+        depends on !BSP_USING_GP16C4T0_HWTIMER
+
+    config BSP_USING_GP16C4T1_PWM
+        bool "Register PWM2 "
+        select RT_USING_PWM
+        default n
+        depends on !BSP_USING_GP16C4T1_HWTIMER
+
+    config BSP_USING_GP16C4T2_PWM
+        bool "Register PWM3 "
+        select RT_USING_PWM
+        default n
+        depends on !BSP_USING_GP16C4T1_HWTIMER
+
+endmenu
+
+menu "PM Drivers"
+
+    config BSP_USING_PM
+        bool "Register PM "
+        select RT_USING_PM
+        default n
+
+endmenu
+
+menu "DMA Drivers"
+    config BSP_USING_DMA0
+        bool "Using DMA0 "
+        select ES_CONF_DMA_ENABLE
+        default n
+endmenu

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_adc.h

@@ -0,0 +1,80 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_ADC_H__
+#define __ES_CONF_INFO_ADC_H__
+
+#include "es_conf_info_map.h"
+
+#include <ald_adc.h>
+
+
+#define ES_C_ADC_CLK_DIV_1     ALD_ADC_CKDIV_1
+#define ES_C_ADC_CLK_DIV_2     ALD_ADC_CKDIV_2
+#define ES_C_ADC_CLK_DIV_4     ALD_ADC_CKDIV_4
+#define ES_C_ADC_CLK_DIV_8     ALD_ADC_CKDIV_8
+#define ES_C_ADC_CLK_DIV_16     ALD_ADC_CKDIV_16
+#define ES_C_ADC_CLK_DIV_32     ALD_ADC_CKDIV_32
+#define ES_C_ADC_CLK_DIV_64     ALD_ADC_CKDIV_64
+#define ES_C_ADC_CLK_DIV_128    ALD_ADC_CKDIV_128
+
+#define ES_C_ADC_ALIGN_RIGHT        ALD_ADC_DATAALIGN_RIGHT
+#define ES_C_ADC_ALIGN_LEFT        ALD_ADC_DATAALIGN_LEFT
+
+#define ES_C_ADC_CONV_BIT_6        ALD_ADC_CONV_BIT_6
+#define ES_C_ADC_CONV_BIT_8        ALD_ADC_CONV_BIT_8
+#define ES_C_ADC_CONV_BIT_10        ALD_ADC_CONV_BIT_10
+#define ES_C_ADC_CONV_BIT_12        ALD_ADC_CONV_BIT_12
+
+#define ES_C_ADC_SAMPLE_TIME_1       ALD_ADC_SAMPLETIME_1
+#define ES_C_ADC_SAMPLE_TIME_2       ALD_ADC_SAMPLETIME_2
+#define ES_C_ADC_SAMPLE_TIME_4       ALD_ADC_SAMPLETIME_4
+#define ES_C_ADC_SAMPLE_TIME_15       ALD_ADC_SAMPLETIME_15
+
+/* ADC 配置 */
+
+/* codes_main */
+
+
+#define ES_ADC0_ALIGN      ES_C_ADC_ALIGN_RIGHT
+#define ES_ADC0_DATA_BIT   ES_C_ADC_CONV_BIT_12
+
+#ifndef  ES_DEVICE_NAME_ADC0
+#define  ES_DEVICE_NAME_ADC0     "adc0"
+#endif
+
+#ifndef  ES_ADC0_CLK_DIV
+#define ES_ADC0_CLK_DIV    ES_C_ADC_CLK_DIV_16
+#endif
+#ifndef  ES_ADC0_ALIGN
+#define ES_ADC0_ALIGN      ES_C_ADC_ALIGN_RIGHT
+#endif
+#ifndef  ES_ADC0_DATA_BIT
+#define ES_ADC0_DATA_BIT   ES_C_ADC_CONV_BIT_12
+#endif
+#ifndef  ES_ADC0_NCH_SAMPLETIME
+#define ES_ADC0_NCH_SAMPLETIME    ES_C_ADC_SAMPLE_TIME_4
+#endif
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_can.h

@@ -0,0 +1,73 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_CAN_H__
+#define __ES_CONF_INFO_CAN_H__
+
+#include "es_conf_info_map.h"
+#include <ald_can.h>
+#include <ald_gpio.h>
+
+
+/*默认的CAN硬件过滤器的编号   0 */
+#define ES_C_CAN_DEFAULT_FILTER_NUMBER   0
+
+/*硬件过滤器，过滤帧类型*/
+#define ES_C_CAN_FILTER_FRAME_TYPE       0
+
+
+#define ES_C_CAN_SJW_NUM_1   CAN_SJW_1
+#define ES_C_CAN_SJW_NUM_2   CAN_SJW_2
+#define ES_C_CAN_SJW_NUM_3   CAN_SJW_3
+#define ES_C_CAN_SJW_NUM_4   CAN_SJW_4
+
+
+
+/* CAN 配置 */
+
+/* codes_main */
+
+
+
+#ifndef  ES_DEVICE_NAME_CAN0
+#define  ES_DEVICE_NAME_CAN0     "can0"
+#endif
+
+#ifndef  ES_CAN0_AUTO_BAN_RE_T
+#define ES_CAN0_AUTO_BAN_RE_T    ES_C_DISABLE
+#endif
+#ifndef  ES_CAN0_SPEED
+#define ES_CAN0_SPEED           1000000
+#endif
+#ifndef  ES_CAN0_SJW
+#define ES_CAN0_SJW             ES_C_CAN_SJW_NUM_4
+#endif
+
+#define ES_CAN0_CONFIG        \
+{                               \
+        ES_CAN0_SPEED,              \
+        RT_CANMSG_BOX_SZ,       \
+        RT_CANSND_BOX_NUM,      \
+        RT_CAN_MODE_NORMAL,     \
+};
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_cmu.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_CMU_H__
+#define __ES_CONF_INFO_CMU_H__
+
+
+/* 时钟树 配置 */
+
+#define  ES_C_DIV_1          ALD_CMU_DIV_1
+#define  ES_C_DIV_2          ALD_CMU_DIV_2
+#define  ES_C_DIV_4          ALD_CMU_DIV_4
+#define  ES_C_DIV_8          ALD_CMU_DIV_8
+#define  ES_C_DIV_16          ALD_CMU_DIV_16
+#define  ES_C_DIV_32          ALD_CMU_DIV_32
+#define  ES_C_DIV_64          ALD_CMU_DIV_64
+#define  ES_C_DIV_128          ALD_CMU_DIV_128
+#define  ES_C_DIV_256          ALD_CMU_DIV_256
+#define  ES_C_DIV_512          ALD_CMU_DIV_512
+#define  ES_C_DIV_1024          ALD_CMU_DIV_1024
+#define  ES_C_DIV_2048          ALD_CMU_DIV_2048
+#define  ES_C_DIV_4096          ALD_CMU_DIV_4096
+
+#define  ES_C_HOSC_DIV_1        ALD_CMU_PLL1_INPUT_HOSC
+#define  ES_C_HOSC_DIV_2        ALD_CMU_PLL1_INPUT_HOSC_2
+#define  ES_C_HOSC_DIV_3        ALD_CMU_PLL1_INPUT_HOSC_3
+#define  ES_C_HOSC_DIV_4        ALD_CMU_PLL1_INPUT_HOSC_4
+#define  ES_C_HOSC_DIV_5        ALD_CMU_PLL1_INPUT_HOSC_5
+#define  ES_C_HOSC_DIV_6        ALD_CMU_PLL1_INPUT_HOSC_6
+#define  ES_C_HRC_DIV_6         ALD_CMU_PLL1_INPUT_HRC_6
+
+
+
+
+
+#define   ES_PLL1_REFER_CLK           ES_C_PLL_REF_HOSC8M
+#define   ES_PLL1_OUT_CLK             ES_C_PLL_OUT_72M
+#define   ES_CMU_PLL1_SAFE_EN         ES_C_DISABLE
+#define   ES_CMU_HOSM_SAFE_EN         ES_C_DISABLE
+#define   ES_CMU_LRC_EN               ES_C_ENABLE
+#define   ES_CMU_HRC4M_EN             ES_C_ENABLE
+#define   ES_CMU_HRC48M_EN            ES_C_ENABLE
+#define   ES_CMU_SYS_DIV              ES_C_DIV_1
+#define   ES_CMU_PCLK_DIV             ES_C_DIV_1
+#define   ES_CMU_UART_BUAND_MAX       XXXXXX
+#define   ES_CMU_UART_BUAND_MIN       XXXXXX
+#define   ES_CMU_SPI_BUAND_MAX        XXXXXX
+#define   ES_CMU_SPI_BUAND_MIN        XXXXXX
+#define   ES_SYS_CLK_SOURSE           CMU_CLOCK_PLL
+#define   ES_SYS_SOURCE_CLK           72000000
+#define   ES_PCLK_CLK                 72000000
+#define   ES_SYS_HCLK_CLK             72000000
+#define   ES_CMU_EXTERN_CLK_HOSC      8000000
+
+
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_dma.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_DMA_H__
+#define __ES_CONF_INFO_DMA_H__
+
+#include "rtconfig.h"
+
+#ifdef BSP_EUART0_TX_USING_DMA
+#endif
+
+#ifdef BSP_CUART2_TX_USING_DMA
+#define   ES_CONF_CUART2_DMA_TX
+#endif
+#ifdef BSP_CUART2_RX_USING_DMA
+#define   ES_CONF_CUART2_DMA_RX
+#endif
+
+
+enum ES_DMA_CHANNELS
+{
+#ifdef ES_CONF_EUART0_DMA_TX
+    ES_EUART0_DMATX_CHANNEL,
+#endif
+#ifdef ES_CONF_EUART0_DMA_RX
+    ES_EUART0_DMARX_CHANNEL,
+#endif
+#ifdef ES_CONF_EUART1_DMA_TX
+    ES_EUART1_DMATX_CHANNEL,
+#endif
+#ifdef ES_CONF_EUART1_DMA_RX
+    ES_EUART1_DMARX_CHANNEL,
+#endif
+#ifdef ES_CONF_CUART0_DMA_TX
+    ES_CUART0_DMATX_CHANNEL,
+#endif
+#ifdef ES_CONF_CUART0_DMA_RX
+    ES_CUART0_DMARX_CHANNEL,
+#endif
+#ifdef ES_CONF_CUART1_DMA_TX
+    ES_CUART1_DMATX_CHANNEL,
+#endif
+#ifdef ES_CONF_CUART1_DMA_RX
+    ES_CUART1_DMARX_CHANNEL,
+#endif
+#ifdef ES_CONF_CUART2_DMA_TX
+    ES_CUART2_DMATX_CHANNEL,
+#endif
+#ifdef ES_CONF_CUART2_DMA_RX
+    ES_CUART2_DMARX_CHANNEL,
+#endif
+#ifdef ES_SPI0_I2S_MODE
+    ES_SPI0_I2S_DMATX_CHANNEL,
+    ES_SPI0_I2S_DMARX_CHANNEL,
+#endif
+#ifdef ES_SPI1_I2S_MODE
+    ES_SPI1_I2S_DMATX_CHANNEL,
+    ES_SPI1_I2S_DMARX_CHANNEL,
+#endif
+    ES_DMA_CHANNEL_NUM
+};
+#define ES_DMA_INVAILD_CHANNEL (ES_DMA_CHANNEL_NUM)
+#define ES_DMA_USER_CHANNEL (ES_DMA_CHANNEL_NUM)
+
+#endif /* __ES_CONF_INFO_DMA_H__ */

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h

@@ -0,0 +1,103 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_HWTIMER_H__
+#define __ES_CONF_INFO_HWTIMER_H__
+
+#include <ald_cmu.h>
+#include <ald_timer.h>
+
+#define ES_C_HWTIMER_MODE_UP         HWTIMER_CNTMODE_UP
+#define ES_C_HWTIMER_MODE_DOWN         HWTIMER_CNTMODE_DW
+
+/* HWTIMER 配置 */
+
+/* codes_main */
+
+
+
+#ifndef  ES_AD16C4T0_HWTIMER_MODE
+#define ES_AD16C4T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+
+#ifndef  ES_GP16C4T0_HWTIMER_MODE
+#define ES_GP16C4T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+#ifndef  ES_GP16C4T1_HWTIMER_MODE
+#define ES_GP16C4T1_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+#ifndef  ES_GP16C4T2_HWTIMER_MODE
+#define ES_GP16C4T2_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+#ifndef  ES_BS16T0_HWTIMER_MODE
+#define ES_BS16T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+#ifndef  ES_BS16T1_HWTIMER_MODE
+#define ES_BS16T1_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+#ifndef  ES_BS16T2_HWTIMER_MODE
+#define ES_BS16T2_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+#ifndef  ES_BS16T3_HWTIMER_MODE
+#define ES_BS16T3_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP
+#endif
+
+
+
+
+#define ES_AD16C4T0_HWTIMER_PRES          1
+#define ES_GP16C4T0_HWTIMER_PRES          1
+#define ES_GP16C2T0_HWTIMER_PRES          1
+#define ES_GP16C2T1_HWTIMER_PRES          1
+#define ES_BS16T0_HWTIMER_PRES          1
+#define ES_BS16T1_HWTIMER_PRES          1
+#define ES_BS16T2_HWTIMER_PRES          1
+#define ES_BS16T3_HWTIMER_PRES          1
+
+#ifndef  ES_DEVICE_NAME_AD16C4T0_HWTIMER
+#define  ES_DEVICE_NAME_AD16C4T0_HWTIMER     "timer0"
+#endif
+#ifndef  ES_DEVICE_NAME_GP16C4T0_HWTIMER
+#define  ES_DEVICE_NAME_GP16C4T0_HWTIMER     "timer1"
+#endif
+#ifndef  ES_DEVICE_NAME_GP16C4T1_HWTIMER
+#define  ES_DEVICE_NAME_GP16C4T1_HWTIMER     "timer2"
+#endif
+#ifndef  ES_DEVICE_NAME_GP16C4T2_HWTIMER
+#define  ES_DEVICE_NAME_GP16C4T2_HWTIMER     "timer3"
+#endif
+#ifndef  ES_DEVICE_NAME_BS16T0_HWTIMER
+#define  ES_DEVICE_NAME_BS16T0_HWTIMER     "timer4"
+#endif
+#ifndef  ES_DEVICE_NAME_BS16T1_HWTIMER
+#define  ES_DEVICE_NAME_BS16T1_HWTIMER     "timer5"
+#endif
+#ifndef  ES_DEVICE_NAME_BS16T2_HWTIMER
+#define  ES_DEVICE_NAME_BS16T2_HWTIMER     "timer6"
+#endif
+#ifndef  ES_DEVICE_NAME_BS16T3_HWTIMER
+#define  ES_DEVICE_NAME_BS16T3_HWTIMER     "timer7"
+#endif
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_i2c.h

@@ -0,0 +1,95 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_I2C_H__
+#define __ES_CONF_INFO_I2C_H__
+
+#include "es_conf_info_map.h"
+#include <ald_i2c.h>
+#include <ald_gpio.h>
+#include <rtdbg.h>
+
+#define ES_C_I2C_STRETCH                 ALD_I2C_NOSTRETCH_DISABLE
+#define ES_C_I2C_NO_STRETCH              ALD_I2C_NOSTRETCH_ENABLE
+
+#define ES_C_I2C_GENERALCALL             ALD_I2C_GENERALCALL_ENABLE
+#define ES_C_I2C_NO_GENERALCALL          ALD_I2C_GENERALCALL_DISABLE
+
+
+#define ES_C_I2C_ADDR_7_MODE                ALD_I2C_ADDR_7BIT
+#define ES_C_I2C_ADDR_10_MODE                ALD_I2C_ADDR_10BIT
+
+
+/* I2C 配置 */
+
+
+
+/* codes_main */
+
+
+
+
+
+#ifndef  ES_DEVICE_NAME_I2C0
+#define  ES_DEVICE_NAME_I2C0     "i2c0"
+#endif
+
+#ifndef  ES_DEVICE_NAME_I2C1
+#define  ES_DEVICE_NAME_I2C1     "i2c1"
+#endif
+
+#ifndef  ES_I2C0_CLK_SPEED
+#define ES_I2C0_CLK_SPEED                100000
+#endif
+#ifndef  ES_I2C0_OWN_ADDR1
+#define ES_I2C0_OWN_ADDR1                0x20
+#endif
+#ifndef  ES_I2C0_GENERAL_CALL
+#define ES_I2C0_GENERAL_CALL             ES_C_I2C_NO_GENERALCALL
+#endif
+#ifndef  ES_I2C0_STRETCH
+#define ES_I2C0_STRETCH               ES_C_I2C_STRETCH
+#endif
+#ifndef ES_I2C0_ADDR_MODE
+#define ES_I2C0_ADDR_MODE                ES_C_I2C_ADDR_7_MODE
+#endif
+
+#ifndef  ES_I2C1_CLK_SPEED
+#define ES_I2C1_CLK_SPEED                100000
+#endif
+#ifndef  ES_I2C1_OWN_ADDR1
+#define ES_I2C1_OWN_ADDR1                0x20
+#endif
+#ifndef  ES_I2C1_GENERAL_CALL
+#define ES_I2C1_GENERAL_CALL             ES_C_I2C_NO_GENERALCALL
+#endif
+#ifndef  ES_I2C1_STRETCH
+#define ES_I2C1_STRETCH               ES_C_I2C_STRETCH
+#endif
+#ifndef ES_I2C1_ADDR_MODE
+#define ES_I2C1_ADDR_MODE                ES_C_I2C_ADDR_7_MODE
+#endif
+
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pm.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_PM_H__
+#define __ES_CONF_INFO_PM_H__
+
+#include <ald_cmu.h>
+#include <ald_pmu.h>
+
+#define ES_PMU_SAVE_LOAD_UART
+
+/* PM 配置 */
+
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pwm.h

@@ -0,0 +1,72 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_PWM_H__
+#define __ES_CONF_INFO_PWM_H__
+
+#include "es_conf_info_map.h"
+#include <ald_cmu.h>
+#include <ald_timer.h>
+#include <ald_gpio.h>
+
+
+#define ES_C_PWM_OC_POL_HIGH   ALD_TIMER_OC_POLARITY_HIGH
+#define ES_C_PWM_OC_POL_LOW    ALD_TIMER_OC_POLARITY_LOW
+
+#define  ES_C_PWM_OC_MODE_PWM1     ALD_TIMER_OC_MODE_PWM1
+#define  ES_C_PWM_OC_MODE_PWM2     ALD_TIMER_OC_MODE_PWM2
+
+
+
+/* PWM 配置 */
+
+
+/* codes_main */
+
+
+
+#define ES_PWM_OC_POLARITY   ES_C_PWM_OC_POL_HIGH
+#define ES_PWM_OC_MODE       ES_C_PWM_OC_MODE_PWM1
+
+#ifndef ES_PWM_OC_POLARITY
+#define ES_PWM_OC_POLARITY   ES_C_PWM_OC_POL_HIGH
+#endif
+#ifndef ES_PWM_OC_MODE
+#define ES_PWM_OC_MODE       ES_C_PWM_OC_MODE_PWM2
+#endif
+
+#ifndef  ES_DEVICE_NAME_AD16C4T0_PWM
+#define  ES_DEVICE_NAME_AD16C4T0_PWM     "pwm0"
+#endif
+#ifndef  ES_DEVICE_NAME_GP16C4T0_PWM
+#define  ES_DEVICE_NAME_GP16C4T0_PWM     "pwm1"
+#endif
+#ifndef  ES_DEVICE_NAME_GP16C2T0_PWM
+#define  ES_DEVICE_NAME_GP16C2T0_PWM     "pwm2"
+#endif
+#ifndef  ES_DEVICE_NAME_GP16C2T1_PWM
+#define  ES_DEVICE_NAME_GP16C2T1_PWM     "pwm3"
+#endif
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_rtc.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_RTC_H__
+#define __ES_CONF_INFO_RTC_H__
+
+#include <ald_cmu.h>
+#include <ald_rtc.h>
+
+/* RTC 配置 */
+
+#define ES_C_RTC_SOURCE_LRC      RTC_SOURCE_LRC
+#define ES_C_RTC_SOURCE_LOSC      RTC_SOURCE_LOSC
+
+#define ES_RTC_CLK_SOURCE        ES_C_RTC_SOURCE_LOSC
+
+
+
+
+/* codes_main */
+
+
+#ifndef  ES_DEVICE_NAME_RTC
+#define  ES_DEVICE_NAME_RTC     "rtc"
+#endif
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_select.h

@@ -0,0 +1,44 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_SELECT_H__
+#define __ES_CONF_INFO_SELECT_H__
+
+
+#define ES_C_ENABLE     1
+#define ES_C_DISABLE    0
+
+
+/* codes_main */
+//#define  ES_USE_ASSERT    ES_C_ENABLE
+
+#ifndef  ES_USE_ASSERT
+#define  ES_USE_ASSERT    ES_C_DISABLE
+#endif
+
+
+#if ES_USE_ASSERT
+    #define USE_ASSERT
+#endif
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_spi.h

@@ -0,0 +1,132 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_SPI_H__
+#define __ES_CONF_INFO_SPI_H__
+
+#include "es_conf_info_map.h"
+#include <ald_spi.h>
+#include <ald_gpio.h>
+#include <ald_cmu.h>
+
+/* SPI 配置 */
+
+#define SPI_BUS_CONFIG(_CONF_,_I_)       do{_CONF_.mode = 0U;                                         \
+                                            _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE |             \
+                                                             ES_SPI##_I_##_WIRE_3_4     |             \
+                                                             ES_SPI##_I_##_CPHA_1_2     |             \
+                                                             ES_SPI##_I_##_CPOL_H_L     |             \
+                                                             ES_SPI##_I_##_CS           |             \
+                                                             ES_SPI##_I_##_M_L_SB          );         \
+                                            _CONF_.data_width = ES_SPI##_I_##_DATA_W;                 \
+                                            _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ;                     \
+                                            }while(0)
+
+
+//    spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
+//    spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
+//    spi_config.mode |= RT_SPI_CPHA;   /* 第二边沿采样 */
+//    spi_config.mode |= RT_SPI_CPOL;   /* 空闲高电平 */
+//    spi_config.mode |= RT_SPI_NO_CS;  /* 禁用软件从机选择管理 */
+//    spi_config.mode |= RT_SPI_MSB;    /* 高位在前 */
+//    spi_config.data_width = 8;        /* 数据长度：8 */
+//    spi_config.max_hz = 2000000;      /* 最快时钟频率 */
+
+#define ES_C_SPI_CLK_POL_HIGH            RT_SPI_CPOL
+#define ES_C_SPI_CLK_POL_LOW             !RT_SPI_CPOL
+
+#define ES_C_SPI_CLK_PHA_FIRST            !RT_SPI_CPHA
+#define ES_C_SPI_CLK_PHA_SECOND           RT_SPI_CPHA
+
+#define ES_C_SPI_MSB                      RT_SPI_MSB
+#define ES_C_SPI_LSB                      RT_SPI_LSB
+
+#define ES_C_SPI_CS_LOW_LEVEL             0
+#define ES_C_SPI_CS_HIGH_LEVEL            1
+
+/* codes_main */
+
+
+#ifndef  ES_DEVICE_NAME_SPI0_BUS
+#define  ES_DEVICE_NAME_SPI0_BUS     "spi0"
+#endif
+#ifndef  ES_DEVICE_NAME_SPI0_DEV0
+#define  ES_DEVICE_NAME_SPI0_DEV0     "spi00"
+#endif
+
+#ifndef  ES_DEVICE_NAME_SPI1_BUS
+#define  ES_DEVICE_NAME_SPI1_BUS     "spi1"
+#endif
+#ifndef  ES_DEVICE_NAME_SPI1_DEV0
+#define  ES_DEVICE_NAME_SPI1_DEV0     "spi10"
+#endif
+
+
+#define ES_SPI_CS_LEVEL               ES_C_SPI_CS_LOW_LEVEL
+
+#ifndef   ES_SPI0_CPHA_1_2
+#define   ES_SPI0_CPHA_1_2               ES_C_SPI_CLK_PHA_SECOND
+#endif
+#ifndef   ES_SPI0_CPOL_H_L
+#define   ES_SPI0_CPOL_H_L               ES_C_SPI_CLK_POL_HIGH
+#endif
+#ifndef   ES_SPI0_M_L_SB
+#define   ES_SPI0_M_L_SB                 RT_SPI_MSB
+#endif
+#ifndef   ES_SPI0_MAX_HZ
+#define   ES_SPI0_MAX_HZ                 2000000
+#endif
+#ifndef   ES_SPI0_NSS_PIN
+#define ES_SPI0_NSS_PIN 0xFFFFFFFF
+#endif
+
+#ifndef   ES_SPI1_CPHA_1_2
+#define   ES_SPI1_CPHA_1_2               ES_C_SPI_CLK_PHA_SECOND
+#endif
+#ifndef   ES_SPI1_CPOL_H_L
+#define   ES_SPI1_CPOL_H_L               ES_C_SPI_CLK_POL_HIGH
+#endif
+#ifndef   ES_SPI1_M_L_SB
+#define   ES_SPI1_M_L_SB                 RT_SPI_MSB
+#endif
+#ifndef   ES_SPI1_MAX_HZ
+#define   ES_SPI1_MAX_HZ                 2000000
+#endif
+#ifndef   ES_SPI1_NSS_PIN
+#define ES_SPI1_NSS_PIN 0xFFFFFFFF
+#endif
+
+
+
+#define   ES_SPI0_MASTER_SLAVE           !RT_SPI_SLAVE
+#define   ES_SPI0_WIRE_3_4               !RT_SPI_3WIRE
+#define   ES_SPI0_CS                     RT_SPI_NO_CS
+#define   ES_SPI0_DATA_W                 8
+
+#define   ES_SPI1_MASTER_SLAVE           !RT_SPI_SLAVE
+#define   ES_SPI1_WIRE_3_4               !RT_SPI_3WIRE
+#define   ES_SPI1_CS                     RT_SPI_NO_CS
+#define   ES_SPI1_DATA_W                 8
+
+
+#endif

bsp/essemi/es32vf2264/drivers/ES/es_conf_info_uart.h

@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_UART_H__
+#define __ES_CONF_INFO_UART_H__
+
+#define ES_C_UART_PARITY_NONE        ALD_UART_PARITY_NONE
+#define ES_C_UART_PARITY_ODD         ALD_UART_PARITY_ODD
+#define ES_C_UART_PARITY_EVEN        ALD_UART_PARITY_EVEN
+
+#define ES_C_UART_STOP_1          ALD_UART_STOP_BITS_1
+#define ES_C_UART_STOP_2          ALD_UART_STOP_BITS_2
+
+
+/* UART 配置 */
+
+
+
+
+#ifndef  ES_DEVICE_NAME_EUART0
+#define  ES_DEVICE_NAME_EUART0     "euart0"
+#endif
+#ifndef  ES_DEVICE_NAME_EUART1
+#define  ES_DEVICE_NAME_EUART1     "euart1"
+#endif
+#ifndef  ES_DEVICE_NAME_CUART0
+#define  ES_DEVICE_NAME_CUART0     "cuart0"
+#endif
+#ifndef  ES_DEVICE_NAME_CUART1
+#define  ES_DEVICE_NAME_CUART1     "cuart1"
+#endif
+#ifndef  ES_DEVICE_NAME_CUART2
+#define  ES_DEVICE_NAME_CUART2     "cuart2"
+#endif
+
+
+#ifndef ES_CONF_CUART0_BAUD_RATE
+#define ES_CONF_CUART0_BAUD_RATE         115200
+#endif
+#ifndef ES_CONF_CUART0_PARITY
+#define ES_CONF_CUART0_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_CUART0_STOP_BITS
+#define ES_CONF_CUART0_STOP_BITS        ES_C_UART_STOP_1
+#endif
+
+#ifndef ES_CONF_CUART1_BAUD_RATE
+#define ES_CONF_CUART1_BAUD_RATE         115200
+#endif
+#ifndef ES_CONF_CUART1_PARITY
+#define ES_CONF_CUART1_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_CUART1_STOP_BITS
+#define ES_CONF_CUART1_STOP_BITS        ES_C_UART_STOP_1
+#endif
+
+#ifndef ES_CONF_CUART0_BAUD_RATE
+#define ES_CONF_CUART0_BAUD_RATE         115200
+#endif
+#ifndef ES_CONF_CUART0_PARITY
+#define ES_CONF_CUART0_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_CUART0_STOP_BITS
+#define ES_CONF_CUART0_STOP_BITS        ES_C_UART_STOP_1
+#endif
+
+#ifndef ES_CONF_CUART1_BAUD_RATE
+#define ES_CONF_CUART1_BAUD_RATE         115200
+#endif
+#ifndef ES_CONF_CUART1_PARITY
+#define ES_CONF_CUART1_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_CUART1_STOP_BITS
+#define ES_CONF_CUART1_STOP_BITS        ES_C_UART_STOP_1
+#endif
+
+#ifndef ES_CONF_CUART2_BAUD_RATE
+#define ES_CONF_CUART2_BAUD_RATE         115200
+#endif
+#ifndef ES_CONF_CUART2_PARITY
+#define ES_CONF_CUART2_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_CUART2_STOP_BITS
+#define ES_CONF_CUART2_STOP_BITS        ES_C_UART_STOP_1
+#endif
+
+
+#define ES_EUART0_CONFIG                         \
+{                                               \
+    ES_CONF_EUART0_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_EUART0_STOP_BITS,                                \
+    ES_CONF_EUART0_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+
+#define ES_EUART1_CONFIG                         \
+{                                               \
+    ES_CONF_EUART1_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_EUART1_STOP_BITS,                                \
+    ES_CONF_EUART1_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+
+#define ES_CUART0_CONFIG                         \
+{                                               \
+    ES_CONF_CUART0_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_CUART0_STOP_BITS,                                \
+    ES_CONF_CUART0_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+
+#define ES_CUART1_CONFIG                         \
+{                                               \
+    ES_CONF_CUART1_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_CUART1_STOP_BITS,                                \
+    ES_CONF_CUART1_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+
+#define ES_CUART2_CONFIG                         \
+{                                               \
+    ES_CONF_CUART2_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_CUART2_STOP_BITS,                                \
+    ES_CONF_CUART2_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+
+
+#endif

bsp/essemi/es32vf2264/drivers/Kconfig

@@ -0,0 +1,39 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+    source "drivers/ES/Kconfig"    
+
+    endmenu
+
+    menu "Onboard Peripheral Drivers"
+
+        config BSP_USING_SPI_FLASH
+            bool "Enable SPI FLASH (W25Q64 spi0)"
+            select BSP_USING_SPI
+            select RT_USING_SFUD
+            select RT_SFUD_USING_SFDP
+            default n
+
+if BSP_USING_SPI_FLASH
+
+        config ES_DEVICE_NAME_SPI_DEV
+            string "The name of spi device (registered)"
+            default "spi00"
+
+        config ES_DEVICE_NAME_SPI_FALSH_DEV
+            string "The name of spi flash device"
+            default "W25Q64"
+endif
+
+    endmenu
+
+    menu "Offboard Peripheral Drivers"
+
+    endmenu
+
+endmenu

bsp/essemi/es32vf2264/drivers/SConscript

@@ -0,0 +1,80 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+objs = []
+
+# add the general drivers.
+src = Split('''
+board.c
+''')
+
+# add gpio code
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \
+    GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \
+    GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \
+    GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5') or \
+    GetDepend('RT_USING_SERIAL'):
+    src += ['drv_uart.c']
+
+# add spi driver code
+if  GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'):
+    src += ['drv_spi.c']
+
+# add i2c driver code
+if  GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
+    src += ['drv_i2c.c']
+
+# add can driver code
+if  GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'):
+    src += ['drv_can.c']
+
+
+# add adc driver code
+if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC'):
+    src += ['drv_adc.c']
+
+# add rtc driver code
+if GetDepend(['BSP_USING_RTC']):
+    src += ['drv_rtc.c']
+
+# add spi flash driver code
+if GetDepend('BSP_USING_SPI_FLASH'):
+    src += ['drv_spiflash.c']
+
+# add hwtimer driver code
+if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or GetDepend('BSP_USING_GP16C4T2_HWTIMER') or \
+    GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \
+    GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'):
+    src += ['drv_hwtimer.c']
+
+# add pwm driver code
+if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \
+    GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM') or GetDepend('BSP_USING_GP16C4T2_PWM') or  \
+    GetDepend('BSP_USING_GP16C2T0__PWM') or GetDepend('BSP_USING_GP16C2T1_PWM') or \
+    GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \
+    GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'):
+    src += ['drv_pwm.c']
+
+# add pm driver code
+if GetDepend(['BSP_USING_PM']):
+    src += ['drv_pm.c']
+CPPPATH = [cwd]
+CPPPATH = CPPPATH + [cwd + '/ES']
+#__SYS_SELECT_H__ 用来规避冲突
+#cdkrepo\toolchain\xtgccelfnewlib\v2.6.1\r\riscv64-unknown-elf\include\sys\select.h
+#components/libc/compilers/common/include/sys/select.h
+CPPDEFINES = ['__SYS_SELECT_H__']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+objs = objs + group
+
+Return('objs')
+

bsp/essemi/es32vf2264/drivers/board.c

@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2022-02-10     Lisq          the first version
+ */
+
+#include "board.h"
+
+/**
+ * @addtogroup es32
+ */
+
+/*@{*/
+
+/*******************************************************************************
+ * Function Name  : SystemClock_Configuration
+ * Description    : Configures the System Clock.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SystemClock_Config(void)
+{
+    /* Configure system clock */
+    ald_cmu_pll_config(ALD_CMU_PLL_INPUT_HOSC8M, ALD_CMU_PLL_OUTPUT_72M);
+    ald_cmu_clock_config(ALD_CMU_CLOCK_PLL, 72000000);
+
+    /* Enable all peripherals */
+    ald_cmu_perh_clock_config(ALD_CMU_PERH_ALL, ENABLE);
+
+    __enable_irq();
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void SysTick_Configuration(void)
+{
+    ald_cmu_init();
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void __attribute__((interrupt)) CLINT_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    csi_coret_clr(ald_cmu_get_clock() / RT_TICK_PER_SECOND, CLINT_IRQn);
+    ald_inc_tick();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void __attribute__((interrupt)) DMA_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    ald_dma_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/*@}*/
+/**
+ * This function will initial ES32F0 board.
+ */
+void rt_hw_board_init(void)
+{
+    csi_vic_set_prio(MACHINE_MODE_SOFT_IRQn, 0);
+    csi_vic_enable_sirq(MACHINE_MODE_SOFT_IRQn);
+    CLIC->CLICINT[MACHINE_MODE_SOFT_IRQn].ATTR |= (3);
+
+    csi_vic_set_prio(DMA_IRQn, 4);
+    csi_vic_enable_sirq(DMA_IRQn);
+
+    csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_DEEP);
+
+    /*System Clock Configuration */
+    SystemClock_Config();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    unsigned int start, now, delta, reload, us_tick;
+    start = CORET->MTIME;
+    reload = CORET->MTIMECMP;
+    us_tick = ald_cmu_get_clock() / 1000000UL;
+    do
+    {
+        now = CORET->MTIME;
+        delta = start > now ? start - now : reload + start - now;
+    }
+    while (delta <  us_tick * us);
+}
+
+void rt_trigger_software_interrupt(void)
+{
+    *((uint8_t*)0xE080100C) = 0x1;
+}
+
+void rt_hw_do_after_save_above(void)
+{
+}

bsp/essemi/es32vf2264/drivers/board.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2022-04-18     liuhy         the first version
+ */
+
+/* <<< Use Configuration Wizard in Context Menu >>>*/
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "ald_conf.h"
+
+#include "rtconfig.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "es_conf_info_cmu.h"
+#include "es_conf_info_dma.h"
+#include "es_conf_info_map.h"
+#include "es_conf_info_gpio.h"
+#include "es_conf_info_adc.h"
+#include "es_conf_info_hwtimer.h"
+#include "es_conf_info_pwm.h"
+#include "es_conf_info_uart.h"
+#include "es_conf_info_spi.h"
+#include "es_conf_info_i2c.h"
+#include "es_conf_info_pm.h"
+
+#define GET_PIN(port,pin)  (ES_PIN_GPIO_##port##_##pin)
+
+extern int __bss_end__;
+#define HEAP_BEGIN  ((void *)&__bss_end__)
+
+#define HEAP_END    (0x20008000)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_adc.c

@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-04-03     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_adc.h"
+
+#ifdef RT_USING_ADC
+
+/* define adc instance */
+
+#ifdef BSP_USING_ADC0
+static struct rt_adc_device _device_adc0;
+#endif /*BSP_USING_ADC0*/
+
+#ifdef BSP_USING_ADC1
+static struct rt_adc_device _device_adc1;
+#endif /*BSP_USING_ADC1*/
+
+/* enable or disable adc */
+static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
+{
+    ald_adc_handle_t *_hadc = (ald_adc_handle_t *)device->parent.user_data;
+
+    RT_ASSERT(device != RT_NULL);
+
+    if (enabled)
+    {
+        ALD_ADC_ENABLE(_hadc); ;
+    }
+    else
+    {
+        ALD_ADC_DISABLE(_hadc);
+    }
+
+    return RT_EOK;
+}
+
+static ald_adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel)
+{
+    ald_adc_channel_t es32f3_channel;
+    ald_gpio_init_t gpio_initstruct;
+
+    /* Initialize ADC pin */
+    gpio_initstruct.mode = ALD_GPIO_MODE_CLOSE;
+    gpio_initstruct.pupd = ALD_GPIO_FLOATING;
+    gpio_initstruct.od = ALD_GPIO_PUSH_PULL;
+    gpio_initstruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL;
+    gpio_initstruct.flt  = ALD_GPIO_FILTER_DISABLE;
+    gpio_initstruct.type = ALD_GPIO_TYPE_CMOS;
+    gpio_initstruct.func = ALD_GPIO_FUNC_0;
+
+    /* select gpio pin as adc function */
+    switch (channel)
+    {
+    case  0:
+        es32f3_channel = ALD_ADC_CHANNEL_0;
+        ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct);
+        break;
+    case  1:
+        es32f3_channel = ALD_ADC_CHANNEL_1;
+        ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct);
+        break;
+    case  2:
+        es32f3_channel = ALD_ADC_CHANNEL_2;
+        ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct);
+        break;
+    case  3:
+        es32f3_channel = ALD_ADC_CHANNEL_3;
+        ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct);
+        break;
+    case  4:
+        es32f3_channel = ALD_ADC_CHANNEL_4;
+        ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct);
+        break;
+    case  5:
+        es32f3_channel = ALD_ADC_CHANNEL_5;
+        ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct);
+        break;
+    case  6:
+        es32f3_channel = ALD_ADC_CHANNEL_6;
+        ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct);
+        break;
+    case  7:
+        es32f3_channel = ALD_ADC_CHANNEL_7;
+        ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct);
+        break;
+    case  8:
+        es32f3_channel = ALD_ADC_CHANNEL_8;
+        ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct);
+        break;
+    case  9:
+        es32f3_channel = ALD_ADC_CHANNEL_9;
+        ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct);
+        break;
+    case 10:
+        es32f3_channel = ALD_ADC_CHANNEL_10;
+        ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct);
+        break;
+    case 11:
+        es32f3_channel = ALD_ADC_CHANNEL_11;
+        ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct);
+        break;
+    case 12:
+        es32f3_channel = ALD_ADC_CHANNEL_12;
+        ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct);
+        break;
+    case 13:
+        es32f3_channel = ALD_ADC_CHANNEL_13;
+        ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct);
+        break;
+    case 14:
+        es32f3_channel = ALD_ADC_CHANNEL_14;
+        ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct);
+        break;
+    case 15:
+        es32f3_channel = ALD_ADC_CHANNEL_15;
+        ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct);
+        break;
+
+    default:
+        break;
+    }
+
+    return es32f3_channel;
+}
+
+static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
+{
+    ald_adc_handle_t *_hadc = (ald_adc_handle_t *)device->parent.user_data;
+    ald_adc_nch_conf_t nm_config;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    /* config adc channel */
+    nm_config.ch       = es32f3_adc_get_channel(channel);
+    nm_config.idx          = ALD_ADC_NCH_IDX_1;
+    nm_config.samp = ES_ADC0_NCH_SAMPLETIME;
+    ald_adc_normal_channel_config(_hadc, &nm_config);
+
+    ald_adc_normal_start(_hadc);
+
+    if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == ALD_OK)
+        *value = ald_adc_normal_get_value(_hadc);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops es32f3_adc_ops =
+{
+    es32f3_adc_enabled,
+    es32f3_get_adc_value,
+};
+
+int rt_hw_adc_init(void)
+{
+    ald_adc_handle_t _h_adc;
+
+    /* adc function initialization */
+    _h_adc.init.scan = ENABLE;
+    _h_adc.init.cont = DISABLE;
+    _h_adc.init.disc = ALD_ADC_ALL_DISABLE;
+    _h_adc.init.disc_nr = ALD_ADC_DISC_NR_1;
+    _h_adc.init.data_bit   = ALD_ADC_CONV_BIT_12;
+    _h_adc.init.div        = ALD_ADC_CKDIV_16;
+    _h_adc.init.nch_nr = ALD_ADC_NCH_NR_1;
+    _h_adc.init.nche_sel = ALD_ADC_NCHESEL_MODE_ALL;
+    _h_adc.init.cont = DISABLE;
+    _h_adc.init.n_ref = ALD_ADC_NEG_REF_VSS;
+    _h_adc.init.p_ref = ALD_ADC_POS_REF_VDD;
+
+#ifdef BSP_USING_ADC0
+
+    static ald_adc_handle_t _h_adc0;
+
+    _h_adc0.init = _h_adc.init;
+
+    _h_adc0.perh = ADC;
+    _h_adc0.init.align = ES_ADC0_ALIGN;
+    _h_adc0.init.data_bit = ES_ADC0_DATA_BIT;
+    _h_adc0.init.div = ES_ADC0_CLK_DIV;
+    ALD_ADC_ENABLE(&_h_adc0);
+    ALD_ADC_DISABLE(&_h_adc0);
+    ald_adc_init(&_h_adc0);
+
+    rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f3_adc_ops, &_h_adc0);
+
+#endif /*BSP_USING_ADC0*/
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_adc_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_adc.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-04-03     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_ADC_H__
+#define DRV_ADC_H__
+
+#include "es_conf_info_adc.h"
+
+int rt_hw_adc_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_gpio.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+#include "board.h"
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_hwtimer.c

@@ -0,0 +1,354 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-3-19      wangyq       the first version
+ * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_hwtimer.h>
+#include <board.h>
+
+
+#ifdef RT_USING_HWTIMER
+
+struct es32f3_hwtimer_dev
+{
+    rt_hwtimer_t parent;
+    ald_timer_handle_t *hwtimer_periph;
+    IRQn_Type IRQn;
+};
+
+#ifdef BSP_USING_AD16C4T0_HWTIMER
+static struct es32f3_hwtimer_dev ad16c4t0_hwtimer;
+
+static struct rt_hwtimer_info ad16c4t0_info =
+{
+    ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
+    (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_AD16C4T0_HWTIMER_MODE
+};
+
+void __attribute__((interrupt)) AD16C4T_Handler(void)
+{
+    rt_interrupt_enter();
+    ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, ALD_TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent);
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_GP16C4T0_HWTIMER
+
+static struct es32f3_hwtimer_dev gp16c4t0_hwtimer;
+
+static struct rt_hwtimer_info gp16c4t0_info =
+{
+    ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
+    (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_GP16C4T0_HWTIMER_MODE
+};
+
+void __attribute__((interrupt)) GPTIMB0_Handler(void)
+{
+    rt_interrupt_enter();
+    ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent);
+    rt_interrupt_leave();
+}
+
+#endif
+#ifdef BSP_USING_GP16C4T1_HWTIMER
+
+static struct es32f3_hwtimer_dev gp16c4t1_hwtimer;
+
+static struct rt_hwtimer_info gp16c4t1_info =
+{
+    ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
+    (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_GP16C4T1_HWTIMER_MODE
+};
+
+void __attribute__((interrupt)) GPTIMB1_Handler(void)
+{
+    rt_interrupt_enter();
+    ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent);
+    rt_interrupt_leave();
+}
+
+#endif
+#ifdef BSP_USING_GP16C4T1_HWTIMER
+
+static struct es32f3_hwtimer_dev gp16c4t1_hwtimer;
+
+static struct rt_hwtimer_info gp16c4t1_info =
+{
+    ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
+    (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_GP16C4T1_HWTIMER_MODE
+};
+
+void __attribute__((interrupt)) GPTIMB2_Handler(void)
+{
+    rt_interrupt_enter();
+    ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent);
+    rt_interrupt_leave();
+}
+
+#endif
+#ifdef BSP_USING_BS16T0_HWTIMER
+
+static struct es32f3_hwtimer_dev bs16t0_hwtimer;
+
+static struct rt_hwtimer_info bs16t0_info =
+{
+    ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
+    (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_BS16T0_HWTIMER_MODE
+};
+
+void __attribute__((interrupt)) BSTIM0_Handler(void)
+{
+    rt_interrupt_enter();
+    ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&bs16t0_hwtimer.parent);
+    rt_interrupt_leave();
+}
+
+#endif
+
+static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
+
+    struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    if (1 == state)
+    {
+        ald_timer_base_init(hwtimer->hwtimer_periph);
+        ald_timer_interrupt_config(hwtimer->hwtimer_periph, ALD_TIMER_IT_UPDATE, ENABLE);
+        csi_vic_enable_sirq(hwtimer->IRQn);
+    }
+
+    hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
+    hwtimer_info->maxfreq = hwtimer->parent.freq;
+    hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF;
+
+}
+
+static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer,
+                                     rt_uint32_t cnt,
+                                     rt_hwtimer_mode_t mode)
+{
+    struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
+    ald_timer_base_start(hwtimer->hwtimer_periph);
+
+    return RT_EOK;
+}
+
+static void es32f3_hwtimer_stop(rt_hwtimer_t *timer)
+{
+    struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    ald_timer_base_stop(hwtimer->hwtimer_periph);
+}
+
+static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer)
+{
+    struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
+    uint32_t hwtimer_count = 0;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT);
+
+    return hwtimer_count;
+}
+
+static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer,
+                                       rt_uint32_t cmd,
+                                       void *args)
+{
+    rt_err_t ret = RT_EOK;
+    rt_uint32_t freq = 0;
+    struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+        freq = *(rt_uint32_t *)args;
+
+        ret = -RT_ERROR;
+
+        if(freq)
+        {
+            double temp,target;
+            temp = (double)ald_cmu_get_pclk_clock();
+            target = temp/freq;
+
+            if(target < 0x10001)   /*最大分频 = max(PRES)+1*/
+            {
+                temp = target - (int)(target);
+
+                if((temp > 0.998)&&(target < 0x10000))
+                {
+                    hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target;
+                    ret = RT_EOK;
+                }
+                if((temp < 0.002)&&(target >= 0x1))
+                {
+                    hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1;
+                    ret = RT_EOK;
+                }
+
+            }
+
+            if(ret == RT_EOK)     /*更新信息*/
+                hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
+
+        }
+
+        break;
+
+    case HWTIMER_CTRL_STOP:
+        ald_timer_base_stop(hwtimer->hwtimer_periph);
+        break;
+
+    default:
+        ret = RT_EINVAL;
+        break;
+    }
+
+    return ret;
+}
+
+static struct rt_hwtimer_ops es32f3_hwtimer_ops =
+{
+    es32f3_hwtimer_init,
+    es32f3_hwtimer_start,
+    es32f3_hwtimer_stop,
+    es32f3_hwtimer_count_get,
+    es32f3_hwtimer_control
+};
+
+int rt_hw_hwtimer_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+#ifdef BSP_USING_AD16C4T0_HWTIMER
+    static ald_timer_handle_t ad16c4t0_hwtimer_periph;
+
+    ad16c4t0_hwtimer_periph.perh = AD16C4T;
+    ad16c4t0_hwtimer.IRQn = AD16C4T_IRQn;
+
+    ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1;
+    ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? ALD_TIMER_CNT_MODE_UP : ALD_TIMER_CNT_MODE_DOWN;
+    ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph;
+
+    ad16c4t0_hwtimer.parent.info = &ad16c4t0_info;
+    ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer);
+#endif
+
+#ifdef BSP_USING_GP16C4T0_HWTIMER
+    static timer_handle_t gp16c4t0_hwtimer_periph;
+
+    gp16c4t0_hwtimer_periph.perh = GP16C4T0;
+    gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn;
+
+    gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1;
+    gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph;
+
+    gp16c4t0_hwtimer.parent.info = &gp16c4t0_info;
+    gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer);
+#endif
+
+#ifdef BSP_USING_GP16C4T1_HWTIMER
+    static timer_handle_t gp16c4t1_hwtimer_periph;
+
+    gp16c4t1_hwtimer_periph.perh = GP16C4T1;
+    gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn;
+
+    gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1;
+    gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph;
+
+    gp16c4t1_hwtimer.parent.info = &gp16c4t1_info;
+    gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer);
+#endif
+
+#ifdef BSP_USING_GP16C4T2_HWTIMER
+    static timer_handle_t gp16c4t2_hwtimer_periph;
+
+    gp16c4t2_hwtimer_periph.perh = GP16C4T2;
+    gp16c4t2_hwtimer.IRQn = GP16C4T2_IRQn;
+
+    gp16c4t2_hwtimer_periph.init.prescaler = ES_GP16C4T2_HWTIMER_PRES - 1;
+    gp16c4t2_hwtimer_periph.init.mode = ( ES_GP16C4T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    gp16c4t2_hwtimer.hwtimer_periph = &gp16c4t2_hwtimer_periph;
+
+    gp16c4t2_hwtimer.parent.info = &gp16c4t2_info;
+    gp16c4t2_hwtimer.parent.ops = &es32f3_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&gp16c4t2_hwtimer.parent, ES_DEVICE_NAME_GP16C4T2_HWTIMER, &gp16c4t2_hwtimer);
+#endif
+
+#ifdef BSP_USING_BS16T0_HWTIMER
+    static timer_handle_t bs16t0_hwtimer_periph;
+
+    bs16t0_hwtimer_periph.perh = BS16T0;
+    bs16t0_hwtimer.IRQn = BS16T0_IRQn;
+
+    bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1;
+    bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph;
+
+    bs16t0_hwtimer.parent.info = &bs16t0_info;
+    bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer);
+#endif
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_hwtimer.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-3-19      wangyq       the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_HWTIMER_H__
+#define DRV_HWTIMER_H__
+
+#include "es_conf_info_hwtimer.h"
+int rt_hw_hwtimer_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_i2c.c

@@ -0,0 +1,347 @@
+/*
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-11-01     wangyq        update libraries
+ * 2020-01-14     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_i2c.h"
+
+
+#ifdef RT_USING_I2C
+
+#define TIMEOUT 0x0FFF
+
+/* I2C struct definition */
+#ifdef BSP_USING_I2C0
+    static ald_i2c_handle_t _h_i2c0;
+#endif
+
+#ifdef BSP_USING_I2C1
+    static i2c_handle_t _h_i2c1;
+#endif
+
+static void _i2c_init(void)
+{
+    ald_gpio_init_t gpio_instruct;
+
+    /* Initialize I2C Pin */
+    gpio_instruct.mode = ALD_GPIO_MODE_OUTPUT;
+    gpio_instruct.od = ALD_GPIO_OPEN_DRAIN;
+    gpio_instruct.pupd = ALD_GPIO_PUSH_UP;
+    gpio_instruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL;
+    gpio_instruct.flt  = ALD_GPIO_FILTER_DISABLE;
+    gpio_instruct.type = ALD_GPIO_TYPE_CMOS;
+
+
+#ifdef BSP_USING_I2C0
+
+#if  defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN)
+    gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC;
+    ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if  defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN)
+    gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC;
+    ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct);
+#endif
+
+    /* Initialize I2C Function */
+    _h_i2c0.perh = I2C0;
+    _h_i2c0.init.module       = ALD_I2C_MODULE_MASTER;
+    _h_i2c0.init.clk_speed    = ES_I2C0_CLK_SPEED;
+    _h_i2c0.init.own_addr1    = ES_I2C0_OWN_ADDR1;
+    _h_i2c0.init.addr_mode    = ES_I2C0_ADDR_MODE;
+    _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL;
+    _h_i2c0.init.no_stretch   = ES_I2C0_STRETCH;
+
+    ald_i2c_reset(&_h_i2c0);
+    ald_i2c_init(&_h_i2c0);
+
+#endif
+
+#ifdef BSP_USING_I2C1
+
+#if  defined(ES_I2C1_SCL_GPIO_FUNC)&&defined(ES_I2C1_SCL_GPIO_PORT)&&defined(ES_I2C1_SCL_GPIO_PIN)
+    gpio_instruct.func = ES_I2C1_SCL_GPIO_FUNC;
+    ald_gpio_init(ES_I2C1_SCL_GPIO_PORT, ES_I2C1_SCL_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if  defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN)
+    gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC;
+    ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct);
+#endif
+
+    /* Initialize i2c function */
+    _h_i2c1.perh = I2C1;
+    _h_i2c1.init.module       = I2C_MODULE_MASTER;
+    _h_i2c1.init.clk_speed    = ES_I2C1_CLK_SPEED;
+    _h_i2c1.init.own_addr1    = ES_I2C1_OWN_ADDR1;
+    _h_i2c1.init.addr_mode    = ES_I2C1_ADDR_MODE;
+    _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL;
+    _h_i2c1.init.no_stretch   = ES_I2C1_STRETCH;
+
+    ald_i2c_reset(&_h_i2c1);
+    ald_i2c_init(&_h_i2c1);
+
+#endif
+}
+#define _I2C_NO_START 0x1
+#define _I2C_NO_STOP  0x2
+int _i2c_master_req(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout,uint32_t req_write)
+{
+    if (hperh->init.addr_mode == ALD_I2C_ADDR_7BIT) {
+        CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
+    }
+    else {
+        SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
+    }
+
+    MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS);
+    if (req_write)
+        CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
+    else
+        SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
+
+    return ALD_OK;
+}
+int _i2c_wait_flag(ald_i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
+{
+    uint32_t tickstart = 0;
+
+        tickstart = ald_get_tick();
+            while (ALD_I2C_GET_FLAG(hperh, flag) == status) {
+                if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
+                    hperh->error_code |= ALD_I2C_ERROR_TIMEOUT;
+                    return TIMEOUT;
+                }
+            }
+
+        return ALD_OK;
+}
+int _i2c_wait_txe(ald_i2c_handle_t *hperh, uint32_t timeout)
+{
+    uint32_t tickstart = ald_get_tick();
+
+    while (ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_TXE) == RESET) {
+        if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_ARLO)) {
+            hperh->error_code |= ALD_I2C_ERROR_ARLO;
+            return ALD_ERROR;
+        }
+
+        if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_NACK) == SET) {
+            hperh->error_code |= ALD_I2C_ERROR_AF;
+            return ALD_ERROR;
+        }
+
+        if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) {
+            hperh->error_code |= ALD_I2C_ERROR_TIMEOUT;
+            return ALD_ERROR;
+        }
+    }
+
+    return ALD_OK;
+}
+int _i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
+                                 uint32_t size, uint32_t timeout,uint32_t flag)
+{
+    if (hperh->state != ALD_I2C_STATE_READY)
+        return ALD_BUSY;
+
+    if ((buf == NULL) || (size == 0))
+        return  ALD_ERROR;
+    if ((flag&_I2C_NO_START)==0x0) //NOSTART==0
+    {
+        if (_i2c_wait_flag(hperh, ALD_I2C_STAT_BUSY, SET, 100) != ALD_OK)
+            return ALD_BUSY;
+        _i2c_master_req(hperh, dev_addr, timeout,1);
+    }
+    assert_param(IS_I2C_TYPE(hperh->perh));
+    __LOCK(hperh);
+
+    hperh->state      = ALD_I2C_STATE_BUSY_TX;
+    hperh->mode       = ALD_I2C_MODE_MASTER;
+    hperh->error_code = ALD_I2C_ERROR_NONE;
+    hperh->p_buff     = buf;
+    hperh->xfer_size  = size;
+    hperh->xfer_count = 0;
+
+    if ((flag&_I2C_NO_STOP)!=0)  //NOSTOP==1
+        SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
+    else
+        CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
+
+    if (size <= 0xFF) {
+        MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
+    }
+    else {
+        MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
+        SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
+    }
+
+    if ((flag&_I2C_NO_START)==0x0)
+        SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
+
+    while (size > 0) {
+        hperh->perh->TXDATA  = (*buf++);
+        size--;
+        hperh->xfer_count++;
+
+        if (_i2c_wait_txe(hperh, timeout) != ALD_OK)
+            goto ERROR;
+
+        if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
+            if (_i2c_wait_flag(hperh, ALD_I2C_STAT_TCR, RESET, 10) == ALD_OK) {
+                if (size > 0xFF) {
+                    MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
+                }
+                else {
+                    MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
+                    if ((flag&_I2C_NO_STOP)==0)
+                        CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
+                }
+            }
+            else {
+                goto ERROR;
+            }
+        }
+    }
+
+    if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET)
+        goto SUCCESS;
+
+    if ((flag&_I2C_NO_STOP)!=0&&_i2c_wait_flag(hperh, ALD_I2C_STAT_TCR, RESET, 10) == ALD_OK)
+    {
+        goto SUCCESS;
+    }
+
+    if (_i2c_wait_flag(hperh, ALD_I2C_STAT_TC, RESET, 10) == ALD_OK) {
+        if ((flag&_I2C_NO_STOP)==0x0)
+            SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
+        goto SUCCESS;
+    }
+    else {
+        goto ERROR;
+    }
+
+ERROR:
+    SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
+    hperh->state = ALD_I2C_STATE_READY;
+    hperh->mode  = ALD_I2C_MODE_NONE;
+    __UNLOCK(hperh);
+
+    return ALD_ERROR;
+
+SUCCESS:
+    hperh->state = ALD_I2C_STATE_READY;
+    hperh->mode  = ALD_I2C_MODE_NONE;
+    __UNLOCK(hperh);
+
+    return ALD_OK;
+}
+
+static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    rt_uint32_t i;
+    rt_err_t ret = RT_ERROR;
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        if (msg->flags & RT_I2C_RD)
+        {
+            if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                LOG_E("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+        else
+        {
+            uint32_t f=((msg->flags&RT_I2C_NO_START)?0x1:0)|((msg->flags&RT_I2C_NO_STOP)?0x2:0);
+
+            if (_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT,f) != 0)
+            {
+                LOG_E("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+    }
+
+    ret = i;
+
+out:
+    //LOG_E("send stop condition\n");
+
+    return ret;
+}
+
+const struct rt_i2c_bus_device_ops es32f3_i2c_ops =
+{
+    es32f3_master_xfer,
+    RT_NULL,
+    RT_NULL,
+};
+
+int rt_hw_i2c_init(void)
+{
+    int result = RT_EOK;
+
+    _i2c_init();
+
+#ifdef BSP_USING_I2C0
+    /* define i2c Instance */
+    static struct rt_i2c_bus_device _i2c_device0;
+    rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device));
+
+    _i2c_device0.ops = &es32f3_i2c_ops;
+    _i2c_device0.priv = &_h_i2c0;
+    result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* define i2c Instance */
+    static struct rt_i2c_bus_device _i2c_device1;
+    rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device));
+
+    _i2c_device1.ops = &es32f3_i2c_ops;
+    _i2c_device1.priv = &_h_i2c1;
+    rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_i2c.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_I2C_H__
+#define DRV_I2C_H__
+
+#include "es_conf_info_i2c.h"
+
+int rt_hw_i2c_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_pm.c

@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-12-15     liuhy        the first version
+ */
+
+#include "drv_pm.h"
+
+#ifdef RT_USING_PM
+
+/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/
+static void sleep(struct rt_pm *pm, uint8_t mode)
+{
+    rt_base_t level;
+    level = rt_hw_interrupt_disable();
+    rt_hw_interrupt_enable(0x88);
+
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_NONE:
+        break;
+
+    case PM_SLEEP_MODE_IDLE:
+        break;
+
+    case PM_SLEEP_MODE_LIGHT:
+        ald_pmu_stop_enter();
+        break;
+
+    case PM_SLEEP_MODE_DEEP:
+        ald_pmu_stop_enter();
+        break;
+
+    case PM_SLEEP_MODE_STANDBY:
+        ald_pmu_stop_enter();
+        break;
+
+    case PM_SLEEP_MODE_SHUTDOWN:
+        ald_pmu_stop_enter();
+        break;
+
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+
+    rt_hw_interrupt_enable(level);
+}
+
+static void run(struct rt_pm *pm, uint8_t mode)
+{
+    static uint8_t last_mode;
+
+    if (mode == last_mode)
+        return;
+    last_mode = mode;
+
+    switch (mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+    case PM_RUN_MODE_MEDIUM_SPEED:
+    case PM_RUN_MODE_LOW_SPEED:
+    default:
+        break;
+    }
+}
+
+/**
+ * This function caculate the PM tick from OS tick
+ *
+ * @param tick OS tick
+ *
+ * @return the PM tick
+ */
+static rt_tick_t es32f3_pm_tick_from_os_tick(rt_tick_t tick)
+{
+    rt_uint32_t freq = 1;
+
+    return (freq * tick / RT_TICK_PER_SECOND);
+}
+
+/**
+ * This function caculate the OS tick from PM tick
+ *
+ * @param tick PM tick
+ *
+ * @return the OS tick
+ */
+static rt_tick_t es32f3_os_tick_from_pm_tick(rt_uint32_t tick)
+{
+    static rt_uint32_t os_tick_remain = 0;
+    rt_uint32_t ret, freq;
+
+    freq = 1;
+    ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq;
+
+    os_tick_remain += (tick * RT_TICK_PER_SECOND);
+    os_tick_remain %= freq;
+
+    return ret;
+}
+
+/**
+ * This function start the timer of pm
+ *
+ * @param pm Pointer to power manage structure
+ * @param timeout How many OS Ticks that MCU can sleep
+ */
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
+{
+    RT_ASSERT(pm != RT_NULL);
+    RT_ASSERT(timeout > 0);
+
+    if (timeout != RT_TICK_MAX)
+    {
+        /* Convert OS Tick to pmtimer timeout value */
+        timeout = es32f3_pm_tick_from_os_tick(timeout);
+        /* MAX 0xFFFF */
+        if (timeout > 0xFFFF)
+        {
+            timeout = 0xFFFF;
+        }
+    }
+}
+
+/**
+ * This function stop the timer of pm
+ *
+ * @param pm Pointer to power manage structure
+ */
+static void pm_timer_stop(struct rt_pm *pm)
+{
+    RT_ASSERT(pm != RT_NULL);
+}
+
+/**
+ * This function calculate how many OS Ticks that MCU have suspended
+ *
+ * @param pm Pointer to power manage structure
+ *
+ * @return OS Ticks
+ */
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm)
+{
+    rt_uint32_t timer_tick;
+
+    RT_ASSERT(pm != RT_NULL);
+
+    timer_tick = 1;
+
+    return es32f3_os_tick_from_pm_tick(timer_tick);
+}
+
+/**
+ * This function initialize the power manager
+ */
+int drv_pm_hw_init(void)
+{
+    static const struct rt_pm_ops _ops =
+    {
+        sleep,
+        run,
+        pm_timer_start,
+        pm_timer_stop,
+        pm_timer_get_tick
+    };
+
+    rt_uint8_t timer_mask = 0;
+
+    /* initialize timer mask */
+    timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
+
+    /* initialize system pm module */
+    rt_system_pm_init(&_ops, timer_mask, RT_NULL);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(drv_pm_hw_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_pm.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-04-01     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_PM_H__
+#define DRV_PM_H__
+
+#include <rthw.h>
+#include <board.h>
+#include <rtdevice.h>
+#include "es_conf_info_pm.h"
+#include <string.h>
+
+int rt_hw_pm_init(void);
+
+extern void save_register(void *p_head,uint32_t size,void *p_save);
+
+extern void load_register(void *p_head,uint32_t size,void *p_load);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_pwm.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-11     wangyq       the first version
+ * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+#include "es_conf_info_pwm.h"
+
+
+#ifdef RT_USING_PWM
+
+static void pwm_set_duty(ald_timer_handle_t *timer_initstruct, ald_timer_channel_t ch, uint32_t ns)
+{
+    uint64_t tmp = (uint64_t)ald_cmu_get_pclk_clock() * ns / 1000000000 /
+                   (timer_initstruct->init.prescaler + 1);
+
+    if (ch == ALD_TIMER_CHANNEL_1)
+        WRITE_REG(timer_initstruct->perh->CCVAL1, (uint32_t)tmp);
+    else if (ch == ALD_TIMER_CHANNEL_2)
+        WRITE_REG(timer_initstruct->perh->CCVAL2, (uint32_t)tmp);
+    else if (ch == ALD_TIMER_CHANNEL_3)
+        WRITE_REG(timer_initstruct->perh->CCVAL3, (uint32_t)tmp);
+    else if (ch == ALD_TIMER_CHANNEL_4)
+        WRITE_REG(timer_initstruct->perh->CCVAL4, (uint32_t)tmp);
+}
+
+static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    rt_err_t ret = RT_EOK;
+    uint64_t _arr,bus_speed,tmp;
+    uint32_t _maxcnt,_ccep_ch_en = 0U;
+    ald_timer_channel_t pwm_channel;
+    ald_timer_oc_init_t tim_ocinit;
+    ald_timer_handle_t *timer_initstruct = (ald_timer_handle_t *)device->parent.user_data;
+    struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
+
+    RT_ASSERT(timer_initstruct != RT_NULL);
+
+
+    /* select pwm output channel */
+    if (1 == cfg->channel)
+    {
+        pwm_channel = ALD_TIMER_CHANNEL_1;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK;
+    }
+    else if (2 == cfg->channel)
+    {
+        pwm_channel = ALD_TIMER_CHANNEL_2;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK;
+    }
+    else if (3 == cfg->channel)
+    {
+        pwm_channel = ALD_TIMER_CHANNEL_3;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK;
+    }
+    else if (4 == cfg->channel)
+    {
+        pwm_channel = ALD_TIMER_CHANNEL_4;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK;
+    }
+    else
+        return RT_EINVAL;
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        ald_timer_pwm_start(timer_initstruct, pwm_channel);
+        break;
+
+    case PWM_CMD_DISABLE:
+        ald_timer_pwm_stop(timer_initstruct, pwm_channel);
+        break;
+
+    case PWM_CMD_SET:
+
+          /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/
+        if(!_ccep_ch_en)
+        {
+         tim_ocinit.oc_mode      = ES_PWM_OC_MODE;
+         tim_ocinit.oc_polarity  = ES_PWM_OC_POLARITY;
+         tim_ocinit.oc_fast_en   = DISABLE;
+         tim_ocinit.ocn_polarity = ALD_TIMER_OCN_POLARITY_HIGH;
+         tim_ocinit.ocn_idle     = ALD_TIMER_OCN_IDLE_RESET;
+         tim_ocinit.oc_idle      = ALD_TIMER_OC_IDLE_RESET;
+
+            ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
+        }
+
+        bus_speed = (uint64_t)ald_cmu_get_pclk_clock();
+
+        /*判断外设的计数器最大值*/
+#ifdef ES32F36xx
+        if((timer_initstruct->perh == GP32C4T0)||(timer_initstruct->perh == GP32C4T1))
+        {
+            _maxcnt = 0xFFFFFFFF;
+        }
+        else _maxcnt = 0xFFFF;
+#else
+        _maxcnt = 0xFFFF;
+#endif
+
+        /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */
+        tmp = bus_speed * (cfg->period)/1000000000/_maxcnt;
+        timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ;    /*bus_speed < 500000000*/
+
+        /* count registers max , auto adjust prescaler */
+        do
+        {
+          _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler);
+
+        }
+        while (_arr > _maxcnt);
+
+        WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
+        timer_initstruct->init.period   = (uint32_t)_arr;
+
+        /* update prescaler */
+        WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler);
+
+        pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse);
+
+        break;
+
+    case PWM_CMD_GET:
+        cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
+                     READ_REG(timer_initstruct->perh->AR);
+        break;
+
+    default:
+        break;
+    }
+    return ret;
+}
+
+const static struct rt_pwm_ops es32f3_pwm_ops =
+{
+    es32f3_pwm_control
+};
+
+int rt_hw_pwm_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    ald_gpio_init_t gpio_initstructure;
+
+    gpio_initstructure.mode = ALD_GPIO_MODE_OUTPUT;
+    gpio_initstructure.od = ALD_GPIO_PUSH_PULL;
+    gpio_initstructure.pupd = ALD_GPIO_PUSH_UP;
+    gpio_initstructure.odrv = ALD_GPIO_OUT_DRIVE_NORMAL;
+    gpio_initstructure.flt  = ALD_GPIO_FILTER_DISABLE;
+    gpio_initstructure.type = ALD_GPIO_TYPE_CMOS;
+
+#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */
+    static struct rt_device_pwm ad16c4t0_pwm_dev;
+    static timer_handle_t ad16c4t0_timer_initstruct;
+
+    ad16c4t0_timer_initstruct.perh = AD16C4T0;
+    ald_timer_pwm_init(&ad16c4t0_timer_initstruct);
+
+    /* gpio initialization */
+
+#if  defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC)
+    gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure);
+#endif
+
+    ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f3_pwm_ops,
+                                 &ad16c4t0_timer_initstruct);
+#endif
+
+#ifdef BSP_USING_AD16C4T1_PWM /* 4 channels */
+    static struct rt_device_pwm ad16c4t1_pwm_dev;
+    static timer_handle_t ad16c4t1_timer_initstruct;
+
+    ad16c4t1_timer_initstruct.perh = AD16C4T1;
+    ald_timer_pwm_init(&ad16c4t1_timer_initstruct);
+
+    /* gpio initialization */
+
+#if  defined(ES_AD16C4T1_CH1_GPIO_FUNC)&&defined(ES_AD16C4T1_CH1_GPIO_PORT)&&defined(ES_AD16C4T1_CH1_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T1_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T1_CH1_GPIO_PORT, ES_AD16C4T1_CH1_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_AD16C4T1_CH2_GPIO_FUNC)&&defined(ES_AD16C4T1_CH2_GPIO_PORT)&&defined(ES_AD16C4T1_CH2_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T1_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T1_CH2_GPIO_PORT, ES_AD16C4T1_CH2_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_AD16C4T1_CH3_GPIO_FUNC)&&defined(ES_AD16C4T1_CH3_GPIO_PORT)&&defined(ES_AD16C4T1_CH3_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T1_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T1_CH3_GPIO_PORT, ES_AD16C4T1_CH3_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_AD16C4T1_CH4_GPIO_FUNC)&&defined(ES_AD16C4T1_CH4_GPIO_PORT)&&defined(ES_AD16C4T1_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_AD16C4T1_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T1_CH4_GPIO_PORT, ES_AD16C4T1_CH4_GPIO_PIN, &gpio_initstructure);
+#endif
+
+    ret = rt_device_pwm_register(&ad16c4t1_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops,
+                                 &ad16c4t1_timer_initstruct);
+#endif
+
+
+#ifdef BSP_USING_GP32C4T0_PWM /* 4 channels */
+    static struct rt_device_pwm gp32c4t0_pwm_dev;
+    static timer_handle_t gp32c4t0_timer_initstruct;
+
+    gp32c4t0_timer_initstruct.perh = GP32C4T0;
+    ald_timer_pwm_init(&gp32c4t0_timer_initstruct);
+
+    /* gpio initialization */
+
+#if  defined(ES_GP32C4T0_CH1_GPIO_FUNC)&&defined(ES_GP32C4T0_CH1_GPIO_PORT)&&defined(ES_GP32C4T0_CH1_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T0_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T0_CH1_GPIO_PORT, ES_GP32C4T0_CH1_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP32C4T0_CH2_GPIO_FUNC)&&defined(ES_GP32C4T0_CH2_GPIO_PORT)&&defined(ES_GP32C4T0_CH2_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T0_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T0_CH2_GPIO_PORT, ES_GP32C4T0_CH2_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP32C4T0_CH3_GPIO_FUNC)&&defined(ES_GP32C4T0_CH3_GPIO_PORT)&&defined(ES_GP32C4T0_CH3_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T0_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T0_CH3_GPIO_PORT, ES_GP32C4T0_CH3_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP32C4T0_CH4_GPIO_FUNC)&&defined(ES_GP32C4T0_CH4_GPIO_PORT)&&defined(ES_GP32C4T0_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T0_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T0_CH4_GPIO_PORT, ES_GP32C4T0_CH4_GPIO_PIN, &gpio_initstructure);
+#endif
+
+    ret = rt_device_pwm_register(&gp32c4t0_pwm_dev, ES_DEVICE_NAME_GP32C4T0_PWM, &es32f3_pwm_ops,
+                                 &gp32c4t0_timer_initstruct);
+#endif
+
+
+#ifdef BSP_USING_GP32C4T1_PWM /* 4 channels */
+    static struct rt_device_pwm gp32c4t1_pwm_dev;
+    static timer_handle_t gp32c4t1_timer_initstruct;
+
+    gp32c4t1_timer_initstruct.perh = GP32C4T1;
+    ald_timer_pwm_init(&gp32c4t1_timer_initstruct);
+
+    /* gpio initialization */
+
+#if  defined(ES_GP32C4T1_CH1_GPIO_FUNC)&&defined(ES_GP32C4T1_CH1_GPIO_PORT)&&defined(ES_GP32C4T1_CH1_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T1_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T1_CH1_GPIO_PORT, ES_GP32C4T1_CH1_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP32C4T1_CH2_GPIO_FUNC)&&defined(ES_GP32C4T1_CH2_GPIO_PORT)&&defined(ES_GP32C4T1_CH2_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T1_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T1_CH2_GPIO_PORT, ES_GP32C4T1_CH2_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP32C4T1_CH3_GPIO_FUNC)&&defined(ES_GP32C4T1_CH3_GPIO_PORT)&&defined(ES_GP32C4T1_CH3_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T1_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T1_CH3_GPIO_PORT, ES_GP32C4T1_CH3_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP32C4T1_CH4_GPIO_FUNC)&&defined(ES_GP32C4T1_CH4_GPIO_PORT)&&defined(ES_GP32C4T1_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_GP32C4T1_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_GP32C4T1_CH4_GPIO_PORT, ES_GP32C4T1_CH4_GPIO_PIN, &gpio_initstructure);
+#endif
+
+    ret = rt_device_pwm_register(&gp32c4t1_pwm_dev, ES_DEVICE_NAME_GP32C4T1_PWM, &es32f3_pwm_ops,
+                                 &gp32c4t1_timer_initstruct);
+#endif
+
+
+#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */
+    static struct rt_device_pwm gp16c4t0_pwm_dev;
+    static ald_timer_handle_t gp16c4t0_timer_initstruct;
+
+    gp16c4t0_timer_initstruct.perh = GP16C4T0;
+    ald_timer_pwm_init(&gp16c4t0_timer_initstruct);
+
+    /* gpio initialization */
+
+#if  defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure);
+#endif
+
+    ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f3_pwm_ops,
+                                 &gp16c4t0_timer_initstruct);
+#endif
+
+
+#ifdef BSP_USING_GP16C4T1_PWM /* 4 channels */
+    static struct rt_device_pwm gp16c4t1_pwm_dev;
+    static timer_handle_t gp16c4t1_timer_initstruct;
+
+    gp16c4t1_timer_initstruct.perh = GP16C4T1;
+    ald_timer_pwm_init(&gp16c4t1_timer_initstruct);
+
+    /* gpio initialization */
+
+#if  defined(ES_GP16C4T1_CH1_GPIO_FUNC)&&defined(ES_GP16C4T1_CH1_GPIO_PORT)&&defined(ES_GP16C4T1_CH1_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T1_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T1_CH1_GPIO_PORT, ES_GP16C4T1_CH1_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP16C4T1_CH2_GPIO_FUNC)&&defined(ES_GP16C4T1_CH2_GPIO_PORT)&&defined(ES_GP16C4T1_CH2_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T1_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T1_CH2_GPIO_PORT, ES_GP16C4T1_CH2_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP16C4T1_CH3_GPIO_FUNC)&&defined(ES_GP16C4T1_CH3_GPIO_PORT)&&defined(ES_GP16C4T1_CH3_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T1_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T1_CH3_GPIO_PORT, ES_GP16C4T1_CH3_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_GP16C4T1_CH4_GPIO_FUNC)&&defined(ES_GP16C4T1_CH4_GPIO_PORT)&&defined(ES_GP16C4T1_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T1_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T1_CH4_GPIO_PORT, ES_GP16C4T1_CH4_GPIO_PIN, &gpio_initstructure);
+#endif
+
+    ret = rt_device_pwm_register(&gp16c4t1_pwm_dev, ES_DEVICE_NAME_GP16C4T1_PWM, &es32f3_pwm_ops,
+                                 &gp16c4t1_timer_initstruct);
+#endif
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_pwm_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_pwm.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-11     wangyq       the first version
+ */
+
+#ifndef DRV_PWM_H__
+#define DRV_PWM_H__
+
+int rt_hw_pwm_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_spi.c

@@ -0,0 +1,430 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-11-01     wangyq        update libraries
+ * 2020-01-14     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <string.h>
+#include <rthw.h>
+#include "board.h"
+#include "drv_spi.h"
+
+
+#ifdef RT_USING_SPI
+
+#define SPITIMEOUT 0xFFF
+
+rt_err_t spi_configure(struct rt_spi_device *device,
+                       struct rt_spi_configuration *cfg)
+{
+    ald_spi_handle_t *hspi;
+    hspi = (ald_spi_handle_t *)device->bus->parent.user_data;
+
+    hspi->init.ss_en    = DISABLE;
+    hspi->init.crc_calc = DISABLE;
+    hspi->init.frame    = ALD_SPI_FRAME_MOTOROLA;
+
+    /* config spi mode */
+    if (cfg->mode & RT_SPI_SLAVE)
+    {
+        hspi->init.mode = ALD_SPI_MODE_SLAVER;
+    }
+    else
+    {
+        hspi->init.mode = ALD_SPI_MODE_MASTER;
+    }
+    if (cfg->mode & RT_SPI_3WIRE)
+    {
+        hspi->init.dir = ALD_SPI_DIRECTION_1LINE;
+    }
+    else
+    {
+        hspi->init.dir = ALD_SPI_DIRECTION_2LINES;
+    }
+    if (cfg->data_width == 8)
+    {
+        hspi->init.data_size = ALD_SPI_DATA_SIZE_8;
+    }
+    else if (cfg->data_width == 16)
+    {
+        hspi->init.data_size = ALD_SPI_DATA_SIZE_16;
+    }
+
+    if (cfg->mode & RT_SPI_CPHA)
+    {
+        hspi->init.phase = ALD_SPI_CPHA_SECOND;
+    }
+    else
+    {
+        hspi->init.phase = ALD_SPI_CPHA_FIRST;
+    }
+    if (cfg->mode & RT_SPI_MSB)
+    {
+        hspi->init.first_bit = ALD_SPI_FIRSTBIT_MSB;
+    }
+    else
+    {
+        hspi->init.first_bit = ALD_SPI_FIRSTBIT_LSB;
+    }
+
+    if (cfg->mode & RT_SPI_CPOL)
+    {
+        hspi->init.polarity = ALD_SPI_CPOL_HIGH;
+    }
+    else
+    {
+        hspi->init.polarity = ALD_SPI_CPOL_LOW;
+    }
+    if (cfg->mode & RT_SPI_NO_CS)
+    {
+        hspi->init.ss_en = DISABLE;
+    }
+    else
+    {
+        hspi->init.ss_en = ENABLE;
+    }
+
+    /* config spi clock */
+    if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 2)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_2;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 4)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_4;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 8)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_8;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 16)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_16;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 32)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_32;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 64)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_64;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 128)
+    {
+        hspi->init.baud = ALD_SPI_BAUD_128;
+    }
+    else
+    {
+        hspi->init.baud = ALD_SPI_BAUD_256;
+    }
+    ALD_SPI_DISABLE(hspi);
+    ald_spi_init(hspi);
+    return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    rt_err_t res;
+    ald_spi_handle_t *hspi;
+    struct es32f3_hw_spi_cs *cs;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+
+    hspi = (ald_spi_handle_t *)device->bus->parent.user_data;
+    cs = device->parent.user_data;
+
+    if (message->cs_take)
+        {
+            rt_pin_write(cs->pin, ES_SPI_CS_LEVEL);
+        }
+
+    if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL)
+    {
+    /* send & receive */
+    if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
+    {
+        res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                                (rt_int32_t)message->length, SPITIMEOUT);
+    }
+    else
+    {
+        /* only send data */
+        if (message->recv_buf == RT_NULL)
+        {
+            res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        }
+        /* only receive data */
+        if (message->send_buf == RT_NULL)
+        {
+            res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        }
+    }
+
+     if (message->cs_release)
+     {
+        rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL);
+     }
+
+     if (res != RT_EOK)
+         return RT_ERROR;
+     else
+         return message->length;
+
+    }
+    else
+    {
+
+        if (message->cs_release)
+        {
+            rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL);
+        }
+            return RT_EOK;
+    }
+
+}
+const struct rt_spi_ops es32f3_spi_i2s_ops =
+{
+    RT_NULL,
+    RT_NULL,
+};
+const struct rt_spi_ops es32f3_spi_ops =
+{
+    spi_configure,
+    spixfer,
+};
+
+rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
+{
+    int result;
+    /* define spi Instance */
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+    cs_pin->pin = pin;
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+    rt_pin_write(pin, 1);
+
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+#ifdef BSP_USING_SPI0
+    if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0);
+#endif
+#ifdef BSP_USING_SPI1
+    if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1);
+#endif
+#ifdef BSP_USING_SPI2
+    if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI2_BUS)))SPI_BUS_CONFIG(spi_device->config,2);
+#endif
+
+    return result;
+}
+
+#ifdef BSP_USING_SPI0
+    static struct rt_spi_bus _spi_bus0;
+    static ald_spi_handle_t _spi0;
+#endif
+
+#ifdef BSP_USING_SPI1
+    static struct rt_spi_bus _spi_bus1;
+    static spi_handle_t _spi1;
+#endif
+
+#ifdef BSP_USING_SPI2
+    static struct rt_spi_bus _spi_bus2;
+    static spi_handle_t _spi2;
+#endif
+
+int rt_hw_spi_init(void)
+{
+    int result = RT_EOK;
+
+    struct rt_spi_bus *spi_bus;
+    ald_spi_handle_t *spi;
+    ald_gpio_init_t gpio_instruct;
+
+    gpio_instruct.pupd = ALD_GPIO_PUSH_UP_DOWN;
+    gpio_instruct.od = ALD_GPIO_PUSH_PULL;
+    gpio_instruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL;
+    gpio_instruct.type = ALD_GPIO_TYPE_CMOS;
+    gpio_instruct.flt  = ALD_GPIO_FILTER_DISABLE;
+
+#ifdef BSP_USING_SPI0
+    _spi0.perh = SPI0;
+    spi_bus = &_spi_bus0;
+    spi = &_spi0;
+    /* SPI0 gpio init */
+    gpio_instruct.mode = ALD_GPIO_MODE_OUTPUT;
+
+#if  defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN)
+    gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if  defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN)
+    gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if !defined(ES_SPI0_I2S_MODE)
+    gpio_instruct.mode = ALD_GPIO_MODE_INPUT;
+#endif
+
+#if  defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN)
+    gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if defined(ES_SPI0_I2S_MODE)&&defined(ES_SPI0_NSS_GPIO_FUNC)&&defined(ES_SPI0_NSS_GPIO_PORT)&&defined(ES_SPI0_NSS_GPIO_PIN)
+    gpio_instruct.func = ES_SPI0_NSS_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_NSS_GPIO_PORT, ES_SPI0_NSS_GPIO_PIN, &gpio_instruct);
+#endif
+
+    spi_bus->parent.user_data = spi;
+    #if defined(ES_SPI0_I2S_MODE)
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_i2s_ops);
+    #else
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    result = es32f3_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0);
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+    #endif
+
+#endif
+
+#ifdef BSP_USING_SPI1
+    _spi1.perh = SPI1;
+    spi_bus = &_spi_bus1;
+    spi = &_spi1;
+
+    /* SPI1 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+
+#if  defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN)
+    gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if  defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN)
+    gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if !defined(ES_SPI1_I2S_MODE)
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+#endif
+
+#if  defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN)
+    gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if defined(ES_SPI1_I2S_MODE)&&defined(ES_SPI1_NSS_GPIO_FUNC)&&defined(ES_SPI1_NSS_GPIO_PORT)&&defined(ES_SPI1_NSS_GPIO_PIN)
+    gpio_instruct.func = ES_SPI1_NSS_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_NSS_GPIO_PORT, ES_SPI1_NSS_GPIO_PIN, &gpio_instruct);
+#endif
+
+    spi_bus->parent.user_data = spi;
+    #if defined(ES_SPI1_I2S_MODE)
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_i2s_ops);
+    #else
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    result = es32f3_spi_device_attach(ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0);
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+    #endif
+#endif
+
+#ifdef BSP_USING_SPI2
+    _spi2.perh = SPI2;
+    spi_bus = &_spi_bus2;
+    spi = &_spi2;
+
+    /* SPI2 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+
+#if  defined(ES_SPI2_SCK_GPIO_FUNC)&&defined(ES_SPI2_SCK_GPIO_PORT)&&defined(ES_SPI2_SCK_GPIO_PIN)
+    gpio_instruct.func = ES_SPI2_SCK_GPIO_FUNC;
+    ald_gpio_init(ES_SPI2_SCK_GPIO_PORT, ES_SPI2_SCK_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if  defined(ES_SPI2_MOSI_GPIO_FUNC)&&defined(ES_SPI2_MOSI_GPIO_PORT)&&defined(ES_SPI2_MOSI_GPIO_PIN)
+    gpio_instruct.func = ES_SPI2_MOSI_GPIO_FUNC;
+    ald_gpio_init(ES_SPI2_MOSI_GPIO_PORT, ES_SPI2_MOSI_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if !defined(ES_SPI2_I2S_MODE)
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+#endif
+
+#if  defined(ES_SPI2_MISO_GPIO_FUNC)&&defined(ES_SPI2_MISO_GPIO_PORT)&&defined(ES_SPI2_MISO_GPIO_PIN)
+    gpio_instruct.func = ES_SPI2_MISO_GPIO_FUNC;
+    ald_gpio_init(ES_SPI2_MISO_GPIO_PORT, ES_SPI2_MISO_GPIO_PIN, &gpio_instruct);
+#endif
+
+#if defined(ES_SPI2_I2S_MODE)&&defined(ES_SPI2_NSS_GPIO_FUNC)&&defined(ES_SPI2_NSS_GPIO_PORT)&&defined(ES_SPI2_NSS_GPIO_PIN)
+    gpio_instruct.func = ES_SPI2_NSS_GPIO_FUNC;
+    ald_gpio_init(ES_SPI2_NSS_GPIO_PORT, ES_SPI2_NSS_GPIO_PIN, &gpio_instruct);
+#endif
+
+    spi_bus->parent.user_data = spi;
+    #if defined(ES_SPI2_I2S_MODE)
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_i2s_ops);
+    #else
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI2_BUS, &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    result = es32f3_spi_device_attach(ES_SPI2_NSS_PIN, ES_DEVICE_NAME_SPI2_BUS, ES_DEVICE_NAME_SPI1_DEV0);
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+    #endif
+#endif
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_spi.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_SPI_H__
+#define DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "es_conf_info_spi.h"
+
+struct es32f3_hw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+/* cannot be used before completion init */
+rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name);
+int rt_hw_spi_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_spiflash.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-02-15     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
+ */
+
+#include "board.h"
+#include <rtthread.h>
+
+#if defined(BSP_USING_SPI_FLASH)
+
+#include "spi_flash.h"
+#include "drv_spiflash.h"
+#include "spi_flash_sfud.h"
+#include "drv_spi.h"
+
+int rt_hw_spi_flash_init(void)
+{
+
+    if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV))
+    {
+        return -RT_ERROR;
+    };
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_spiflash.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-02-15     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
+ */
+
+#ifndef DRV_NOR_FLASH_H__
+#define DRV_NOR_FLASH_H__
+
+#include "es_conf_info_spi.h"
+
+int rt_hw_spi_flash_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/drv_uart.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2022-02-11     Lisq          the first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+#include "board.h"
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/essemi/es32vf2264/drivers/es32vf2264.ld

@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file     gcc_csky.ld
+ * @brief    csky linker file
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+MEMORY
+{
+	I-SRAM : ORIGIN = 0x00000000 , LENGTH = 0x40000   /* I-SRAM  256KB */
+	D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0x8000    /* D-SRAM  32KB */
+	O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000  /* off-chip SRAM 8MB */
+	SRAM   : ORIGIN = 0x60000000 , LENGTH = 0x20000   /* on-chip SRAM 128KB */
+}
+
+__min_heap_size = 0x200;
+__rt_rvstack_bss_size = 0x400;
+PROVIDE (__ram_end  = 0x20007FFF);
+PROVIDE (__heap_end = __ram_end);
+
+REGION_ALIAS("REGION_TEXT",    I-SRAM);
+REGION_ALIAS("REGION_RODATA",  I-SRAM);
+REGION_ALIAS("REGION_DATA",    D-SRAM);
+REGION_ALIAS("REGION_BSS",     D-SRAM);
+
+ENTRY(Reset_Handler)
+SECTIONS
+{
+ .text : {
+  . = ALIGN(0x4) ;
+  __stext = . ;
+  KEEP(*startup_es32vf2264.o(*.text*))
+  *(.text)
+  *(.text*)
+  *(.text.*)
+  *(.gnu.warning)
+  *(.stub)
+  *(.gnu.linkonce.t*)
+  *(.glue_7t)
+  *(.glue_7)
+  *(.jcr)
+  KEEP (*(.init))
+  KEEP (*(.fini))
+  . = ALIGN(0x40) ;
+  KEEP(*startup_es32vf2264.o(*.vectors*))
+
+  /* section information for finsh shell */
+  . = ALIGN(4);
+  __fsymtab_start = .;
+  KEEP(*(FSymTab))
+  __fsymtab_end = .;
+
+  . = ALIGN (4) ;
+  PROVIDE(__ctbp = .);
+  *(.call_table_data)
+  *(.call_table_text)
+  . = ALIGN(0x10) ;
+  __etext = . ;
+ } > REGION_TEXT
+ 
+ 
+ .eh_frame_hdr : {
+  *(.eh_frame_hdr)
+ } > REGION_TEXT
+ 
+ 
+ .eh_frame : ONLY_IF_RO {
+  KEEP (*(.eh_frame))
+ } > REGION_TEXT
+ 
+ 
+ .gcc_except_table : ONLY_IF_RO {
+  *(.gcc_except_table .gcc_except_table.*)
+ } > REGION_TEXT
+ 
+ 
+ .rodata : {
+  . = ALIGN(0x4) ;
+  __srodata = .;
+  *(.rdata)
+  *(.rdata*)
+  *(.rdata1)
+  *(.rdata.*)
+  KEEP (*(.rti_fn.0))
+  KEEP (*(.rti_fn.0.end))
+  KEEP (*(.rti_fn.1))
+  KEEP (*(.rti_fn.1.end))
+  KEEP (*(.rti_fn.2))
+  KEEP (*(.rti_fn.2.end))
+  KEEP (*(.rti_fn.3))
+  KEEP (*(.rti_fn.3.end))
+  KEEP (*(.rti_fn.4))
+  KEEP (*(.rti_fn.4.end))
+  KEEP (*(.rti_fn.5))
+  KEEP (*(.rti_fn.5.end))
+  KEEP (*(.rti_fn.6))
+  KEEP (*(.rti_fn.6.end))
+  *(.rodata)
+  *(.rodata1)
+  *(.rodata*)
+  *(.rodata.*)
+  *(.rodata.str1.4)
+  *(.srodata*)
+  . = ALIGN(0x4) ;
+  __ctor_start__ = .;
+  KEEP (*(SORT(.ctors.*)))
+  KEEP (*(.ctors))
+  __ctor_end__ = .;
+  KEEP (*(SORT(.dtors.*)))
+  KEEP (*(.dtors))
+  __dtor_end__ = .;
+  . = ALIGN(0x4) ;
+  __erodata = .;
+  __rodata_end__ = .;
+ } > REGION_RODATA
+ 
+ 
+ 
+ .data : {
+  . = ALIGN(0x4) ;
+  __sdata = . ;
+  __data_start__ = . ;
+  data_start = . ;
+  *(.got.plt)
+  *(.got)
+  *(.gnu.linkonce.r*)
+  *(.data)
+  *(.data*)
+  *(.data1)
+  *(.data.*)
+  *(.gnu.linkonce.d*)
+  *(.data1)
+  *(.gcc_except_table)
+  *(.gcc_except_table*)
+  __start_init_call = .;
+  *(.initcall.init)
+  __stop_init_call = .;
+  __start_cmd = .;
+  *(.bootloaddata.cmd)
+  . = ALIGN(4) ;
+  __stop_cmd = .;
+  __global_pointer$ = .;
+  *(.sdata)
+  *(.sdata.*)
+  *(.sdata2.*)
+  *(.gnu.linkonce.s.*)
+  *(__libc_atexit)
+  *(__libc_subinit)
+  *(__libc_subfreeres)
+  *(.note.ABI-tag)
+  __edata = .;
+  __data_end__ = .;
+  . = ALIGN(0x4) ;
+ } > REGION_DATA AT > REGION_RODATA
+ 
+ 
+ 
+ .eh_frame : ONLY_IF_RW {
+  KEEP (*(.eh_frame))
+ } > REGION_DATA AT > REGION_RODATA
+ 
+ 
+ 
+ .gcc_except_table : ONLY_IF_RW {
+  *(.gcc_except_table .gcc_except_table.*)
+  __edata = .;
+  __data_end__ = .;
+ } > REGION_DATA AT > REGION_RODATA
+ 
+ 
+ 
+ .bss : {
+  . = ALIGN(0x4) ;
+  __sbss = ALIGN(0x4) ;
+  __bss_start__ = . ;
+  *(.dynsbss)
+  *(.sbss)
+  *(.sbss.*)
+  *(.scommon)
+  *(.dynbss)
+  *(.bss)
+  *(.bss.*)
+  *(COMMON)
+  . = ALIGN(0x4) ;
+  __ebss = . ;
+  __bss_end__ = .;
+  __end = . ;
+  end = . ;
+ } > REGION_BSS AT > REGION_BSS
+ 
+ 
+ 
+ ._user_heap : {
+  . = ALIGN(0x4) ;
+  __heap_start = .;
+  . += __min_heap_size;
+  . = ALIGN(0x4) ;
+ } > REGION_BSS AT > REGION_BSS
+ 
+ ._rtt_v5_use_stack1 : {
+  . = ALIGN(0x4) ;
+  . += __rt_rvstack_bss_size;
+  __rt_rvstack = .;
+  . = ALIGN(0x4) ;
+ } > REGION_BSS AT > REGION_BSS
+ 
+ 
+ 
+}

bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_cmu.h

@@ -0,0 +1,428 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_cmu.h
+  * @brief   Header file of CMU module driver.
+  *
+  * @version V1.0
+  * @date    30 Jan. 2023
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          30 Jan. 2023    Lisq            The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#ifndef __ALD_CMU_H__
+#define __ALD_CMU_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ald_syscfg.h"
+
+
+/** @addtogroup ALD
+  * @{
+  */
+
+/** @addtogroup CMU
+  * @{
+  */
+
+/** @defgroup CMU_Public_Macros CMU Public Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CMU_Public_Types CMU Public Types
+  * @{
+  */
+/**
+  * @brief CMU state structure definition
+  */
+typedef enum
+{
+    ALD_CMU_CLOCK_HRC48M  = 0x1U,   /**< HRC48M */
+    ALD_CMU_CLOCK_LRC     = 0x2U,   /**< LRC */
+    ALD_CMU_CLOCK_HOSC    = 0x3U,   /**< HOSC */
+    ALD_CMU_CLOCK_PLL     = 0x4U,   /**< PLL */
+    ALD_CMU_CLOCK_HRC4M   = 0x5U,   /**< HRC4M */
+} ald_cmu_clock_t;
+
+/**
+  * @brief PLL output clock
+  */
+typedef enum
+{
+    ALD_CMU_PLL_OUTPUT_72M = 0x0U,  /**< 72MHz */
+    ALD_CMU_PLL_OUTPUT_64M = 0x2U,  /**< 64MHz */
+    ALD_CMU_PLL_OUTPUT_48M = 0x3U,  /**< 48MHz */
+} ald_cmu_pll_output_t;
+
+/**
+  * @brief PLL referance clock
+  */
+typedef enum
+{
+    ALD_CMU_PLL_INPUT_HRC4M   = 0x0U,   /**< HRC4M */
+    ALD_CMU_PLL_INPUT_HOSC4M  = 0x1U,   /**< HOSC4M */
+    ALD_CMU_PLL_INPUT_HOSC8M  = 0x2U,   /**< HOSC8M */
+    ALD_CMU_PLL_INPUT_HOSC16M = 0x3U,   /**< HOSC16M */
+} ald_cmu_pll_input_t;
+
+/**
+  * @brief HOSC range
+  */
+typedef enum {
+    ALD_CMU_HOSC_1M_2M   = 0x0U,    /**< 1~2MHz */
+    ALD_CMU_HOSC_2M_4M   = 0x1U,    /**< 2~4MHz */
+    ALD_CMU_HOSC_4M_8M   = 0x2U,    /**< 4~8MHz */
+    ALD_CMU_HOSC_8M_16M  = 0x3U,    /**< 8~16MHz */
+    ALD_CMU_HOSC_16M_24M = 0x4U,    /**< 16~24MHz */
+} ald_cmu_hosc_range_t;
+
+/**
+  * @brief Frequency division select bit
+  */
+typedef enum
+{
+    ALD_CMU_DIV_1    = 0x0U,     /**< Division by 1 */
+    ALD_CMU_DIV_2    = 0x1U,     /**< Division by 2 */
+    ALD_CMU_DIV_4    = 0x2U,     /**< Division by 4 */
+    ALD_CMU_DIV_8    = 0x3U,     /**< Division by 8 */
+    ALD_CMU_DIV_16   = 0x4U,     /**< Division by 16 */
+    ALD_CMU_DIV_32   = 0x5U,     /**< Division by 32 */
+    ALD_CMU_DIV_64   = 0x6U,     /**< Division by 64 */
+    ALD_CMU_DIV_128  = 0x7U,     /**< Division by 128 */
+    ALD_CMU_DIV_256  = 0x8U,     /**< Division by 256 */
+    ALD_CMU_DIV_512  = 0x9U,     /**< Division by 512 */
+    ALD_CMU_DIV_1024 = 0xAU,     /**< Division by 1024 */
+    ALD_CMU_DIV_2048 = 0xBU,     /**< Division by 2048 */
+    ALD_CMU_DIV_4096 = 0xCU,     /**< Division by 4096 */
+} ald_cmu_div_t;
+
+/**
+  * @brief BUZZ frequency division
+  */
+typedef enum {
+    ALD_CMU_BUZZ_DIV_2   = 0x0U,    /**< Division by 2 */
+    ALD_CMU_BUZZ_DIV_4   = 0x1U,    /**< Division by 4 */
+    ALD_CMU_BUZZ_DIV_8   = 0x2U,    /**< Division by 8 */
+    ALD_CMU_BUZZ_DIV_16  = 0x3U,    /**< Division by 16 */
+    ALD_CMU_BUZZ_DIV_32  = 0x4U,    /**< Division by 32 */
+    ALD_CMU_BUZZ_DIV_64  = 0x5U,    /**< Division by 64 */
+    ALD_CMU_BUZZ_DIV_128 = 0x6U,    /**< Division by 128 */
+    ALD_CMU_BUZZ_DIV_256 = 0x7U,    /**< Division by 256 */
+} ald_cmu_buzz_div_t;
+
+/**
+  * @brief Safe clock source type
+  */
+typedef enum {
+    ALD_CMU_SAFE_CLK_PLL = 0x0U,    /**< PLL */
+} ald_cmu_clock_safe_type_t;
+
+/**
+  * @brief Bus type
+  */
+typedef enum
+{
+    ALD_CMU_SYS    = 0x1U,     /**< SYS bus */
+    ALD_CMU_PCLK   = 0x2U,     /**< APB bus */
+} ald_cmu_bus_t;
+
+/**
+  * @brief Output frequency division
+  */
+typedef enum {
+    ALD_CMU_OUTPUT_DIV_1   = 0x0U,  /**< Division by 1 */
+    ALD_CMU_OUTPUT_DIV_2   = 0x1U,  /**< Division by 2 */
+    ALD_CMU_OUTPUT_DIV_4   = 0x2U,  /**< Division by 4 */
+    ALD_CMU_OUTPUT_DIV_8   = 0x3U,  /**< Division by 8 */
+    ALD_CMU_OUTPUT_DIV_16  = 0x4U,  /**< Division by 16 */
+    ALD_CMU_OUTPUT_DIV_32  = 0x5U,  /**< Division by 32 */
+    ALD_CMU_OUTPUT_DIV_64  = 0x6U,  /**< Division by 64 */
+    ALD_CMU_OUTPUT_DIV_128 = 0x7U,  /**< Division by 128 */
+} ald_cmu_output_high_div_t;
+
+/**
+  * @brief Output high clock select
+  */
+typedef enum {
+    ALD_CMU_OUTPUT_HIGH_SEL_HOSC    = 0x0U, /**< Select HOSC */
+    ALD_CMU_OUTPUT_HIGH_SEL_HOSM    = 0x1U, /**< Select HOSM */
+    ALD_CMU_OUTPUT_HIGH_SEL_HRC4M   = 0x2U, /**< Select HRC4M */
+    ALD_CMU_OUTPUT_HIGH_SEL_LRC     = 0x3U, /**< Select LRC */
+    ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK  = 0x4U, /**< Select SYSCLK */
+    ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K = 0x5U, /**< Select HOSC32K */
+    ALD_CMU_OUTPUT_HIGH_SEL_HRC48M  = 0x6U, /**< Select HRC48M */
+    ALD_CMU_OUTPUT_HIGH_SEL_PLL     = 0x7U, /**< Select PLL */
+} ald_cmu_output_high_sel_t;
+
+/**
+  * @brief Output low clock select
+  */
+typedef enum {
+    ALD_CMU_OUTPUT_LOW_SEL_LRC  = 0x0U, /**< Select LRC */
+    ALD_CMU_OUTPUT_LOW_SEL_BUZZ = 0x1U, /**< Select BUZZ */
+} ald_cmu_output_low_sel_t;
+
+/**
+  * @brief Peripheral clock enable/disable
+  */
+typedef enum {
+    ALD_CMU_PERH_GPIO      = (1U << 0),                 /**< GPIO */
+    ALD_CMU_PERH_CRC       = (1U << 1),                 /**< CRC */
+    ALD_CMU_PERH_DMA       = (1U << 2),                 /**< DMA */
+    ALD_CMU_PERH_PIS       = (1U << 5),                 /**< PIS */
+    ALD_CMU_PERH_USB       = (1U << 6),                 /**< USB */
+    ALD_CMU_PERH_CSU       = (1U << 7),                 /**< CSU */
+    ALD_CMU_PERH_AD16C4T0  = (1U << 0)  | (1U << 27),   /**< AD16C4T0 */
+    ALD_CMU_PERH_BS16T0    = (1U << 1)  | (1U << 27),   /**< BS16T0 */
+    ALD_CMU_PERH_GP16C4T0  = (1U << 2)  | (1U << 27),   /**< CP16C4T0 */
+    ALD_CMU_PERH_GP16C4T1  = (1U << 3)  | (1U << 27),   /**< GP16C4T1 */
+    ALD_CMU_PERH_GP16C4T2  = (1U << 4)  | (1U << 27),   /**< GP16C4T2 */
+    ALD_CMU_PERH_EUART0    = (1U << 8)  | (1U << 27),   /**< EUART0 */
+    ALD_CMU_PERH_EUART1    = (1U << 9)  | (1U << 27),   /**< EUART1 */
+    ALD_CMU_PERH_CUART0    = (1U << 12) | (1U << 27),   /**< CUART0 */
+    ALD_CMU_PERH_CUART1    = (1U << 13) | (1U << 27),   /**< CUART1 */
+    ALD_CMU_PERH_CUART2    = (1U << 14) | (1U << 27),   /**< CUART2 */
+    ALD_CMU_PERH_SPI0      = (1U << 16) | (1U << 27),   /**< SPI0 */
+    ALD_CMU_PERH_SPI1      = (1U << 17) | (1U << 27),   /**< SPI1 */
+    ALD_CMU_PERH_I2C0      = (1U << 20) | (1U << 27),   /**< I2C0 */
+    ALD_CMU_PERH_I2C1      = (1U << 21) | (1U << 27),   /**< I2C1 */
+    ALD_CMU_PERH_WWDT      = (1U << 22) | (1U << 27),   /**< WWDT */
+    ALD_CMU_PERH_IWDT      = (1U << 23) | (1U << 27),   /**< IWDT */
+    ALD_CMU_PERH_DBGC      = (1U << 24) | (1U << 27),   /**< DBGC */
+    ALD_CMU_PERH_ADC       = (1U << 25) | (1U << 27),   /**< ADC */
+    ALD_CMU_PERH_ALL       = (0x7FFFFFFFU),             /**< ALL */
+} ald_cmu_perh_t;
+
+/**
+  * @brief CMU interrupt type
+  */
+typedef enum {
+    ALD_CMU_HOSC_STOP    = 0x0U,    /**< HOSC STOP INTERRUPT */
+    ALD_CMU_PLL_UNLOCK   = 0x1U,    /**< PLL UNLOCK INTERRUPT */
+    ALD_CMU_HOSC_START   = 0x2U,    /**< HOSC START INTERRUPT */
+} ald_cmu_security_t;
+
+/**
+  * @brief CMU clock state type
+  */
+typedef enum {
+    ALD_CMU_CLOCK_STATE_HOSCACT   = (1U << 0),  /**< HOSC active */
+    ALD_CMU_CLOCK_STATE_PLLACT    = (1U << 1),  /**< PLL active */
+    ALD_CMU_CLOCK_STATE_HRC4MACT  = (1U << 2),  /**< HRC4M active */
+    ALD_CMU_CLOCK_STATE_HRC48MACT = (1U << 3),  /**< HRC48M active */
+    ALD_CMU_CLOCK_STATE_HOSCRDY   = (1U << 16), /**< HOSC ready */
+    ALD_CMU_CLOCK_STATE_HRC4MRDY  = (1U << 17), /**< HRC4M ready */
+    ALD_CMU_CLOCK_STATE_HRC48MRDY = (1U << 18), /**< HRC48M ready */
+    ALD_CMU_CLOCK_STATE_LRCRDY    = (1U << 19), /**< LRC ready */
+    ALD_CMU_CLOCK_STATE_PLLRDY    = (1U << 24), /**< PLL ready */
+} ald_cmu_clock_state_t;
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CMU_Private_Macros CMU Private Macros
+  * @{
+  */
+#define IS_CMU_CLOCK(x)     (((x) == ALD_CMU_CLOCK_HRC48M)  || \
+                                 ((x) == ALD_CMU_CLOCK_LRC)  || \
+                                 ((x) == ALD_CMU_CLOCK_HOSC) || \
+                                 ((x) == ALD_CMU_CLOCK_PLL) || \
+                                 ((x) == ALD_CMU_CLOCK_HRC4M))
+#define IS_CMU_PLL_INPUT(x) (((x) == ALD_CMU_PLL_INPUT_HRC4M)  || \
+                                 ((x) == ALD_CMU_PLL_INPUT_HOSC4M)   || \
+                                 ((x) == ALD_CMU_PLL_INPUT_HOSC8M)   || \
+                                 ((x) == ALD_CMU_PLL_INPUT_HOSC16M))
+#define IS_CMU_PLL_OUTPUT(x)    (((x) == ALD_CMU_PLL_OUTPUT_48M) || \
+                                 ((x) == ALD_CMU_PLL_OUTPUT_64M) || \
+                                 ((x) == ALD_CMU_PLL_OUTPUT_72M))
+#define IS_CMU_HOSC_RANGE(x)    (((x) == ALD_CMU_HOSC_1M_2M)  || \
+                                 ((x) == ALD_CMU_HOSC_2M_4M)  || \
+                                 ((x) == ALD_CMU_HOSC_4M_8M)  || \
+                                 ((x) == ALD_CMU_HOSC_8M_16M) || \
+                                 ((x) == ALD_CMU_HOSC_16M_24M))
+#define IS_CMU_DIV(x)       (((x) == ALD_CMU_DIV_1)    || \
+                                 ((x) == ALD_CMU_DIV_2)    || \
+                                 ((x) == ALD_CMU_DIV_4)    || \
+                                 ((x) == ALD_CMU_DIV_8)    || \
+                                 ((x) == ALD_CMU_DIV_16)   || \
+                                 ((x) == ALD_CMU_DIV_32)   || \
+                                 ((x) == ALD_CMU_DIV_64)   || \
+                                 ((x) == ALD_CMU_DIV_128)  || \
+                                 ((x) == ALD_CMU_DIV_256)  || \
+                                 ((x) == ALD_CMU_DIV_512)  || \
+                                 ((x) == ALD_CMU_DIV_1024) || \
+                                 ((x) == ALD_CMU_DIV_2048) || \
+                                 ((x) == ALD_CMU_DIV_4096))
+#define IS_CMU_BUS(x)       (((x) == ALD_CMU_PCLK) || \
+                                 ((x) == ALD_CMU_SYS))
+#define IS_CMU_OUTPUT_HIGH_SEL(x)   (((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC) || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSM) || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC4M)  || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_LRC)  || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK) || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K) || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC48M) || \
+                                         ((x) == ALD_CMU_OUTPUT_HIGH_SEL_PLL))
+#define IS_CMU_OUTPUT_HIGH_DIV(x)   (((x) == ALD_CMU_OUTPUT_DIV_1)  || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_2)  || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_4)  || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_8)  || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_16) || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_32) || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_64) || \
+                                         ((x) == ALD_CMU_OUTPUT_DIV_128))
+#define IS_CMU_OUTPUT_LOW_SEL(x)    (((x) == ALD_CMU_OUTPUT_LOW_SEL_LRC) || \
+                                         ((x) == ALD_CMU_OUTPUT_LOW_SEL_BUZZ))
+#define IS_CMU_SAFE_CLOCK_TYPE(x)   (((x) == ALD_CMU_SAFE_CLK_PLL))
+#define IS_CMU_BUZZ_DIV(x)  (((x) == ALD_CMU_BUZZ_DIV_2)   || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_4)   || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_8)   || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_16)  || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_32)  || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_64)  || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_128) || \
+                                 ((x) == ALD_CMU_BUZZ_DIV_256))
+#define IS_CMU_PERH(x)      (((x) == ALD_CMU_PERH_GPIO)    || \
+                                 ((x) == ALD_CMU_PERH_CRC)     || \
+                                 ((x) == ALD_CMU_PERH_DMA)    || \
+                                 ((x) == ALD_CMU_PERH_PIS)   || \
+                                 ((x) == ALD_CMU_PERH_USB)    || \
+                                 ((x) == ALD_CMU_PERH_CSU)     || \
+                                 ((x) == ALD_CMU_PERH_AD16C4T0)  || \
+                                 ((x) == ALD_CMU_PERH_BS16T0)  || \
+                                 ((x) == ALD_CMU_PERH_GP16C4T0)  || \
+                                 ((x) == ALD_CMU_PERH_GP16C4T1)  || \
+                                 ((x) == ALD_CMU_PERH_GP16C4T2)  || \
+                                 ((x) == ALD_CMU_PERH_EUART0)  || \
+                                 ((x) == ALD_CMU_PERH_EUART1)  || \
+                                 ((x) == ALD_CMU_PERH_CUART0)  || \
+                                 ((x) == ALD_CMU_PERH_CUART1)   || \
+                                 ((x) == ALD_CMU_PERH_CUART2)   || \
+                                 ((x) == ALD_CMU_PERH_SPI0)    || \
+                                 ((x) == ALD_CMU_PERH_SPI1)    || \
+                                 ((x) == ALD_CMU_PERH_I2C0)    || \
+                                 ((x) == ALD_CMU_PERH_I2C1)    || \
+                                 ((x) == ALD_CMU_PERH_WWDT)     || \
+                                 ((x) == ALD_CMU_PERH_IWDT)  || \
+                                 ((x) == ALD_CMU_PERH_DBGC)    || \
+                                 ((x) == ALD_CMU_PERH_ADC)    || \
+                                 ((x) == ALD_CMU_PERH_ALL))
+#define IS_CMU_CLOCK_STATE(x)   (((x) == ALD_CMU_CLOCK_STATE_HOSCACT) || \
+                                 ((x) == ALD_CMU_CLOCK_STATE_PLLACT) || \
+                 ((x) == ALD_CMU_CLOCK_STATE_HRC4MACT)  || \
+                 ((x) == ALD_CMU_CLOCK_STATE_HRC48MACT)  || \
+                 ((x) == ALD_CMU_CLOCK_STATE_HOSCRDY) || \
+                 ((x) == ALD_CMU_CLOCK_STATE_HRC4MRDY) || \
+                 ((x) == ALD_CMU_CLOCK_STATE_HRC48MRDY) || \
+                 ((x) == ALD_CMU_CLOCK_STATE_LRCRDY) || \
+                 ((x) == ALD_CMU_CLOCK_STATE_PLLRDY))
+/**
+  * @}
+  */
+
+/** @addtogroup CMU_Public_Functions
+  * @{
+  */
+/** @addtogroup CMU_Public_Functions_Group1
+  * @{
+  */
+/* System clock configure */
+ald_status_t ald_cmu_clock_config_default(void);
+ald_status_t ald_cmu_clock_config(ald_cmu_clock_t clk, uint32_t clock);
+void ald_cmu_pll_config(ald_cmu_pll_input_t input, ald_cmu_pll_output_t output);
+uint32_t ald_cmu_get_clock(void);
+/**
+  * @}
+  */
+
+/** @addtogroup CMU_Public_Functions_Group2
+  * @{
+  */
+/* BUS division control */
+void ald_cmu_div_config(ald_cmu_bus_t bus, ald_cmu_div_t div);
+uint32_t ald_cmu_get_sys_clock(void);
+uint32_t ald_cmu_get_pclk_clock(void);
+/**
+  * @}
+  */
+
+/** @addtogroup CMU_Public_Functions_Group3
+  * @{
+  */
+/* Clock safe configure */
+void ald_cmu_hosc_safe_config(ald_cmu_hosc_range_t clock, type_func_t status);
+void ald_cmu_pll_safe_config(type_func_t status);
+uint32_t ald_cmu_pulmcr_current_clock_source_get(void);
+flag_status_t ald_cmu_get_clock_state(ald_cmu_clock_state_t sr);
+void ald_cmu_irq_handler(void);
+void ald_cmu_irq_cbk(ald_cmu_security_t se);
+/**
+  * @}
+  */
+
+/** @addtogroup CMU_Public_Functions_Group4
+  * @{
+  */
+/* Clock output configure */
+void ald_cmu_output_high_clock_config(ald_cmu_output_high_sel_t sel,
+        ald_cmu_output_high_div_t div, type_func_t status);
+void ald_cmu_output_low_clock_config(ald_cmu_output_low_sel_t sel, type_func_t status);
+/**
+  * @}
+  */
+
+/** @addtogroup CMU_Public_Functions_Group5
+  * @{
+  */
+/* Peripheral Clock configure */
+void ald_cmu_buzz_config(ald_cmu_buzz_div_t div, uint16_t dat, type_func_t status);
+void ald_cmu_perh_clock_config(ald_cmu_perh_t perh, type_func_t status);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALD_CMU_H__ */

bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_conf.h

@@ -0,0 +1,136 @@
+/**********************************************************************************
+ *
+ * @file    ald_conf.h
+ * @brief   Enable/Disable the peripheral module.
+ *
+ * @date    23 Feb. 2023
+ * @author  AE Team
+ * @note
+ *          Change Logs:
+ *          Date            Author          Notes
+ *          23 Feb. 2023    Lisq            the first version
+ *
+ * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ **********************************************************************************
+ */
+#ifndef   __ALD_CONF_H__
+#define   __ALD_CONF_H__
+
+/* Exported Macros ----------------------------------------------------------- */
+/* Includes ------------------------------------------------------------------ */
+#define ALD_I2C
+#define ALD_GPIO
+#define ALD_TIMER
+#define ALD_ADC
+#define ALD_DMA
+#define ALD_SPI
+/* #define ALD_IWDT */
+/* #define ALD_WWDT */
+/* #define ALD_CRC */
+#define ALD_UART
+#define ALD_CMU
+/* #define ALD_DBGC */
+/* #define ALD_PIS */
+#define ALD_PMU
+/* #define ALD_RMU */
+#define ALD_SYSCFG
+/* #define ALD_TYPE */
+#define ALD_UTILS
+
+#ifdef ALD_I2C
+    #include "ald_i2c.h"
+#endif /* ALD_I2C */
+
+#ifdef ALD_GPIO
+    #include "ald_gpio.h"
+#endif /* MD_GPIO */
+
+#ifdef ALD_TIMER
+    #include "ald_timer.h"
+#endif /* ALD_TIMER */
+
+#ifdef ALD_ADC
+    #include "ald_adc.h"
+#endif /* ALD_ADC */
+
+#ifdef ALD_DMA
+    #include "ald_dma.h"
+#endif /* ALD_DMA */
+
+#ifdef ALD_SPI
+    #include "ald_spi.h"
+#endif /* ALD_SPI */
+
+#ifdef ALD_IWDT
+    #include "ald_iwdt.h"
+#endif /* ALD_IWDT */
+
+#ifdef ALD_WWDT
+    #include "ald_wwdt.h"
+#endif /* ALD_WWDT */
+
+#ifdef ALD_CRC
+    #include "ald_crc.h"
+#endif /* ALD_CRC */
+
+#ifdef ALD_UART
+    #include "ald_uart.h"
+#endif /* ALD_UART */
+
+#ifdef ALD_CMU
+    #include "ald_cmu.h"
+#endif /* ALD_CMU */
+
+#ifdef ALD_DBGC
+    #include "ald_dbgc.h"
+#endif /* ALD_DBGC */
+
+#ifdef ALD_PIS
+    #include "ald_pis.h"
+#endif /* ALD_PIS */
+
+#ifdef ALD_PMU
+    #include "ald_pmu.h"
+#endif /* ALD_PMU */
+
+#ifdef ALD_RMU
+    #include "ald_rmu.h"
+#endif /* ALD_RMU */
+
+#ifdef ALD_SYSCFG
+    #include "ald_syscfg.h"
+#endif /* ALD_SYSCFG */
+
+#ifdef ALD_UTILS
+    #include "ald_utils.h"
+#endif /* ALD_UTILS */
+
+#ifdef ALD_TYPE
+    #include "type.h"
+#endif /* ALD_TYPE */
+
+#define TICK_INT_PRIORITY   3
+
+/* Exported Types ------------------------------------------------------------ */
+/* Exported Variables -------------------------------------------------------- */
+/* Exported Constants -------------------------------------------------------- */
+/* Exported Functions -------------------------------------------------------- */
+
+#endif /*__MD_CONF_H__*/
+
+/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/

bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_crc.h

@@ -0,0 +1,212 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_crc.h
+  * @brief   Header file of CRC module driver.
+  *
+  * @version V1.0
+  * @date    06 Mar. 2023
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          06 Mar. 2023    Lisq            The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#ifndef __ALD_CRC_H__
+#define __ALD_CRC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+#include "ald_utils.h"
+#include "ald_dma.h"
+
+/** @addtogroup ES32VF2264_ALD
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Public_Types CRC Public Types
+  * @{
+  */
+
+/**
+  * @brief CRC mode
+  */
+typedef enum {
+    ALD_CRC_MODE_CCITT = 0U,    /**< CCITT */
+    ALD_CRC_MODE_8     = 1U,    /**< CRC8 */
+    ALD_CRC_MODE_16    = 2U,    /**< CRC16 */
+    ALD_CRC_MODE_32    = 3U,    /**< CRC32 */
+} ald_crc_mode_t;
+
+/**
+  * @brief CRC input length
+  */
+typedef enum {
+    ALD_CRC_LEN_AUTO    = 0U,   /**< Auto */
+    ALD_CRC_DATASIZE_8  = 1U,   /**< Byte */
+    ALD_CRC_DATASIZE_16 = 2U,   /**< Half word */
+    ALD_CRC_DATASIZE_32 = 3U,   /**< Word */
+} ald_crc_datasize_t;
+
+/**
+  * @brief CRC whether write error or no
+  */
+typedef enum {
+    ALD_CRC_WERR_NO  = 0U,  /**< No error */
+    ALD_CRC_WERR_ERR = 1U,  /**< Error */
+} ald_crc_werr_t;
+
+/**
+  * @brief CRC state structures definition
+  */
+typedef enum {
+    ALD_CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
+    ALD_CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
+    ALD_CRC_STATE_BUSY  = 0x2U, /**< An internal process is ongoing */
+    ALD_CRC_STATE_ERROR = 0x4U, /**< Error */
+} ald_crc_state_t;
+
+/**
+  * @brief CRC init structure definition
+  */
+typedef struct {
+    ald_crc_mode_t mode;    /**< CRC mode */
+    type_func_t data_rev;   /**< CRC data reverse or no */
+    type_func_t data_inv;   /**< CRC data inverse or no */
+    type_func_t chs_rev;    /**< CRC check sum reverse or no */
+    type_func_t chs_inv;    /**< CRC check sum inverse or no */
+    uint32_t seed;      /**< CRC seed */
+} ald_crc_init_t;
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct ald_crc_handle_s {
+    CRC_TypeDef *perh;  /**< Register base address */
+    ald_crc_init_t init;    /**< CRC required parameters */
+    uint8_t *cal_buf;   /**< The pointer of preparing buffer */
+    uint32_t *cal_res;  /**< The pointer of result */
+
+    ald_dma_handle_t hdma;  /**< CRC DMA handle parameters */
+
+    lock_state_t lock;  /**< Locking object */
+    ald_crc_state_t state;  /**< CRC operation state */
+
+    void (*cal_cplt_cbk)(struct ald_crc_handle_s *arg); /**< Calculate completed callback */
+    void (*err_cplt_cbk)(struct ald_crc_handle_s *arg); /**< Calculate error callback */
+} ald_crc_handle_t;
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Public_Macros CRC Public Macros
+  * @{
+  */
+#define ALD_CRC_ENABLE(handle)      (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
+#define ALD_CRC_DISABLE(handle)     (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
+#define ALD_CRC_RESET(handle)       (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
+#define ALD_CRC_DMA_ENABLE(handle)      (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
+#define ALD_CRC_DMA_DISABLE(handle)     (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
+#define ALD_CRC_CLEAR_ERROR_FLAG(handle)    (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros   CRC Private Macros
+  * @{
+  */
+#define IS_CRC(x)   ((x) == CRC)
+#define IS_CRC_MODE(x)  (((x) == ALD_CRC_MODE_CCITT) || \
+             ((x) == ALD_CRC_MODE_8)     || \
+             ((x) == ALD_CRC_MODE_16)    || \
+             ((x) == ALD_CRC_MODE_32))
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Public_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_Public_Functions_Group1
+  * @{
+  */
+ald_status_t ald_crc_init(ald_crc_handle_t *hperh);
+void ald_crc_reset(ald_crc_handle_t *hperh);
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Public_Functions_Group2
+  * @{
+  */
+uint32_t ald_crc_calculate(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t size);
+uint32_t ald_crc_calculate_halfword(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t size);
+uint32_t ald_crc_calculate_word(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t size);
+/**
+  * @}
+  */
+
+
+/** @addtogroup CRC_Public_Functions_Group3
+  * @{
+  */
+ald_status_t ald_crc_calculate_by_dma(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
+ald_status_t ald_crc_calculate_halfword_by_dma(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
+ald_status_t ald_crc_calculate_word_by_dma(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
+ald_status_t ald_crc_dma_pause(ald_crc_handle_t *hperh);
+ald_status_t ald_crc_dma_resume(ald_crc_handle_t *hperh);
+ald_status_t ald_crc_dma_stop(ald_crc_handle_t *hperh);
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Public_Functions_Group4
+  * @{
+  */
+ald_crc_state_t ald_crc_get_state(ald_crc_handle_t *hperh);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALD_CRC_H__ */