From 3650fdd58343e284577a677316fc8fe8b0b72234 Mon Sep 17 00:00:00 2001 From: liuhy-2020 <74852322+liuhy-2020@users.noreply.github.com> Date: Wed, 10 May 2023 18:33:20 +0800 Subject: [PATCH] =?UTF-8?q?[bsp/essemi]=E5=A2=9E=E5=8A=A0rsicv=E8=8A=AF?= =?UTF-8?q?=E7=89=87bsp=EF=BC=9Aes32vf2264.=20(#7463)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/essemi/es32vf2264/.config | 1027 ++++ bsp/essemi/es32vf2264/.ignore_format.yml | 4 + bsp/essemi/es32vf2264/Kconfig | 27 + bsp/essemi/es32vf2264/README.md | 92 + bsp/essemi/es32vf2264/SConscript | 14 + bsp/essemi/es32vf2264/SConstruct | 40 + bsp/essemi/es32vf2264/applications/SConscript | 11 + bsp/essemi/es32vf2264/applications/main.c | 34 + bsp/essemi/es32vf2264/drivers/ES/Kconfig | 195 + .../es32vf2264/drivers/ES/es_conf_info_adc.h | 80 + .../es32vf2264/drivers/ES/es_conf_info_can.h | 73 + .../es32vf2264/drivers/ES/es_conf_info_cmu.h | 60 + .../es32vf2264/drivers/ES/es_conf_info_dma.h | 67 + .../es32vf2264/drivers/ES/es_conf_info_gpio.h | 5155 +++++++++++++++++ .../drivers/ES/es_conf_info_hwtimer.h | 103 + .../es32vf2264/drivers/ES/es_conf_info_i2c.h | 95 + .../es32vf2264/drivers/ES/es_conf_info_map.h | 3804 ++++++++++++ .../es32vf2264/drivers/ES/es_conf_info_pm.h | 32 + .../es32vf2264/drivers/ES/es_conf_info_pwm.h | 72 + .../es32vf2264/drivers/ES/es_conf_info_rtc.h | 43 + .../drivers/ES/es_conf_info_select.h | 44 + .../es32vf2264/drivers/ES/es_conf_info_spi.h | 132 + .../es32vf2264/drivers/ES/es_conf_info_uart.h | 156 + bsp/essemi/es32vf2264/drivers/Kconfig | 39 + bsp/essemi/es32vf2264/drivers/SConscript | 80 + bsp/essemi/es32vf2264/drivers/board.c | 150 + bsp/essemi/es32vf2264/drivers/board.h | 55 + bsp/essemi/es32vf2264/drivers/drv_adc.c | 218 + bsp/essemi/es32vf2264/drivers/drv_adc.h | 31 + bsp/essemi/es32vf2264/drivers/drv_gpio.c | 611 ++ bsp/essemi/es32vf2264/drivers/drv_gpio.h | 29 + bsp/essemi/es32vf2264/drivers/drv_hwtimer.c | 354 ++ bsp/essemi/es32vf2264/drivers/drv_hwtimer.h | 30 + bsp/essemi/es32vf2264/drivers/drv_i2c.c | 347 ++ bsp/essemi/es32vf2264/drivers/drv_i2c.h | 31 + bsp/essemi/es32vf2264/drivers/drv_pm.c | 197 + bsp/essemi/es32vf2264/drivers/drv_pm.h | 39 + bsp/essemi/es32vf2264/drivers/drv_pwm.c | 380 ++ bsp/essemi/es32vf2264/drivers/drv_pwm.h | 16 + bsp/essemi/es32vf2264/drivers/drv_spi.c | 430 ++ bsp/essemi/es32vf2264/drivers/drv_spi.h | 42 + bsp/essemi/es32vf2264/drivers/drv_spiflash.c | 34 + bsp/essemi/es32vf2264/drivers/drv_spiflash.h | 19 + bsp/essemi/es32vf2264/drivers/drv_uart.c | 770 +++ bsp/essemi/es32vf2264/drivers/drv_uart.h | 30 + bsp/essemi/es32vf2264/drivers/es32vf2264.ld | 212 + .../ALD/ES32VF2264/Include/ald_adc.h | 577 ++ .../ALD/ES32VF2264/Include/ald_cmu.h | 428 ++ .../ALD/ES32VF2264/Include/ald_conf.h | 136 + .../ALD/ES32VF2264/Include/ald_crc.h | 212 + .../ALD/ES32VF2264/Include/ald_dma.h | 342 ++ .../ALD/ES32VF2264/Include/ald_gpio.h | 300 + .../ALD/ES32VF2264/Include/ald_i2c.h | 524 ++ .../ALD/ES32VF2264/Include/ald_i2s.h | 399 ++ .../ALD/ES32VF2264/Include/ald_pis.h | 692 +++ .../ALD/ES32VF2264/Include/ald_pmu.h | 222 + .../ALD/ES32VF2264/Include/ald_rmu.h | 211 + .../ALD/ES32VF2264/Include/ald_spi.h | 452 ++ .../ALD/ES32VF2264/Include/ald_syscfg.h | 83 + .../ALD/ES32VF2264/Include/ald_timer.h | 1115 ++++ .../ALD/ES32VF2264/Include/ald_uart.h | 503 ++ .../ALD/ES32VF2264/Include/ald_usb.h | 821 +++ .../ALD/ES32VF2264/Include/ald_utils.h | 193 + .../ALD/ES32VF2264/Include/ald_wdt.h | 132 + .../libraries/ALD/ES32VF2264/Include/type.h | 145 + .../ES32VF2264/Include/usb_library_config.h | 94 + .../ALD/ES32VF2264/Include/usb_lowlayer_api.h | 742 +++ .../libraries/ALD/ES32VF2264/Source/ald_adc.c | 1101 ++++ .../libraries/ALD/ES32VF2264/Source/ald_cmu.c | 879 +++ .../libraries/ALD/ES32VF2264/Source/ald_crc.c | 503 ++ .../libraries/ALD/ES32VF2264/Source/ald_dma.c | 446 ++ .../ALD/ES32VF2264/Source/ald_gpio.c | 640 ++ .../libraries/ALD/ES32VF2264/Source/ald_i2c.c | 3590 ++++++++++++ .../libraries/ALD/ES32VF2264/Source/ald_i2s.c | 1042 ++++ .../libraries/ALD/ES32VF2264/Source/ald_pis.c | 316 + .../libraries/ALD/ES32VF2264/Source/ald_pmu.c | 219 + .../libraries/ALD/ES32VF2264/Source/ald_rmu.c | 156 + .../libraries/ALD/ES32VF2264/Source/ald_spi.c | 2032 +++++++ .../ALD/ES32VF2264/Source/ald_timer.c | 3642 ++++++++++++ .../ALD/ES32VF2264/Source/ald_uart.c | 1458 +++++ .../libraries/ALD/ES32VF2264/Source/ald_usb.c | 1665 ++++++ .../ALD/ES32VF2264/Source/ald_utils.c | 414 ++ .../libraries/ALD/ES32VF2264/Source/ald_wdt.c | 228 + .../ES32VF2264/Include/ES32VF2264/reg_adc.h | 416 ++ .../ES32VF2264/Include/ES32VF2264/reg_cmu.h | 354 ++ .../ES32VF2264/Include/ES32VF2264/reg_crc.h | 105 + .../ES32VF2264/Include/ES32VF2264/reg_csu.h | 225 + .../ES32VF2264/Include/ES32VF2264/reg_dbg.h | 91 + .../ES32VF2264/Include/ES32VF2264/reg_dma.h | 149 + .../ES32VF2264/Include/ES32VF2264/reg_gpio.h | 334 ++ .../ES32VF2264/Include/ES32VF2264/reg_i2c.h | 564 ++ .../ES32VF2264/Include/ES32VF2264/reg_iwdt.h | 94 + .../ES32VF2264/Include/ES32VF2264/reg_msc.h | 176 + .../ES32VF2264/Include/ES32VF2264/reg_pis.h | 465 ++ .../ES32VF2264/Include/ES32VF2264/reg_pmu.h | 127 + .../ES32VF2264/Include/ES32VF2264/reg_rmu.h | 220 + .../ES32VF2264/Include/ES32VF2264/reg_spi.h | 472 ++ .../Include/ES32VF2264/reg_syscfg.h | 142 + .../ES32VF2264/Include/ES32VF2264/reg_timer.h | 634 ++ .../ES32VF2264/Include/ES32VF2264/reg_uart.h | 547 ++ .../ES32VF2264/Include/ES32VF2264/reg_usb.h | 969 ++++ .../ES32VF2264/Include/ES32VF2264/reg_wwdt.h | 98 + .../EastSoft/ES32VF2264/Include/es32vf2264.h | 177 + .../Device/EastSoft/ES32VF2264/SConscript | 26 + .../ES32VF2264/Startup/startup_es32vf2264.S | 363 ++ .../EastSoft/ES32VF2264/Startup/trap_c.c | 20 + .../EastSoft/ES32VF2264/Svc/es32vf2264.svc | 3997 +++++++++++++ .../ES32VF2264/System/system_es32vf2264.c | 44 + .../libraries/RV_CORE/Include/core_rv32.h | 1187 ++++ .../libraries/RV_CORE/Include/csi_core.h | 54 + .../libraries/RV_CORE/Include/csi_rv32_gcc.h | 2829 +++++++++ bsp/essemi/es32vf2264/libraries/SConscript | 25 + bsp/essemi/es32vf2264/project.cdkproj | 320 + bsp/essemi/es32vf2264/project.cdkws | 10 + bsp/essemi/es32vf2264/rtconfig.h | 251 + bsp/essemi/es32vf2264/rtconfig.py | 104 + bsp/essemi/es32vf2264/template.cdkproj | 244 + bsp/essemi/es32vf2264/template.cdkws | 11 + 118 files changed, 58002 insertions(+) create mode 100644 bsp/essemi/es32vf2264/.config create mode 100644 bsp/essemi/es32vf2264/.ignore_format.yml create mode 100644 bsp/essemi/es32vf2264/Kconfig create mode 100644 bsp/essemi/es32vf2264/README.md create mode 100644 bsp/essemi/es32vf2264/SConscript create mode 100644 bsp/essemi/es32vf2264/SConstruct create mode 100644 bsp/essemi/es32vf2264/applications/SConscript create mode 100644 bsp/essemi/es32vf2264/applications/main.c create mode 100644 bsp/essemi/es32vf2264/drivers/ES/Kconfig create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_adc.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_can.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_cmu.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_dma.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_gpio.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_i2c.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_map.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pm.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pwm.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_rtc.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_select.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_spi.h create mode 100644 bsp/essemi/es32vf2264/drivers/ES/es_conf_info_uart.h create mode 100644 bsp/essemi/es32vf2264/drivers/Kconfig create mode 100644 bsp/essemi/es32vf2264/drivers/SConscript create mode 100644 bsp/essemi/es32vf2264/drivers/board.c create mode 100644 bsp/essemi/es32vf2264/drivers/board.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_adc.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_adc.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_gpio.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_gpio.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_hwtimer.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_hwtimer.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_i2c.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_i2c.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_pm.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_pm.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_pwm.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_pwm.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_spi.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_spi.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_spiflash.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_spiflash.h create mode 100644 bsp/essemi/es32vf2264/drivers/drv_uart.c create mode 100644 bsp/essemi/es32vf2264/drivers/drv_uart.h create mode 100644 bsp/essemi/es32vf2264/drivers/es32vf2264.ld create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_adc.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_cmu.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_conf.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_crc.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_dma.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_gpio.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2c.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2s.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pis.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pmu.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_rmu.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_spi.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_syscfg.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_timer.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_uart.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_usb.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_utils.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_wdt.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/type.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_library_config.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_lowlayer_api.h create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_adc.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_cmu.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_crc.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_dma.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_gpio.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2c.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2s.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pis.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pmu.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_rmu.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_spi.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_timer.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_uart.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_usb.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_utils.c create mode 100644 bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_wdt.c create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_adc.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_cmu.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_crc.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_csu.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dbg.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dma.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_gpio.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_i2c.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_iwdt.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_msc.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pis.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pmu.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_rmu.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_spi.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_syscfg.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_timer.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_uart.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_usb.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_wwdt.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/es32vf2264.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/SConscript create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/startup_es32vf2264.S create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/trap_c.c create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Svc/es32vf2264.svc create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/System/system_es32vf2264.c create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Include/core_rv32.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_core.h create mode 100644 bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_rv32_gcc.h create mode 100644 bsp/essemi/es32vf2264/libraries/SConscript create mode 100644 bsp/essemi/es32vf2264/project.cdkproj create mode 100644 bsp/essemi/es32vf2264/project.cdkws create mode 100644 bsp/essemi/es32vf2264/rtconfig.h create mode 100644 bsp/essemi/es32vf2264/rtconfig.py create mode 100644 bsp/essemi/es32vf2264/template.cdkproj create mode 100644 bsp/essemi/es32vf2264/template.cdkws diff --git a/bsp/essemi/es32vf2264/.config b/bsp/essemi/es32vf2264/.config new file mode 100644 index 0000000000..fa3d3fc624 --- /dev/null +++ b/bsp/essemi/es32vf2264/.config @@ -0,0 +1,1027 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +# CONFIG_RT_USING_HOOK is not set +# CONFIG_RT_USING_IDLE_HOOK is not set +CONFIG_IDLE_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +# CONFIG_RT_USING_EVENT is not set +# CONFIG_RT_USING_MAILBOX is not set +# CONFIG_RT_USING_MESSAGEQUEUE is not set +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="cuart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_ES32VF2264=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +# CONFIG_BSP_USING_EUART0 is not set +# CONFIG_BSP_USING_EUART1 is not set +# CONFIG_BSP_USING_CUART0 is not set +CONFIG_BSP_USING_CUART1=y +# CONFIG_BSP_CUART1_TX_USING_DMA is not set +# CONFIG_BSP_CUART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_CUART2 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPI1 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C0 is not set +# CONFIG_BSP_USING_I2C1 is not set + +# +# ADC Drivers +# +# CONFIG_BSP_USING_ADC0 is not set + +# +# HWTIMER Drivers +# +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T2_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set + +# +# PWM Drivers +# +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T1_PWM is not set +# CONFIG_BSP_USING_GP16C4T2_PWM is not set + +# +# PM Drivers +# +# CONFIG_BSP_USING_PM is not set + +# +# DMA Drivers +# +# CONFIG_BSP_USING_DMA0 is not set + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SPI_FLASH is not set + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/essemi/es32vf2264/.ignore_format.yml b/bsp/essemi/es32vf2264/.ignore_format.yml new file mode 100644 index 0000000000..242d393b1a --- /dev/null +++ b/bsp/essemi/es32vf2264/.ignore_format.yml @@ -0,0 +1,4 @@ +# files format check exclude path, please follow the instructions below to modify; + +dir_path: +- libraries diff --git a/bsp/essemi/es32vf2264/Kconfig b/bsp/essemi/es32vf2264/Kconfig new file mode 100644 index 0000000000..24102e346a --- /dev/null +++ b/bsp/essemi/es32vf2264/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES32VF2264 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/essemi/es32vf2264/README.md b/bsp/essemi/es32vf2264/README.md new file mode 100644 index 0000000000..1c38dfb1cc --- /dev/null +++ b/bsp/essemi/es32vf2264/README.md @@ -0,0 +1,92 @@ +# ES-PDS-ES32VF2264 开发板 BSP 说明 +标签： EastSoft、国产MCU、RISCV、ES32VF2264 + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 ES-PDS-ES32VF2264 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +ES-PDS-ES32VF2264 是东软载波微电子官方推出的一款基于 RISCV E902 内核的开发板，最高主频为 72MHz，可满足基础功能测试及高端功能扩展等开发需求。 + +该开发板常用 **板载资源** 如下： + +- MCU：ES32VF2264LT，主频 72MHz，32KB SRAM，256KB FLASH，51 GPIOs +- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) +- 常用外设 + - 可调电阻：1个(PC02) + - LED：4个，(PC12/PC13/PC14/PA15) + - 按键：6个，PD02、PB06、PB07、PB08、PB09、RESET(MRST) +- 常用接口：GPIO、UART、SPI、I2C、USB +- 调试接口，ESLinkⅡOB(EastSoft 官方推出的开发工具，自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------------------ | +| SPI FLASH | 支持 | SPI0 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | 51 GPIOs | +| UART | 支持 | EUART0/1,CUART0/1/2 | +| SPI | 支持 | SPI0/1 | +| I2C | 支持 | I2C0/1 | +| PWM | 支持 | PWM0/1/2/3 | +| TIMER | 支持 | TIMER0/1/2/3/4 | +| ADC | 支持 | ADC0 | + +### 1.2 注意事项 + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 CDK 工程。下面以 CDK 开发环境为例，介绍如何将系统运行起来。 + +### 硬件连接 + +使用 ESLinkⅡOB (自带 CDC 串口)或 CKlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 CUART1_TX(PA02)、CUART1_RX(PA03)、GND 接到串口工具上。 + +### 编译下载 + +双击 project.uvprojx 文件，打开 CDK 工程，工程默认配置使用ESLinkⅡOB，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 +```bash + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build May 8 2023 19:32:03 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 cuart1 的功能，如果需使用更多高级功能，可以使用ES-CodeMaker进行更多的芯片配置。然后利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + + a）如果需要使用内核用例，先配置rt-thread内核，然后配置内核用例。 + + b）如果需要使用驱动用例：先使能驱动，然后配置驱动用例。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=cdk。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [liuhongyan](https://gitee.com/liuhongyan98) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/essemi/es32vf2264/SConscript b/bsp/essemi/es32vf2264/SConscript new file mode 100644 index 0000000000..468297b6a9 --- /dev/null +++ b/bsp/essemi/es32vf2264/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/essemi/es32vf2264/SConstruct b/bsp/essemi/es32vf2264/SConstruct new file mode 100644 index 0000000000..fef9564af4 --- /dev/null +++ b/bsp/essemi/es32vf2264/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'project.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es32vf2264/applications/SConscript b/bsp/essemi/es32vf2264/applications/SConscript new file mode 100644 index 0000000000..e0c84e8f14 --- /dev/null +++ b/bsp/essemi/es32vf2264/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32vf2264/applications/main.c b/bsp/essemi/es32vf2264/applications/main.c new file mode 100644 index 0000000000..35ab880a19 --- /dev/null +++ b/bsp/essemi/es32vf2264/applications/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-05-08 liuhy the first version + */ + +#include "board.h" + +#ifdef ES_RTT_APP_LED_PIN +#define LED_PIN ES_RTT_APP_LED_PIN +#else +#define LED_PIN GET_PIN( C , 12 ) +#endif + +int main(void) +{ + int count = 1; + /* set pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + return RT_EOK; +} + diff --git a/bsp/essemi/es32vf2264/drivers/ES/Kconfig b/bsp/essemi/es32vf2264/drivers/ES/Kconfig new file mode 100644 index 0000000000..8c2fffd7b4 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/Kconfig @@ -0,0 +1,195 @@ +menu "UART Drivers" + + config BSP_USING_EUART0 + bool "Register EUART0 " + select RT_USING_SERIAL + default y + + if BSP_USING_EUART0 + config BSP_EUART0_TX_USING_DMA + bool "EUART0 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_EUART0_RX_USING_DMA + bool "EUART0 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_EUART1 + bool "Register EUART1 " + select RT_USING_SERIAL + default n + + if BSP_USING_EUART1 + config BSP_EUART1_TX_USING_DMA + bool "EUART1 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_EUART1_RX_USING_DMA + bool "EUART1 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_CUART0 + bool "Register CUART0 " + select RT_USING_SERIAL + default y + + if BSP_USING_CUART0 + config BSP_CUART0_TX_USING_DMA + bool "CUART0 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_CUART0_RX_USING_DMA + bool "CUART0 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_CUART1 + bool "Register CUART1 " + select RT_USING_SERIAL + default n + + if BSP_USING_CUART1 + config BSP_CUART1_TX_USING_DMA + bool "CUART1 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_CUART1_RX_USING_DMA + bool "CUART1 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_CUART2 + bool "Register CUART2 " + select RT_USING_SERIAL + default n + + if BSP_USING_CUART2 + config BSP_CUART2_TX_USING_DMA + bool "CUART2 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_CUART2_RX_USING_DMA + bool "CUART2 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1 " + select RT_USING_SPI + select RT_USING_PIN + default n + +endmenu + +menu "I2C Drivers" + + config BSP_USING_I2C0 + bool "Register I2C0 " + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1 " + select RT_USING_I2C + default n + +endmenu + +menu "ADC Drivers" + + config BSP_USING_ADC0 + bool "Register ADC0 " + select RT_USING_ADC + default n + +endmenu + +menu "HWTIMER Drivers" + + config BSP_USING_AD16C4T0_HWTIMER + bool "Register HWTIMER0 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register HWTIMER1 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T1_HWTIMER + bool "Register HWTIMER2 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T2_HWTIMER + bool "Register HWTIMER3 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T0_HWTIMER + bool "Register HWTIMER4 " + select RT_USING_HWTIMER + default n + +endmenu + +menu "PWM Drivers" + + config BSP_USING_AD16C4T0_PWM + bool "Register PWM0 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T0_HWTIMER + + config BSP_USING_GP16C4T0_PWM + bool "Register PWM1 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T0_HWTIMER + + config BSP_USING_GP16C4T1_PWM + bool "Register PWM2 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T1_HWTIMER + + config BSP_USING_GP16C4T2_PWM + bool "Register PWM3 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T1_HWTIMER + +endmenu + +menu "PM Drivers" + + config BSP_USING_PM + bool "Register PM " + select RT_USING_PM + default n + +endmenu + +menu "DMA Drivers" + config BSP_USING_DMA0 + bool "Using DMA0 " + select ES_CONF_DMA_ENABLE + default n +endmenu diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..a2731802d9 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,80 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include + + +#define ES_C_ADC_CLK_DIV_1 ALD_ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ALD_ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ALD_ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ALD_ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ALD_ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ALD_ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ALD_ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ALD_ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ALD_ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ALD_ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ALD_ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ALD_ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ALD_ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ALD_ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ALD_ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ALD_ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ALD_ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ALD_ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_16 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..7254f5660b --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include +#include + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_DISABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..5afec55bee --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +/* 时钟树 配置 */ + +#define ES_C_DIV_1 ALD_CMU_DIV_1 +#define ES_C_DIV_2 ALD_CMU_DIV_2 +#define ES_C_DIV_4 ALD_CMU_DIV_4 +#define ES_C_DIV_8 ALD_CMU_DIV_8 +#define ES_C_DIV_16 ALD_CMU_DIV_16 +#define ES_C_DIV_32 ALD_CMU_DIV_32 +#define ES_C_DIV_64 ALD_CMU_DIV_64 +#define ES_C_DIV_128 ALD_CMU_DIV_128 +#define ES_C_DIV_256 ALD_CMU_DIV_256 +#define ES_C_DIV_512 ALD_CMU_DIV_512 +#define ES_C_DIV_1024 ALD_CMU_DIV_1024 +#define ES_C_DIV_2048 ALD_CMU_DIV_2048 +#define ES_C_DIV_4096 ALD_CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 ALD_CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 ALD_CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 ALD_CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 ALD_CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 ALD_CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 ALD_CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 ALD_CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_PLL_REF_HOSC8M +#define ES_PLL1_OUT_CLK ES_C_PLL_OUT_72M +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_HOSM_SAFE_EN ES_C_DISABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HRC4M_EN ES_C_ENABLE +#define ES_CMU_HRC48M_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_PCLK_DIV ES_C_DIV_1 +#define ES_CMU_UART_BUAND_MAX XXXXXX +#define ES_CMU_UART_BUAND_MIN XXXXXX +#define ES_CMU_SPI_BUAND_MAX XXXXXX +#define ES_CMU_SPI_BUAND_MIN XXXXXX +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL +#define ES_SYS_SOURCE_CLK 72000000 +#define ES_PCLK_CLK 72000000 +#define ES_SYS_HCLK_CLK 72000000 +#define ES_CMU_EXTERN_CLK_HOSC 8000000 + + + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_dma.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_dma.h new file mode 100644 index 0000000000..04d6cf5fd7 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_dma.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. + * + */ + +#ifndef __ES_CONF_INFO_DMA_H__ +#define __ES_CONF_INFO_DMA_H__ + +#include "rtconfig.h" + +#ifdef BSP_EUART0_TX_USING_DMA +#endif + +#ifdef BSP_CUART2_TX_USING_DMA +#define ES_CONF_CUART2_DMA_TX +#endif +#ifdef BSP_CUART2_RX_USING_DMA +#define ES_CONF_CUART2_DMA_RX +#endif + + +enum ES_DMA_CHANNELS +{ +#ifdef ES_CONF_EUART0_DMA_TX + ES_EUART0_DMATX_CHANNEL, +#endif +#ifdef ES_CONF_EUART0_DMA_RX + ES_EUART0_DMARX_CHANNEL, +#endif +#ifdef ES_CONF_EUART1_DMA_TX + ES_EUART1_DMATX_CHANNEL, +#endif +#ifdef ES_CONF_EUART1_DMA_RX + ES_EUART1_DMARX_CHANNEL, +#endif +#ifdef ES_CONF_CUART0_DMA_TX + ES_CUART0_DMATX_CHANNEL, +#endif +#ifdef ES_CONF_CUART0_DMA_RX + ES_CUART0_DMARX_CHANNEL, +#endif +#ifdef ES_CONF_CUART1_DMA_TX + ES_CUART1_DMATX_CHANNEL, +#endif +#ifdef ES_CONF_CUART1_DMA_RX + ES_CUART1_DMARX_CHANNEL, +#endif +#ifdef ES_CONF_CUART2_DMA_TX + ES_CUART2_DMATX_CHANNEL, +#endif +#ifdef ES_CONF_CUART2_DMA_RX + ES_CUART2_DMARX_CHANNEL, +#endif +#ifdef ES_SPI0_I2S_MODE + ES_SPI0_I2S_DMATX_CHANNEL, + ES_SPI0_I2S_DMARX_CHANNEL, +#endif +#ifdef ES_SPI1_I2S_MODE + ES_SPI1_I2S_DMATX_CHANNEL, + ES_SPI1_I2S_DMARX_CHANNEL, +#endif + ES_DMA_CHANNEL_NUM +}; +#define ES_DMA_INVAILD_CHANNEL (ES_DMA_CHANNEL_NUM) +#define ES_DMA_USER_CHANNEL (ES_DMA_CHANNEL_NUM) + +#endif /* __ES_CONF_INFO_DMA_H__ */ diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..4102224f8d --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5155 @@ +/* + * Change Logs: + * Date Author Notes + * 2022-02-10 Lisq the first version + * + * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ +//#define ES_INIT_PIN_GPIO_C_8 +//#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_ENABLE + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..f712810bcb --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,103 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include +#include + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T1_HWTIMER_MODE +#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T2_HWTIMER_MODE +#define ES_GP16C4T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T2_HWTIMER_MODE +#define ES_BS16T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T3_HWTIMER_MODE +#define ES_BS16T3_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C2T0_HWTIMER_PRES 1 +#define ES_GP16C2T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 +#define ES_BS16T2_HWTIMER_PRES 1 +#define ES_BS16T3_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER +#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T2_HWTIMER +#define ES_DEVICE_NAME_GP16C4T2_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T2_HWTIMER +#define ES_DEVICE_NAME_BS16T2_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T3_HWTIMER +#define ES_DEVICE_NAME_BS16T3_HWTIMER "timer7" +#endif + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..41a1723454 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +#define ES_C_I2C_STRETCH ALD_I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH ALD_I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL ALD_I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL ALD_I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE ALD_I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE ALD_I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..2db7dee600 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_map.h @@ -0,0 +1,3804 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include "ald_conf.h" + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, ALD_GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +#if 0 +#define ES_GPIO_ADC_CH10_GPIO GPIOC +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH11_GPIO GPIOC +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH0_GPIO GPIOA +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_GPIO GPIOA +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_GPIO GPIOA +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_GPIO GPIOA +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH14_GPIO GPIOC +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH15_GPIO GPIOC +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH8_GPIO GPIOB +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH9_GPIO GPIOB +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH15_GPIO GPIOB +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_8 + + + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2,C,13), + __ES_PIN(3,C,14), + __ES_PIN(4,C,15), + __ES_PIN(5,D,0), + __ES_PIN(6,D,1), + __ES_PIN_DEFAULT, + __ES_PIN(8,C,0), + __ES_PIN(9,C,1), + __ES_PIN(10,C,2), + __ES_PIN(11,C,3), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(14,A,0), + __ES_PIN(15,A,1), + __ES_PIN(16,A,2), + __ES_PIN(17,A,3), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(20,A,4), + __ES_PIN(21,A,5), + __ES_PIN(22,A,6), + __ES_PIN(23,A,7), + __ES_PIN(24,C,4), + __ES_PIN(25,C,5), + __ES_PIN(26,B,0), + __ES_PIN(27,B,1), + __ES_PIN(28,B,2), + __ES_PIN(29,B,10), + __ES_PIN(30,B,11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33,B,12), + __ES_PIN(34,B,13), + __ES_PIN(35,B,14), + __ES_PIN(36,B,15), + __ES_PIN(37,C,6), + __ES_PIN(38,C,7), + __ES_PIN(39,C,8), + __ES_PIN(40,C,9), + __ES_PIN(41,A,8), + __ES_PIN(42,A,9), + __ES_PIN(43,A,10), + __ES_PIN(44,A,11), + __ES_PIN(45,A,12), + __ES_PIN(46,A,13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49,A,14), + __ES_PIN(50,A,15), + __ES_PIN(51,C,10), + __ES_PIN(52,C,11), + __ES_PIN(53,C,12), + __ES_PIN(54,D,2), + __ES_PIN(55,B,3), + __ES_PIN(56,B,4), + __ES_PIN(57,B,5), + __ES_PIN(58,B,6), + __ES_PIN(59,B,7), + __ES_PIN_DEFAULT, + __ES_PIN(61,B,8), + __ES_PIN(62,B,9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#endif + + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH0_PIN ALD_GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH1_PIN ALD_GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH2_PIN ALD_GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH3_PIN ALD_GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_GPIO GPIOC +#define ES_GPIO_ADC_CH4_PIN ALD_GPIO_PIN_4 +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH5_PIN ALD_GPIO_PIN_5 +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH6_PIN ALD_GPIO_PIN_6 +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH7_PIN ALD_GPIO_PIN_7 +#define ES_GPIO_ADC_CH8_GPIO GPIOB +#define ES_GPIO_ADC_CH8_PIN ALD_GPIO_PIN_0 +#define ES_GPIO_ADC_CH9_GPIO GPIOB +#define ES_GPIO_ADC_CH9_PIN ALD_GPIO_PIN_1 +#define ES_GPIO_ADC_CH10_GPIO GPIOC +#define ES_GPIO_ADC_CH10_PIN ALD_GPIO_PIN_5 +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH11_PIN ALD_GPIO_PIN_0 +#define ES_GPIO_ADC_CH12_GPIO GPIOA +#define ES_GPIO_ADC_CH12_PIN ALD_GPIO_PIN_1 +#define ES_GPIO_ADC_CH13_GPIO GPIOA +#define ES_GPIO_ADC_CH13_PIN ALD_GPIO_PIN_2 +#define ES_GPIO_ADC_CH14_GPIO GPIOA +#define ES_GPIO_ADC_CH14_PIN ALD_GPIO_PIN_3 +#define ES_GPIO_ADC_CH15_GPIO GPIOA +#define ES_GPIO_ADC_CH15_PIN ALD_GPIO_PIN_4 +#define ES_GPIO_ADC_CH16_GPIO GPIOB +#define ES_GPIO_ADC_CH16_PIN ALD_GPIO_PIN_8 + + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN(1,C,13), + __ES_PIN(2,C,14), + __ES_PIN(3,C,15), + __ES_PIN(4,D,0), + __ES_PIN(5,D,1), + __ES_PIN(6,C,0), + __ES_PIN(7,C,1), + __ES_PIN(8,C,2), + __ES_PIN(9,C,3), + __ES_PIN(10,A,0), + __ES_PIN(11,A,1), + __ES_PIN(12,A,2), + __ES_PIN(13,A,3), + __ES_PIN(14,A,4), + __ES_PIN(15,A,5), + __ES_PIN(16,A,6), + __ES_PIN(17,A,7), + __ES_PIN(18,C,4), + __ES_PIN(19,C,5), + __ES_PIN(20,B,0), + __ES_PIN(21,B,1), + __ES_PIN(22,B,2), + __ES_PIN(23,B,10), + __ES_PIN(24,B,11), + __ES_PIN(25,B,12), + __ES_PIN(26,B,13), + __ES_PIN(27,B,14), + __ES_PIN(28,B,15), + __ES_PIN(29,C,6), + __ES_PIN(30,C,7), + __ES_PIN(31,C,8), + __ES_PIN(32,C,9), + __ES_PIN(33,A,8), + __ES_PIN(34,A,9), + __ES_PIN(35,A,10), + __ES_PIN(36,A,11), + __ES_PIN(37,A,12), + __ES_PIN(38,A,13), + __ES_PIN(39,A,14), + __ES_PIN(40,A,15), + __ES_PIN(41,C,10), + __ES_PIN(42,C,11), + __ES_PIN(43,C,12), + __ES_PIN(44,D,2), + __ES_PIN(45,B,3), + __ES_PIN(46,B,4), + __ES_PIN(47,B,5), + __ES_PIN(48,B,6), + __ES_PIN(49,B,7), + __ES_PIN(50,B,8), + __ES_PIN(51,B,9), +}; + +#define ES_PIN_GPIO_C_13 1 +#define ES_PIN_GPIO_C_14 2 +#define ES_PIN_GPIO_C_15 3 +#define ES_PIN_GPIO_D_0 4 +#define ES_PIN_GPIO_D_1 5 +#define ES_PIN_GPIO_C_0 6 +#define ES_PIN_GPIO_C_1 7 +#define ES_PIN_GPIO_C_2 8 +#define ES_PIN_GPIO_C_3 9 +#define ES_PIN_GPIO_A_0 10 +#define ES_PIN_GPIO_A_1 11 +#define ES_PIN_GPIO_A_2 12 +#define ES_PIN_GPIO_A_3 13 +#define ES_PIN_GPIO_A_4 14 +#define ES_PIN_GPIO_A_5 15 +#define ES_PIN_GPIO_A_6 16 +#define ES_PIN_GPIO_A_7 17 +#define ES_PIN_GPIO_C_4 18 +#define ES_PIN_GPIO_C_5 19 +#define ES_PIN_GPIO_B_0 20 +#define ES_PIN_GPIO_B_1 21 +#define ES_PIN_GPIO_B_2 22 +#define ES_PIN_GPIO_B_10 23 +#define ES_PIN_GPIO_B_11 24 +#define ES_PIN_GPIO_B_12 25 +#define ES_PIN_GPIO_B_13 26 +#define ES_PIN_GPIO_B_14 27 +#define ES_PIN_GPIO_B_15 28 +#define ES_PIN_GPIO_C_6 29 +#define ES_PIN_GPIO_C_7 30 +#define ES_PIN_GPIO_C_8 31 +#define ES_PIN_GPIO_C_9 32 +#define ES_PIN_GPIO_A_8 33 +#define ES_PIN_GPIO_A_9 34 +#define ES_PIN_GPIO_A_10 35 +#define ES_PIN_GPIO_A_11 36 +#define ES_PIN_GPIO_A_12 37 +#define ES_PIN_GPIO_A_13 38 +#define ES_PIN_GPIO_A_14 39 +#define ES_PIN_GPIO_A_15 40 +#define ES_PIN_GPIO_C_10 41 +#define ES_PIN_GPIO_C_11 42 +#define ES_PIN_GPIO_C_12 43 +#define ES_PIN_GPIO_D_2 44 +#define ES_PIN_GPIO_B_3 45 +#define ES_PIN_GPIO_B_4 46 +#define ES_PIN_GPIO_B_5 47 +#define ES_PIN_GPIO_B_6 48 +#define ES_PIN_GPIO_B_7 49 +#define ES_PIN_GPIO_B_8 50 +#define ES_PIN_GPIO_B_9 51 + + +#if 1 + +#ifndef ES_MAP__PIN_PA2_USED +#define ES_MAP__PIN_PA2_USED +#ifndef ES_CUART1_TX_GPIO_FUNC +#define ES_CUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_TX_GPIO_PORT +#define ES_CUART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART1_TX_GPIO_PIN +#define ES_CUART1_TX_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_CUART1_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_CUART1_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif +#endif + +#ifndef ES_MAP__PIN_PA3_USED +#define ES_MAP__PIN_PA3_USED +#ifndef ES_CUART1_RX_GPIO_FUNC +#define ES_CUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_RX_GPIO_PORT +#define ES_CUART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART1_RX_GPIO_PIN +#define ES_CUART1_RX_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_CUART1_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_CUART1_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif +#endif + +#ifndef ES_MAP__PIN_PA7_USED +#define ES_MAP__PIN_PA7_USED +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif +#endif + +#ifndef ES_MAP__PIN_PA6_USED +#define ES_MAP__PIN_PA6_USED +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif +#endif + +#ifndef ES_MAP__PIN_PB2_USED +#define ES_MAP__PIN_PB2_USED +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_2 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_2 +#endif +#endif +#endif + +#ifndef ES_MAP__PIN_PB3_USED +#define ES_MAP__PIN_PB3_USED +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_3 +#endif +#endif +#endif + +#endif + +#if 1 + +#ifndef ES_MAP__PIN_PC13_USED +#define ES_MAP__PIN_PC13_USED +#ifndef ES_EUART1_RX_GPIO_FUNC +#define ES_EUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_EUART1_RX_GPIO_PORT +#define ES_EUART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART1_RX_GPIO_PIN +#define ES_EUART1_RX_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_EUART1_RX_PIN +#ifdef ES_PIN_GPIO_C_13 +#define ES_EUART1_RX_PIN ES_PIN_GPIO_C_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC13_USED +#define ES_MAP__PIN_PC13_USED +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_C_13 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_C_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC13_USED +#define ES_MAP__PIN_PC13_USED +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC14_USED +#define ES_MAP__PIN_PC14_USED +#ifndef ES_EUART1_TX_GPIO_FUNC +#define ES_EUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_EUART1_TX_GPIO_PORT +#define ES_EUART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART1_TX_GPIO_PIN +#define ES_EUART1_TX_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_EUART1_TX_PIN +#ifdef ES_PIN_GPIO_C_14 +#define ES_EUART1_TX_PIN ES_PIN_GPIO_C_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC14_USED +#define ES_MAP__PIN_PC14_USED +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_C_14 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_C_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC14_USED +#define ES_MAP__PIN_PC14_USED +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC15_USED +#define ES_MAP__PIN_PC15_USED +#ifndef ES_GP16C4T2_CH4_GPIO_FUNC +#define ES_GP16C4T2_CH4_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T2_CH4_GPIO_PORT +#define ES_GP16C4T2_CH4_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T2_CH4_GPIO_PIN +#define ES_GP16C4T2_CH4_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T2_CH4_PIN +#ifdef ES_PIN_GPIO_C_15 +#define ES_GP16C4T2_CH4_PIN ES_PIN_GPIO_C_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC15_USED +#define ES_MAP__PIN_PC15_USED +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_C_15 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_C_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC15_USED +#define ES_MAP__PIN_PC15_USED +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD0_USED +#define ES_MAP__PIN_PD0_USED +#ifndef ES_CUART2_RX_GPIO_FUNC +#define ES_CUART2_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART2_RX_GPIO_PORT +#define ES_CUART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_CUART2_RX_GPIO_PIN +#define ES_CUART2_RX_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_CUART2_RX_PIN +#ifdef ES_PIN_GPIO_D_0 +#define ES_CUART2_RX_PIN ES_PIN_GPIO_D_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD0_USED +#define ES_MAP__PIN_PD0_USED +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_D_0 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_D_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD0_USED +#define ES_MAP__PIN_PD0_USED +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC ALD_GPIO_FUNC_7 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOD +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_D_0 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_D_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD1_USED +#define ES_MAP__PIN_PD1_USED +#ifndef ES_CUART2_TX_GPIO_FUNC +#define ES_CUART2_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART2_TX_GPIO_PORT +#define ES_CUART2_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_CUART2_TX_GPIO_PIN +#define ES_CUART2_TX_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_CUART2_TX_PIN +#ifdef ES_PIN_GPIO_D_1 +#define ES_CUART2_TX_PIN ES_PIN_GPIO_D_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD1_USED +#define ES_MAP__PIN_PD1_USED +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_D_1 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_D_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD1_USED +#define ES_MAP__PIN_PD1_USED +#ifndef ES_GP16C4T2_CH3_GPIO_FUNC +#define ES_GP16C4T2_CH3_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T2_CH3_GPIO_PORT +#define ES_GP16C4T2_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T2_CH3_GPIO_PIN +#define ES_GP16C4T2_CH3_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_GP16C4T2_CH3_PIN +#ifdef ES_PIN_GPIO_D_1 +#define ES_GP16C4T2_CH3_PIN ES_PIN_GPIO_D_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD1_USED +#define ES_MAP__PIN_PD1_USED +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_D_1 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_D_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD1_USED +#define ES_MAP__PIN_PD1_USED +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC ALD_GPIO_FUNC_7 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOD +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_D_1 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_D_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC0_USED +#define ES_MAP__PIN_PC0_USED +#ifndef ES_CUART1_TX_GPIO_FUNC +#define ES_CUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_TX_GPIO_PORT +#define ES_CUART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_CUART1_TX_GPIO_PIN +#define ES_CUART1_TX_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_CUART1_TX_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_CUART1_TX_PIN ES_PIN_GPIO_C_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC0_USED +#define ES_MAP__PIN_PC0_USED +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_C_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC0_USED +#define ES_MAP__PIN_PC0_USED +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_C_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC0_USED +#define ES_MAP__PIN_PC0_USED +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_C_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC1_USED +#define ES_MAP__PIN_PC1_USED +#ifndef ES_CUART1_RX_GPIO_FUNC +#define ES_CUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_RX_GPIO_PORT +#define ES_CUART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_CUART1_RX_GPIO_PIN +#define ES_CUART1_RX_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_CUART1_RX_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_CUART1_RX_PIN ES_PIN_GPIO_C_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC1_USED +#define ES_MAP__PIN_PC1_USED +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_C_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC1_USED +#define ES_MAP__PIN_PC1_USED +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_C_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC1_USED +#define ES_MAP__PIN_PC1_USED +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_C_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC2_USED +#define ES_MAP__PIN_PC2_USED +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_C_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC2_USED +#define ES_MAP__PIN_PC2_USED +#ifndef ES_GP16C4T2_CH1_GPIO_FUNC +#define ES_GP16C4T2_CH1_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_CH1_GPIO_PORT +#define ES_GP16C4T2_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T2_CH1_GPIO_PIN +#define ES_GP16C4T2_CH1_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T2_CH1_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_GP16C4T2_CH1_PIN ES_PIN_GPIO_C_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC3_USED +#define ES_MAP__PIN_PC3_USED +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_C_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC3_USED +#define ES_MAP__PIN_PC3_USED +#ifndef ES_GP16C4T2_CH2_GPIO_FUNC +#define ES_GP16C4T2_CH2_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_CH2_GPIO_PORT +#define ES_GP16C4T2_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T2_CH2_GPIO_PIN +#define ES_GP16C4T2_CH2_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T2_CH2_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_GP16C4T2_CH2_PIN ES_PIN_GPIO_C_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA0_USED +#define ES_MAP__PIN_PA0_USED +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA0_USED +#define ES_MAP__PIN_PA0_USED +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA0_USED +#define ES_MAP__PIN_PA0_USED +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA1_USED +#define ES_MAP__PIN_PA1_USED +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA1_USED +#define ES_MAP__PIN_PA1_USED +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA1_USED +#define ES_MAP__PIN_PA1_USED +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA2_USED +#define ES_MAP__PIN_PA2_USED +#ifndef ES_CUART1_TX_GPIO_FUNC +#define ES_CUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_TX_GPIO_PORT +#define ES_CUART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART1_TX_GPIO_PIN +#define ES_CUART1_TX_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_CUART1_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_CUART1_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA2_USED +#define ES_MAP__PIN_PA2_USED +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA2_USED +#define ES_MAP__PIN_PA2_USED +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA2_USED +#define ES_MAP__PIN_PA2_USED +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA3_USED +#define ES_MAP__PIN_PA3_USED +#ifndef ES_CUART1_RX_GPIO_FUNC +#define ES_CUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_RX_GPIO_PORT +#define ES_CUART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART1_RX_GPIO_PIN +#define ES_CUART1_RX_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_CUART1_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_CUART1_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA3_USED +#define ES_MAP__PIN_PA3_USED +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA3_USED +#define ES_MAP__PIN_PA3_USED +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA3_USED +#define ES_MAP__PIN_PA3_USED +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA4_USED +#define ES_MAP__PIN_PA4_USED +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA4_USED +#define ES_MAP__PIN_PA4_USED +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_GP16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_GP16C4T1_CH3_PIN ES_PIN_GPIO_A_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA5_USED +#define ES_MAP__PIN_PA5_USED +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA5_USED +#define ES_MAP__PIN_PA5_USED +#ifndef ES_EUART1_RX_GPIO_FUNC +#define ES_EUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_EUART1_RX_GPIO_PORT +#define ES_EUART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_EUART1_RX_GPIO_PIN +#define ES_EUART1_RX_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_EUART1_RX_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_EUART1_RX_PIN ES_PIN_GPIO_A_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA5_USED +#define ES_MAP__PIN_PA5_USED +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_GP16C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_GP16C4T1_CH4_PIN ES_PIN_GPIO_A_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA5_USED +#define ES_MAP__PIN_PA5_USED +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC ALD_GPIO_FUNC_7 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA6_USED +#define ES_MAP__PIN_PA6_USED +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA6_USED +#define ES_MAP__PIN_PA6_USED +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP16C4T1_CH1_PIN ES_PIN_GPIO_A_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA6_USED +#define ES_MAP__PIN_PA6_USED +#ifndef ES_GP16C4T2_ET_GPIO_FUNC +#define ES_GP16C4T2_ET_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_ET_GPIO_PORT +#define ES_GP16C4T2_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T2_ET_GPIO_PIN +#define ES_GP16C4T2_ET_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T2_ET_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP16C4T2_ET_PIN ES_PIN_GPIO_A_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA6_USED +#define ES_MAP__PIN_PA6_USED +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC ALD_GPIO_FUNC_7 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA7_USED +#define ES_MAP__PIN_PA7_USED +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA7_USED +#define ES_MAP__PIN_PA7_USED +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_GP16C4T1_CH2_PIN ES_PIN_GPIO_A_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA7_USED +#define ES_MAP__PIN_PA7_USED +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC4_USED +#define ES_MAP__PIN_PC4_USED +#ifndef ES_EUART1_RX_GPIO_FUNC +#define ES_EUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_EUART1_RX_GPIO_PORT +#define ES_EUART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART1_RX_GPIO_PIN +#define ES_EUART1_RX_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_EUART1_RX_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_EUART1_RX_PIN ES_PIN_GPIO_C_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC4_USED +#define ES_MAP__PIN_PC4_USED +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_C_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC4_USED +#define ES_MAP__PIN_PC4_USED +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_C_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC4_USED +#define ES_MAP__PIN_PC4_USED +#ifndef ES_GP16C4T2_CH3_GPIO_FUNC +#define ES_GP16C4T2_CH3_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_CH3_GPIO_PORT +#define ES_GP16C4T2_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T2_CH3_GPIO_PIN +#define ES_GP16C4T2_CH3_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_GP16C4T2_CH3_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_GP16C4T2_CH3_PIN ES_PIN_GPIO_C_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC5_USED +#define ES_MAP__PIN_PC5_USED +#ifndef ES_EUART1_TX_GPIO_FUNC +#define ES_EUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_EUART1_TX_GPIO_PORT +#define ES_EUART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART1_TX_GPIO_PIN +#define ES_EUART1_TX_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_EUART1_TX_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_EUART1_TX_PIN ES_PIN_GPIO_C_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC5_USED +#define ES_MAP__PIN_PC5_USED +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_C_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC5_USED +#define ES_MAP__PIN_PC5_USED +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_GP16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_GP16C4T1_ET_PIN ES_PIN_GPIO_C_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB0_USED +#define ES_MAP__PIN_PB0_USED +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_GP16C4T1_CH3_PIN ES_PIN_GPIO_B_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB0_USED +#define ES_MAP__PIN_PB0_USED +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB0_USED +#define ES_MAP__PIN_PB0_USED +#ifndef ES_CUART0_RX_GPIO_FUNC +#define ES_CUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_CUART0_RX_GPIO_PORT +#define ES_CUART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART0_RX_GPIO_PIN +#define ES_CUART0_RX_GPIO_PIN ALD_GPIO_PIN_0 +#endif + +#ifndef ES_CUART0_RX_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_CUART0_RX_PIN ES_PIN_GPIO_B_0 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB1_USED +#define ES_MAP__PIN_PB1_USED +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_GP16C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_GP16C4T1_CH4_PIN ES_PIN_GPIO_B_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB1_USED +#define ES_MAP__PIN_PB1_USED +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB1_USED +#define ES_MAP__PIN_PB1_USED +#ifndef ES_CUART0_TX_GPIO_FUNC +#define ES_CUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_CUART0_TX_GPIO_PORT +#define ES_CUART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART0_TX_GPIO_PIN +#define ES_CUART0_TX_GPIO_PIN ALD_GPIO_PIN_1 +#endif + +#ifndef ES_CUART0_TX_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_CUART0_TX_PIN ES_PIN_GPIO_B_1 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB2_USED +#define ES_MAP__PIN_PB2_USED +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_2 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB2_USED +#define ES_MAP__PIN_PB2_USED +#ifndef ES_EUART0_RX_GPIO_FUNC +#define ES_EUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_EUART0_RX_GPIO_PORT +#define ES_EUART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART0_RX_GPIO_PIN +#define ES_EUART0_RX_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_EUART0_RX_PIN +#ifdef ES_PIN_GPIO_B_2 +#define ES_EUART0_RX_PIN ES_PIN_GPIO_B_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB2_USED +#define ES_MAP__PIN_PB2_USED +#ifndef ES_EUART1_TX_GPIO_FUNC +#define ES_EUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_EUART1_TX_GPIO_PORT +#define ES_EUART1_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART1_TX_GPIO_PIN +#define ES_EUART1_TX_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_EUART1_TX_PIN +#ifdef ES_PIN_GPIO_B_2 +#define ES_EUART1_TX_PIN ES_PIN_GPIO_B_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB2_USED +#define ES_MAP__PIN_PB2_USED +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_2 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB10_USED +#define ES_MAP__PIN_PB10_USED +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB10_USED +#define ES_MAP__PIN_PB10_USED +#ifndef ES_CUART2_TX_GPIO_FUNC +#define ES_CUART2_TX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_CUART2_TX_GPIO_PORT +#define ES_CUART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART2_TX_GPIO_PIN +#define ES_CUART2_TX_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_CUART2_TX_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_CUART2_TX_PIN ES_PIN_GPIO_B_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB10_USED +#define ES_MAP__PIN_PB10_USED +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB10_USED +#define ES_MAP__PIN_PB10_USED +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB11_USED +#define ES_MAP__PIN_PB11_USED +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB11_USED +#define ES_MAP__PIN_PB11_USED +#ifndef ES_CUART2_RX_GPIO_FUNC +#define ES_CUART2_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_CUART2_RX_GPIO_PORT +#define ES_CUART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART2_RX_GPIO_PIN +#define ES_CUART2_RX_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_CUART2_RX_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_CUART2_RX_PIN ES_PIN_GPIO_B_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB11_USED +#define ES_MAP__PIN_PB11_USED +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB11_USED +#define ES_MAP__PIN_PB11_USED +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB12_USED +#define ES_MAP__PIN_PB12_USED +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN ALD_GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_B_12 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB13_USED +#define ES_MAP__PIN_PB13_USED +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB13_USED +#define ES_MAP__PIN_PB13_USED +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB14_USED +#define ES_MAP__PIN_PB14_USED +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB14_USED +#define ES_MAP__PIN_PB14_USED +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB14_USED +#define ES_MAP__PIN_PB14_USED +#ifndef ES_GP16C4T2_CH1_GPIO_FUNC +#define ES_GP16C4T2_CH1_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_CH1_GPIO_PORT +#define ES_GP16C4T2_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T2_CH1_GPIO_PIN +#define ES_GP16C4T2_CH1_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T2_CH1_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_GP16C4T2_CH1_PIN ES_PIN_GPIO_B_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB15_USED +#define ES_MAP__PIN_PB15_USED +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB15_USED +#define ES_MAP__PIN_PB15_USED +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB15_USED +#define ES_MAP__PIN_PB15_USED +#ifndef ES_EUART0_RX_GPIO_FUNC +#define ES_EUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_EUART0_RX_GPIO_PORT +#define ES_EUART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART0_RX_GPIO_PIN +#define ES_EUART0_RX_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_EUART0_RX_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_EUART0_RX_PIN ES_PIN_GPIO_B_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB15_USED +#define ES_MAP__PIN_PB15_USED +#ifndef ES_GP16C4T2_CH2_GPIO_FUNC +#define ES_GP16C4T2_CH2_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_CH2_GPIO_PORT +#define ES_GP16C4T2_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T2_CH2_GPIO_PIN +#define ES_GP16C4T2_CH2_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T2_CH2_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_GP16C4T2_CH2_PIN ES_PIN_GPIO_B_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC6_USED +#define ES_MAP__PIN_PC6_USED +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC6_USED +#define ES_MAP__PIN_PC6_USED +#ifndef ES_EUART0_RX_GPIO_FUNC +#define ES_EUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_EUART0_RX_GPIO_PORT +#define ES_EUART0_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART0_RX_GPIO_PIN +#define ES_EUART0_RX_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_EUART0_RX_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_EUART0_RX_PIN ES_PIN_GPIO_C_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC6_USED +#define ES_MAP__PIN_PC6_USED +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_GP16C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC7_USED +#define ES_MAP__PIN_PC7_USED +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_C_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC7_USED +#define ES_MAP__PIN_PC7_USED +#ifndef ES_EUART0_TX_GPIO_FUNC +#define ES_EUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_EUART0_TX_GPIO_PORT +#define ES_EUART0_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART0_TX_GPIO_PIN +#define ES_EUART0_TX_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_EUART0_TX_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_EUART0_TX_PIN ES_PIN_GPIO_C_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC7_USED +#define ES_MAP__PIN_PC7_USED +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_GP16C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC7_USED +#define ES_MAP__PIN_PC7_USED +#ifndef ES_CUART0_RX_GPIO_FUNC +#define ES_CUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_CUART0_RX_GPIO_PORT +#define ES_CUART0_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_CUART0_RX_GPIO_PIN +#define ES_CUART0_RX_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_CUART0_RX_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_CUART0_RX_PIN ES_PIN_GPIO_C_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC8_USED +#define ES_MAP__PIN_PC8_USED +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_C_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC8_USED +#define ES_MAP__PIN_PC8_USED +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_GP16C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC8_USED +#define ES_MAP__PIN_PC8_USED +#ifndef ES_CUART0_TX_GPIO_FUNC +#define ES_CUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_CUART0_TX_GPIO_PORT +#define ES_CUART0_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_CUART0_TX_GPIO_PIN +#define ES_CUART0_TX_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_CUART0_TX_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_CUART0_TX_PIN ES_PIN_GPIO_C_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC9_USED +#define ES_MAP__PIN_PC9_USED +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_C_9 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC9_USED +#define ES_MAP__PIN_PC9_USED +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_C_9 +#define ES_GP16C4T1_CH4_PIN ES_PIN_GPIO_C_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA8_USED +#define ES_MAP__PIN_PA8_USED +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_8 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA9_USED +#define ES_MAP__PIN_PA9_USED +#ifndef ES_CUART0_TX_GPIO_FUNC +#define ES_CUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART0_TX_GPIO_PORT +#define ES_CUART0_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART0_TX_GPIO_PIN +#define ES_CUART0_TX_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_CUART0_TX_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_CUART0_TX_PIN ES_PIN_GPIO_A_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA9_USED +#define ES_MAP__PIN_PA9_USED +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_A_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA9_USED +#define ES_MAP__PIN_PA9_USED +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_A_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA9_USED +#define ES_MAP__PIN_PA9_USED +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_A_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA10_USED +#define ES_MAP__PIN_PA10_USED +#ifndef ES_CUART0_RX_GPIO_FUNC +#define ES_CUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART0_RX_GPIO_PORT +#define ES_CUART0_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART0_RX_GPIO_PIN +#define ES_CUART0_RX_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_CUART0_RX_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_CUART0_RX_PIN ES_PIN_GPIO_A_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA10_USED +#define ES_MAP__PIN_PA10_USED +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_A_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA10_USED +#define ES_MAP__PIN_PA10_USED +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_GP16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_GP16C4T1_ET_PIN ES_PIN_GPIO_A_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA10_USED +#define ES_MAP__PIN_PA10_USED +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_A_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA11_USED +#define ES_MAP__PIN_PA11_USED +#ifndef ES_CUART2_TX_GPIO_FUNC +#define ES_CUART2_TX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_CUART2_TX_GPIO_PORT +#define ES_CUART2_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART2_TX_GPIO_PIN +#define ES_CUART2_TX_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_CUART2_TX_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_CUART2_TX_PIN ES_PIN_GPIO_A_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA11_USED +#define ES_MAP__PIN_PA11_USED +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_A_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA11_USED +#define ES_MAP__PIN_PA11_USED +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_A_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA12_USED +#define ES_MAP__PIN_PA12_USED +#ifndef ES_CUART2_RX_GPIO_FUNC +#define ES_CUART2_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_CUART2_RX_GPIO_PORT +#define ES_CUART2_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART2_RX_GPIO_PIN +#define ES_CUART2_RX_GPIO_PIN ALD_GPIO_PIN_12 +#endif + +#ifndef ES_CUART2_RX_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_CUART2_RX_PIN ES_PIN_GPIO_A_12 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA12_USED +#define ES_MAP__PIN_PA12_USED +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN ALD_GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_A_12 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA13_USED +#define ES_MAP__PIN_PA13_USED +#ifndef ES_CUART1_TX_GPIO_FUNC +#define ES_CUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_TX_GPIO_PORT +#define ES_CUART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART1_TX_GPIO_PIN +#define ES_CUART1_TX_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_CUART1_TX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_CUART1_TX_PIN ES_PIN_GPIO_A_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA13_USED +#define ES_MAP__PIN_PA13_USED +#ifndef ES_EUART0_RX_GPIO_FUNC +#define ES_EUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_EUART0_RX_GPIO_PORT +#define ES_EUART0_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_EUART0_RX_GPIO_PIN +#define ES_EUART0_RX_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_EUART0_RX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_EUART0_RX_PIN ES_PIN_GPIO_A_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA13_USED +#define ES_MAP__PIN_PA13_USED +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_A_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA13_USED +#define ES_MAP__PIN_PA13_USED +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN ALD_GPIO_PIN_13 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_A_13 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA14_USED +#define ES_MAP__PIN_PA14_USED +#ifndef ES_CUART1_RX_GPIO_FUNC +#define ES_CUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_CUART1_RX_GPIO_PORT +#define ES_CUART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CUART1_RX_GPIO_PIN +#define ES_CUART1_RX_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_CUART1_RX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_CUART1_RX_PIN ES_PIN_GPIO_A_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA14_USED +#define ES_MAP__PIN_PA14_USED +#ifndef ES_EUART0_TX_GPIO_FUNC +#define ES_EUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_EUART0_TX_GPIO_PORT +#define ES_EUART0_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_EUART0_TX_GPIO_PIN +#define ES_EUART0_TX_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_EUART0_TX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_EUART0_TX_PIN ES_PIN_GPIO_A_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA14_USED +#define ES_MAP__PIN_PA14_USED +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_A_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA14_USED +#define ES_MAP__PIN_PA14_USED +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN ALD_GPIO_PIN_14 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_A_14 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA15_USED +#define ES_MAP__PIN_PA15_USED +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_A_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA15_USED +#define ES_MAP__PIN_PA15_USED +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PA15_USED +#define ES_MAP__PIN_PA15_USED +#ifndef ES_GP16C4T2_ET_GPIO_FUNC +#define ES_GP16C4T2_ET_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T2_ET_GPIO_PORT +#define ES_GP16C4T2_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T2_ET_GPIO_PIN +#define ES_GP16C4T2_ET_GPIO_PIN ALD_GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T2_ET_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP16C4T2_ET_PIN ES_PIN_GPIO_A_15 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC10_USED +#define ES_MAP__PIN_PC10_USED +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC10_USED +#define ES_MAP__PIN_PC10_USED +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_C_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC10_USED +#define ES_MAP__PIN_PC10_USED +#ifndef ES_CUART2_TX_GPIO_FUNC +#define ES_CUART2_TX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_CUART2_TX_GPIO_PORT +#define ES_CUART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_CUART2_TX_GPIO_PIN +#define ES_CUART2_TX_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_CUART2_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_CUART2_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC10_USED +#define ES_MAP__PIN_PC10_USED +#ifndef ES_EUART1_TX_GPIO_FUNC +#define ES_EUART1_TX_GPIO_FUNC ALD_GPIO_FUNC_7 +#endif +#ifndef ES_EUART1_TX_GPIO_PORT +#define ES_EUART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART1_TX_GPIO_PIN +#define ES_EUART1_TX_GPIO_PIN ALD_GPIO_PIN_10 +#endif + +#ifndef ES_EUART1_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_EUART1_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC11_USED +#define ES_MAP__PIN_PC11_USED +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC11_USED +#define ES_MAP__PIN_PC11_USED +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_C_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC11_USED +#define ES_MAP__PIN_PC11_USED +#ifndef ES_CUART2_RX_GPIO_FUNC +#define ES_CUART2_RX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_CUART2_RX_GPIO_PORT +#define ES_CUART2_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_CUART2_RX_GPIO_PIN +#define ES_CUART2_RX_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_CUART2_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_CUART2_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC11_USED +#define ES_MAP__PIN_PC11_USED +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_C_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC11_USED +#define ES_MAP__PIN_PC11_USED +#ifndef ES_EUART1_RX_GPIO_FUNC +#define ES_EUART1_RX_GPIO_FUNC ALD_GPIO_FUNC_7 +#endif +#ifndef ES_EUART1_RX_GPIO_PORT +#define ES_EUART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_EUART1_RX_GPIO_PIN +#define ES_EUART1_RX_GPIO_PIN ALD_GPIO_PIN_11 +#endif + +#ifndef ES_EUART1_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_EUART1_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC12_USED +#define ES_MAP__PIN_PC12_USED +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN ALD_GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_12 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC12_USED +#define ES_MAP__PIN_PC12_USED +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_12 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_C_12 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PC12_USED +#define ES_MAP__PIN_PC12_USED +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOC +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN ALD_GPIO_PIN_12 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_C_12 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD2_USED +#define ES_MAP__PIN_PD2_USED +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_GP16C4T1_ET_PIN ES_PIN_GPIO_D_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD2_USED +#define ES_MAP__PIN_PD2_USED +#ifndef ES_CUART2_RX_GPIO_FUNC +#define ES_CUART2_RX_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_CUART2_RX_GPIO_PORT +#define ES_CUART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_CUART2_RX_GPIO_PIN +#define ES_CUART2_RX_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_CUART2_RX_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_CUART2_RX_PIN ES_PIN_GPIO_D_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PD2_USED +#define ES_MAP__PIN_PD2_USED +#ifndef ES_GP16C4T2_CH4_GPIO_FUNC +#define ES_GP16C4T2_CH4_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_GP16C4T2_CH4_GPIO_PORT +#define ES_GP16C4T2_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T2_CH4_GPIO_PIN +#define ES_GP16C4T2_CH4_GPIO_PIN ALD_GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T2_CH4_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_GP16C4T2_CH4_PIN ES_PIN_GPIO_D_2 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB3_USED +#define ES_MAP__PIN_PB3_USED +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB3_USED +#define ES_MAP__PIN_PB3_USED +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB3_USED +#define ES_MAP__PIN_PB3_USED +#ifndef ES_CUART2_TX_GPIO_FUNC +#define ES_CUART2_TX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_CUART2_TX_GPIO_PORT +#define ES_CUART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART2_TX_GPIO_PIN +#define ES_CUART2_TX_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_CUART2_TX_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_CUART2_TX_PIN ES_PIN_GPIO_B_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB3_USED +#define ES_MAP__PIN_PB3_USED +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN ALD_GPIO_PIN_3 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_3 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB4_USED +#define ES_MAP__PIN_PB4_USED +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_GP16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_GP16C4T1_CH1_PIN ES_PIN_GPIO_B_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB4_USED +#define ES_MAP__PIN_PB4_USED +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB4_USED +#define ES_MAP__PIN_PB4_USED +#ifndef ES_CUART2_RX_GPIO_FUNC +#define ES_CUART2_RX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_CUART2_RX_GPIO_PORT +#define ES_CUART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART2_RX_GPIO_PIN +#define ES_CUART2_RX_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_CUART2_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_CUART2_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB4_USED +#define ES_MAP__PIN_PB4_USED +#ifndef ES_EUART0_RX_GPIO_FUNC +#define ES_EUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_EUART0_RX_GPIO_PORT +#define ES_EUART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART0_RX_GPIO_PIN +#define ES_EUART0_RX_GPIO_PIN ALD_GPIO_PIN_4 +#endif + +#ifndef ES_EUART0_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_EUART0_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB5_USED +#define ES_MAP__PIN_PB5_USED +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_GP16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_GP16C4T1_CH2_PIN ES_PIN_GPIO_B_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB5_USED +#define ES_MAP__PIN_PB5_USED +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB5_USED +#define ES_MAP__PIN_PB5_USED +#ifndef ES_EUART0_TX_GPIO_FUNC +#define ES_EUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_EUART0_TX_GPIO_PORT +#define ES_EUART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART0_TX_GPIO_PIN +#define ES_EUART0_TX_GPIO_PIN ALD_GPIO_PIN_5 +#endif + +#ifndef ES_EUART0_TX_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_EUART0_TX_PIN ES_PIN_GPIO_B_5 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB6_USED +#define ES_MAP__PIN_PB6_USED +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB6_USED +#define ES_MAP__PIN_PB6_USED +#ifndef ES_GP16C4T2_CH1_GPIO_FUNC +#define ES_GP16C4T2_CH1_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T2_CH1_GPIO_PORT +#define ES_GP16C4T2_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T2_CH1_GPIO_PIN +#define ES_GP16C4T2_CH1_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T2_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_GP16C4T2_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB6_USED +#define ES_MAP__PIN_PB6_USED +#ifndef ES_CUART0_TX_GPIO_FUNC +#define ES_CUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_CUART0_TX_GPIO_PORT +#define ES_CUART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART0_TX_GPIO_PIN +#define ES_CUART0_TX_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_CUART0_TX_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_CUART0_TX_PIN ES_PIN_GPIO_B_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB6_USED +#define ES_MAP__PIN_PB6_USED +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN ALD_GPIO_PIN_6 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB7_USED +#define ES_MAP__PIN_PB7_USED +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB7_USED +#define ES_MAP__PIN_PB7_USED +#ifndef ES_GP16C4T2_CH2_GPIO_FUNC +#define ES_GP16C4T2_CH2_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_GP16C4T2_CH2_GPIO_PORT +#define ES_GP16C4T2_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T2_CH2_GPIO_PIN +#define ES_GP16C4T2_CH2_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T2_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_GP16C4T2_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB7_USED +#define ES_MAP__PIN_PB7_USED +#ifndef ES_CUART0_RX_GPIO_FUNC +#define ES_CUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_CUART0_RX_GPIO_PORT +#define ES_CUART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CUART0_RX_GPIO_PIN +#define ES_CUART0_RX_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_CUART0_RX_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_CUART0_RX_PIN ES_PIN_GPIO_B_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB7_USED +#define ES_MAP__PIN_PB7_USED +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN ALD_GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB8_USED +#define ES_MAP__PIN_PB8_USED +#ifndef ES_GP16C4T2_CH3_GPIO_FUNC +#define ES_GP16C4T2_CH3_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T2_CH3_GPIO_PORT +#define ES_GP16C4T2_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T2_CH3_GPIO_PIN +#define ES_GP16C4T2_CH3_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T2_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C4T2_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB8_USED +#define ES_MAP__PIN_PB8_USED +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB8_USED +#define ES_MAP__PIN_PB8_USED +#ifndef ES_EUART0_RX_GPIO_FUNC +#define ES_EUART0_RX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_EUART0_RX_GPIO_PORT +#define ES_EUART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART0_RX_GPIO_PIN +#define ES_EUART0_RX_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_EUART0_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_EUART0_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB8_USED +#define ES_MAP__PIN_PB8_USED +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN ALD_GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB9_USED +#define ES_MAP__PIN_PB9_USED +#ifndef ES_GP16C4T2_CH4_GPIO_FUNC +#define ES_GP16C4T2_CH4_GPIO_FUNC ALD_GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T2_CH4_GPIO_PORT +#define ES_GP16C4T2_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T2_CH4_GPIO_PIN +#define ES_GP16C4T2_CH4_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T2_CH4_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_GP16C4T2_CH4_PIN ES_PIN_GPIO_B_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB9_USED +#define ES_MAP__PIN_PB9_USED +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC ALD_GPIO_FUNC_3 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB9_USED +#define ES_MAP__PIN_PB9_USED +#ifndef ES_EUART0_TX_GPIO_FUNC +#define ES_EUART0_TX_GPIO_FUNC ALD_GPIO_FUNC_4 +#endif +#ifndef ES_EUART0_TX_GPIO_PORT +#define ES_EUART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_EUART0_TX_GPIO_PIN +#define ES_EUART0_TX_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_EUART0_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_EUART0_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif +#endif + + +#ifndef ES_MAP__PIN_PB9_USED +#define ES_MAP__PIN_PB9_USED +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC ALD_GPIO_FUNC_5 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN ALD_GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_9 +#endif +#endif +#endif + + + + +#endif + +#define ES_RTT_APP_LED_PIN ES_PIN_GPIO_A_15 + + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..68cf747791 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include +#include + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..5c5470592b --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,72 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + +#define ES_C_PWM_OC_POL_HIGH ALD_TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW ALD_TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 ALD_TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 ALD_TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM1 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T0_PWM +#define ES_DEVICE_NAME_GP16C2T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T1_PWM +#define ES_DEVICE_NAME_GP16C2T1_PWM "pwm3" +#endif + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..c03cd2b790 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include +#include + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..d36c4a9c32 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_select.h @@ -0,0 +1,44 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ +//#define ES_USE_ASSERT ES_C_ENABLE + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..71558ef42c --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,132 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..79c9ce34cf --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#define ES_C_UART_PARITY_NONE ALD_UART_PARITY_NONE +#define ES_C_UART_PARITY_ODD ALD_UART_PARITY_ODD +#define ES_C_UART_PARITY_EVEN ALD_UART_PARITY_EVEN + +#define ES_C_UART_STOP_1 ALD_UART_STOP_BITS_1 +#define ES_C_UART_STOP_2 ALD_UART_STOP_BITS_2 + + +/* UART 配置 */ + + + + +#ifndef ES_DEVICE_NAME_EUART0 +#define ES_DEVICE_NAME_EUART0 "euart0" +#endif +#ifndef ES_DEVICE_NAME_EUART1 +#define ES_DEVICE_NAME_EUART1 "euart1" +#endif +#ifndef ES_DEVICE_NAME_CUART0 +#define ES_DEVICE_NAME_CUART0 "cuart0" +#endif +#ifndef ES_DEVICE_NAME_CUART1 +#define ES_DEVICE_NAME_CUART1 "cuart1" +#endif +#ifndef ES_DEVICE_NAME_CUART2 +#define ES_DEVICE_NAME_CUART2 "cuart2" +#endif + + +#ifndef ES_CONF_CUART0_BAUD_RATE +#define ES_CONF_CUART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_CUART0_PARITY +#define ES_CONF_CUART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_CUART0_STOP_BITS +#define ES_CONF_CUART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_CUART1_BAUD_RATE +#define ES_CONF_CUART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_CUART1_PARITY +#define ES_CONF_CUART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_CUART1_STOP_BITS +#define ES_CONF_CUART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_CUART0_BAUD_RATE +#define ES_CONF_CUART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_CUART0_PARITY +#define ES_CONF_CUART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_CUART0_STOP_BITS +#define ES_CONF_CUART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_CUART1_BAUD_RATE +#define ES_CONF_CUART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_CUART1_PARITY +#define ES_CONF_CUART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_CUART1_STOP_BITS +#define ES_CONF_CUART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_CUART2_BAUD_RATE +#define ES_CONF_CUART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_CUART2_PARITY +#define ES_CONF_CUART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_CUART2_STOP_BITS +#define ES_CONF_CUART2_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_EUART0_CONFIG \ +{ \ + ES_CONF_EUART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_EUART0_STOP_BITS, \ + ES_CONF_EUART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_EUART1_CONFIG \ +{ \ + ES_CONF_EUART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_EUART1_STOP_BITS, \ + ES_CONF_EUART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_CUART0_CONFIG \ +{ \ + ES_CONF_CUART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_CUART0_STOP_BITS, \ + ES_CONF_CUART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_CUART1_CONFIG \ +{ \ + ES_CONF_CUART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_CUART1_STOP_BITS, \ + ES_CONF_CUART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_CUART2_CONFIG \ +{ \ + ES_CONF_CUART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_CUART2_STOP_BITS, \ + ES_CONF_CUART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/Kconfig b/bsp/essemi/es32vf2264/drivers/Kconfig new file mode 100644 index 0000000000..cd22a63aa1 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/Kconfig @@ -0,0 +1,39 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + source "drivers/ES/Kconfig" + + endmenu + + menu "Onboard Peripheral Drivers" + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi0)" + select BSP_USING_SPI + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + +if BSP_USING_SPI_FLASH + + config ES_DEVICE_NAME_SPI_DEV + string "The name of spi device (registered)" + default "spi00" + + config ES_DEVICE_NAME_SPI_FALSH_DEV + string "The name of spi flash device" + default "W25Q64" +endif + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/essemi/es32vf2264/drivers/SConscript b/bsp/essemi/es32vf2264/drivers/SConscript new file mode 100644 index 0000000000..8354af609f --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/SConscript @@ -0,0 +1,80 @@ +from building import * + +cwd = GetCurrentDir() + +objs = [] + +# add the general drivers. +src = Split(''' +board.c +''') + +# add gpio code +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5') or \ + GetDepend('RT_USING_SERIAL'): + src += ['drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): + src += ['drv_spi.c'] + +# add i2c driver code +if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): + src += ['drv_i2c.c'] + +# add can driver code +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): + src += ['drv_can.c'] + + +# add adc driver code +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] + +# add rtc driver code +if GetDepend(['BSP_USING_RTC']): + src += ['drv_rtc.c'] + +# add spi flash driver code +if GetDepend('BSP_USING_SPI_FLASH'): + src += ['drv_spiflash.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or GetDepend('BSP_USING_GP16C4T2_HWTIMER') or \ + GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \ + GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'): + src += ['drv_hwtimer.c'] + +# add pwm driver code +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM') or GetDepend('BSP_USING_GP16C4T2_PWM') or \ + GetDepend('BSP_USING_GP16C2T0__PWM') or GetDepend('BSP_USING_GP16C2T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): + src += ['drv_pwm.c'] + +# add pm driver code +if GetDepend(['BSP_USING_PM']): + src += ['drv_pm.c'] +CPPPATH = [cwd] +CPPPATH = CPPPATH + [cwd + '/ES'] +#__SYS_SELECT_H__ 用来规避冲突 +#cdkrepo\toolchain\xtgccelfnewlib\v2.6.1\r\riscv64-unknown-elf\include\sys\select.h +#components/libc/compilers/common/include/sys/select.h +CPPDEFINES = ['__SYS_SELECT_H__'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) +objs = objs + group + +Return('objs') + diff --git a/bsp/essemi/es32vf2264/drivers/board.c b/bsp/essemi/es32vf2264/drivers/board.c new file mode 100644 index 0000000000..02c0ee1709 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/board.c @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2022-02-10 Lisq the first version + */ + +#include "board.h" + +/** + * @addtogroup es32 + */ + +/*@{*/ + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + /* Configure system clock */ + ald_cmu_pll_config(ALD_CMU_PLL_INPUT_HOSC8M, ALD_CMU_PLL_OUTPUT_72M); + ald_cmu_clock_config(ALD_CMU_CLOCK_PLL, 72000000); + + /* Enable all peripherals */ + ald_cmu_perh_clock_config(ALD_CMU_PERH_ALL, ENABLE); + + __enable_irq(); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + ald_cmu_init(); +} + +/** + * This is the timer interrupt service routine. + * + */ +void __attribute__((interrupt)) CLINT_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + csi_coret_clr(ald_cmu_get_clock() / RT_TICK_PER_SECOND, CLINT_IRQn); + ald_inc_tick(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void __attribute__((interrupt)) DMA_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + ald_dma_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/*@}*/ +/** + * This function will initial ES32F0 board. + */ +void rt_hw_board_init(void) +{ + csi_vic_set_prio(MACHINE_MODE_SOFT_IRQn, 0); + csi_vic_enable_sirq(MACHINE_MODE_SOFT_IRQn); + CLIC->CLICINT[MACHINE_MODE_SOFT_IRQn].ATTR |= (3); + + csi_vic_set_prio(DMA_IRQn, 4); + csi_vic_enable_sirq(DMA_IRQn); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_DEEP); + + /*System Clock Configuration */ + SystemClock_Config(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + unsigned int start, now, delta, reload, us_tick; + start = CORET->MTIME; + reload = CORET->MTIMECMP; + us_tick = ald_cmu_get_clock() / 1000000UL; + do + { + now = CORET->MTIME; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} + +void rt_trigger_software_interrupt(void) +{ + *((uint8_t*)0xE080100C) = 0x1; +} + +void rt_hw_do_after_save_above(void) +{ +} diff --git a/bsp/essemi/es32vf2264/drivers/board.h b/bsp/essemi/es32vf2264/drivers/board.h new file mode 100644 index 0000000000..a230d97a39 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/board.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2022-04-18 liuhy the first version + */ + +/* <<< Use Configuration Wizard in Context Menu >>>*/ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "ald_conf.h" + +#include "rtconfig.h" +#include +#include +#include + +#include "es_conf_info_cmu.h" +#include "es_conf_info_dma.h" +#include "es_conf_info_map.h" +#include "es_conf_info_gpio.h" +#include "es_conf_info_adc.h" +#include "es_conf_info_hwtimer.h" +#include "es_conf_info_pwm.h" +#include "es_conf_info_uart.h" +#include "es_conf_info_spi.h" +#include "es_conf_info_i2c.h" +#include "es_conf_info_pm.h" + +#define GET_PIN(port,pin) (ES_PIN_GPIO_##port##_##pin) + +extern int __bss_end__; +#define HEAP_BEGIN ((void *)&__bss_end__) + +#define HEAP_END (0x20008000) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_adc.c b/bsp/essemi/es32vf2264/drivers/drv_adc.c new file mode 100644 index 0000000000..87260397c0 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_adc.c @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-04-03 wangyq the first version + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include "board.h" +#include "drv_adc.h" + +#ifdef RT_USING_ADC + +/* define adc instance */ + +#ifdef BSP_USING_ADC0 +static struct rt_adc_device _device_adc0; +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 +static struct rt_adc_device _device_adc1; +#endif /*BSP_USING_ADC1*/ + +/* enable or disable adc */ +static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) +{ + ald_adc_handle_t *_hadc = (ald_adc_handle_t *)device->parent.user_data; + + RT_ASSERT(device != RT_NULL); + + if (enabled) + { + ALD_ADC_ENABLE(_hadc); ; + } + else + { + ALD_ADC_DISABLE(_hadc); + } + + return RT_EOK; +} + +static ald_adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) +{ + ald_adc_channel_t es32f3_channel; + ald_gpio_init_t gpio_initstruct; + + /* Initialize ADC pin */ + gpio_initstruct.mode = ALD_GPIO_MODE_CLOSE; + gpio_initstruct.pupd = ALD_GPIO_FLOATING; + gpio_initstruct.od = ALD_GPIO_PUSH_PULL; + gpio_initstruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_initstruct.flt = ALD_GPIO_FILTER_DISABLE; + gpio_initstruct.type = ALD_GPIO_TYPE_CMOS; + gpio_initstruct.func = ALD_GPIO_FUNC_0; + + /* select gpio pin as adc function */ + switch (channel) + { + case 0: + es32f3_channel = ALD_ADC_CHANNEL_0; + ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct); + break; + case 1: + es32f3_channel = ALD_ADC_CHANNEL_1; + ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct); + break; + case 2: + es32f3_channel = ALD_ADC_CHANNEL_2; + ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct); + break; + case 3: + es32f3_channel = ALD_ADC_CHANNEL_3; + ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct); + break; + case 4: + es32f3_channel = ALD_ADC_CHANNEL_4; + ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct); + break; + case 5: + es32f3_channel = ALD_ADC_CHANNEL_5; + ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct); + break; + case 6: + es32f3_channel = ALD_ADC_CHANNEL_6; + ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct); + break; + case 7: + es32f3_channel = ALD_ADC_CHANNEL_7; + ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct); + break; + case 8: + es32f3_channel = ALD_ADC_CHANNEL_8; + ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct); + break; + case 9: + es32f3_channel = ALD_ADC_CHANNEL_9; + ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct); + break; + case 10: + es32f3_channel = ALD_ADC_CHANNEL_10; + ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct); + break; + case 11: + es32f3_channel = ALD_ADC_CHANNEL_11; + ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct); + break; + case 12: + es32f3_channel = ALD_ADC_CHANNEL_12; + ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct); + break; + case 13: + es32f3_channel = ALD_ADC_CHANNEL_13; + ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct); + break; + case 14: + es32f3_channel = ALD_ADC_CHANNEL_14; + ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct); + break; + case 15: + es32f3_channel = ALD_ADC_CHANNEL_15; + ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct); + break; + + default: + break; + } + + return es32f3_channel; +} + +static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) +{ + ald_adc_handle_t *_hadc = (ald_adc_handle_t *)device->parent.user_data; + ald_adc_nch_conf_t nm_config; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + /* config adc channel */ + nm_config.ch = es32f3_adc_get_channel(channel); + nm_config.idx = ALD_ADC_NCH_IDX_1; + nm_config.samp = ES_ADC0_NCH_SAMPLETIME; + ald_adc_normal_channel_config(_hadc, &nm_config); + + ald_adc_normal_start(_hadc); + + if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == ALD_OK) + *value = ald_adc_normal_get_value(_hadc); + + return RT_EOK; +} + +static const struct rt_adc_ops es32f3_adc_ops = +{ + es32f3_adc_enabled, + es32f3_get_adc_value, +}; + +int rt_hw_adc_init(void) +{ + ald_adc_handle_t _h_adc; + + /* adc function initialization */ + _h_adc.init.scan = ENABLE; + _h_adc.init.cont = DISABLE; + _h_adc.init.disc = ALD_ADC_ALL_DISABLE; + _h_adc.init.disc_nr = ALD_ADC_DISC_NR_1; + _h_adc.init.data_bit = ALD_ADC_CONV_BIT_12; + _h_adc.init.div = ALD_ADC_CKDIV_16; + _h_adc.init.nch_nr = ALD_ADC_NCH_NR_1; + _h_adc.init.nche_sel = ALD_ADC_NCHESEL_MODE_ALL; + _h_adc.init.cont = DISABLE; + _h_adc.init.n_ref = ALD_ADC_NEG_REF_VSS; + _h_adc.init.p_ref = ALD_ADC_POS_REF_VDD; + +#ifdef BSP_USING_ADC0 + + static ald_adc_handle_t _h_adc0; + + _h_adc0.init = _h_adc.init; + + _h_adc0.perh = ADC; + _h_adc0.init.align = ES_ADC0_ALIGN; + _h_adc0.init.data_bit = ES_ADC0_DATA_BIT; + _h_adc0.init.div = ES_ADC0_CLK_DIV; + ALD_ADC_ENABLE(&_h_adc0); + ALD_ADC_DISABLE(&_h_adc0); + ald_adc_init(&_h_adc0); + + rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f3_adc_ops, &_h_adc0); + +#endif /*BSP_USING_ADC0*/ + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_adc.h b/bsp/essemi/es32vf2264/drivers/drv_adc.h new file mode 100644 index 0000000000..fa51cdbb21 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_adc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_ADC_H__ +#define DRV_ADC_H__ + +#include "es_conf_info_adc.h" + +int rt_hw_adc_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_gpio.c b/bsp/essemi/es32vf2264/drivers/drv_gpio.c new file mode 100644 index 0000000000..dd13df8e09 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_gpio.c @@ -0,0 +1,611 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#include "drv_gpio.h" + +/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/ + +#ifdef RT_USING_PIN + + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {ALD_GPIO_PIN_0, EXTI0_3_IRQn}, + {ALD_GPIO_PIN_1, EXTI0_3_IRQn}, + {ALD_GPIO_PIN_2, EXTI0_3_IRQn}, + {ALD_GPIO_PIN_3, EXTI0_3_IRQn}, + {ALD_GPIO_PIN_4, EXTI4_7_IRQn}, + {ALD_GPIO_PIN_5, EXTI4_7_IRQn}, + {ALD_GPIO_PIN_6, EXTI4_7_IRQn}, + {ALD_GPIO_PIN_7, EXTI4_7_IRQn}, + {ALD_GPIO_PIN_8, EXTI8_11_IRQn}, + {ALD_GPIO_PIN_9, EXTI8_11_IRQn}, + {ALD_GPIO_PIN_10, EXTI8_11_IRQn}, + {ALD_GPIO_PIN_11, EXTI8_11_IRQn}, + {ALD_GPIO_PIN_12, EXTI12_15_IRQn}, + {ALD_GPIO_PIN_13, EXTI12_15_IRQn}, + {ALD_GPIO_PIN_14, EXTI12_15_IRQn}, + {ALD_GPIO_PIN_15, EXTI12_15_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, +}; + +#ifdef ES_CONF_EXTI_IRQ_0 + +RT_WEAK void irq_pin0_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 0\r\n"); +} +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 + +RT_WEAK void irq_pin1_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 1\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 + + RT_WEAK void irq_pin2_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 2\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 + +RT_WEAK void irq_pin3_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 3\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 + +RT_WEAK void irq_pin4_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 4\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 + +RT_WEAK void irq_pin5_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 5\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 + +RT_WEAK void irq_pin6_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 6\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 + +RT_WEAK void irq_pin7_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 7\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 + +RT_WEAK void irq_pin8_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 8\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 + +RT_WEAK void irq_pin9_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 9\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 + +RT_WEAK void irq_pin10_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 10\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 + +RT_WEAK void irq_pin11_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 11\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 + +RT_WEAK void irq_pin12_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 12\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 + +RT_WEAK void irq_pin13_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 13\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 + +RT_WEAK void irq_pin14_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 14\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 + +RT_WEAK void irq_pin15_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 15\r\n"); +} + +#endif + + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + ald_gpio_write_pin(index->gpio, index->pin, value); +} + +rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = ald_gpio_read_pin(index->gpio, index->pin); + return value; +} + +void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + const struct pin_index *index; + ald_gpio_init_t gpio_initstruct; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + gpio_initstruct.mode = ALD_GPIO_MODE_OUTPUT; + gpio_initstruct.func = ALD_GPIO_FUNC_1; + gpio_initstruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_initstruct.type = ALD_GPIO_TYPE_CMOS; + gpio_initstruct.od = ALD_GPIO_PUSH_PULL; + gpio_initstruct.flt = ALD_GPIO_FILTER_DISABLE; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpio_initstruct.mode = ALD_GPIO_MODE_OUTPUT; + gpio_initstruct.pupd = ALD_GPIO_FLOATING; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpio_initstruct.mode = ALD_GPIO_MODE_INPUT; + gpio_initstruct.pupd = ALD_GPIO_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpio_initstruct.mode = ALD_GPIO_MODE_INPUT; + gpio_initstruct.pupd = ALD_GPIO_PUSH_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpio_initstruct.mode = ALD_GPIO_MODE_INPUT; + gpio_initstruct.pupd = ALD_GPIO_PUSH_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpio_initstruct.mode = ALD_GPIO_MODE_OUTPUT; + gpio_initstruct.pupd = ALD_GPIO_FLOATING; + gpio_initstruct.od = ALD_GPIO_OPEN_DRAIN; + } + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) +{ + uint8_t map_index = 0U; + + while(gpio_pin >> (++map_index)) + { + } + map_index--; + + if (map_index >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[map_index]; +}; + +rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + /* Configure GPIO_InitStructure & EXTI_InitStructure */ + ald_gpio_init_t gpio_initstruct; + ald_exti_init_t exti_initstruct; + exti_initstruct.filter = DISABLE; + exti_initstruct.filter_time = 0x0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); + /* Configure GPIO_InitStructure */ + gpio_initstruct.mode = ALD_GPIO_MODE_INPUT; + gpio_initstruct.od = ALD_GPIO_PUSH_PULL; + gpio_initstruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_initstruct.func = ALD_GPIO_FUNC_1; + gpio_initstruct.flt = ALD_GPIO_FILTER_DISABLE; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + gpio_initstruct.pupd = ALD_GPIO_PUSH_DOWN; + ald_gpio_exti_interrupt_config(index->pin, ALD_EXTI_TRIGGER_RISING_EDGE, ENABLE); + break; + case PIN_IRQ_MODE_FALLING: + gpio_initstruct.pupd = ALD_GPIO_PUSH_UP; + ald_gpio_exti_interrupt_config(index->pin, ALD_EXTI_TRIGGER_TRAILING_EDGE, ENABLE); + break; + case PIN_IRQ_MODE_RISING_FALLING: + gpio_initstruct.pupd = ALD_GPIO_FLOATING; + ald_gpio_exti_interrupt_config(index->pin, ALD_EXTI_TRIGGER_BOTH_EDGE, ENABLE); + break; + } + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); + csi_vic_enable_sirq(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + + /*csi_vic_disable_sirq(irqmap->irqno);*/ + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _es32f3_pin_ops = +{ + es32f3_pin_mode, + es32f3_pin_write, + es32f3_pin_read, + es32f3_pin_attach_irq, + es32f3_pin_detach_irq, + es32f3_pin_irq_enable, + /*RT_NULL,*/ +}; + +rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) +{ + uint16_t irqno; + /* pin no. convert to dec no. */ + for (irqno = 0; irqno < 16; irqno++) + { + if ((0x01 << irqno) == GPIO_Pin) + { + break; + } + } + if (irqno == 16) + return; + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET) + { + ald_gpio_exti_clear_flag_status(GPIO_Pin); + pin_irq_hdr(GPIO_Pin); + } +} + +void __attribute__((interrupt)) EXTI0_3_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(ALD_GPIO_PIN_0); + GPIO_EXTI_Callback(ALD_GPIO_PIN_1); + GPIO_EXTI_Callback(ALD_GPIO_PIN_2); + GPIO_EXTI_Callback(ALD_GPIO_PIN_3); + rt_interrupt_leave(); +} + +void __attribute__((interrupt)) EXTI4_7_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(ALD_GPIO_PIN_4); + GPIO_EXTI_Callback(ALD_GPIO_PIN_5); + GPIO_EXTI_Callback(ALD_GPIO_PIN_6); + GPIO_EXTI_Callback(ALD_GPIO_PIN_7); + rt_interrupt_leave(); +} + +void __attribute__((interrupt)) EXTI8_11_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(ALD_GPIO_PIN_8); + GPIO_EXTI_Callback(ALD_GPIO_PIN_9); + GPIO_EXTI_Callback(ALD_GPIO_PIN_10); + GPIO_EXTI_Callback(ALD_GPIO_PIN_11); + rt_interrupt_leave(); +} + +void __attribute__((interrupt)) EXTI12_15_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(ALD_GPIO_PIN_12); + GPIO_EXTI_Callback(ALD_GPIO_PIN_13); + GPIO_EXTI_Callback(ALD_GPIO_PIN_14); + GPIO_EXTI_Callback(ALD_GPIO_PIN_15); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ + int result; + + +#ifdef ES_INIT_GPIOS + + rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t); + +#endif + + result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f3_pin_ops, RT_NULL); + + if(result != RT_EOK)return result; + +#ifdef ES_INIT_GPIOS + + for(i = 0;i < gpio_conf_num;i++) + { + rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode); + + if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD)) + rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level); + + if(!gpio_conf_all[i].irq_en)continue; + + rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL); + rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en); + } + +#endif + + + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_gpio.h b/bsp/essemi/es32vf2264/drivers/drv_gpio.h new file mode 100644 index 0000000000..086a1ca8ba --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_gpio.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +#include "board.h" + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_hwtimer.c b/bsp/essemi/es32vf2264/drivers/drv_hwtimer.c new file mode 100644 index 0000000000..e42819af09 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_hwtimer.c @@ -0,0 +1,354 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-3-19 wangyq the first version + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include +#include + + +#ifdef RT_USING_HWTIMER + +struct es32f3_hwtimer_dev +{ + rt_hwtimer_t parent; + ald_timer_handle_t *hwtimer_periph; + IRQn_Type IRQn; +}; + +#ifdef BSP_USING_AD16C4T0_HWTIMER +static struct es32f3_hwtimer_dev ad16c4t0_hwtimer; + +static struct rt_hwtimer_info ad16c4t0_info = +{ + ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ + (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_HWTIMER_MODE +}; + +void __attribute__((interrupt)) AD16C4T_Handler(void) +{ + rt_interrupt_enter(); + ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, ALD_TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t0_hwtimer; + +static struct rt_hwtimer_info gp16c4t0_info = +{ + ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ + (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_HWTIMER_MODE +}; + +void __attribute__((interrupt)) GPTIMB0_Handler(void) +{ + rt_interrupt_enter(); + ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); + rt_interrupt_leave(); +} + +#endif +#ifdef BSP_USING_GP16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; + +static struct rt_hwtimer_info gp16c4t1_info = +{ + ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ + (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T1_HWTIMER_MODE +}; + +void __attribute__((interrupt)) GPTIMB1_Handler(void) +{ + rt_interrupt_enter(); + ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); + rt_interrupt_leave(); +} + +#endif +#ifdef BSP_USING_GP16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; + +static struct rt_hwtimer_info gp16c4t1_info = +{ + ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ + (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T1_HWTIMER_MODE +}; + +void __attribute__((interrupt)) GPTIMB2_Handler(void) +{ + rt_interrupt_enter(); + ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); + rt_interrupt_leave(); +} + +#endif +#ifdef BSP_USING_BS16T0_HWTIMER + +static struct es32f3_hwtimer_dev bs16t0_hwtimer; + +static struct rt_hwtimer_info bs16t0_info = +{ + ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ + (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_HWTIMER_MODE +}; + +void __attribute__((interrupt)) BSTIM0_Handler(void) +{ + rt_interrupt_enter(); + ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); + rt_interrupt_leave(); +} + +#endif + +static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + + struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + + RT_ASSERT(hwtimer != RT_NULL); + + if (1 == state) + { + ald_timer_base_init(hwtimer->hwtimer_periph); + ald_timer_interrupt_config(hwtimer->hwtimer_periph, ALD_TIMER_IT_UPDATE, ENABLE); + csi_vic_enable_sirq(hwtimer->IRQn); + } + + hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + hwtimer_info->maxfreq = hwtimer->parent.freq; + hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; + +} + +static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer, + rt_uint32_t cnt, + rt_hwtimer_mode_t mode) +{ + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); + ald_timer_base_start(hwtimer->hwtimer_periph); + + return RT_EOK; +} + +static void es32f3_hwtimer_stop(rt_hwtimer_t *timer) +{ + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + ald_timer_base_stop(hwtimer->hwtimer_periph); +} + +static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer) +{ + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + uint32_t hwtimer_count = 0; + + RT_ASSERT(hwtimer != RT_NULL); + + hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT); + + return hwtimer_count; +} + +static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, + rt_uint32_t cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t freq = 0; + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + freq = *(rt_uint32_t *)args; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk_clock(); + target = temp/freq; + + if(target < 0x10001) /*最大分频 = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*更新信息*/ + hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + + } + + break; + + case HWTIMER_CTRL_STOP: + ald_timer_base_stop(hwtimer->hwtimer_periph); + break; + + default: + ret = RT_EINVAL; + break; + } + + return ret; +} + +static struct rt_hwtimer_ops es32f3_hwtimer_ops = +{ + es32f3_hwtimer_init, + es32f3_hwtimer_start, + es32f3_hwtimer_stop, + es32f3_hwtimer_count_get, + es32f3_hwtimer_control +}; + +int rt_hw_hwtimer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_AD16C4T0_HWTIMER + static ald_timer_handle_t ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer_periph.perh = AD16C4T; + ad16c4t0_hwtimer.IRQn = AD16C4T_IRQn; + + ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; + ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? ALD_TIMER_CNT_MODE_UP : ALD_TIMER_CNT_MODE_DOWN; + ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; + ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + static timer_handle_t gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer_periph.perh = GP16C4T0; + gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn; + + gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; + gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; + gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T1_HWTIMER + static timer_handle_t gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer_periph.perh = GP16C4T1; + gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn; + + gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1; + gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer.parent.info = &gp16c4t1_info; + gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T2_HWTIMER + static timer_handle_t gp16c4t2_hwtimer_periph; + + gp16c4t2_hwtimer_periph.perh = GP16C4T2; + gp16c4t2_hwtimer.IRQn = GP16C4T2_IRQn; + + gp16c4t2_hwtimer_periph.init.prescaler = ES_GP16C4T2_HWTIMER_PRES - 1; + gp16c4t2_hwtimer_periph.init.mode = ( ES_GP16C4T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t2_hwtimer.hwtimer_periph = &gp16c4t2_hwtimer_periph; + + gp16c4t2_hwtimer.parent.info = &gp16c4t2_info; + gp16c4t2_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t2_hwtimer.parent, ES_DEVICE_NAME_GP16C4T2_HWTIMER, &gp16c4t2_hwtimer); +#endif + +#ifdef BSP_USING_BS16T0_HWTIMER + static timer_handle_t bs16t0_hwtimer_periph; + + bs16t0_hwtimer_periph.perh = BS16T0; + bs16t0_hwtimer.IRQn = BS16T0_IRQn; + + bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; + bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + + bs16t0_hwtimer.parent.info = &bs16t0_info; + bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); +#endif + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_hwtimer.h b/bsp/essemi/es32vf2264/drivers/drv_hwtimer.h new file mode 100644 index 0000000000..bbf51a4771 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_hwtimer.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_HWTIMER_H__ +#define DRV_HWTIMER_H__ + +#include "es_conf_info_hwtimer.h" +int rt_hw_hwtimer_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_i2c.c b/bsp/essemi/es32vf2264/drivers/drv_i2c.c new file mode 100644 index 0000000000..dc629bc27b --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_i2c.c @@ -0,0 +1,347 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include "board.h" +#include "drv_i2c.h" + + +#ifdef RT_USING_I2C + +#define TIMEOUT 0x0FFF + +/* I2C struct definition */ +#ifdef BSP_USING_I2C0 + static ald_i2c_handle_t _h_i2c0; +#endif + +#ifdef BSP_USING_I2C1 + static i2c_handle_t _h_i2c1; +#endif + +static void _i2c_init(void) +{ + ald_gpio_init_t gpio_instruct; + + /* Initialize I2C Pin */ + gpio_instruct.mode = ALD_GPIO_MODE_OUTPUT; + gpio_instruct.od = ALD_GPIO_OPEN_DRAIN; + gpio_instruct.pupd = ALD_GPIO_PUSH_UP; + gpio_instruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_instruct.flt = ALD_GPIO_FILTER_DISABLE; + gpio_instruct.type = ALD_GPIO_TYPE_CMOS; + + +#ifdef BSP_USING_I2C0 + +#if defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); +#endif + + /* Initialize I2C Function */ + _h_i2c0.perh = I2C0; + _h_i2c0.init.module = ALD_I2C_MODULE_MASTER; + _h_i2c0.init.clk_speed = ES_I2C0_CLK_SPEED; + _h_i2c0.init.own_addr1 = ES_I2C0_OWN_ADDR1; + _h_i2c0.init.addr_mode = ES_I2C0_ADDR_MODE; + _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL; + _h_i2c0.init.no_stretch = ES_I2C0_STRETCH; + + ald_i2c_reset(&_h_i2c0); + ald_i2c_init(&_h_i2c0); + +#endif + +#ifdef BSP_USING_I2C1 + +#if defined(ES_I2C1_SCL_GPIO_FUNC)&&defined(ES_I2C1_SCL_GPIO_PORT)&&defined(ES_I2C1_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SCL_GPIO_PORT, ES_I2C1_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + + /* Initialize i2c function */ + _h_i2c1.perh = I2C1; + _h_i2c1.init.module = I2C_MODULE_MASTER; + _h_i2c1.init.clk_speed = ES_I2C1_CLK_SPEED; + _h_i2c1.init.own_addr1 = ES_I2C1_OWN_ADDR1; + _h_i2c1.init.addr_mode = ES_I2C1_ADDR_MODE; + _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL; + _h_i2c1.init.no_stretch = ES_I2C1_STRETCH; + + ald_i2c_reset(&_h_i2c1); + ald_i2c_init(&_h_i2c1); + +#endif +} +#define _I2C_NO_START 0x1 +#define _I2C_NO_STOP 0x2 +int _i2c_master_req(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout,uint32_t req_write) +{ + if (hperh->init.addr_mode == ALD_I2C_ADDR_7BIT) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + else { + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + if (req_write) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return ALD_OK; +} +int _i2c_wait_flag(ald_i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + while (ALD_I2C_GET_FLAG(hperh, flag) == status) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return TIMEOUT; + } + } + + return ALD_OK; +} +int _i2c_wait_txe(ald_i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_TXE) == RESET) { + if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_ARLO)) { + hperh->error_code |= ALD_I2C_ERROR_ARLO; + return ALD_ERROR; + } + + if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_NACK) == SET) { + hperh->error_code |= ALD_I2C_ERROR_AF; + return ALD_ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_ERROR; + } + } + + return ALD_OK; +} +int _i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout,uint32_t flag) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + if ((flag&_I2C_NO_START)==0x0) //NOSTART==0 + { + if (_i2c_wait_flag(hperh, ALD_I2C_STAT_BUSY, SET, 100) != ALD_OK) + return ALD_BUSY; + _i2c_master_req(hperh, dev_addr, timeout,1); + } + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if ((flag&_I2C_NO_STOP)!=0) //NOSTOP==1 + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + else + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + if ((flag&_I2C_NO_START)==0x0) + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + hperh->perh->TXDATA = (*buf++); + size--; + hperh->xfer_count++; + + if (_i2c_wait_txe(hperh, timeout) != ALD_OK) + goto ERROR; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (_i2c_wait_flag(hperh, ALD_I2C_STAT_TCR, RESET, 10) == ALD_OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + if ((flag&_I2C_NO_STOP)==0) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET) + goto SUCCESS; + + if ((flag&_I2C_NO_STOP)!=0&&_i2c_wait_flag(hperh, ALD_I2C_STAT_TCR, RESET, 10) == ALD_OK) + { + goto SUCCESS; + } + + if (_i2c_wait_flag(hperh, ALD_I2C_STAT_TC, RESET, 10) == ALD_OK) { + if ((flag&_I2C_NO_STOP)==0x0) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + } + else { + goto ERROR; + } + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + if (msg->flags & RT_I2C_RD) + { + if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + LOG_E("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + else + { + uint32_t f=((msg->flags&RT_I2C_NO_START)?0x1:0)|((msg->flags&RT_I2C_NO_STOP)?0x2:0); + + if (_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT,f) != 0) + { + LOG_E("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + } + + ret = i; + +out: + //LOG_E("send stop condition\n"); + + return ret; +} + +const struct rt_i2c_bus_device_ops es32f3_i2c_ops = +{ + es32f3_master_xfer, + RT_NULL, + RT_NULL, +}; + +int rt_hw_i2c_init(void) +{ + int result = RT_EOK; + + _i2c_init(); + +#ifdef BSP_USING_I2C0 + /* define i2c Instance */ + static struct rt_i2c_bus_device _i2c_device0; + rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device)); + + _i2c_device0.ops = &es32f3_i2c_ops; + _i2c_device0.priv = &_h_i2c0; + result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0); + if (result != RT_EOK) + { + return result; + } +#endif + +#ifdef BSP_USING_I2C1 + /* define i2c Instance */ + static struct rt_i2c_bus_device _i2c_device1; + rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); + + _i2c_device1.ops = &es32f3_i2c_ops; + _i2c_device1.priv = &_h_i2c1; + rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1); + if (result != RT_EOK) + { + return result; + } +#endif + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_i2c.h b/bsp/essemi/es32vf2264/drivers/drv_i2c.h new file mode 100644 index 0000000000..d04b05c361 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_i2c.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +#include "es_conf_info_i2c.h" + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_pm.c b/bsp/essemi/es32vf2264/drivers/drv_pm.c new file mode 100644 index 0000000000..14c8a2403e --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_pm.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy the first version + */ + +#include "drv_pm.h" + +#ifdef RT_USING_PM + +/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/ +static void sleep(struct rt_pm *pm, uint8_t mode) +{ + rt_base_t level; + level = rt_hw_interrupt_disable(); + rt_hw_interrupt_enable(0x88); + + switch (mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + break; + + case PM_SLEEP_MODE_LIGHT: + ald_pmu_stop_enter(); + break; + + case PM_SLEEP_MODE_DEEP: + ald_pmu_stop_enter(); + break; + + case PM_SLEEP_MODE_STANDBY: + ald_pmu_stop_enter(); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + ald_pmu_stop_enter(); + break; + + default: + RT_ASSERT(0); + break; + } + + rt_hw_interrupt_enable(level); +} + +static void run(struct rt_pm *pm, uint8_t mode) +{ + static uint8_t last_mode; + + if (mode == last_mode) + return; + last_mode = mode; + + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + case PM_RUN_MODE_MEDIUM_SPEED: + case PM_RUN_MODE_LOW_SPEED: + default: + break; + } +} + +/** + * This function caculate the PM tick from OS tick + * + * @param tick OS tick + * + * @return the PM tick + */ +static rt_tick_t es32f3_pm_tick_from_os_tick(rt_tick_t tick) +{ + rt_uint32_t freq = 1; + + return (freq * tick / RT_TICK_PER_SECOND); +} + +/** + * This function caculate the OS tick from PM tick + * + * @param tick PM tick + * + * @return the OS tick + */ +static rt_tick_t es32f3_os_tick_from_pm_tick(rt_uint32_t tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, freq; + + freq = 1; + ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; + + os_tick_remain += (tick * RT_TICK_PER_SECOND); + os_tick_remain %= freq; + + return ret; +} + +/** + * This function start the timer of pm + * + * @param pm Pointer to power manage structure + * @param timeout How many OS Ticks that MCU can sleep + */ +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + RT_ASSERT(pm != RT_NULL); + RT_ASSERT(timeout > 0); + + if (timeout != RT_TICK_MAX) + { + /* Convert OS Tick to pmtimer timeout value */ + timeout = es32f3_pm_tick_from_os_tick(timeout); + /* MAX 0xFFFF */ + if (timeout > 0xFFFF) + { + timeout = 0xFFFF; + } + } +} + +/** + * This function stop the timer of pm + * + * @param pm Pointer to power manage structure + */ +static void pm_timer_stop(struct rt_pm *pm) +{ + RT_ASSERT(pm != RT_NULL); +} + +/** + * This function calculate how many OS Ticks that MCU have suspended + * + * @param pm Pointer to power manage structure + * + * @return OS Ticks + */ +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_uint32_t timer_tick; + + RT_ASSERT(pm != RT_NULL); + + timer_tick = 1; + + return es32f3_os_tick_from_pm_tick(timer_tick); +} + +/** + * This function initialize the power manager + */ +int drv_pm_hw_init(void) +{ + static const struct rt_pm_ops _ops = + { + sleep, + run, + pm_timer_start, + pm_timer_stop, + pm_timer_get_tick + }; + + rt_uint8_t timer_mask = 0; + + /* initialize timer mask */ + timer_mask = 1UL << PM_SLEEP_MODE_DEEP; + + /* initialize system pm module */ + rt_system_pm_init(&_ops, timer_mask, RT_NULL); + + return 0; +} +INIT_BOARD_EXPORT(drv_pm_hw_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_pm.h b/bsp/essemi/es32vf2264/drivers/drv_pm.h new file mode 100644 index 0000000000..cc4a847703 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_pm.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-04-01 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_PM_H__ +#define DRV_PM_H__ + +#include +#include +#include +#include "es_conf_info_pm.h" +#include + +int rt_hw_pm_init(void); + +extern void save_register(void *p_head,uint32_t size,void *p_save); + +extern void load_register(void *p_head,uint32_t size,void *p_load); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_pwm.c b/bsp/essemi/es32vf2264/drivers/drv_pwm.c new file mode 100644 index 0000000000..32a9ff6556 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_pwm.c @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-03-11 wangyq the first version + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include +#include "es_conf_info_pwm.h" + + +#ifdef RT_USING_PWM + +static void pwm_set_duty(ald_timer_handle_t *timer_initstruct, ald_timer_channel_t ch, uint32_t ns) +{ + uint64_t tmp = (uint64_t)ald_cmu_get_pclk_clock() * ns / 1000000000 / + (timer_initstruct->init.prescaler + 1); + + if (ch == ALD_TIMER_CHANNEL_1) + WRITE_REG(timer_initstruct->perh->CCVAL1, (uint32_t)tmp); + else if (ch == ALD_TIMER_CHANNEL_2) + WRITE_REG(timer_initstruct->perh->CCVAL2, (uint32_t)tmp); + else if (ch == ALD_TIMER_CHANNEL_3) + WRITE_REG(timer_initstruct->perh->CCVAL3, (uint32_t)tmp); + else if (ch == ALD_TIMER_CHANNEL_4) + WRITE_REG(timer_initstruct->perh->CCVAL4, (uint32_t)tmp); +} + +static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + rt_err_t ret = RT_EOK; + uint64_t _arr,bus_speed,tmp; + uint32_t _maxcnt,_ccep_ch_en = 0U; + ald_timer_channel_t pwm_channel; + ald_timer_oc_init_t tim_ocinit; + ald_timer_handle_t *timer_initstruct = (ald_timer_handle_t *)device->parent.user_data; + struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(timer_initstruct != RT_NULL); + + + /* select pwm output channel */ + if (1 == cfg->channel) + { + pwm_channel = ALD_TIMER_CHANNEL_1; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK; + } + else if (2 == cfg->channel) + { + pwm_channel = ALD_TIMER_CHANNEL_2; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK; + } + else if (3 == cfg->channel) + { + pwm_channel = ALD_TIMER_CHANNEL_3; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK; + } + else if (4 == cfg->channel) + { + pwm_channel = ALD_TIMER_CHANNEL_4; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK; + } + else + return RT_EINVAL; + + switch (cmd) + { + case PWM_CMD_ENABLE: + ald_timer_pwm_start(timer_initstruct, pwm_channel); + break; + + case PWM_CMD_DISABLE: + ald_timer_pwm_stop(timer_initstruct, pwm_channel); + break; + + case PWM_CMD_SET: + + /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/ + if(!_ccep_ch_en) + { + tim_ocinit.oc_mode = ES_PWM_OC_MODE; + tim_ocinit.oc_polarity = ES_PWM_OC_POLARITY; + tim_ocinit.oc_fast_en = DISABLE; + tim_ocinit.ocn_polarity = ALD_TIMER_OCN_POLARITY_HIGH; + tim_ocinit.ocn_idle = ALD_TIMER_OCN_IDLE_RESET; + tim_ocinit.oc_idle = ALD_TIMER_OC_IDLE_RESET; + + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + } + + bus_speed = (uint64_t)ald_cmu_get_pclk_clock(); + + /*判断外设的计数器最大值*/ +#ifdef ES32F36xx + if((timer_initstruct->perh == GP32C4T0)||(timer_initstruct->perh == GP32C4T1)) + { + _maxcnt = 0xFFFFFFFF; + } + else _maxcnt = 0xFFFF; +#else + _maxcnt = 0xFFFF; +#endif + + /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */ + tmp = bus_speed * (cfg->period)/1000000000/_maxcnt; + timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ; /*bus_speed < 500000000*/ + + /* count registers max , auto adjust prescaler */ + do + { + _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler); + + } + while (_arr > _maxcnt); + + WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); + timer_initstruct->init.period = (uint32_t)_arr; + + /* update prescaler */ + WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); + + pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); + + break; + + case PWM_CMD_GET: + cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 / + READ_REG(timer_initstruct->perh->AR); + break; + + default: + break; + } + return ret; +} + +const static struct rt_pwm_ops es32f3_pwm_ops = +{ + es32f3_pwm_control +}; + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + ald_gpio_init_t gpio_initstructure; + + gpio_initstructure.mode = ALD_GPIO_MODE_OUTPUT; + gpio_initstructure.od = ALD_GPIO_PUSH_PULL; + gpio_initstructure.pupd = ALD_GPIO_PUSH_UP; + gpio_initstructure.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_initstructure.flt = ALD_GPIO_FILTER_DISABLE; + gpio_initstructure.type = ALD_GPIO_TYPE_CMOS; + +#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t0_pwm_dev; + static timer_handle_t ad16c4t0_timer_initstruct; + + ad16c4t0_timer_initstruct.perh = AD16C4T0; + ald_timer_pwm_init(&ad16c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC) + gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f3_pwm_ops, + &ad16c4t0_timer_initstruct); +#endif + +#ifdef BSP_USING_AD16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t1_pwm_dev; + static timer_handle_t ad16c4t1_timer_initstruct; + + ad16c4t1_timer_initstruct.perh = AD16C4T1; + ald_timer_pwm_init(&ad16c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_AD16C4T1_CH1_GPIO_FUNC)&&defined(ES_AD16C4T1_CH1_GPIO_PORT)&&defined(ES_AD16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH1_GPIO_PORT, ES_AD16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH2_GPIO_FUNC)&&defined(ES_AD16C4T1_CH2_GPIO_PORT)&&defined(ES_AD16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH2_GPIO_PORT, ES_AD16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH3_GPIO_FUNC)&&defined(ES_AD16C4T1_CH3_GPIO_PORT)&&defined(ES_AD16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH3_GPIO_PORT, ES_AD16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH4_GPIO_FUNC)&&defined(ES_AD16C4T1_CH4_GPIO_PORT)&&defined(ES_AD16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH4_GPIO_PORT, ES_AD16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t1_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &ad16c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t0_pwm_dev; + static timer_handle_t gp32c4t0_timer_initstruct; + + gp32c4t0_timer_initstruct.perh = GP32C4T0; + ald_timer_pwm_init(&gp32c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T0_CH1_GPIO_FUNC)&&defined(ES_GP32C4T0_CH1_GPIO_PORT)&&defined(ES_GP32C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH1_GPIO_PORT, ES_GP32C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH2_GPIO_FUNC)&&defined(ES_GP32C4T0_CH2_GPIO_PORT)&&defined(ES_GP32C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH2_GPIO_PORT, ES_GP32C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH3_GPIO_FUNC)&&defined(ES_GP32C4T0_CH3_GPIO_PORT)&&defined(ES_GP32C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH3_GPIO_PORT, ES_GP32C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH4_GPIO_FUNC)&&defined(ES_GP32C4T0_CH4_GPIO_PORT)&&defined(ES_GP32C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH4_GPIO_PORT, ES_GP32C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t0_pwm_dev, ES_DEVICE_NAME_GP32C4T0_PWM, &es32f3_pwm_ops, + &gp32c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t1_pwm_dev; + static timer_handle_t gp32c4t1_timer_initstruct; + + gp32c4t1_timer_initstruct.perh = GP32C4T1; + ald_timer_pwm_init(&gp32c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T1_CH1_GPIO_FUNC)&&defined(ES_GP32C4T1_CH1_GPIO_PORT)&&defined(ES_GP32C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH1_GPIO_PORT, ES_GP32C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH2_GPIO_FUNC)&&defined(ES_GP32C4T1_CH2_GPIO_PORT)&&defined(ES_GP32C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH2_GPIO_PORT, ES_GP32C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH3_GPIO_FUNC)&&defined(ES_GP32C4T1_CH3_GPIO_PORT)&&defined(ES_GP32C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH3_GPIO_PORT, ES_GP32C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH4_GPIO_FUNC)&&defined(ES_GP32C4T1_CH4_GPIO_PORT)&&defined(ES_GP32C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH4_GPIO_PORT, ES_GP32C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t1_pwm_dev, ES_DEVICE_NAME_GP32C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t0_pwm_dev; + static ald_timer_handle_t gp16c4t0_timer_initstruct; + + gp16c4t0_timer_initstruct.perh = GP16C4T0; + ald_timer_pwm_init(&gp16c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f3_pwm_ops, + &gp16c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t1_pwm_dev; + static timer_handle_t gp16c4t1_timer_initstruct; + + gp16c4t1_timer_initstruct.perh = GP16C4T1; + ald_timer_pwm_init(&gp16c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP16C4T1_CH1_GPIO_FUNC)&&defined(ES_GP16C4T1_CH1_GPIO_PORT)&&defined(ES_GP16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH1_GPIO_PORT, ES_GP16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH2_GPIO_FUNC)&&defined(ES_GP16C4T1_CH2_GPIO_PORT)&&defined(ES_GP16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH2_GPIO_PORT, ES_GP16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH3_GPIO_FUNC)&&defined(ES_GP16C4T1_CH3_GPIO_PORT)&&defined(ES_GP16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH3_GPIO_PORT, ES_GP16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH4_GPIO_FUNC)&&defined(ES_GP16C4T1_CH4_GPIO_PORT)&&defined(ES_GP16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH4_GPIO_PORT, ES_GP16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t1_pwm_dev, ES_DEVICE_NAME_GP16C4T1_PWM, &es32f3_pwm_ops, + &gp16c4t1_timer_initstruct); +#endif + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_pwm.h b/bsp/essemi/es32vf2264/drivers/drv_pwm.h new file mode 100644 index 0000000000..f4fcfe7cff --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-11 wangyq the first version + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_spi.c b/bsp/essemi/es32vf2264/drivers/drv_spi.c new file mode 100644 index 0000000000..940ddb541d --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_spi.c @@ -0,0 +1,430 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_spi.h" + + +#ifdef RT_USING_SPI + +#define SPITIMEOUT 0xFFF + +rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *cfg) +{ + ald_spi_handle_t *hspi; + hspi = (ald_spi_handle_t *)device->bus->parent.user_data; + + hspi->init.ss_en = DISABLE; + hspi->init.crc_calc = DISABLE; + hspi->init.frame = ALD_SPI_FRAME_MOTOROLA; + + /* config spi mode */ + if (cfg->mode & RT_SPI_SLAVE) + { + hspi->init.mode = ALD_SPI_MODE_SLAVER; + } + else + { + hspi->init.mode = ALD_SPI_MODE_MASTER; + } + if (cfg->mode & RT_SPI_3WIRE) + { + hspi->init.dir = ALD_SPI_DIRECTION_1LINE; + } + else + { + hspi->init.dir = ALD_SPI_DIRECTION_2LINES; + } + if (cfg->data_width == 8) + { + hspi->init.data_size = ALD_SPI_DATA_SIZE_8; + } + else if (cfg->data_width == 16) + { + hspi->init.data_size = ALD_SPI_DATA_SIZE_16; + } + + if (cfg->mode & RT_SPI_CPHA) + { + hspi->init.phase = ALD_SPI_CPHA_SECOND; + } + else + { + hspi->init.phase = ALD_SPI_CPHA_FIRST; + } + if (cfg->mode & RT_SPI_MSB) + { + hspi->init.first_bit = ALD_SPI_FIRSTBIT_MSB; + } + else + { + hspi->init.first_bit = ALD_SPI_FIRSTBIT_LSB; + } + + if (cfg->mode & RT_SPI_CPOL) + { + hspi->init.polarity = ALD_SPI_CPOL_HIGH; + } + else + { + hspi->init.polarity = ALD_SPI_CPOL_LOW; + } + if (cfg->mode & RT_SPI_NO_CS) + { + hspi->init.ss_en = DISABLE; + } + else + { + hspi->init.ss_en = ENABLE; + } + + /* config spi clock */ + if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 2) + { + hspi->init.baud = ALD_SPI_BAUD_2; + } + else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 4) + { + hspi->init.baud = ALD_SPI_BAUD_4; + } + else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 8) + { + hspi->init.baud = ALD_SPI_BAUD_8; + } + else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 16) + { + hspi->init.baud = ALD_SPI_BAUD_16; + } + else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 32) + { + hspi->init.baud = ALD_SPI_BAUD_32; + } + else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 64) + { + hspi->init.baud = ALD_SPI_BAUD_64; + } + else if (cfg->max_hz >= ald_cmu_get_pclk_clock() / 128) + { + hspi->init.baud = ALD_SPI_BAUD_128; + } + else + { + hspi->init.baud = ALD_SPI_BAUD_256; + } + ALD_SPI_DISABLE(hspi); + ald_spi_init(hspi); + return RT_EOK; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + ald_spi_handle_t *hspi; + struct es32f3_hw_spi_cs *cs; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + hspi = (ald_spi_handle_t *)device->bus->parent.user_data; + cs = device->parent.user_data; + + if (message->cs_take) + { + rt_pin_write(cs->pin, ES_SPI_CS_LEVEL); + } + + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) + { + /* send & receive */ + if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) + { + res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); + } + else + { + /* only send data */ + if (message->recv_buf == RT_NULL) + { + res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + } + /* only receive data */ + if (message->send_buf == RT_NULL) + { + res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + } + } + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + + if (res != RT_EOK) + return RT_ERROR; + else + return message->length; + + } + else + { + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + return RT_EOK; + } + +} +const struct rt_spi_ops es32f3_spi_i2s_ops = +{ + RT_NULL, + RT_NULL, +}; +const struct rt_spi_ops es32f3_spi_ops = +{ + spi_configure, + spixfer, +}; + +rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) +{ + int result; + /* define spi Instance */ + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, 1); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + +#ifdef BSP_USING_SPI0 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0); +#endif +#ifdef BSP_USING_SPI1 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); +#endif +#ifdef BSP_USING_SPI2 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI2_BUS)))SPI_BUS_CONFIG(spi_device->config,2); +#endif + + return result; +} + +#ifdef BSP_USING_SPI0 + static struct rt_spi_bus _spi_bus0; + static ald_spi_handle_t _spi0; +#endif + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus _spi_bus1; + static spi_handle_t _spi1; +#endif + +#ifdef BSP_USING_SPI2 + static struct rt_spi_bus _spi_bus2; + static spi_handle_t _spi2; +#endif + +int rt_hw_spi_init(void) +{ + int result = RT_EOK; + + struct rt_spi_bus *spi_bus; + ald_spi_handle_t *spi; + ald_gpio_init_t gpio_instruct; + + gpio_instruct.pupd = ALD_GPIO_PUSH_UP_DOWN; + gpio_instruct.od = ALD_GPIO_PUSH_PULL; + gpio_instruct.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_instruct.type = ALD_GPIO_TYPE_CMOS; + gpio_instruct.flt = ALD_GPIO_FILTER_DISABLE; + +#ifdef BSP_USING_SPI0 + _spi0.perh = SPI0; + spi_bus = &_spi_bus0; + spi = &_spi0; + /* SPI0 gpio init */ + gpio_instruct.mode = ALD_GPIO_MODE_OUTPUT; + +#if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct); +#endif + +#if !defined(ES_SPI0_I2S_MODE) + gpio_instruct.mode = ALD_GPIO_MODE_INPUT; +#endif + +#if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI0_I2S_MODE)&&defined(ES_SPI0_NSS_GPIO_FUNC)&&defined(ES_SPI0_NSS_GPIO_PORT)&&defined(ES_SPI0_NSS_GPIO_PIN) + gpio_instruct.func = ES_SPI0_NSS_GPIO_FUNC; + ald_gpio_init(ES_SPI0_NSS_GPIO_PORT, ES_SPI0_NSS_GPIO_PIN, &gpio_instruct); +#endif + + spi_bus->parent.user_data = spi; + #if defined(ES_SPI0_I2S_MODE) + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_i2s_ops); + #else + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_ops); + if (result != RT_EOK) + { + return result; + } + + result = es32f3_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0); + + if (result != RT_EOK) + { + return result; + } + #endif + +#endif + +#ifdef BSP_USING_SPI1 + _spi1.perh = SPI1; + spi_bus = &_spi_bus1; + spi = &_spi1; + + /* SPI1 gpio init */ + gpio_instruct.mode = GPIO_MODE_OUTPUT; + +#if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); +#endif + +#if !defined(ES_SPI1_I2S_MODE) + gpio_instruct.mode = GPIO_MODE_INPUT; +#endif + +#if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_I2S_MODE)&&defined(ES_SPI1_NSS_GPIO_FUNC)&&defined(ES_SPI1_NSS_GPIO_PORT)&&defined(ES_SPI1_NSS_GPIO_PIN) + gpio_instruct.func = ES_SPI1_NSS_GPIO_FUNC; + ald_gpio_init(ES_SPI1_NSS_GPIO_PORT, ES_SPI1_NSS_GPIO_PIN, &gpio_instruct); +#endif + + spi_bus->parent.user_data = spi; + #if defined(ES_SPI1_I2S_MODE) + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_i2s_ops); + #else + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_ops); + if (result != RT_EOK) + { + return result; + } + + result = es32f3_spi_device_attach(ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0); + + if (result != RT_EOK) + { + return result; + } + #endif +#endif + +#ifdef BSP_USING_SPI2 + _spi2.perh = SPI2; + spi_bus = &_spi_bus2; + spi = &_spi2; + + /* SPI2 gpio init */ + gpio_instruct.mode = GPIO_MODE_OUTPUT; + +#if defined(ES_SPI2_SCK_GPIO_FUNC)&&defined(ES_SPI2_SCK_GPIO_PORT)&&defined(ES_SPI2_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI2_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI2_SCK_GPIO_PORT, ES_SPI2_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI2_MOSI_GPIO_FUNC)&&defined(ES_SPI2_MOSI_GPIO_PORT)&&defined(ES_SPI2_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MOSI_GPIO_PORT, ES_SPI2_MOSI_GPIO_PIN, &gpio_instruct); +#endif + +#if !defined(ES_SPI2_I2S_MODE) + gpio_instruct.mode = GPIO_MODE_INPUT; +#endif + +#if defined(ES_SPI2_MISO_GPIO_FUNC)&&defined(ES_SPI2_MISO_GPIO_PORT)&&defined(ES_SPI2_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MISO_GPIO_PORT, ES_SPI2_MISO_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI2_I2S_MODE)&&defined(ES_SPI2_NSS_GPIO_FUNC)&&defined(ES_SPI2_NSS_GPIO_PORT)&&defined(ES_SPI2_NSS_GPIO_PIN) + gpio_instruct.func = ES_SPI2_NSS_GPIO_FUNC; + ald_gpio_init(ES_SPI2_NSS_GPIO_PORT, ES_SPI2_NSS_GPIO_PIN, &gpio_instruct); +#endif + + spi_bus->parent.user_data = spi; + #if defined(ES_SPI2_I2S_MODE) + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_i2s_ops); + #else + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI2_BUS, &es32f3_spi_ops); + if (result != RT_EOK) + { + return result; + } + + result = es32f3_spi_device_attach(ES_SPI2_NSS_PIN, ES_DEVICE_NAME_SPI2_BUS, ES_DEVICE_NAME_SPI1_DEV0); + + if (result != RT_EOK) + { + return result; + } + #endif +#endif + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_spi.h b/bsp/essemi/es32vf2264/drivers/drv_spi.h new file mode 100644 index 0000000000..0938f9aed4 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_spi.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include +#include +#include + +#include "es_conf_info_spi.h" + +struct es32f3_hw_spi_cs +{ + rt_uint32_t pin; +}; + +/* cannot be used before completion init */ +rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_spiflash.c b/bsp/essemi/es32vf2264/drivers/drv_spiflash.c new file mode 100644 index 0000000000..334f908887 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_spiflash.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2019-11-01 wangyq update libraries + */ + +#include "board.h" +#include + +#if defined(BSP_USING_SPI_FLASH) + +#include "spi_flash.h" +#include "drv_spiflash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +int rt_hw_spi_flash_init(void) +{ + + if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV)) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_spiflash.h b/bsp/essemi/es32vf2264/drivers/drv_spiflash.h new file mode 100644 index 0000000000..9c90e1caf2 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_spiflash.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +#include "es_conf_info_spi.h" + +int rt_hw_spi_flash_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_uart.c b/bsp/essemi/es32vf2264/drivers/drv_uart.c new file mode 100644 index 0000000000..0c88798f35 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_uart.c @@ -0,0 +1,770 @@ +/* + * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2023-02-11 liuhy the first version + */ + +#include "drv_uart.h" + +#ifdef RT_USING_SERIAL + +#define UART_DMA_BUF_SECTIONS 4 + +/* + * To use UART DMA, + * 1. select 'DMA->DMA0' + * 2. select 'UART->UARTx->DMATX(or DMARX)' + * 3. add RT_DEVICE_FLAG_DMA_TX(or RT_DEVICE_FLAG_DMA_RX) flag when open serial device + */ +#ifdef BSP_EUART0_TX_USING_DMA +#define EUART0_DMATX_CHANNEL ES_EUART0_DMATX_CHANNEL +#define EUART0_DMATX_FLAG RT_DEVICE_FLAG_DMA_TX +#else +#define EUART0_DMATX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define EUART0_DMATX_FLAG 0 +#endif + +#ifdef BSP_EUART0_RX_USING_DMA +#define EUART0_DMARX_CHANNEL ES_EUART0_DMARX_CHANNEL +#define EUART0_DMARX_FLAG RT_DEVICE_FLAG_DMA_RX +#else +#define EUART0_DMARX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define EUART0_DMARX_FLAG 0 +#endif + +#ifdef BSP_EUART1_TX_USING_DMA +#define EUART1_DMATX_CHANNEL ES_EUART1_DMATX_CHANNEL +#define EUART1_DMATX_FLAG RT_DEVICE_FLAG_DMA_TX +#else +#define EUART1_DMATX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define EUART1_DMATX_FLAG 0 +#endif + +#ifdef BSP_EUART1_RX_USING_DMA +#define EUART1_DMARX_CHANNEL ES_EUART1_DMARX_CHANNEL +#define EUART1_DMARX_FLAG RT_DEVICE_FLAG_DMA_RX +#else +#define EUART1_DMARX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define EUART1_DMARX_FLAG 0 +#endif + +#ifdef BSP_CUART0_TX_USING_DMA +#define CUART0_DMATX_CHANNEL ES_CUART0_DMATX_CHANNEL +#define CUART0_DMATX_FLAG RT_DEVICE_FLAG_DMA_TX +#else +#define CUART0_DMATX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define CUART0_DMATX_FLAG 0 +#endif + +#ifdef BSP_CUART0_RX_USING_DMA +#define CUART0_DMARX_CHANNEL ES_CUART0_DMARX_CHANNEL +#define CUART0_DMARX_FLAG RT_DEVICE_FLAG_DMA_RX +#else +#define CUART0_DMARX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define CUART0_DMARX_FLAG 0 +#endif + +#ifdef BSP_CUART1_TX_USING_DMA +#define CUART1_DMATX_CHANNEL ES_CUART1_DMATX_CHANNEL +#define CUART1_DMATX_FLAG RT_DEVICE_FLAG_DMA_TX +#else +#define CUART1_DMATX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define CUART1_DMATX_FLAG 0 +#endif + +#ifdef BSP_CUART1_RX_USING_DMA +#define CUART1_DMARX_CHANNEL ES_CUART1_DMARX_CHANNEL +#define CUART1_DMARX_FLAG RT_DEVICE_FLAG_DMA_RX +#else +#define CUART1_DMARX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define CUART1_DMARX_FLAG 0 +#endif + +#ifdef BSP_CUART2_TX_USING_DMA +#define CUART2_DMATX_CHANNEL ES_CUART2_DMATX_CHANNEL +#define CUART2_DMATX_FLAG RT_DEVICE_FLAG_DMA_TX +#else +#define CUART2_DMATX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define CUART2_DMATX_FLAG 0 +#endif + +#ifdef BSP_CUART2_RX_USING_DMA +#define CUART2_DMARX_CHANNEL ES_CUART2_DMARX_CHANNEL +#define CUART2_DMARX_FLAG RT_DEVICE_FLAG_DMA_RX +#else +#define CUART2_DMARX_CHANNEL ES_DMA_INVAILD_CHANNEL +#define CUART2_DMARX_FLAG 0 +#endif + +#define UART_INVAILD_DMA_CHANNEL (ES_DMA_INVAILD_CHANNEL) + +/* es32 uart driver */ +struct es32_uart +{ + ald_uart_handle_t huart; + struct rt_serial_device *serial; + IRQn_Type irq; +#ifdef RT_SERIAL_USING_DMA + uint16_t dma_tx_channel; + uint16_t dma_rx_channel; + + uint32_t last_rx_count; + uint32_t buf_select; +#endif /* RT_SERIAL_USING_DMA */ +}; + +#ifdef RT_SERIAL_USING_DMA + static void _dma_recv_timeout(struct es32_uart *uart, uint32_t dma_end); +#endif /* RT_SERIAL_USING_DMA */ + +static void uart_int_handler(struct es32_uart*uart) +{ + if ((ald_uart_get_mask_flag_status(&uart->huart, ALD_UART_IF_RFNEMPTY)) != RESET) + { + rt_hw_serial_isr(uart->serial, RT_SERIAL_EVENT_RX_IND); + ald_uart_clear_flag_status(&uart->huart, ALD_UART_IF_RFNEMPTY); + } + #ifdef RT_SERIAL_USING_DMA + if ((ald_uart_get_mask_flag_status(&uart->huart, ALD_UART_IF_RXTO)) != RESET) + { + ald_uart_clear_flag_status(&uart->huart, ALD_UART_IF_RXTO); + _dma_recv_timeout(uart, 0); + } + + if ((ald_uart_get_mask_flag_status(&uart->huart, ALD_UART_IF_TBC)) != RESET) + { + uint32_t cnt = 1000; + ald_uart_clear_flag_status(&uart->huart, ALD_UART_IF_TBC); + ald_uart_interrupt_config(&uart->huart, ALD_UART_IT_TBC, DISABLE); + CLEAR_BIT(uart->huart.state, ALD_UART_STATE_TX_MASK); + + while ((uart->huart.perh->STAT & ALD_UART_STATUS_TSBUSY) && (cnt--)); + + ald_uart_clear_flag_status(&uart->huart, ALD_UART_IF_TBC); + + if (uart->huart.tx_cplt_cbk) + uart->huart.tx_cplt_cbk(&uart->huart); + } + #endif /* RT_SERIAL_USING_DMA */ +} + + +#ifdef BSP_USING_EUART0 + +struct rt_serial_device serial0; +/* EUART0 device driver structure */ +struct es32_uart uart0 = +{ + {EUART0}, + &serial0, + EUART0_IRQn, +#ifdef RT_SERIAL_USING_DMA + EUART0_DMATX_CHANNEL, + EUART0_DMARX_CHANNEL +#endif /* RT_SERIAL_USING_DMA */ +}; +void __attribute__((interrupt)) EUART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + uart_int_handler(&uart0); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_EUART0 */ + +#ifdef BSP_USING_EUART1 + +struct rt_serial_device serial1; +/* EUART1 device driver structure */ +struct es32_uart uart1 = +{ + {EUART1}, + &serial1, + EUART1_IRQn, +#ifdef RT_SERIAL_USING_DMA + EUART1_DMATX_CHANNEL, + EUART1_DMARX_CHANNEL +#endif /* RT_SERIAL_USING_DMA */ +}; + +void __attribute__((interrupt)) EUART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + uart_int_handler(&uart1); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_EUART1 */ + +#ifdef BSP_USING_CUART0 + +struct rt_serial_device serial2; +/* CUART0 device driver structure */ +struct es32_uart uart2 = +{ + {CUART0}, + &serial2, + CUART0_IRQn, +#ifdef RT_SERIAL_USING_DMA + CUART0_DMATX_CHANNEL, + CUART0_DMARX_CHANNEL +#endif /* RT_SERIAL_USING_DMA */ +}; + +void __attribute__((interrupt)) CUART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + uart_int_handler(&uart2); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_CUART0 */ + +#ifdef BSP_USING_CUART1 + +struct rt_serial_device serial3; +/* CUART1 device driver structure */ +struct es32_uart uart3 = +{ + {CUART1}, + &serial3, + CUART1_IRQn, +#ifdef RT_SERIAL_USING_DMA + CUART1_DMATX_CHANNEL, + CUART1_DMARX_CHANNEL +#endif /* RT_SERIAL_USING_DMA */ +}; + +void __attribute__((interrupt)) CUART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + uart_int_handler(&uart3); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_CUART1 */ + +#ifdef BSP_USING_CUART2 + +struct rt_serial_device serial4; +/* CUART2 device driver structure */ +struct es32_uart uart4 = +{ + {CUART2}, + &serial4, + CUART2_IRQn, +#ifdef RT_SERIAL_USING_DMA + CUART2_DMATX_CHANNEL, + CUART2_DMARX_CHANNEL +#endif /* RT_SERIAL_USING_DMA */ +}; + +void __attribute__((interrupt)) CUART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + uart_int_handler(&uart4); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_CUART2 */ + +static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + ald_gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = ALD_GPIO_MODE_OUTPUT; + gpio_initstructure.od = ALD_GPIO_PUSH_PULL; + gpio_initstructure.pupd = ALD_GPIO_PUSH_UP; + gpio_initstructure.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + gpio_initstructure.flt = ALD_GPIO_FILTER_DISABLE; + gpio_initstructure.type = ALD_GPIO_TYPE_CMOS; + +#ifdef BSP_USING_EUART0 + + if (uart == (&uart0)) + { +#if defined(ES_EUART0_TX_GPIO_FUNC)&&defined(ES_EUART0_TX_GPIO_PORT)&&defined(ES_EUART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_EUART0_TX_GPIO_FUNC; + ald_gpio_init(ES_EUART0_TX_GPIO_PORT, ES_EUART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_EUART0_RX_GPIO_FUNC)&&defined(ES_EUART0_RX_GPIO_PORT)&&defined(ES_EUART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = ALD_GPIO_MODE_INPUT; + gpio_initstructure.func = ES_EUART0_RX_GPIO_FUNC; + ald_gpio_init(ES_EUART0_RX_GPIO_PORT, ES_EUART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + } + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_EUART1 + + if (uart == (&uart1)) + { +#if defined(ES_EUART1_TX_GPIO_FUNC)&&defined(ES_EUART1_TX_GPIO_PORT)&&defined(ES_EUART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_EUART1_TX_GPIO_FUNC; + ald_gpio_init(ES_EUART1_TX_GPIO_PORT, ES_EUART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_EUART1_RX_GPIO_FUNC)&&defined(ES_EUART1_RX_GPIO_PORT)&&defined(ES_EUART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = ALD_GPIO_MODE_INPUT; + gpio_initstructure.func = ES_EUART1_RX_GPIO_FUNC; + ald_gpio_init(ES_EUART1_RX_GPIO_PORT, ES_EUART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + } + +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_CUART0 + + if (uart == (&uart2)) + { +#if defined(ES_CUART0_TX_GPIO_FUNC)&&defined(ES_CUART0_TX_GPIO_PORT)&&defined(ES_CUART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_CUART0_TX_GPIO_FUNC; + ald_gpio_init(ES_CUART0_TX_GPIO_PORT, ES_CUART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_CUART0_RX_GPIO_FUNC)&&defined(ES_CUART0_RX_GPIO_PORT)&&defined(ES_CUART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = ALD_GPIO_MODE_INPUT; + gpio_initstructure.func = ES_CUART0_RX_GPIO_FUNC; + ald_gpio_init(ES_CUART0_RX_GPIO_PORT, ES_CUART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + } + +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_CUART1 + + if (uart == (&uart3)) + { +#if defined(ES_CUART1_TX_GPIO_FUNC)&&defined(ES_CUART1_TX_GPIO_PORT)&&defined(ES_CUART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_CUART1_TX_GPIO_FUNC; + ald_gpio_init(ES_CUART1_TX_GPIO_PORT, ES_CUART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_CUART1_RX_GPIO_FUNC)&&defined(ES_CUART1_RX_GPIO_PORT)&&defined(ES_CUART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = ALD_GPIO_MODE_INPUT; + gpio_initstructure.func = ES_CUART1_RX_GPIO_FUNC; + ald_gpio_init(ES_CUART1_RX_GPIO_PORT, ES_CUART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + } + +#endif /* uart3 gpio init */ + +#ifdef BSP_USING_CUART2 + + if (uart == (&uart4)) + { +#if defined(ES_CUART2_TX_GPIO_FUNC)&&defined(ES_CUART2_TX_GPIO_PORT)&&defined(ES_CUART2_TX_GPIO_PIN) + gpio_initstructure.func = ES_CUART2_TX_GPIO_FUNC; + ald_gpio_init(ES_CUART2_TX_GPIO_PORT, ES_CUART2_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_CUART2_RX_GPIO_FUNC)&&defined(ES_CUART2_RX_GPIO_PORT)&&defined(ES_CUART2_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = ALD_GPIO_MODE_INPUT; + gpio_initstructure.func = ES_CUART2_RX_GPIO_FUNC; + ald_gpio_init(ES_CUART2_RX_GPIO_PORT, ES_CUART2_RX_GPIO_PIN, &gpio_initstructure); +#endif + } + +#endif /* uart4 gpio init */ + + uart->huart.init.mode = ALD_UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (ald_uart_word_length_t)(8 - cfg->data_bits); + uart->huart.init.parity = (ald_uart_parity_t)(cfg->parity == PARITY_EVEN ? ALD_UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = ALD_UART_HW_FLOW_CTL_DISABLE; + uart->huart.init.stop_bits = ALD_UART_STOP_BITS_1; + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + ALD_UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + ALD_UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + ALD_UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + ALD_UART_DATA_INV_DISABLE(&uart->huart); + } + + return RT_EOK; +} + + + +#ifdef RT_SERIAL_USING_DMA + +static void _dma_recv_timeout(struct es32_uart *uart, uint32_t dma_end) +{ + ald_dma_config_t *dma_cfg; + uint32_t rx_count_total; + uint32_t rx_count; + uint16_t dma_remain_transfer_num; + + if (dma_end) + { + rx_count = dma_end - uart->last_rx_count; + uart->last_rx_count = 0; + } + else + { + dma_cfg = &uart->huart.hdmarx.config; + dma_remain_transfer_num = (uint16_t)((DMA->CHANNEL[dma_cfg->channel].NDT) >> 16); + rx_count_total = (dma_cfg->size) - dma_remain_transfer_num; + + if (rx_count_total) + rx_count = rx_count_total - uart->last_rx_count; + else + return; + + uart->last_rx_count = rx_count_total; + } + + rt_hw_serial_isr(uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (rx_count << 8)); + +} + +/** + * DMA TX complete callback + */ +static void _uart_tx_dma_cplt(ald_uart_handle_t *arg) +{ + struct es32_uart *uart; + uart = rt_container_of(arg, struct es32_uart, huart); + rt_hw_serial_isr(uart->serial, RT_SERIAL_EVENT_TX_DMADONE); +} +/** + * DMA RX complete callback + */ +static void _uart_rx_dma_cplt(ald_uart_handle_t *arg) +{ + struct es32_uart *uart; + uart = rt_container_of(arg, struct es32_uart, huart); + + if (uart->buf_select == UART_DMA_BUF_SECTIONS - 1) + { + arg->hdmarx.config.dst = (uint8_t *)arg->hdmarx.config.dst - arg->hdmarx.config.size * (UART_DMA_BUF_SECTIONS - 1); + uart->buf_select = 0; + } + else + { + arg->hdmarx.config.dst = (uint8_t *)arg->hdmarx.config.dst + arg->hdmarx.config.size; + uart->buf_select += 1; + } + + ald_dma_config_basic(&(arg->hdmarx)); + ald_uart_dma_req_config(arg, ALD_UART_DMA_REQ_RX, ENABLE); + _dma_recv_timeout(uart, arg->hdmarx.config.size); +} +/** + * Setup DMA + */ +static rt_err_t es32f3x_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct es32_uart *uart; + struct rt_serial_rx_fifo *rx_fifo; + extern ald_dma_call_back_t dma_cbk[]; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + if (serial->config.bufsz > 0xFFFF) + return -RT_ERROR; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + if (uart->dma_rx_channel >= UART_INVAILD_DMA_CHANNEL) + return -ALD_ERROR; + + uart->huart.rx_cplt_cbk = _uart_rx_dma_cplt; + //dma_cbk[uart->dma_rx_channel].cplt_tc_cbk = _uart_rx_dma_cplt; + + ALD_UART_SET_TIMEOUT_VALUE(&uart->huart, 0xFF); + ALD_UART_RX_TIMEOUT_ENABLE(&uart->huart); + ald_uart_interrupt_config(&uart->huart, ALD_UART_IT_RFNEMPTY, DISABLE); + ald_uart_interrupt_config(&uart->huart, ALD_UART_IT_RXTO, ENABLE); + uart->last_rx_count = 0; + + if (serial->config.bufsz > 0) + { + ald_uart_recv_by_dma(&uart->huart, rx_fifo->buffer, serial->config.bufsz / UART_DMA_BUF_SECTIONS, uart->dma_rx_channel);; + } + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + if (uart->dma_tx_channel >= UART_INVAILD_DMA_CHANNEL) + return -ALD_ERROR; + + uart->huart.tx_cplt_cbk = _uart_tx_dma_cplt; + dma_cbk[uart->dma_tx_channel].cplt_tc_cbk = _uart_tx_dma_cplt; + } + + uart->huart.err_code = ALD_UART_ERROR_NONE; + + csi_vic_enable_sirq(uart->irq); + + return RT_EOK; +} +#endif /* RT_SERIAL_USING_DMA */ + +static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + csi_vic_disable_sirq(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, ALD_UART_IT_RFNEMPTY, DISABLE); +#ifdef RT_SERIAL_USING_DMA + + /* disable DMA */ + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + ald_uart_dma_req_config(&uart->huart, ALD_UART_DMA_REQ_RX, DISABLE); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { + ald_uart_dma_req_config(&uart->huart, ALD_UART_DMA_REQ_TX, DISABLE); + } + +#endif + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + csi_vic_enable_sirq(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, ALD_UART_IT_RFNEMPTY, ENABLE); + break; +#ifdef RT_SERIAL_USING_DMA + + case RT_DEVICE_CTRL_CONFIG: + /* Setup DMA */ + es32f3x_dma_config(serial, ctrl_arg); + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + while (ald_uart_get_status(&uart->huart, (ALD_UART_STATUS_TSBUSY))); + +#ifdef RT_SERIAL_USING_DMA + uart->huart.rx_cplt_cbk = NULL; + uart->huart.tx_cplt_cbk = NULL; + /* disable DMA */ + ald_uart_dma_stop(&uart->huart); +#endif + ald_uart_reset(&uart->huart); + break; + } + + return RT_EOK; +} + +static int es32f3x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (ald_uart_get_status(&uart->huart, ALD_UART_STATUS_TFEMPTY) == RESET) + ; + + WRITE_REG(uart->huart.perh->TXBUF, c); + + return 1; +} + +static int es32f3x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (ald_uart_get_status(&uart->huart, ALD_UART_STATUS_RFNEMPTY)) + { + ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); + } + + return ch; +} + +#ifdef RT_SERIAL_USING_DMA + +/** + * DMA transmit + */ +static rt_ssize_t es32f3x_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (direction == RT_SERIAL_DMA_TX) + { + if (uart->dma_tx_channel >= UART_INVAILD_DMA_CHANNEL) + return 0; + + if (ALD_OK == ald_uart_send_by_dma(&uart->huart, buf, size, uart->dma_tx_channel)) + { + return size; + } + else + { + return 0; + } + } + else if (direction == RT_SERIAL_DMA_RX) + { + + if (uart->dma_rx_channel >= UART_INVAILD_DMA_CHANNEL) + return 0; + + if (ALD_OK == ald_uart_recv_by_dma(&uart->huart, buf, size, uart->dma_rx_channel)) + { + return size; + } + else + { + return 0; + } + + } + + return 0; +} +#endif +static const struct rt_uart_ops es32f3x_uart_ops = +{ + es32f3x_configure, + es32f3x_control, + es32f3x_putc, + es32f3x_getc, +#ifdef RT_SERIAL_USING_DMA + es32f3x_dma_transmit +#else + NULL +#endif +}; + +int rt_hw_uart_init(void) +{ + struct es32_uart *uart; + +#ifdef BSP_USING_EUART0 + uart = &uart0; + serial0.ops = &es32f3x_uart_ops; + serial0.config = (struct serial_configure)ES_EUART0_CONFIG; + + /* register EUART0 device */ + rt_hw_serial_register(&serial0, ES_DEVICE_NAME_EUART0, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + EUART0_DMATX_FLAG | EUART0_DMARX_FLAG, + uart); +#endif /* BSP_USING_EUART0 */ + +#ifdef BSP_USING_EUART1 + uart = &uart1; + serial1.ops = &es32f3x_uart_ops; + serial1.config = (struct serial_configure)ES_EUART1_CONFIG; + + /* register EUART1 device */ + rt_hw_serial_register(&serial1, ES_DEVICE_NAME_EUART1, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + EUART1_DMATX_FLAG | EUART1_DMARX_FLAG, + uart); +#endif /* BSP_USING_EUART1 */ + +#ifdef BSP_USING_CUART0 + uart = &uart2; + serial2.ops = &es32f3x_uart_ops; + serial2.config = (struct serial_configure)ES_CUART0_CONFIG; + + /* register CUART0 device */ + rt_hw_serial_register(&serial2, ES_DEVICE_NAME_CUART0, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + CUART0_DMATX_FLAG | CUART0_DMARX_FLAG, + uart); +#endif /* BSP_USING_CUART0 */ + +#ifdef BSP_USING_CUART1 + uart = &uart3; + serial3.ops = &es32f3x_uart_ops; + serial3.config = (struct serial_configure)ES_CUART1_CONFIG; + + /* register CUART1 device */ + rt_hw_serial_register(&serial3, ES_DEVICE_NAME_CUART1, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + CUART1_DMATX_FLAG | CUART1_DMARX_FLAG, + uart); +#endif /* BSP_USING_CUART1 */ + +#ifdef BSP_USING_CUART2 + uart = &uart4; + serial4.ops = &es32f3x_uart_ops; + serial4.config = (struct serial_configure)ES_CUART2_CONFIG; + + /* register CUART2 device */ + rt_hw_serial_register(&serial4, ES_DEVICE_NAME_CUART2, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + CUART2_DMATX_FLAG | CUART2_DMARX_FLAG, + uart); +#endif /* BSP_USING_CUART2 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_uart.h b/bsp/essemi/es32vf2264/drivers/drv_uart.h new file mode 100644 index 0000000000..87e7d2a538 --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/drv_uart.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2022 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2022-02-11 Lisq the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +#include "board.h" + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/es32vf2264.ld b/bsp/essemi/es32vf2264/drivers/es32vf2264.ld new file mode 100644 index 0000000000..f369ad2b2f --- /dev/null +++ b/bsp/essemi/es32vf2264/drivers/es32vf2264.ld @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + +/****************************************************************************** + * @file gcc_csky.ld + * @brief csky linker file + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ +MEMORY +{ + I-SRAM : ORIGIN = 0x00000000 , LENGTH = 0x40000 /* I-SRAM 256KB */ + D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0x8000 /* D-SRAM 32KB */ + O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000 /* off-chip SRAM 8MB */ + SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* on-chip SRAM 128KB */ +} + +__min_heap_size = 0x200; +__rt_rvstack_bss_size = 0x400; +PROVIDE (__ram_end = 0x20007FFF); +PROVIDE (__heap_end = __ram_end); + +REGION_ALIAS("REGION_TEXT", I-SRAM); +REGION_ALIAS("REGION_RODATA", I-SRAM); +REGION_ALIAS("REGION_DATA", D-SRAM); +REGION_ALIAS("REGION_BSS", D-SRAM); + +ENTRY(Reset_Handler) +SECTIONS +{ + .text : { + . = ALIGN(0x4) ; + __stext = . ; + KEEP(*startup_es32vf2264.o(*.text*)) + *(.text) + *(.text*) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.gnu.linkonce.t*) + *(.glue_7t) + *(.glue_7) + *(.jcr) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(0x40) ; + KEEP(*startup_es32vf2264.o(*.vectors*)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN (4) ; + PROVIDE(__ctbp = .); + *(.call_table_data) + *(.call_table_text) + . = ALIGN(0x10) ; + __etext = . ; + } > REGION_TEXT + + + .eh_frame_hdr : { + *(.eh_frame_hdr) + } > REGION_TEXT + + + .eh_frame : ONLY_IF_RO { + KEEP (*(.eh_frame)) + } > REGION_TEXT + + + .gcc_except_table : ONLY_IF_RO { + *(.gcc_except_table .gcc_except_table.*) + } > REGION_TEXT + + + .rodata : { + . = ALIGN(0x4) ; + __srodata = .; + *(.rdata) + *(.rdata*) + *(.rdata1) + *(.rdata.*) + KEEP (*(.rti_fn.0)) + KEEP (*(.rti_fn.0.end)) + KEEP (*(.rti_fn.1)) + KEEP (*(.rti_fn.1.end)) + KEEP (*(.rti_fn.2)) + KEEP (*(.rti_fn.2.end)) + KEEP (*(.rti_fn.3)) + KEEP (*(.rti_fn.3.end)) + KEEP (*(.rti_fn.4)) + KEEP (*(.rti_fn.4.end)) + KEEP (*(.rti_fn.5)) + KEEP (*(.rti_fn.5.end)) + KEEP (*(.rti_fn.6)) + KEEP (*(.rti_fn.6.end)) + *(.rodata) + *(.rodata1) + *(.rodata*) + *(.rodata.*) + *(.rodata.str1.4) + *(.srodata*) + . = ALIGN(0x4) ; + __ctor_start__ = .; + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __ctor_end__ = .; + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __dtor_end__ = .; + . = ALIGN(0x4) ; + __erodata = .; + __rodata_end__ = .; + } > REGION_RODATA + + + + .data : { + . = ALIGN(0x4) ; + __sdata = . ; + __data_start__ = . ; + data_start = . ; + *(.got.plt) + *(.got) + *(.gnu.linkonce.r*) + *(.data) + *(.data*) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + *(.data1) + *(.gcc_except_table) + *(.gcc_except_table*) + __start_init_call = .; + *(.initcall.init) + __stop_init_call = .; + __start_cmd = .; + *(.bootloaddata.cmd) + . = ALIGN(4) ; + __stop_cmd = .; + __global_pointer$ = .; + *(.sdata) + *(.sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + *(__libc_atexit) + *(__libc_subinit) + *(__libc_subfreeres) + *(.note.ABI-tag) + __edata = .; + __data_end__ = .; + . = ALIGN(0x4) ; + } > REGION_DATA AT > REGION_RODATA + + + + .eh_frame : ONLY_IF_RW { + KEEP (*(.eh_frame)) + } > REGION_DATA AT > REGION_RODATA + + + + .gcc_except_table : ONLY_IF_RW { + *(.gcc_except_table .gcc_except_table.*) + __edata = .; + __data_end__ = .; + } > REGION_DATA AT > REGION_RODATA + + + + .bss : { + . = ALIGN(0x4) ; + __sbss = ALIGN(0x4) ; + __bss_start__ = . ; + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.scommon) + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(0x4) ; + __ebss = . ; + __bss_end__ = .; + __end = . ; + end = . ; + } > REGION_BSS AT > REGION_BSS + + + + ._user_heap : { + . = ALIGN(0x4) ; + __heap_start = .; + . += __min_heap_size; + . = ALIGN(0x4) ; + } > REGION_BSS AT > REGION_BSS + + ._rtt_v5_use_stack1 : { + . = ALIGN(0x4) ; + . += __rt_rvstack_bss_size; + __rt_rvstack = .; + . = ALIGN(0x4) ; + } > REGION_BSS AT > REGION_BSS + + + +} diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_adc.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_adc.h new file mode 100644 index 0000000000..6e9c9b4758 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_adc.h @@ -0,0 +1,577 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum { + ALD_ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ + ALD_ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ + ALD_ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ + ALD_ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ + ALD_ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ + ALD_ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ + ALD_ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ + ALD_ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */ +} ald_adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum { + ALD_ADC_ERROR_NONE = 0x0U, /**< No error */ + ALD_ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ + ALD_ADC_ERROR_OVR = 0x2U, /**< Overrun error */ + ALD_ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ +} ald_adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum { + ALD_ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + ALD_ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ +} ald_adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum { + ALD_ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + ALD_ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ +} ald_adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum { + ALD_ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + ALD_ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + ALD_ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + ALD_ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + ALD_ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + ALD_ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + ALD_ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + ALD_ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + ALD_ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + ALD_ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + ALD_ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + ALD_ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + ALD_ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + ALD_ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + ALD_ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + ALD_ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + ALD_ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + ALD_ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + ALD_ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ + ALD_ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */ +} ald_adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum { + ALD_ADC_SAMPLETIME_4 = 0x0U, /**< ADC sampling times 4 clk */ + ALD_ADC_SAMPLETIME_6 = 0x1U, /**< ADC sampling times 6 clk */ + ALD_ADC_SAMPLETIME_10 = 0x2U, /**< ADC sampling times 10 clk */ + ALD_ADC_SAMPLETIME_18 = 0x3U, /**< ADC sampling times 18 clk */ +} ald_adc_samp_t; + +/** + *@brief ADC index channel in normal group + */ +typedef enum { + ALD_ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + ALD_ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + ALD_ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + ALD_ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + ALD_ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + ALD_ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + ALD_ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + ALD_ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + ALD_ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + ALD_ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + ALD_ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + ALD_ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + ALD_ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + ALD_ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + ALD_ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + ALD_ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} ald_adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group + */ +typedef enum { + ALD_ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + ALD_ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + ALD_ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + ALD_ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} ald_adc_ich_idx_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum { + ALD_ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + ALD_ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + ALD_ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel Injec watch dog */ + ALD_ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + ALD_ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + ALD_ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + ALD_ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} ald_adc_ana_wdg_t; + +/** + * @brief ADC Event type + */ +typedef enum { + ALD_ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} ald_adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum { + ALD_ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ALD_ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ALD_ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ALD_ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} ald_adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum { + ALD_ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ALD_ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ALD_ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ALD_ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ALD_ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ALD_ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ALD_ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ALD_ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) +#define ALD_ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) +#define ALD_ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) +#define ALD_ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +#define ALD_ADC_SPEED_HIGH_DISABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ALD_ADC_SPEED_HIGH_ENABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ALD_ADC_TEMP_SENSE_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_TSEN_MSK)) +#define ALD_ADC_TEMP_SENSE_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_TSEN_MSK)) +#define ALD_ADC_PREDIV_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_PREDIV_MSK)) +#define ALD_ADC_PREDIV_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_PREDIV_MSK)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ALD_ADC_ICH_IDX_4) +#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ALD_ADC_NCH_IDX_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ALD_ADC_SAMPLETIME_4) || \ + ((x) == ALD_ADC_SAMPLETIME_6) || \ + ((x) == ALD_ADC_SAMPLETIME_10) || \ + ((x) == ALD_ADC_SAMPLETIME_18)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ALD_ADC_CHANNEL_19) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ALD_ADC_DATAALIGN_RIGHT) || \ + ((x) == ALD_ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ALD_ADC_ANAWTD_NONE) || \ + ((x) == ALD_ADC_ANAWTD_SING_NM) || \ + ((x) == ALD_ADC_ANAWTD_SING_IST) || \ + ((x) == ALD_ADC_ANAWTD_SING_NMIST) || \ + ((x) == ALD_ADC_ANAWTD_ALL_NM) || \ + ((x) == ALD_ADC_ANAWTD_ALL_IST) || \ + ((x) == ALD_ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ALD_ADC_IT_NCH) || \ + ((x) == ALD_ADC_IT_AWD) || \ + ((x) == ALD_ADC_IT_ICH) || \ + ((x) == ALD_ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ALD_ADC_FLAG_AWD) || \ + ((x) == ALD_ADC_FLAG_NCH) || \ + ((x) == ALD_ADC_FLAG_ICH) || \ + ((x) == ALD_ADC_FLAG_OVR) || \ + ((x) == ALD_ADC_FLAG_NCHS) || \ + ((x) == ALD_ADC_FLAG_ICHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ALD_ADC_CKDIV_2) || \ + ((x) == ALD_ADC_CKDIV_4) || \ + ((x) == ALD_ADC_CKDIV_8) || \ + ((x) == ALD_ADC_CKDIV_16) || \ + ((x) == ALD_ADC_CKDIV_32) || \ + ((x) == ALD_ADC_CKDIV_64) || \ + ((x) == ALD_ADC_CKDIV_128) || \ + ((x) == ALD_ADC_CKDIV_256)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ALD_ADC_NEG_REF_VSS ) || \ + ((x) == ALD_ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ALD_ADC_POS_REF_VDD) || \ + ((x) == ALD_ADC_POS_REF_VREEFP)) +#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ALD_ADC_NCH_NR_16) +#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ALD_ADC_ICH_NR_4) +#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ALD_ADC_DISC_NR_8) +#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ALD_ADC_CONV_BIT_6) || \ + ((x) == ALD_ADC_CONV_BIT_8) || \ + ((x) == ALD_ADC_CONV_BIT_10) || \ + ((x) == ALD_ADC_CONV_BIT_12)) +#define IS_ADC_TYPE(x) (((x) == ADC)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ALD_ADC_NCHESEL_MODE_ALL) || \ + ((x) == ALD_ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ALD_ADC_AWD_EVENT) +#define IS_ADC_NCH_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_adc_init(ald_adc_handle_t *hperh); +ald_status_t ald_adc_reset(ald_adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_adc_normal_start(ald_adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop(ald_adc_handle_t *hperh); +ald_status_t ald_adc_normal_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_poll_for_event(ald_adc_handle_t *hperh, ald_adc_event_type_t event_type, uint32_t timeout); +ald_status_t ald_adc_normal_start_by_it(ald_adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop_by_it(ald_adc_handle_t *hperh); + +ald_status_t ald_adc_start_by_dma(ald_adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_adc_stop_by_dma(ald_adc_handle_t *hperh, uint8_t channel); +ald_status_t ald_adc_timer_trigger_adc_by_dma(ald_adc_timer_config_t *config); +ald_status_t ald_adc_timer_trigger_insert(ald_adc_timer_config_t *config); + +uint32_t ald_adc_normal_get_value(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_start(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_insert_start_by_it(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop_by_it(ald_adc_handle_t *hperh); +uint32_t ald_adc_insert_get_value(ald_adc_handle_t *hperh, ald_adc_ich_idx_t ih_rank); +void ald_adc_irq_handler(ald_adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_adc_normal_channel_config(ald_adc_handle_t *hperh, ald_adc_nch_conf_t *config); +ald_status_t ald_adc_insert_channel_config(ald_adc_handle_t *hperh, ald_adc_ich_conf_t *config); +ald_status_t ald_adc_analog_wdg_config(ald_adc_handle_t *hperh, ald_adc_analog_wdg_conf_t *config); +void ald_adc_interrupt_config(ald_adc_handle_t *hperh, ald_adc_it_t it, type_func_t state); +it_status_t ald_adc_get_it_status(ald_adc_handle_t *hperh, ald_adc_it_t it); +flag_status_t ald_adc_get_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag); +void ald_adc_clear_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t ald_adc_get_state(ald_adc_handle_t *hperh); +uint32_t ald_adc_get_error(ald_adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus + extern "C" } +#endif /* __cplusplus */ + +#endif /* __ALD_ADC_H */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_cmu.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_cmu.h new file mode 100644 index 0000000000..3eebfc3146 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_cmu.h @@ -0,0 +1,428 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.h + * @brief Header file of CMU module driver. + * + * @version V1.0 + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CMU_H__ +#define __ALD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ald_syscfg.h" + + +/** @addtogroup ALD + * @{ + */ + +/** @addtogroup CMU + * @{ + */ + +/** @defgroup CMU_Public_Macros CMU Public Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CMU_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum +{ + ALD_CMU_CLOCK_HRC48M = 0x1U, /**< HRC48M */ + ALD_CMU_CLOCK_LRC = 0x2U, /**< LRC */ + ALD_CMU_CLOCK_HOSC = 0x3U, /**< HOSC */ + ALD_CMU_CLOCK_PLL = 0x4U, /**< PLL */ + ALD_CMU_CLOCK_HRC4M = 0x5U, /**< HRC4M */ +} ald_cmu_clock_t; + +/** + * @brief PLL output clock + */ +typedef enum +{ + ALD_CMU_PLL_OUTPUT_72M = 0x0U, /**< 72MHz */ + ALD_CMU_PLL_OUTPUT_64M = 0x2U, /**< 64MHz */ + ALD_CMU_PLL_OUTPUT_48M = 0x3U, /**< 48MHz */ +} ald_cmu_pll_output_t; + +/** + * @brief PLL referance clock + */ +typedef enum +{ + ALD_CMU_PLL_INPUT_HRC4M = 0x0U, /**< HRC4M */ + ALD_CMU_PLL_INPUT_HOSC4M = 0x1U, /**< HOSC4M */ + ALD_CMU_PLL_INPUT_HOSC8M = 0x2U, /**< HOSC8M */ + ALD_CMU_PLL_INPUT_HOSC16M = 0x3U, /**< HOSC16M */ +} ald_cmu_pll_input_t; + +/** + * @brief HOSC range + */ +typedef enum { + ALD_CMU_HOSC_1M_2M = 0x0U, /**< 1~2MHz */ + ALD_CMU_HOSC_2M_4M = 0x1U, /**< 2~4MHz */ + ALD_CMU_HOSC_4M_8M = 0x2U, /**< 4~8MHz */ + ALD_CMU_HOSC_8M_16M = 0x3U, /**< 8~16MHz */ + ALD_CMU_HOSC_16M_24M = 0x4U, /**< 16~24MHz */ +} ald_cmu_hosc_range_t; + +/** + * @brief Frequency division select bit + */ +typedef enum +{ + ALD_CMU_DIV_1 = 0x0U, /**< Division by 1 */ + ALD_CMU_DIV_2 = 0x1U, /**< Division by 2 */ + ALD_CMU_DIV_4 = 0x2U, /**< Division by 4 */ + ALD_CMU_DIV_8 = 0x3U, /**< Division by 8 */ + ALD_CMU_DIV_16 = 0x4U, /**< Division by 16 */ + ALD_CMU_DIV_32 = 0x5U, /**< Division by 32 */ + ALD_CMU_DIV_64 = 0x6U, /**< Division by 64 */ + ALD_CMU_DIV_128 = 0x7U, /**< Division by 128 */ + ALD_CMU_DIV_256 = 0x8U, /**< Division by 256 */ + ALD_CMU_DIV_512 = 0x9U, /**< Division by 512 */ + ALD_CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + ALD_CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + ALD_CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ +} ald_cmu_div_t; + +/** + * @brief BUZZ frequency division + */ +typedef enum { + ALD_CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ + ALD_CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ + ALD_CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ + ALD_CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ + ALD_CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ + ALD_CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ + ALD_CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ + ALD_CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ +} ald_cmu_buzz_div_t; + +/** + * @brief Safe clock source type + */ +typedef enum { + ALD_CMU_SAFE_CLK_PLL = 0x0U, /**< PLL */ +} ald_cmu_clock_safe_type_t; + +/** + * @brief Bus type + */ +typedef enum +{ + ALD_CMU_SYS = 0x1U, /**< SYS bus */ + ALD_CMU_PCLK = 0x2U, /**< APB bus */ +} ald_cmu_bus_t; + +/** + * @brief Output frequency division + */ +typedef enum { + ALD_CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ + ALD_CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ + ALD_CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ + ALD_CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ + ALD_CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ + ALD_CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ + ALD_CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ + ALD_CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ +} ald_cmu_output_high_div_t; + +/** + * @brief Output high clock select + */ +typedef enum { + ALD_CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ + ALD_CMU_OUTPUT_HIGH_SEL_HOSM = 0x1U, /**< Select HOSM */ + ALD_CMU_OUTPUT_HIGH_SEL_HRC4M = 0x2U, /**< Select HRC4M */ + ALD_CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ + ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x4U, /**< Select SYSCLK */ + ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K = 0x5U, /**< Select HOSC32K */ + ALD_CMU_OUTPUT_HIGH_SEL_HRC48M = 0x6U, /**< Select HRC48M */ + ALD_CMU_OUTPUT_HIGH_SEL_PLL = 0x7U, /**< Select PLL */ +} ald_cmu_output_high_sel_t; + +/** + * @brief Output low clock select + */ +typedef enum { + ALD_CMU_OUTPUT_LOW_SEL_LRC = 0x0U, /**< Select LRC */ + ALD_CMU_OUTPUT_LOW_SEL_BUZZ = 0x1U, /**< Select BUZZ */ +} ald_cmu_output_low_sel_t; + +/** + * @brief Peripheral clock enable/disable + */ +typedef enum { + ALD_CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + ALD_CMU_PERH_CRC = (1U << 1), /**< CRC */ + ALD_CMU_PERH_DMA = (1U << 2), /**< DMA */ + ALD_CMU_PERH_PIS = (1U << 5), /**< PIS */ + ALD_CMU_PERH_USB = (1U << 6), /**< USB */ + ALD_CMU_PERH_CSU = (1U << 7), /**< CSU */ + ALD_CMU_PERH_AD16C4T0 = (1U << 0) | (1U << 27), /**< AD16C4T0 */ + ALD_CMU_PERH_BS16T0 = (1U << 1) | (1U << 27), /**< BS16T0 */ + ALD_CMU_PERH_GP16C4T0 = (1U << 2) | (1U << 27), /**< CP16C4T0 */ + ALD_CMU_PERH_GP16C4T1 = (1U << 3) | (1U << 27), /**< GP16C4T1 */ + ALD_CMU_PERH_GP16C4T2 = (1U << 4) | (1U << 27), /**< GP16C4T2 */ + ALD_CMU_PERH_EUART0 = (1U << 8) | (1U << 27), /**< EUART0 */ + ALD_CMU_PERH_EUART1 = (1U << 9) | (1U << 27), /**< EUART1 */ + ALD_CMU_PERH_CUART0 = (1U << 12) | (1U << 27), /**< CUART0 */ + ALD_CMU_PERH_CUART1 = (1U << 13) | (1U << 27), /**< CUART1 */ + ALD_CMU_PERH_CUART2 = (1U << 14) | (1U << 27), /**< CUART2 */ + ALD_CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + ALD_CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + ALD_CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + ALD_CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + ALD_CMU_PERH_WWDT = (1U << 22) | (1U << 27), /**< WWDT */ + ALD_CMU_PERH_IWDT = (1U << 23) | (1U << 27), /**< IWDT */ + ALD_CMU_PERH_DBGC = (1U << 24) | (1U << 27), /**< DBGC */ + ALD_CMU_PERH_ADC = (1U << 25) | (1U << 27), /**< ADC */ + ALD_CMU_PERH_ALL = (0x7FFFFFFFU), /**< ALL */ +} ald_cmu_perh_t; + +/** + * @brief CMU interrupt type + */ +typedef enum { + ALD_CMU_HOSC_STOP = 0x0U, /**< HOSC STOP INTERRUPT */ + ALD_CMU_PLL_UNLOCK = 0x1U, /**< PLL UNLOCK INTERRUPT */ + ALD_CMU_HOSC_START = 0x2U, /**< HOSC START INTERRUPT */ +} ald_cmu_security_t; + +/** + * @brief CMU clock state type + */ +typedef enum { + ALD_CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + ALD_CMU_CLOCK_STATE_PLLACT = (1U << 1), /**< PLL active */ + ALD_CMU_CLOCK_STATE_HRC4MACT = (1U << 2), /**< HRC4M active */ + ALD_CMU_CLOCK_STATE_HRC48MACT = (1U << 3), /**< HRC48M active */ + ALD_CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + ALD_CMU_CLOCK_STATE_HRC4MRDY = (1U << 17), /**< HRC4M ready */ + ALD_CMU_CLOCK_STATE_HRC48MRDY = (1U << 18), /**< HRC48M ready */ + ALD_CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + ALD_CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +} ald_cmu_clock_state_t; + +/** + * @} + */ + +/** + * @defgroup CMU_Private_Macros CMU Private Macros + * @{ + */ +#define IS_CMU_CLOCK(x) (((x) == ALD_CMU_CLOCK_HRC48M) || \ + ((x) == ALD_CMU_CLOCK_LRC) || \ + ((x) == ALD_CMU_CLOCK_HOSC) || \ + ((x) == ALD_CMU_CLOCK_PLL) || \ + ((x) == ALD_CMU_CLOCK_HRC4M)) +#define IS_CMU_PLL_INPUT(x) (((x) == ALD_CMU_PLL_INPUT_HRC4M) || \ + ((x) == ALD_CMU_PLL_INPUT_HOSC4M) || \ + ((x) == ALD_CMU_PLL_INPUT_HOSC8M) || \ + ((x) == ALD_CMU_PLL_INPUT_HOSC16M)) +#define IS_CMU_PLL_OUTPUT(x) (((x) == ALD_CMU_PLL_OUTPUT_48M) || \ + ((x) == ALD_CMU_PLL_OUTPUT_64M) || \ + ((x) == ALD_CMU_PLL_OUTPUT_72M)) +#define IS_CMU_HOSC_RANGE(x) (((x) == ALD_CMU_HOSC_1M_2M) || \ + ((x) == ALD_CMU_HOSC_2M_4M) || \ + ((x) == ALD_CMU_HOSC_4M_8M) || \ + ((x) == ALD_CMU_HOSC_8M_16M) || \ + ((x) == ALD_CMU_HOSC_16M_24M)) +#define IS_CMU_DIV(x) (((x) == ALD_CMU_DIV_1) || \ + ((x) == ALD_CMU_DIV_2) || \ + ((x) == ALD_CMU_DIV_4) || \ + ((x) == ALD_CMU_DIV_8) || \ + ((x) == ALD_CMU_DIV_16) || \ + ((x) == ALD_CMU_DIV_32) || \ + ((x) == ALD_CMU_DIV_64) || \ + ((x) == ALD_CMU_DIV_128) || \ + ((x) == ALD_CMU_DIV_256) || \ + ((x) == ALD_CMU_DIV_512) || \ + ((x) == ALD_CMU_DIV_1024) || \ + ((x) == ALD_CMU_DIV_2048) || \ + ((x) == ALD_CMU_DIV_4096)) +#define IS_CMU_BUS(x) (((x) == ALD_CMU_PCLK) || \ + ((x) == ALD_CMU_SYS)) +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC4M) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC48M) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_PLL)) +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == ALD_CMU_OUTPUT_DIV_1) || \ + ((x) == ALD_CMU_OUTPUT_DIV_2) || \ + ((x) == ALD_CMU_OUTPUT_DIV_4) || \ + ((x) == ALD_CMU_OUTPUT_DIV_8) || \ + ((x) == ALD_CMU_OUTPUT_DIV_16) || \ + ((x) == ALD_CMU_OUTPUT_DIV_32) || \ + ((x) == ALD_CMU_OUTPUT_DIV_64) || \ + ((x) == ALD_CMU_OUTPUT_DIV_128)) +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == ALD_CMU_OUTPUT_LOW_SEL_LRC) || \ + ((x) == ALD_CMU_OUTPUT_LOW_SEL_BUZZ)) +#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == ALD_CMU_SAFE_CLK_PLL)) +#define IS_CMU_BUZZ_DIV(x) (((x) == ALD_CMU_BUZZ_DIV_2) || \ + ((x) == ALD_CMU_BUZZ_DIV_4) || \ + ((x) == ALD_CMU_BUZZ_DIV_8) || \ + ((x) == ALD_CMU_BUZZ_DIV_16) || \ + ((x) == ALD_CMU_BUZZ_DIV_32) || \ + ((x) == ALD_CMU_BUZZ_DIV_64) || \ + ((x) == ALD_CMU_BUZZ_DIV_128) || \ + ((x) == ALD_CMU_BUZZ_DIV_256)) +#define IS_CMU_PERH(x) (((x) == ALD_CMU_PERH_GPIO) || \ + ((x) == ALD_CMU_PERH_CRC) || \ + ((x) == ALD_CMU_PERH_DMA) || \ + ((x) == ALD_CMU_PERH_PIS) || \ + ((x) == ALD_CMU_PERH_USB) || \ + ((x) == ALD_CMU_PERH_CSU) || \ + ((x) == ALD_CMU_PERH_AD16C4T0) || \ + ((x) == ALD_CMU_PERH_BS16T0) || \ + ((x) == ALD_CMU_PERH_GP16C4T0) || \ + ((x) == ALD_CMU_PERH_GP16C4T1) || \ + ((x) == ALD_CMU_PERH_GP16C4T2) || \ + ((x) == ALD_CMU_PERH_EUART0) || \ + ((x) == ALD_CMU_PERH_EUART1) || \ + ((x) == ALD_CMU_PERH_CUART0) || \ + ((x) == ALD_CMU_PERH_CUART1) || \ + ((x) == ALD_CMU_PERH_CUART2) || \ + ((x) == ALD_CMU_PERH_SPI0) || \ + ((x) == ALD_CMU_PERH_SPI1) || \ + ((x) == ALD_CMU_PERH_I2C0) || \ + ((x) == ALD_CMU_PERH_I2C1) || \ + ((x) == ALD_CMU_PERH_WWDT) || \ + ((x) == ALD_CMU_PERH_IWDT) || \ + ((x) == ALD_CMU_PERH_DBGC) || \ + ((x) == ALD_CMU_PERH_ADC) || \ + ((x) == ALD_CMU_PERH_ALL)) +#define IS_CMU_CLOCK_STATE(x) (((x) == ALD_CMU_CLOCK_STATE_HOSCACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_PLLACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC4MACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC48MACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC4MRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC48MRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_PLLRDY)) +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions + * @{ + */ +/** @addtogroup CMU_Public_Functions_Group1 + * @{ + */ +/* System clock configure */ +ald_status_t ald_cmu_clock_config_default(void); +ald_status_t ald_cmu_clock_config(ald_cmu_clock_t clk, uint32_t clock); +void ald_cmu_pll_config(ald_cmu_pll_input_t input, ald_cmu_pll_output_t output); +uint32_t ald_cmu_get_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group2 + * @{ + */ +/* BUS division control */ +void ald_cmu_div_config(ald_cmu_bus_t bus, ald_cmu_div_t div); +uint32_t ald_cmu_get_sys_clock(void); +uint32_t ald_cmu_get_pclk_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group3 + * @{ + */ +/* Clock safe configure */ +void ald_cmu_hosc_safe_config(ald_cmu_hosc_range_t clock, type_func_t status); +void ald_cmu_pll_safe_config(type_func_t status); +uint32_t ald_cmu_pulmcr_current_clock_source_get(void); +flag_status_t ald_cmu_get_clock_state(ald_cmu_clock_state_t sr); +void ald_cmu_irq_handler(void); +void ald_cmu_irq_cbk(ald_cmu_security_t se); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group4 + * @{ + */ +/* Clock output configure */ +void ald_cmu_output_high_clock_config(ald_cmu_output_high_sel_t sel, + ald_cmu_output_high_div_t div, type_func_t status); +void ald_cmu_output_low_clock_config(ald_cmu_output_low_sel_t sel, type_func_t status); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group5 + * @{ + */ +/* Peripheral Clock configure */ +void ald_cmu_buzz_config(ald_cmu_buzz_div_t div, uint16_t dat, type_func_t status); +void ald_cmu_perh_clock_config(ald_cmu_perh_t perh, type_func_t status); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_CMU_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_conf.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_conf.h new file mode 100644 index 0000000000..4d54b61e85 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_conf.h @@ -0,0 +1,136 @@ +/********************************************************************************** + * + * @file ald_conf.h + * @brief Enable/Disable the peripheral module. + * + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ +#ifndef __ALD_CONF_H__ +#define __ALD_CONF_H__ + +/* Exported Macros ----------------------------------------------------------- */ +/* Includes ------------------------------------------------------------------ */ +#define ALD_I2C +#define ALD_GPIO +#define ALD_TIMER +#define ALD_ADC +#define ALD_DMA +#define ALD_SPI +/* #define ALD_IWDT */ +/* #define ALD_WWDT */ +/* #define ALD_CRC */ +#define ALD_UART +#define ALD_CMU +/* #define ALD_DBGC */ +/* #define ALD_PIS */ +#define ALD_PMU +/* #define ALD_RMU */ +#define ALD_SYSCFG +/* #define ALD_TYPE */ +#define ALD_UTILS + +#ifdef ALD_I2C + #include "ald_i2c.h" +#endif /* ALD_I2C */ + +#ifdef ALD_GPIO + #include "ald_gpio.h" +#endif /* MD_GPIO */ + +#ifdef ALD_TIMER + #include "ald_timer.h" +#endif /* ALD_TIMER */ + +#ifdef ALD_ADC + #include "ald_adc.h" +#endif /* ALD_ADC */ + +#ifdef ALD_DMA + #include "ald_dma.h" +#endif /* ALD_DMA */ + +#ifdef ALD_SPI + #include "ald_spi.h" +#endif /* ALD_SPI */ + +#ifdef ALD_IWDT + #include "ald_iwdt.h" +#endif /* ALD_IWDT */ + +#ifdef ALD_WWDT + #include "ald_wwdt.h" +#endif /* ALD_WWDT */ + +#ifdef ALD_CRC + #include "ald_crc.h" +#endif /* ALD_CRC */ + +#ifdef ALD_UART + #include "ald_uart.h" +#endif /* ALD_UART */ + +#ifdef ALD_CMU + #include "ald_cmu.h" +#endif /* ALD_CMU */ + +#ifdef ALD_DBGC + #include "ald_dbgc.h" +#endif /* ALD_DBGC */ + +#ifdef ALD_PIS + #include "ald_pis.h" +#endif /* ALD_PIS */ + +#ifdef ALD_PMU + #include "ald_pmu.h" +#endif /* ALD_PMU */ + +#ifdef ALD_RMU + #include "ald_rmu.h" +#endif /* ALD_RMU */ + +#ifdef ALD_SYSCFG + #include "ald_syscfg.h" +#endif /* ALD_SYSCFG */ + +#ifdef ALD_UTILS + #include "ald_utils.h" +#endif /* ALD_UTILS */ + +#ifdef ALD_TYPE + #include "type.h" +#endif /* ALD_TYPE */ + +#define TICK_INT_PRIORITY 3 + +/* Exported Types ------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ + +#endif /*__MD_CONF_H__*/ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_crc.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_crc.h new file mode 100644 index 0000000000..c036029fb9 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_crc.h @@ -0,0 +1,212 @@ +/** + ********************************************************************************* + * + * @file ald_crc.h + * @brief Header file of CRC module driver. + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CRC_H__ +#define __ALD_CRC_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Public_Types CRC Public Types + * @{ + */ + +/** + * @brief CRC mode + */ +typedef enum { + ALD_CRC_MODE_CCITT = 0U, /**< CCITT */ + ALD_CRC_MODE_8 = 1U, /**< CRC8 */ + ALD_CRC_MODE_16 = 2U, /**< CRC16 */ + ALD_CRC_MODE_32 = 3U, /**< CRC32 */ +} ald_crc_mode_t; + +/** + * @brief CRC input length + */ +typedef enum { + ALD_CRC_LEN_AUTO = 0U, /**< Auto */ + ALD_CRC_DATASIZE_8 = 1U, /**< Byte */ + ALD_CRC_DATASIZE_16 = 2U, /**< Half word */ + ALD_CRC_DATASIZE_32 = 3U, /**< Word */ +} ald_crc_datasize_t; + +/** + * @brief CRC whether write error or no + */ +typedef enum { + ALD_CRC_WERR_NO = 0U, /**< No error */ + ALD_CRC_WERR_ERR = 1U, /**< Error */ +} ald_crc_werr_t; + +/** + * @brief CRC state structures definition + */ +typedef enum { + ALD_CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + ALD_CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + ALD_CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + ALD_CRC_STATE_ERROR = 0x4U, /**< Error */ +} ald_crc_state_t; + +/** + * @brief CRC init structure definition + */ +typedef struct { + ald_crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} ald_crc_init_t; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct ald_crc_handle_s { + CRC_TypeDef *perh; /**< Register base address */ + ald_crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ + + ald_dma_handle_t hdma; /**< CRC DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_crc_state_t state; /**< CRC operation state */ + + void (*cal_cplt_cbk)(struct ald_crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct ald_crc_handle_s *arg); /**< Calculate error callback */ +} ald_crc_handle_t; +/** + * @} + */ + +/** @defgroup CRC_Public_Macros CRC Public Macros + * @{ + */ +#define ALD_CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define ALD_CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define ALD_CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define ALD_CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define ALD_CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define ALD_CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == ALD_CRC_MODE_CCITT) || \ + ((x) == ALD_CRC_MODE_8) || \ + ((x) == ALD_CRC_MODE_16) || \ + ((x) == ALD_CRC_MODE_32)) +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions + * @{ + */ + +/** @addtogroup CRC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_crc_init(ald_crc_handle_t *hperh); +void ald_crc_reset(ald_crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group2 + * @{ + */ +uint32_t ald_crc_calculate(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate_halfword(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t size); +uint32_t ald_crc_calculate_word(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t size); +/** + * @} + */ + + +/** @addtogroup CRC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_crc_calculate_by_dma(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_halfword_by_dma(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_word_by_dma(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_dma_pause(ald_crc_handle_t *hperh); +ald_status_t ald_crc_dma_resume(ald_crc_handle_t *hperh); +ald_status_t ald_crc_dma_stop(ald_crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group4 + * @{ + */ +ald_crc_state_t ald_crc_get_state(ald_crc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_CRC_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_dma.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_dma.h new file mode 100644 index 0000000000..b6d21d9a39 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_dma.h @@ -0,0 +1,342 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 16 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Feb. 2023 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define ALD_DMA_CH_COUNT 7U +/** + * @} + */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + */ +typedef enum { + ALD_DMA_MSEL_NONE = 0x0U, /**< NONE */ + ALD_DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + ALD_DMA_MSEL_ADC = 0x2U, /**< ADC */ + ALD_DMA_MSEL_CRC = 0x3U, /**< CRC */ + ALD_DMA_MSEL_EUART0 = 0x4U, /**< EUART0 */ + ALD_DMA_MSEL_EUART1 = 0x5U, /**< EUART1 */ + ALD_DMA_MSEL_CUART0 = 0x6U, /**< CUART0 */ + ALD_DMA_MSEL_CUART1 = 0x7U, /**< CUART1 */ + ALD_DMA_MSEL_CUART2 = 0x8U, /**< CUART2 */ + ALD_DMA_MSEL_SPI0 = 0x9U, /**< SPI0 */ + ALD_DMA_MSEL_SPI1 = 0xAU, /**< SPI1 */ + ALD_DMA_MSEL_I2C0 = 0xBU, /**< I2C0 */ + ALD_DMA_MSEL_I2C1 = 0xCU, /**< I2C1 */ + ALD_DMA_MSEL_AD16C4T = 0xDU, /**< AD16C4T */ + ALD_DMA_MSEL_GP16C4T0= 0xEU, /**< GP16C4T0 */ + ALD_DMA_MSEL_GP16C4T1= 0xFU, /**< GP16C4T1 */ + ALD_DMA_MSEL_GP16C4T2= 0x10U, /**< GP16C4T2 */ + ALD_DMA_MSEL_PIS = 0x11U, /**< PIS */ + ALD_DMA_MSEL_BS16T = 0x12U, /**< BS16T */ +} ald_dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum { + ALD_DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + ALD_DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + ALD_DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + ALD_DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + ALD_DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + ALD_DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + ALD_DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + ALD_DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + ALD_DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + ALD_DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + ALD_DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + ALD_DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + ALD_DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + ALD_DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + ALD_DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + ALD_DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + ALD_DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + ALD_DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + ALD_DMA_MSIGSEL_CRC = 0x0U, /**< CRC */ + ALD_DMA_MSIGSEL_UART_RNR = 0x0U, /**< UART reveive */ + ALD_DMA_MSIGSEL_UART_TXEMPTY = 0x1U, /**< UART transmit */ + ALD_DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + ALD_DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + ALD_DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + ALD_DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + ALD_DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + ALD_DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + ALD_DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + ALD_DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + ALD_DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + ALD_DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + ALD_DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + ALD_DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + ALD_DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + ALD_DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + ALD_DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + ALD_DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + ALD_DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + ALD_DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + ALD_DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ + ALD_DMA_MSIGSEL_BSTIM = 0x0U, /**< BSTIM */ +} ald_dma_msigsel_t; + +/** + * @brief Priority of DMA channel + */ +typedef enum +{ + ALD_DMA_LOW_PRIORITY = 0, + ALD_DMA_MEDIUM_PRIORITY = 1, + ALD_DMA_HIGH_PRIORUTY = 2, + ALD_DMA_HIGHEST_PRIORITY = 3 +} ald_dma_priority_t; + +/** + * @brief data increment + */ +typedef enum +{ + ALD_DMA_DATA_INC_DISABLE = 0x0U, + ALD_DMA_DATA_INC_ENABLE = 0x1U, +} ald_dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum { + ALD_DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + ALD_DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + ALD_DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ +} ald_dma_data_size_t; + +/** + * @brief Interrupt flag trigger mode + */ +typedef enum +{ + ALD_DMA_IT_FLAG_TC = 0x0U, /**< DMA transfer complete interrupt */ + ALD_DMA_IT_FLAG_HT = 0x1U, /**< DMA transfer half complete interrupt */ +} ald_dma_it_flag_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum { + ALD_DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + ALD_DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + ALD_DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + ALD_DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + ALD_DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + ALD_DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + ALD_DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + ALD_DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + ALD_DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + ALD_DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + ALD_DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ +} ald_dma_arbiter_config_t; + +/** + * @brief Callback function pointer and param + */ +typedef struct { + void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*cplt_ht_cbk)(void* arg); /**< DMA transfers half complete callback */ + void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */ + void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */ +} ald_dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct { + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + ald_dma_data_size_t src_data_width; /**< Source data width */ + ald_dma_data_size_t dst_data_width; /**< Dest data width */ + ald_dma_data_inc_t src_inc; /**< Source increment type */ + ald_dma_data_inc_t dst_inc; /**< Destination increment type */ + ald_dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates */ + ald_dma_priority_t priority; /**< High priority or default priority */ + TypeFunc mem_to_mem; /**< Enable/disable memory to memory mode */ + TypeFunc circle_mode; /**< Enable/disable circular mode */ + ald_dma_msel_t msel; /**< Input source to DMA channel */ + ald_dma_msigsel_t msigsel; /**< Input signal to DMA channel */ + uint8_t channel; /**< Channel index */ +} ald_dma_config_t; + +/** @defgroup ALD_DMA_Public_Constants DMA Public Constants + * @{ + */ +/** + * brief ALD_DMA_CHANNEL DMA channel + */ +#define ALD_DMA_CH_0 0x0U /**< Channel 0 */ +#define ALD_DMA_CH_1 0x1U /**< Channel 1 */ +#define ALD_DMA_CH_2 0x2U /**< Channel 2 */ +#define ALD_DMA_CH_3 0x3U /**< Channel 3 */ +#define ALD_DMA_CH_4 0x4U /**< Channel 4 */ +#define ALD_DMA_CH_5 0x5U /**< Channel 5 */ +#define ALD_DMA_CH_6 0x6U /**< Channel 6 */ +/** + * @} + */ + +/** + * @brief DMA handle structure definition + */ +typedef struct { + DMA_TypeDef *perh; /**< DMA registers base address */ + ald_dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*cplt_ht_cbk)(void *arg); /**< DMA transfers half complete callback */ + void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */ + void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */ +} ald_dma_handle_t; + +/** + * @} + */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= ALD_DMA_MSEL_BS16T) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= ALD_DMA_MSIGSEL_EXTI_15) +#define IS_DMA_DATAINC_TYPE(x) (((x) == ALD_DMA_DATA_INC_DISABLE) || \ + ((x) == ALD_DMA_DATA_INC_ENABLE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == ALD_DMA_DATA_SIZE_BYTE) || \ + ((x) == ALD_DMA_DATA_SIZE_HALFWORD) || \ + ((x) == ALD_DMA_DATA_SIZE_WORD)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == ALD_DMA_R_POWER_1) || \ + ((x) == ALD_DMA_R_POWER_2) || \ + ((x) == ALD_DMA_R_POWER_4) || \ + ((x) == ALD_DMA_R_POWER_8) || \ + ((x) == ALD_DMA_R_POWER_16) || \ + ((x) == ALD_DMA_R_POWER_32) || \ + ((x) == ALD_DMA_R_POWER_64) || \ + ((x) == ALD_DMA_R_POWER_128) || \ + ((x) == ALD_DMA_R_POWER_256) || \ + ((x) == ALD_DMA_R_POWER_512) || \ + ((x) == ALD_DMA_R_POWER_1024)) +#define IS_DMA_PRIORITY_TYPE(x) (((x) == ALD_DMA_LOW_PRIORITY) || \ + ((x) == ALD_DMA_MEDIUM_PRIORITY) || \ + ((x) == ALD_DMA_HIGH_PRIORUTY) || \ + ((x) == ALD_DMA_HIGHEST_PRIORITY)) +#define IS_DMA_IT_TYPE(x) (((x) == ALD_DMA_IT_FLAG_TC) || \ + ((x) == ALD_DMA_IT_FLAG_HT)) +#define IS_DMA(x) ((x) == DMA) +#define IS_DMA_CHANNEL(x) ((x) <= ALD_DMA_CH_6) +#define IS_DMA_DATA_SIZE(x) ((x) <= 65535) +/** + * @} + */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_dma_config_base(ald_dma_config_t *config); +extern void ald_dma_config_basic(ald_dma_handle_t *hperh); +extern void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel, + ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_irq_handler(void); +extern void ald_dma_reset(void); +extern void ald_dma_init(void); +extern void ald_dma_config_struct(ald_dma_config_t *p); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* DMA control functions */ +extern void ald_dma_channel_config(uint8_t channel, type_func_t state); +void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state); +extern it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it); +extern flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it); +extern void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /*__ALD_DMA_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_gpio.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_gpio.h new file mode 100644 index 0000000000..4d142da272 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_gpio.h @@ -0,0 +1,300 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.h + * @brief Header file of GPIO module driver + * + * @version V1.0 + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_GPIO_H__ +#define __ALD_GPIO_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" + + +/** @addtogroup ALD + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define ALD_GPIO_PIN_0 (0x1U) +#define ALD_GPIO_PIN_1 (0x2U) +#define ALD_GPIO_PIN_2 (0x4U) +#define ALD_GPIO_PIN_3 (0x8U) +#define ALD_GPIO_PIN_4 (0x10U) +#define ALD_GPIO_PIN_5 (0x20U) +#define ALD_GPIO_PIN_6 (0x40U) +#define ALD_GPIO_PIN_7 (0x80U) +#define ALD_GPIO_PIN_8 (0x100U) +#define ALD_GPIO_PIN_9 (0x200U) +#define ALD_GPIO_PIN_10 (0x400U) +#define ALD_GPIO_PIN_11 (0x800U) +#define ALD_GPIO_PIN_12 (0x1000U) +#define ALD_GPIO_PIN_13 (0x2000U) +#define ALD_GPIO_PIN_14 (0x4000U) +#define ALD_GPIO_PIN_15 (0x8000U) +#define ALD_GPIO_PIN_ALL (0xFFFF) + +/* Toggle IO */ +#define ALD_GPIOA_TOGGLE_PIN(x) (GPIOA->BIR = (x)) +#define ALD_GPIOB_TOGGLE_PIN(x) (GPIOB->BIR = (x)) +#define ALD_GPIOC_TOGGLE_PIN(x) (GPIOC->BIR = (x)) +#define ALD_GPIOD_TOGGLE_PIN(x) (GPIOD->BIR = (x)) + +/* Read IO level */ +#define ALD_GPIOA_READ_PIN(x) ((GPIOA->DIN & (x)) ? 1 : 0) +#define ALD_GPIOB_READ_PIN(x) ((GPIOB->DIN & (x)) ? 1 : 0) +#define ALD_GPIOC_READ_PIN(x) ((GPIOC->DIN & (x)) ? 1 : 0) +#define ALD_GPIOD_READ_PIN(x) ((GPIOD->DIN & (x)) ? 1 : 0) + +/* Set IO as high */ +#define ALD_GPIOA_SET_PIN(x) (GPIOA->BSRR = (x)) +#define ALD_GPIOB_SET_PIN(x) (GPIOB->BSRR = (x)) +#define ALD_GPIOC_SET_PIN(x) (GPIOC->BSRR = (x)) +#define ALD_GPIOD_SET_PIN(x) (GPIOD->BSRR = (x)) + +/* Set IO as low */ +#define ALD_GPIOA_RESET_PIN(x) (GPIOA->BSRR = ((x) << 16)) +#define ALD_GPIOB_RESET_PIN(x) (GPIOB->BSRR = ((x) << 16)) +#define ALD_GPIOC_RESET_PIN(x) (GPIOC->BSRR = ((x) << 16)) +#define ALD_GPIOD_RESET_PIN(x) (GPIOD->BSRR = ((x) << 16)) +/** + * @} + */ + +/** + * @defgroup GPIO_Public_Types GPIO Public Types + * @{ + */ + +/** + * @brief GPIO mode + */ +typedef enum { + ALD_GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + ALD_GPIO_MODE_INPUT = 0x1U, /**< Input */ + ALD_GPIO_MODE_OUTPUT = 0x2U, /**< Output */ +} ald_gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum { + ALD_GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + ALD_GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ +} ald_gpio_od_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum { + ALD_GPIO_FLOATING = 0x0U, /**< Floating */ + ALD_GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + ALD_GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + ALD_GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ +} ald_gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum { + ALD_GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */ + ALD_GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */ +} ald_gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum { + ALD_GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + ALD_GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ +} ald_gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum { + ALD_GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + ALD_GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ +} ald_gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum { + ALD_GPIO_FUNC_0 = 0U, /**< function #0 */ + ALD_GPIO_FUNC_1 = 1U, /**< function #1 */ + ALD_GPIO_FUNC_2 = 2U, /**< function #2 */ + ALD_GPIO_FUNC_3 = 3U, /**< function #3 */ + ALD_GPIO_FUNC_4 = 4U, /**< function #4 */ + ALD_GPIO_FUNC_5 = 5U, /**< function #5 */ + ALD_GPIO_FUNC_6 = 6U, /**< function #6 */ + ALD_GPIO_FUNC_7 = 7U, /**< function #7 */ +} ald_gpio_func_t; + +/** + * @brief GPIO Init Structure definition + */ +typedef struct { + ald_gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + ald_gpio_od_t od; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_od_t */ + ald_gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + ald_gpio_out_drive_t odrv; /**< Specifies the output MOS driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + ald_gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + ald_gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + ald_gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ +} ald_gpio_init_t; + +/** + * @brief EXTI trigger style + */ +typedef enum { + ALD_EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ + ALD_EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ + ALD_EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ +} ald_exti_trigger_style_t; + +/** + * @brief EXTI Init Structure definition + */ +typedef struct { + type_func_t filter; /**< Enable filter. */ + uint8_t filter_time; /**< Filter duration */ +} ald_exti_init_t; +/** + * @} + */ + +/** + * @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define ALD_PIN_MASK 0xFFFFU +#define ALD_UNLOCK_KEY 0x55AAU + +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD)) +#define IS_GPIO_MODE(x) (((x) == ALD_GPIO_MODE_CLOSE) || \ + ((x) == ALD_GPIO_MODE_INPUT) || \ + ((x) == ALD_GPIO_MODE_OUTPUT)) +#define IS_GPIO_OD(x) (((x) == ALD_GPIO_PUSH_PULL) || \ + ((x) == ALD_GPIO_OPEN_DRAIN)) +#define IS_GPIO_PUPD(x) (((x) == ALD_GPIO_FLOATING) || \ + ((x) == ALD_GPIO_PUSH_UP) || \ + ((x) == ALD_GPIO_PUSH_DOWN) || \ + ((x) == ALD_GPIO_PUSH_UP_DOWN)) +#define IS_GPIO_ODRV(x) (((x) == ALD_GPIO_OUT_DRIVE_NORMAL) || \ + ((x) == ALD_GPIO_OUT_DRIVE_STRONG)) +#define IS_GPIO_FLT(x) (((x) == ALD_GPIO_FILTER_DISABLE) || \ + ((x) == ALD_GPIO_FILTER_ENABLE)) +#define IS_GPIO_TYPE(x) (((x) == ALD_GPIO_TYPE_TTL) || \ + ((x) == ALD_GPIO_TYPE_CMOS)) +#define IS_TRIGGER_STYLE(x) (((x) == ALD_EXTI_TRIGGER_RISING_EDGE) || \ + ((x) == ALD_EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == ALD_EXTI_TRIGGER_BOTH_EDGE)) +#define IS_GPIO_FUNC(x) ((x) <= 7) +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions + * @{ + */ + +/** @addtogroup GPIO_Public_Functions_Group1 + * @{ + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_gpio_init_t *init); +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_func_default(GPIO_TypeDef *GPIOx); +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_exti_init_t *init); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group2 + * @{ + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group3 + * @{ + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, ald_exti_trigger_style_t style, type_func_t status); +type_func_t ald_gpio_exti_get_ie_status(uint16_t pin); +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); +void ald_gpio_exti_clear_flag_status(uint16_t pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_GPIO_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2c.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2c.h new file mode 100644 index 0000000000..456e1a9b6e --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2c.h @@ -0,0 +1,524 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 24 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 24 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include +#include "ald_cmu.h" +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum { + ALD_I2C_ERROR_NONE = 0x0U, /**< No error */ + ALD_I2C_ERROR_BERR = 0x1U, /**< Berr error */ + ALD_I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ + ALD_I2C_ERROR_RUD = 0x4U, /**< Rx underflow error */ + ALD_I2C_ERROR_AF = 0x8U, /**< Af error */ + ALD_I2C_ERROR_ROV = 0x10U, /**< Rx overflow error */ + ALD_I2C_ERROR_RF = 0x20U, /**< Rx full error */ + ALD_I2C_ERROR_TUD = 0x40U, /**< Tx underflow error */ + ALD_I2C_ERROR_TOV = 0x80U, /**< Tx overflow error */ + ALD_I2C_ERROR_TE = 0x100U, /**< Tx empty error */ + ALD_I2C_ERROR_DMA = 0x200U, /**< Dma error */ + ALD_I2C_ERROR_TIMEOUT = 0x400U, /**< Timeout error */ +} ald_i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum { + ALD_I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ + ALD_I2C_STATE_READY = 0x20U, /**< Peripheral Initialized and ready for use */ + ALD_I2C_STATE_BUSY = 0x24U, /**< An internal process is ongoing */ + ALD_I2C_STATE_BUSY_TX = 0x21U, /**< Data Transmission process is ongoing */ + ALD_I2C_STATE_BUSY_RX = 0x22U, /**< Data Reception process is ongoing */ + + ALD_I2C_STATE_LISTEN = 0x28U, /**< Address Listen */ + ALD_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /**< Address Listen and Data Transmission */ + ALD_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /**< Address Listen and Data Receive */ + + ALD_I2C_STATE_ABORT = 0x60U, /**< Abort user request */ + ALD_I2C_STATE_TIMEOUT = 0xA0U, /**< timeout state */ + ALD_I2C_STATE_ERROR = 0xE0U, /**< Error */ +} ald_i2c_state_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum { + ALD_I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ + ALD_I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ +} ald_i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum { + ALD_I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + ALD_I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ +} ald_i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum { + ALD_I2C_GENERALCALL_DISABLE = 0x0U, /**< general call address is disable */ + ALD_I2C_GENERALCALL_ENABLE = 0x1U, /**< general call address is enable */ +} ald_i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum { + ALD_I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + ALD_I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ +} ald_i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum { + ALD_I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ + ALD_I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ +} ald_i2c_addr_size_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum { + ALD_I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + ALD_I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + ALD_I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + ALD_I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ +} ald_i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum { + ALD_I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + ALD_I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ + ALD_I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ +} ald_i2c_clock_t; + +/** + * @brief I2C OAR2 Register + */ +typedef enum { + ALD_I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ + ALD_I2C_OAR2_ADD2 = (1U << 1) /**< ADD2 BIT */ +} ald_i2c_oar2_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum { + ALD_I2C_CON1_PE = (1U << 0), /**< Peripheral enable BIT */ + ALD_I2C_CON1_TXDMA = (1U << 14), /**< Transmit DMA BIT */ + ALD_I2C_CON1_RXDMA = (1U << 15), /**< Receive DMA BIT */ + ALD_I2C_CON1_SBC = (1U << 16), /**< Receive DMA BIT */ + ALD_I2C_CON1_NOSTRETCH = (1U << 17), /**< Slave bytes control BIT */ + ALD_I2C_CON1_GCEN = (1U << 19), /**< General call BIT */ + ALD_I2C_CON1_SMBHEN = (1U << 20), /**< SMBus slave device enable BIT */ + ALD_I2C_CON1_SMBDEN = (1U << 21), /**< SMBus master device enable BIT */ + ALD_I2C_CON1_ALERTEN = (1U << 22), /**< SMBus alert device enable BIT */ + ALD_I2C_CON1_PECEN = (1U << 23), /**< PEC enable BIT */ +} ald_i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum { + ALD_I2C_CON2_RD_WRN = (1U << 10), /**< Master R/W control BIT */ + ALD_I2C_CON2_ADD10 = (1U << 11), /**< 10bit address control BIT */ + ALD_I2C_CON2_HEAD10R = (1U << 12), /**< 10bit address master Receive control BIT */ + ALD_I2C_CON2_START = (1U << 13), /**< Master start singal control BIT */ + ALD_I2C_CON2_STOP = (1U << 14), /**< Master stop singal control BIT */ + ALD_I2C_CON2_NACK = (1U << 15), /**< Master Nack control BIT */ + ALD_I2C_CON2_RELOAD = (1U << 24), /**< Master communication reload control BIT */ + ALD_I2C_CON2_AUTOEND = (1U << 25), /**< Master Autoend control BIT */ + ALD_I2C_CON2_PECBYTE = (1U << 26), /**< PEC control BIT */ + ALD_I2C_CON2_HOLDACK = (1U << 28), /**< Hold ack control BIT */ +} ald_i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum { + ALD_I2C_OA1MODE = (1U << 10), /**< Addr1 bits choose BIT */ + ALD_I2C_OA1EN = (1U << 15), /**< Addr1 enable BIT */ +} ald_i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum { + ALD_I2C_OA2EN = (1U << 15), /**< Addr2 enable BIT */ +} ald_i2c_addr2_t; + +/** + * @brief I2C TIMEOUTR Register + */ +typedef enum { + ALD_I2C_TIMEOUTR_TIDLE = (1U << 12), /**< SCL idle check enable BIT */ + ALD_I2C_TIMEOUTR_TIMEOUTEN = (1U << 15), /**< Timeout enable BIT */ +} ald_i2c_timoutr_t; + +/** + * @brief I2C peripherals module + */ +typedef enum { + ALD_I2C_MODULE_MASTER = (1U << 0), /**< Master module */ + ALD_I2C_MODULE_SLAVE = (1U << 1) /**< Slave module */ +} ald_i2c_module_t; + +/** + * @brief I2C STAT Register + */ +typedef enum { + ALD_I2C_STAT_TXE = (1U << 0), /**< Transmit empty flag */ + ALD_I2C_STAT_TXOV = (1U << 2), /**< Transmit overrun flag */ + ALD_I2C_STAT_TXUD = (1U << 3), /**< Transmit underrun flag */ + ALD_I2C_STAT_RXNE = (1U << 5), /**< Receive not empty flag */ + ALD_I2C_STAT_RXOV = (1U << 7), /**< Receive overrun flag */ + ALD_I2C_STAT_RXUD = (1U << 8), /**< Receive underrun flag */ + ALD_I2C_STAT_TC = (1U << 10), /**< Transmit completed flag */ + ALD_I2C_STAT_TCR = (1U << 11), /**< Transmit and reload completed flag */ + ALD_I2C_STAT_BUSY = (1U << 15), /**< Bus status busy flag */ + ALD_I2C_STAT_DIR = (1U << 16), /**< Slave R/W flag */ +} ald_i2c_stat_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum { + ALD_I2C_IT_TXE = (1U << 0), /**< Transmit empty interrupt */ + ALD_I2C_IT_TXOV = (1U << 2), /**< Transmit overrun interrupt */ + ALD_I2C_IT_TXUD = (1U << 3), /**< Transmit underrun interrupt */ + ALD_I2C_IT_RXNE = (1U << 5), /**< Receive not empty interrupt */ + ALD_I2C_IT_RXOV = (1U << 7), /**< Receive overrun interrupt */ + ALD_I2C_IT_RXUD = (1U << 8), /**< Receive underrun interrupt */ + ALD_I2C_IT_TC = (1U << 10), /**< Transmit completed interrupt */ + ALD_I2C_IT_TCR = (1U << 11), /**< Transmit and reload completed interrupt */ + ALD_I2C_IT_ADDR = (1U << 12), /**< Address matching interrupt */ + ALD_I2C_IT_NACK = (1U << 13), /**< NACK interrupt */ + ALD_I2C_IT_STOP = (1U << 14), /**< Stop detection interrupt */ + ALD_I2C_IT_BERR = (1U << 16), /**< Bus error interrupt */ + ALD_I2C_IT_ARLO = (1U << 17), /**< Arbitration loss interrupt */ + ALD_I2C_IT_PECE = (1U << 18), /**< PEC error interrupt */ + ALD_I2C_IT_TOUT = (1U << 19), /**< Timeout interrupt */ + ALD_I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */ +} ald_i2c_interrupt_t; + +/** + * @brief I2C TRISE Register + */ +typedef enum { + ALD_I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */ +} ald_i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct { + ald_i2c_module_t module; /**< Specifies the communication module */ + uint32_t clk_speed; /**< Specifies the clock frequency */ + uint32_t own_addr1; /**< Specifies the first device own address */ + ald_i2c_addr_t addr_mode; /**< Specifies addressing mode */ + ald_i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + ald_i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */ + ald_i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} ald_i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct ald_i2c_handle_s { + I2C_TypeDef *perh; /**< I2C registers base address */ + ald_i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ + + __IO uint32_t xfer_opt; /**< I2C transfer options */ + __IO uint32_t pre_state; /**< I2C previous communication state */ + + ald_dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + ald_dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ + + lock_state_t lock; /**< I2C locking object */ + __IO ald_i2c_state_t state; /**< I2C communication state */ + __IO ald_i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*addr_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Call Slave Addr callback */ + void (*listen_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Listen callback */ + + void (*master_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct ald_i2c_handle_s *arg); /**< Error callback */ +} ald_i2c_handle_t; + +/** + * @} + */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ + +/** + * @brief I2C Direction Definition + */ +#define ALD_I2C_DIRECTION_RECEIVE (0x00000000U) +#define ALD_I2C_DIRECTION_TRANSMIT (0x00000001U) +/** + * @brief I2C Transfer Definition + */ +#define ALD_I2C_NO_OPTION_FRAME (0xFFFF0000U) + +#define ALD_I2C_FIRST_FRAME (0x00000001U) +#define ALD_I2C_FIRST_AND_NEXT_FRAME (0x00000002U) +#define ALD_I2C_NEXT_FRAME (0x00000004U) +#define ALD_I2C_FIRST_AND_LAST_FRAME (0x00000008U) +#define ALD_I2C_LAST_FRAME_NO_STOP (0x00000010U) +#define ALD_I2C_LAST_FRAME (0x00000020U) + +#define ALD_I2C_OTHER_FRAME (0x00550000U) +#define ALD_I2C_OTHER_AND_LAST_FRAME (0x55000000U) + +#define ALD_I2C_FLAG_MASK (0xFFFFFFFFU) +#define ALD_I2C_RESET_HANDLE_STATE(x) ((x)->state = ALD_I2C_STATE_RESET) +#define ALD_I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) +#define ALD_I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) +#define ALD_I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y))) +#define ALD_I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y))) +#define ALD_I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) +#define ALD_I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & ALD_I2C_FLAG_MASK)) != RESET) +#define ALD_I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) +#define ALD_I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK)) +#define ALD_I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +#define ALD_I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1)) +#define IS_I2C_MODULE(x) (((x) == ALD_I2C_MODULE_MASTER) || ((x) == ALD_I2C_MODULE_SLAVE)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == ALD_I2C_ADDR_7BIT) || \ + ((ADDRESS) == ALD_I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == ALD_I2C_DUALADDR_DISABLE) || \ + ((ADDRESS) == ALD_I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == ALD_I2C_GENERALCALL_DISABLE) || \ + ((CALL) == ALD_I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(size) (((size) == ALD_I2C_MEMADD_SIZE_8BIT) || \ + ((size) == ALD_I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == ALD_I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == ALD_I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= ALD_I2C_EXTREME_FAST_MODE_MAX_CLK) ) +#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define IS_I2C_IT(x) (((x) == ALD_I2C_IT_TXE) || \ + ((x) == ALD_I2C_IT_TXOV) || \ + ((x) == ALD_I2C_IT_TXUD) || \ + ((x) == ALD_I2C_IT_RXNE) || \ + ((x) == ALD_I2C_IT_RXOV) || \ + ((x) == ALD_I2C_IT_RXUD) || \ + ((x) == ALD_I2C_IT_TC) || \ + ((x) == ALD_I2C_IT_TCR) || \ + ((x) == ALD_I2C_IT_ADDR) || \ + ((x) == ALD_I2C_IT_NACK) || \ + ((x) == ALD_I2C_IT_STOP) || \ + ((x) == ALD_I2C_IT_BERR) || \ + ((x) == ALD_I2C_IT_ARLO) || \ + ((x) == ALD_I2C_IT_PECE) || \ + ((x) == ALD_I2C_IT_TOUT) || \ + ((x) == ALD_I2C_IT_ALERT)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS(OPTION) (((OPTION) == ALD_I2C_OTHER_FRAME) || \ + ((OPTION) == ALD_I2C_OTHER_AND_LAST_FRAME)) + +#define IS_I2C_TRANSFER_OPTIONS(OPTION) (((OPTION) == ALD_I2C_FIRST_FRAME) || \ + ((OPTION) == ALD_I2C_FIRST_AND_NEXT_FRAME) || \ + ((OPTION) == ALD_I2C_NEXT_FRAME) || \ + ((OPTION) == ALD_I2C_FIRST_AND_LAST_FRAME) || \ + ((OPTION) == ALD_I2C_LAST_FRAME) || \ + ((OPTION) == ALD_I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS(OPTION)) + +#define ALD_I2C_STATE_MSK ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_BUSY_RX) & (~(ALD_I2C_STATE_READY))) +#define ALD_I2C_STATE_NONE (ALD_I2C_MODE_NONE) +#define ALD_I2C_STATE_MASTER_BUSY_TX ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_MASTER)) +#define ALD_I2C_STATE_MASTER_BUSY_RX ((ALD_I2C_STATE_BUSY_RX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_MASTER)) +#define ALD_I2C_STATE_SLAVE_BUSY_TX ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_SLAVE)) +#define ALD_I2C_STATE_SLAVE_BUSY_RX ((ALD_I2C_STATE_BUSY_RX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_SLAVE)) + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +ald_status_t ald_i2c_init(ald_i2c_handle_t *hperh); +ald_status_t ald_i2c_reset(ald_i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions + * @{ + */ +/** Blocking mode: Polling */ +ald_status_t ald_i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_master_recv(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_send(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_recv(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); + +/** Non-Blocking mode: Interrupt */ +ald_status_t ald_i2c_master_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_master_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_write_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_read_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); + + +/** Non-Blocking mode: DMA */ +ald_status_t ald_i2c_master_send_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_master_recv_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_send_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_recv_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_write_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_read_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); + +/** Non-Blocking Sequence transmit mode */ + +ald_status_t ald_i2c_master_seq_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_master_seq_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_slave_seq_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_slave_seq_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_master_abort_it(ald_i2c_handle_t *hperh, uint16_t addr); +ald_status_t ald_i2c_enablelisten_it(ald_i2c_handle_t *hperh); +ald_status_t ald_i2c_disablelisten_it(ald_i2c_handle_t *hperh); + +void ald_i2c_seq_ev_irq_handler(ald_i2c_handle_t *hperh); +void ald_i2c_seq_er_irq_handler(ald_i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @{ + */ +ald_i2c_state_t ald_i2c_get_state(ald_i2c_handle_t *hperh); +uint32_t ald_i2c_get_error(ald_i2c_handle_t *hperh); +void ald_i2c_clear_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); +flag_status_t ald_i2c_get_mask_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); +flag_status_t ald_i2c_get_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); +it_status_t ald_i2c_get_it_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ +void ald_i2c_ev_irq_handler(ald_i2c_handle_t *hperh); +void ald_i2c_er_irq_handler(ald_i2c_handle_t *hperh); +void ald_i2c_interrupt_config(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it, type_func_t state); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_I2C_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2s.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2s.h new file mode 100644 index 0000000000..b5e8ca879c --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_i2s.h @@ -0,0 +1,399 @@ +/** + ********************************************************************************* + * + * @file ald_i2s.c + * @brief Header file of I2S module driver. + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_I2S_H__ +#define __ALD_I2S_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/** @defgroup I2S_Public_Types I2S Public Types + * @{ + */ + +/** + * @brief Channel length + */ +typedef enum { + ALD_I2S_WIDE_16 = 0x0U, /**< Channel length is 16 */ + ALD_I2S_WIDE_32 = 0x1U, /**< Channel length is 32 */ +} ald_i2s_chlen_t; + +/** + * @brief Data length + */ +typedef enum { + ALD_I2S_LEN_16 = 0x0U, /**< Data length is 16 */ + ALD_I2S_LEN_24 = 0x1U, /**< Data length is 24 */ + ALD_I2S_LEN_32 = 0x2U, /**< Data length is 32 */ +} ald_i2s_datalen_t; + +/** + * @brief Inactive state clock polarity + */ +typedef enum { + ALD_I2S_INACTIVE_LOW = 0x0U, /**< Inactive state is low */ + ALD_I2S_INACTIVE_HIGH = 0x1U, /**< Inactive state is high */ +} ald_i2s_cpol_t; + +/** + * @brief I2s standard + */ +typedef enum { + ALD_I2S_STD_PHI = 0x0U, /**< Philips standard */ + ALD_I2S_STD_MSB = 0x1U, /**< MSB standard */ + ALD_I2S_STD_LSB = 0x2U, /**< LSB standard */ + ALD_I2S_STD_PCM = 0x3U, /**< PCM standard */ +} ald_i2s_standard_t; + +/** + * @brief I2s configuration mode + */ +typedef enum { + ALD_I2S_SLAVE_DUPLEX = 0x0U, /**< I2S slave full duplex mode */ + ALD_I2S_SLAVE_RECEIVE = 0x1U, /**< I2S slave receive mode */ + ALD_I2S_SLAVE_TRANSMIT = 0x2U, /**< I2S slave transmit mode */ + ALD_I2S_MASTER_DUPLEX = 0x4U, /**< I2S master full duplex mode */ + ALD_I2S_MASTER_TRANSMIT = 0x5U, /**< I2S master transmit mode */ + ALD_I2S_MASTER_RECEIVE = 0x6U, /**< I2S master receive mode */ +} ald_i2s_cfg_t; + +/** + * @brief Pcm frame synchronization + */ +typedef enum { + ALD_I2S_FRAME_SHORT = 0x0U, /**< I2S PCM short frame */ + ALD_I2S_FRAME_LONG = 0x1U, /**< I2S PCM long frame */ +} ald_i2s_pcms_t; + +/** + * @brief Channel side + */ +typedef enum { + ALD_I2S_SIDE_LEFT = 0U, /**< Sound channel is left */ + ALD_I2S_SIDE_RIGHT = 1U, /**< Sound channel is right */ +} ald_i2s_ch_side_t; + +/** + * @brief I2S error status + */ +typedef enum { + ALD_I2S_ERROR_NONE = 0x0U, /**< none */ + ALD_I2S_ERROR_MODF = 0x1U, /**< mode fault */ + ALD_I2S_ERROR_DMA = 0x2U, /**< crc error */ + ALD_I2S_ERROR_FRE = 0x4U, /**< frame error */ + ALD_I2S_ERROR_RXOV = 0x8U, /**< receive over error */ + ALD_I2S_ERROR_TXOV = 0x10U, /**< dma error */ + ALD_I2S_ERROR_FLAG = 0x20U, /**< interrupt flag error */ +} ald_i2s_error_t; + +/** + * @brief interrupt control + */ +typedef enum { + ALD_I2S_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + ALD_I2S_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + ALD_I2S_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + ALD_I2S_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */ + ALD_I2S_IT_RXNE = (1U << 8), /**< Receive fifo not empty interrupt */ + ALD_I2S_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + ALD_I2S_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + ALD_I2S_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + ALD_I2S_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + ALD_I2S_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + ALD_I2S_IT_MODF = (1U << 17), /**< Mode error interrupt */ + ALD_I2S_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} ald_i2s_it_t; + +/** + * @brief I2S dma request definition + */ +typedef enum { + ALD_I2S_DMA_REQ_TX = 0U, /**< TX dma request */ + ALD_I2S_DMA_REQ_RX = 1U, /**< RX dma request */ +} ald_i2s_dma_req_t; + +/** + * @brief interrupt flag + */ +typedef enum { + ALD_I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + ALD_I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + ALD_I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + ALD_I2S_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */ + ALD_I2S_IF_RXNE = (1U << 8), /**< Receive fifo not empty interrupt flag */ + ALD_I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + ALD_I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + ALD_I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + ALD_I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + ALD_I2S_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */ + ALD_I2S_IF_MODF = (1U << 17), /**< Mode error interrupt flag */ + ALD_I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} ald_i2s_flag_t; + +/** + * @brief I2S state structures definition + */ +typedef enum { + ALD_I2S_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_I2S_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_I2S_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + ALD_I2S_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + ALD_I2S_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + ALD_I2S_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + ALD_I2S_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_I2S_STATE_ERROR = 0x04U, /**< Error */ +} ald_i2s_state_t; + +/** + * @brief I2S status definition + */ +typedef enum { + ALD_I2S_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + ALD_I2S_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + ALD_I2S_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + ALD_I2S_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + ALD_I2S_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */ + ALD_I2S_STATUS_RXNE = (1U << 8), /**< Receive fifo not empty status */ + ALD_I2S_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + ALD_I2S_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + ALD_I2S_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + ALD_I2S_STATUS_RXTH = (1U << 12), /**< Receive fifo over threshold status */ + ALD_I2S_STATUS_CHSIDE = (1U << 14), /**< Sound channel status */ + ALD_I2S_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} ald_i2s_status_t; + +/** + * @brief I2S TXE/RXNE status definition + */ +typedef enum { + ALD_I2S_SR_TXE = 0U, /**< STAT TXE set */ + ALD_I2S_SR_RXNE = 1U, /**< STAT RXTH set */ + ALD_I2S_SR_TXE_RXNE = 2U, /**< STAT TXE and RXTH set */ +} ald_i2s_sr_status_t; + +/** + * @brief I2S init structure definition + */ +typedef struct { + ald_i2s_chlen_t ch_len; /**< Channel length choose */ + ald_i2s_datalen_t data_len; /**< Data length choose */ + ald_i2s_cpol_t polarity; /**< Inactive clock polarity */ + ald_i2s_standard_t standard; /**< Standard choose */ + ald_i2s_pcms_t pcm_frame; /**< PCM frame synchronization */ + type_func_t ext_clk_en; /**< Choose external clock or APB1 clock */ + uint32_t ext_clk; /**< External clock, unit is Hz */ + type_func_t mck_en; /**< Main clock output function */ + uint32_t sampling; /**< Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz */ +} ald_i2s_init_t; + +/** + * @brief I2S handle structure definition + */ +typedef struct ald_i2s_handle_s { + SPI_I2S_TypeDef *perh; /**< I2S registers base address */ + ald_i2s_init_t init; /**< I2S communication parameters */ + uint16_t *tx_buf; /**< Pointer to I2S Tx transfer buffer */ + uint32_t tx_size; /**< I2S Tx transfer size */ + uint32_t tx_count; /**< I2S Tx transfer counter */ + uint16_t *rx_buf; /**< Pointer to I2S Rx transfer buffer */ + uint32_t rx_size; /**< I2S Rx Transfer size */ + uint32_t rx_count; /**< I2S Rx Transfer Counter */ + + ald_dma_handle_t hdmatx; /**< I2S DMA handle parameters */ + ald_dma_handle_t hdmarx; /**< I2S DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_i2s_state_t state; /**< I2S communication state */ + uint8_t side; /**< I2S channel side */ + uint32_t err_code; /**< I2S error code */ + + void (*tx_cplt_cbk)(struct ald_i2s_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct ald_i2s_handle_s *arg); /**< Rx completed callback */ + void (*err_cbk)(struct ald_i2s_handle_s *arg); /**< error callback */ +} ald_i2s_handle_t; +/** + * @} + */ + +/** @defgroup I2S_Public_Macros I2S Public Macros + * @{ + */ +#define ALD_I2S_RESET_HANDLE_STATE(x) ((x)->state = ALD_I2S_STATE_RESET) +#define ALD_I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +#define ALD_I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +/** + * @} + */ + +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ +#define IS_I2S(x) ((x) == I2S0) +#define IS_I2S_CH_LEN(x) (((x) == ALD_I2S_WIDE_16) || \ + ((x) == ALD_I2S_WIDE_32)) +#define IS_I2S_DATE_LEN(x) (((x) == ALD_I2S_LEN_16) || \ + ((x) == ALD_I2S_LEN_24) || \ + ((x) == ALD_I2S_LEN_32)) +#define IS_I2S_CPOL(x) (((x) == ALD_I2S_INACTIVE_LOW) || \ + ((x) == ALD_I2S_INACTIVE_HIGH)) +#define IS_I2S_STANDARD(x) (((x) == ALD_I2S_STD_PHI) || \ + ((x) == ALD_I2S_STD_MSB) || \ + ((x) == ALD_I2S_STD_LSB) || \ + ((x) == ALD_I2S_STD_PCM)) +#define IS_I2S_PCMS(x) (((x) == ALD_I2S_FRAME_SHORT) || \ + ((x) == ALD_I2S_FRAME_LONG)) +#define IS_I2S_IT(x) (((x) == ALD_I2S_IT_TXE) || \ + ((x) == ALD_I2S_IT_TXOV) || \ + ((x) == ALD_I2S_IT_TXUD) || \ + ((x) == ALD_I2S_IT_TXTH) || \ + ((x) == ALD_I2S_IT_RXNE) || \ + ((x) == ALD_I2S_IT_RXF) || \ + ((x) == ALD_I2S_IT_RXOV) || \ + ((x) == ALD_I2S_IT_RXUD) || \ + ((x) == ALD_I2S_IT_RXTH) || \ + ((x) == ALD_I2S_IT_CRCERR) || \ + ((x) == ALD_I2S_IT_MODF) || \ + ((x) == ALD_I2S_IT_FRE)) +#define IS_I2S_IF(x) (((x) == ALD_I2S_IF_TXE) || \ + ((x) == ALD_I2S_IF_TXOV) || \ + ((x) == ALD_I2S_IF_TXUD) || \ + ((x) == ALD_I2S_IF_TXTH) || \ + ((x) == ALD_I2S_IF_RXNE) || \ + ((x) == ALD_I2S_IF_RXF) || \ + ((x) == ALD_I2S_IF_RXOV) || \ + ((x) == ALD_I2S_IF_RXUD) || \ + ((x) == ALD_I2S_IF_RXTH) || \ + ((x) == ALD_I2S_IF_CRCERR) || \ + ((x) == ALD_I2S_IF_MODF) || \ + ((x) == ALD_I2S_IF_FRE)) +#define IS_I2S_STATUS(x) (((x) == ALD_I2S_STATUS_TXE) || \ + ((x) == ALD_I2S_STATUS_TXF) || \ + ((x) == ALD_I2S_STATUS_TXOV) || \ + ((x) == ALD_I2S_STATUS_TXUD) || \ + ((x) == ALD_I2S_STATUS_TXTH) || \ + ((x) == ALD_I2S_STATUS_RXNE) || \ + ((x) == ALD_I2S_STATUS_RXF) || \ + ((x) == ALD_I2S_STATUS_RXOV) || \ + ((x) == ALD_I2S_STATUS_RXUD) || \ + ((x) == ALD_I2S_STATUS_RXTH) || \ + ((x) == ALD_I2S_STATUS_CHSIDE) || \ + ((x) == ALD_I2S_STATUS_BUSY)) +#define IS_I2S_DMA_REQ(x) (((x) == ALD_I2S_DMA_REQ_TX) || \ + ((x) == ALD_I2S_DMA_REQ_RX)) +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions + * @{ + */ + +/** @addtogroup I2S_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_i2s_init(ald_i2s_handle_t *hperh); +void ald_i2s_reset(ald_i2s_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_i2s_master_send(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_recv(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_send_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size); +ald_status_t ald_i2s_master_recv_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size); + +ald_status_t ald_i2s_master_send_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel); +ald_status_t ald_i2s_master_recv_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch); +ald_status_t ald_i2s_dma_pause(ald_i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_resume(ald_i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_stop(ald_i2s_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group3 + * @{ + */ +void ald_i2s_irq_handler(ald_i2s_handle_t *hperh); +void ald_i2s_interrupt_config(ald_i2s_handle_t *hperh, ald_i2s_it_t it, type_func_t state); +void ald_i2s_dma_req_config(ald_i2s_handle_t *hperh, ald_i2s_dma_req_t req, type_func_t state); +flag_status_t ald_i2s_get_status(ald_i2s_handle_t *hperh, ald_i2s_status_t status); +it_status_t ald_i2s_get_it_status(ald_i2s_handle_t *hperh, ald_i2s_it_t it); +flag_status_t ald_i2s_get_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag); +flag_status_t ald_i2s_get_mask_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag); +void ald_i2s_clear_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group4 + * @{ + */ +ald_i2s_state_t ald_i2s_get_state(ald_i2s_handle_t *hperh); +uint32_t ald_i2s_get_error(ald_i2s_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_I2S_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pis.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pis.h new file mode 100644 index 0000000000..11c397f974 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pis.h @@ -0,0 +1,692 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** + * @brief Producer entry + */ +/** @defgroup PIS_Public_Types PIS Public Types + * @verbatim + In PIS module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + TIMER0 ----> AD16C4T + TIMER4 ----> BS16T + TIMER5 ----> GP16C4T0 + TIMER6 ----> GP16C4T1 + TIMER7 ----> GP16C4T2 + @endverbatim + * @{ + */ +typedef enum { + ALD_PIS_NON = 0x0U, /**< No async */ + ALD_PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + ALD_PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + ALD_PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + ALD_PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + ALD_PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + ALD_PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + ALD_PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + ALD_PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + ALD_PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + ALD_PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + ALD_PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + ALD_PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + ALD_PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + ALD_PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + ALD_PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + ALD_PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + ALD_PIS_CLK_HSCO = 0x20U, /**< CLK: HSCO, level,support async */ + ALD_PIS_CLK_LSCO = 0x21U, /**< CLK: LSCO, level,support async */ + ALD_PIS_CLK_BUZ = 0x22U, /**< PCLK: BUZ, level,support async */ + ALD_PIS_ADC0_INSERT = 0x60U, /**< ADC0 insert, pclk2 pulse,support async */ + ALD_PIS_ADC0_NORMAL = 0x61U, /**< ADC0 normal, pclk2 pulse,support async */ + ALD_PIS_ADC0_AWDT = 0x62U, /**< ADC0 AWDT */ + ALD_PIS_LVD = 0x70U, /**< LVD, level,support async */ + ALD_PIS_UART0_RESERVE0 = 0x80U, /**< Uart0 reserve bit 0 */ + ALD_PIS_UART0_RESERVE1 = 0x81U, /**< Uart0 reserve bit 1 */ + ALD_PIS_UART0_RESERVE2 = 0x82U, /**< Uart0 reserve bit 2 */ + ALD_PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level */ + ALD_PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level */ + ALD_PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse */ + ALD_PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse */ + ALD_PIS_UART1_RESERVE0 = 0x90U, /**< Uart1 reserve bit 0 */ + ALD_PIS_UART1_RESERVE1 = 0x91U, /**< Uart1 reserve bit 1 */ + ALD_PIS_UART1_RESERVE2 = 0x92U, /**< Uart1 reserve bit 2 */ + ALD_PIS_UART1_RTSOUT = 0x93U, /**< Uart1 rtsout, level */ + ALD_PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level */ + ALD_PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse */ + ALD_PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse */ + ALD_PIS_UART2_RESERVE0 = 0xa0U, /**< Uart2 reserve bit 0 */ + ALD_PIS_UART2_RESERVE1 = 0xa1U, /**< Uart2 reserve bit 1 */ + ALD_PIS_UART2_RESERVE2 = 0xa2U, /**< Uart2 reserve bit 2 */ + ALD_PIS_UART2_RTSOUT = 0xa3U, /**< Uart2 rtsout, level */ + ALD_PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level */ + ALD_PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse */ + ALD_PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse */ + ALD_PIS_UART3_RESERVE0 = 0xb0U, /**< Uart3 reserve bit 0 */ + ALD_PIS_UART3_RESERVE1 = 0xb1U, /**< Uart3 reserve bit 1 */ + ALD_PIS_UART3_RESERVE2 = 0xb2U, /**< Uart3 reserve bit 2 */ + ALD_PIS_UART3_RTSOUT = 0xb3U, /**< Uart3 rtsout, level */ + ALD_PIS_UART3_TXOUT = 0xb4U, /**< Uart3 txout, level */ + ALD_PIS_UART3_SYN_SEND = 0xb5U, /**< Uart3 syn send, pulse */ + ALD_PIS_UART3_SYN_RECV = 0xb6U, /**< Uart3 syn recv, pulse */ + ALD_PIS_UART4_RESERVE0 = 0xc0U, /**< Uart4 reserve bit 0 */ + ALD_PIS_UART4_RESERVE1 = 0xc1U, /**< Uart4 reserve bit 1 */ + ALD_PIS_UART4_RESERVE2 = 0xc2U, /**< Uart4 reserve bit 2 */ + ALD_PIS_UART4_RTSOUT = 0xc3U, /**< Uart4 rtsout, level */ + ALD_PIS_UART4_TXOUT = 0xc4U, /**< Uart4 txout, level */ + ALD_PIS_UART4_SYN_SEND = 0xc5U, /**< Uart4 syn send, pulse */ + ALD_PIS_UART4_SYN_RECV = 0xc6U, /**< Uart4 syn recv, pulse */ + ALD_PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + ALD_PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + ALD_PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + ALD_PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + ALD_PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + ALD_PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + ALD_PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + ALD_PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + ALD_PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + ALD_PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + ALD_PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + ALD_PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_1 = 0x122U, /**< Timer0 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_1 = 0x122U, /**< Timer0 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_2 = 0x124U, /**< Timer0 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_2 = 0x124U, /**< Timer0 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_3 = 0x126U, /**< Timer0 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_3 = 0x126U, /**< Timer0 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_4 = 0x128U, /**< Timer0 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_4 = 0x128U, /**< Timer0 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER5_UPDATA = 0x1c0U, /**< Timer5 updata, plck1 pulse */ + ALD_PIS_TIMER5_TRIG = 0x1c1U, /**< Timer5 trig, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_1 = 0x1c2U, /**< Timer5 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_1 = 0x1c2U, /**< Timer5 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_2 = 0x1c4U, /**< Timer5 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_2 = 0x1c4U, /**< Timer5 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_3 = 0x1c6U, /**< Timer5 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_3 = 0x1c6U, /**< Timer5 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_4 = 0x1c8U, /**< Timer5 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_4 = 0x1c8U, /**< Timer5 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER6_UPDATA = 0x1d0U, /**< Timer6 updata, plck1 pulse */ + ALD_PIS_TIMER6_TRIG = 0x1d1U, /**< Timer6 trig, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_1 = 0x1d2U, /**< Timer6 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_1 = 0x1d2U, /**< Timer6 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_2 = 0x1d4U, /**< Timer6 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_2 = 0x1d4U, /**< Timer6 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_3 = 0x1d6U, /**< Timer6 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_3 = 0x1d6U, /**< Timer6 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_4 = 0x1d8U, /**< Timer6 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_4 = 0x1d8U, /**< Timer6 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER7_UPDATA = 0x1e0U, /**< Timer7 updata, plck1 pulse */ + ALD_PIS_TIMER7_TRIG = 0x1e1U, /**< Timer7 trig, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_1 = 0x1e2U, /**< Timer7 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_1 = 0x1e2U, /**< Timer7 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_2 = 0x1e4U, /**< Timer7 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_2 = 0x1e4U, /**< Timer7 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_3 = 0x1e6U, /**< Timer7 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_3 = 0x1e6U, /**< Timer7 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_4 = 0x1e8U, /**< Timer7 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_4 = 0x1e8U, /**< Timer7 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER4_UPDATA = 0x1b0U, /**< Timer4 updata, plck1 pulse */ + ALD_PIS_TIMER4_TRIG = 0x1b1U, /**< Timer4 trig, plck1 pulse */ + ALD_PIS_DMA_CH0 = 0x190U, /**< DMA CH0 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH1 = 0x191U, /**< DMA CH1 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH2 = 0x192U, /**< DMA CH2 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH3 = 0x193U, /**< DMA CH3 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH4 = 0x194U, /**< DMA CH4 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH5 = 0x195U, /**< DMA CH5 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH6 = 0x196U, /**< DMA CH6 complete, plck1 pulse, support async */ + ALD_PIS_DMA_ALL = 0x19fU, /**< DMA all channel complete, plck1 pulse, support async */ +} ald_pis_src_t; + +/** + * @brief Consumer entry + */ +/** @defgroup PIS_Public_Types PIS Public Types + * @verbatim + In PIS module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + TIMER0 ----> AD16C4T + TIMER1 ----> GP16C4T0 + TIMER2 ----> GP16C4T1 + TIMER3 ----> GP16C4T2 + @endverbatim + * @{ + */ +typedef enum { + ALD_PIS_CH4_TIMER0_ITR0 = 0x0034U, /** Tim0 internal input chan0 */ + ALD_PIS_CH5_TIMER0_ITR1 = 0x0035U, /** Tim0 internal input chan1 */ + ALD_PIS_CH6_TIMER0_ITR2 = 0x0036U, /** Tim0 internal input chan2 */ + ALD_PIS_CH7_TIMER0_ITR3 = 0x0037U, /** Tim0 internal input chan3 */ + ALD_PIS_CH4_TIMER1_ITR0 = 0x0034U, /** Tim1 internal input chan0 */ + ALD_PIS_CH5_TIMER1_ITR1 = 0x0035U, /** Tim1 internal input chan1 */ + ALD_PIS_CH6_TIMER1_ITR2 = 0x0036U, /** Tim1 internal input chan2 */ + ALD_PIS_CH7_TIMER1_ITR3 = 0x0037U, /** Tim1 internal input chan3 */ + ALD_PIS_CH4_TIMER2_ITR0 = 0x0034U, /** Tim2 internal input chan0 */ + ALD_PIS_CH5_TIMER2_ITR1 = 0x0035U, /** Tim2 internal input chan1 */ + ALD_PIS_CH6_TIMER2_ITR2 = 0x0036U, /** Tim2 internal input chan2 */ + ALD_PIS_CH7_TIMER2_ITR3 = 0x0037U, /** Tim2 internal input chan3 */ + ALD_PIS_CH4_TIMER3_ITR0 = 0x0034U, /** Tim3 internal input chan0 */ + ALD_PIS_CH5_TIMER3_ITR1 = 0x0035U, /** Tim3 internal input chan1 */ + ALD_PIS_CH6_TIMER3_ITR2 = 0x0036U, /** Tim3 internal input chan2 */ + ALD_PIS_CH7_TIMER3_ITR3 = 0x0037U, /** Tim3 internal input chan3 */ + ALD_PIS_CH4_ADC0_NORMAL = 0x0034U, /** ADC0 normal transform */ + ALD_PIS_CH5_ADC0_INSERT = 0x0035U, /** ADC0 insert transform */ + ALD_PIS_CH7_DMA_REQUEST = 0x0037U, /** DMA request 7 */ + ALD_PIS_CH7_UART4_RXD = 0x0417U, /**< Uart4 Rx data */ + ALD_PIS_CH6_UART3_RXD = 0x0316U, /**< Uart3 Rx data */ + ALD_PIS_CH5_UART2_RXD = 0x0215U, /**< Uart2 Rx data */ + ALD_PIS_CH4_UART1_RXD = 0x0114U, /**< Uart1 Rx data */ + ALD_PIS_CH3_UART0_RXD = 0x0013U, /**< Uart0 Rx data */ + ALD_PIS_CH4_TIMER3_CH4IN = 0x1B04U, /**< Tim3 input chan4 */ + ALD_PIS_CH4_TIMER2_CH4IN = 0x1304U, /**< Tim2 input chan4 */ + ALD_PIS_CH3_SPI1_CLK = 0x0F13U, /**< Spi1 clk */ + ALD_PIS_CH7_TIMER3_CH3IN = 0x1A07U, /**< Tim3 input chan3 */ + ALD_PIS_CH7_TIMER2_CH3IN = 0x1207U, /**< Tim2 input chan3 */ + ALD_PIS_CH2_SPI1_RX = 0x0E12U, /**< Spi1 rx */ + ALD_PIS_CH6_TIMER3_CH2IN = 0x1906U, /**< Tim3 input chan2 */ + ALD_PIS_CH6_TIMER2_CH2IN = 0x1106U, /**< Tim2 input chan2 */ + ALD_PIS_CH1_SPI0_CLK = 0x0D11U, /**< SPI0 CLK */ + ALD_PIS_CH5_TIMER3_CH1IN = 0x1805U, /**< Tim3 input chan1 */ + ALD_PIS_CH5_TIMER2_CH1IN = 0x1005U, /**< Tim2 input chan1 */ + ALD_PIS_CH0_SPI0_RX = 0x0C10U, /**< SPI0 RX */ + ALD_PIS_CH4_TIMER1_CH4IN = 0x0B04U, /**< Tim1 input chan4 */ + ALD_PIS_CH4_TIMER0_CH4IN = 0x0304U, /**< Tim0 input chan4 */ + ALD_PIS_CH3_TIMER1_CH3IN = 0x0A03U, /**< Tim1 input chan3 */ + ALD_PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Tim0 input chan3 */ + ALD_PIS_CH2_TIMER1_CH2IN = 0x0902U, /**< Tim1 input chan2 */ + ALD_PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Tim0 input chan2 */ + ALD_PIS_CH1_TIMER1_CH1IN = 0x0801U, /**< Tim1 input chan1 */ + ALD_PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Tim0 input chan1 */ + ALD_PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Tim0 break in */ + ALD_PIS_TRIG_RESERVE = 0xFFFFU, /**< Other Consumer */ +} ald_pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum { + ALD_PIS_CLK_PCLK = 0U, /**< APB peripherals clock */ + ALD_PIS_CLK_HCLK = 2U, /**< AHB peripherals clock */ + ALD_PIS_CLK_RESERVE = 3U, /**< reserve clock */ +} ald_pis_clock_t; + +/** + * @brief Level select + */ +typedef enum { + ALD_PIS_EDGE_NONE = 0U, /**< None edge */ + ALD_PIS_EDGE_UP = 1U, /**< Up edge */ + ALD_PIS_EDGE_DOWN = 2U, /**< Down edge */ + ALD_PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ +} ald_pis_edge_t; + +/** + * @brief Output style + */ +typedef enum { + ALD_PIS_OUT_LEVEL = 0U, /**< Level */ + ALD_PIS_OUT_PULSE = 1U, /**< Pulse */ +} ald_pis_output_t; +/** + * @brief Sync select + */ +typedef enum { + ALD_PIS_SYN_DIRECT = 0U, /**< Direct */ + ALD_PIS_SYN_LEVEL_ASY_APB = 1U, /**< Producer level signal and Consumer in APB */ + ALD_PIS_SYN_LEVEL_ASY_AHB = 3U, /**< Producer level signal and Consumer in AHB */ + ALD_PIS_SYN_PULSE_ASY_APB = 4U, /**< Producer Pulse signal and Consumer in APB */ + ALD_PIS_SYN_PULSE_ASY_AHB = 6U, /**< Producer Pulse signal and Consumer in AHB */ +} ald_pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum { + ALD_PIS_CH_0 = 0U, /**< Channel 0 */ + ALD_PIS_CH_1 = 1U, /**< Channel 1 */ + ALD_PIS_CH_2 = 2U, /**< Channel 2 */ + ALD_PIS_CH_3 = 3U, /**< Channel 3 */ + ALD_PIS_CH_4 = 4U, /**< Channel 4 */ + ALD_PIS_CH_5 = 5U, /**< Channel 5 */ + ALD_PIS_CH_6 = 6U, /**< Channel 6 */ + ALD_PIS_CH_7 = 7U, /**< Channel 7 */ +} ald_pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum { + ALD_PIS_OUT_CH_0 = 0U, /**< Channel 0 */ + ALD_PIS_OUT_CH_1 = 1U, /**< Channel 1 */ + ALD_PIS_OUT_CH_2 = 2U, /**< Channel 2 */ + ALD_PIS_OUT_CH_3 = 3U, /**< Channel 3 */ + ALD_PIS_OUT_CH_4 = 4U, /**< Channel 4 */ + ALD_PIS_OUT_CH_5 = 5U, /**< Channel 5 */ + ALD_PIS_OUT_CH_6 = 6U, /**< Channel 6 */ + ALD_PIS_OUT_CH_7 = 7U, /**< Channel 7 */ +} ald_pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum { + ALD_PIS_CON_0 = 0U, /**< Con 0 */ + ALD_PIS_CON_1 = 1U, /**< Con 1 */ + ALD_PIS_CON_NONE = 2U, /**< None */ +} ald_pis_con_t; + +/** + * @brief PIS state structures definition + */ +typedef enum { + ALD_PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + ALD_PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_PIS_STATE_ERROR = 0x04U, /**< Error */ +} ald_pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum { + ALD_PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + ALD_PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + ALD_PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + ALD_PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + ALD_PIS_UART4_TX = 4U, /**< Modulate uart4 tx */ +} ald_pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum { + ALD_PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + ALD_PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ +} ald_pis_modu_level_t; + +/** + * @brief PIS modulate source + */ +typedef enum { + ALD_PIS_SRC_NONE = 0U, /**< Stop modulate */ + ALD_PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + ALD_PIS_SRC_TIMER5 = 4U, /**< Modulate source is TIMER5 */ + ALD_PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + ALD_PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + ALD_PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ +} ald_pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum { + ALD_PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + ALD_PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + ALD_PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + ALD_PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ +} ald_pis_modu_channel_t; + +/** + * @brief PIS input channel choose + */ +typedef enum { + ALD_PIS_NONE_INPUT = 0U, /**< Consumer input none */ + ALD_PIS_PORT_INPUT = 1U, /**< Consumer input choose external port */ + ALD_PIS_CHAN_INPUT = 2U, /**< Consumer input choose pis channel */ +} ald_pis_input_sel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct { + ald_pis_src_t producer_src; /**< Producer entry */ + ald_pis_output_t producer_signal; /**< Producer signal mode */ + ald_pis_clock_t producer_clk; /**< Producer module clock */ + ald_pis_edge_t producer_edge; /**< Producer module pin output edge */ + ald_pis_trig_t consumer_trig; /**< Consumer entry */ + ald_pis_clock_t consumer_clk; /**< Consumer clock */ + ald_pis_input_sel_t input_chan; /**< Consumer input channel */ +} ald_pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct { + ald_pis_modu_targ_t target; /**< Modulate target */ + ald_pis_modu_level_t level; /**< Modulate level */ + ald_pis_modu_src_t src; /**< Modulate src */ + ald_pis_modu_channel_t channel; /**< Modulate channel */ +} ald_pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct ald_pis_handle_s { + PIS_TypeDef *perh; /**< Register base address */ + ald_pis_init_t init; /**< PIS required parameters */ + ald_pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + ald_pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + ald_pis_state_t state; /**< PIS operation state */ +} ald_pis_handle_t; +/** + * @} + */ + + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == ALD_PIS_NON) || \ + ((x) == ALD_PIS_GPIO_PIN0) || \ + ((x) == ALD_PIS_GPIO_PIN1) || \ + ((x) == ALD_PIS_GPIO_PIN2) || \ + ((x) == ALD_PIS_GPIO_PIN3) || \ + ((x) == ALD_PIS_GPIO_PIN4) || \ + ((x) == ALD_PIS_GPIO_PIN5) || \ + ((x) == ALD_PIS_GPIO_PIN6) || \ + ((x) == ALD_PIS_GPIO_PIN7) || \ + ((x) == ALD_PIS_GPIO_PIN8) || \ + ((x) == ALD_PIS_GPIO_PIN9) || \ + ((x) == ALD_PIS_GPIO_PIN10) || \ + ((x) == ALD_PIS_GPIO_PIN11) || \ + ((x) == ALD_PIS_GPIO_PIN12) || \ + ((x) == ALD_PIS_GPIO_PIN13) || \ + ((x) == ALD_PIS_GPIO_PIN14) || \ + ((x) == ALD_PIS_GPIO_PIN15) || \ + ((x) == ALD_PIS_CLK_HSCO) || \ + ((x) == ALD_PIS_CLK_LSCO) || \ + ((x) == ALD_PIS_CLK_BUZ) || \ + ((x) == ALD_PIS_ADC0_INSERT) || \ + ((x) == ALD_PIS_ADC0_NORMAL) || \ + ((x) == ALD_PIS_ADC0_AWDT) || \ + ((x) == ALD_PIS_LVD) || \ + ((x) == ALD_PIS_UART0_RESERVE0) || \ + ((x) == ALD_PIS_UART0_RESERVE1) || \ + ((x) == ALD_PIS_UART0_RESERVE2) || \ + ((x) == ALD_PIS_UART0_RTSOUT) || \ + ((x) == ALD_PIS_UART0_TXOUT) || \ + ((x) == ALD_PIS_UART0_SYN_SEND) || \ + ((x) == ALD_PIS_UART0_SYN_RECV) || \ + ((x) == ALD_PIS_UART1_RESERVE0) || \ + ((x) == ALD_PIS_UART1_RESERVE1) || \ + ((x) == ALD_PIS_UART1_RESERVE2) || \ + ((x) == ALD_PIS_UART1_RTSOUT) || \ + ((x) == ALD_PIS_UART1_TXOUT) || \ + ((x) == ALD_PIS_UART1_SYN_SEND) || \ + ((x) == ALD_PIS_UART1_SYN_RECV) || \ + ((x) == ALD_PIS_UART2_RESERVE0) || \ + ((x) == ALD_PIS_UART2_RESERVE1) || \ + ((x) == ALD_PIS_UART2_RESERVE2) || \ + ((x) == ALD_PIS_UART2_RTSOUT) || \ + ((x) == ALD_PIS_UART2_TXOUT) || \ + ((x) == ALD_PIS_UART2_SYN_SEND) || \ + ((x) == ALD_PIS_UART2_SYN_RECV) || \ + ((x) == ALD_PIS_UART3_RESERVE0) || \ + ((x) == ALD_PIS_UART3_RESERVE1) || \ + ((x) == ALD_PIS_UART3_RESERVE2) || \ + ((x) == ALD_PIS_UART3_RTSOUT) || \ + ((x) == ALD_PIS_UART3_TXOUT) || \ + ((x) == ALD_PIS_UART3_SYN_SEND) || \ + ((x) == ALD_PIS_UART3_SYN_RECV) || \ + ((x) == ALD_PIS_UART4_RESERVE0) || \ + ((x) == ALD_PIS_UART4_RESERVE1) || \ + ((x) == ALD_PIS_UART4_RESERVE2) || \ + ((x) == ALD_PIS_UART4_RTSOUT) || \ + ((x) == ALD_PIS_UART4_TXOUT) || \ + ((x) == ALD_PIS_UART4_SYN_SEND) || \ + ((x) == ALD_PIS_UART4_SYN_RECV) || \ + ((x) == ALD_PIS_SPI0_RECV) || \ + ((x) == ALD_PIS_SPI0_SEND) || \ + ((x) == ALD_PIS_SPI0_NE) || \ + ((x) == ALD_PIS_SPI1_RECV) || \ + ((x) == ALD_PIS_SPI1_SEND) || \ + ((x) == ALD_PIS_SPI1_NE) || \ + ((x) == ALD_PIS_I2C0_RECV) || \ + ((x) == ALD_PIS_I2C0_SEND) || \ + ((x) == ALD_PIS_I2C1_RECV) || \ + ((x) == ALD_PIS_I2C1_SEND) || \ + ((x) == ALD_PIS_TIMER0_UPDATA) || \ + ((x) == ALD_PIS_TIMER0_TRIG) || \ + ((x) == ALD_PIS_TIMER0_INPUT_1) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER0_INPUT_2) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER0_INPUT_3) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER0_INPUT_4) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER5_UPDATA) || \ + ((x) == ALD_PIS_TIMER5_TRIG) || \ + ((x) == ALD_PIS_TIMER5_INPUT_1) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER5_INPUT_2) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER5_INPUT_3) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER5_INPUT_4) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER6_UPDATA) || \ + ((x) == ALD_PIS_TIMER6_TRIG) || \ + ((x) == ALD_PIS_TIMER6_INPUT_1) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER6_INPUT_2) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER6_INPUT_3) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER6_INPUT_4) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER7_UPDATA) || \ + ((x) == ALD_PIS_TIMER7_TRIG) || \ + ((x) == ALD_PIS_TIMER7_INPUT_1) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER7_INPUT_2) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER7_INPUT_3) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER7_INPUT_4) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER4_UPDATA) || \ + ((x) == ALD_PIS_TIMER4_TRIG) || \ + ((x) == ALD_PIS_DMA_CH0) || \ + ((x) == ALD_PIS_DMA_CH1) || \ + ((x) == ALD_PIS_DMA_CH2) || \ + ((x) == ALD_PIS_DMA_CH3) || \ + ((x) == ALD_PIS_DMA_CH4) || \ + ((x) == ALD_PIS_DMA_CH5) || \ + ((x) == ALD_PIS_DMA_CH6) || \ + ((x) == ALD_PIS_DMA_ALL)) +#define IS_PIS_TRIG(x) (((x) == ALD_PIS_CH4_TIMER0_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER0_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER0_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER0_ITR3) || \ + ((x) == ALD_PIS_CH4_TIMER1_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER1_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER1_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER1_ITR3) || \ + ((x) == ALD_PIS_CH4_TIMER2_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER2_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER2_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER2_ITR3) || \ + ((x) == ALD_PIS_CH4_TIMER3_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER3_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER3_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER3_ITR3) || \ + ((x) == ALD_PIS_CH4_ADC0_NORMAL ) || \ + ((x) == ALD_PIS_CH5_ADC0_INSERT) || \ + ((x) == ALD_PIS_CH7_DMA_REQUEST) || \ + ((x) == ALD_PIS_CH7_UART4_RXD) || \ + ((x) == ALD_PIS_CH6_UART3_RXD) || \ + ((x) == ALD_PIS_CH5_UART2_RXD) || \ + ((x) == ALD_PIS_CH4_UART1_RXD) || \ + ((x) == ALD_PIS_CH3_UART0_RXD) || \ + ((x) == ALD_PIS_CH4_TIMER3_CH4IN) || \ + ((x) == ALD_PIS_CH4_TIMER2_CH4IN) || \ + ((x) == ALD_PIS_CH3_SPI1_CLK) || \ + ((x) == ALD_PIS_CH7_TIMER3_CH3IN) || \ + ((x) == ALD_PIS_CH7_TIMER2_CH3IN) || \ + ((x) == ALD_PIS_CH2_SPI1_RX) || \ + ((x) == ALD_PIS_CH6_TIMER3_CH2IN) || \ + ((x) == ALD_PIS_CH6_TIMER2_CH2IN) || \ + ((x) == ALD_PIS_CH1_SPI0_CLK) || \ + ((x) == ALD_PIS_CH5_TIMER3_CH1IN) || \ + ((x) == ALD_PIS_CH5_TIMER2_CH1IN) || \ + ((x) == ALD_PIS_CH0_SPI0_RX) || \ + ((x) == ALD_PIS_CH4_TIMER1_CH4IN) || \ + ((x) == ALD_PIS_CH4_TIMER0_CH4IN) || \ + ((x) == ALD_PIS_CH3_TIMER1_CH3IN) || \ + ((x) == ALD_PIS_CH3_TIMER0_CH3IN) || \ + ((x) == ALD_PIS_CH2_TIMER1_CH2IN) || \ + ((x) == ALD_PIS_CH2_TIMER0_CH2IN) || \ + ((x) == ALD_PIS_CH1_TIMER1_CH1IN) || \ + ((x) == ALD_PIS_CH1_TIMER0_CH1IN) || \ + ((x) == ALD_PIS_CH0_TIMER0_BRKIN) || \ + ((x) == ALD_PIS_TRIG_RESERVE) || \ + ((x) <= 0x7U)) +#define IS_PIS_CLOCK(x) (((x) == ALD_PIS_CLK_PCLK) || \ + ((x) == ALD_PIS_CLK_HCLK) || \ + ((x) == ALD_PIS_CLK_RESERVE)) +#define IS_PIS_SIGNAL_MODE(x) (((x) == ALD_PIS_OUT_LEVEL) || \ + ((x) == ALD_PIS_OUT_PULSE)) +#define IS_PIS_EDGE(x) (((x) == ALD_PIS_EDGE_NONE) || \ + ((x) == ALD_PIS_EDGE_UP) || \ + ((x) == ALD_PIS_EDGE_DOWN) || \ + ((x) == ALD_PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == ALD_PIS_OUT_LEVEL) || \ + ((x) == ALD_PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == ALD_PIS_OUT_CH_0) || \ + ((x) == ALD_PIS_OUT_CH_1) || \ + ((x) == ALD_PIS_OUT_CH_2) || \ + ((x) == ALD_PIS_OUT_CH_3) || \ + ((x) == ALD_PIS_OUT_CH_4) || \ + ((x) == ALD_PIS_OUT_CH_5) || \ + ((x) == ALD_PIS_OUT_CH_6) || \ + ((x) == ALD_PIS_OUT_CH_7)) +#define IS_PIS_MODU_TARGET(x) (((x) == ALD_PIS_UART0_TX) || \ + ((x) == ALD_PIS_UART1_TX) || \ + ((x) == ALD_PIS_UART2_TX) || \ + ((x) == ALD_PIS_UART3_TX) || \ + ((x) == ALD_PIS_UART4_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == ALD_PIS_LOW_LEVEL) || \ + ((x) == ALD_PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == ALD_PIS_SRC_NONE) || \ + ((x) == ALD_PIS_SRC_TIMER0) || \ + ((x) == ALD_PIS_SRC_TIMER5) || \ + ((x) == ALD_PIS_SRC_TIMER6) || \ + ((x) == ALD_PIS_SRC_TIMER7) || \ + ((x) == ALD_PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == ALD_PIS_TIMER_CH1) || \ + ((x) == ALD_PIS_TIMER_CH2) || \ + ((x) == ALD_PIS_TIMER_CH3) || \ + ((x) == ALD_PIS_TIMER_CH4)) +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_pis_create(ald_pis_handle_t *hperh); +ald_status_t ald_pis_destroy(ald_pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_pis_output_start(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch); +ald_status_t ald_pis_output_stop(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +ald_pis_state_t ald_pis_get_state(ald_pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t ald_pis_modu_config(ald_pis_handle_t *hperh, ald_pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_PIS_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pmu.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pmu.h new file mode 100644 index 0000000000..e8566f8872 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_pmu.h @@ -0,0 +1,222 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.h + * @brief Header file of PMU module driver. + * + * @version V1.0 + * @date 08 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 08 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_PMU_H__ +#define __ALD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" +#include "ald_syscfg.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup PMU + * @{ + */ + +/** @defgroup PMU_Public_Macros PMU Public Macros + * @{ + */ +#define ALD_PMU_LPSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_LPSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_FLASH_STOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_FSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_FLASH_STOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_FSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_BGSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_BGSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_VROSCEN_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_VROSCEN_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_STPRTNEN_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define ALD_PMU_STPRTNEN_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define ALD_PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +/** + * @} + */ + + +/** @defgroup PMU_Public_Types PMU Public Types + * @{ + */ +/** + * @brief Low power mode + */ +typedef enum { + ALD_PMU_LP_STOP = 0x0U, /**< Stop */ +} ald_pmu_lp_mode_t; + +typedef enum { + ALD_PMU_SR_WUF = (1U << 0), /**< WakeUp status */ +} ald_pmu_status_t; + +/** + * @brief LVD voltage select + */ +typedef enum { + ALD_PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V */ + ALD_PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V */ + ALD_PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V */ + ALD_PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V */ + ALD_PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V */ + ALD_PMU_LVD_VOL_SEL_3_6 = 0x5U, /**< 3.6V */ + ALD_PMU_LVD_VOL_SEL_4_0 = 0x6U, /**< 4.0V */ + ALD_PMU_LVD_VOL_SEL_4_6 = 0x7U, /**< 4.6V */ +} ald_pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum { + ALD_PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + ALD_PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + ALD_PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + ALD_PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + ALD_PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ +} ald_pmu_lvd_trigger_mode_t; + +/** + * @} + */ + +/** + * @defgroup PMU_Private_Macros PMU Private Macros + * @{ + */ +#define IS_PMU_LP_MODE(x) (((x) == ALD_PMU_LP_STOP)) +#define IS_PMU_STATUS(x) (((x) == ALD_PMU_SR_WUF)) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == ALD_PMU_LVD_VOL_SEL_2_2) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_2_4) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_2_6) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_2_8) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_3_0) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_3_6) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_4_0) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_4_6)) +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == ALD_PMU_LVD_TRIGGER_RISING_EDGE) || \ + ((x) == ALD_PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == ALD_PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == ALD_PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == ALD_PMU_LVD_TRIGGER_RISING_FALLING)) +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions + * @{ + */ +void ald_pmu_sleep_enter(void); +void ald_pmu_stop_enter(void); + +flag_status_t ald_pmu_get_status(ald_pmu_status_t sr); +void ald_pmu_clear_status(ald_pmu_status_t sr); +/** + * @} + */ +/** @addtogroup PMU_Public_Functions_Group2 + * @{ + */ +/* LVD configure */ +void ald_pmu_lvd_config(ald_pmu_lvd_voltage_sel_t sel, ald_pmu_lvd_trigger_mode_t mode, type_func_t state); +void ald_lvd_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_PMU_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_rmu.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_rmu.h new file mode 100644 index 0000000000..699cabf61b --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_rmu.h @@ -0,0 +1,211 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.h + * @brief Header file of RMU module driver. + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_RMU_H__ +#define __ALD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup RMU + * @{ + */ + +/** @defgroup RMU_Public_Types RMU Public Types + * @{ + */ +/** + * @brief RMU BOR fliter + */ +typedef enum { + ALD_RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + ALD_RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + ALD_RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + ALD_RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + ALD_RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + ALD_RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + ALD_RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ +} ald_rmu_bor_filter_t; + +/** + * @brief RMU reset status + */ +typedef enum { + ALD_RMU_RST_POR = (1U << 0), /**< POR */ + ALD_RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + ALD_RMU_RST_BOR = (1U << 2), /**< BOR */ + ALD_RMU_RST_NMRST = (1U << 3), /**< NMRST */ + ALD_RMU_RST_IWDT = (1U << 4), /**< IWDT */ + ALD_RMU_RST_WWDT = (1U << 5), /**< WWDT */ + ALD_RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + ALD_RMU_RST_CHIP = (1U << 7), /**< CHIP */ + ALD_RMU_RST_MCU = (1U << 8), /**< MCU */ + ALD_RMU_RST_CPU = (1U << 9), /**< CPU */ + ALD_RMU_RST_CFG = (1U << 10), /**< CFG */ + ALD_RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + ALD_RMU_RST_ALL = (0xFFFFFU), /**< ALL */ +} ald_rmu_state_t; + +/** + * @brief RMU periperal select bit + */ +typedef enum { + ALD_RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + ALD_RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + ALD_RMU_PERH_DMA = (1U << 2), /**< AHB1: DMA */ + ALD_RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + ALD_RMU_PERH_USB = (1U << 6), /**< AHB1: USB */ + ALD_RMU_PERH_CSU = (1U << 7), /**< AHB1: CSU */ + + ALD_RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + ALD_RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + + ALD_RMU_PERH_AD16C4T = (1U << 0) | (1U << 28), /**< APB: AD16C4T */ + ALD_RMU_PERH_BS16T0 = (1U << 1) | (1U << 28), /**< APB: BS16T0 */ + ALD_RMU_PERH_GP16C4T0 = (1U << 2) | (1U << 28), /**< APB: GP16C4T0 */ + ALD_RMU_PERH_GP16C4T1 = (1U << 3) | (1U << 28), /**< APB: GP16C4T1 */ + ALD_RMU_PERH_GP16C4T2 = (1U << 4) | (1U << 28), /**< APB: GP16C4T2 */ + ALD_RMU_PERH_EUART0 = (1U << 8) | (1U << 28), /**< APB: EUART0 */ + ALD_RMU_PERH_EUART1 = (1U << 9) | (1U << 28), /**< APB: EUART1 */ + ALD_RMU_PERH_CUART0 = (1U << 12) | (1U << 28), /**< APB: CUART0 */ + ALD_RMU_PERH_CUART1 = (1U << 13) | (1U << 28), /**< APB: CUART1 */ + ALD_RMU_PERH_CUART2 = (1U << 14) | (1U << 28), /**< APB: CUART2 */ + ALD_RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB: SPI0 */ + ALD_RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB: SPI1 */ + ALD_RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB: I2C0 */ + ALD_RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB: I2C1 */ + ALD_RMU_PERH_WWDT = (1U << 22) | (1U << 28), /**< APB: WWDT */ + ALD_RMU_PERH_IWDT = (1U << 23) | (1U << 28), /**< APB: IWDT */ + ALD_RMU_PERH_DBGCON = (1U << 24) | (1U << 28), /**< APB: DBGCON */ + ALD_RMU_PERH_ADC = (1U << 25) | (1U << 28), /**< APB: ADC */ +} ald_rmu_peripheral_t; +/** + * @} + */ + +/** + * @defgroup RMU_Private_Macros RMU Private Macros + * @{ + */ +#define IS_RMU_BORFLT(x) (((x) == ALD_RMU_BORFLT_1) || \ + ((x) == ALD_RMU_BORFLT_2) || \ + ((x) == ALD_RMU_BORFLT_3) || \ + ((x) == ALD_RMU_BORFLT_4) || \ + ((x) == ALD_RMU_BORFLT_5) || \ + ((x) == ALD_RMU_BORFLT_6) || \ + ((x) == ALD_RMU_BORFLT_7)) +#define IS_RMU_STATE(x) (((x) == ALD_RMU_RST_POR) || \ + ((x) == ALD_RMU_RST_WAKEUP) || \ + ((x) == ALD_RMU_RST_BOR) || \ + ((x) == ALD_RMU_RST_NMRST) || \ + ((x) == ALD_RMU_RST_IWDT) || \ + ((x) == ALD_RMU_RST_WWDT) || \ + ((x) == ALD_RMU_RST_LOCKUP) || \ + ((x) == ALD_RMU_RST_CHIP) || \ + ((x) == ALD_RMU_RST_MCU) || \ + ((x) == ALD_RMU_RST_CPU) || \ + ((x) == ALD_RMU_RST_CFG) || \ + ((x) == ALD_RMU_RST_CFGERR) || \ + ((x) == ALD_RMU_RST_ALL)) +#define IS_RMU_STATE_CLEAR(x) (((x) == ALD_RMU_RST_POR) || \ + ((x) == ALD_RMU_RST_WAKEUP) || \ + ((x) == ALD_RMU_RST_BOR) || \ + ((x) == ALD_RMU_RST_NMRST) || \ + ((x) == ALD_RMU_RST_IWDT) || \ + ((x) == ALD_RMU_RST_WWDT) || \ + ((x) == ALD_RMU_RST_LOCKUP) || \ + ((x) == ALD_RMU_RST_CHIP) || \ + ((x) == ALD_RMU_RST_MCU) || \ + ((x) == ALD_RMU_RST_CPU) || \ + ((x) == ALD_RMU_RST_CFG) || \ + ((x) == ALD_RMU_RST_ALL)) +#define IS_RMU_PERH(x) (((x) == ALD_RMU_PERH_GPIO) || \ + ((x) == ALD_RMU_PERH_CRC) || \ + ((x) == ALD_RMU_PERH_DMA) || \ + ((x) == ALD_RMU_PERH_PIS) || \ + ((x) == ALD_RMU_PERH_USB) || \ + ((x) == ALD_RMU_PERH_CSU) || \ + ((x) == ALD_RMU_PERH_CHIP) || \ + ((x) == ALD_RMU_PERH_CPU) || \ + ((x) == ALD_RMU_PERH_AD16C4T) || \ + ((x) == ALD_RMU_PERH_BS16T0) || \ + ((x) == ALD_RMU_PERH_GP16C4T0) || \ + ((x) == ALD_RMU_PERH_GP16C4T1) || \ + ((x) == ALD_RMU_PERH_GP16C4T2) || \ + ((x) == ALD_RMU_PERH_EUART0) || \ + ((x) == ALD_RMU_PERH_EUART1) || \ + ((x) == ALD_RMU_PERH_CUART0) || \ + ((x) == ALD_RMU_PERH_CUART1) || \ + ((x) == ALD_RMU_PERH_CUART2) || \ + ((x) == ALD_RMU_PERH_SPI0) || \ + ((x) == ALD_RMU_PERH_SPI1) || \ + ((x) == ALD_RMU_PERH_I2C0) || \ + ((x) == ALD_RMU_PERH_I2C1) || \ + ((x) == ALD_RMU_PERH_WWDT) || \ + ((x) == ALD_RMU_PERH_IWDT) || \ + ((x) == ALD_RMU_PERH_DBGCON) || \ + ((x) == ALD_RMU_PERH_ADC)) +/** + * @} + */ + +/** @addtogroup RMU_Public_Functions + * @{ + */ +void ald_rmu_bor_config(ald_rmu_bor_filter_t flt); +uint32_t ald_rmu_get_reset_status(ald_rmu_state_t state); +void ald_rmu_clear_reset_status(ald_rmu_state_t state); +void ald_rmu_reset_periperal(ald_rmu_peripheral_t perh); +void ald_rmu_reset_system(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_RMU_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_spi.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_spi.h new file mode 100644 index 0000000000..980c68fc66 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_spi.h @@ -0,0 +1,452 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_dma.h" +#include "ald_syscfg.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum { + ALD_SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + ALD_SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ +} ald_spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum { + ALD_SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + ALD_SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ +} ald_spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum { + ALD_SPI_MODE_SLAVER = 0U, /**< Slave mode */ + ALD_SPI_MODE_MASTER = 1U, /**< Master mode */ +} ald_spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum { + ALD_SPI_BAUD_2 = 0U, /**< fpclk/2 */ + ALD_SPI_BAUD_4 = 1U, /**< fpclk/4 */ + ALD_SPI_BAUD_8 = 2U, /**< fpclk/8 */ + ALD_SPI_BAUD_16 = 3U, /**< fpclk/16 */ + ALD_SPI_BAUD_32 = 4U, /**< fpclk/32 */ + ALD_SPI_BAUD_64 = 5U, /**< fpclk/64 */ + ALD_SPI_BAUD_128 = 6U, /**< fpclk/128 */ + ALD_SPI_BAUD_256 = 7U, /**< fpclk/256 */ +} ald_spi_baud_t; + +/** + * @brief frame format + */ +typedef enum { + ALD_SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + ALD_SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ +} ald_spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum { + ALD_SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + ALD_SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ +} ald_spi_datasize_t; + +/** + * @brief SPI error status + */ +typedef enum { + ALD_SPI_ERROR_NONE = 0U, /**< none */ + ALD_SPI_ERROR_MODF = 1U, /**< mode fault */ + ALD_SPI_ERROR_CRC = 2U, /**< crc error */ + ALD_SPI_ERROR_FRE = 4U, /**< frame error */ + ALD_SPI_ERROR_RXOV = 8U, /**< receive over error */ + ALD_SPI_ERROR_TXOV = 0x10U, /**< dma error */ + ALD_SPI_ERROR_FLAG = 0x20U, /**< interrupt flag error */ +} ald_spi_error_t; + +/** + * @brief interrupt control + */ +typedef enum { + ALD_SPI_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + ALD_SPI_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + ALD_SPI_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + ALD_SPI_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */ + ALD_SPI_IT_RXNE = (1U << 8), /**< Receive fifo not empty interrupt */ + ALD_SPI_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + ALD_SPI_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + ALD_SPI_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + ALD_SPI_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + ALD_SPI_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + ALD_SPI_IT_MODF = (1U << 17), /**< Mode error interrupt */ + ALD_SPI_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} ald_spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum { + ALD_SPI_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + ALD_SPI_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + ALD_SPI_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + ALD_SPI_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */ + ALD_SPI_IF_RXNE = (1U << 8), /**< Receive fifo not empty interrupt flag */ + ALD_SPI_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + ALD_SPI_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + ALD_SPI_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + ALD_SPI_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + ALD_SPI_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */ + ALD_SPI_IF_MODF = (1U << 17), /**< Mode error interrupt flag */ + ALD_SPI_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} ald_spi_flag_t; + +/** + * @brief SPI state structures definition + */ +typedef enum { + ALD_SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + ALD_SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + ALD_SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + ALD_SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + ALD_SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_SPI_STATE_ERROR = 0x04U, /**< Error */ +} ald_spi_state_t; + +/** + * @brief SPI direction definition + */ +typedef enum { + ALD_SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + ALD_SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + ALD_SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + ALD_SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ +} ald_spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum { + ALD_SPI_DMA_REQ_TX = 0U, /**< TX dma request */ + ALD_SPI_DMA_REQ_RX = 1U, /**< RX dma request */ +} ald_spi_dma_req_t; + +/** + * @brief SPI crc length definition + */ +typedef enum { + ALD_SPI_FRAME_MOTOROLA = 0U, /**< SPI motorola mode */ + ALD_SPI_FRAME_TI = 1U, /**< SPI TI mode */ +} ald_spi_frame_t; + +/** + * @brief SPI status definition + */ +typedef enum { + ALD_SPI_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + ALD_SPI_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + ALD_SPI_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + ALD_SPI_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + ALD_SPI_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */ + ALD_SPI_STATUS_RXNE = (1U << 8), /**< Receive fifo not empty status */ + ALD_SPI_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + ALD_SPI_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + ALD_SPI_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + ALD_SPI_STATUS_RXTH = (1U << 12), /**< Receive fifo under threshold status */ + ALD_SPI_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} ald_spi_status_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum { + ALD_SPI_SR_TXE = 0U, /**< SR.TXE set */ + ALD_SPI_SR_RXNE = 1U, /**< SR.RXTH set */ + ALD_SPI_SR_TXE_RXNE = 2U, /**< SR.TXE and SR.RXNE set */ +} ald_spi_sr_status_t; + + +/** + * @brief SPI init structure definition + */ +typedef struct { + ald_spi_mode_t mode; /**< SPI mode */ + ald_spi_direction_t dir; /**< SPI direction */ + ald_spi_datasize_t data_size; /**< SPI data size */ + ald_spi_baud_t baud; /**< SPI baudrate prescaler */ + ald_spi_cpha_t phase; /**< SPI clock phase */ + ald_spi_cpol_t polarity; /**< SPI clock polarity */ + ald_spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + ald_spi_frame_t frame; /**< SPI frame format */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} ald_spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct ald_spi_handle_s { + SPI_I2S_TypeDef *perh; /**< SPI registers base address */ + ald_spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ + + ald_dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + ald_dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct ald_spi_handle_s *arg); /**< error callback */ +} ald_spi_handle_t; +/** + * @} + */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define ALD_SPI_RESET_HANDLE_STATE(x) ((x)->state = ALD_SPI_STATE_RESET) +#define ALD_SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define ALD_SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define ALD_SPI_CRC_RESET(x) \ +do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ +} while (0) +#define ALD_SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define ALD_SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define ALD_SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define ALD_SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define ALD_SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define ALD_SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define ALD_SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define ALD_SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define ALD_SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define ALD_SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1)) +#define IS_SPI_CPHA(x) (((x) == ALD_SPI_CPHA_FIRST) || \ + ((x) == ALD_SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == ALD_SPI_CPOL_LOW) || \ + ((x) == ALD_SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == ALD_SPI_MODE_SLAVER) || \ + ((x) == ALD_SPI_MODE_MASTER)) +#define IS_SPI_FIRBIT(x) (((x) == ALD_SPI_FIRSTBIT_MSB) || \ + ((x) == ALD_SPI_FIRSTBIT_LSB)) +#define IS_SPI_BAUD(x) (((x) == ALD_SPI_BAUD_2) || \ + ((x) == ALD_SPI_BAUD_4) || \ + ((x) == ALD_SPI_BAUD_8) || \ + ((x) == ALD_SPI_BAUD_16) || \ + ((x) == ALD_SPI_BAUD_32) || \ + ((x) == ALD_SPI_BAUD_64) || \ + ((x) == ALD_SPI_BAUD_128) || \ + ((x) == ALD_SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == ALD_SPI_DATA_SIZE_8) || \ + ((x) == ALD_SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == ALD_SPI_BID_RX) || \ + ((x) == ALD_SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == ALD_SPI_BIDMODE_DUAL) || \ + ((x) == ALD_SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == ALD_SPI_DIRECTION_2LINES) || \ + ((x) == ALD_SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == ALD_SPI_DIRECTION_1LINE) || \ + ((x) == ALD_SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == ALD_SPI_DMA_REQ_TX) || \ + ((x) == ALD_SPI_DMA_REQ_RX)) +#define IS_SPI_STATUS(x) (((x) == ALD_SPI_STATUS_TXE) || \ + ((x) == ALD_SPI_STATUS_TXF) || \ + ((x) == ALD_SPI_STATUS_TXOV) || \ + ((x) == ALD_SPI_STATUS_TXUD) || \ + ((x) == ALD_SPI_STATUS_TXTH) || \ + ((x) == ALD_SPI_STATUS_RXNE) || \ + ((x) == ALD_SPI_STATUS_RXF) || \ + ((x) == ALD_SPI_STATUS_RXOV) || \ + ((x) == ALD_SPI_STATUS_RXUD) || \ + ((x) == ALD_SPI_STATUS_RXTH) || \ + ((x) == ALD_SPI_STATUS_BUSY)) +#define IS_SPI_IT(x) (((x) == ALD_SPI_IT_TXE) || \ + ((x) == ALD_SPI_IT_TXOV) || \ + ((x) == ALD_SPI_IT_TXUD) || \ + ((x) == ALD_SPI_IT_TXTH) || \ + ((x) == ALD_SPI_IT_RXNE) || \ + ((x) == ALD_SPI_IT_RXF) || \ + ((x) == ALD_SPI_IT_RXOV) || \ + ((x) == ALD_SPI_IT_RXUD) || \ + ((x) == ALD_SPI_IT_RXTH) || \ + ((x) == ALD_SPI_IT_CRCERR) || \ + ((x) == ALD_SPI_IT_MODF) || \ + ((x) == ALD_SPI_IT_FRE)) +#define IS_SPI_IF(x) (((x) == ALD_SPI_IF_TXE) || \ + ((x) == ALD_SPI_IF_TXOV) || \ + ((x) == ALD_SPI_IF_TXUD) || \ + ((x) == ALD_SPI_IF_TXTH) || \ + ((x) == ALD_SPI_IF_RXNE) || \ + ((x) == ALD_SPI_IF_RXF) || \ + ((x) == ALD_SPI_IF_RXOV) || \ + ((x) == ALD_SPI_IF_RXUD) || \ + ((x) == ALD_SPI_IF_RXTH) || \ + ((x) == ALD_SPI_IF_CRCERR) || \ + ((x) == ALD_SPI_IF_MODF) || \ + ((x) == ALD_SPI_IF_FRE)) +#define IS_SPI_FRAME(x) (((x) == ALD_SPI_FRAME_MOTOROLA) || \ + ((x) == ALD_SPI_FRAME_TI) ) +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_spi_init(ald_spi_handle_t *hperh); +void ald_spi_reset(ald_spi_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t ald_spi_send_byte_fast(ald_spi_handle_t *hperh, uint8_t data); +int32_t ald_spi_send_byte_fast_1line(ald_spi_handle_t *hperh, uint8_t data); +uint8_t ald_spi_recv_byte_fast(ald_spi_handle_t *hperh, int *status); +ald_status_t ald_spi_send_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_send_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_spi_send(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_recv(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_recv(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_recv_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_send_recv_by_it(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); + +ald_status_t ald_spi_send_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_send_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_spi_dma_pause(ald_spi_handle_t *hperh); +ald_status_t ald_spi_dma_resume(ald_spi_handle_t *hperh); +ald_status_t ald_spi_dma_stop(ald_spi_handle_t *hperh); + +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +void ald_spi_irq_handler(ald_spi_handle_t *hperh); +void ald_spi_interrupt_config(ald_spi_handle_t *hperh, ald_spi_it_t it, type_func_t state); +void ald_spi_speed_config(ald_spi_handle_t *hperh, ald_spi_baud_t speed); +void ald_spi_dma_req_config(ald_spi_handle_t *hperh, ald_spi_dma_req_t req, type_func_t state); +it_status_t ald_spi_get_it_status(ald_spi_handle_t *hperh, ald_spi_it_t it); +flag_status_t spi_get_status(ald_spi_handle_t *hperh, ald_spi_status_t status); +flag_status_t ald_spi_get_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag); +void ald_spi_clear_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group5 + * @{ + */ +ald_spi_state_t ald_spi_get_state(ald_spi_handle_t *hperh); +uint32_t ald_spi_get_error(ald_spi_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_SPI_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_syscfg.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_syscfg.h new file mode 100644 index 0000000000..8446f18a1b --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_syscfg.h @@ -0,0 +1,83 @@ +/** + ********************************************************************************* + * + * @file ald_syscfg.h + * @brief SYSCFG module driver. + * + * @version V1.0 + * @date 31 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 31 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SYSCFG_H__ +#define __ALD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" + + +/** @addtogroup ALD + * @{ + */ + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG module driver + * @{ + */ + +/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) +#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +/** + * @brief PIS IO Select + */ +typedef enum { + ALD_SYSCFG_PISIOCFG_PA = 0x0U, + ALD_SYSCFG_PISIOCFG_PB = 0x1U, + ALD_SYSCFG_PISIOCFG_PC = 0x2U, + ALD_SYSCFG_PISIOCFG_PD = 0x3U, +} ald_syscfg_pisiocfg_t; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_SYSCFG_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_timer.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_timer.h new file mode 100644 index 0000000000..3ed7c2e24d --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_timer.h @@ -0,0 +1,1115 @@ +/** + ********************************************************************************* + * + * @file ald_timer.h + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_TIMER_H__ +#define __ALD_TIMER_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" +#include "ald_cmu.h" +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types TIMER Public Types + * @{ + */ + +/** + * @brief TIMER counter mode + */ +typedef enum { + ALD_TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + ALD_TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + ALD_TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + ALD_TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + ALD_TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ +} ald_timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum { + ALD_TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + ALD_TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + ALD_TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ +} ald_timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum { + ALD_TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + ALD_TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + ALD_TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + ALD_TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + ALD_TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + ALD_TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + ALD_TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + ALD_TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ +} ald_timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum { + ALD_TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + ALD_TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ +} ald_timer_oc_polarity_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum { + ALD_TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + ALD_TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ +} ald_timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum { + ALD_TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + ALD_TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ +} ald_timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum { + ALD_TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + ALD_TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ +} ald_timer_ocn_idle_t; + +/** + * @brief TIMER channel + */ +typedef enum { + ALD_TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + ALD_TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + ALD_TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + ALD_TIMER_CHANNEL_4 = 3U, /**< Channel 4 */ + ALD_TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ +} ald_timer_channel_t; + +/** + * @brief TIMER one pulse mode + */ +typedef enum { + ALD_TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ + ALD_TIMER_OP_MODE_SINGLE = 1U, /**< single */ +} ald_timer_op_mode_t; + +/** + * @brief TIMER one pulse output channel + */ +typedef enum { + ALD_TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ + ALD_TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ +} ald_timer_op_output_channel_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct { + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + ald_timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + ald_timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} ald_timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct { + ald_timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + ald_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + ald_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + ald_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + ald_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} ald_timer_oc_init_t; + +/** + * @brief State structures definition + */ +typedef enum { + ALD_TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + ALD_TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + ALD_TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ + ALD_TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ +} ald_timer_state_t; + +/** + * @brief Active channel structures definition + */ +typedef enum { + ALD_TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ + ALD_TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ + ALD_TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ + ALD_TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ + ALD_TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ +} ald_timer_active_channel_t; + +/** + * @brief TIMER time base handle structure definition + */ +typedef struct ald_timer_handle_s { + TIMER_TypeDef *perh; /**< Register base address */ + ald_timer_base_init_t init; /**< TIMER Time Base required parameters */ + ald_timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + ald_timer_state_t state; /**< TIMER operation state */ + + ald_dma_handle_t hdma1; /**< Timer DMA handle parameters */ + ald_dma_handle_t hdma2; + + void (*period_elapse_cbk)(struct ald_timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct ald_timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct ald_timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct ald_timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct ald_timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct ald_timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct ald_timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct ald_timer_handle_s *arg); /**< Error callback */ +} ald_timer_handle_t; + + +/** + * @brief TIMER encoder mode + */ +typedef enum { + ALD_TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + ALD_TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + ALD_TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ +} ald_timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum { + ALD_TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + ALD_TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ +} ald_timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum { + ALD_TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + ALD_TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + ALD_TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ +} ald_timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum { + ALD_TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + ALD_TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + ALD_TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + ALD_TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ +} ald_timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct { + ald_timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + ald_timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t ic1_sel; /**< Specifies the input */ + ald_timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + ald_timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t ic2_sel; /**< Specifies the input */ + ald_timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} ald_timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct { + ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t sel; /**< Specifies the input */ + ald_timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} ald_timer_ic_init_t; + +/** + * @brief TIMER one pulse mode configuration structure definition + */ +typedef struct { + ald_timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + ald_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + ald_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + ald_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + ald_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ +} ald_timer_one_pulse_init_t; + +/** @brief TIMER clear input source + */ +typedef enum { + ALD_TIMER_INPUT_NONE = 0U, /**< Clear input none */ + ALD_TIMER_INPUT_ETR = 1U, /**< Clear input etr */ +} ald_timer_clear_input_source_t; + +/** @brief TIMER clear input polarity + */ +typedef enum { + ALD_TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ + ALD_TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ +} ald_timer_clear_input_polarity_t; + +/** @brief TIMER clear input polarity + */ +typedef enum { + ALD_TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ + ALD_TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ + ALD_TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ + ALD_TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ +} ald_timer_etr_psc_t; + +/** @brief TIMER CHnREF Clear Select + */ +typedef enum { + ALD_TIMER_CHNREF_CLR_CMP_IN = 0U, /**< Comparator CMP_IN */ + ALD_TIMER_CHNREF_CLR_ETF = 1U, /**< External Trigger Signal ETF */ +} ald_timer_chnref_clr_sel_t; + +/** @brief TIMER clear input configuration handle structure definition + */ +typedef struct { + type_func_t state; /**< TIMER clear Input state */ + ald_timer_clear_input_source_t source; /**< TIMER clear Input sources */ + ald_timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + ald_timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + ald_timer_chnref_clr_sel_t clrsel; /**state = TIMER_STATE_RESET) + +/** + * @brief Enable the TIMER peripheral. + */ +#define ALD_TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) + +/** + * @brief Enable the TIMER main output. + */ +#define ALD_TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) + +/** + * @brief Disable the TIMER peripheral. + */ +#define ALD_TIMER_DISABLE(hperh) \ +do { \ + if ((((hperh)->perh->CCEP & ALD_CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & ALD_CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ +} while (0) + +/** + * @brief Disable the TIMER main output. + * @note The Main Output Enable of a timer instance is disabled only if + * all the CCx and CCxN channels have been disabled + */ +#define ALD_TIMER_MOE_DISABLE(hperh) \ +do { \ + if ((((hperh)->perh->CCEP & ALD_CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & ALD_CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ +} while (0) + +/** + * @brief Sets the TIMER autoreload register value on runtime without calling + * another time any Init function. + */ +#define ALD_TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ +do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ +} while (0) + +/** + * @brief Gets the TIMER autoreload register value on runtime + */ +#define ALD_TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) + +/** + * @brief Gets the TIMER count register value on runtime + */ +#define ALD_TIMER_GET_CNT(handle) ((handle)->perh->COUNT) + +/** + * @brief Gets the TIMER count direction value on runtime + */ +#define ALD_TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) + +/** + * @brief CCx DMA request sent when CCx event occurs + */ +#define ALD_TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief CCx DMA request sent when update event occurs + */ +#define ALD_TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief Enable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define ALD_TIMER_CCx_ENABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ +(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) + +/** + * @brief Disable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define ALD_TIMER_CCx_DISABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ +(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) + +/** + * @brief Enable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define ALD_TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) + +/** + * @brief Disable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define ALD_TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +/** + * @} + */ + +/** @defgroup TIMER_Private_Macros TIMER Private Macros + * @{ + */ + +#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == BS16T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define IS_TIMER_BREAK_INSTANCE(x) ((x) == AD16C4T) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T2) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T0) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T1) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T2) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) (((x) == AD16C4T) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) ((x) == AD16C4T) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#define IS_TIMER_COUNTER_MODE(x) (((x) == ALD_TIMER_CNT_MODE_UP) || \ + ((x) == ALD_TIMER_CNT_MODE_DOWN) || \ + ((x) == ALD_TIMER_CNT_MODE_CENTER1) || \ + ((x) == ALD_TIMER_CNT_MODE_CENTER2) || \ + ((x) == ALD_TIMER_CNT_MODE_CENTER3)) +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == ALD_TIMER_CLOCK_DIV1) || \ + ((x) == ALD_TIMER_CLOCK_DIV2) || \ + ((x) == ALD_TIMER_CLOCK_DIV4)) +#define IS_TIMER_PWM_MODE(x) (((x) == ALD_TIMER_OC_MODE_PWM1) || \ + ((x) == ALD_TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_MODE(x) (((x) == ALD_TIMER_OC_MODE_TIMERING) || \ + ((x) == ALD_TIMER_OC_MODE_ACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_INACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_TOGGLE) || \ + ((x) == ALD_TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_PWM1) || \ + ((x) == ALD_TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_POLARITY(x) (((x) == ALD_TIMER_OC_POLARITY_HIGH) || \ + ((x) == ALD_TIMER_OC_POLARITY_LOW)) +#define IS_TIMER_OCN_POLARITY(x) (((x) == ALD_TIMER_OCN_POLARITY_HIGH) || \ + ((x) == ALD_TIMER_OCN_POLARITY_LOW)) +#define IS_TIMER_OCIDLE_STATE(x) (((x) == ALD_TIMER_OC_IDLE_RESET) || \ + ((x) == ALD_TIMER_OC_IDLE_SET)) +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == ALD_TIMER_OCN_IDLE_RESET) || \ + ((x) == ALD_TIMER_OCN_IDLE_SET)) +#define IS_TIMER_CHANNELS(x) (((x) == ALD_TIMER_CHANNEL_1) || \ + ((x) == ALD_TIMER_CHANNEL_2) || \ + ((x) == ALD_TIMER_CHANNEL_3) || \ + ((x) == ALD_TIMER_CHANNEL_4) || \ + ((x) == ALD_TIMER_CHANNEL_ALL)) +#define IS_TIMER_OP_MODE(x) (((x) == ALD_TIMER_OP_MODE_REPEAT) || \ + ((x) == ALD_TIMER_OP_MODE_SINGLE)) +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == ALD_TIMER_OP_OUTPUT_CHANNEL_1) || \ + ((x) == ALD_TIMER_OP_OUTPUT_CHANNEL_2)) +#define IS_TIMER_ENCODER_MODE(x) (((x) == ALD_TIMER_ENC_MODE_TI1) || \ + ((x) == ALD_TIMER_ENC_MODE_TI2) || \ + ((x) == ALD_TIMER_ENC_MODE_TI12)) +#define IS_TIMER_IC_POLARITY(x) (((x) == ALD_TIMER_IC_POLARITY_RISE) || \ + ((x) == ALD_TIMER_IC_POLARITY_FALL)) +#define IS_TIMER_IC_SELECT(x) (((x) == ALD_TIMER_IC_SEL_DIRECT) || \ + ((x) == ALD_TIMER_IC_SEL_INDIRECT) || \ + ((x) == ALD_TIMER_IC_SEL_TRC)) +#define IS_TIMER_IC_PSC(x) (((x) == ALD_TIMER_IC_PSC_DIV1) || \ + ((x) == ALD_TIMER_IC_PSC_DIV2) || \ + ((x) == ALD_TIMER_IC_PSC_DIV4) || \ + ((x) == ALD_TIMER_IC_PSC_DIV8)) +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == ALD_TIMER_INPUT_NONE) || \ + ((x) == ALD_TIMER_INPUT_ETR)) +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == ALD_TIMER_POLARITY_NO_INV) || \ + ((x) == ALD_TIMER_POLARITY_INV)) +#define IS_TIMER_ETR_PSC(x) (((x) == ALD_TIMER_ETR_PSC_DIV1) || \ + ((x) == ALD_TIMER_ETR_PSC_DIV2) || \ + ((x) == ALD_TIMER_ETR_PSC_DIV4) || \ + ((x) == ALD_TIMER_ETR_PSC_DIV8)) +#define IS_TIMER_CHNREF_CLEAR(X) (((X) == ALD_TIMER_CHNREF_CLR_CMP_IN) || \ + ((X) == ALD_TIMER_CHNREF_CLR_ETF)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == ALD_TIMER_SRC_ETRMODE2) || \ + ((x) == ALD_TIMER_SRC_INTER) || \ + ((x) == ALD_TIMER_SRC_ITR0) || \ + ((x) == ALD_TIMER_SRC_ITR1) || \ + ((x) == ALD_TIMER_SRC_ITR2) || \ + ((x) == ALD_TIMER_SRC_ITR3) || \ + ((x) == ALD_TIMER_SRC_TI1ED) || \ + ((x) == ALD_TIMER_SRC_TI1) || \ + ((x) == ALD_TIMER_SRC_TI2) || \ + ((x) == ALD_TIMER_SRC_ETRMODE1)) +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == ALD_TIMER_CLK_POLARITY_INV) || \ + ((x) == ALD_TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == ALD_TIMER_CLK_POLARITY_RISE) || \ + ((x) == ALD_TIMER_CLK_POLARITY_FALL) || \ + ((x) == ALD_TIMER_CLK_POLARITY_BOTH)) +#define IS_TIMER_SLAVE_MODE(x) (((x) == ALD_TIMER_MODE_DISABLE) || \ + ((x) == ALD_TIMER_MODE_ENC1) || \ + ((x) == ALD_TIMER_MODE_ENC2) || \ + ((x) == ALD_TIMER_MODE_ENC3) || \ + ((x) == ALD_TIMER_MODE_RESET) || \ + ((x) == ALD_TIMER_MODE_GATED) || \ + ((x) == ALD_TIMER_MODE_TRIG) || \ + ((x) == ALD_TIMER_MODE_EXTERNAL1)) +#define IS_TIMER_EVENT_SOURCE(x) (((x) == ALD_TIMER_SRC_UPDATE) || \ + ((x) == ALD_TIMER_SRC_CC1) || \ + ((x) == ALD_TIMER_SRC_CC2) || \ + ((x) == ALD_TIMER_SRC_CC3) || \ + ((x) == ALD_TIMER_SRC_CC4) || \ + ((x) == ALD_TIMER_SRC_COM) || \ + ((x) == ALD_TIMER_SRC_TRIG) || \ + ((x) == ALD_TIMER_SRC_BREAK)) +#define IS_TIMER_TS(x) (((x) == ALD_TIMER_TS_ITR0) || \ + ((x) == ALD_TIMER_TS_ITR1) || \ + ((x) == ALD_TIMER_TS_ITR2) || \ + ((x) == ALD_TIMER_TS_ITR3) || \ + ((x) == ALD_TIMER_TS_TI1F_ED) || \ + ((x) == ALD_TIMER_TS_TI1FP1) || \ + ((x) == ALD_TIMER_TS_TI2FP2) || \ + ((x) == ALD_TIMER_TS_ETRF)) +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == ALD_TIMER_LOCK_LEVEL_OFF) || \ + ((x) == ALD_TIMER_LOCK_LEVEL_1) || \ + ((x) == ALD_TIMER_LOCK_LEVEL_2) || \ + ((x) == ALD_TIMER_LOCK_LEVEL_3)) +#define IS_TIMER_BREAK_POLARITY(x) (((x) == ALD_TIMER_BREAK_POLARITY_LOW) || \ + ((x) == ALD_TIMER_BREAK_POLARITY_HIGH)) +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == ALD_TIMER_TRGO_RESET) || \ + ((x) == ALD_TIMER_TRGO_ENABLE) || \ + ((x) == ALD_TIMER_TRGO_UPDATE) || \ + ((x) == ALD_TIMER_TRGO_OC1) || \ + ((x) == ALD_TIMER_TRGO_OC1REF) || \ + ((x) == ALD_TIMER_TRGO_OC2REF) || \ + ((x) == ALD_TIMER_TRGO_OC3REF) || \ + ((x) == ALD_TIMER_TRGO_OC4REF)) +#define IS_TIMER_IT(x) (((x) == ALD_TIMER_IT_UPDATE) || \ + ((x) == ALD_TIMER_IT_CC1) || \ + ((x) == ALD_TIMER_IT_CC2) || \ + ((x) == ALD_TIMER_IT_CC3) || \ + ((x) == ALD_TIMER_IT_CC4) || \ + ((x) == ALD_TIMER_IT_COM) || \ + ((x) == ALD_TIMER_IT_TRIGGER) || \ + ((x) == ALD_TIMER_IT_BREAK)) +#define IS_TIMER_DMA_REQ(x) (((x) == ALD_TIMER_DMA_UPDATE) || \ + ((x) == ALD_TIMER_DMA_CC1) || \ + ((x) == ALD_TIMER_DMA_CC2) || \ + ((x) == ALD_TIMER_DMA_CC3) || \ + ((x) == ALD_TIMER_DMA_CC4) || \ + ((x) == ALD_TIMER_DMA_COM) || \ + ((x) == ALD_TIMER_DMA_TRIGGER)) +#define IS_TIMER_FLAG(x) (((x) == ALD_TIMER_FLAG_UPDATE) || \ + ((x) == ALD_TIMER_FLAG_CC1) || \ + ((x) == ALD_TIMER_FLAG_CC2) || \ + ((x) == ALD_TIMER_FLAG_CC3) || \ + ((x) == ALD_TIMER_FLAG_CC4) || \ + ((x) == ALD_TIMER_FLAG_COM) || \ + ((x) == ALD_TIMER_FLAG_TRIGGER) || \ + ((x) == ALD_TIMER_FLAG_BREAK) || \ + ((x) == ALD_TIMER_FLAG_CC1OF) || \ + ((x) == ALD_TIMER_FLAG_CC2OF) || \ + ((x) == ALD_TIMER_FLAG_CC3OF) || \ + ((x) == ALD_TIMER_FLAG_CC4OF)) +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions + * @{ + */ +/** @addtogroup TIMER_Public_Functions_Group1 + * @{ + */ +/* Time Base functions */ +ald_status_t ald_timer_base_init(ald_timer_handle_t *hperh); +void ald_timer_base_reset(ald_timer_handle_t *hperh); +void ald_timer_base_start(ald_timer_handle_t *hperh); +void ald_timer_base_stop(ald_timer_handle_t *hperh); +void ald_timer_base_start_by_it(ald_timer_handle_t *hperh); +void ald_timer_base_stop_by_it(ald_timer_handle_t *hperh); + +ald_status_t ald_timer_base_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_base_stop_by_dma(ald_timer_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions */ +ald_status_t ald_timer_oc_init(ald_timer_handle_t *hperh); +void ald_timer_oc_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_oc_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_oc_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_oc_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_oc_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_oc_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group3 + * @{ + */ +/* Timer PWM functions */ +ald_status_t ald_timer_pwm_init(ald_timer_handle_t *hperh); +void ald_timer_pwm_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_set_freq(ald_timer_handle_t *hperh, uint32_t freq); +void ald_timer_pwm_set_duty(ald_timer_handle_t *hperh, ald_timer_channel_t ch, uint16_t duty); +void ald_timer_pwm_set_input(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_pwm_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwm_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions */ +ald_status_t ald_timer_ic_init(ald_timer_handle_t *hperh); +void ald_timer_ic_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ic_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ic_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ic_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_ic_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ic_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions */ +ald_status_t ald_timer_one_pulse_init(ald_timer_handle_t *hperh, ald_timer_op_mode_t mode); +void ald_timer_one_pulse_start(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +void ald_timer_one_pulse_start_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group6 + * @{ + */ +/* Timer encoder functions */ +ald_status_t ald_timer_encoder_init(ald_timer_handle_t *hperh, ald_timer_encoder_init_t *config); +void ald_timer_encoder_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_encoder_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_encoder_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_encoder_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_encoder_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2); +void ald_timer_encoder_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group7 + * @{ + */ +/* Timer hall sensor functions */ +ald_status_t ald_timer_hall_sensor_init(ald_timer_handle_t *hperh, ald_timer_hall_sensor_init_t *config); +void ald_timer_hall_sensor_start(ald_timer_handle_t *hperh); +void ald_timer_hall_sensor_stop(ald_timer_handle_t *hperh); +void ald_timer_hall_sensor_start_by_it(ald_timer_handle_t *hperh); +void ald_timer_hall_sensor_stop_by_it(ald_timer_handle_t *hperh); + +ald_status_t ald_timer_hall_sensor_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_hall_sensor_stop_by_dma(ald_timer_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group8 + * @{ + */ +/* Timer complementary output compare functions */ +void ald_timer_ocn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ocn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ocn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ocn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_ocn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ocn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group9 + * @{ + */ +/* Timer complementary PWM functions */ +void ald_timer_pwmn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwmn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwmn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwmn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_pwmn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwmn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group10 + * @{ + */ +/* Timer complementary one pulse functions */ +void ald_timer_one_pulse_n_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_one_pulse_n_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_one_pulse_n_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_one_pulse_n_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group11 + * @{ + */ +/* Control functions */ +ald_status_t ald_timer_oc_config_channel(ald_timer_handle_t *hperh, ald_timer_oc_init_t* config, ald_timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(ald_timer_handle_t *hperh, ald_timer_ic_init_t* config, ald_timer_channel_t ch); +ald_status_t ald_timer_one_pulse_config_channel(ald_timer_handle_t *hperh, ald_timer_one_pulse_init_t *config, ald_timer_channel_t ch_out, ald_timer_channel_t ch_in); +ald_status_t ald_timer_config_oc_ref_clear(ald_timer_handle_t *hperh, ald_timer_clear_input_config_t *config, ald_timer_channel_t ch); +ald_status_t ald_timer_config_clock_source(ald_timer_handle_t *hperh, ald_timer_clock_config_t *config); +ald_status_t ald_timer_config_ti1_input(ald_timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t ald_timer_slave_config_sync(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); +ald_status_t ald_timer_slave_config_sync_by_it(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); +ald_status_t ald_timer_generate_event(ald_timer_handle_t *hperh, ald_timer_event_source_t event); +uint32_t ald_timer_read_capture_value(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_set_output_mode(ald_timer_handle_t *hperh, ald_timer_oc_mode_t mode, ald_timer_channel_t ch); +void ald_timer_com_change_config(ald_timer_handle_t *hperh, ald_timer_com_channel_config_t *config); +void ald_timer_com_event_config(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi); +void ald_timer_com_event_config_it(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi); +void ald_timer_break_dead_time_config(ald_timer_handle_t *hperh, ald_timer_break_dead_time_t *config); +void ald_timer_master_sync_config(ald_timer_handle_t *hperh, ald_timer_master_config_t *config); +void ald_timer_irq_handler(ald_timer_handle_t *hperh); +void ald_timer_dma_req_config(ald_timer_handle_t *hperh, ald_timer_dma_req_t req, type_func_t state); +void ald_timer_interrupt_config(ald_timer_handle_t *hperh, ald_timer_it_t it, type_func_t state); +it_status_t ald_timer_get_it_status(ald_timer_handle_t *hperh, ald_timer_it_t it); +flag_status_t ald_timer_get_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag); +void ald_timer_clear_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group12 + * @{ + */ +/* State functions */ +ald_timer_state_t ald_timer_get_state(ald_timer_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_TIMER_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_uart.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_uart.h new file mode 100644 index 0000000000..755a7ffbab --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_uart.h @@ -0,0 +1,503 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 22 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 22 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ald_cmu.h" +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define ALD_UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define ALD_UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define ALD_UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define ALD_UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define ALD_UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define ALD_UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define ALD_UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define ALD_UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define ALD_UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define ALD_UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define ALD_UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define ALD_UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define ALD_UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define ALD_UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define ALD_UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define ALD_UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define ALD_UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define ALD_UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define ALD_UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define ALD_UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define ALD_UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define ALD_UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define ALD_UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK)) +#define ALD_UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define ALD_UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +#define ALD_UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define ALD_UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define ALD_UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define ALD_UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define ALD_UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +#define ALD_UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +/** + * @} + */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum { + ALD_UART_WORD_LENGTH_8B = 0x0U, /**< 8-bits */ + ALD_UART_WORD_LENGTH_7B = 0x1U, /**< 7-bits */ + ALD_UART_WORD_LENGTH_6B = 0x2U, /**< 6-bits */ + ALD_UART_WORD_LENGTH_5B = 0x3U, /**< 5-bits */ +} ald_uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum { + ALD_UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + ALD_UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ + ALD_UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + ALD_UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ +} ald_uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum { + ALD_UART_PARITY_NONE = 0x0U, /**< Not parity */ + ALD_UART_PARITY_ODD = 0x1U, /**< Odd parity */ + ALD_UART_PARITY_EVEN = 0x3U, /**< Even parity */ +} ald_uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum { + ALD_UART_MODE_UART = 0x0U, /**< UART */ + ALD_UART_MODE_LIN = 0x1U, /**< LIN */ + ALD_UART_MODE_IrDA = 0x2U, /**< IrDA */ + ALD_UART_MODE_RS485 = 0x3U, /**< RS485 */ + ALD_UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ + ALD_UART_MODE_SCARD = 0x5U, /**< Smart card */ +} ald_uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum { + ALD_UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + ALD_UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ +} ald_uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum { + ALD_UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + ALD_UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + ALD_UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + ALD_UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + ALD_UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_UART_STATE_ERROR = 0x04U, /**< Error */ +} ald_uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum { + ALD_UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + ALD_UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + ALD_UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + ALD_UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + ALD_UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + ALD_UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ +} ald_uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct { + uint32_t baud; /**< Specifies the uart communication baud rate */ + ald_uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + ald_uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + ald_uart_parity_t parity; /**< Specifies the parity mode */ + ald_uart_mode_t mode; /**< Specifies uart mode */ + ald_uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} ald_uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct ald_uart_handle_s { + UART_TypeDef *perh; /**< UART registers base address */ + ald_uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ + + ald_dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + ald_dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_uart_state_t state; /**< UART communication state */ + ald_uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct ald_uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct ald_uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct ald_uart_handle_s *arg); /**< error callback */ +} ald_uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct { + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} ald_uart_rs485_config_t; + +/** + * @brief Smart_card Rx/Tx handle retry time + */ +typedef enum { + ALD_SCARD_RETRY_CNT0 = 0x0U, /**< retry time 0 */ + ALD_SCARD_RETRY_CNT1 = 0x1U, /**< retry time 1 */ + ALD_SCARD_RETRY_CNT2 = 0x2U, /**< retry time 2 */ + ALD_SCARD_RETRY_CNT3 = 0x3U, /**< retry time 3 */ + ALD_SCARD_RETRY_CNT4 = 0x4U, /**< retry time 4 */ + ALD_SCARD_RETRY_CNT5 = 0x5U, /**< retry time 5 */ + ALD_SCARD_RETRY_CNT6 = 0x6U, /**< retry time 6 */ + ALD_SCARD_RETRY_CNT7 = 0x7U, /**< retry time 7 */ +} ald_scard_retry_t; + +/** + * @brief UART Smart card configure structure definition + */ +typedef struct { + uint8_t block_len; /**< Specifies the data block length.*/ + uint8_t pt; /**< Specifies the protect time*/ + ald_scard_retry_t retry; /**< Specifies retry time.*/ + uint8_t clk_div; /**< Specifies the clock division.*/ + type_func_t clk_out; /**< Specifies the clock out */ +} ald_uart_scard_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum { + ALD_LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + ALD_LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ +} ald_uart_lin_break_len_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum { + ALD_UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + ALD_UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + ALD_UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ +} ald_uart_auto_baud_mode_t; + +/** + * @brief UART DMA Requests + */ +typedef enum { + ALD_UART_DMA_REQ_TX = 0x0U, /**< TX dma */ + ALD_UART_DMA_REQ_RX = 0x1U, /**< RX dma */ +} ald_uart_dma_req_t; + +/** + * @brief UART status types + */ +typedef enum { + ALD_UART_STATUS_PERR = (1U << 0), /**< Parity error */ + ALD_UART_STATUS_FERR = (1U << 1), /**< Framing error */ + ALD_UART_STATUS_BKERR = (1U << 2), /**< Break error */ + ALD_UART_STATUS_CTSSTA = (1U << 3), /**< Clear to send status */ + ALD_UART_STATUS_RSBUSY = (1U << 8), /**< Receive shif register busy */ + ALD_UART_STATUS_RFNEMPTY = (1U << 10), /**< Receive FIFO not empty */ + ALD_UART_STATUS_RFOERR = (1U << 12), /**< Reveive FIFO overrun error */ + ALD_UART_STATUS_RFUERR = (1U << 13), /**< Receive FIFO underrun error */ + ALD_UART_STATUS_TSBUSY = (1U << 14), /**< Transmit shit register busy */ + ALD_UART_STATUS_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + ALD_UART_STATUS_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} ald_uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum { + ALD_UART_IT_RXBERR = (1U << 0), /**< Receiver byte error */ + ALD_UART_IT_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + ALD_UART_IT_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + ALD_UART_IT_DCTS = (1U << 3), /**< Delta CTS status */ + ALD_UART_IT_RXTO = (1U << 4), /**< Receiver timeout */ + ALD_UART_IT_ADDRM = (1U << 5), /**< Addredd match */ + ALD_UART_IT_LINBK = (1U << 6), /**< Lin break detection */ + ALD_UART_IT_EOB = (1U << 7), /**< End of block */ + ALD_UART_IT_NOISE = (1U << 8), /**< Start bit noise detection */ + ALD_UART_IT_RFNEMPTY = (1U << 10), /**< Receive FIFO not empty */ + ALD_UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */ + ALD_UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + ALD_UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + ALD_UART_IT_TBC = (1U << 14), /**< Transmit shift register empty */ + ALD_UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + ALD_UART_IT_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} ald_uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum { + ALD_UART_IF_RXBERR = (1U << 0), /**< Receiver byte error */ + ALD_UART_IF_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + ALD_UART_IF_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + ALD_UART_IF_DCTS = (1U << 3), /**< Delta CTS status */ + ALD_UART_IF_RXTO = (1U << 4), /**< Receiver timeout */ + ALD_UART_IF_ADDRM = (1U << 5), /**< Addredd match */ + ALD_UART_IF_LINBK = (1U << 6), /**< Lin break detection */ + ALD_UART_IF_EOB = (1U << 7), /**< End of block */ + ALD_UART_IF_NOISE = (1U << 8), /**< Start bit noise detection */ + ALD_UART_IF_RFNEMPTY = (1U << 10), /**< Receive FIFO not empty */ + ALD_UART_IF_RFFULL = (1U << 11), /**< Receive FIFO full */ + ALD_UART_IF_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + ALD_UART_IF_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + ALD_UART_IF_TBC = (1U << 14), /**< Transmit shift register empty */ + ALD_UART_IF_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + ALD_UART_IF_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} ald_uart_flag_t; +/** + * @} + */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_ENHANCE(x)(((x) == EUART0) || \ + ((x) == EUART1)) +#define IS_UART_ALL(x) (((x) == EUART0) || \ + ((x) == EUART1) || \ + ((x) == CUART0) || \ + ((x) == CUART1) || \ + ((x) == CUART2)) +#define IS_UART_WORD_LENGTH(x) (((x) == ALD_UART_WORD_LENGTH_5B) || \ + ((x) == ALD_UART_WORD_LENGTH_6B) || \ + ((x) == ALD_UART_WORD_LENGTH_7B) || \ + ((x) == ALD_UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == ALD_UART_STOP_BITS_1) || \ + ((x) == ALD_UART_STOP_BITS_2) || \ + ((x) == ALD_UART_STOP_BITS_0_5) || \ + ((x) == ALD_UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == ALD_UART_PARITY_NONE) || \ + ((x) == ALD_UART_PARITY_ODD) || \ + ((x) == ALD_UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == ALD_UART_MODE_UART) || \ + ((x) == ALD_UART_MODE_LIN) || \ + ((x) == ALD_UART_MODE_IrDA) || \ + ((x) == ALD_UART_MODE_HDSEL) || \ + ((x) == ALD_UART_MODE_SCARD) || \ + ((x) == ALD_UART_MODE_RS485)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == ALD_UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == ALD_UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == ALD_LIN_BREAK_LEN_10B) || \ + ((x) == ALD_LIN_BREAK_LEN_11B)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == ALD_UART_ABRMOD_1_TO_0) || \ + ((x) == ALD_UART_ABRMOD_1) || \ + ((x) == ALD_UART_ABRMOD_0_TO_1)) +#define IS_UART_DMA_REQ(x) (((x) == ALD_UART_DMA_REQ_TX) || \ + ((x) == ALD_UART_DMA_REQ_RX)) +#define IS_UART_STATUS(x) (((x) == ALD_UART_STATUS_PERR) || \ + ((x) == ALD_UART_STATUS_FERR) || \ + ((x) == ALD_UART_STATUS_BKERR) || \ + ((x) == ALD_UART_STATUS_CTSSTA) || \ + ((x) == ALD_UART_STATUS_RSBUSY) || \ + ((x) == ALD_UART_STATUS_RFNEMPTY) || \ + ((x) == ALD_UART_STATUS_RFOERR) || \ + ((x) == ALD_UART_STATUS_RFUERR) || \ + ((x) == ALD_UART_STATUS_TSBUSY) || \ + ((x) == ALD_UART_STATUS_TFEMPTY) || \ + ((x) == ALD_UART_STATUS_TFOERR)) +#define IS_UART_IT(x) (((x) == ALD_UART_IT_RXBERR) || \ + ((x) == ALD_UART_IT_ABEND) || \ + ((x) == ALD_UART_IT_ABTO) || \ + ((x) == ALD_UART_IT_DCTS) || \ + ((x) == ALD_UART_IT_RXTO) || \ + ((x) == ALD_UART_IT_ADDRM) || \ + ((x) == ALD_UART_IT_LINBK) || \ + ((x) == ALD_UART_IT_EOB) || \ + ((x) == ALD_UART_IT_NOISE) || \ + ((x) == ALD_UART_IT_RFNEMPTY) || \ + ((x) == ALD_UART_IT_RFOERR) || \ + ((x) == ALD_UART_IT_RFUERR) || \ + ((x) == ALD_UART_IT_TBC) || \ + ((x) == ALD_UART_IT_TFEMPTY) || \ + ((x) == ALD_UART_IT_TFOERR)) +#define IS_UART_IF(x) (((x) == ALD_UART_IF_RXBERR) || \ + ((x) == ALD_UART_IF_ABEND) || \ + ((x) == ALD_UART_IF_ABTO) || \ + ((x) == ALD_UART_IF_DCTS) || \ + ((x) == ALD_UART_IF_RXTO) || \ + ((x) == ALD_UART_IF_ADDRM) || \ + ((x) == ALD_UART_IF_LINBK) || \ + ((x) == ALD_UART_IF_EOB) || \ + ((x) == ALD_UART_IF_NOISE) || \ + ((x) == ALD_UART_IF_RFNEMPTY) || \ + ((x) == ALD_UART_IF_RFOERR) || \ + ((x) == ALD_UART_IF_RFUERR) || \ + ((x) == ALD_UART_IF_TBC) || \ + ((x) == ALD_UART_IF_TFEMPTY) || \ + ((x) == ALD_UART_IF_TFOVER)) +#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) + +#define ALD_UART_STATE_TX_MASK (1U << 4) +#define ALD_UART_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_uart_init(ald_uart_handle_t *hperh); +void ald_uart_reset(ald_uart_handle_t *hperh); +void ald_uart_rs485_config(ald_uart_handle_t *hperh, ald_uart_rs485_config_t *config); +void ald_uart_scard_config(ald_uart_handle_t *hperh, ald_uart_scard_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_uart_send(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_frame_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out); + +ald_status_t ald_uart_send_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_recv_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_dma_pause(ald_uart_handle_t *hperh); +ald_status_t ald_uart_dma_resume(ald_uart_handle_t *hperh); +ald_status_t ald_uart_dma_stop(ald_uart_handle_t *hperh); + +void ald_uart_irq_handler(ald_uart_handle_t *hperh); +void ald_uart_irq_handler_fast(ald_uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void ald_uart_interrupt_config(ald_uart_handle_t *hperh, ald_uart_it_t it, type_func_t state); +void ald_uart_dma_req_config(ald_uart_handle_t *hperh, ald_uart_dma_req_t req, type_func_t state); +void uart_lin_break_detect_irq(ald_uart_handle_t *hperh, type_func_t status); +void ald_uart_lin_send_break(ald_uart_handle_t *hperh); +void ald_uart_lin_detect_break_len_config(ald_uart_handle_t *hperh, ald_uart_lin_break_len_t len); +void ald_uart_auto_baud_config(ald_uart_handle_t *hperh, ald_uart_auto_baud_mode_t mode); +ald_status_t ald_uart_rs485_send_addr(ald_uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t ald_uart_get_it_status(ald_uart_handle_t *hperh, ald_uart_it_t it); +flag_status_t ald_uart_get_status(ald_uart_handle_t *hperh, ald_uart_status_t status); +flag_status_t ald_uart_get_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag); +flag_status_t ald_uart_get_mask_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag); +void ald_uart_clear_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +ald_uart_state_t ald_uart_get_state(ald_uart_handle_t *hperh); +uint32_t ald_uart_get_error(ald_uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_UART_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_usb.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_usb.h new file mode 100644 index 0000000000..d6a6f5a49d --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_usb.h @@ -0,0 +1,821 @@ +/** + ********************************************************************************* + * + * @file ald_usb.h + * @brief Header file of USB module driver. + * + * @version V1.0 + * @date 25 Feb. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Feb. 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_USB_H__ +#define __ALD_USB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include +#include "ald_utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Public_Macros USB Public Macros + * @{ + */ +/* Power */ +#define ALD_USB_POWER_RESET 0x00000008U +#define ALD_USB_POWER_RESUME 0x00000004U +#define ALD_USB_POWER_SUSPEND 0x00000002U +#define ALD_USB_POWER_ISOUDT 0x00000080U +#define ALD_USB_POWER_SUSPENDEN 0x00000001U + +/* DPDMCON */ +#define ALD_USB_DPDMCON_DPPUD 0x00000018U +#define ALD_USB_DPDMCON_DPPUD_FLOAT 0x00000000U +#define ALD_USB_DPDMCON_DPPUD_UP 0x00000008U +#define ALD_USB_DPDMCON_DPPUD_DOWN 0x00000010U +#define ALD_USB_DPDMCON_DMPUD 0x00000006U +#define ALD_USB_DPDMCON_DMPUD_FLOAT 0x00000000U +#define ALD_USB_DPDMCON_DMPUD_UP 0x00000002U +#define ALD_USB_DPDMCON_DMPUD_DOWN 0x00000004U +#define ALD_USB_DPDMCON_PHYPWREN 0x00000001U + +/* SWCID */ +#define ALD_USB_SWCID_HOST 0x00000002U +#define ALD_USB_SWCID_CIDCTRL 0x00000001U + +/* SWVBUS */ +#define ALD_USB_SWVBUS_VALTH 0x00000008U +#define ALD_USB_SWVBUS_SESVALTH 0x00000004U +#define ALD_USB_SWVBUS_SESENDTH 0x00000002U +#define ALD_USB_SWVBUS_SIGCTRL 0x00000001U + +/* SWTMODE */ +#define ALD_USB_SWTMODE_EN 0x00000001U + +/* DEVCON */ +#define ALD_USB_DEVCON_FSDEV 0x00000040U +#define ALD_USB_DEVCON_LSDEV 0x00000020U +#define ALD_USB_DEVCON_HOST 0x00000004U +#define ALD_USB_DEVCON_HOSTREQ 0x00000002U +#define ALD_USB_DEVCON_SESSION 0x00000001U + +/* CSR0L_TXCSRL */ +#define ALD_USB_CSR0L_NAKTO 0x00000080U +#define ALD_USB_CSR0L_STATUSPKT 0x00000040U +#define ALD_USB_CSR0L_REQPKT 0x00000020U +#define ALD_USB_CSR0L_ERROR 0x00000010U +#define ALD_USB_CSR0L_SETUPPKT 0x00000008U +#define ALD_USB_CSR0L_STALLED 0x00000004U +#define ALD_USB_CSR0L_TXRDY 0x00000002U +#define ALD_USB_CSR0L_RXRDY 0x00000001U + +#define ALD_USB_CSR0L_SETENDC 0x00000080U +#define ALD_USB_CSR0L_RXRDYC 0x00000040U +#define ALD_USB_CSR0L_STALL 0x00000020U +#define ALD_USB_CSR0L_SETEND 0x00000010U +#define ALD_USB_CSR0L_DATAEND 0x00000008U + +#define ALD_USB_TXCSRL_NAKTO 0x00000080U +#define ALD_USB_TXCSRL_CLRDT 0x00000040U +#define ALD_USB_TXCSRL_STALLED 0x00000020U +#define ALD_USB_TXCSRL_FLUSH 0x00000008U +#define ALD_USB_TXCSRL_ERROR 0x00000004U +#define ALD_USB_TXCSRL_FIFONE 0x00000002U +#define ALD_USB_TXCSRL_TXRDY 0x00000001U + +#define ALD_USB_TXCSRL_STALL 0x00000010U +#define ALD_USB_TXCSRL_UNDRUN 0x00000004U + +/* CSR0H_TXCSRH */ +#define ALD_USB_CSR0H_FLUSH 0x00000001U + +#define ALD_USB_TXCSRH_AUTOSET 0x00000080U +#define ALD_USB_TXCSRH_ISO 0x00000040U +#define ALD_USB_TXCSRH_MODE 0x00000020U +#define ALD_USB_TXCSRH_FDT 0x00000008U + +/* RXCSRL */ +#define ALD_USB_RXCSRL_CLRDT 0x00000080U +#define ALD_USB_RXCSRL_STALLED 0x00000040U +#define ALD_USB_RXCSRL_REQPKT 0x00000020U +#define ALD_USB_RXCSRL_FLUSH 0x00000010U +#define ALD_USB_RXCSRL_DATAERR_NAKTO 0x00000008U +#define ALD_USB_RXCSRL_ERROR 0x00000004U +#define ALD_USB_RXCSRL_FULL 0x00000002U +#define ALD_USB_RXCSRL_RXRDY 0x00000001U + +#define ALD_USB_RXCSRL_STALL 0x00000020U +#define ALD_USB_RXCSRL_DATAERR 0x00000008U +#define ALD_USB_RXCSRL_OVERRUN 0x00000004U + +/* RXCSRH */ +#define ALD_USB_RXCSRL_AUTOCLR 0x00000080U +#define ALD_USB_RXCSRL_AUTOREQ 0x00000040U + +#define ALD_USB_RXCSRL_ISO 0x00000040U + +/* TXTYPE */ +#define ALD_USB_TXTYPE_PROTOCOL 0x00000030U +#define ALD_USB_TXTYPE1_PROTOCOL_CTRL 0x00000000U +#define ALD_USB_TXTYPE_PROTOCOL_ISO 0x00000010U +#define ALD_USB_TXTYPE_PROTOCOL_BULK 0x00000020U +#define ALD_USB_TXTYPE_PROTOCOL_INT 0x00000030U +#define ALD_USB_TXTYPE_TEPN_1 0x00000001U +#define ALD_USB_TXTYPE_TEPN_2 0x00000002U +#define ALD_USB_TXTYPE_TEPN_3 0x00000003U +#define ALD_USB_TXTYPE_TEPN_4 0x00000004U +#define ALD_USB_TXTYPE_TEPN_5 0x00000005U +#define ALD_USB_TXTYPE_TEPN_6 0x00000006U + +/* RXTYPE */ +#define ALD_USB_RXTYPE_PROTOCOL_ISO 0x00000010U +#define ALD_USB_RXTYPE_PROTOCOL_BULK 0x00000020U +#define ALD_USB_RXTYPE_PROTOCOL_INT 0x00000030U +#define ALD_USB_RXTYPE_TEPN_1 0x00000001U +#define ALD_USB_RXTYPE_TEPN_2 0x00000002U +#define ALD_USB_RXTYPE_TEPN_3 0x00000003U +#define ALD_USB_RXTYPE_TEPN_4 0x00000004U +#define ALD_USB_RXTYPE_TEPN_5 0x00000005U +#define ALD_USB_RXTYPE_TEPN_6 0x00000006U + +/* TXFIFO2 */ +#define ALD_USB_TXFIFO2_MAXPKTSIZE_1024 0x000000E0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_512 0x000000C0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_256 0x000000A0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_128 0x00000080U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_64 0x00000060U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_32 0x00000040U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_16 0x00000020U +#define ALD_USB_TXFIFO2_DPB 0x00000010U +#define ALD_USB_TXFIFO2_ADDRH 0x00000007U + +/* RXFIFO2 */ +#define ALD_USB_RXFIFO2_MAXPKTSIZE_1024 0x000000E0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_512 0x000000C0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_256 0x000000A0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_128 0x00000080U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_64 0x00000060U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_32 0x00000040U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_16 0x00000020U +#define ALD_USB_RXFIFO2_DPB 0x00000010U + +/* TXIER */ +#define ALD_USB_TXIER_EP6IE 0x00000040U +#define ALD_USB_TXIER_EP5IE 0x00000020U +#define ALD_USB_TXIER_EP4IE 0x00000010U +#define ALD_USB_TXIER_EP3IE 0x00000008U +#define ALD_USB_TXIER_EP2IE 0x00000004U +#define ALD_USB_TXIER_EP1IE 0x00000002U +#define ALD_USB_TXIER_EP0IE 0x00000001U + +/* RXIER */ +#define ALD_USB_RXIER_EP6IE 0x00000040U +#define ALD_USB_RXIER_EP5IE 0x00000020U +#define ALD_USB_RXIER_EP4IE 0x00000010U +#define ALD_USB_RXIER_EP3IE 0x00000008U +#define ALD_USB_RXIER_EP2IE 0x00000004U +#define ALD_USB_RXIER_EP1IE 0x00000002U + +/* TXIDR */ +#define ALD_USB_TXIDR_EP6ID 0x00000040U +#define ALD_USB_TXIDR_EP5ID 0x00000020U +#define ALD_USB_TXIDR_EP4ID 0x00000010U +#define ALD_USB_TXIDR_EP3ID 0x00000008U +#define ALD_USB_TXIDR_EP2ID 0x00000004U +#define ALD_USB_TXIDR_EP1ID 0x00000002U +#define ALD_USB_TXIDR_EP0ID 0x00000001U + +/* RXIDR */ +#define ALD_USB_RXIDR_EP6ID 0x00000040U +#define ALD_USB_RXIDR_EP5ID 0x00000020U +#define ALD_USB_RXIDR_EP4ID 0x00000010U +#define ALD_USB_RXIDR_EP3ID 0x00000008U +#define ALD_USB_RXIDR_EP2ID 0x00000004U +#define ALD_USB_RXIDR_EP1ID 0x00000002U + +/* TXIVS */ +#define ALD_USB_TXIVS_EP6IVS 0x00000040U +#define ALD_USB_TXIVS_EP5IVS 0x00000020U +#define ALD_USB_TXIVS_EP4IVS 0x00000010U +#define ALD_USB_TXIVS_EP3IVS 0x00000008U +#define ALD_USB_TXIVS_EP2IVS 0x00000004U +#define ALD_USB_TXIVS_EP1IVS 0x00000002U +#define ALD_USB_TXIVS_EP0IVS 0x00000001U + +/* RXIVS */ +#define ALD_USB_RXIVS_EP6IVS 0x00000040U +#define ALD_USB_RXIVS_EP5IVS 0x00000020U +#define ALD_USB_RXIVS_EP4IVS 0x00000010U +#define ALD_USB_RXIVS_EP3IVS 0x00000008U +#define ALD_USB_RXIVS_EP2IVS 0x00000004U +#define ALD_USB_RXIVS_EP1IVS 0x00000002U + +/* TXRIF */ +#define ALD_USB_TXRIF_EP6RIF 0x00000040U +#define ALD_USB_TXRIF_EP5RIF 0x00000020U +#define ALD_USB_TXRIF_EP4RIF 0x00000010U +#define ALD_USB_TXRIF_EP3RIF 0x00000008U +#define ALD_USB_TXRIF_EP2RIF 0x00000004U +#define ALD_USB_TXRIF_EP1RIF 0x00000002U +#define ALD_USB_TXRIF_EP0RIF 0x00000001U + +/* RXRIF */ +#define ALD_USB_RXRIF_EP6RIF 0x00000040U +#define ALD_USB_RXRIF_EP5RIF 0x00000020U +#define ALD_USB_RXRIF_EP4RIF 0x00000010U +#define ALD_USB_RXRIF_EP3RIF 0x00000008U +#define ALD_USB_RXRIF_EP2RIF 0x00000004U +#define ALD_USB_RXRIF_EP1RIF 0x00000002U + +/* TXIFM */ +#define ALD_USB_TXIFM_EP6IFM 0x00000040U +#define ALD_USB_TXIFM_EP5IFM 0x00000020U +#define ALD_USB_TXIFM_EP4IFM 0x00000010U +#define ALD_USB_TXIFM_EP3IFM 0x00000008U +#define ALD_USB_TXIFM_EP2IFM 0x00000004U +#define ALD_USB_TXIFM_EP1IFM 0x00000002U +#define ALD_USB_TXIFM_EP0IFM 0x00000001U + +/* RXIFM */ +#define ALD_USB_RXIFM_EP6IFM 0x00000040U +#define ALD_USB_RXIFM_EP5IFM 0x00000020U +#define ALD_USB_RXIFM_EP4IFM 0x00000010U +#define ALD_USB_RXIFM_EP3IFM 0x00000008U +#define ALD_USB_RXIFM_EP2IFM 0x00000004U +#define ALD_USB_RXIFM_EP1IFM 0x00000002U + +/* TXICR */ +#define ALD_USB_TXICR_EP6ICR 0x00000040U +#define ALD_USB_TXICR_EP5ICR 0x00000020U +#define ALD_USB_TXICR_EP4ICR 0x00000010U +#define ALD_USB_TXICR_EP3ICR 0x00000008U +#define ALD_USB_TXICR_EP2ICR 0x00000004U +#define ALD_USB_TXICR_EP1ICR 0x00000002U +#define ALD_USB_TXICR_EP0ICR 0x00000001U + +/* RXICR */ +#define ALD_USB_RXICR_EP6ICR 0x00000040U +#define ALD_USB_RXICR_EP5ICR 0x00000020U +#define ALD_USB_RXICR_EP4ICR 0x00000010U +#define ALD_USB_RXICR_EP3ICR 0x00000008U +#define ALD_USB_RXICR_EP2ICR 0x00000004U +#define ALD_USB_RXICR_EP1ICR 0x00000002U + +/* IER */ +#define ALD_USB_IER_STATUS 0x000000FFU +#define ALD_USB_IER_SESREQIE 0x00000040U +#define ALD_USB_IER_DISCONIE 0x00000020U +#define ALD_USB_IER_CONIE 0x00000010U +#define ALD_USB_IER_SOFIE 0x00000008U +#define ALD_USB_IER_BABIE 0x00000004U +#define ALD_USB_IER_RESIE 0x00000002U + +/* IDR */ +#define ALD_USB_IDR_STATUS 0x000000FFU +#define ALD_USB_IDR_SESREQID 0x00000040U +#define ALD_USB_IDR_DISCONID 0x00000020U +#define ALD_USB_IDR_CONID 0x00000010U +#define ALD_USB_IDR_SOFID 0x00000008U +#define ALD_USB_IDR_BABID 0x00000004U +#define ALD_USB_IDR_RESID 0x00000002U + +/* IVS */ +#define ALD_USB_IVS_SESREQIVS 0x00000040U +#define ALD_USB_IVS_DISCONIVS 0x00000020U +#define ALD_USB_IVS_CONIVS 0x00000010U +#define ALD_USB_IVS_SOFIVS 0x00000008U +#define ALD_USB_IVS_BABIVS 0x00000004U +#define ALD_USB_IVS_RESIVS 0x00000002U + +/* RIF */ +#define ALD_USB_RIF_SESREQRIF 0x00000040U +#define ALD_USB_RIF_DISCONRIF 0x00000020U +#define ALD_USB_RIF_CONRIF 0x00000010U +#define ALD_USB_RIF_SOFRIF 0x00000008U +#define ALD_USB_RIF_BABRIF 0x00000004U +#define ALD_USB_RIF_RESRIF 0x00000002U + +/* IFM */ +#define ALD_USB_IFM_SESREQIFM 0x00000040U +#define ALD_USB_IFM_DISCONIFM 0x00000020U +#define ALD_USB_IFM_CONIFM 0x00000010U +#define ALD_USB_IFM_SOFIFM 0x00000008U +#define ALD_USB_IFM_BABIFM 0x00000004U +#define ALD_USB_IFM_RESIFM 0x00000002U + +/* ICR */ +#define ALD_USB_ICR_SESREQICR 0x00000040U +#define ALD_USB_ICR_DISCONICR 0x00000020U +#define ALD_USB_ICR_CONICR 0x00000010U +#define ALD_USB_ICR_SOFICR 0x00000008U +#define ALD_USB_ICR_BABICR 0x00000004U +#define ALD_USB_ICR_RESICR 0x00000002U + + +#define ALD_MAX_NAK_LIMIT 255U +#define ALD_DISABLE_NAK_LIMIT 0U + +#define ALD_USB_RX_EPSTATUS_SHIFT 16U +#define ALD_USB_INTEP_RX_SHIFT 16U + +#define ALD_MAX_PACKET_SIZE_EP0 64U + +#define ALD_USB_TXTYPE1_PROTO_M 0x00000030U +#define ALD_USB_TXTYPE1_PROTO_CTRL 0x00000000U +#define ALD_USB_TXTYPE1_PROTO_ISOC 0x00000010U +#define ALD_USB_TXTYPE1_PROTO_BULK 0x00000020U +#define ALD_USB_TXTYPE1_PROTO_INT 0x00000030U + +#define ALD_USB_FIFO_SZ_8 0x00000000U +#define ALD_USB_FIFO_SZ_16 0x00000001U +#define ALD_USB_FIFO_SZ_32 0x00000002U +#define ALD_USB_FIFO_SZ_64 0x00000003U +#define ALD_USB_FIFO_SZ_128 0x00000004U +#define ALD_USB_FIFO_SZ_256 0x00000005U +#define ALD_USB_FIFO_SZ_512 0x00000006U +#define ALD_USB_FIFO_SZ_1024 0x00000007U +#define ALD_USB_FIFO_SZ_2048 0x00000008U +#define ALD_USBFIFOSizeToBytes(x) (8 << (x)) + +#define ALD_USB_TRANS_OUT 0x00000102U +#define ALD_USB_TRANS_IN 0x00000102U +#define ALD_USB_TRANS_IN_LAST 0x0000010aU +#define ALD_USB_TRANS_SETUP 0x0000110aU +#define ALD_USB_TRANS_STATUS 0x00000142U + +#define ALD_USB_RX_EPSTATUS_SHIFT 16U +#define ALD_USB_INTEP_RX_SHIFT 16U + +#define ALD_USB_UNDEF_SPEED 0x80000000U +#define ALD_USB_HIGH_SPEED 0x00000002U +#define ALD_USB_FULL_SPEED 0x00000001U +#define ALD_USB_LOW_SPEED 0x00000000U + +#define ALD_USB_EP_AUTO_SET 0x00000001 +#define ALD_USB_EP_AUTO_REQUEST 0x00000002 +#define ALD_USB_EP_AUTO_CLEAR 0x00000004 +#define ALD_USB_EP_DUAL_BUFFERING 0x00000008 +#define ALD_USB_EP_DMA_MODE_0 0x00000008 +#define ALD_USB_EP_DMA_MODE_1 0x00000010 +#define ALD_USB_EP_DIS_NYET 0x00000020 + +#define ALD_USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define ALD_USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define ALD_USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define ALD_USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define ALD_USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define ALD_USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define ALD_USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define ALD_USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define ALD_USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define ALD_USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define ALD_USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define ALD_USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +#define ALD_USB_INTCTRL_ALL 0x000003FFU +#define ALD_USB_INTCTRL_STATUS 0x000000FFU +#define ALD_USB_INTCTRL_VBUS_ERR 0x00000080U +#define ALD_USB_INTCTRL_SESSION 0x00000040U +#define ALD_USB_INTCTRL_SESSION_END 0x00000040U +#define ALD_USB_INTCTRL_DISCONNECT 0x00000020U +#define ALD_USB_INTCTRL_CONNECT 0x00000010U +#define ALD_USB_INTCTRL_SOF 0x00000008U +#define ALD_USB_INTCTRL_BABBLE 0x00000004U +#define ALD_USB_INTCTRL_RESET 0x00000004U +#define ALD_USB_INTCTRL_RESUME 0x00000002U +#define ALD_USB_INTCTRL_SUSPEND 0x00000001U +#define ALD_USB_INTCTRL_MODE_DETECT 0x00000200U +#define ALD_USB_INTCTRL_POWER_FAULT 0x00000100U + + +#define ALD_USB_INTEP_ALL 0xFFFFFFFFU +#define ALD_USB_INTEP_HOST_IN 0x001E0000U +#define ALD_USB_INTEP_HOST_IN_15 0x80000000U +#define ALD_USB_INTEP_HOST_IN_14 0x40000000U +#define ALD_USB_INTEP_HOST_IN_13 0x20000000U +#define ALD_USB_INTEP_HOST_IN_12 0x10000000U +#define ALD_USB_INTEP_HOST_IN_11 0x08000000U +#define ALD_USB_INTEP_HOST_IN_10 0x04000000U +#define ALD_USB_INTEP_HOST_IN_9 0x02000000U +#define ALD_USB_INTEP_HOST_IN_8 0x01000000U +#define ALD_USB_INTEP_HOST_IN_7 0x00800000U +#define ALD_USB_INTEP_HOST_IN_6 0x00400000U +#define ALD_USB_INTEP_HOST_IN_5 0x00200000U +#define ALD_USB_INTEP_HOST_IN_4 0x00100000U +#define ALD_USB_INTEP_HOST_IN_3 0x00080000U +#define ALD_USB_INTEP_HOST_IN_2 0x00040000U +#define ALD_USB_INTEP_HOST_IN_1 0x00020000U +#define ALD_USB_INTEP_DEV_OUT 0x001E0000U +#define ALD_USB_INTEP_DEV_OUT_15 0x80000000U +#define ALD_USB_INTEP_DEV_OUT_14 0x40000000U +#define ALD_USB_INTEP_DEV_OUT_13 0x20000000U +#define ALD_USB_INTEP_DEV_OUT_12 0x10000000U +#define ALD_USB_INTEP_DEV_OUT_11 0x08000000U +#define ALD_USB_INTEP_DEV_OUT_10 0x04000000U +#define ALD_USB_INTEP_DEV_OUT_9 0x02000000U +#define ALD_USB_INTEP_DEV_OUT_8 0x01000000U +#define ALD_USB_INTEP_DEV_OUT_7 0x00800000U +#define ALD_USB_INTEP_DEV_OUT_6 0x00400000U +#define ALD_USB_INTEP_DEV_OUT_5 0x00200000U +#define ALD_USB_INTEP_DEV_OUT_4 0x00100000U +#define ALD_USB_INTEP_DEV_OUT_3 0x00080000U +#define ALD_USB_INTEP_DEV_OUT_2 0x00040000U +#define ALD_USB_INTEP_DEV_OUT_1 0x00020000U +#define ALD_USB_INTEP_HOST_OUT 0x0000001EU +#define ALD_USB_INTEP_HOST_OUT_15 0x00008000U +#define ALD_USB_INTEP_HOST_OUT_14 0x00004000U +#define ALD_USB_INTEP_HOST_OUT_13 0x00002000U +#define ALD_USB_INTEP_HOST_OUT_12 0x00001000U +#define ALD_USB_INTEP_HOST_OUT_11 0x00000800U +#define ALD_USB_INTEP_HOST_OUT_10 0x00000400U +#define ALD_USB_INTEP_HOST_OUT_9 0x00000200U +#define ALD_USB_INTEP_HOST_OUT_8 0x00000100U +#define ALD_USB_INTEP_HOST_OUT_7 0x00000080U +#define ALD_USB_INTEP_HOST_OUT_6 0x00000040U +#define ALD_USB_INTEP_HOST_OUT_5 0x00000020U +#define ALD_USB_INTEP_HOST_OUT_4 0x00000010U +#define ALD_USB_INTEP_HOST_OUT_3 0x00000008U +#define ALD_USB_INTEP_HOST_OUT_2 0x00000004U +#define ALD_USB_INTEP_HOST_OUT_1 0x00000002U +#define ALD_USB_INTEP_DEV_IN 0x0000001EU +#define ALD_USB_INTEP_DEV_IN_15 0x00008000U +#define ALD_USB_INTEP_DEV_IN_14 0x00004000U +#define ALD_USB_INTEP_DEV_IN_13 0x00002000U +#define ALD_USB_INTEP_DEV_IN_12 0x00001000U +#define ALD_USB_INTEP_DEV_IN_11 0x00000800U +#define ALD_USB_INTEP_DEV_IN_10 0x00000400U +#define ALD_USB_INTEP_DEV_IN_9 0x00000200U +#define ALD_USB_INTEP_DEV_IN_8 0x00000100U +#define ALD_USB_INTEP_DEV_IN_7 0x00000080U +#define ALD_USB_INTEP_DEV_IN_6 0x00000040U +#define ALD_USB_INTEP_DEV_IN_5 0x00000020U +#define ALD_USB_INTEP_DEV_IN_4 0x00000010U +#define ALD_USB_INTEP_DEV_IN_3 0x00000008U +#define ALD_USB_INTEP_DEV_IN_2 0x00000004U +#define ALD_USB_INTEP_DEV_IN_1 0x00000002U +#define ALD_USB_INTEP_0 0x00000001U + + +#define ALD_USB_UNDEF_SPEED 0x80000000U +#define ALD_USB_HIGH_SPEED 0x00000002U +#define ALD_USB_FULL_SPEED 0x00000001U +#define ALD_USB_LOW_SPEED 0x00000000U + +#define ALD_USB_HOST_IN_STATUS 0x114F0000U +#define ALD_USB_HOST_IN_PID_ERROR 0x10000000U +#define ALD_USB_HOST_IN_NOT_COMP 0x01000000U +#define ALD_USB_HOST_IN_STALL 0x00400000U +#define ALD_USB_HOST_IN_DATA_ERROR 0x00080000U +#define ALD_USB_HOST_IN_NAK_TO 0x00080000U +#define ALD_USB_HOST_IN_ERROR 0x00040000U +#define ALD_USB_HOST_IN_FIFO_FULL 0x00020000U +#define ALD_USB_HOST_IN_PKTRDY 0x00010000U +#define ALD_USB_HOST_OUT_STATUS 0x000000A7U +#define ALD_USB_HOST_OUT_NAK_TO 0x00000080U +#define ALD_USB_HOST_OUT_NOT_COMP 0x00000080U +#define ALD_USB_HOST_OUT_STALL 0x00000020U +#define ALD_USB_HOST_OUT_ERROR 0x00000004U +#define ALD_USB_HOST_OUT_FIFO_NE 0x00000002U +#define ALD_USB_HOST_OUT_PKTPEND 0x00000001U +#define ALD_USB_HOST_EP0_NAK_TO 0x00000080U +#define ALD_USB_HOST_EP0_STATUS 0x00000040U +#define ALD_USB_HOST_EP0_ERROR 0x00000010U +#define ALD_USB_HOST_EP0_RX_STALL 0x00000004U +#define ALD_USB_HOST_EP0_RXPKTRDY 0x00000001U +#define ALD_USB_DEV_RX_PID_ERROR 0x01000000U +#define ALD_USB_DEV_RX_SENT_STALL 0x00400000U +#define ALD_USB_DEV_RX_DATA_ERROR 0x00080000U +#define ALD_USB_DEV_RX_OVERRUN 0x00040000U +#define ALD_USB_DEV_RX_FIFO_FULL 0x00020000U +#define ALD_USB_DEV_RX_PKT_RDY 0x00010000U +#define ALD_USB_DEV_TX_NOT_COMP 0x00000080U +#define ALD_USB_DEV_TX_SENT_STALL 0x00000020U +#define ALD_USB_DEV_TX_UNDERRUN 0x00000004U +#define ALD_USB_DEV_TX_FIFO_NE 0x00000002U +#define ALD_USB_DEV_TX_TXPKTRDY 0x00000001U +#define ALD_USB_DEV_EP0_SETUP_END 0x00000010U +#define ALD_USB_DEV_EP0_SENT_STALL 0x00000004U +#define ALD_USB_DEV_EP0_IN_PKTPEND 0x00000002U +#define ALD_USB_DEV_EP0_OUT_PKTRDY 0x00000001U + + +#define ALD_USB_EP_0 0x00000000U +#define ALD_USB_EP_1 0x00000001U +#define ALD_USB_EP_2 0x00000002U +#define ALD_USB_EP_3 0x00000003U +#define ALD_USB_EP_4 0x00000004U +#define ALD_USB_EP_5 0x00000005U +#define ALD_USB_EP_6 0x00000006U +#define ALD_USB_EP_7 0x00000007U +#define ALD_NUM_USB_EP 8U + +#define ALD_USB_FIFO_SZ_8 0x00000000U +#define ALD_USB_FIFO_SZ_16 0x00000001U +#define ALD_USB_FIFO_SZ_32 0x00000002U +#define ALD_USB_FIFO_SZ_64 0x00000003U +#define ALD_USB_FIFO_SZ_128 0x00000004U +#define ALD_USB_FIFO_SZ_256 0x00000005U +#define ALD_USB_FIFO_SZ_512 0x00000006U +#define ALD_USB_FIFO_SZ_1024 0x00000007U +#define ALD_USB_FIFO_SZ_2048 0x00000008U + +#define ALD_USB_TRANS_OUT 0x00000102U +#define ALD_USB_TRANS_IN 0x00000102U +#define ALD_USB_TRANS_IN_LAST 0x0000010aU +#define ALD_USB_TRANS_SETUP 0x0000110aU +#define ALD_USB_TRANS_STATUS 0x00000142U +#define ALD_USB_DMA_EP_CFG_TX 0x00000001U +#define ALD_USB_DMA_EP_CFG_RX_DEV 0x00000002U +#define ALD_USB_DMA_EP_CFG_RX_HOST 0x00000004U +#define ALD_USB_DMA_EP_TX_MSK 0x94U +#define ALD_USB_DMA_EP_RX_DEV_MSK 0xA8U +#define ALD_USB_DMA_EP_RX_HOST_MSK 0xE8U + +#define ALD_USB_INTLPM_ERROR 0x00000020U +#define ALD_USB_INTLPM_RESUME 0x00000010U +#define ALD_USB_INTLPM_INCOMPLETE 0x00000008U +#define ALD_USB_INTLPM_ACK 0x00000004U +#define ALD_USB_INTLPM_NYET 0x00000002U +#define ALD_USB_INTLPM_STALL 0x00000001U + + +#define ALD_USB_DEV_LPM_NAK 0x00000010U +#define ALD_USB_DEV_LPM_NONE 0x00000000U +#define ALD_USB_DEV_LPM_EN 0x0000000cU +#define ALD_USB_DEV_LPM_EXTONLY 0x00000004U + +#define ALD_USB_HOST_LPM_RMTWAKE 0x00000100U +#define ALD_USB_HOST_LPM_L1 0x00000001U + +#define ALD_USB_DEV_LPM_LS_RMTWAKE 0x00000100U +#define ALD_USB_DEV_LPM_LS_L1 0x00000001U + +#define ALD_USB_HOST_PWRFLT_LOW 0x00000010U +#define ALD_USB_HOST_PWRFLT_HIGH 0x00000030U +#define ALD_USB_HOST_PWRFLT_EP_NONE 0x00000000U +#define ALD_USB_HOST_PWRFLT_EP_TRI 0x00000140U +#define ALD_USB_HOST_PWRFLT_EP_LOW 0x00000240U +#define ALD_USB_HOST_PWRFLT_EP_HIGH 0x00000340U +#define ALD_USB_HOST_PWREN_MAN_LOW 0x00000000U +#define ALD_USB_HOST_PWREN_MAN_HIGH 0x00000001U +#define ALD_USB_HOST_PWREN_AUTOLOW 0x00000002U +#define ALD_USB_HOST_PWREN_AUTOHIGH 0x00000003U +#define ALD_USB_HOST_PWREN_FILTER 0x00010000U + + +/** + * @} + */ + + +/** + * @defgroup USB_Public_Types USB Public Types + * @{ + */ + +/** + * @brief USB DP/DM line push-up or push-down + */ +typedef enum { + ALD_USB_DPDM_FLOATING = 0x0U, /**< Floating */ + ALD_USB_DPDM_PUSH_UP = 0x1U, /**< Push-Up */ + ALD_USB_DPDM_PUSH_DOWN = 0x2U, /**< Push-Down */ +} ald_dpdm_push_t; + + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions + * @{ + */ + +/** @addtogroup USB_Public_Functions_Group1 + * @{ + */ +/* Base functions */ +extern uint32_t ald_usb_frame_number_get(void); +extern void ald_usb_otg_session_request(bool start); +extern uint32_t ald_usb_mode_get(void); +extern uint32_t ald_usb_mode_host_req(void); +extern uint32_t ald_usb_mode_host_req_clear(void); +extern void ald_usb_high_speed_enable(bool enable); +extern uint32_t ald_usb_device_speed_get(void); +extern uint32_t ald_usb_num_ep_get( void); +extern void ald_usb_control_reset(void); +void ald_usb_dppud_set(ald_dpdm_push_t pupd); +void ald_usb_dmpud_set(ald_dpdm_push_t pupd); +void ald_usb_swcid_cidctrl(uint8_t cid); +void ald_usb_swcid_host(uint8_t host); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group2 + * @{ + */ +/* Device functions */ +extern uint8_t ald_usb_dev_get_addr(void); +extern void ald_usb_dev_set_addr(uint8_t addr); +extern void ald_usb_dev_connect(void); +extern void ald_usb_dev_disconnect(void); +extern void ald_usb_dev_suspend_enable(void); +extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags); +extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags); +extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last); +extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group3 + * @{ + */ +/* Host functions */ +extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags); +extern void ald_usb_host_ep_data_ack(uint32_t ep_idx); +extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags); +extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags); +extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_pwr_disable(void); +extern void ald_usb_host_pwr_enable(void); +extern void ald_usb_host_pwr_config(uint32_t flags); +extern void ald_usb_host_pwr_fault_disable(void); +extern void ald_usb_host_pwr_fault_enable(void); +extern void ald_usb_host_request_in(uint32_t ep_idx); +extern void ald_usb_host_request_in_clear(uint32_t ep_idx); +extern void ald_usb_host_request_status(void); +extern void ald_usb_host_reset(bool start); +extern void ald_usb_host_resume(bool start); +extern void ald_usb_host_suspend(void); +extern uint32_t ald_usb_host_speed_get(void); +extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group4 + * @{ + */ +/* Endpoint functions */ +extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx); +extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size); +extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size); +extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type); +extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count); +extern uint32_t ald_usb_ep_status(uint32_t ep_idx); +extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group5 + * @{ + */ +/* FIFO functions */ +extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx); +extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags); +extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags); +extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group6 + * @{ + */ +/* Interrupt functions */ +extern void ald_usb_int_disable(uint32_t flags); +extern void ald_usb_int_enable(uint32_t flags); +extern uint32_t ald_usb_int_status_get(void); +extern void ald_usb_int_disable_ep(uint32_t flags); +extern void ald_usb_int_enable_ep(uint32_t flags); +extern uint32_t ald_usb_int_status_ep_get(void); +extern void ald_usb_int_register(void); +extern void ald_usb_int_unregister(void); +extern uint32_t ald_usb_int_num_get(void); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group7 + * @{ + */ +/* DMA functions */ +extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl); +extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx); +extern void ald_usb_dma_channel_start(uint8_t ch); +extern void ald_usb_dma_channel_stop(uint8_t ch); +extern uint32_t ald_usb_dma_get_interrupt_flag(void); +extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch); +extern void ald_usb_dma_clear_channel_error(uint8_t ch); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group8 + * @{ + */ +/* LPM functions */ +extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx); +extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config); +extern uint32_t ald_usb_lpm_remote_wake_is_enable(void); +extern void ald_usb_host_lpm_resume(void); +extern void ald_usb_dev_lpm_remote_wake(void); +extern void ald_usb_dev_lpm_config(uint32_t config); +extern void ald_usb_dev_lpm_enable(void); +extern void ald_usb_dev_lpm_disable(void); +extern uint32_t ald_usb_lpm_link_status_get(void); +extern uint32_t ald_usb_lpm_ep_get(void); +extern uint32_t ald_usb_lpm_int_status_get(void); +extern void ald_usb_lpm_int_disable(uint32_t ints); +extern void ald_usb_lpm_int_enable(uint32_t ints); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group9 + * @{ + */ +/* usb swvbus control functions */ +extern void ald_usb_swvbus_sigctl_set(uint8_t sigctl); +extern uint8_t ald_usb_swvbus_sigctl_get(void); +extern void ald_usb_swvbus_sesendth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_sesendth_get(void); +extern void ald_usb_swvbus_sesvalth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_valth_get(void); +extern void ald_usb_swvbus_valth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_valth_get(void); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group10 + * @{ + */ +/* usb init functions */ +extern void ald_usb_host_components_init(void); +extern void ald_usb_device_components_init(void); + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_USB_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_utils.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_utils.h new file mode 100644 index 0000000000..e97585c747 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_utils.h @@ -0,0 +1,193 @@ +/** + ********************************************************************************* + * + * @file ald_utils.h + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 8 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 8 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_UTILS_H__ +#define __ALD_UTILS_H__ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include +#include "es32vf2264.h" +#include "type.h" + +/** @addtogroup ALD + * @{ + */ + +/** @addtogroup ALD_UTILS + * @{ + */ + +/** @defgroup ALD_Public_Types Public Types + * @{ + */ +/** + * @brief SysTick interval + */ +extern uint32_t __systick_interval; + +/** + * @brief ALD Status structures definition + */ +typedef enum { + ALD_OK = 0x0U, /**< OK */ + ALD_ERROR = 0x1U, /**< ERROR */ + ALD_BUSY = 0x2U, /**< BUSY */ + ALD_TIMEOUT = 0x3U, /**< TIMEOUT */ +} ald_status_t; + +/** + * @brief SysTick interval definition + */ +typedef enum { + ALD_SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ + ALD_SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ + ALD_SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ + ALD_SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ +} ald_systick_interval_t; +/** + * @} + */ + +/** @defgroup ALD_Public_Macros Public Macros + * @{ + */ +#define ALD_MAX_DELAY 0xFFFFFFFFU +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define ALD_RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ +do { \ + if ((x)->lock == LOCK) { \ + return ALD_BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ +} while (0) +#define __UNLOCK(x) \ +do { \ + (x)->lock = UNLOCK; \ +} while (0) +#define ALD_PANIC() \ +do { \ + while (1) \ + ; \ +} while (0) + +/** + * @brief Nested IRQ start : Save CSR and enable global interrupt. + */ +#define ALD_NEST_INT_START() \ + volatile uint32_t val_mcause, val_mstatus, val_mepc; \ + __ASM volatile("csrr %0, mcause" : "=r"(val_mcause)); \ + __ASM volatile("csrr %0, mepc" : "=r"(val_mepc)); \ + __ASM volatile("csrr %0, mstatus" : "=r"(val_mstatus)); \ + __enable_irq(); \ + +/** + * @brief Nested IRQ end : Restore CSR and disable global interrupt. + */ +#define ALD_NEST_INT_END() \ + __disable_irq(); \ + __ASM volatile("csrw mstatus, %0" : : "r"(val_mstatus));\ + __ASM volatile("csrw mepc, %0" : : "r"(val_mepc));\ + __ASM volatile("csrw mcause, %0" : : "r"(val_mcause));\ + +/** + * @} + */ + +/** @defgroup ALD_Private_Macros Private Macros + * @{ + */ +#define IS_SYSTICK_INTERVAL(x) (((x) == ALD_SYSTICK_INTERVAL_1MS) || \ + ((x) == ALD_SYSTICK_INTERVAL_10MS) || \ + ((x) == ALD_SYSTICK_INTERVAL_100MS) || \ + ((x) == ALD_SYSTICK_INTERVAL_1000MS)) +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions + * @{ + */ + +/** @addtogroup ALD_Public_Functions_Group1 + * @{ + */ + +/* Initialization functions */ +void ald_cmu_init(void); +void ald_tick_init(uint32_t prio); +void ald_systick_interval_select(ald_systick_interval_t value); + +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions_Group2 + * @{ + */ +/* Peripheral Control functions */ +void ald_inc_tick(void); +void ald_systick_irq_cbk(void); +void ald_delay_1ms(__IO uint32_t delay); +void ald_delay_1us(__IO uint32_t delay); +uint32_t ald_get_tick(void); +uint32_t ald_get_ald_version(void); +void ald_flash_wait_config(uint8_t cycle); +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_UTILS_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_wdt.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_wdt.h new file mode 100644 index 0000000000..bcde4d1fa0 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/ald_wdt.h @@ -0,0 +1,132 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.h + * @brief Header file of WDT module driver. + * + * @version V1.0 + * @date 07 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_WDT_H__ +#define __ALD_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ald_utils.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + +/** @defgroup WDT_Public_Types WDT Public Types + * @{ + */ + +/** + * @brief Wwdt no dog window + */ +typedef enum { + ALD_WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + ALD_WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + ALD_WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + ALD_WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ +} ald_wwdt_win_t; + +/** + * @} + */ + +/** + * @defgroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define ALD_WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define ALD_WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +#define ALD_IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define ALD_IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} + +/** + * @} + */ + +/** + * @addtogroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define IS_WWDT_WIN_TYPE(x) ((x == ALD_WWDT_WIN_25) || \ + (x == ALD_WWDT_WIN_50) || \ + (x == ALD_WWDT_WIN_75) || \ + (x == ALD_WWDT_WIN_00)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +/** + * @} + */ + +/** @addtogroup WWDT_Public_Functions + * @{ + */ +void ald_wwdt_init(uint32_t load, ald_wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_start(void); +uint32_t ald_wwdt_get_value(void); +it_status_t ald_wwdt_get_flag_status(void); +void ald_wwdt_clear_flag_status(void); +void ald_wwdt_feed_dog(void); +/** + * @} + */ + +/** @addtogroup IWDT_Public_Functions + * @{ + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt); +void ald_iwdt_start(void); +uint32_t ald_iwdt_get_value(void); +it_status_t ald_iwdt_get_flag_status(void); +void ald_iwdt_clear_flag_status(void); +void ald_iwdt_feed_dog(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_WDT_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/type.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/type.h new file mode 100644 index 0000000000..5f090b68b2 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/type.h @@ -0,0 +1,145 @@ +/********************************************************************************** + * + * @file type.h + * @brief define type + * + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include + + +#if defined (__CC_ARM) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif + +#define __isr__ + +typedef enum +{ + RESET = 0x0U, + SET = 0x1U, +} flag_status_t, it_status_t; + +typedef enum +{ + BIT_RESET = 0x0U, + BIT_SET = 0x1U, +} bit_status_t; + +typedef enum +{ + DISABLE = 0x0U, + ENABLE = 0x1U, +} type_func_t, TypeFunc; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum +{ + FALSE = 0x0U, + TRUE = 0x1U, +} type_bool_t; + +typedef enum +{ + UNLOCK = 0x0U, + LOCK = 0x1U, +} lock_state_t; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ + do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) +#else +#define assert_param(x) +#endif + + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_library_config.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_library_config.h new file mode 100644 index 0000000000..8230783707 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_library_config.h @@ -0,0 +1,94 @@ +/** + ********************************************************************************* + * + * @file usb_library_config.h + * @brief USB Library configure. + * + * @version V1.0 + * @date 12 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 12 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. EASTSOFT SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************************* + */ + +#ifndef __USB_LIBRARY_CONFIG_H__ +#define __USB_LIBRARY_CONFIG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#undef USB_DEBUG +#define USB_DEBUG + + +#if (defined(ES32VF2664) || defined(ES32VF2264) ) +#define USB_DMA_N_SUPPORT /* USB Built-in DMA is not supported, using external DMA automatic */ +#define USB_DRIVER_ALD +#endif + + +//#define USB_DEBUG + +/* USB Device Endpoints Assignment */ +#define AUDIO_EP_OUT USB_EP_1 +#define BULK_EP_IN USB_EP_1 +#define BULK_EP_OUT USB_EP_1 +#define CDC0_EP_CTRL USB_EP_1 +#define CDC0_EP_IN USB_EP_2 +#define CDC0_EP_OUT USB_EP_2 +#define CDC1_EP_CTRL USB_EP_3 +#define CDC1_EP_IN USB_EP_4 +#define CDC1_EP_OUT USB_EP_4 +#define HID_GAME_EP_IN USB_EP_1 +#define HID_KEYB_EP_IN USB_EP_2 +#define HID_KEYB_EP_OUT USB_EP_2 +#define HID_MOUSE_EP_IN USB_EP_1 +#define MSC_EP_IN USB_EP_1 +#define MSC_EP_OUT USB_EP_1 +#define PRINTER_EP_IN USB_EP_2 +#define PRINTER_EP_OUT USB_EP_2 + +/* USB External DMA Channel Assignment */ +#if defined(ES32VF2264) || defined(ES32VF2664) +#define USBD_E_DMA_MSC_TX_CH 3 +#define USBD_E_DMA_MSC_RX_CH 4 +#define USBD_E_DMA_AUDIO_RX_CH 5 +#define USBD_E_DMA_BULK_TX_CH 3 +#define USBD_E_DMA_BULK_RX_CH 4 +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_lowlayer_api.h b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_lowlayer_api.h new file mode 100644 index 0000000000..1717974e5d --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/usb_lowlayer_api.h @@ -0,0 +1,742 @@ +/** + ********************************************************************************* + * + * @file usb_lowlayer_api.h + * @brief USB Lower Layer API. + * + * @version V1.0 + * @date 12 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 12 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. EASTSOFT SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************************* + */ + +#ifndef __USB_LOWLAYER_API_H__ +#define __USB_LOWLAYER_API_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "usb_library_config.h" + +#if (defined(ES32VF2264) || defined(ES32VF2664)) +#ifdef USB_DRIVER_ALD +#include "type.h" +#include "ald_dma.h" +#include "ald_usb.h" +#endif /* USB_DRIVER_ALD */ +#endif /* defined(ES32VF2264) || defined(ES32VF2664) */ + +#if defined (USB_DRIVER_ALD) +/* System functions */ +// #if (defined(ES32VF2664) || defined(ES32VF2264)) +// #define map_delay_ms ald_delay_ms +// #define map_dma_handle_t dma_handle_t +// #define map_dma_config_struct dma_config_t +// #define EXT_DMA DMA +// #define map_dma_config_auto ald_dma_config_auto +// #define DMA_DATA_DST_INC_NONE DMA_DATA_INC_NONE +// #define DMA_DATA_DST_INC_BYTE DMA_DATA_INC_BYTE +// #define DMA_DATA_SRC_INC_NONE DMA_DATA_INC_NONE +// #define DMA_DATA_SRC_INC_BYTE DMA_DATA_INC_BYTE +// #else +// #endif +#if (defined(ES32VF2664) || defined(ES32VF2264)) +#include "ald_utils.h" +#define map_delay_ms md_delay_1ms +#define map_dma_handle_t dma_handle_t +#define map_dma_config_struct dma_config_t +#define EXT_DMA DMA +#define map_dma_config_auto ald_dma_config_auto +#define DMA_DATA_DST_INC_NONE DMA_DATA_INC_NONE +#define DMA_DATA_DST_INC_BYTE DMA_DATA_INC_BYTE +#define DMA_DATA_SRC_INC_NONE DMA_DATA_INC_NONE +#define DMA_DATA_SRC_INC_BYTE DMA_DATA_INC_BYTE +#else +#endif +#ifdef ES32VF2664 +#undef map_delay_ms +#define map_delay_ms ald_delay_ms +#endif + +/* low level layer init functions */ +#define map_usb_host_components_init ald_usb_host_components_init +#define map_usb_device_components_init ald_usb_device_components_init + +/* Base functions */ +#define map_usb_frame_number_get ald_usb_frame_number_get +#define map_usb_otg_session_request ald_usb_otg_session_request +#define map_usb_mode_get ald_usb_mode_get +#define map_usb_high_speed_enable ald_usb_high_speed_enable +#define map_usb_device_speed_get ald_usb_device_speed_get +#define map_usb_num_ep_get ald_usb_num_ep_get +#define map_usb_control_reset ald_usb_control_reset + +/* Device functions */ +#define map_usb_dev_get_addr ald_usb_dev_get_addr +#define map_usb_dev_set_addr ald_usb_dev_set_addr +#define map_usb_dev_connect ald_usb_dev_connect +#define map_usb_dev_disconnect ald_usb_dev_disconnect +#define map_usb_dev_ep_config ald_usb_dev_ep_config +#define map_usb_dev_ep_get_config ald_usb_dev_ep_get_config +#define map_usb_dev_ep_data_ack ald_usb_dev_ep_data_ack +#define map_usb_dev_ep_stall ald_usb_dev_ep_stall +#define map_usb_dev_ep_stall_clear ald_usb_dev_ep_stall_clear +#define map_usb_dev_ep_status_clear ald_usb_dev_ep_status_clear + +/* Host functions */ +#define map_usb_host_addr_get ald_usb_host_addr_get +#define map_usb_host_addr_set ald_usb_host_addr_set +#define map_usb_host_ep_config ald_usb_host_ep_config +#define map_usb_host_ep_data_ack ald_usb_host_ep_data_ack +#define map_usb_host_ep_data_toggle ald_usb_host_ep_data_toggle +#define map_usb_host_ep_status_clear ald_usb_host_ep_status_clear +#define map_usb_host_hub_addr_get ald_usb_host_hub_addr_get +#define map_usb_host_hub_addr_set ald_usb_host_hub_addr_set +#define map_usb_host_pwr_disable ald_usb_host_pwr_disable +#define map_usb_host_pwr_enable ald_usb_host_pwr_enable +#define map_usb_host_pwr_config ald_usb_host_pwr_config +#define map_usb_host_pwr_fault_disable ald_usb_host_pwr_fault_disable +#define map_usb_host_pwr_fault_enable ald_usb_host_pwr_fault_enable +#define map_usb_host_request_in ald_usb_host_request_in +#define map_usb_host_request_in_clear ald_usb_host_request_in_clear +#define map_usb_host_request_status ald_usb_host_request_status +#define map_usb_host_reset ald_usb_host_reset +#define map_usb_host_resume ald_usb_host_resume +#define map_usb_host_suspend ald_usb_host_suspend +#define map_usb_host_speed_get ald_usb_host_speed_get +#define map_usb_host_ep_speed_set ald_usb_host_ep_speed_set +#define map_usb_host_ep_ping ald_usb_host_ep_ping + +/* Endpoint functions */ +#define map_usb_ep_data_avail ald_usb_ep_data_avail +#define map_usb_ep_data_get ald_usb_ep_data_get +#define map_usb_ep_data_put ald_usb_ep_data_put +#define map_usb_ep_data_send ald_usb_ep_data_send +#define map_usb_ep_data_toggle_clear ald_usb_ep_data_toggle_clear +#define map_usb_ep_req_packet_count ald_usb_ep_req_packet_count +#define map_usb_ep_status ald_usb_ep_status +#define map_usb_ep_dma_config ald_usb_ep_dma_config + +/* FIFO functions */ +#define map_usb_fifo_addr_get ald_usb_fifo_addr_get +#define map_usb_fifo_config_get ald_usb_fifo_config_get +#define map_usb_fifo_config_set ald_usb_fifo_config_set +#define map_usb_fifo_flush ald_usb_fifo_flush + +/* Interrupt functions */ +#define map_usb_int_disable ald_usb_int_disable +#define map_usb_int_enable ald_usb_int_enable +#define map_usb_int_status_get ald_usb_int_status_get +#define map_usb_int_disable_ep ald_usb_int_disable_ep +#define map_usb_int_enable_ep ald_usb_int_enable_ep +#define map_usb_int_status_ep_get ald_usb_int_status_ep_get +#define map_usb_int_register ald_usb_int_register +#define map_usb_int_unregister ald_usb_int_unregister +#define map_usb_int_num_get ald_usb_int_num_get + +/* DMA functions */ +#define map_usb_dma_channel_config ald_usb_dma_channel_config +#define map_usb_dma_mult_recv_start ald_usb_dma_mult_recv_start +#define map_usb_dma_channel_start ald_usb_dma_channel_start +#define map_usb_dma_channel_stop ald_usb_dma_channel_stop +#define map_usb_dma_get_interrupt_flag ald_usb_dma_get_interrupt_flag +#define map_usb_dma_get_channel_error ald_usb_dma_get_channel_error +#define map_usb_dma_clear_channel_error ald_usb_dma_clear_channel_error + +/* LPM functions */ +#define map_usb_host_lpm_send ald_usb_host_lpm_send +#define map_usb_host_lpm_config ald_usb_host_lpm_config +#define map_usb_lpm_remote_wake_is_enable ald_usb_lpm_remote_wake_is_enable +#define map_usb_host_lpm_resume ald_usb_host_lpm_resume +#define map_usb_dev_lpm_remote_wake ald_usb_dev_lpm_remote_wake +#define map_usb_dev_lpm_config ald_usb_dev_lpm_config +#define map_usb_dev_lpm_enable ald_usb_dev_lpm_enable +#define map_usb_dev_lpm_disable ald_usb_dev_lpm_disable +#define map_usb_lpm_link_status_get ald_usb_lpm_link_status_get +#define map_usb_lpm_ep_get ald_usb_lpm_ep_get +#define map_usb_lpm_int_status_get ald_usb_lpm_int_status_get +#define map_usb_lpm_int_disable ald_usb_lpm_int_disable +#define map_usb_lpm_int_enable ald_usb_lpm_int_enable + +#elif defined (USB_DRIVER_MD) +#ifdef USE_ASSERT +#define assert_param(x) \ +do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) +#else +#define assert_param(x) +#endif + +#define USB_INTCTRL_ALL 0x000003FFU +#define USB_INTCTRL_STATUS 0x000000FFU +#define USB_INTCTRL_VBUS_ERR 0x00000080U +#define USB_INTCTRL_SESSION 0x00000040U +#define USB_INTCTRL_SESSION_END 0x00000040U +#define USB_INTCTRL_DISCONNECT 0x00000020U +#define USB_INTCTRL_CONNECT 0x00000010U +#define USB_INTCTRL_SOF 0x00000008U +#define USB_INTCTRL_BABBLE 0x00000004U +#define USB_INTCTRL_RESET 0x00000004U +#define USB_INTCTRL_RESUME 0x00000002U +#define USB_INTCTRL_SUSPEND 0x00000001U +#define USB_INTCTRL_MODE_DETECT 0x00000200U +#define USB_INTCTRL_POWER_FAULT 0x00000100U + +#define USB_INTEP_ALL 0xFFFFFFFFU +#define USB_INTEP_HOST_IN 0xFFFE0000U +#define USB_INTEP_HOST_IN_15 0x80000000U +#define USB_INTEP_HOST_IN_14 0x40000000U +#define USB_INTEP_HOST_IN_13 0x20000000U +#define USB_INTEP_HOST_IN_12 0x10000000U +#define USB_INTEP_HOST_IN_11 0x08000000U +#define USB_INTEP_HOST_IN_10 0x04000000U +#define USB_INTEP_HOST_IN_9 0x02000000U +#define USB_INTEP_HOST_IN_8 0x01000000U +#define USB_INTEP_HOST_IN_7 0x00800000U +#define USB_INTEP_HOST_IN_6 0x00400000U +#define USB_INTEP_HOST_IN_5 0x00200000U +#define USB_INTEP_HOST_IN_4 0x00100000U +#define USB_INTEP_HOST_IN_3 0x00080000U +#define USB_INTEP_HOST_IN_2 0x00040000U +#define USB_INTEP_HOST_IN_1 0x00020000U +#define USB_INTEP_DEV_OUT 0xFFFE0000U +#define USB_INTEP_DEV_OUT_15 0x80000000U +#define USB_INTEP_DEV_OUT_14 0x40000000U +#define USB_INTEP_DEV_OUT_13 0x20000000U +#define USB_INTEP_DEV_OUT_12 0x10000000U +#define USB_INTEP_DEV_OUT_11 0x08000000U +#define USB_INTEP_DEV_OUT_10 0x04000000U +#define USB_INTEP_DEV_OUT_9 0x02000000U +#define USB_INTEP_DEV_OUT_8 0x01000000U +#define USB_INTEP_DEV_OUT_7 0x00800000U +#define USB_INTEP_DEV_OUT_6 0x00400000U +#define USB_INTEP_DEV_OUT_5 0x00200000U +#define USB_INTEP_DEV_OUT_4 0x00100000U +#define USB_INTEP_DEV_OUT_3 0x00080000U +#define USB_INTEP_DEV_OUT_2 0x00040000U +#define USB_INTEP_DEV_OUT_1 0x00020000U +#define USB_INTEP_HOST_OUT 0x0000FFFEU +#define USB_INTEP_HOST_OUT_15 0x00008000U +#define USB_INTEP_HOST_OUT_14 0x00004000U +#define USB_INTEP_HOST_OUT_13 0x00002000U +#define USB_INTEP_HOST_OUT_12 0x00001000U +#define USB_INTEP_HOST_OUT_11 0x00000800U +#define USB_INTEP_HOST_OUT_10 0x00000400U +#define USB_INTEP_HOST_OUT_9 0x00000200U +#define USB_INTEP_HOST_OUT_8 0x00000100U +#define USB_INTEP_HOST_OUT_7 0x00000080U +#define USB_INTEP_HOST_OUT_6 0x00000040U +#define USB_INTEP_HOST_OUT_5 0x00000020U +#define USB_INTEP_HOST_OUT_4 0x00000010U +#define USB_INTEP_HOST_OUT_3 0x00000008U +#define USB_INTEP_HOST_OUT_2 0x00000004U +#define USB_INTEP_HOST_OUT_1 0x00000002U +#define USB_INTEP_DEV_IN 0x0000FFFEU +#define USB_INTEP_DEV_IN_15 0x00008000U +#define USB_INTEP_DEV_IN_14 0x00004000U +#define USB_INTEP_DEV_IN_13 0x00002000U +#define USB_INTEP_DEV_IN_12 0x00001000U +#define USB_INTEP_DEV_IN_11 0x00000800U +#define USB_INTEP_DEV_IN_10 0x00000400U +#define USB_INTEP_DEV_IN_9 0x00000200U +#define USB_INTEP_DEV_IN_8 0x00000100U +#define USB_INTEP_DEV_IN_7 0x00000080U +#define USB_INTEP_DEV_IN_6 0x00000040U +#define USB_INTEP_DEV_IN_5 0x00000020U +#define USB_INTEP_DEV_IN_4 0x00000010U +#define USB_INTEP_DEV_IN_3 0x00000008U +#define USB_INTEP_DEV_IN_2 0x00000004U +#define USB_INTEP_DEV_IN_1 0x00000002U +#define USB_INTEP_0 0x00000001U + +#define USB_UNDEF_SPEED 0x80000000U +#define USB_HIGH_SPEED 0x00000002U +#define USB_FULL_SPEED 0x00000001U +#define USB_LOW_SPEED 0x00000000U + +#define USB_HOST_IN_STATUS 0x114F0000U +#define USB_HOST_IN_PID_ERROR 0x10000000U +#define USB_HOST_IN_NOT_COMP 0x01000000U +#define USB_HOST_IN_STALL 0x00400000U +#define USB_HOST_IN_DATA_ERROR 0x00080000U +#define USB_HOST_IN_NAK_TO 0x00080000U +#define USB_HOST_IN_ERROR 0x00040000U +#define USB_HOST_IN_FIFO_FULL 0x00020000U +#define USB_HOST_IN_PKTRDY 0x00010000U +#define USB_HOST_OUT_STATUS 0x000000A7U +#define USB_HOST_OUT_NAK_TO 0x00000080U +#define USB_HOST_OUT_NOT_COMP 0x00000080U +#define USB_HOST_OUT_STALL 0x00000020U +#define USB_HOST_OUT_ERROR 0x00000004U +#define USB_HOST_OUT_FIFO_NE 0x00000002U +#define USB_HOST_OUT_PKTPEND 0x00000001U +#define USB_HOST_EP0_NAK_TO 0x00000080U +#define USB_HOST_EP0_STATUS 0x00000040U +#define USB_HOST_EP0_ERROR 0x00000010U +#define USB_HOST_EP0_RX_STALL 0x00000004U +#define USB_HOST_EP0_RXPKTRDY 0x00000001U +#define USB_DEV_RX_PID_ERROR 0x01000000U +#define USB_DEV_RX_SENT_STALL 0x00400000U +#define USB_DEV_RX_DATA_ERROR 0x00080000U +#define USB_DEV_RX_OVERRUN 0x00040000U +#define USB_DEV_RX_FIFO_FULL 0x00020000U +#define USB_DEV_RX_PKT_RDY 0x00010000U +#define USB_DEV_TX_NOT_COMP 0x00000080U +#define USB_DEV_TX_SENT_STALL 0x00000020U +#define USB_DEV_TX_UNDERRUN 0x00000004U +#define USB_DEV_TX_FIFO_NE 0x00000002U +#define USB_DEV_TX_TXPKTRDY 0x00000001U +#define USB_DEV_EP0_SETUP_END 0x00000010U +#define USB_DEV_EP0_SENT_STALL 0x00000004U +#define USB_DEV_EP0_IN_PKTPEND 0x00000002U +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001U + +#define USB_EP_AUTO_SET 0x00000001U +#define USB_EP_AUTO_REQUEST 0x00000002U +#define USB_EP_AUTO_CLEAR 0x00000004U +#define USB_EP_DUAL_BUFFERING 0x00000008U +#define USB_EP_DMA_MODE_0 0x00000008U +#define USB_EP_DMA_MODE_1 0x00000010U +#define USB_EP_DIS_NYET 0x00000020U +#define USB_EP_MODE_ISOC 0x00000000U +#define USB_EP_MODE_BULK 0x00000100U +#define USB_EP_MODE_INT 0x00000200U +#define USB_EP_MODE_CTRL 0x00000300U +#define USB_EP_MODE_MASK 0x00000300U +#define USB_EP_SPEED_LOW 0x00000000U +#define USB_EP_SPEED_FULL 0x00001000U +#define USB_EP_SPEED_HIGH 0x00004000U +#define USB_EP_HOST_IN 0x00000000U +#define USB_EP_HOST_OUT 0x00002000U +#define USB_EP_DEV_IN 0x00002000U +#define USB_EP_DEV_OUT 0x00000000U + +#define USB_HOST_PWRFLT_LOW 0x00000010U +#define USB_HOST_PWRFLT_HIGH 0x00000030U +#define USB_HOST_PWRFLT_EP_NONE 0x00000000U +#define USB_HOST_PWRFLT_EP_TRI 0x00000140U +#define USB_HOST_PWRFLT_EP_LOW 0x00000240U +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340U +#define USB_HOST_PWREN_MAN_LOW 0x00000000U +#define USB_HOST_PWREN_MAN_HIGH 0x00000001U +#define USB_HOST_PWREN_AUTOLOW 0x00000002U +#define USB_HOST_PWREN_AUTOHIGH 0x00000003U +#define USB_HOST_PWREN_FILTER 0x00010000U + +#define USB_HOST_LPM_RMTWAKE 0x00000100U +#define USB_HOST_LPM_L1 0x00000001U + +#define USB_DEV_LPM_NAK 0x00000010U +#define USB_DEV_LPM_NONE 0x00000000U +#define USB_DEV_LPM_EN 0x0000000cU +#define USB_DEV_LPM_EXTONLY 0x00000004U + +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100U +#define USB_DEV_LPM_LS_L1 0x00000001U + +#define USB_INTLPM_ERROR 0x00000020U +#define USB_INTLPM_RESUME 0x00000010U +#define USB_INTLPM_INCOMPLETE 0x00000008U +#define USB_INTLPM_ACK 0x00000004U +#define USB_INTLPM_NYET 0x00000002U +#define USB_INTLPM_STALL 0x00000001U + +#define USB_CLOCK_INTERNAL 0x00000200U +#define USB_CLOCK_EXTERNAL 0x00000300U + +#define USB_ULPI_EXTVBUS 0x00000001U +#define USB_ULPI_EXTVBUS_IND 0x00000002U + +#define MAX_NAK_LIMIT 31U +#define DISABLE_NAK_LIMIT 0U + +#define MAX_PACKET_SIZE_EP0 64U + +#define USB_EP_0 0x00000000U +#define USB_EP_1 0x00000010U +#define USB_EP_2 0x00000020U +#define USB_EP_3 0x00000030U +#define USB_EP_4 0x00000040U +#define USB_EP_5 0x00000050U +#define USB_EP_6 0x00000060U +#define USB_EP_7 0x00000070U +#define NUM_USB_EP 8U + +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +#define USB_FIFO_SZ_8 0x00000000U +#define USB_FIFO_SZ_16 0x00000001U +#define USB_FIFO_SZ_32 0x00000002U +#define USB_FIFO_SZ_64 0x00000003U +#define USB_FIFO_SZ_128 0x00000004U +#define USB_FIFO_SZ_256 0x00000005U +#define USB_FIFO_SZ_512 0x00000006U +#define USB_FIFO_SZ_1024 0x00000007U +#define USB_FIFO_SZ_2048 0x00000008U +#define USBFIFOSizeToBytes(x) (8U << (x)) + +#define USB_TRANS_OUT 0x00000102U +#define USB_TRANS_IN 0x00000102U +#define USB_TRANS_IN_LAST 0x0000010aU +#define USB_TRANS_SETUP 0x0000110aU +#define USB_TRANS_STATUS 0x00000142U + +#define USB_DUAL_MODE_HOST 0x00000001U +#define USB_DUAL_MODE_DEVICE 0x00000081U +#define USB_DUAL_MODE_NONE 0x00000080U +#define USB_OTG_MODE_ASIDE_HOST 0x0000001dU +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001U +#define USB_OTG_MODE_ASIDE_SESS 0x00000009U +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011U +#define USB_OTG_MODE_ASIDE_DEV 0x00000019U +#define USB_OTG_MODE_BSIDE_HOST 0x0000009dU +#define USB_OTG_MODE_BSIDE_DEV 0x00000099U +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081U +#define USB_OTG_MODE_NONE 0x00000080U + +#define DMA_DST_INC_8 0x00000000U +#define DMA_DST_INC_16 0x40000000U +#define DMA_DST_INC_32 0x80000000U +#define DMA_DST_INC_NONE 0xc0000000U +#define DMA_SRC_INC_8 0x00000000U +#define DMA_SRC_INC_16 0x04000000U +#define DMA_SRC_INC_32 0x08000000U +#define DMA_SRC_INC_NONE 0x0c000000U +#define DMA_SIZE_8 0x00000000U +#define DMA_SIZE_16 0x11000000U +#define DMA_SIZE_32 0x22000000U +#define DMA_DST_PROT_PRIV 0x00200000U +#define DMA_SRC_PROT_PRIV 0x00040000U +#define DMA_ARB_1 0x00000000U +#define DMA_ARB_2 0x00004000U +#define DMA_ARB_4 0x00008000U +#define DMA_ARB_8 0x0000c000U +#define DMA_ARB_16 0x00010000U +#define DMA_ARB_32 0x00014000U +#define DMA_ARB_64 0x00018000U +#define DMA_ARB_128 0x0001c000U +#define DMA_ARB_256 0x00020000U +#define DMA_ARB_512 0x00024000U +#define DMA_ARB_1024 0x00028000U +#define DMA_NEXT_USEBURST 0x00000008U +#define USB_DMA_INT_CH8 0x00000080U +#define USB_DMA_INT_CH7 0x00000040U +#define USB_DMA_INT_CH6 0x00000020U +#define USB_DMA_INT_CH5 0x00000010U +#define USB_DMA_INT_CH4 0x00000008U +#define USB_DMA_INT_CH3 0x00000004U +#define USB_DMA_INT_CH2 0x00000002U +#define USB_DMA_INT_CH1 0x00000001U +#define USB_DMA_STATUS_ERROR 0x00000100U +#define USB_DMA_CFG_BURST_NONE 0x00000000U +#define USB_DMA_CFG_BURST_4 0x00000200U +#define USB_DMA_CFG_BURST_8 0x00000400U +#define USB_DMA_CFG_BURST_16 0x00000600U +#define USB_DMA_CFG_INT_EN 0x00000008U +#define USB_DMA_CFG_MODE_0 0x00000000U +#define USB_DMA_CFG_MODE_1 0x00000004U +#define USB_DMA_CFG_DIR_RX 0x00000000U +#define USB_DMA_CFG_DIR_TX 0x00000002U +#define USB_DMA_CFG_EN 0x00000001U +#define USB_MODE_HOST_VBUS 0x00000004U +#define USB_MODE_HOST 0x00000002U +#define USB_MODE_DEV_VBUS 0x00000005U +#define USB_MODE_DEV 0x00000003U +#define USB_MODE_OTG 0x00000000U +#define DMA_ATTR_USEBURST 0x00000001U +#define DMA_ATTR_ALTSELECT 0x00000002U +#define DMA_ATTR_HIGH_PRIORITY 0x00000004U +#define DMA_ATTR_REQMASK 0x00000008U +#define DMA_ATTR_ALL 0x0000000FU +#define USB_DMA_EP_CFG_TX 0x00000001U +#define USB_DMA_EP_CFG_RX_DEV 0x00000002U +#define USB_DMA_EP_CFG_RX_HOST 0x00000004U +#define USB_DMA_EP_TX_MSK 0x94U +#define USB_DMA_EP_RX_DEV_MSK 0xA8U +#define USB_DMA_EP_RX_HOST_MSK 0xE8U + +#else + +/* System API */ +#define map_usb_re_config md_usb_re_config +#define map_delay_ms md_usb_system_delayms +#define map_usb_controller_reset md_usb_controller_reset +#define map_usb_control_reset md_usb_controller_reset +#define map_usb_controller_enable md_usb_controller_enable +#define map_usb_controller_disable md_usb_controller_disable +#define map_usb_clk_phy_enable md_usb_clk_phy_enable +#define map_usb_clk_phy_disable md_usb_clk_phy_disable +#define map_usb_int_num_get md_usb_nvic_number_get +#define map_usb_int_register md_usb_nvic_enable +#define map_usb_int_unregister md_usb_nvic_disable + +/* DMA API */ +#define EXT_DMA DMA +#define DMA_DATA_DST_INC_NONE ALD_DMA_DATA_DINC_DISABLE +#define DMA_DATA_DST_INC_BYTE ALD_DMA_DATA_DINC_ENABLE +#define DMA_DATA_SRC_INC_NONE ALD_DMA_DATA_SINC_DISABLE +#define DMA_DATA_SRC_INC_BYTE ALD_DMA_DATA_SINC_ENABLE +#define map_dma_handle_t ald_dma_handle_t +#define map_dma_config_struct ald_dma_deinit_struct +#define map_dma_config_basic ald_dma_config_basic + +/* USB Base API */ +/* Host Mode */ +#define map_usb_host_reset md_usb_hos_reset +#define map_usb_host_resume md_usb_hos_resume +#define map_usb_host_suspend md_usb_hos_suspend +#define map_usb_host_request_status md_usb_hos_request_status +#define map_usb_host_request_in md_usb_hos_request_in +#define map_usb_host_request_in_clear md_usb_hos_request_in_clear +#define map_usb_host_speed_get md_usb_hos_speed_get +#define map_usb_host_addr_get md_usb_hos_addr_get +#define map_usb_host_addr_set md_usb_hos_addr_set +#define map_usb_host_hub_addr_get md_usb_hos_hub_addr_get +#define map_usb_host_hub_addr_set md_usb_hos_hub_addr_set +/* Device Mode */ +#define map_usb_dev_set_addr md_usb_dev_addr_set +#define map_usb_dev_get_addr md_usb_dev_addr_get +#define map_usb_dev_connect md_usb_dev_connect +#define map_usb_dev_disconnect md_usb_dev_disconnect +/* Host/Device Mode */ +#define map_usb_frame_number_get md_usb_hosdev_frame_get +#define map_usb_int_disable md_usb_hosdev_int_disable +#define map_usb_int_enable md_usb_hosdev_int_enable +#define map_usb_int_status_get md_usb_hosdev_int_status +#define map_usb_mode_get md_usb_hosdev_mode_get +/* otg Mode */ +#define map_usb_otg_session_request md_usb_otg_session_request +#define map_usb_mode_force_host md_usb_force_host_mode +#define map_usb_mode_force_device md_usb_force_device_mode +#define map_usb_mode_force_otg md_usb_force_otg_mode +#define map_usb_mode_config md_usb_mode_config + +/* USB Endpoint API */ +/* Host Mode */ +#define map_usb_host_ep_config md_usb_hos_endpoint_config_set +#define map_usb_host_ep_data_ack md_usb_hos_endpoint_data_ack +#define map_usb_host_ep_data_toggle md_usb_hos_endpoint_data_toggle +#define map_usb_host_ep_status_clear md_usb_hos_endpoint_status_clear +#define map_usb_host_ep_speed_set md_usb_hos_endpoint_speed +#define map_usb_host_ep_ping md_usb_hos_endpoint_ping +/* Device Mode */ +#define map_usb_dev_ep_config md_usb_dev_endpoint_config_set +#define map_usb_dev_ep_get_config md_usb_dev_endpoint_config_get +#define map_usb_dev_ep_data_ack md_usb_dev_endpoint_ack +#define map_usb_dev_ep_stall md_usb_dev_endpoint_stall +#define map_usb_dev_ep_stall_clear md_usb_dev_endpoint_stall_clear +#define map_usb_dev_ep_status_clear md_usb_dev_endpoint_status_clear +/* Host/Device Mode */ +#define map_usb_ep_data_avail md_usb_hosdev_endpoint_datavai +#define map_usb_ep_data_get md_usb_hosdev_endpoint_data_get +#define map_usb_ep_data_put md_usb_hosdev_endpoint_data_put +#define map_usb_ep_data_send md_usb_hosdev_endpoint_data_send +#define map_usb_ep_data_toggle_clear md_usb_hosdev_endpoint_data_togglec +#define map_usb_ep_req_packet_count md_usb_hosdev_endpoint_pkcount_set +#define map_usb_ep_status md_usb_hosdev_endpoint_status +#define map_usb_int_disable_ep md_usb_hosdev_endpoint_int_disable +#define map_usb_int_enable_ep md_usb_hosdev_endpoint_int_enable +#define map_usb_int_status_ep_get md_usb_hosdev_endpoint_int_status +#define map_usb_num_ep_get md_usb_endpoint_number_get + +/* USB FIFO API */ +#define map_usb_fifo_addr_get md_usb_hosdev_fifo_addr_get +#define map_usb_fifo_config_get md_usb_hosdev_fifo_config_get +#define map_usb_fifo_config_set md_usb_hosdev_fifo_config_set +#define map_usb_fifo_flush md_usb_hosdev_fifo_flush + +/* Not Support API By USB_DRIVER_MD */ +#define map_usb_host_pwr_disable md_usb_hos_pwr_disable +#define map_usb_host_pwr_enable md_usb_hos_pwr_enable +#define map_usb_host_pwr_config md_usb_hos_pwr_config +#define map_usb_host_pwr_fault_disabl md_usb_hos_pwrfault_disable +#define map_usb_host_pwr_fault_enable md_usb_hos_pwrfault_enable +#define map_usb_host_lpm_send md_usb_hos_lpm_send +#define map_usb_host_lpm_config md_usb_hos_lpm_config +#define map_usb_lpm_remote_wake_is_enable md_usb_lpm_remotewake_is_enabled +#define map_usb_host_lpm_resume md_usb_hos_lpm_resume +#define map_usb_dev_lpm_remote_wake md_usb_dev_lpm_remotewake +#define map_usb_dev_lpm_config md_usb_dev_lpm_config +#define map_usb_dev_lpm_enable md_usb_dev_lpm_enable +#define map_usb_dev_lpm_disable md_usb_dev_lpm_disable +#define map_usb_lpm_link_status_get md_usb_lpm_link_state_get +#define map_usb_lpm_ep_get md_usb_lpm_endpoint_get +#define map_usb_lpm_int_status_get md_usb_lpm_status +#define map_usb_lpm_int_disable md_usb_lpm_int_disable +#define map_usb_lpm_int_enable md_usb_lpm_int_enable +#define map_usb_dma_channel_config md_usb_dma_channel_config +#define map_usb_dma_mult_recv_start md_usb_dma_mult_recv_start +#define map_usb_dma_channel_start md_usb_dma_channel_start +#define map_usb_dma_channel_stop md_usb_dma_channel_stop +#define map_usb_dma_get_interrupt_flag md_usb_dma_get_interrupt_flag +#define map_usb_dma_get_channel_error md_usb_dma_get_channel_error +#define map_usb_dma_clear_channel_error md_usb_dma_clear_channel_error +#define map_usb_ep_dma_config md_usb_ep_dma_config + + +/* SYSTEM API. */ +extern void md_usb_system_int_disable(void); +extern void md_usb_system_int_enable(void); +extern void md_usb_re_config(bool Device); /* Weak defination */ +extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ +extern void md_usb_systic_disable(void); +extern void md_usb_controller_reset(void); +extern void md_usb_controller_enable(void); +extern void md_usb_controller_disable(void); +extern void md_usb_clk_phy_enable(void); +extern void md_usb_clk_phy_disable(void); +extern uint32_t md_usb_nvic_number_get(void); +extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ +extern void md_usb_nvic_enable(void); +extern void md_usb_nvic_disable(void); + +/* USB basic API */ +/* Host Mode */ +extern void md_usb_hos_reset(bool bStart); +extern void md_usb_hos_resume(bool bStart); +extern void md_usb_hos_suspend(void); +extern void md_usb_hos_request_status(void); +extern void md_usb_hos_request_in(uint32_t ui32Endpoint); +extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); +extern uint32_t md_usb_hos_speed_get(void); +extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +/* Device Mode */ +extern void md_usb_dev_addr_set(uint8_t ui32Address); +extern uint8_t md_usb_dev_addr_get(void); +extern void md_usb_dev_connect(void); +extern void md_usb_dev_disconnect(void); +extern uint32_t md_usb_dev_speed_get(void); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_frame_get(void); +extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_int_status(void); +extern uint32_t md_usb_hosdev_mode_get(void); +/* otg Mode */ +extern void md_usb_otg_session_request(bool bStart); +extern void md_usb_force_host_mode(void); +extern void md_usb_force_device_mode(void); +extern void md_usb_force_otg_mode(void); +extern void md_usb_mode_config(uint32_t ui32Mode); + +/* USB endpoint API */ +/* Host Mode */ +extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); +extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, bool bDataToggle, uint32_t ui32Flags); +extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, bool bEnable); +/* Device Mode */ +extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, uint32_t ui32MaxPacketSize, uint32_t ui32Flags); +extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags); +extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, bool bIsLastPacket); +extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, uint32_t ui32Flags); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); +extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, uint32_t ui32TransType); +extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, uint32_t ui32Count); +extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); +extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_endpoint_int_status(void); +extern uint32_t md_usb_endpoint_number_get(void); + +/* USB FIFO API.*/ +extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); +extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); + +/* Not Support API By USB_DRIVER_MD */ +extern void md_usb_hos_pwr_disable(void); +extern void md_usb_hos_pwr_enable(void); +extern void md_usb_hos_pwr_config(uint32_t ui32Flags); +extern void md_usb_hos_pwrfault_disable(void); +extern void md_usb_hos_pwrfault_enable(void); +extern void md_usb_hos_lpm_send(uint32_t ui32Address, uint32_t uiEndpoint); +extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, uint32_t ui32Config); +extern bool md_usb_lpm_remotewake_is_enabled(void); +extern void md_usb_hos_lpm_resume(void); +extern void md_usb_dev_lpm_remotewake(void); +extern void md_usb_dev_lpm_config(uint32_t ui32Config); +extern void md_usb_dev_lpm_enable(void); +extern void md_usb_dev_lpm_disable(void); +extern uint32_t md_usb_lpm_link_state_get(void); +extern uint32_t md_usb_lpm_endpoint_get(void); +extern uint32_t md_usb_lpm_status(void); +extern void md_usb_lpm_int_disable(uint32_t ui32Ints); +extern void md_usb_lpm_int_enable(uint32_t ui32Ints); +/* DMA functions */ +extern void md_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl); +extern void md_usb_dma_mult_recv_start(uint32_t ep_idx); +extern void md_usb_dma_channel_start(uint8_t ch); +extern void md_usb_dma_channel_stop(uint8_t ch); +extern uint32_t md_usb_dma_get_interrupt_flag(void); +extern uint32_t md_usb_dma_get_channel_error(uint8_t ch); +extern void md_usb_dma_clear_channel_error(uint8_t ch); +extern void md_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, uint8_t en); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_adc.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_adc.c new file mode 100644 index 0000000000..5a5ad91d0c --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_adc.c @@ -0,0 +1,1101 @@ +/** + ****************************************************************************** + * @file ald_adc.c + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of normal + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on normal group + * ++ Channels configuration on insert group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team. + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + + +#include "ald_adc.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC module driver + * @{ + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ +static void adc_dma_normal_conv_cplt(void *arg); +/** + * @} + */ + +/** @defgroup ADC_Public_Functions ADC Public Functions + * @{ + */ + +/** @defgroup ADC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and normal group according to + * parameters specified in structure "adc_handle_t". + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_init(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); + assert_param(IS_FUNC_STATE(hperh->init.scan)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); + assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); + assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); + assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); + assert_param(IS_FUNC_STATE(hperh->init.cont)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); + + if (hperh->state == ALD_ADC_STATE_RESET ) { + hperh->error_code = ALD_ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + ALD_ADC_DISABLE(hperh); + ald_adc_reset(hperh); + hperh->state = ALD_ADC_STATE_BUSY; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (hperh->init.disc == ALD_ADC_NCH_DISC_EN) { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc == ALD_ADC_ICH_DISC_EN) { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + + if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ALD_ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS); + + WRITE_REG(hperh->perh->CCR, 0x0); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_POSDIV_MSK, hperh->init.div << ADC_CCR_POSDIV_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + ALD_ADC_ENABLE(hperh); + + hperh->error_code = ALD_ADC_ERROR_NONE; + hperh->state = ALD_ADC_STATE_READY; + return ALD_OK; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_reset(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + WRITE_REG(hperh->perh->CLR, 0x30F); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->NCHOFF, 0x0); + WRITE_REG(hperh->perh->ICHOFF1, 0x0); + WRITE_REG(hperh->perh->ICHOFF2, 0x0); + WRITE_REG(hperh->perh->ICHOFF3, 0x0); + WRITE_REG(hperh->perh->ICHOFF4, 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->SMPT3, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + hperh->state = ALD_ADC_STATE_RESET; + hperh->error_code = ALD_ADC_ERROR_NONE; + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group2 IO operation functions + * @brief Input and Output operation functions + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of normal group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCH | ALD_ADC_FLAG_NCHS); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on insert group. If insert group is under use, it + * should be preliminarily stopped using ald_adc_insert_stop function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + hperh->state = ALD_ADC_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Wait for normal group conversion to be completed. + * @note This function cannot be used in a particular setup: ADC configured in DMA mode. + * In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. + * @note When use this function,you should be pay attention to the hperh->init.reocs_mode, + * if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. + * if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ALD_ADC_STATE_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCHS | ALD_ADC_FLAG_NCH); + return ALD_OK; +} + +/** + * @brief Poll for conversion event. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param event_type: the ADC event type. + * This parameter can be one of the following values: + * ADC_awd_event: ADC Analog watchdog event. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_poll_for_event(ald_adc_handle_t *hperh, ald_adc_event_type_t event_type, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + _tick = ald_get_tick(); + while (ald_adc_get_flag_status(hperh, (ald_adc_flag_t)event_type) == RESET) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ALD_ADC_STATE_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_WDG); + return ALD_OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group with interruption. + * Interruptions enabled in this function: + * - REOC (end of conversion of normal group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_NCH, ENABLE); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_NCH, DISABLE); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + return ALD_OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group and transfers result + * through DMA. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param buf: The destination Buffer address. + * @param size: The length of data to be transferred from ADC peripheral to memory. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_start_by_dma(ald_adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + SET_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + hperh->hdma.cplt_tc_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_tc_arg = hperh; + ald_dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_ADC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_ADC; + hperh->hdma.config.circle_mode = ENABLE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&hperh->hdma); + + ALD_ADC_ENABLE(hperh); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_insert mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_stop_by_dma(ald_adc_handle_t *hperh, uint8_t channel) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + ald_dma_channel_config(channel, DISABLE); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + return ALD_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_timer_trigger_cplt(void *arg) +{ + ald_adc_timer_config_t *hperh = (ald_adc_timer_config_t *)arg; + + ald_timer_base_stop(&hperh->h_timer); + CLEAR_BIT(hperh->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ALD_ADC_DISABLE(&hperh->h_adc); + ald_dma_channel_config(hperh->dma_ch, DISABLE); + CLEAR_BIT(hperh->h_adc.state, ALD_ADC_STATE_BUSY_N); + + if (hperh->h_adc.normal_cplt_cbk) + hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); + + return; +} + +/** + * @brief Config timer trigger adc insert channel conversion. + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_insert(ald_adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = ALD_PIS_CLK_PCLK; + config->h_pis.init.producer_edge = ALD_PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = ALD_PIS_CLK_PCLK; + + if (config->p_timer == AD16C4T) + config->h_pis.init.producer_src = ALD_PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = ALD_PIS_TIMER5_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = ALD_PIS_TIMER6_UPDATA; + else if (config->p_timer == GP16C4T2) + config->h_pis.init.producer_src = ALD_PIS_TIMER7_UPDATA; + else + return ALD_ERROR; + + config->h_pis.init.consumer_trig = ALD_PIS_CH5_ADC0_INSERT; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = ALD_TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = ALD_TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ALD_ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.ich_nr = ALD_ADC_ICH_NR_1; + config->h_adc.init.disc = ALD_ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ALD_ADC_DISC_NR_1; + config->h_adc.init.data_bit = ALD_ADC_CONV_BIT_12; + config->h_adc.init.div = ALD_ADC_CKDIV_128; + config->h_adc.init.nche_sel = ALD_ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x00100000; /* rising edge trigger insert channel convert */ + config->i_config.ch = config->adc_ch; + config->i_config.idx = ALD_ADC_ICH_IDX_1; + config->i_config.samp = ALD_ADC_SAMPLETIME_4; + config->i_config.nr = ALD_ADC_ICH_NR_1; + config->i_config.auto_m = DISABLE; + ald_adc_insert_channel_config(&config->h_adc, &config->i_config); + + ALD_ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return ALD_OK; +} + +/** + * @brief Config Timer trigger adc function + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_adc_by_dma(ald_adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = ALD_PIS_CLK_PCLK; + config->h_pis.init.producer_edge = ALD_PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = ALD_PIS_CLK_PCLK; + + if (config->p_timer == AD16C4T) + config->h_pis.init.producer_src = ALD_PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = ALD_PIS_TIMER5_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = ALD_PIS_TIMER6_UPDATA; + else if (config->p_timer == GP16C4T2) + config->h_pis.init.producer_src = ALD_PIS_TIMER7_UPDATA; + else + return ALD_ERROR; + + config->h_pis.init.consumer_trig = ALD_PIS_CH4_ADC0_NORMAL; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = ALD_TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = ALD_TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ALD_ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.nch_nr = ALD_ADC_NCH_NR_1; + config->h_adc.init.disc = ALD_ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ALD_ADC_DISC_NR_1; + config->h_adc.init.data_bit = ALD_ADC_CONV_BIT_12; + config->h_adc.init.div = ALD_ADC_CKDIV_128; + config->h_adc.init.nche_sel = ALD_ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x10000000; + config->config.ch = config->adc_ch; + config->config.idx = ALD_ADC_NCH_IDX_1; + config->config.samp = ALD_ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_tc_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_tc_arg = config; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + config->h_dma.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + config->h_dma.config.msel = ALD_DMA_MSEL_ADC; + config->h_dma.config.msigsel = ALD_DMA_MSIGSEL_ADC; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + ald_dma_interrupt_config(config->dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + + SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ALD_ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return ALD_OK; +} + +/** + * @brief Get ADC normal group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal conversion data + */ +uint32_t ald_adc_normal_get_value(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + return hperh->perh->NCHDR; +} + +/** + * @brief Enables ADC, starts conversion of insert group. + * Interruptions enabled in this function: None. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_start(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICH); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop conversion of insert channels. Disable ADC peripheral if + * no normal conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_stop(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + hperh->state = ALD_ADC_STATE_READY; + return ALD_OK; +} + +/** + * @brief Wait for insert group conversion to be completed. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state |= ALD_ADC_STATE_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICHS | ALD_ADC_FLAG_ICH); + return ALD_OK; +} + +/** + * @brief Enables ADC, starts conversion of insert group with interruption. + * - JEOC (end of conversion of insert group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t.. + */ +ald_status_t ald_adc_insert_start_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_I); + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICHS | ALD_ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_ICH, ENABLE); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop conversion of insert channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no normal conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +ald_status_t ald_adc_insert_stop_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_I); + ALD_ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_ICH, DISABLE); + return ALD_OK; +} + +/** + * @brief Get ADC insert group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param idx: Index of converted ADC insert channel. + * @retval ADC group insert conversion data + */ +uint32_t ald_adc_insert_get_value(ald_adc_handle_t *hperh, ald_adc_ich_idx_t idx) +{ + uint32_t tmp; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ICH_IDX_TYPE(idx)); + + switch (idx) { + case ALD_ADC_ICH_IDX_1: + tmp = hperh->perh->ICHDR1; + break; + case ALD_ADC_ICH_IDX_2: + tmp = hperh->perh->ICHDR2; + break; + case ALD_ADC_ICH_IDX_3: + tmp = hperh->perh->ICHDR3; + break; + case ALD_ADC_ICH_IDX_4: + tmp = hperh->perh->ICHDR4; + break; + default: + tmp = hperh->perh->ICHDR1; + break; + } + + return tmp; +} + +/** + * @brief Handles ADC interrupt request + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +void ald_adc_irq_handler(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_NCH)) { + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCH | ALD_ADC_FLAG_NCHS); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_ICH)) { + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICH | ALD_ADC_FLAG_ICHS); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_I); + + if (hperh->insert_cplt_cbk) + hperh->insert_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_AWD)) { + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_WDG); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_AWD); + + if (hperh->wdg_cbk) + hperh->wdg_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_OVR)) { + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_OVR); + hperh->error_code |= ALD_ADC_ERROR_OVR; + hperh->state |= ALD_ADC_STATE_ERROR; + + if (hperh->ovr_cbk) + hperh->ovr_cbk(hperh); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the normal + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for normal group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_channel_config(ald_adc_handle_t *hperh, ald_adc_nch_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + + if (config->idx <= ALD_ADC_NCH_IDX_4 ) { + hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); + } + else if (config->idx <= ALD_ADC_NCH_IDX_8) { + hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); + } + else if (config->idx <= ALD_ADC_NCH_IDX_12) { + hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); + } + else { + hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); + } + + if (config->ch < ALD_ADC_CHANNEL_8) { + hperh->perh->SMPT1 &= ~(0xf << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < ALD_ADC_CHANNEL_16) { + hperh->perh->SMPT2 &= ~(0xf << (uint32_t)((config->ch - ALD_ADC_CHANNEL_8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - ALD_ADC_CHANNEL_8) << 2); + } + else { + hperh->perh->SMPT3 &= ~(0xf << (uint32_t)((config->ch - ALD_ADC_CHANNEL_16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - ALD_ADC_CHANNEL_16) << 2); + } + + return ALD_OK; +} + +/** + * @brief Configures the the selected channel to be linked to the insert + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for insert group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_channel_config(ald_adc_handle_t *hperh, ald_adc_ich_conf_t *config) +{ + ald_status_t tmp_status = ALD_OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); + assert_param(IS_FUNC_STATE(config->auto_m)); + + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); + + if (config->auto_m == ENABLE) + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + + if (hperh->init.disc == ALD_ADC_ICH_DISC_EN) { + if (config->auto_m == DISABLE) { + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else { + hperh->state |= ALD_ADC_STATE_ERROR; + hperh->error_code |= ALD_ADC_ERROR_INTERNAL; + tmp_status = ALD_ERROR; + } + } + + if (config->ch < 8) { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else { + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + switch (config->idx) { + case ALD_ADC_ICH_IDX_1: + hperh->perh->ICHOFF1 = config->offset; + break; + case ALD_ADC_ICH_IDX_2: + hperh->perh->ICHOFF2 = config->offset; + break; + case ALD_ADC_ICH_IDX_3: + hperh->perh->ICHOFF3 = config->offset; + break; + case ALD_ADC_ICH_IDX_4: + hperh->perh->ICHOFF4 = config->offset; + break; + default: + break; + } + + return tmp_status; +} + +/** + * @brief Configures the analog watchdog. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC analog watchdog configuration + * @retval ALD status + */ +ald_status_t ald_adc_analog_wdg_config(ald_adc_handle_t *hperh, ald_adc_analog_wdg_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_HTR_TYPE(config->high_thrd)); + assert_param(IS_LTR_TYPE(config->low_thrd)); + + if ((config->mode == ALD_ADC_ANAWTD_SING_NM) + || (config->mode == ALD_ADC_ANAWTD_SING_IST) + || (config->mode == ALD_ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + + if (config->interrupt == DISABLE) + ald_adc_interrupt_config(hperh, ALD_ADC_IT_AWD, DISABLE); + else + ald_adc_interrupt_config(hperh, ALD_ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_thrd); + WRITE_REG(hperh->perh->WDTH, config->high_thrd); + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_WDG); + + return ALD_OK; +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref adc_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_adc_interrupt_config(ald_adc_handle_t *hperh, ald_adc_it_t it, type_func_t state) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); + + return; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt source to check. + * This parameter can be one of the @ref adc_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_adc_get_it_status(ald_adc_handle_t *hperh, ald_adc_it_t it) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + + if (READ_BIT(hperh->perh->CON0, it)) + return SET; + + return RESET; +} + +/** @brief Check whether the specified ADC flag is set or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_adc_get_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified ADC pending flags. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval None + */ +void ald_adc_clear_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + WRITE_REG(hperh->perh->CLR, flag); + return; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ + +/** + * @brief return the ADC state + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval state + */ +uint32_t ald_adc_get_state(ald_adc_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the ADC error code + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC Error Code + */ +uint32_t ald_adc_get_error(ald_adc_handle_t *hperh) +{ + return hperh->error_code; +} + +/** + *@} + */ + +/** + *@} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_normal_conv_cplt(void *arg) +{ + ald_adc_handle_t *hperh = (ald_adc_handle_t *)arg; + + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + +} + +/** + *@} + */ +/** + *@} + */ + +/** + *@} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_cmu.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_cmu.c new file mode 100644 index 0000000000..48ab12f2da --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_cmu.c @@ -0,0 +1,879 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.c + * @brief CMU module driver. + * + * @version V1.0 + * @date 13 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** System clock configure *** + ================================= + [..] + (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. + It will select HRC as system clock. The system clock is 48MHz. + (+) If you want to change system clock, you can using ald_cmu_clock_config() API. + You can select one of the following as system clock: + @ref CMU_CLOCK_HRC 4MHz or 48MHz + @ref CMU_CLOCK_LRC 32000Hz + @ref CMU_CLOCK_PLL 48MHz, 64MHz or 72MHz + @ref CMU_CLOCK_HOSC 32000Hz, 4MHz, 8MHz, 12MHz, 16MHz, 20MHz, 24MHz + (+) If you select CMU_CLOCK_PLL as system clock, it must config the PLL + using ald_cmu_pll_config() API. + (+) If you get current clock, you can using ald_cmu_get_clock() API. + ****************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup CMU CMU + * @brief CMU module driver + * @{ + */ + +/** + * @defgroup CMU_Private_Variables CMU Private Variables + * @{ + */ +uint32_t __system_clock = 48000000U; +/** + * @} + */ + +/** @defgroup CMU_Private_Functions CMU Private Functions + * @{ + */ + +/** + * @brief Update the current system clock. This function + * will be invoked, when system clock has changed. + * @param clock: The new clock. + * @retval None + */ + +static void cmu_clock_update(uint32_t clock) +{ + __system_clock = clock; + + if (clock > 1000000) + ald_tick_init(TICK_INT_PRIORITY); + + return; +} + +/** + * @brief CMU module interrupt handler + * @retval None + */ +void ald_cmu_irq_handler(void) +{ + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_FLAG_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(4000000); /* HRC4M */ + + ald_cmu_irq_cbk(ALD_CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_FLAG_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3))) + { + if(READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) > 0x5) + cmu_clock_update(4000000); /* HOSC4M */ + else + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 4000000); + } + + ald_cmu_irq_cbk(ALD_CMU_HOSC_START); + } + + /* PLL unlock */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(4000000); /* HRC4M */ + + ald_cmu_irq_cbk(ALD_CMU_PLL_UNLOCK); + } + + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions CMU Public Functions + * @{ + */ + +/** @defgroup CMU_Public_Functions_Group1 System clock configuration + * @brief System clock configuration functions + * + ============================================================================== + ##### System clock Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure system clock using default parameters. + (+) Configure system clock using specified parameters. + (+) Configure PLL using specified parameters. + (+) Get system clock. + * @{ + */ + +/** + * @brief Configure system clock using default. + * Select CMU_CLOCK_HRC(48MHz) as system clock and + * enable CMU_CLOCK_LRC(32000Hz). + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config_default(void) +{ + uint32_t cnt = 4000, tmp; + + ald_flash_wait_config(2); + + SYSCFG_UNLOCK(); + + WRITE_REG(CMU->CFGR, 0x0); + + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC48M */ + SET_BIT(tmp, CMU_CLKENR_HRC48MEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + /* Select HRC48M */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HRC48M) + { + SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(48000000); + + SYSCFG_LOCK(); + + return ALD_OK; +} + +/** + * @brief Configure system clock using specified parameters + * @param clk: The parameter can be one of the following: + * @arg @ref CMU_CLOCK_HRC 4MHz or 48MHz + * @arg @ref CMU_CLOCK_LRC 32kHz + * @arg @ref CMU_CLOCK_PLL 48MHz, 64MHz, 72MHz + * @arg @ref CMU_CLOCK_HOSC 4MHz, 8MHz, 12MHz, 16MHz, 20MHz, 24MHz + * @param clock: The clock which will be set. the value depends + * on the parameter of clk. + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config(ald_cmu_clock_t clk, uint32_t clock) +{ + uint32_t cnt = 8000; + + ald_flash_wait_config(2); + + assert_param(IS_CMU_CLOCK(clk)); + SYSCFG_UNLOCK(); + + switch (clk) { + case ALD_CMU_CLOCK_HRC48M: + assert_param(clock == 48000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HRC48M) + { + SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + case ALD_CMU_CLOCK_LRC: + + assert_param(clock == 32000); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_LRC) + { + SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + case ALD_CMU_CLOCK_HOSC: + assert_param(clock == 4000000 || clock == 8000000 || clock == 12000000 || + clock == 16000000 || clock == 20000000 || clock == 24000000); + + if(clock > 12000000) + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCFLYBPS_MSK); /* HOSC > 12MHz, enable HOSC Bypass Filter */ + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 4000000 - 1); + + for (cnt = 8000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HOSC) + { + SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + break; + + case ALD_CMU_CLOCK_PLL: + assert_param(clock == 72000000 || clock == 64000000 || clock == 48000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLLACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLLRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_PLL << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_PLL) + { + SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + case ALD_CMU_CLOCK_HRC4M: + assert_param(clock == 4000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC4MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC4MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC4M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HRC4M) + { + SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + default: + break; + } + + SYSCFG_LOCK(); + return ALD_OK; +} + +/** + * @brief Configure PLL using specified parameters. + * @param input: The input clock type. + * @param output: The output clock which can be 48MHz/64MHz/72MHz. + * @retval None + */ +void ald_cmu_pll_config(ald_cmu_pll_input_t input, ald_cmu_pll_output_t output) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_PLL_INPUT(input)); + assert_param(IS_CMU_PLL_OUTPUT(output)); + + SYSCFG_UNLOCK(); + + if(READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == ALD_CMU_CLOCK_PLL) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + } + + if (input == ALD_CMU_PLL_INPUT_HRC4M) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); + } + else + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + + if(input == ALD_CMU_PLL_INPUT_HOSC4M) + { + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 0); + } + else if(input == ALD_CMU_PLL_INPUT_HOSC8M) + { + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 1); + } + else if(input == ALD_CMU_PLL_INPUT_HOSC16M) + { + /* HOSC > 12MHz, enable HOSC Bypass Filter */ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCFLYBPS_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 3); + } + + cnt = 20000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + } + + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_REFS_MSK, input << CMU_PLLCFG_REFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_CLKOS_MSK, output << CMU_PLLCFG_CLKOS_POSS); + + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x2 << CMU_PULMCR_MODE_POSS); + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Gets current system clock. + * @retval The value of system clock. + */ +uint32_t ald_cmu_get_clock(void) +{ + return __system_clock; +} + +/** + * @} + */ + +/** + * @brief Configure the bus division. + * @param bus: The type of bus: + * @arg CMU_SYS + * @arg CMU_PCLK + * @param div: The value of divider. + * @retval None + */ +void ald_cmu_div_config(ald_cmu_bus_t bus, ald_cmu_div_t div) +{ + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(div)); + + SYSCFG_UNLOCK(); + + switch (bus) + { + case ALD_CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); + ald_tick_init(TICK_INT_PRIORITY); + break; + + case ALD_CMU_PCLK: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, div << CMU_CFGR_PCLKDIV_POSS); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get SYS clock. + * @retval The value of SYS clock. + */ +uint32_t ald_cmu_get_sys_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + return __system_clock >> sys_div; +} + +/** + * @brief Get APB clock. + * @retval The value of APB clock. + */ +uint32_t ald_cmu_get_pclk_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, CMU_CFGR_PCLKDIV_POSS); + + return (__system_clock >> sys_div) >> apb_div; +} + +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group3 Clock safe configure + * @brief Clock safe configure functions + * + * @verbatim + ============================================================================== + ##### Clock safe configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable outer high crystal safe mode. + (+) Enable/Disable outer low crystal safe mode. + (+) Enable/Disable PLL safe mode. + (+) Interrupt callback function. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/Disable outer high crystal safe mode. + * @param clock: the value of outer crystal frequency. + * @param status: The new status. + * @retval None + */ +void ald_cmu_hosc_safe_config(ald_cmu_hosc_range_t clock, type_func_t status) +{ + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable PLL1 safe mode. + * @param status: The new status. + * @retval None + */ +void ald_cmu_pll_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get current clock source. + * @retval Status: + * - 0: Current clock is PLL + * - 1: Current clock is HRC + */ +uint32_t ald_cmu_pulmcr_current_clock_source_get(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); +} + +/** + * @brief Get clock state. + * @param sr: The state type, see @ref cmu_clock_state_t. + * @retval SET/RESET + */ +flag_status_t ald_cmu_get_clock_state(ald_cmu_clock_state_t sr) +{ + assert_param(IS_CMU_CLOCK_STATE(sr)); + + if (READ_BIT(CMU->CLKSR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_cmu_irq_cbk(ald_cmu_security_t se) +{ + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group4 Clock output configure + * @brief Clock output configure functions + * + * @verbatim + ============================================================================== + ##### Clock output configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the high-speed clock output. + (+) Configure the low-speed clock output. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the high-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_HIGH_SEL_HOSC + * @arg CMU_OUTPUT_HIGH_SEL_HOSM + * @arg CMU_OUTPUT_HIGH_SEL_HRC4M + * @arg CMU_OUTPUT_HIGH_SEL_LRC + * @arg CMU_OUTPUT_HIGH_SEL_SYSCLK + * @arg CMU_OUTPUT_HIGH_SEL_HOSC32K + * @arg CMU_OUTPUT_HIGH_SEL_HRC48M + * @arg CMU_OUTPUT_HIGH_SEL_PLL + * @param div: The value of divider: + * @arg CMU_OUTPUT_DIV_1 + * @arg CMU_OUTPUT_DIV_2 + * @arg CMU_OUTPUT_DIV_4 + * @arg CMU_OUTPUT_DIV_8 + * @arg CMU_OUTPUT_DIV_16 + * @arg CMU_OUTPUT_DIV_32 + * @arg CMU_OUTPUT_DIV_64 + * @arg CMU_OUTPUT_DIV_128 + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_high_clock_config(ald_cmu_output_high_sel_t sel, + ald_cmu_output_high_div_t div, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else + { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure the low-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_LOW_SEL_LRC + * @arg CMU_OUTPUT_LOW_SEL_BUZZ + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_low_clock_config(ald_cmu_output_low_sel_t sel, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else + { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure + * @brief Peripheral clock configure functions + * + * @verbatim + ============================================================================== + ##### Peripheral clock configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure buzz clock. + (+) Enable/Disable peripheral clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure buzz clock. + * freq = sysclk / (2^(div + 1) * (dat + 1)) + * @param div: The value of divider. + * @param dat: The value of coefficient. + * @param status: The new status. + * @retval None + */ +void ald_cmu_buzz_config(ald_cmu_buzz_div_t div, uint16_t dat, type_func_t status) +{ + assert_param(IS_CMU_BUZZ_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else + { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable peripheral clock. + * @param perh: The type of peripheral, you can see @ref cmu_perh_t + * @param status: The new status. + * @retval None + */ +void ald_cmu_perh_clock_config(ald_cmu_perh_t perh, type_func_t status) +{ + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (perh == ALD_CMU_PERH_ALL) { + if (status) { + WRITE_REG(CMU->AHBENR, ~0); + WRITE_REG(CMU->APBENR, ~0); + } + else { + WRITE_REG(CMU->AHBENR, 0); + WRITE_REG(CMU->APBENR, 0); + } + + SYSCFG_LOCK(); + return; + } + + idx = ((uint32_t)perh >> 27) & 0x1; + pos = perh & ~(0x1 << 27); + + if (status) { + switch (idx) { + case 0: + SET_BIT(CMU->AHBENR, pos); + break; + + case 1: + SET_BIT(CMU->APBENR, pos); + break; + + default: + break; + } + } + else { + switch (idx) { + case 0: + CLEAR_BIT(CMU->AHBENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APBENR, pos); + break; + + default: + break; + } + } + + SYSCFG_LOCK(); + return; +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_crc.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_crc.c new file mode 100644 index 0000000000..c7a5485d92 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_crc.c @@ -0,0 +1,503 @@ +/** + ********************************************************************************* + * + * @file ald_crc.c + * @brief CRC module driver. + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_crc.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ +/** @addtogroup CRC_Private_Functions CRC Private Functions + * @{ + */ +void ald_crc_reset(ald_crc_handle_t *hperh); +static void crc_dma_calculate_cplt(void *arg); +/** + * @} + */ + + +/** @defgroup CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** @defgroup CRC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRC mode according to the specified parameters in + * the crc_handle_t and create the associated handle. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_init(ald_crc_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + + ald_crc_reset(hperh); + __LOCK(hperh); + + ALD_CRC_ENABLE(hperh); + + tmp = hperh->perh->CR; + + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATINV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (ALD_CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (0 << CRC_CR_BYTORD_POS)); + + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + ALD_CRC_RESET(hperh); + + hperh->state = ALD_CRC_STATE_READY; + + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group2 Calculate functions + * @brief Calculate functions + * @{ + */ + +/** + * @brief Calculate the crc value of data by byte. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = ALD_CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by halfword. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 2 bytes. + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_halfword(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = ALD_CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 4 bytes + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_word(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + hperh->state = ALD_CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; + + for (i = 0; i < 3; i++); + + ret = CRC->CHECKSUM; + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Calculate an amount of data used dma channel + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param res: Pointer to result + * @param size: Amount of data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_by_dma(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_CRC_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + + hperh->state = ALD_CRC_STATE_BUSY; + + hperh->cal_buf = buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + hperh->hdma.cplt_tc_arg = (void *)hperh; + hperh->hdma.cplt_tc_cbk = &crc_dma_calculate_cplt; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_CRC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is half-word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to half_word data buffer + * @param res: Pointer to result + * @param size: Amount of half_word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_halfword_by_dma(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_CRC_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + + hperh->state = ALD_CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + hperh->hdma.cplt_tc_arg = (void *)hperh; + hperh->hdma.cplt_tc_cbk = &crc_dma_calculate_cplt; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_CRC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to word data buffer + * @param res: Pointer to result + * @param size: Amount of word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_word_by_dma(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_CRC_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + + hperh->state = ALD_CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + hperh->hdma.cplt_tc_arg = (void *)hperh; + hperh->hdma.cplt_tc_cbk = &crc_dma_calculate_cplt; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_WORD; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_CRC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + + return ALD_OK; +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_pause(ald_crc_handle_t *hperh) +{ + __LOCK(hperh); + ALD_CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_resume(ald_crc_handle_t *hperh) +{ + __LOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_stop(ald_crc_handle_t *hperh) +{ + __LOCK(hperh); + ALD_CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = ALD_CRC_STATE_READY; + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions + * @brief CRC State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval CRC state + */ +ald_crc_state_t ald_crc_get_state(ald_crc_handle_t *hperh) +{ + assert_param(IS_CRC(hperh->perh)); + + return hperh->state; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions CRC Private Functions + * @brief CRC Private functions + * @{ + */ + +/** + * @brief Reset the CRC peripheral. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +void ald_crc_reset(ald_crc_handle_t *hperh) +{ + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; + + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + return; +} + +/** + * @brief DMA CRC calculate process complete callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_calculate_cplt(void *arg) +{ + ald_crc_handle_t *hperh = (ald_crc_handle_t *)arg; + + *(hperh->cal_res) = CRC->CHECKSUM; + ALD_CRC_DMA_DISABLE(hperh); + + hperh->state = ALD_CRC_STATE_READY; + + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_dma.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_dma.c new file mode 100644 index 0000000000..508428a4fa --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_dma.c @@ -0,0 +1,446 @@ +/** + ********************************************************************************* + * + * @file ald_dma.c + * @brief DMA module driver. + * + * @version V1.0 + * @date 17 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 17 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include +#include "ald_dma.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA module driver + * @{ + */ + +/** @defgroup DMA_Private_Variables DMA Private Variables + * @{ + */ +ald_dma_call_back_t dma_cbk[7]; +/** + * @} + */ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +/** + * @brief Configure DMA channel using dma_config_t structure + * @param None + * @param config: Pointer to dma_config_t which contains + * DMA channel parameter. see @ref dma_config_t + * @retval None + */ +void ald_dma_config_base(ald_dma_config_t *config) +{ + assert_param(config->src != NULL); + assert_param(config->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(config->size)); + assert_param(IS_DMA_DATASIZE_TYPE(config->src_data_width)); + assert_param(IS_DMA_DATASIZE_TYPE(config->dst_data_width)); + assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); + assert_param(IS_DMA_PRIORITY_TYPE(config->priority)); + assert_param(IS_DMA_MSEL_TYPE(config->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); + assert_param(IS_DMA_CHANNEL(config->channel)); + + WRITE_REG(DMA->CHANNEL[config->channel].SAR, (uint32_t)config->src); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SDWSEL_MSK, config->src_data_width << DMA_CON_SDWSEL_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SINC_MSK, config->src_inc << DMA_CON_SINC_POS); + WRITE_REG(DMA->CHANNEL[config->channel].DAR, (uint32_t)config->dst); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_DDWSEL_MSK, config->dst_data_width << DMA_CON_DDWSEL_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_DINC_MSK, config->dst_inc << DMA_CON_DINC_POS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_CIRC_MSK, config->circle_mode << DMA_CON_CIRC_POS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_M2M_MSK, config->mem_to_mem << DMA_CON_M2M_POS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_CHPRI_MSK, config->priority << DMA_CON_CHPRI_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_MAX_BURST_MSK, config->R_power << DMA_CON_MAX_BURST_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].NDT, DMA_NDT_TNDT_MSK, config->size << DMA_NDT_TNDT_POSS); + MODIFY_REG(DMA_MUX->CH_SELCON[config->channel], DMA_SELCON_MSEL_MSK, config->msel << DMA_SELCON_MSEL_POSS); + MODIFY_REG(DMA_MUX->CH_SELCON[config->channel], DMA_SELCON_MSIGSEL_MSK, config->msigsel << DMA_SELCON_MSIGSEL_POSS); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is basic. + * This mode is used to carry data from peripheral to memory + * or from memory to peripheral. + * @param hperh: Pointer to dma_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void ald_dma_config_basic(ald_dma_handle_t *hperh) +{ + dma_cbk[hperh->config.channel].cplt_tc_cbk = hperh->cplt_tc_cbk; + dma_cbk[hperh->config.channel].cplt_ht_cbk = hperh->cplt_ht_cbk; + dma_cbk[hperh->config.channel].cplt_tc_arg = hperh->cplt_tc_arg; + dma_cbk[hperh->config.channel].cplt_ht_arg = hperh->cplt_ht_arg; + + ald_dma_clear_flag_status(hperh->config.channel, ALD_DMA_IT_FLAG_TC); + ald_dma_clear_flag_status(hperh->config.channel, ALD_DMA_IT_FLAG_HT); + ald_dma_config_base(&hperh->config); + ald_dma_channel_config(hperh->config.channel, ENABLE); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is basic. This mode is used to carry data + * from peripheral to memory or negative direction. If user want + * use the dma easily, they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used + * @param cbk: DMA complete callback function + * + * @retval None + * + */ +void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel, + ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + ald_dma_handle_t hperh; + + ald_dma_config_struct(&hperh.config); + + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; + + hperh.perh = DMA; + hperh.cplt_tc_cbk = cbk; + hperh.cplt_tc_arg = NULL; + hperh.cplt_ht_cbk = NULL; + + ald_dma_clear_flag_status(channel, ALD_DMA_IT_FLAG_TC); + ald_dma_clear_flag_status(channel, ALD_DMA_IT_FLAG_HT); + ald_dma_config_basic(&hperh); + + return; +} + +/** + * @brief Handle DMA interrupt + * @retval None + */ +void ald_dma_irq_handler(void) +{ + uint8_t i; + + for (i = 0; i < ALD_DMA_CH_COUNT; ++i) + { + if (READ_BIT(DMA->IFM, 1U << (2U * i))) + { + if (dma_cbk[i].cplt_tc_cbk != NULL) + dma_cbk[i].cplt_tc_cbk(dma_cbk[i].cplt_tc_arg); + + DMA->ICR = 1U << (2U * i); + } + + if (READ_BIT(DMA->IFM, 1U << (2U * i + 1U))) + { + if (dma_cbk[i].cplt_ht_cbk != NULL) + dma_cbk[i].cplt_ht_cbk(dma_cbk[i].cplt_ht_arg); + + DMA->ICR = 1U << (2U * i + 1U); + } + } + + return; +} +/** + * @} + */ + +/** @defgroup DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup DMA_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @{ + */ + +/** + * @brief Reset the DMA register + * @param None + * @retval None + */ +void ald_dma_reset(void) +{ + uint32_t i; + + WRITE_REG(DMA->IDR, 0x3FFF); + WRITE_REG(DMA->ICR, 0x3FFF); + + for (i = 0; i < DMA_CHANNELS; ++i) + { + CLEAR_BIT(DMA->CHANNEL[i].CON, DMA_CON_CHEN_MSK); + WRITE_REG(DMA->CHANNEL[i].CON, 0x0); + WRITE_REG(DMA->CHANNEL[i].SAR, 0x0); + WRITE_REG(DMA->CHANNEL[i].DAR, 0x0); + WRITE_REG(DMA->CHANNEL[i].NDT, 0x0); + WRITE_REG(DMA_MUX->CH_SELCON[i], 0x0); + } + + return; +} + +/** + * @brief DMA module initialization, this function + * is invoked by ald_cmu_init(). + * @param None + * @retval None + */ +void ald_dma_init(void) +{ + memset(dma_cbk, 0x0, sizeof(dma_cbk)); + + ald_dma_reset(); + ald_mcu_irq_config(DMA_IRQn, 4, ENABLE); + + return; +} + +/** + * @brief Configure dma_config_t structure using default parameter. + * User can invoked this function, before configure dma_config_t + * @param config: Pointer to dma_config_t structure, see @ref dma_config_t + * @retval None + */ +void ald_dma_config_struct(ald_dma_config_t *config) +{ + config->size = 0; + config->src_data_width = ALD_DMA_DATA_SIZE_BYTE; + config->dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + config->src_inc = ALD_DMA_DATA_INC_DISABLE; + config->dst_inc = ALD_DMA_DATA_INC_DISABLE; + config->R_power = ALD_DMA_R_POWER_1; + config->priority = ALD_DMA_LOW_PRIORITY; + config->mem_to_mem = DISABLE; + config->circle_mode = DISABLE; + config->msel = ALD_DMA_MSEL_NONE; + config->msigsel = ALD_DMA_MSIGSEL_NONE; + config->channel = ALD_DMA_CH_0; + + return; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group2 DMA Control functions + * @brief DMA control functions + * + * @verbatim + =================================================================== + + #### DMA control functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to control DMA: + (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or + DISABLE. + (+) ald_dma_get_it_status(): Check whether the specified channel + interrupt is SET or RESET. + (+) ald_dma_get_flag_status(): Check whether the specified channel + flag is SET or RESET. + (+) ald_dma_clear_flag_status(): Clear the specified channel + pending flag + + @endverbatim + * @{ + */ + +/** + * @brief Configure channel enable or disable. It will unbind descriptor with + * channel, when channel has been disable. + * @param None + * @param channel: channel index + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * @retval None + */ +void ald_dma_channel_config(uint8_t channel, type_func_t state) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + { + SET_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK); + } + else + { + CLEAR_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK); + WRITE_REG(DMA->CHANNEL[channel].CON, 0x0); + WRITE_REG(DMA->CHANNEL[channel].SAR, 0x0); + WRITE_REG(DMA->CHANNEL[channel].DAR, 0x0); + WRITE_REG(DMA->CHANNEL[channel].NDT, 0x0); + WRITE_REG(DMA_MUX->CH_SELCON[channel], 0x0); + } + + return; +} + +/** + * @brief Configure the interrupt enable or disable + * @param channel: Channel index. + * @arg 0~6: Channel index + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * + * @retval None + */ +void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(DMA->IER, 1U << (channel * 2U + it)); + else + SET_BIT(DMA->IDR, 1U << (channel * 2U + it)); + + return; +} + +/** + * @brief Check whether the specified channel interrupt + * is set or reset + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @param channel: Channel index + * @arg 0~6: Channel index + * @retval Status: + * - SET: Channel interrupt is set + * - RESET: Channel interrupt is reset + */ +it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + + if (READ_BIT(DMA->IVS, 1 << (channel * 2U + it))) + return SET; + + return RESET; +} + +/** + * @brief Check whether the specified channel flag + * is set or reset + * @param channel: Channel index + * @arg 0~6: Channel index + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @retval Status: + * - SET: Channel flag is set + * - RESET: Channel flag is reset + */ +flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + + if (READ_BIT(DMA->IFM, 1 << (channel * 2U + it))) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified channel pending flag + * @param channel: Channel index + * @arg 0~6: Channel index + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @retval None + */ +void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + + SET_BIT(DMA->ICR, 1U << (channel * 2U + it)); + return; +} + +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_gpio.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_gpio.c new file mode 100644 index 0000000000..f70f4fbf5e --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_gpio.c @@ -0,0 +1,640 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.c + * @brief GPIO module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization functions + * + IO operation functions + * + Control functions + * + * @version V1.0 + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) External interrupt/event lines + + [..] + During and just after reset, the external interrupt lines are not active and + the I/O ports are configured Analog mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output mode, each IO can be configured on open-drain or push-pull + type and the Output driver can be selected depending on ODRV register. + + [..] + In Input mode, each IO can select filter function. + + [..] + Each IO can select TTL or SMIT type. + + [..] + Each IO have up to eight functions, user can configure the functions depend + on the user's environment. + + [..] + Each IO can be locked. Once locked, uesr can only change the output data. + Only when the CPU reset to unlock the GPIO port. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO clock. + + (#) Configure the GPIO pin(s) using ald_gpio_init(). + (++) Configure the IO mode using "mode" member from gpio_init_t structure + (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t + structure. + (++) In Output mode, configured on open-drain or push-pull using "odos" + member from gpio_init_t structure. + (++) In Output mode, configured output driver using "odrv" member + from gpio_init_t structure. + (++) In Input mode, configured filter function using "flt" member + from gpio_init_t structure. + (++) Configured type using "type" member from gpio_init_t structure. + (++) Configured functions using "func" member from gpio_init_t structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + + (#) Configure the GPIO pin(s) using ald_gpio_init_default(). + (++) Configure GPIO pin using default param: + init.mode = ALD_GPIO_MODE_OUTPUT; + init.odos = ALD_GPIO_PUSH_PULL; + init.pupd = ALD_GPIO_PUSH_UP; + init.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + init.flt = ALD_GPIO_FILTER_DISABLE; + init.type = ALD_GPIO_TYPE_CMOS; + init.func = ALD_GPIO_FUNC_1; + + (#) In case of external interrupt/event mode selection, user need invoke + ald_gpio_exti_init() to configure some param. And then invoke + ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using NVIC_SetPriority() and enable it using + NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use GPIO_read_pin(). + + (#) To set/reset the level of a pin configured in output mode use + ald_gpio_write_pin()/ald_gpio_toggle_pin(). + + (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). + + (#) Configure external interrupt mode and enable/disable using + ald_gpio_exti_interrupt_config(). + + (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). + + (#) Clear pending external interrupt flag status using + ald_gpio_exti_clear_flag_status(). + + @endverbatim + */ + +#include "ald_gpio.h" + +/** @addtogroup ALD + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO module driver + * @{ + */ + +/** @defgroup GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup GPIO_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the GPIOs or external + interrupt to be ready for use. + + @endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified + * parameters in the gpio_init_t. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a gpio_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_gpio_init_t *init) +{ + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_OD(init->od)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->odrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->OD); + tmp &= ~mask; + tmp |= (init->od << pos); + WRITE_REG(GPIOx->OD, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output driver */ + tmp = READ_REG(GPIOx->ODRV); + tmp &= ~mask; + tmp |= (init->odrv << pos); + WRITE_REG(GPIOx->ODRV, tmp); + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + } + + return; +} + +/** + * @brief Initialize the GPIOx peripheral using the default parameters. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @retval None + */ +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + ald_gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = ALD_GPIO_MODE_OUTPUT; + init.od = ALD_GPIO_PUSH_PULL; + init.pupd = ALD_GPIO_PUSH_UP; + init.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + init.flt = ALD_GPIO_FILTER_DISABLE; + init.type = ALD_GPIO_TYPE_CMOS; + init.func = ALD_GPIO_FUNC_1; + + ald_gpio_init(GPIOx, pin, &init); + + return; +} + +/** + * @brief Sets GPIO function to default(func0). + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @retval None + */ +void ald_gpio_func_default(GPIO_TypeDef *GPIOx) +{ + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); + + return; +} + +/** + * @brief Initialize the external interrupt according to the specified + * parameters in the exti_init_t. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a exti_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_exti_init_t *init) +{ + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) { + EXTI->EXTIPSR0 &= ~(0xFU << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else { + i -= 8; + EXTI->EXTIPSR1 &= ~(0xFU << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * + @verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + + @endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: Specifies the pin to read. + * @retval The input pin value + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(GPIOx->DIN, pin)) + return 1; + else + return 0; +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The specified pin to be written. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if ((val & (0x01)) == 0x00) + GPIOx->BSRR = pin << 16U; + else + GPIOx->BSRR = pin; + + return; +} + +/** + * @brief Turn over the select data. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(GPIOx->BIR, pin); + return; +} + +/** + * @brief Turn over the direction. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) { + value = 2; + } + else { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; +} + +/** + * @brief Lock the GPIO prot. Once locked, can + * only change the output data. Only when the CPU + * reset to unlock the GPIO port. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The specified Pin to be written. + * @retval None + */ +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, ALD_UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); + + return; +} + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @retval The value; + */ +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + return READ_REG(GPIOx->DIN); +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + WRITE_REG(GPIOx->DOUT, val); + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group3 Control functions + * @brief EXTI Control functions + * + @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to + control external interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the interrupt according to the specified parameter. + * @param pin: The Pin which need to configure. + * @param style: External interrupt trigger style. + * @param status: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, ald_exti_trigger_style_t style, type_func_t status) +{ + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) { + if (style == ALD_EXTI_TRIGGER_RISING_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == ALD_EXTI_TRIGGER_TRAILING_EDGE) { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == ALD_EXTI_TRIGGER_BOTH_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else { + if (style == ALD_EXTI_TRIGGER_RISING_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == ALD_EXTI_TRIGGER_TRAILING_EDGE) { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == ALD_EXTI_TRIGGER_BOTH_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; +} + +/** + * @brief Get the IE status about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval IE status + * - ENABLE + * - DISABLE + */ +type_func_t ald_gpio_exti_get_ie_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIEN, pin)) + return ENABLE; + + return DISABLE; +} + +/** + * @brief Get the Flag about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval Flag status + * - SET + * - RESET + */ +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; + + return RESET; +} + +/** + * @brief Clear the external interrupt flag. + * @param pin: The pin which belong to external interrupt. + * @retval None + */ +void ald_gpio_exti_clear_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(EXTI->EXTICFR, pin); + return; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2c.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2c.c new file mode 100644 index 0000000000..7a29a57acb --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2c.c @@ -0,0 +1,3590 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.c + * @brief I2C module driver. + * + * @version V1.0 + * @date 24 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 24 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2C driver can be used as follows: + + (#) Declare a i2c_handle_t handle structure, for example: + i2c_handle_t hperh; + + (#) Configure the Communication Speed, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. + + (#) Initialize the I2C registers by calling the ald_i2c_init(). + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + ald_i2c_mem_write_by_it() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + ald_i2c_mem_read_by_it() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_send_by_dma() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_recv_by_dma() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_send_by_dma() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_recv_by_dma() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + ald_i2c_mem_write_by_dma() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + ald_i2c_mem_read_by_dma() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + + *** I2C ald_status_t driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C ald_status_t driver. + + (+) __I2C_ENABLE: Enable the I2C peripheral + (+) __I2C_DISABLE: Disable the I2C peripheral + (+) I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) I2C_DISABLE_IT: Disable the specified I2C interrupt + (@) You can refer to the I2C ald_status_t driver header file for more useful macros + + *** I2C Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations implemented for library on our product. + (@) See ErrataSheet to know full silicon limitation list of your product. + + (#) Workarounds Implemented inside I2C library + (##) Wrong data read into data register (Polling and Interrupt mode) + (##) Start cannot be generated after a misplaced Stop + (##) Some software events must be managed before the current byte is being transferred: + Workaround: Use DMA in general, except when the Master is receiving a single byte. + For Interupt mode, I2C should have the highest priority in the application. + (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: + Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if + supported by the slave. + (##) Data valid time (tVD;DAT) violated without the OVR flag being set: + Workaround: If the slave device allows it, use the clock stretching mechanism + by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. + + @endverbatim + ********************************************************************************* + */ + +#include "ald_i2c.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C module driver + * @{ + */ + +/** @addtogroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +#define I2C_TIMEOUT_FLAG (10) +#define I2C_TIMEOUT_ADDR_SLAVE (10) +#define I2C_TIMEOUT_BUSY_FLAG (10) +#define I2C_MAX_DELAY 0xFFFFFFFF + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +static void i2c_dma_master_send_cplt(void *argv); +static void i2c_dma_master_recv_cplt(void *argv); +static void i2c_dma_slave_send_cplt(void *argv); +static void i2c_dma_slave_recv_cplt(void *argv); +static void i2c_dma_mem_send_cplt(void *argv); +static void i2c_dma_mem_recv_cplt(void *argv); +static ald_status_t i2c_req_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); + +static ald_status_t i2c_master_req_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_master_req_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_req_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +static ald_status_t i2c_wait_flag_change_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, + flag_status_t status, uint32_t timeout); +static ald_status_t i2c_wait_master_addr_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, uint32_t timeout); +static ald_status_t i2c_wait_txe_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_rxne_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_master_send_tc(ald_i2c_handle_t *hperh); +static ald_status_t i2c_master_send_txe(ald_i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_tc(ald_i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_rxne(ald_i2c_handle_t *hperh); +static ald_status_t i2c_slave_send_txe(ald_i2c_handle_t *hperh); +static ald_status_t i2c_slave_recv_rxne(ald_i2c_handle_t *hperh); +static ald_status_t i2c_slave_stopf(ald_i2c_handle_t *hperh); + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions I2C Public functions + * @{ + */ + +/** @defgroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Cx peripheral: + + (+) Call the function ald_i2c_init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function ald_i2c_reset() to restore the default configuration + of the selected I2Cx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief I2C Configuration Speed function. + * @param hperh: Pointer to a i2c_handle_t structure that contains. + * the configuration information for the I2C speed. + * @param clk: I2C Peripheral bus clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_speed_init(ald_i2c_handle_t *hperh, uint32_t clk) +{ + int32_t t_scl, t_pre, tmp; + uint8_t scll, sclh, sdadel, scldel; + + if (clk > 72000000) + return ALD_ERROR; + if (hperh->init.module == ALD_I2C_MODULE_SLAVE) { + hperh->init.clk_speed = 400000UL; + } + + if (hperh->init.clk_speed <= 100000UL) { + tmp = clk / 4000000UL; + tmp = tmp >= 16UL ? 16UL : tmp; + clk = clk / tmp; + } + else if (hperh->init.clk_speed <= 500000UL) { + if (clk < 8000000UL) + return ALD_ERROR; + + tmp = clk / 8000000UL; + clk = clk / tmp; + } + else { + if (clk < 12000000UL) + return ALD_ERROR; + + tmp = clk / 12000000UL; + clk = clk / tmp; + } + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_PRESC_MSK, (tmp - 1) << I2C_TIMINGR_PRESC_POSS); + + t_scl = 1000000000UL / hperh->init.clk_speed; + t_pre = 1000000000UL / clk; + + tmp = (t_scl << 4UL) / (t_pre << 1UL); + tmp = ((tmp + 8UL) >> 4UL); + tmp = tmp >= 255UL ? 255UL : tmp; + scll = tmp; + + if (scll < 4) + return ALD_ERROR; + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (scll - 1) << I2C_TIMINGR_SCLL_POSS); + scldel = ((scll << 1) / 3); + scldel = scldel > 16 ? 16 : scldel; + sdadel = (scll / 3) < (scll - scldel - 1) ? (scll / 3) : (scll - scldel - 1); + sdadel = sdadel > 3 ? 3 : sdadel; + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, (scldel - 1) << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, sdadel << I2C_TIMINGR_SDADEL_POSS); + + if (scll > 6) + sclh = scll - 3; + else if (scll > 4) + sclh = 3; + else + sclh = 2; + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (sclh - 1UL) << I2C_TIMINGR_SCLH_POSS); + return ALD_OK; +} +/** + * @brief Initializes the I2C according to the specified parameters + * in the i2c_init_t and initialize the associated handle. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_init(ald_i2c_handle_t *hperh) +{ + uint32_t freqrange = ald_cmu_get_pclk_clock(); + + if (hperh == NULL) + return ALD_ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + assert_param(IS_I2C_MODULE(hperh->init.module)); + + if (hperh->state == ALD_I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_I2C_STATE_BUSY; + + ALD_I2C_DISABLE(hperh); + + if (ALD_OK != i2c_speed_init(hperh, freqrange)) + return ALD_ERROR; + + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NOSTRETCH_MSK, (hperh->init.no_stretch) << I2C_CON1_NOSTRETCH_POS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_GCEN_MSK, (hperh->init.general_call) << I2C_CON1_GCEN_POS); + + if (hperh->init.dual_addr == ALD_I2C_DUALADDR_ENABLE) { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } else { + if (hperh->init.addr_mode == ALD_I2C_ADDR_10BIT) { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1MODE_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + } + else { + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + } + + ALD_I2C_ENABLE(hperh); + + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + return ALD_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_reset(ald_i2c_handle_t *hperh) +{ + if (hperh == NULL) + return ALD_ERROR; + + ALD_I2C_DISABLE(hperh); + + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + __UNLOCK(hperh); + + WRITE_REG(hperh->perh->CON1, 0); + WRITE_REG(hperh->perh->CON2, 0); + WRITE_REG(hperh->perh->ADDR1, 0); + WRITE_REG(hperh->perh->ADDR2, 0); + WRITE_REG(hperh->perh->TIMINGR, 0); + WRITE_REG(hperh->perh->TIMEOUTR, 0); + WRITE_REG(hperh->perh->IDR, ALD_I2C_FLAG_MASK); + WRITE_REG(hperh->perh->ICR, ALD_I2C_FLAG_MASK); + + ALD_I2C_ENABLE(hperh); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) ald_i2c_master_send() + (++) ald_i2c_master_recv() + (++) ald_i2c_slave_send() + (++) ald_i2c_slave_recv() + (++) ald_i2c_mem_write() + (++) ald_i2c_mem_read() + + (#) No-Blocking mode functions with Interrupt are : + (++) ald_i2c_master_send_by_it() + (++) ald_i2c_master_recv_by_it() + (++) ald_i2c_slave_send_by_it() + (++) ald_i2c_slave_recv_by_it() + (++) ald_i2c_mem_write_by_it() + (++) ald_i2c_mem_read_by_it() + + (#) No-Blocking mode functions with DMA are : + (++) ald_i2c_master_send_by_dma() + (++) ald_i2c_master_recv_by_dma() + (++) ald_i2c_slave_send_by_dma() + (++) ald_i2c_slave_recv_by_dma() + (++) ald_i2c_mem_write_by_dma() + (++) ald_i2c_mem_read_by_dma() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) hperh->mem_tx_cplt_cbk() + (++) hperh->mem_rx_cplt_cbk() + (++) hperh->master_tx_cplt_cbk() + (++) hperh->master_rx_cplt_cbk() + (++) hperh->slave_tx_cplt_cbk() + (++) hperh->slave_rx_cplt_cbk() + (++) hperh->error_callback() + +@endverbatim + * @{ + */ +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, timeout); + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) + { + hperh->perh->TXDATA = (*buf++); + size--; + hperh->xfer_count++; + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + + if (((hperh->xfer_count % 0xFFFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + } + else + { + goto ERROR; + } + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t + */ + ald_status_t ald_i2c_master_recv(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, timeout); + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + ALD_I2C_ENABLE(hperh); + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TXE, RESET, timeout) != ALD_OK) + goto ERROR; + + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, timeout) == ALD_ERROR) + goto ERROR; + + while (size > 0) + { + if (i2c_wait_txe_to_timeout(hperh, timeout) == ALD_ERROR) + goto ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TXE, RESET, timeout) != ALD_OK) + goto ERROR; + + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + } + + goto SUCCESS; + +ERROR: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, timeout) == ALD_ERROR) + goto ERROR; + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) == ALD_ERROR) + goto ERROR; + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_HOLDACK_MSK)) + SET_BIT(hperh->perh->CON2, I2C_CON2_ACK_UPD_MSK); + + (*buf++) = hperh->perh->RXDATA; + --size; + hperh->xfer_count++; + } + + goto SUCCESS; + +ERROR: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + return ALD_OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) ; + + if (size <= 0xFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR | ALD_I2C_IT_TC); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return ALD_OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_STOP | ALD_I2C_IT_TXE); + + return ALD_OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_ADDR | ALD_I2C_IT_STOP); + + return ALD_OK; +} + +/** + * @brief Sequential Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_seq_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option) +{ + uint32_t pre_state = 0; + uint32_t it_flag = 0; + + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (hperh->state == ALD_I2C_STATE_READY) { + if ((READ_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK) == I2C_CON2_STOP_MSK) || (option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_FIRST_FRAME)) { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + __UNLOCK(hperh); + return ALD_BUSY; + } + } + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) { + ALD_I2C_ENABLE(hperh); + } + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + hperh->xfer_opt = option; + pre_state = hperh->pre_state; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + + if ((pre_state != ALD_I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS(option))) { + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + it_flag = ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TCR; + + if ((option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_LAST_FRAME) || (option == ALD_I2C_OTHER_AND_LAST_FRAME)) { + it_flag |= ALD_I2C_IT_TC; + + if (size <= 0xFFFF) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + it_flag &= ~ALD_I2C_IT_TCR; + } + } + + ALD_I2C_ENABLE_IT(hperh, it_flag); + + __UNLOCK(hperh); + } else { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Sequential Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_seq_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option) +{ + uint32_t pre_state = 0; + uint32_t it_flag = 0; + + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (hperh->state == ALD_I2C_STATE_READY) + { + if ((READ_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK) == I2C_CON2_STOP_MSK) || (option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_FIRST_FRAME)) { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + __UNLOCK(hperh); + return ALD_BUSY; + } + } + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + ALD_I2C_ENABLE(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + pre_state = hperh->pre_state; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + + if ((pre_state != ALD_I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS(option))) { + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + it_flag = ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR; + if ((option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_LAST_FRAME) || (option == ALD_I2C_OTHER_AND_LAST_FRAME)) + it_flag |= ALD_I2C_IT_TC; + + ALD_I2C_ENABLE_IT(hperh, it_flag); + + __UNLOCK(hperh); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Sequential Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_seq_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option) +{ + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (((hperh->state & ALD_I2C_STATE_LISTEN) == ALD_I2C_STATE_LISTEN) || (hperh->state == ALD_I2C_STATE_READY)) + { + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + ALD_I2C_ENABLE(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX_LISTEN; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + hperh->xfer_opt = option; + + __UNLOCK(hperh); + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_STOP | ALD_I2C_IT_TXE); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Sequential Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_seq_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option) +{ + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (((hperh->state & ALD_I2C_STATE_LISTEN) == ALD_I2C_STATE_LISTEN) || (hperh->state == ALD_I2C_STATE_READY)) + { + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + ALD_I2C_ENABLE(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX_LISTEN; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + hperh->xfer_opt = option; + + __UNLOCK(hperh); + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_ADDR | ALD_I2C_IT_STOP); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Enable the Address listen mode whit Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param addr: Devaddress Target device address + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_abort_it(ald_i2c_handle_t *hperh, uint16_t addr) +{ + UNUSED(addr); + if ((READ_BIT(hperh->perh->STAT, I2C_STAT_BUSY_MSK) != RESET) && (hperh->mode == ALD_I2C_MODE_MASTER)) + { + __LOCK(hperh); + + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->state = ALD_I2C_STATE_ABORT; + + SET_BIT(hperh->perh->CON1, I2C_CON2_STOP_MSK); + hperh->xfer_size = 0; + hperh->xfer_count = 0; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + __UNLOCK(hperh); + return ALD_OK; + } + else + { + return ALD_ERROR; + } +} + +/** + * @brief Enable the Address listen mode whit Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_enablelisten_it(ald_i2c_handle_t *hperh) +{ + if (hperh->state == ALD_I2C_STATE_READY) + { + hperh->state = ALD_I2C_STATE_LISTEN; + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + ALD_I2C_ENABLE(hperh); + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_ADDR); + + return ALD_OK; + } + else + { + return ALD_BUSY; + } +} + +/** + * @brief Disable the Address listen mode whit Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_disablelisten_it(ald_i2c_handle_t *hperh) +{ + if (hperh->state == ALD_I2C_STATE_LISTEN) + { + hperh->pre_state = ((hperh->state) & ALD_I2C_STATE_MSK) | (hperh->mode); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + return ALD_OK; + } + else + { + return ALD_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @note The maximum amount of data to be sent is 0xFF. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent (maximum is 0xFF) + * @param channel: DMA channel as I2C transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFFFF) + size = 0xFFFF; + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_tc_arg = hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFFFF) + size = 0xFFFF; + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return ALD_OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C Transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFFFF) + size = 0xFFFF; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_tc_arg = hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ALD_ERROR) + { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + return ALD_OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFF) + size = 0xFF; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ALD_ERROR) + { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + return ALD_OK; +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != ALD_OK) + goto ERROR; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + while (size > 0) + { + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, timeout)) + goto ERROR; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != ALD_OK) + return ALD_ERROR; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, timeout) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + return ALD_OK; +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh , ALD_I2C_IT_TCR); + + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return ALD_OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address(Maxsiz 0xFF) + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint32_t nbyte = 0; + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_tc_arg = hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + return ALD_OK; +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be read + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint32_t nbyte = 0; + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + } + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @brief Peripheral state and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral state and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval ald_status_t state + */ +ald_i2c_state_t ald_i2c_get_state(ald_i2c_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the I2C error code. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t ald_i2c_get_error(ald_i2c_handle_t *hperh) +{ + return hperh->error_code; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void ald_i2c_ev_irq_handler(ald_i2c_handle_t *hperh) +{ + uint32_t size = hperh->xfer_size - hperh->xfer_count; + + /**< Transmit empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXE) == SET) + { + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + i2c_master_send_txe(hperh); + else if (hperh->mode == ALD_I2C_MODE_SLAVE) + i2c_slave_send_txe(hperh); + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXE); + } + + /**< Receive not empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXNE) == SET) + { + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + i2c_master_recv_rxne(hperh); + else if (hperh->mode == ALD_I2C_MODE_SLAVE) + i2c_slave_recv_rxne(hperh); + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXNE); + } + + /**< Transmit completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TC) == SET) + { + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + { + if (ALD_I2C_MASTER_GET_DIR(hperh) == RESET) + i2c_master_send_tc(hperh); + else + i2c_master_recv_tc(hperh); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TC); + } + + /**< Transmit and reload completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TCR) == SET) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + } + + /**< Address matching interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ADDR) == SET) + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ADDR); + + /**< Stop detection interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_STOP) == SET) + { + i2c_slave_stopf(hperh); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_STOP); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void ald_i2c_er_irq_handler(ald_i2c_handle_t *hperh) +{ + /**< Transmit overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXOV); + hperh->error_code |= ALD_I2C_ERROR_TOV; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + /**< Transmit underrun */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXUD); + hperh->error_code |= ALD_I2C_ERROR_TUD; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Receive overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXOV); + hperh->error_code |= ALD_I2C_ERROR_ROV; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Receive underrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXUD); + hperh->error_code |= ALD_I2C_ERROR_RUD; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< NACK interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_NACK) == SET) + { + if (hperh->xfer_count != hperh->xfer_size) + { + hperh->state |= ALD_I2C_ERROR_AF; + } + else + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_NACK); + return; + } + + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_NACK); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Bus error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_BERR) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_BERR); + hperh->state |= ALD_I2C_ERROR_BERR; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Arbitration loss interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ARLO) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ARLO); + hperh->state |= ALD_I2C_ERROR_ARLO; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< PEC error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_PECE) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_PECE); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Timeout interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TOUT) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TOUT); + hperh->state |= ALD_I2C_ERROR_TIMEOUT; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< SMBus Alert interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ALERT) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ALERT); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void ald_i2c_seq_ev_irq_handler(ald_i2c_handle_t *hperh) +{ + uint32_t size = hperh->xfer_size - hperh->xfer_count; + ald_i2c_state_t current_state = hperh->state; + uint32_t current_opt = hperh->xfer_opt; + uint8_t tmp = 0; + + /**< Address matching interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ADDR) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ADDR); + + if ((hperh->state & ALD_I2C_STATE_LISTEN) == ALD_I2C_STATE_LISTEN) + { + if (hperh->addr_cplt_cbk != NULL) + hperh->addr_cplt_cbk(hperh); + + if (hperh->state == ALD_I2C_STATE_BUSY_TX_LISTEN) + hperh->state = ALD_I2C_STATE_BUSY_TX; + + if (hperh->state == ALD_I2C_STATE_BUSY_RX_LISTEN) + hperh->state = ALD_I2C_STATE_BUSY_RX; + } + } + + /**< Transmit empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXE) == SET) + { + if (hperh->mode == ALD_I2C_MODE_MASTER) + { + if ((hperh->xfer_size == 0) && (current_state == ALD_I2C_STATE_BUSY_TX)) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if ((current_opt != ALD_I2C_LAST_FRAME) && (current_opt != ALD_I2C_FIRST_AND_LAST_FRAME) && (current_opt != ALD_I2C_OTHER_AND_LAST_FRAME)) + { + hperh->pre_state = ALD_I2C_STATE_BUSY_TX; + __UNLOCK(hperh); + } + else + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->pre_state = (uint32_t)ALD_I2C_STATE_NONE; + + __UNLOCK(hperh); + } + + if (hperh->master_tx_cplt_cbk != NULL) + hperh->master_tx_cplt_cbk (hperh); + } + + if (hperh->xfer_count != hperh->xfer_size) + { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + } + else if (hperh->mode == ALD_I2C_MODE_SLAVE) + { + if (hperh->xfer_size > hperh->xfer_count) + { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXE); + } + + /**< Receive not empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXNE) == SET) + { + if ((hperh->state == ALD_I2C_STATE_BUSY_RX) || (hperh->state == ALD_I2C_STATE_BUSY_RX_LISTEN)) + { + if (hperh->xfer_size - hperh->xfer_count > 0) + { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else + { + tmp = hperh->perh->RXDATA; + UNUSED(tmp); + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXNE); + } + + /**< Transmit completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TC) == SET) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->mode = ALD_I2C_MODE_NONE; + hperh->state = ALD_I2C_STATE_READY; + __UNLOCK(hperh); + + if (current_state == ALD_I2C_STATE_MASTER_BUSY_TX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + if (hperh->master_tx_cplt_cbk != NULL) + hperh->master_tx_cplt_cbk (hperh); + } + else if (current_state == ALD_I2C_STATE_SLAVE_BUSY_TX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + if (hperh->slave_tx_cplt_cbk != NULL) + hperh->slave_tx_cplt_cbk (hperh); + } + else if (current_state == ALD_I2C_STATE_MASTER_BUSY_RX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE); + if (hperh->master_rx_cplt_cbk != NULL) + hperh->master_rx_cplt_cbk (hperh); + } + else if (current_state == ALD_I2C_STATE_SLAVE_BUSY_RX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE); + if (hperh->slave_rx_cplt_cbk != NULL) + hperh->slave_rx_cplt_cbk (hperh); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TC); + } + + /**< Transmit and reload completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TCR) == SET) + { + if (size == 0) + { + if (current_state == ALD_I2C_STATE_BUSY_TX) + { + if (hperh->mode == ALD_I2C_MODE_MASTER) + hperh->pre_state = ALD_I2C_STATE_MASTER_BUSY_TX; + else + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_TX; + + hperh->mode = ALD_I2C_MODE_NONE; + hperh->state = ALD_I2C_STATE_READY; + __UNLOCK(hperh); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TCR); + + if (hperh->master_tx_cplt_cbk != NULL) + hperh->master_tx_cplt_cbk (hperh); + } + else if (current_state == ALD_I2C_STATE_BUSY_RX) + { + if (hperh->mode == ALD_I2C_MODE_MASTER) + hperh->pre_state = ALD_I2C_STATE_MASTER_BUSY_RX; + else + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_RX; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR); + + if (hperh->master_rx_cplt_cbk != NULL) + hperh->master_rx_cplt_cbk(hperh); + } + } + else + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + if ((current_opt == ALD_I2C_FIRST_AND_LAST_FRAME) || (current_opt == ALD_I2C_LAST_FRAME) || (current_opt == ALD_I2C_OTHER_AND_LAST_FRAME)) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + } + + /**< Stop detection interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_STOP) == SET) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_RXNE | ALD_I2C_IT_TXE | ALD_I2C_IT_STOP); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_STOP); + + if ((size == 0) && (hperh->error_code == ALD_I2C_ERROR_NONE)) + { + if (hperh->state == ALD_I2C_STATE_BUSY_TX_LISTEN) + { + hperh->pre_state = ALD_I2C_STATE_BUSY_TX_LISTEN; + hperh->state = ALD_I2C_STATE_LISTEN; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->slave_tx_cplt_cbk != NULL) + hperh->slave_tx_cplt_cbk(hperh); + } + if (hperh->state == ALD_I2C_STATE_BUSY_RX_LISTEN) + { + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_RX; + hperh->state = ALD_I2C_STATE_LISTEN; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->slave_rx_cplt_cbk != NULL) + hperh->slave_rx_cplt_cbk(hperh); + } + if (hperh->state == ALD_I2C_STATE_LISTEN) + { + hperh->xfer_opt = ALD_I2C_NO_OPTION_FRAME; + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->listen_cplt_cbk != NULL) + hperh->listen_cplt_cbk(hperh); + } + } + } +} + + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void ald_i2c_seq_er_irq_handler(ald_i2c_handle_t *hperh) +{ + /**< Transmit overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXOV); + hperh->error_code |= ALD_I2C_ERROR_TOV; + } + /**< Transmit underrun */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXUD); + hperh->error_code |= ALD_I2C_ERROR_TUD; + } + + /**< Receive overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXOV); + hperh->error_code |= ALD_I2C_ERROR_ROV; + } + + /**< Receive underrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXUD); + hperh->error_code |= ALD_I2C_ERROR_RUD; + } + + /**< NACK interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_NACK) == SET) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + if ((hperh->mode == ALD_I2C_MODE_SLAVE) && (hperh->xfer_count == hperh->xfer_size) && \ + ((hperh->state == ALD_I2C_STATE_BUSY_TX) || (hperh->state == ALD_I2C_STATE_BUSY_TX_LISTEN) || \ + ((hperh->state == ALD_I2C_STATE_LISTEN) && (hperh->pre_state == ALD_I2C_STATE_SLAVE_BUSY_TX)))) { + if (((hperh->xfer_opt == ALD_I2C_FIRST_AND_LAST_FRAME) || (hperh->xfer_opt == ALD_I2C_LAST_FRAME)) && \ + (hperh->state == ALD_I2C_STATE_LISTEN)) { + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->listen_cplt_cbk != NULL) + hperh->listen_cplt_cbk(hperh); + + } + else if (hperh->state == ALD_I2C_STATE_BUSY_TX) + { + hperh->xfer_opt = ALD_I2C_NO_OPTION_FRAME; + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_TX; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->slave_tx_cplt_cbk != NULL) + hperh->slave_tx_cplt_cbk(hperh); + } + } + else + { + hperh->error_code |= ALD_I2C_ERROR_AF; + if (hperh->mode == ALD_I2C_MODE_MASTER) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_NACK); + } + + /**< Bus error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_BERR) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_BERR); + hperh->state |= ALD_I2C_ERROR_BERR; + } + + /**< Arbitration loss interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ARLO) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ARLO); + hperh->state |= ALD_I2C_ERROR_ARLO; + } + + /**< PEC error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_PECE) == SET) + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_PECE); + + /**< Timeout interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TOUT) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TOUT); + hperh->state |= ALD_I2C_ERROR_TIMEOUT; + } + + /**< SMBus Alert interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ALERT) == SET) + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ALERT); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); +} + +/** + * @brief Enable/disable the specified I2C interrupts. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the i2c interrupt sources to be enabled or disabled. + * @param state: New state of the specified I2C interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_i2c_interrupt_config(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it, type_func_t state) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Get the status of I2C interrupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the I2C interrupt source. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_i2c_get_it_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it) +{ + it_status_t status = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_mask_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * @retval None + */ +void ald_i2c_clear_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + hperh->perh->ICR = flag; + return; +} + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle transmit complete flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_tc(ald_i2c_handle_t *hperh) +{ + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = ALD_I2C_STATE_READY; + + if (hperh->mode == ALD_I2C_MODE_MEM) + { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else + { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + + return ALD_OK; +} + +/** + * @brief Handle transmit empty flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_txe(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_count != hperh->xfer_size) + { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return ALD_OK; +} + +/** + * @brief Handle receive complete for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_tc(ald_i2c_handle_t *hperh) +{ + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR | ALD_I2C_IT_TC); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = ALD_I2C_STATE_READY; + + if (hperh->mode == ALD_I2C_MODE_MEM) + { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else + { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + + return ALD_OK; +} + +/** + * @brief Handle receive not empty for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_rxne(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_size - hperh->xfer_count > 0) + { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else + { + return ALD_OK; + } + + return ALD_OK; +} + +/** + * @brief Handle TXE flag for Slave Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_send_txe(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) + { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return ALD_OK; +} + +/** + * @brief Handle RXNE flag for Slave Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_recv_rxne(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) + { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else + { + return ALD_OK; + } + + return ALD_OK; +} + +/** + * @brief Handle STOPF flag for Slave mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_stopf(ald_i2c_handle_t *hperh) +{ + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_RXNE | ALD_I2C_IT_TXE | ALD_I2C_IT_STOP); + + hperh->mode = ALD_I2C_MODE_NONE; + hperh->error_code = ALD_I2C_ERROR_NONE; + __UNLOCK(hperh); + + if (hperh->state == ALD_I2C_STATE_BUSY_TX) + { + hperh->state = ALD_I2C_STATE_READY; + if ((hperh->slave_tx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_tx_cplt_cbk(hperh); + } + else if (hperh->state == ALD_I2C_STATE_BUSY_RX) + { + hperh->state = ALD_I2C_STATE_READY; + if ((hperh->slave_rx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_rx_cplt_cbk(hperh); + } + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == ALD_I2C_ADDR_7BIT) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == ALD_I2C_ADDR_7BIT) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + uint32_t tmp = hperh->perh->CON2; + i2c_master_req_write(hperh, dev_addr, timeout); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == ALD_I2C_MEMADD_SIZE_8BIT) + { + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else + { + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + return ALD_ERROR; + + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, timeout) != ALD_OK) + { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + return ALD_ERROR; + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + + if ((hperh->state == ALD_I2C_STATE_BUSY_RX) && (hperh->mode == ALD_I2C_MODE_MEM)) + { + tmp = hperh->perh->CON2; + tmp &= ~(I2C_CON2_RELOAD_MSK | I2C_CON2_NBYTES_MSK); + hperh->perh->CON2 = tmp; + + tmp = hperh->perh->CON1; + tmp &= ~I2C_CON1_NBYTES_MSK; + hperh->perh->CON1 = tmp; + } + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + uint32_t tim_count = 0; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != ALD_OK) + { + __UNLOCK(hperh); + return ALD_ERROR; + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == ALD_I2C_MEMADD_SIZE_8BIT) + { + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else + { + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + { + if (hperh->error_code == ALD_I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + return ALD_ERROR; + } + else + { + return ALD_TIMEOUT; + } + } + + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + while (!ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_TXE)) + { + tim_count++; + + if (tim_count > 0xFFFF) + return ALD_TIMEOUT; + } + + return ALD_OK; +} + +/** +* @brief DMA I2C master transmit process complete callback. +* @param argv: I2C handle +* @retval None +*/ +static void i2c_dma_master_send_cplt(void *argv) +{ + ald_i2c_handle_t* hperh = (ald_i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ALD_ERROR) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_send_cplt(void *argv) +{ + ald_i2c_handle_t* hperh = (ald_i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_master_recv_cplt(void *argv) +{ + ald_i2c_handle_t* hperh = (ald_i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ALD_ERROR) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_recv_cplt(void *argv) +{ + ald_i2c_handle_t* hperh = (ald_i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_send_cplt(void *argv) +{ + uint32_t cnt = 0xFFFFFF; + + ald_i2c_handle_t* hperh = (ald_i2c_handle_t*)argv; + + while (cnt--) + { + if ((hperh->perh->STAT & ALD_I2C_STAT_TC) != 0) + break; + } + + if (cnt == 0) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_recv_cplt(void *argv) +{ + uint32_t cnt = 0xFFFFF; + + ald_i2c_handle_t* hperh = (ald_i2c_handle_t*)argv; + + while (cnt--) + { + if ((hperh->perh->STAT & ALD_I2C_STAT_TC) != 0) + break; + } + + if (cnt == 0) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } +} + +/** + * @brief This function handles I2C Communication timeout. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param status: The checked flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_flag_change_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + if (status == RESET) + { + while (ALD_I2C_GET_FLAG(hperh, flag) == RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + else + { + while (ALD_I2C_GET_FLAG(hperh, flag) != RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + return ALD_OK; +} + +/** + * @brief This function handles I2C Communication timeout for Master addressing phase. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_master_addr_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_IT_FLAG(hperh, flag) == RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + { + hperh->error_code = ALD_I2C_ERROR_TIMEOUT; + + return ALD_ERROR; + } + } + + return ALD_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of TXE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_txe_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_TXE) == RESET) + { + if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_ARLO)) + { + hperh->error_code |= ALD_I2C_ERROR_ARLO; + return ALD_ERROR; + } + + if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_NACK) == SET) + { + hperh->error_code |= ALD_I2C_ERROR_AF; + return ALD_ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_ERROR; + } + } + + return ALD_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_rxne_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_RXNE) == RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_ERROR; + } + } + + return ALD_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2s.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2s.c new file mode 100644 index 0000000000..961b980a2e --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_i2s.c @@ -0,0 +1,1042 @@ +/** + ********************************************************************************* + * + * @file ald_I2S.c + * @brief I2S module driver. + * This file provides firmware functions to manage the following + * functionalities of I2S peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2S driver can be used as follows: + + (#) Declare a i2s_handle_t structure, for example: + i2s_handle_t hperh; + + (#) Initialize the I2S low level resources: + (##) Enable the I2Sx interface clock + (##) I2S pins configuration + (+++) Enable the clock for the I2S GPIOs + (+++) Configure these I2S pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_i2s_irq_handler() function in I2S-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Channel length, Data length, Polarity, Standard, Pcm frame, + external clock and Main clock output, Odd factor and Divide clock in the i2s_init_t structure. + + (#) Initialize the I2S module by invoking the ald_i2s_init() API. + + [..] + Circular mode restriction: + (#) When the I2S DMA Pause/Stop features are used, we must use the following APIs + the ald_i2s_dma_pause()/ ald_i2s_dma_stop(). + + * @endverbatim + */ +#include "ald_cmu.h" +#include "ald_i2s.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S module driver + * @{ + */ +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static ald_status_t i2s_wait_status(ald_i2s_handle_t *hperh, ald_i2s_status_t state, flag_status_t status, uint32_t timeout); +static void __i2s_send_by_it(ald_i2s_handle_t *hperh); +static void __i2s_recv_by_it(ald_i2s_handle_t *hperh); +static void __i2s_tx_recv_by_it(ald_i2s_handle_t *hperh); + +static void i2s_dma_send_cplt(void *arg); +static void i2s_dma_recv_cplt(void *arg); + +/** + * @} + */ + +/** @defgroup I2S_Public_Functions I2S Public Functions + * @{ + */ + +/** @defgroup I2S_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the I2Sx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_i2s_init() to configure the selected device with + the selected configuration: + (++) Channel length + (++) Data length + (++) Polarity + (++) Standard + (++) Pcm frame + (++) External clock + (++) Main clock output function + (++) Odd factor + (++) Divide clock + + (+) Call the function ald_i2s_reset() to reset the selected I2Sx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the I2S peripheral. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified I2S module. + * @retval None + */ +void ald_i2s_reset(ald_i2s_handle_t *hperh) +{ + hperh->perh->I2SCFG = 0x0; + hperh->perh->I2SPR = 0x0; + + ALD_I2S_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the I2S mode according to the specified parameters in + * the i2s_init_t and create the associated handle. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_init(ald_i2s_handle_t *hperh) +{ + uint32_t tmp = 0, clk, _div; + + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_CH_LEN(hperh->init.ch_len)); + assert_param(IS_I2S_DATE_LEN(hperh->init.data_len)); + assert_param(IS_I2S_CPOL(hperh->init.polarity)); + assert_param(IS_I2S_STANDARD(hperh->init.standard)); + assert_param(IS_FUNC_STATE(hperh->init.ext_clk_en)); + assert_param(IS_FUNC_STATE(hperh->init.mck_en)); + assert_param(IS_I2S_PCMS(hperh->init.pcm_frame)); + + ald_i2s_reset(hperh); + + tmp |= (hperh->init.ext_clk_en << SPI_I2SPR_EXTCKEN_POS); + + /* Get I2S clock */ + if (hperh->init.ext_clk_en) + clk = hperh->init.ext_clk; + else + clk = ald_cmu_get_pclk_clock(); + + if (hperh->init.mck_en) { + _div = ((clk / hperh->init.sampling) >> 8); + } + else { + if (hperh->init.ch_len == ALD_I2S_WIDE_16) + _div = ((clk / hperh->init.sampling) >> 5); + else + _div = ((clk / hperh->init.sampling) >> 6); + } + + if (_div & 0x1) { + SET_BIT(tmp, SPI_I2SPR_ODD_MSK); + --_div; + } + else { + CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK); + } + + if (hperh->init.standard != ALD_I2S_STD_PCM) + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS); + else + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS); + + hperh->perh->I2SPR = tmp; + + tmp = hperh->perh->I2SCFG; + tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) | + (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) | + (1 << SPI_I2SCFG_I2SMOD_POS)); + hperh->perh->I2SCFG = tmp; + + if (hperh->init.standard == ALD_I2S_STD_PCM) + hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS); + + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->state = ALD_I2S_STATE_READY; + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group2 IO operation functions + * @brief I2S Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the I2S + data transfers. + + [..] The I2S supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA). + + * @endverbatim + * @{ + */ + +/** + * @brief Master mode transmit an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX; + hperh->err_code = ALD_I2S_ERROR_NONE; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + while (size > 0) { + if (i2s_wait_status(hperh, ALD_I2S_STATUS_TXE, SET, timeout) != ALD_OK) { + ALD_I2S_DISABLE(hperh); + + hperh->state = ALD_I2S_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *buf++; + --size; + } + + if ((i2s_wait_status(hperh, ALD_I2S_STATUS_TXE, SET, timeout) != ALD_OK) + || (i2s_wait_status(hperh, ALD_I2S_STATUS_BUSY, RESET, timeout) != ALD_OK)) { + ALD_I2S_DISABLE(hperh); + hperh->state = ALD_I2S_STATE_READY; + return ALD_TIMEOUT; + } + + ALD_I2S_DISABLE(hperh); + hperh->state = ALD_I2S_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Master mode receive an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_RX; + hperh->err_code = ALD_I2S_ERROR_NONE; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + while (size > 0) { + hperh->perh->DATA = 0xffff; + if (i2s_wait_status(hperh, ALD_I2S_STATUS_RXNE, SET, timeout) != ALD_OK) { + ALD_I2S_DISABLE(hperh); + hperh->state = ALD_I2S_STATE_READY; + return ALD_TIMEOUT; + } + + *buf++ = hperh->perh->DATA; + --size; + } + + hperh->state = ALD_I2S_STATE_READY; + return ALD_OK; +} + +/** + * @brief Wraps up master mode transmission in non blocking mode. + * @param hperh: pointer to a i2s_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, ENABLE); + return ALD_OK; +} + +/** + * @brief Master mode receives an amount of data in non blocking mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX_RX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = 0; + hperh->tx_size = size; + hperh->tx_count = size; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, ENABLE); + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, ENABLE); + + return ALD_OK; +} + +/** + * @brief Master mode transmit an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + hperh->hdmatx.cplt_tc_cbk = i2s_dma_send_cplt; + + /* Configure I2S DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = ALD_DMA_MSEL_SPI0; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmatx)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, ENABLE); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Master mode receive an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param dma_ch: DMA channel for I2S receive + * @param _dma_ch: DMA channel for sending clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_RX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + buf[size - 1] = 0xFFFF; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + hperh->hdmatx.cplt_tc_cbk = i2s_dma_send_cplt; + + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&buf[size - 1]; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = ALD_DMA_MSEL_SPI0; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = _dma_ch; + ald_dma_config_basic(&(hperh->hdmatx)); + ald_dma_interrupt_config(_dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, ENABLE); + + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + hperh->hdmarx.cplt_tc_cbk = i2s_dma_recv_cplt; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.perh = DMA; + hperh->hdmarx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = ALD_DMA_MSEL_SPI0; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = dma_ch; + ald_dma_config_basic(&(hperh->hdmarx)); + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, ENABLE); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_pause(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, DISABLE); + + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_resume(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, ENABLE); + + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_stop(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, DISABLE); + + hperh->state = ALD_I2S_STATE_READY; + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group3 Control functions + * @brief I2S Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) Handle interrupt about I2S module. The ald_i2s_irq_handler() function must + be invoked by I2S-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles I2S interrupt request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None + */ +void ald_i2s_irq_handler(ald_i2s_handle_t *hperh) +{ + if (ald_i2s_get_mask_flag_status(hperh, ALD_I2S_IF_RXTH) == SET) { + ald_i2s_clear_flag_status(hperh, ALD_I2S_IF_RXTH); + if ((hperh->state == ALD_I2S_STATE_BUSY_TX_RX) || (hperh->state == ALD_I2S_STATE_BUSY_RX)) + __i2s_recv_by_it(hperh); + } + + if (ald_i2s_get_mask_flag_status(hperh, ALD_I2S_IF_TXE) == SET) { + ald_i2s_clear_flag_status(hperh, ALD_I2S_IF_TXE); + if (hperh->state == ALD_I2S_STATE_BUSY_TX) + __i2s_send_by_it(hperh); + else if (hperh->state == ALD_I2S_STATE_BUSY_TX_RX) + __i2s_tx_recv_by_it(hperh); + + } + + if (hperh->err_code != ALD_I2S_ERROR_NONE) { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief Enables or disables the specified I2S interrupts. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_interrupt_config(ald_i2s_handle_t *hperh, ald_i2s_it_t it, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = (uint32_t)it; + else + hperh->perh->IDR = (uint32_t)it; + + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param req: Specifies the I2S dma request sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_dma_req_config(ald_i2s_handle_t *hperh, ald_i2s_dma_req_t req, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == ALD_I2S_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == ALD_I2S_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified I2S flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref i2s_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_status(ald_i2s_handle_t *hperh, ald_i2s_status_t status) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified I2S interrupt has occurred or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt source to check. + * This parameter can be one of the @ref i2s_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_i2s_get_it_status(ald_i2s_handle_t *hperh, ald_i2s_it_t it) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_mask_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified I2S interrupt flags. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval None + */ +void ald_i2s_clear_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group4 Peripheral State and Errors functions + * @brief I2S State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) ald_i2s_get_state() API can check in run-time the state of the I2S peripheral + (+) ald_i2s_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the I2S state. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status, see @ref i2s_state_t. + */ +ald_i2s_state_t ald_i2s_get_state(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the I2S error code + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval I2S Error Code + */ +uint32_t ald_i2s_get_error(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ +/** + * @} + */ + +/** @defgroup I2S_Private_Functions I2S Private Functions + * @brief I2S Private functions + * @{ + */ +/** + * @brief This function wait I2S status until timeout. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the I2S flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2s_wait_status(ald_i2s_handle_t *hperh, ald_i2s_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((ald_i2s_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + return ALD_TIMEOUT; + } + } + + return ALD_OK; +} + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_send_by_it(ald_i2s_handle_t *hperh) +{ + int cnt = 8000; + + if (hperh->tx_count == 0) { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + if (cnt == 0) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *hperh->tx_buf++; + --hperh->tx_count; + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_recv_by_it(ald_i2s_handle_t *hperh) +{ + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) { + *(hperh->rx_buf++) = hperh->perh->DATA; + --hperh->rx_count; + } + + if (hperh->rx_count == 0) { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_tx_recv_by_it(ald_i2s_handle_t *hperh) +{ + if (hperh->tx_count != 0) { + ald_i2s_clear_flag_status(hperh, ALD_I2S_IF_TXE); + hperh->perh->DATA = 0xffff; + --hperh->tx_count; + if (hperh->tx_count == 0) + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + } +} + +/** + * @brief DMA I2S transmit process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_send_cplt(void *arg) +{ + int cnt = 8000; + ald_i2s_handle_t *hperh = (ald_i2s_handle_t *)arg; + + hperh->tx_count = 0; + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + if (cnt == 0) + hperh->err_code |= ALD_I2S_ERROR_FLAG; + + if (hperh->err_code == ALD_I2S_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA I2S receive process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_recv_cplt(void *arg) +{ + ald_i2s_handle_t *hperh = (ald_i2s_handle_t *)arg; + + hperh->rx_count = 0; + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + if (hperh->err_code == ALD_I2S_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pis.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pis.c new file mode 100644 index 0000000000..beb2097d23 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pis.c @@ -0,0 +1,316 @@ +/** + ********************************************************************************* + * + * @file ald_pis.c + * @brief PIS module driver. + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_pis.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup PIS PIS + * @brief PIS module driver + * @{ + */ +/** @defgroup PIS_Public_Functions PIS Public Functions + * @{ + */ + +/** @defgroup PIS_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Create the PIS mode according to the specified parameters in + * the pis_handle_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_create(ald_pis_handle_t *hperh) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + hperh->consumer_ch = (ald_pis_ch_t)(hperh->init.consumer_trig & 0x0F); + hperh->consumer_con = (ald_pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F); + hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF)); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { + __UNLOCK(hperh); + return ALD_BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + if (hperh->init.producer_clk == hperh->init.consumer_clk) { + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_TSCKS_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_TSCKS_POSS); + } + else { + if (hperh->init.producer_signal == ALD_PIS_OUT_LEVEL) { + if (hperh->init.consumer_clk == ALD_PIS_CLK_PCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_LEVEL_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == ALD_PIS_CLK_HCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + + if (hperh->init.producer_signal == ALD_PIS_OUT_PULSE) { + if (hperh->init.consumer_clk == ALD_PIS_CLK_PCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_PULSE_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == ALD_PIS_CLK_HCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_TSCKS_MSK, hperh->init.consumer_clk << PIS_CH0_CON_TSCKS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + if (hperh->init.input_chan == ALD_PIS_CHAN_INPUT) { + switch (hperh->consumer_con) { + case ALD_PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + case ALD_PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + default: + break; + } + } + + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Destroy the PIS mode according to the specified parameters in + * the pis_init_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_destroy(ald_pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ALD_ERROR; + + __LOCK(hperh); + + CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + + switch (hperh->consumer_con) { + case ALD_PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + case ALD_PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + default: + break; + } + + hperh->state = ALD_PIS_STATE_RESET; + __UNLOCK(hperh); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group2 Operation functions + * @brief PIS output enable or disable functions + * @{ + */ + +/** + * @brief Start the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel enable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_start(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (0x1UL << (uint32_t)ch)); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Stop the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel disable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_stop(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (0x1UL << (uint32_t)ch)); + __UNLOCK(hperh); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions + * @brief PIS State and Errors functions + * @{ + */ + +/** + * @brief Returns the PIS state. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval ALD state + */ +ald_pis_state_t ald_pis_get_state(ald_pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + return hperh->state; +} + +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group4 modulate output functions + * @brief PIS modulate output signal functions + * @{ + */ + +/** + * @brief Config the PIS modulate signal function + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param config: Pointer to a pis_modulate_config_t structure that + * contains the selected target (UART0,UART1,UART2,UART3 or + * LPUART0) how to modulate the target output signal. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_modu_config(ald_pis_handle_t *hperh, ald_pis_modulate_config_t *config) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) { + case ALD_PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART4_TX: + MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXMLVLS_MSK, config->level << PIS_UART4_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXMSS_MSK, config->src << PIS_UART4_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXSIGS_MSK, config->channel << PIS_UART4_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return ALD_OK; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pmu.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pmu.c new file mode 100644 index 0000000000..48bfffc67f --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_pmu.c @@ -0,0 +1,219 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.c + * @brief PMU module driver. + * + * @version V1.0 + * @date 08 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 08 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_pmu.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup PMU PMU + * @brief PMU module driver + * @{ + */ +/** @defgroup PMU_Private_Functions PMU Private Functions + * @{ + */ + +/** + * @brief PMU module interrupt handler + * @retval None + */ +void ald_lvd_irq_handler(void) +{ + SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SYSCFG_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup PMU_Public_Functions PMU Public Functions + * @{ + */ + +/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode + * @brief Low power mode select functions + * + * @verbatim + ============================================================================== + ##### Low power mode select functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get wakeup status. + (+) Clear wakeup status. + + @endverbatim + * @{ + */ + +/** + * @brief Get wakup status. + * @param sr: Status bit. + * @retval Status. + */ +flag_status_t ald_pmu_get_status(ald_pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + + if (READ_BIT(PMU->SR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Clear wakup status. + * @param sr: Status bit. + * @retval None + */ +void ald_pmu_clear_status(ald_pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + SYSCFG_UNLOCK(); + + if (sr == ALD_PMU_SR_WUF) + SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); + else + ;/* do nothing */ + + SYSCFG_LOCK(); + return; +} + +/** + * @} + */ + +/** + * @brief Enter stop mode + * @retval None + */ +void ald_pmu_stop_enter(void) +{ + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, ALD_PMU_LP_STOP << PMU_CR_LPM_POSS); + CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPSTOP_MSK | PMU_CR_BGSTOP_MSK | \ + PMU_CR_STPRTNEN_MSK | PMU_CR_FSTOP_MSK, \ + 1 << PMU_CR_LPSTOP_POS | 1 << PMU_CR_BGSTOP_POS \ + | 1 << PMU_CR_STPRTNEN_POS | 1 << PMU_CR_FSTOP_POS); + /* WKEVNSEL is only for testing, and user should set it to be 0x10. */ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); + SYSCFG_LOCK(); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_DEEP); + + __WFI(); +} + +/** + * @brief Enter sleep mode + * @retval None + */ +void ald_pmu_sleep_enter(void) +{ + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, ALD_PMU_LP_STOP << PMU_CR_LPM_POSS); + /* WKEVNSEL is only for testing, and user should set it to be 0x10. */ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); + SYSCFG_LOCK(); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_LIGHT); + + __WFI(); +} + +/** @addtogroup PMU_Public_Functions_Group2 LVD Configure + * @brief LVD configure functions + * + * @verbatim + ============================================================================== + ##### LVD configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure lvd parameters. + + @endverbatim + * @{ + */ + +/** + * @brief Configure lvd using specified parameters. + * @param sel: LVD threshold voltage. + * @param mode: LVD trigger mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void ald_pmu_lvd_config(ald_pmu_lvd_voltage_sel_t sel, ald_pmu_lvd_trigger_mode_t mode, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDIFS_MSK, mode << PMU_LVDCR_LVDIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_rmu.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_rmu.c new file mode 100644 index 0000000000..5d3b9e3563 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_rmu.c @@ -0,0 +1,156 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.c + * @brief RMU module driver. + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_syscfg.h" +#include "ald_rmu.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup RMU RMU + * @brief RMU module driver + * @{ + */ + +/** @defgroup RMU_Public_Functions RMU Public Functions + * @{ + */ + +/** + * @brief Configure BOR parameters. + * @param flt: filter time. + * @retval None + */ +void ald_rmu_bor_config(ald_rmu_bor_filter_t flt) +{ + assert_param(IS_RMU_BORFLT(flt)); + + SYSCFG_UNLOCK(); + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Get specified reset status + * @param state: Speicifies the type of the reset, + * @retval The status. + */ +uint32_t ald_rmu_get_reset_status(ald_rmu_state_t state) +{ + assert_param(IS_RMU_STATE(state)); + + if (state == ALD_RMU_RST_ALL) + return RMU->RSTSR; + + if (READ_BIT(RMU->RSTSR, state)) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified reset status + * @param state: Specifies the type of the reset, + * @retval None + */ +void ald_rmu_clear_reset_status(ald_rmu_state_t state) +{ + assert_param(IS_RMU_STATE_CLEAR(state)); + + SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Reset peripheral device + * @param perh: The peripheral device, + * @retval None + */ +void ald_rmu_reset_periperal(ald_rmu_peripheral_t perh) +{ + uint32_t idx, pos; + + assert_param(IS_RMU_PERH(perh)); + + idx = ((uint32_t)perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + SYSCFG_UNLOCK(); + + switch (idx) { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; + + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; + + case 2: + WRITE_REG(RMU->APBRSTR, pos); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief System reset request + * @param None + * @retval None + */ +void ald_rmu_reset_system(void) +{ + csi_cpu_reset(MEXSTATUS_RESET_CORE); + + return; +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_spi.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_spi.c new file mode 100644 index 0000000000..96c9f9ce37 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_spi.c @@ -0,0 +1,2032 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief SPI module driver. + * This file provides firmware functions to manage the following + * functionalities of SPI peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI driver can be used as follows: + + (#) Declare a spi_handle_t structure, for example: + spi_handle_t hperh; + + (#) Initialize the SPI low level resources: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_spi_irq_handler() function in SPI-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI module by invoking the ald_spi_init() API. + + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the ald_spi_dma_pause()/ ald_spi_dma_stop(). + + * @endverbatim + */ + +#include "ald_spi.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI module driver + * @{ + */ +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +static void __spi_send_by_it(ald_spi_handle_t *hperh); +static void __spi_recv_by_it(ald_spi_handle_t *hperh); +static void __spi_send_recv_by_it(ald_spi_handle_t *hperh, ald_spi_sr_status_t status); + +static ald_status_t spi_wait_flag_irq(ald_spi_handle_t *hperh, ald_spi_flag_t flag, flag_status_t status, uint32_t timeout); +static void spi_dma_send_cplt(void *arg); +static void spi_dma_recv_cplt(void *arg); +static void spi_dma_send_recv_cplt(void *arg); +/** + * @} + */ + +/** @defgroup SPI_Public_Functions SPI Public Functions + * @{ + */ + +/** @defgroup SPI_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the SPIx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_spi_init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the SPI peripheral. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void ald_spi_reset(ald_spi_handle_t *hperh) +{ + ALD_SPI_DISABLE(hperh); + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; + + ALD_SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the SPI mode according to the specified parameters in + * the SPI_init_t and create the associated handle. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_init(ald_spi_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_SPI_FIRBIT(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + assert_param(IS_SPI_FRAME(hperh->init.frame)); + + ald_spi_reset(hperh); + tmp = hperh->perh->CON1; + + if (hperh->init.mode == ALD_SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_FRF_MSK, hperh->init.frame << SPI_CON2_FRF_POS); + + if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES_RXONLY) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX) { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + else { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = ALD_SPI_ERROR_NONE; + hperh->state = ALD_SPI_STATE_READY; + + ALD_SPI_ENABLE(hperh); + return ALD_OK; +} + +/** + * @brief Config the fifo threshold + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param threshold: The threshold value of fifo. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_fifo_threshold_config(ald_spi_handle_t *hperh, uint8_t threshold) +{ + assert_param(IS_SPI(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_RXFTH_MSK, threshold << SPI_CON2_RXFTH_POSS); + MODIFY_REG(hperh->perh->CON2, SPI_CON2_TXFTH_MSK, threshold << SPI_CON2_TXFTH_POSS); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group2 IO fast functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO fast functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers fast. + + * @endverbatim + * @{ + */ + +/** + * @brief Transmit one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast(ald_spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000, temp; + + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = data; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + cnt = 5000; + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + temp = hperh->perh->DATA; + UNUSED(temp); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Transmit one byte fast in blocking mode(1line). + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast_1line(ald_spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000; + + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = data; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Receive one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: Status, success[0]/failed[-1] + * @retval Data. + */ +uint8_t ald_spi_recv_byte_fast(ald_spi_handle_t *hperh, int *status) +{ + uint16_t cnt = 5000; + + if (hperh->init.mode == ALD_SPI_MODE_MASTER) { + hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + } + + cnt = 5000; + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + *status = cnt == 0 ? - 1 : 0; + + return (uint8_t)hperh->perh->DATA; +} + +/** + * @brief Transmit some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, n_fifo, tmp = 0; + + while (size--) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf++; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + + if(hperh->perh == SPI0) + n_fifo = 16; + else if(hperh->perh == SPI1) + n_fifo = 4; + else + return ALD_ERROR; + + for (i = 0; i < n_fifo; ++i) { + if ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return ALD_OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000; + + while (size--) { + hperh->perh->DATA = 0xFF; + cnt = 8000; + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + if (cnt) + *buf++ = (uint8_t)hperh->perh->DATA; + else + return ALD_TIMEOUT; + } + + return ALD_OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + + *buf++ = (uint8_t)hperh->perh->DATA; + } + + return ALD_OK; +} + +/** + * @brief Transmit some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, n_fifo, tmp = 0; + + while (size--) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + + if(hperh->perh == SPI0) + n_fifo = 16; + else if(hperh->perh == SPI1) + n_fifo = 4; + else + return ALD_ERROR; + + for (i = 0; i < n_fifo; ++i) { + if ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return ALD_OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000; + + while (size--) { + hperh->perh->DATA = 0xFFFF; + cnt = 8000; + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + if (cnt) { + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + else { + return ALD_TIMEOUT; + } + } + + return ALD_OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group3 IO operation functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + + * @endverbatim + * @{ + */ +/** + * @brief Transmit an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_SPI_STATE_BUSY_TX; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + while (size > 1) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + ++buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + } + + --size; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.crc_calc) { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + } + + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + } + } + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + while ((hperh->perh->STAT & ALD_SPI_STATUS_BUSY) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + while ((spi_get_status(hperh, ALD_SPI_STATUS_RXNE)) != RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; +timeout: + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_TIMEOUT; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + if (hperh->init.mode == ALD_SPI_MODE_MASTER) + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + while (size > 0) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + *buf = hperh->perh->DATA; + ++buf; + } + else { + *(uint16_t *)buf = hperh->perh->DATA; + buf += 2; + } + + --size; + } + + if (hperh->init.crc_calc) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXTH) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + + if ((hperh->perh->RIF & ALD_SPI_IF_CRCERR) != RESET) { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ALD_SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + hperh->state = ALD_SPI_STATE_READY; + + return ALD_ERROR; + } + } + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; + +timeout: + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_TIMEOUT; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (hperh->init.dir != ALD_SPI_DIRECTION_2LINES) + return ALD_ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_SPI_STATE_BUSY_TX_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + while (size > 1) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + ++tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + tx_buf += 2; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + *rx_buf = (uint8_t)hperh->perh->DATA; + ++rx_buf; + } + else { + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + rx_buf += 2; + } + + --size; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + } + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + } + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + *rx_buf = (uint8_t)hperh->perh->DATA; + else + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + + if (hperh->init.crc_calc) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET) { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ALD_SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + hperh->state = ALD_SPI_STATE_READY; + + return ALD_ERROR; + } + } + + while ((hperh->perh->STAT & ALD_SPI_STATUS_BUSY) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; +timeout: + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_TIMEOUT; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a spi_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_TX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES) && (hperh->init.mode == ALD_SPI_MODE_MASTER)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX) + ALD_SPI_1LINE_RX(hperh); + + if (hperh->init.crc_calc == ENABLE) { + ALD_SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, ENABLE); + } + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, ENABLE); + + if (hperh->init.data_size <= ALD_SPI_DATA_SIZE_8) { + *((uint8_t *)&(hperh->perh->DATA)) = 0xFF; + } + else { + *((uint16_t *)&(hperh->perh->DATA)) = 0xFFFF; + } + + return ALD_OK; +} + +/** + * @brief Transmit and Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_it(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ALD_ERROR; + + if (hperh->init.mode == ALD_SPI_MODE_SLAVER) + { + if ((spi_get_status(hperh, ALD_SPI_STATUS_TXE) == RESET) || (spi_get_status(hperh, ALD_SPI_STATUS_RXNE) != RESET)) + { + SYSCFG_UNLOCK(); + + if (hperh->perh == SPI0) + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_SPI0RST_MSK); + else if (hperh->perh == SPI1) + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_SPI1RST_MSK); + else + return ALD_ERROR; + + SYSCFG_LOCK(); + + ald_spi_reset(hperh); + ald_spi_init(hperh); + } + } + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_TX_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) { + ALD_SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, ENABLE); + } + + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX)) + ALD_SPI_ENABLE(hperh); + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, ENABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, ENABLE); + + return ALD_OK; +} + +/** + * @brief Transmit an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_TX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE) + ALD_SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + hperh->hdmatx.cplt_tc_cbk = spi_dma_send_cplt; + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + ALD_SPI_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint16_t tmp_rx = 0xB1B2; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX) + ALD_SPI_1LINE_RX(hperh); + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES) && (hperh->init.mode == ALD_SPI_MODE_MASTER)) { + __UNLOCK(hperh); + return ALD_ERROR; + } + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + hperh->hdmarx.cplt_tc_cbk = spi_dma_recv_cplt; + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + + ald_dma_interrupt_config(ALD_DMA_CH_6, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&tmp_rx; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = ALD_DMA_CH_6; + ald_dma_config_basic(&(hperh->hdmatx)); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX)) + ALD_SPI_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Transmit and Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data buffer + * @param rx_buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param tx_channel: DMA channel as SPI transmit + * @param rx_channel: DMA channel as SPI receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY && hperh->state != ALD_SPI_STATE_BUSY_RX) + return ALD_BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmatx.cplt_tc_arg = NULL; + hperh->hdmatx.cplt_tc_cbk = NULL; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + hperh->hdmarx.cplt_tc_cbk = spi_dma_send_recv_cplt; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, ENABLE); + + ald_dma_interrupt_config(tx_channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + ald_dma_interrupt_config(rx_channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = rx_channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_pause(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_resume(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_stop(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group4 Control functions + * @brief SPI Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must + be invoked by SPI-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles SPI interrupt request. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval None + */ +void ald_spi_irq_handler(ald_spi_handle_t *hperh) +{ + if ((hperh->state == ALD_SPI_STATE_BUSY_RX) || (hperh->state == ALD_SPI_STATE_BUSY_TX)) { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXTH) != RESET)) + __spi_recv_by_it(hperh); + + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET)) + __spi_send_by_it(hperh); + } + + else if (hperh->state == ALD_SPI_STATE_BUSY_TX_RX) { + if (hperh->init.mode == ALD_SPI_MODE_SLAVER) { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_TXE); + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_RXNE); + } + else { + if (hperh->rx_size == hperh->tx_count) { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_TXE); + } + else { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET) + && (ald_spi_get_it_status(hperh, ALD_SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_TXE_RXNE); + } + } + } + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET) { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + } + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_MODF) != RESET) { + hperh->err_code |= ALD_SPI_ERROR_MODF; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_MODF); + } + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_FRE) != RESET) { + hperh->err_code |= ALD_SPI_ERROR_FRE; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_FRE); + + } + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXOV) != RESET) { + if (hperh->state != ALD_SPI_STATE_BUSY_TX) { + hperh->err_code |= ALD_SPI_ERROR_TXOV; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXOV); + } + } + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXOV) != RESET) { + if (hperh->state != ALD_SPI_STATE_BUSY_RX) { + hperh->err_code |= ALD_SPI_ERROR_RXOV; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_RXOV); + } + } + + return; +} + +/** + * @brief Enables or disables the specified SPI interrupts. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref spi_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_interrupt_config(ald_spi_handle_t *hperh, ald_spi_it_t it, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER |= (uint32_t)it; + else + hperh->perh->IDR |= (uint32_t)it; + + return; +} + +/** + * @brief Configure the specified SPI speed. + * @param hperh: Pointer to a spi_handle_t structure. + * @param speed: Specifies the SPI speed. + * This parameter can be one of the @ref spi_baud_t. + * @retval None + */ +void ald_spi_speed_config(ald_spi_handle_t *hperh, ald_spi_baud_t speed) +{ + uint32_t tmp = 0; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a spi_handle_t structure. + * @param req: Specifies the SPI dma request sources to be enabled or disabled. + * This parameter can be one of the @ref spi_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_dma_req_config(ald_spi_handle_t *hperh, ald_spi_dma_req_t req, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == ALD_SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == ALD_SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified SPI state flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref spi_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_status(ald_spi_handle_t *hperh, ald_spi_status_t status) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified SPI interrupt has occurred or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt source to check. + * This parameter can be one of the @ref spi_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_spi_get_it_status(ald_spi_handle_t *hperh, ald_spi_it_t it) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified SPI flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_spi_get_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified SPI pending flags. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval None + */ +void ald_spi_clear_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + hperh->perh->ICR |= flag; + return; +} + +/** + * @brief This function handles SPI communication timeout in interrupt function. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_flag_irq(ald_spi_handle_t *hperh, ald_spi_flag_t flag, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + + if (timeout) + return ALD_OK; + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, DISABLE); + + return ALD_TIMEOUT; +} + +static ald_status_t spi_wait_bsy_flag(ald_spi_handle_t *hperh, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout)); + + if (timeout) + return ALD_OK; + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, DISABLE); + + return ALD_TIMEOUT; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group5 Peripheral State and Errors functions + * @brief SPI State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral + (+) ald_spi_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the SPI state. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval ALD state + */ +ald_spi_state_t ald_spi_get_state(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the SPI error code + * @param hperh: Pointer to a spi_handle_t structure. + * @retval SPI Error Code + */ +uint32_t ald_spi_get_error(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions SPI Private Functions + * @brief SPI Private functions + * @{ + */ + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_by_it(ald_spi_handle_t *hperh) +{ + uint16_t temp; + + if (hperh->tx_count == 0) { + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES) { + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXOV); + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != ALD_OK) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + while ((spi_get_status(hperh, ALD_SPI_STATUS_RXNE)) != RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXE); + + if (hperh->tx_count == 1) { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } + } + else { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + } + + --hperh->tx_count; + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_recv_by_it(ald_spi_handle_t *hperh) +{ + uint16_t temp; + + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_RXTH); + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + if (hperh->init.data_size <= ALD_SPI_DATA_SIZE_8) { + hperh->perh->DATA = 0xff; + } + else { + hperh->perh->DATA = 0xffff; + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: SR.TXE or SR.RXNE set. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_recv_by_it(ald_spi_handle_t *hperh, ald_spi_sr_status_t status) +{ + if (hperh->rx_count != 0) { + if ((status == ALD_SPI_SR_RXNE) || (status == ALD_SPI_SR_TXE_RXNE)) { + while (spi_get_status(hperh, ALD_SPI_STATUS_RXTH) != RESET) { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + --hperh->rx_count; + } + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_RXTH); + } + } + + if (hperh->tx_count != 0) { + if ((status == ALD_SPI_SR_TXE) || (status == ALD_SPI_SR_TXE_RXNE)) { + if (hperh->tx_count == 1) { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } + + --hperh->tx_count; + } + else { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + } + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXE); + } + } + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_send_cplt(void *arg) +{ + uint16_t delay, temp; + ald_spi_handle_t *hperh = (ald_spi_handle_t *)arg; + + hperh->tx_count = 0; + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + while ((spi_get_status(hperh, ALD_SPI_STATUS_RXNE)) != RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXOV); + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + if (hperh->err_code == ALD_SPI_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI receive process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_recv_cplt(void *arg) +{ + uint32_t tmp; + ald_spi_handle_t *hperh = (ald_spi_handle_t *)arg; + + hperh->rx_count = 0; + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, ALD_SPI_IF_RXTH, SET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, ALD_SPI_ERROR_CRC); + ALD_SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + } + } + + if (hperh->err_code == ALD_SPI_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit and receive process complete callback. + * @param arg: Pointer to a SPI_handle_t structure. + * @retval None + */ +static void spi_dma_send_recv_cplt(void *arg) +{ + uint32_t tmp; + uint16_t delay; + ald_spi_handle_t *hperh = (ald_spi_handle_t *)arg; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, ALD_SPI_IF_RXTH, SET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, ALD_SPI_ERROR_CRC); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + } + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = ALD_SPI_STATE_READY; + + if (hperh->err_code == ALD_SPI_ERROR_NONE) { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_timer.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_timer.c new file mode 100644 index 0000000000..801788d2f2 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_timer.c @@ -0,0 +1,3642 @@ +/** + ********************************************************************************* + * + * @file ald_timer.c + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include +#include "ald_timer.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup TIMER TIMER + * @brief TIMER module driver + * @{ + */ + +/** @defgroup TIMER_Private_Functions TIMER Private Functions + * @{ + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, ald_timer_base_init_t *init); +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, ald_timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, ald_timer_channel_t ch, type_func_t state); +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, ald_timer_etr_psc_t psc, ald_timer_clock_polarity_t polarity, uint32_t filter); +static void timer_slave_set_config(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); + +static void timer_dma_oc_cplt(void *arg); +static void timer_dma_capture_cplt(void *arg); +static void timer_dma_period_elapse_cplt(void *arg); +static void timer_dma_msel(TIMER_TypeDef *hperh, ald_dma_config_t *config); + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions TIMER Public Functions + * @{ + */ + +/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions + * @brief Time Base functions + * + * @verbatim + ============================================================================== + ##### Timer Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER base. + (+) Reset the TIMER base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Time base Unit according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_base_init(ald_timer_handle_t *hperh) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = ALD_TIMER_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Reset the TIMER base peripheral + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +void ald_timer_base_reset(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = ALD_TIMER_STATE_BUSY; + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = ALD_TIMER_STATE_BUSY; + ALD_TIMER_ENABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @brief Stops the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = ALD_TIMER_STATE_BUSY; + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @brief Starts the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_UPDATE, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_UPDATE, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. +*/ +ald_status_t ald_timer_base_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + if ((hperh->state == ALD_TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_period_elapse_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.dst = (void *)&hperh->perh->AR; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_UPDATE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_UPDATE, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Stops the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @retval None +*/ +void ald_timer_base_stop_by_dma(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_UPDATE, DISABLE); + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions + * @brief Time Output Compare functions + * + * @verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_init(ald_timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch : TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, ENABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, ENABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, DISABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + if ((hperh->state == ALD_TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + break; + + case ALD_TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + break; + + case ALD_TIMER_CHANNEL_4: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + ALD_TIMER_ENABLE(hperh); + return ALD_OK; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None +*/ +void ald_timer_oc_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, DISABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group3 TIMER PWM functions + * @brief TIMER PWM functions + * + * @verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER PWM Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_init(ald_timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_start(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_stop(hperh, ch); + return; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_start_by_it(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_stop_by_it(hperh, ch); + return; +} + +/** + * @brief Starts the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); +} + +/** + * @brief Stops the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_stop_by_dma(hperh, ch); + return; +} + +/** + * @brief Set the PWM freq. + * @param hperh: TIMER handle + * @param freq: PWM freq to set + * @retval None + */ +void ald_timer_pwm_set_freq(ald_timer_handle_t *hperh, uint32_t freq) +{ + uint32_t _arr; + + if (freq == 0) + return; + + _arr = ald_cmu_get_pclk_clock() / (hperh->init.prescaler + 1) / freq - 1; + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; +} + +/** + * @brief Set the PWM duty. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param duty: PWM duty to set [0, 100] + * @retval None + */ +void ald_timer_pwm_set_duty(ald_timer_handle_t *hperh, ald_timer_channel_t ch, uint16_t duty) +{ + uint32_t tmp = (hperh->init.period + 1) * duty / 100; + + if (ch == ALD_TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == ALD_TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == ALD_TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == ALD_TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); +} + +/** + * @brief Set capture the PWM. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be captured the PWM + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_pwm_set_input(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, ALD_TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, ALD_TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, ALD_TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, ALD_TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions + * @brief Time Input Capture functions + * + * @verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Input Capture Time base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_init(ald_timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, ENABLE); + break; + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, ENABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, DISABLE); + break; + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The destination Buffer address. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + if ((hperh->state == ALD_TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.circle_mode = ENABLE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + break; + + case ALD_TIMER_CHANNEL_3: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + break; + + case ALD_TIMER_CHANNEL_4: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_ENABLE(hperh); + return ALD_OK; +} + +/** + * @brief Stops the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + case ALD_TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + case ALD_TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, DISABLE); + break; + case ALD_TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions + * @brief Time One Pulse functions + * + * @verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER One Pulse Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @param mode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated. + * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_init(ald_timer_handle_t *hperh, ald_timer_op_mode_t mode) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = ALD_TIMER_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Starts the TIMER One Pulse signal generation. + * @param hperh: TIMER One Pulse handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER One Pulse signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation in interrupt mode. + * @param hperh : TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions + * @brief TIMER Encoder functions + * + * @verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_init(ald_timer_handle_t *hperh, ald_timer_encoder_init_t *config) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + + hperh->state = ALD_TIMER_STATE_READY; + return ALD_OK; +} + +/** + * @brief Starts the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + break; + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + break; + } + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + break; + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + break; + } + + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + } + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + } + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @param buf1: The destination Buffer address. Reading data from CCR1. + * @param buf2: The destination Buffer address. Reading data from CCR2. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch1: Channel of DMA. + * @param dma_ch2: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + if ((hperh->state == ALD_TIMER_STATE_READY)) { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ALD_ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + if (hperh->hdma2.perh == NULL) + hperh->hdma2.perh = DMA; + + hperh->state = ALD_TIMER_STATE_BUSY; + hperh->hdma1.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch1, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.dst = (void *)buf2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + hperh->hdma1.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch2, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ALD_TIMER_ENABLE(hperh); + break; + + default: + hperh->hdma2.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma2.cplt_tc_arg = (void *)hperh; + memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(ald_dma_config_t)); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch1, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + + hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma2.config.dst = (void *)buf2; + hperh->hdma2.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + hperh->hdma2.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma2); + ald_dma_interrupt_config(dma_ch2, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ALD_TIMER_ENABLE(hperh); + break; + } + + return ALD_OK; +} + +/** + * @brief Stops the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + } + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions + * @brief TIMER Hall Sensor functions + * + * @verbatim + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_init(ald_timer_handle_t *hperh, ald_timer_hall_sensor_init_t *config) +{ + ald_timer_oc_init_t oc; + + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, ALD_TIMER_IC_SEL_TRC, config->filter); + + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + + oc.oc_mode = ALD_TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = ALD_TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = ALD_TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = ALD_TIMER_OC_IDLE_RESET; + oc.ocn_idle = ALD_TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return ALD_OK; +} +/** + * @brief Starts the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @param buf: The destination Buffer address. Reading data from CCR1. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + if ((hperh->state == ALD_TIMER_STATE_READY)) { + if (((uint32_t)buf == 0) || (len == 0)) + return ALD_ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->state = ALD_TIMER_STATE_BUSY; + hperh->hdma1.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return ALD_OK; +} +/** + * @brief Stops the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_dma(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions + * @brief TIMER complementary output compare functions + * + * @verbatim + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, ENABLE); + break; + default: + break; + } + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, DISABLE); + break; + default: + break; + } + + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NE_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NE_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NE_MSK)))) { + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_BREAK, DISABLE); + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_ocn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + if ((hperh->state == ALD_TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.channel = dma_ch; + hperh->hdma1.config.msel = ALD_DMA_MSEL_AD16C4T; + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + break; + + case ALD_TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; + } + + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, DISABLE); + break; + default: + break; + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions + * @brief TIMER complementary PWM functions + * + * @verbatim + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_pwmn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop_by_dma(hperh, ch); +} + +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions + * @brief TIMER complementary one pulse functions + * + * @verbatim + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group11 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead timere. + (+) Configure Master and the Slave synchronization. + (+) Handle TIMER interrupt. + (+) Get TIMER compare register's vale. + (+) Configure TIMER interrupt ENABLE/DISABLE. + (+) Get TIMER interrupt source status. + (+) Get TIMER interrupt flag status. + (+) Clear TIMER interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare Channels according to the specified + * parameters in the timer_oc_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Output Compare configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_config_channel(ald_timer_handle_t *hperh, ald_timer_oc_init_t* config, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; + + case ALD_TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; + + case ALD_TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; + + case ALD_TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; + + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Initializes the TIMER Input Capture Channels according to the specified + * parameters in the timer_ic_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Input Capture configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_config_channel(ald_timer_handle_t *hperh, ald_timer_ic_init_t* config, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case ALD_TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case ALD_TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Initializes the TIMER One Pulse Channels according to the specified + * parameters in the timer_one_pulse_init_t. + * @param hperh: TIMER handle + * @param config: TIMER One Pulse configuration structure + * @param ch_out: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @param ch_in: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_config_channel(ald_timer_handle_t *hperh, ald_timer_one_pulse_init_t *config, + ald_timer_channel_t ch_out, ald_timer_channel_t ch_in) +{ + ald_timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) { + case ALD_TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + case ALD_TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + default: + break; + } + + switch (ch_in) { + case ALD_TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param hperh: TIMER handle + * @param config: pointer to a TIMER_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIMER peripheral. + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_oc_ref_clear(ald_timer_handle_t *hperh, ald_timer_clear_input_config_t *config, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_CHNREF_CLEAR(config->clrsel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (config->source == ALD_TIMER_INPUT_NONE) { + timer_etr_set_config(hperh->perh, ALD_TIMER_ETR_PSC_DIV1, ALD_TIMER_CLK_POLARITY_NO_INV, 0); + } + else { + timer_etr_set_config(hperh->perh, config->psc, + (ald_timer_clock_polarity_t)config->polarity, config->filter); + } + + if (config->clrsel == ALD_TIMER_CHNREF_CLR_CMP_IN) { + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_OCCS_MSK); + } + else { + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_OCCS_MSK); + } + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case ALD_TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case ALD_TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; + } + + return ALD_OK; +} + +/** + * @brief Configures the clock source to be used + * @param hperh: TIMER handle + * @param config: pointer to a timer_clock_config_t structure that + * contains the clock source information for the TIMER peripheral. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_clock_source(ald_timer_handle_t *hperh, ald_timer_clock_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) { + case ALD_TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case ALD_TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case ALD_TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param hperh: TIMER handle. + * @param ti1_select: Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg 0: The TIMERx_CH1 pin is connected to TI1 input + * @arg 1: The TIMERx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_ti1_input(ald_timer_handle_t *hperh, uint32_t ti1_select) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return ALD_OK; +} + +/** + * @brief Configures the TIMER in Slave mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Configures the TIMER in Slave mode in interrupt mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync_by_it(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Generate a software event + * @param hperh: TIMER handle + * @param event: specifies the event source. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_generate_event(ald_timer_handle_t *hperh, ald_timer_event_source_t event) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param hperh: TIMER handle. + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval Captured value + */ +uint32_t ald_timer_read_capture_value(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + uint32_t tmp; + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + case ALD_TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + case ALD_TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + case ALD_TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + default: + tmp = hperh->perh->CCVAL1; + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; +} + +/** + * @brief Sets TIMER output mode. + * @param hperh: TIMER handle. + * @param mode: TIMER output mode. + * @param ch: TIMER Channels. + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval None + */ +void ald_timer_set_output_mode(ald_timer_handle_t *hperh, ald_timer_oc_mode_t mode, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + case ALD_TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + case ALD_TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + default: + break; + } + + return; +} + +/** + * @brief Configure the channel in commutation event. + * @param hperh: TIMER handel + * @param config: Parameters of the channel. + * @retval None + */ +void ald_timer_com_change_config(ald_timer_handle_t *hperh, ald_timer_com_channel_config_t *config) +{ + uint32_t cm1, cm2, cce; + + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; + + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); + + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Configure the TIMER commutation event sequence. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi) +{ + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + + return; +} + +/** + * @brief Configure the TIMER commutation event sequence with interrupt. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config_it(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi) +{ + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_COM, ENABLE); +} + +/** + * @brief Configure the break, dead timere, lock level state. + * @param hperh: TIMER handle + * @param config: Pointer to the timer_break_dead_timere_t structure. + * @retval None + */ +void ald_timer_break_dead_time_config(ald_timer_handle_t *hperh, ald_timer_break_dead_time_t *config) +{ + uint32_t tmp; + + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); + + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); + + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Configure the master mode + * @param hperh: TIMER handle + * @param config: Pointer to the timer_master_config_t structure. + * @retval None + */ +void ald_timer_master_sync_config(ald_timer_handle_t *hperh, ald_timer_master_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); + + hperh->state = ALD_TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @brief This function handles TIMER interrupts requests. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_irq_handler(ald_timer_handle_t *hperh) +{ + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC1)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC1); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 2 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC2)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC2); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 3 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC3)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC3); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 4 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC4)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC4); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_UPDATE)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_BREAK)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_TRIGGER)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_COM)) { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; +} + +/** + * @brief Configure DMA request source. + * @param hperh: TIMER handle + * @param req: DMA request source. + * @param state: New state of the specified DMA request. + * @retval None + */ +void ald_timer_dma_req_config(ald_timer_handle_t *hperh, ald_timer_dma_req_t req, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->DMAEN, req); + else + CLEAR_BIT(hperh->perh->DMAEN, req); + + return; +} + +/** + * @brief Enable/disable the specified TIMER interrupts. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the timer interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref timer_it_t. + * @param state: New state of the specified TIMER interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_timer_interrupt_config(ald_timer_handle_t *hperh, ald_timer_it_t it, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IER, it); + else + SET_BIT(hperh->perh->IDR, it); + + return; +} + +/** + * @brief Get the status of TIMER interrupt source. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the TIMER interrupt source. + * This parameter can be one of the @ref timer_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_timer_get_it_status(ald_timer_handle_t *hperh, ald_timer_it_t it) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** + * @brief Get the status of TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_timer_get_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval None + */ +void ald_timer_clear_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group12 Peripheral State functions + * @brief Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-timere the status of the peripheral + and the data flow. + + @endverbatim + * @{ + */ + +/** + * @brief Return the TIMER Base state + * @param hperh: TIMER handle + * @retval TIMER peripheral state + */ +ald_timer_state_t ald_timer_get_state(ald_timer_handle_t *hperh) +{ + return hperh->state; +} +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup TIMER_Private_Functions + * @{ + */ + +/** + * @brief TIMER DMA out compare complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_oc_cplt(void *arg) +{ + ald_timer_handle_t *hperh = (ald_timer_handle_t *)arg; + + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Capture complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_capture_cplt(void *arg) +{ + ald_timer_handle_t *hperh = (ald_timer_handle_t *)arg; + + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Period Elapse complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_period_elapse_cplt(void *arg) +{ + ald_timer_handle_t *hperh = (ald_timer_handle_t *)arg; + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Time Base configuration + * @param TIMERx: TIMER periheral + * @param init: TIMER Base configuration structure + * @retval None + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, ald_timer_base_init_t *init) +{ + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + + if (init->mode == ALD_TIMER_CNT_MODE_UP || init->mode == ALD_TIMER_CNT_MODE_DOWN) { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } + + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); + + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); + + return; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, ALD_TIMER_CHANNEL_1)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } + + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, ALD_TIMER_CHANNEL_2)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } + + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, ALD_TIMER_CHANNEL_3)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } + + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } + + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); +} + +/** + * @brief Enables or disables the TIMER Capture Compare Channel x. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @param state: specifies the TIMER Channel CCxE bit new state. + * @retval None + */ +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, ald_timer_channel_t ch, type_func_t state) +{ + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; + + case ALD_TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; + + case ALD_TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; + + default: + break; + } +} +/** + * @brief Enables or disables the TIMER Capture Compare Channel xN. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @param state: specifies the TIMER Channel CCxNE bit new state. + * @retval None + */ +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, ald_timer_channel_t ch, type_func_t state) +{ + switch (ch) { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK, state << TIMER_CCEP_CC1NE_POS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK, state << TIMER_CCEP_CC2NE_POS); + break; + + case ALD_TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK, state << TIMER_CCEP_CC3NE_POS); + break; + + default: + break; + } + +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); + + return; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); + return; +} + +/** + * @brief Configures the TIMERx External Trigger (ETR). + * @param TIMERx: Select the TIMER peripheral + * @param psc: The external Trigger Prescaler. + * @param polarity: The external Trigger Polarity. + * @param filter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, ald_timer_etr_psc_t psc, ald_timer_clock_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; +} + +/** + * @brief Time Slave configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: The slave configuration structure + * @retval None + */ +static void timer_slave_set_config(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config) +{ + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + + switch (config->input) { + case ALD_TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; + + case ALD_TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; + + case ALD_TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + break; + + case ALD_TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + break; + + default: + break; + } +} + +/** + * @brief Timer DMA msel signal configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: DMA configuration structure + * @retval None + */ +static void timer_dma_msel(TIMER_TypeDef *hperh, ald_dma_config_t *config) +{ + if (hperh == AD16C4T) + config->msel = ALD_DMA_MSEL_AD16C4T; + if (hperh == BS16T) + config->msel = ALD_DMA_MSEL_BS16T; + if (hperh == GP16C4T0) + config->msel = ALD_DMA_MSEL_GP16C4T0; + if (hperh == GP16C4T1) + config->msel = ALD_DMA_MSEL_GP16C4T1; + if (hperh == GP16C4T2) + config->msel = ALD_DMA_MSEL_GP16C4T2; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_uart.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_uart.c new file mode 100644 index 0000000000..daf810a58e --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_uart.c @@ -0,0 +1,1458 @@ +/** + ********************************************************************************* + * + * @file ald_uart.c + * @brief UART module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART driver can be used as follows: + + (#) Declare a uart_handle_t handle structure. + + (#) Initialize the UART low level resources: + (##) Enable the UARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() + and ald_uart_recv_by_it() APIs): + (+++) Configure the uart interrupt priority. + (+++) Enable the NVIC UART IRQ handle. + (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() + and ald_uart_recv_by_dma() APIs): + (+++) Select the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the hperh Init structure. + + (#) Initialize the UART registers by calling the ald_uart_init() API. + + [..] + Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using ald_uart_send() + (+) Receive an amount of data in blocking mode using ald_uart_recv() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + (+) Pause the DMA Transfer using ald_uart_dma_pause() + (+) Resume the DMA Transfer using ald_uart_dma_resume() + (+) Stop the DMA Transfer using ald_uart_dma_stop() + + @endverbatim + ****************************************************************************** + */ + +#include "ald_uart.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup UART UART + * @brief UART module driver + * @{ + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @brief UART Private functions + * @{ + */ + +/** + * @brief DMA uart transmit process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_send_cplt(void *arg) +{ + ald_uart_handle_t *hperh = (ald_uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, DISABLE); + hperh->tx_count = 0; + ald_uart_interrupt_config(hperh, ALD_UART_IT_TBC, ENABLE); + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + return; +} + +/** + * @brief DMA uart receive process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_recv_cplt(void *arg) +{ + uint32_t stat = 0; + + ald_uart_handle_t *hperh = (ald_uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, DISABLE); + hperh->rx_count = 0; + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + stat = hperh->perh->STAT; + + /* Handle parity error */ + if ((READ_BIT(stat, ALD_UART_STATUS_PERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, ALD_UART_STATUS_FERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, ALD_UART_STATUS_RFOERR)) != RESET) { + hperh->err_code |= ALD_UART_ERROR_ORE; + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return; +} + +/** + * @brief This function handles uart Communication Timeout. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: specifies the uart flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t uart_wait_flag(ald_uart_handle_t *hperh, ald_uart_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ALD_ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((ald_uart_get_status(hperh, flag)) != status) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_send_by_it(ald_uart_handle_t *hperh) +{ + if ((hperh->state & ALD_UART_STATE_TX_MASK) == 0x0) + return ALD_BUSY; + + hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF); + hperh->tx_count++; + + if (hperh->tx_count >= hperh->tx_size) + { + ald_uart_interrupt_config(hperh, ALD_UART_IT_TFEMPTY, DISABLE); + ald_uart_interrupt_config(hperh, ALD_UART_IT_TBC, ENABLE); + } + + return ALD_OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_end_send_by_it(ald_uart_handle_t *hperh) +{ + uint32_t cnt = 0xFFFFFF; + + ald_uart_interrupt_config(hperh, ALD_UART_IT_TBC, DISABLE); + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + while ((hperh->perh->STAT & ALD_UART_STATUS_TSBUSY) && (cnt--)); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TBC); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_recv_by_it(ald_uart_handle_t *hperh) +{ + if ((hperh->state & ALD_UART_STATE_RX_MASK) == 0x0) + return ALD_BUSY; + + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + + if (hperh->rx_count >= hperh->rx_size) + { + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, DISABLE); + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return ALD_OK; +} +/** + * @} + */ +/** @defgroup UART_Public_Functions UART Public Functions + * @{ + */ +/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * + * @verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the UARTx + and configure UARTx param. + (+) For the UARTx only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity + (++) Hardware flow control + (+) For RS485 mode, user also need configure some parameters by + ald_uart_rs485_config(): + (++) Enable/disable normal point mode + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare + + @endverbatim + * @{ + */ + +/** + * @brief Reset UART peripheral + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified uart module. + * @retval None + */ +void ald_uart_reset(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCON, 0x0); + WRITE_REG(hperh->perh->MCON, 0x0); + WRITE_REG(hperh->perh->RS485, 0x0); + WRITE_REG(hperh->perh->SCARD, 0x0); + WRITE_REG(hperh->perh->LIN, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->state = ALD_UART_STATE_RESET; + + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the UARTx according to the specified + * parameters in the uart_handle_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void ald_uart_init(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + ald_uart_reset(hperh); + + MODIFY_REG(hperh->perh->LCON, UART_LCON_DLS_MSK, hperh->init.word_length << UART_LCON_DLS_POSS); + MODIFY_REG(hperh->perh->LCON, UART_LCON_STOP_MSK, hperh->init.stop_bits << UART_LCON_STOP_POS); + + if ((hperh->init.parity) != ALD_UART_PARITY_NONE) + { + SET_BIT(hperh->perh->LCON, UART_LCON_PE_MSK); + + if ((hperh->init.parity) == ALD_UART_PARITY_ODD) + CLEAR_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + + if ((hperh->init.parity) == ALD_UART_PARITY_EVEN) + SET_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + } + + MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS); + hperh->perh->BRR = (ald_cmu_get_pclk_clock() + (hperh->init.baud >> 1)) / hperh->init.baud; + + if (hperh->init.mode == ALD_UART_MODE_LIN) + SET_BIT(hperh->perh->LIN, UART_LIN_LINEN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_IrDA) + SET_BIT(hperh->perh->MCON, UART_MCON_IREN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_RS485) + SET_BIT(hperh->perh->RS485, UART_RS485_AADEN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCON, UART_MCON_HDEN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_SCARD) + SET_BIT(hperh->perh->SCARD, UART_SCARD_SCEN_MSK); + else + ; /* do nothing */ + + SET_BIT(hperh->perh->LCON, UART_LCON_RXEN_MSK); + SET_BIT(hperh->perh->LCON, UART_LCON_TXEN_MSK); + + hperh->state = ALD_UART_STATE_READY; + hperh->err_code = ALD_UART_ERROR_NONE; + return; +} + +/** + * @brief Configure the RS485 mode according to the specified + * parameters in the uart_rs485_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the RS485 parameters. + * @retval None + */ +void ald_uart_rs485_config(ald_uart_handle_t *hperh, ald_uart_rs485_config_t *config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); + + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADNEN_MSK, config->normal << UART_RS485_AADNEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADACEN_MSK, config->dir << UART_RS485_AADACEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADINV_MSK, config->invert << UART_RS485_AADINV_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_ADDR_MSK, config->addr << UART_RS485_ADDR_POSS); + + return; +} + +/** + * @brief Configure the smart card mode according to the specified + * parameters in the uart_scard_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the scard parameters. + * @retval None + */ +void ald_uart_scard_config(ald_uart_handle_t *hperh, ald_uart_scard_config_t *config) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + assert_param(IS_UART_SCARD_CLK(config->clk_div)); + + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_BLEN_MSK, config->block_len << UART_SCARD_BLEN_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_GT_MSK, config->pt << UART_SCARD_GT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCCNT_MSK, config->retry << UART_SCARD_SCCNT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_PSC_MSK, config->clk_div << UART_SCARD_PSC_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCLKEN_MSK, config->clk_out << UART_SCARD_SCLKEN_POS); + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * @verbatim + ============================================================================== + # IO operation functions # + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the Status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the transmit or receive process. + The hperh->error_cbk() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) ald_uart_send() + (++) ald_uart_recv() + + (#) Non Blocking mode APIs with Interrupt are: + (++) ald_uart_send_by_it() + (++) ald_uart_recv_by_it() + (++) ald_uart_irq_handler() + + (#) Non Blocking mode functions with DMA are: + (++) ald_uart_send_by_dma() + (++) ald_uart_recv_by_dma() + (++) ald_uart_dma_pause() + (++) ald_uart_dma_resume() + (++) ald_uart_dma_stop() + + (#) A set of transfer complete callbacks are provided in non blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->error_cbk() + + @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_RX)) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = 0; + + while (size-- > 0) + { + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) { + __UNLOCK(hperh); + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TSBUSY, RESET, timeout) != ALD_OK) + { + __UNLOCK(hperh); + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t stat = 0; + uint32_t err = 0; + uint32_t tick = 0; + + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_TX)) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0) || (timeout == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = 0; + + err = (ALD_UART_STATUS_PERR | ALD_UART_STATUS_FERR | ALD_UART_STATUS_RFOERR); + + while (size-- > 0) + { + tick = ald_get_tick(); + + /* Waiting for flag */ + while (1) + { + stat = hperh->perh->STAT; + if (READ_BIT(stat, ALD_UART_STATUS_RFNEMPTY) != RESET) + break; + + if (((ald_get_tick()) - tick) > timeout) + { + __UNLOCK(hperh); + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + } + + if ((stat & err) == RESET) + { + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + else + { + /* Handle parity error */ + if ((READ_BIT(stat, ALD_UART_STATUS_PERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, ALD_UART_STATUS_FERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, ALD_UART_STATUS_RFOERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_ORE; + + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return ALD_ERROR; + } + } + + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_RX)) + return ALD_BUSY; + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = 0; + + while (size-- > 0) + { + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TSBUSY, RESET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + return ALD_OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_TX)) + return ALD_BUSY; + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = 0; + + while (size-- > 0) + { + if (uart_wait_flag(hperh, ALD_UART_STATUS_RFNEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + return ALD_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_RX)) + return ALD_BUSY; + + if ((buf == NULL ) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->ICR, UART_ICR_TFEMPTY_MSK); + ald_uart_interrupt_config(hperh, ALD_UART_IT_TFEMPTY, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_TX)) + return ALD_BUSY; + + if ((buf == NULL ) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->ICR, UART_ICR_RFNEMPTY_MSK); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an frame of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Max length of frame. + * @param t_out: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_frame_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_TX)) + return ALD_BUSY; + + if ((buf == NULL ) || (t_out == 0) || (t_out > 0xFFFFFF) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->ICR, UART_ICR_RFNEMPTY_MSK); + SET_BIT(hperh->perh->RTOR, UART_RTOR_RTOEN_MSK); + MODIFY_REG(hperh->perh->RTOR, UART_RTOR_RTO_MSK, t_out << UART_RTOR_RTO_POSS); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, ENABLE); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RXTO, ENABLE); + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as UART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_RX)) + return ALD_BUSY; + + if ((buf == NULL ) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + /* Set the dma parameters */ + hperh->hdmatx.cplt_tc_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXBUF; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_UART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == ALD_UART_MODE_RS485) + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + + if (hperh->perh == CUART0) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_CUART0; + else if (hperh->perh == CUART1) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_CUART1; + else if (hperh->perh == CUART2) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_CUART2; + else if (hperh->perh == EUART0) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_EUART0; + else if (hperh->perh == EUART1) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_EUART1; + else + ; /* do nothing */ + + ald_dma_config_basic(&hperh->hdmatx); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TBC); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as UART receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_TX)) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = ALD_UART_ERROR_NONE; + SET_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + /* Set the dma parameters */ + hperh->hdmarx.cplt_tc_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXBUF; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_UART_RNR; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == ALD_UART_MODE_RS485) + hperh->hdmarx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + + if (hperh->perh == CUART0) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_CUART0; + else if (hperh->perh == CUART1) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_CUART1; + else if (hperh->perh == CUART2) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_CUART2; + else if (hperh->perh == EUART0) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_EUART0; + else if (hperh->perh == EUART1) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_EUART1; + else + ; + + __UNLOCK(hperh); + ald_dma_config_basic(&hperh->hdmarx); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, ENABLE); + + return ALD_OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_pause(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, DISABLE); + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_resume(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, ENABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, ENABLE); + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_stop(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, DISABLE); + hperh->state = ALD_UART_STATE_READY; + return ALD_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler(ald_uart_handle_t *hperh) +{ + uint32_t stat = 0; + + assert_param(IS_UART_ALL(hperh->perh)); + + stat = hperh->perh->STAT; + + /* Handle parity error */ + if (((READ_BIT(stat, ALD_UART_STATUS_PERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == ALD_UART_STATE_RX_MASK) + hperh->err_code |= ALD_UART_ERROR_PE; + + /* Handle frame error */ + if (((READ_BIT(stat, ALD_UART_STATUS_FERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == ALD_UART_STATE_RX_MASK) + hperh->err_code |= ALD_UART_ERROR_FE; + + /* Handle rx overflow error */ + if (((READ_BIT(stat, ALD_UART_STATUS_RFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == ALD_UART_STATE_RX_MASK) + hperh->err_code |= ALD_UART_ERROR_ORE; + + /* Handle tx overflow error */ + if (((READ_BIT(stat, ALD_UART_STATUS_TFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == ALD_UART_STATE_TX_MASK) + hperh->err_code |= ALD_UART_ERROR_ORE; + + /* Receive */ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_RFNEMPTY)) != RESET) + { + __uart_recv_by_it(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_RFNEMPTY); + } + + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_TFEMPTY)) != RESET) + { + __uart_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TFEMPTY); + } + + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_TBC)) != RESET) + { + __uart_end_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TBC); + } + + /* Receive frame timeout*/ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_RXTO)) != RESET) + { + ald_uart_clear_flag_status(hperh, ALD_UART_IF_RXTO); + + ald_uart_interrupt_config(hperh, ALD_UART_IT_RXTO, DISABLE); + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + /* Handle error state */ + if (hperh->err_code != ALD_UART_ERROR_NONE) + { + hperh->state = ALD_UART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } +} + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler_fast(ald_uart_handle_t *hperh) +{ + volatile uint32_t tmp = hperh->perh->IFM; + + /* Transmit */ + if (tmp & 0x10000) + { + hperh->perh->ICR = 0x10000; + hperh->perh->TXBUF = *hperh->tx_buf++; + ++hperh->tx_count; + + if (hperh->tx_count >= hperh->tx_size) + { + hperh->perh->IDR = 0x10000; + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + } + /* End Transmit */ + if (tmp & 0x4000) + { + hperh->perh->ICR = 0x4000; + hperh->perh->IDR = 0x4000; + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + + /* Receive*/ + if (tmp & 0x400) + { + hperh->perh->ICR = 0x400; + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + ++hperh->rx_count; + + if (hperh->rx_count >= hperh->rx_size) + { + hperh->perh->IDR = 0x400; + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + } + /* Receive frame */ + if (tmp & 0x10) + { + hperh->perh->ICR = 0x10; + hperh->perh->IDR = 0x10; + CLEAR_BIT(hperh->state, ALD_UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. + (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) ald_uart_get_it_status() API can get the status of interrupt source. + (+) ald_uart_get_status() API can get the status of UART_SR register. + (+) ald_uart_get_flag_status() API can get the status of UART flag. + (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) ald_uart_clear_flag_status() API can clear UART flag. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/disable the specified UART interrupts. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref uart_it_t. + * @param state: New state of the specified UART interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_interrupt_config(ald_uart_handle_t *hperh, ald_uart_it_t it, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Configure UART DMA request. + * @param hperh: Pointer to a uart_handle_t structure. + * @param req: The type of DMA request. + * @param state: New state of the specified DMA request. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_dma_req_config(ald_uart_handle_t *hperh, ald_uart_dma_req_t req, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (req == ALD_UART_DMA_REQ_TX) + { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + } + else + { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + } + + return; +} + +/** + * @brief Enable/Disable break signal detect interrup. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: The new status. + * @retval None + */ +void uart_lin_break_detect_irq(ald_uart_handle_t *hperh, type_func_t status) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + + if (status == ENABLE) + SET_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + else + CLEAR_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + + return; +} + +/** + * @brief request to send a frame of break. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_lin_send_break(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + + SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK); + hperh->perh->TXBUF = 0x55; + + return; +} + +/** + * @brief Configure the length of break frame to be detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param len: Length of break frame. + * @arg LIN_BREAK_LEN_10B + * @arg LIN_BREAK_LEN_11B + * @retval None + */ +void ald_uart_lin_detect_break_len_config(ald_uart_handle_t *hperh, ald_uart_lin_break_len_t len) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); + + MODIFY_REG(hperh->perh->LIN, UART_LIN_LINBDL_MSK, len << UART_LIN_LINBDL_POS); + + return; +} + +/** + * @brief Configure the mode of auto-baud-rate detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param mode: The mode of auto-baud-rate detect. + * @arg UART_ABRMOD_1_TO_0 + * @arg UART_ABRMOD_1 + * @arg UART_ABRMOD_0_TO_1 + * @retval None + */ +void ald_uart_auto_baud_config(ald_uart_handle_t *hperh, ald_uart_auto_baud_mode_t mode) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + + MODIFY_REG(hperh->perh->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS); + + return; +} + +/** + * @brief Send address in RS485 mode. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param addr: the address of RS485 device. + * @param timeout: Timeout duration + * @retval The ALD status. + */ +ald_status_t ald_uart_rs485_send_addr(ald_uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != ALD_UART_STATE_READY) && (hperh->state != ALD_UART_STATE_BUSY_RX)) + return ALD_BUSY; + + SET_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + WRITE_REG(hperh->perh->TXBUF, (addr | 0x100)); + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + CLEAR_BIT(hperh->state, ALD_UART_STATE_TX_MASK); + + return ALD_OK; +} + +/** + * @brief Get the status of UART interrupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt source. + * This parameter can be one of the @ref uart_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_uart_get_it_status(ald_uart_handle_t *hperh, ald_uart_it_t it) +{ + it_status_t status = RESET; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of UART_SR register. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: Specifies the UART status type. + * This parameter can be one of the @ref uart_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_status(ald_uart_handle_t *hperh, ald_uart_status_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_mask_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval None + */ +void ald_uart_clear_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval ALD state + */ +ald_uart_state_t ald_uart_get_state(ald_uart_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the UART error code + * @param hperh: Pointer to a uart_handle_t structure. + * @retval UART Error Code + */ +uint32_t ald_uart_get_error(ald_uart_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_usb.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_usb.c new file mode 100644 index 0000000000..d536ca64c4 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_usb.c @@ -0,0 +1,1665 @@ +/** + ********************************************************************************* + * + * @file ald_usb.c + * @brief USB module driver. + * + * @version V1.0 + * @date 25 Feb 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Feb 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" +#include "usb_lowlayer_api.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup USB USB + * @brief USB module driver + * @{ + */ +#ifdef ALD_USB +/** + * @defgroup USB_Public_Functions USB Public Function + * @{ + */ +/** @defgroup USB_Public_Functions_Group1 Base functions + * @brief Base functions + * @{ + */ + +/** + * @brief Gets the number of current frame. + * @retval Number of the frame. + */ +uint32_t ald_usb_frame_number_get(void) +{ + uint8_t framel = (uint8_t)USB->FRAME1; + uint8_t frameh = (uint8_t)USB->FRAME2; + return ((uint32_t)(framel & 0xFF) + ((uint32_t)(frameh & 0xFF) << 8)); +} + +/** + * @brief Request the session. + * @param start: true/false. + * @retval None + */ +void ald_usb_otg_session_request(bool start) +{ + if (start) + USB->DEVCON |= (uint8_t)ALD_USB_DEVCON_SESSION; + else + USB->DEVCON &= (uint8_t)(~(ALD_USB_DEVCON_SESSION)); + + return; +} + +/** + * @brief Gets the mode. + * @retval Mode + */ +uint32_t ald_usb_mode_get(void) +{ + return (USB->DEVCON & ((uint8_t)(ALD_USB_DEVCON_HOST | ALD_USB_DEVCON_SESSION))); +} + +/** + * @brief Start host require. + * @retval Mode + */ +uint32_t ald_usb_mode_host_req(void) +{ + USB->DEVCON |= (uint8_t)ALD_USB_DEVCON_HOSTREQ; + return 0; +} + +/** + * @brief Clear host require. + * @retval Mode + */ +uint32_t ald_usb_mode_host_req_clear(void) +{ + USB->DEVCON &= (uint8_t)(~ALD_USB_DEVCON_HOSTREQ); + return 0; +} + +/** + * @brief Enable/Disable the high mode. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_high_speed_enable(bool enable) +{ + assert_param(enable == DISABLE); + + return; +} + +/** + * @brief Gets the speed of the device. + * @retval Type of the speed. + */ +uint32_t ald_usb_device_speed_get(void) +{ + return ALD_USB_FULL_SPEED; +} + +/** + * @brief Gets the number of the endpoint. + * @retval Number of the endpoint. + */ +uint32_t ald_usb_num_ep_get( void) +{ + return ALD_NUM_USB_EP; +} + +/** + * @brief Reset USB Control. + * @retval None + */ +void ald_usb_control_reset(void) +{ + //ALD_RCU_USB_RESET_ENABLE(); + + return; +} + +/** + * @brief Output USB clock, not support. + * @retval None + */ +void ald_usb_clock_output(void) +{ + return; +} + +/** + * @brief Starts eye diagram for high-speed host, not support. + * @param buf: Buffer for eye diagram. + * @param len: Length of the buffer. + * @retval Status, 0 means success, other values means failure. + */ +int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len) +{ + return 0; +} + +/** + * @brief Pull up or pull down USB dp line. + * @param pupd: USB_DPDM_FLOATING/USB_DPDM_PUSH_UP/USB_DPDM_PUSH_DOWN. + * @retval None + */ +void ald_usb_dppud_set(ald_dpdm_push_t pupd) +{ + USB->DPDMCON &= (uint8_t)(~USB_DPDMCON_DPPUD_MSK); + USB->DPDMCON |= (uint8_t)(pupd << USB_DPDMCON_DPPUD_POSS); + return; +} + +/** + * @brief Pull up or pull down USB dm line. + * @param pupd: USB_DPDM_FLOATING/USB_DPDM_PUSH_UP/USB_DPDM_PUSH_DOWN. + * @retval None + */ +void ald_usb_dmpud_set(ald_dpdm_push_t pupd) +{ + USB->DPDMCON &= (uint8_t)(~USB_DPDMCON_DMPUD_MSK); + USB->DPDMCON |= (uint8_t)(pupd << USB_DPDMCON_DMPUD_POSS); + return; +} + +/** + * @brief Switch usb mode by software. + * @param host: 0, indicates that software force to host + host: 1, indicates that software force to device. + * @retval None + */ +void ald_usb_swcid_host(uint8_t host) +{ + if (host) + USB->SWCID |= (uint8_t)(USB_SWCID_HOST_MSK); + else + USB->SWCID &= (uint8_t)(~USB_SWCID_HOST_MSK); + return; +} + +/** + * @brief Switch the control method of CID. + * @param cid: 0, indicates that use the hardware control + cid: 1, indicates that use the software control. + * @retval None + */ +void ald_usb_swcid_cidctrl(uint8_t cid) +{ + if (cid) + USB->SWCID |= (uint8_t)(ALD_USB_SWCID_CIDCTRL); + else + USB->SWCID &= (uint8_t)(~ALD_USB_SWCID_CIDCTRL); + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group2 Device functions + * @brief Device functions + * @{ + */ + +/** + * @brief Gets the address. + * @retval Address. + */ +uint8_t ald_usb_dev_get_addr(void) +{ + return (USB->FADDR); +} + +/** + * @brief Sets the address. + * @param addr: The address which will be set. + * @retval None + */ +void ald_usb_dev_set_addr(uint8_t addr) +{ + USB->FADDR = addr; + return; +} + +/** + * @brief Enable connection. + * @retval None + */ +void ald_usb_dev_connect(void) +{ + USB->DPDMCON |= (uint8_t)(ALD_USB_DPDMCON_PHYPWREN); + return; +} + +/** + * @brief Disable connection. + * @retval None + */ +void ald_usb_dev_disconnect(void) +{ + USB->DPDMCON &= (uint8_t)(~(ALD_USB_DPDMCON_PHYPWREN)); + return; +} + +/** + * @brief Enable the devices suspend. + * @retval None + */ +void ald_usb_dev_suspend_enable(void) +{ + USB->POWER |= (uint8_t)USB_POWER_SUSPENDEN_MSK; + return; +} + +/** + * @brief Configure the endpoint in device mode. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags) +{ + uint32_t tmp = 0U; + + USB->INDEX = (uint8_t)ep_idx; + + if (flags & ALD_USB_EP_DEV_IN) { + USB->TXMAXP = (uint8_t)(p_max); + if (flags & ALD_USB_EP_AUTO_SET) + tmp |= USB_TXCSRH_AUTOSET_MSK; + if ((flags & ALD_USB_EP_MODE_MASK) == ALD_USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH_ISO_MSK; + + USB->CSR0H_TXCSRH |= (uint8_t)tmp; + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_CLRDT_MSK; + } + else { + USB->RXMAXP = (uint8_t)(p_max); + if (flags & ALD_USB_EP_AUTO_CLEAR) + tmp |= USB_RXCSRH_AUTOCLR_MSK; + if ((flags & ALD_USB_EP_MODE_MASK) == ALD_USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH_ISO_MSK; + + USB->RXCSRH |= (uint8_t)tmp; + USB->RXCSRL |= (uint8_t)USB_RXCSRL_CLRDT_MSK; + } + + return; +} + +/** + * @brief Gets the parameters of the endpoint. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags) +{ + uint32_t tmp; + + USB->INDEX = (uint8_t)ep_idx; + + if (*flags & ALD_USB_EP_DEV_IN) { + *flags = ALD_USB_EP_DEV_IN; + *p_max = (uint32_t)USB->TXMAXP; + tmp = (uint32_t)USB->CSR0H_TXCSRH; + if (tmp & USB_TXCSRH_AUTOSET_MSK) + *flags |= ALD_USB_EP_AUTO_SET; + if (tmp & USB_TXCSRH_ISO_MSK) + *flags |= ALD_USB_EP_MODE_ISOC; + else + *flags |= ALD_USB_EP_MODE_BULK; + } + else { + *flags = ALD_USB_EP_DEV_OUT; + *p_max = (uint32_t)USB->RXMAXP; + tmp = (uint32_t)USB->RXCSRH; + + if (tmp & USB_RXCSRH_AUTOCLR_MSK) + *flags |= ALD_USB_EP_AUTO_CLEAR; + if (tmp & USB_RXCSRH_ISO_MSK) + *flags |= ALD_USB_EP_MODE_ISOC; + else + *flags |= ALD_USB_EP_MODE_BULK; + } + return; +} +extern void printf_e(const char *fmt, ...); +/** + * @brief Acknowledge the data from host. + * @param ep_idx: Index of the endpoint + * @param last: true/false + * @retval None + */ +void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)(USB_CSR0L_RXRDYC_MSK | (last ? USB_CSR0L_DATAEND_MSK : 0)); + else + USB->RXCSRL &= (uint8_t)(~USB_RXCSRL_RXRDY_MSK); + + return; +} + +/** + * @brief Stall the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)(USB_CSR0L_RXRDYC_MSK | USB_CSR0L_STALL_MSK); + else if (flags == ALD_USB_EP_DEV_IN) + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_STALL_MSK; + else + USB->RXCSRL |= (uint8_t)USB_RXCSRL_STALL_MSK; + + return; +} + +/** + * @brief Cancel the stall status. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_STALLED_MSK); + else if (flags == ALD_USB_EP_DEV_IN){ + USB->CSR0L_TXCSRL &= (uint8_t)(~(USB_TXCSRL_STALL_MSK | USB_TXCSRL_STALLED_MSK)); + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_CLRDT_MSK; + } + else{ + USB->RXCSRL &= (uint8_t)(~(USB_RXCSRL_STALL_MSK | USB_RXCSRL_STALLED_MSK)); + USB->RXCSRL |= (uint8_t)USB_RXCSRL_CLRDT_MSK; + } + + return; +} + +/** + * @brief Clear the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if (flags & ALD_USB_DEV_EP0_OUT_PKTRDY) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_RXRDYC_MSK; + if (flags & ALD_USB_DEV_EP0_SETUP_END) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_SETENDC_MSK; + if (flags & ALD_USB_DEV_EP0_SENT_STALL) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_STALLED_MSK); + } + else { + USB->CSR0L_TXCSRL &= (uint8_t)(~(flags & (ALD_USB_DEV_TX_SENT_STALL | ALD_USB_DEV_TX_UNDERRUN))); + USB->RXCSRL &= (uint8_t)(~((flags & (ALD_USB_DEV_RX_SENT_STALL | ALD_USB_DEV_RX_DATA_ERROR + | ALD_USB_DEV_RX_OVERRUN)) >> ALD_USB_RX_EPSTATUS_SHIFT)); + } + + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group3 Host functions + * @brief Host functions + * @{ + */ +/** + * @brief Gets the device's address. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + return (USB->FADDR); +} + +/** + * @brief Sets the device's address. + * @param ep_idx: Index of the endpoint. + * @param addr: The device's address. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + USB->FADDR = (uint8_t)addr; + + return; +} + +/** + * @brief Configure the endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param p_max: Size of the maximum package. + * @param nak_val: Value of the nack. + * @param t_ep: Target endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags) +{ + uint32_t tmp = 0U; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)nak_val; + + if (flags & ALD_USB_EP_SPEED_HIGH) + ; + else if (flags & ALD_USB_EP_SPEED_FULL) + ; + else + ; + } + else { + tmp = t_ep; + + if (flags & ALD_USB_EP_SPEED_HIGH) + ; + else if (flags & ALD_USB_EP_SPEED_FULL) + ; + else + ; + + switch (flags & ALD_USB_EP_MODE_MASK) { + case ALD_USB_EP_MODE_BULK: + tmp |= ALD_USB_TXTYPE1_PROTO_BULK; + break; + + case ALD_USB_EP_MODE_ISOC: + tmp |= ALD_USB_TXTYPE1_PROTO_ISOC; + break; + + case ALD_USB_EP_MODE_INT: + tmp |= ALD_USB_TXTYPE1_PROTO_INT; + break; + + case ALD_USB_EP_MODE_CTRL: + tmp |= ALD_USB_TXTYPE1_PROTO_CTRL; + break; + } + + if (flags & ALD_USB_EP_HOST_OUT) { + USB->TXTYPE = (uint8_t)tmp; + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)nak_val; + USB->TXMAXP = (uint8_t)p_max; + + tmp = 0; + if (flags & ALD_USB_EP_AUTO_SET) + tmp = (uint8_t)ALD_USB_TXCSRH_AUTOSET; + USB->CSR0H_TXCSRH |= (uint8_t)tmp; + } + else { + USB->RXTYPE = (uint8_t)tmp; + USB->RXINTERVAL = (uint8_t)nak_val; + USB->RXMAXP = (uint8_t)p_max; + + tmp = 0; + if (flags & ALD_USB_EP_AUTO_CLEAR) + tmp |= (uint8_t)USB_RXCSRH_AUTOCLR_MSK; + if (flags & ALD_USB_EP_AUTO_REQUEST) + tmp |= (uint8_t)USB_RXCSRH_AUTOREQ_MSK; + + USB->RXCSRH |= (uint8_t)tmp; + } + } + + return; +} + +/** + * @brief Acknowledge the data in host mode. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_ep_data_ack(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~(USB_CSR0L_RXRDY_MSK)); + else + USB->RXCSRL &= (uint8_t)(~(USB_RXCSRL_RXRDY_MSK)); + + return; +} + +/** + * @brief Toggle the data in host mode. + * The function is used to force the state of the data toggle in host mode. + * If the value passed in the bDataToggle parameter is false, then the data + * toggle is set to the DATA0 state, and if it is true it is set to the DATA1 + * state. + * @param ep_idx: Index of the endpoint. + * @param toggle: true/false. + * @param flags: can be USB_EP_HOST_IN or USB_EP_HOST_OUT. + * @retval None + */ +void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags) +{ + /* not supported by es32f0271. */ + return; +} + +/** + * @brief Clear the status of endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + USB->CSR0L_TXCSRL &= (uint8_t)(~flags & 0xFF); + } + else { + USB->CSR0L_TXCSRL &= (uint8_t)(~flags & 0xFF); + USB->RXCSRL &= (uint8_t)(~(flags >> 16) & 0xFF); + } + + return; +} + +/** + * @brief Gets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags) +{ + /* not supported by es32f0271. */ + return 0; +} + +/** + * @brief Sets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param addr: HUB's address which will be set. + * @param flags: Flags. + * @retval Address + */ +void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + /* not supported by es32f0271. */ + return; +} + +/** + * @brief Disable power. + * @retval None + */ +void ald_usb_host_pwr_disable(void) +{ + USB->DPDMCON &= (uint8_t)(~(ALD_USB_DPDMCON_PHYPWREN)); + return; +} + +/** + * @brief Enable power. + * @retval None + */ +void ald_usb_host_pwr_enable(void) +{ + USB->DPDMCON |= (uint8_t)(ALD_USB_DPDMCON_PHYPWREN); + return; +} + +/** + * @brief Configure power in host mode. + * @param flags: Flags + * @retval None + */ +void ald_usb_host_pwr_config(uint32_t flags) +{ + return; +} + +/** + * @brief Disable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_disable(void) +{ + return; +} + +/** + * @brief Enable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_enable(void) +{ + return; +} + +/** + * @brief Request data IN(from device to host) + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_REQPKT_MSK; + else + USB->RXCSRL |= (uint8_t)USB_RXCSRL_REQPKT_MSK; + + return; +} + +/** + * @brief Clear the status of request IN. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in_clear(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_REQPKT_MSK); + else + USB->RXCSRL &= (uint8_t)(~USB_RXCSRL_REQPKT_MSK); + + return; +} + +/** + * @brief Set the request for a status IN transaction. + * @retval None + */ +void ald_usb_host_request_status(void) +{ + USB->CSR0L_TXCSRL |= (uint8_t)(ALD_USB_CSR0L_REQPKT | ALD_USB_CSR0L_STATUSPKT); + + return; +} + +/** + * @brief Reset the USB's bus. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_reset(bool start) +{ + if (start) + USB->POWER |= ALD_USB_POWER_RESET; + else + USB->POWER &= ~(ALD_USB_POWER_RESET); + + return; +} + +/** + * @brief Resume the devices. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_resume(bool start) +{ + if (start) + USB->POWER |= (uint8_t)USB_POWER_RESUME_MSK; + else + USB->POWER &= (uint8_t)(~(ALD_USB_POWER_RESUME)); + + return; +} + +/** + * @brief Suspend the devices. + * @retval None + */ +void ald_usb_host_suspend(void) +{ + USB->POWER |= (uint8_t)USB_POWER_SUSPEND_MSK; + return; +} + +/** + * @brief Gets the device's speed. + * @retval Type of the speed. + */ +uint32_t ald_usb_host_speed_get(void) +{ + if (USB->DEVCON & ALD_USB_DEVCON_FSDEV) + return ALD_USB_FULL_SPEED; + + if (USB->DEVCON & ALD_USB_DEVCON_LSDEV) + return ALD_USB_LOW_SPEED; + + return ALD_USB_UNDEF_SPEED; +} + +/** + * @brief Sets the endpoint speed. + * @param ep_idx: Index of the endpoint. + * @param flags: Type of the speed. + * @retval None + */ +void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags) +{ + /* not support in F0271 */ + return; +} + +/** + * @brief Ping the endpoint. + * @param ep_idx: Index of the endpoint. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable) +{ + /* not support in F0271 */ + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group4 Endpoint functions + * @brief Endpoint functions + * @{ + */ +/** + * @brief Gets the size of the available data. + * @param ep_idx: Index of the endpoint + * @retval Size in bytes. + */ +uint32_t ald_usb_ep_data_avail(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if ((USB->CSR0L_TXCSRL & ALD_USB_CSR0L_RXRDY) == 0){ + return 0; + } + + return USB->COUNT0_RX1; + } + else { + if ((USB->RXCSRL & ALD_USB_CSR0L_RXRDY) == 0) + { + return 0; + } + + return (USB->COUNT0_RX1 + (((uint32_t)USB->RXCOUNT2) << 8)); + } +} + +/** + * @brief Gets the data from FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the buffer. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size) +{ + uint32_t i, rx_fifo_addr; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if ((USB->CSR0L_TXCSRL & ALD_USB_CSR0L_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB->COUNT0_RX1; + } + else { + if ((USB->RXCSRL & ALD_USB_CSR0L_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB->COUNT0_RX1 + (((uint32_t)USB->RXCOUNT2) << 8); + } + + i = (i < *size) ? i : *size; + *size = i; + + rx_fifo_addr = (uint32_t)(&USB->EP0FIFO) + 4 * ep_idx; + + for (; i > 0; i--) + *data++ = *(volatile uint8_t *)(rx_fifo_addr); + + return 0; +} + +/** + * @brief Puts data to the FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the data. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size) +{ + uint32_t tx_fifo_addr; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return -1; + } + else { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return -1; + } + + tx_fifo_addr = (uint32_t)(&USB->EP0FIFO) + 4 * ep_idx; + + for (; size > 0; size--) + *(volatile uint8_t *)tx_fifo_addr = *data++; + + return 0; +} + +/** + * @brief Send data. + * @param ep_idx: Index of the endpoint + * @param tx_type: Type. + * @retval Status. + */ +int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type) +{ + uint32_t tmp; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return -1; + + tmp = tx_type & 0xFF; + } + else { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return -1; + + tmp = (tx_type >> 8) & 0xff; + } + + USB->CSR0L_TXCSRL = tmp; + + return 0; +} + +/** + * @brief Clear the status of the toggle. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_CLRDT; + else + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_CLRDT; + + return; +} + +/** + * @brief Sets the size of request data IN + * @param ep_idx: Index of the endpoint + * @param count: Size of request data IN. + * @retval None + */ +void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count) +{ + /* not support in f0271 */ + return; +} + +/** + * @brief Gets the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @retval Status. + */ +uint32_t ald_usb_ep_status(uint32_t ep_idx) +{ + uint32_t status; + + USB->INDEX = (uint8_t)ep_idx; + + status = (ep_idx == ALD_USB_EP_0) ? (USB->CSR0L_TXCSRL): (USB->CSR0L_TXCSRL | (USB->RXCSRL << 16)); + + return status; +} + +/** + * @brief Configure the endpoint in DMA mode. + * @param ep_idx: Index of the endpoint + * @param flag: Flags. + * @param en: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en) +{ + /* Not supported in F0271 */ + + return; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group5 FIFO functions + * @brief FIFO functions + * @{ + */ +/** + * @brief Gets the address of the FIFO. + * @param ep_idx: Index of the endpoint + * @retval Address + */ +uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx) +{ + /* Not supported in F0271 */ + + return 0; +} + +/** + * @brief Gets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + *addr = ((uint32_t)USB->TXFIFO1 | ((uint32_t)USB->TXFIFO2 & 0x03)) << 3; + *size = ((USB->TXFIFO2 & ALD_USB_TXFIFO2_DPB) == 0x00) ? (USB->TXFIFO2 & ALD_USB_TXFIFO2_MAXPKTSIZE_1024) : (2 * (USB->TXFIFO2 & ALD_USB_TXFIFO2_MAXPKTSIZE_1024)); + } + else { + *addr = ((uint32_t)USB->RXFIFO1 | ((uint32_t)USB->RXFIFO2 & 0x03)) << 3; + *size = ((USB->RXFIFO2 & ALD_USB_RXFIFO2_DPB) == 0x00) ? (USB->RXFIFO2 & ALD_USB_RXFIFO2_MAXPKTSIZE_1024) : (2 * (USB->RXFIFO2 & ALD_USB_RXFIFO2_MAXPKTSIZE_1024)); + } + + return; +} + +/** + * @brief Sets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO, valid parameter has defined in usb_lowlayer_api.h. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + USB->TXFIFO1 = (uint8_t)((addr >> 3) & 0xFF); + USB->TXFIFO2 |= (uint8_t)(((addr >> 3) >> 8) & 0x0F); + + USB->TXFIFO2 |= (uint8_t)(size << USB_TXFIFO2_MAXPKTSIZE_POSS); + + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_FLUSH; + } + else { + USB->RXFIFO1 = (uint8_t)((addr >> 3) & 0xFF); + USB->RXFIFO2 |= (uint8_t)(((addr >> 3) >> 8) & 0x0F); + + USB->RXFIFO2 |= (uint8_t)(size << USB_RXFIFO2_MAXPKTSIZE_POSS); + + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_FLUSH; + } + + return; +} + +/** + * @brief Flush the FIFO + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if ((USB->CSR0L_TXCSRL & (ALD_USB_CSR0L_RXRDY | ALD_USB_CSR0L_TXRDY)) != 0) + USB->CSR0H_TXCSRH |= ALD_USB_CSR0H_FLUSH; + } + else { + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + USB->CSR0L_TXCSRL |= ALD_USB_TXCSRL_FLUSH; + } + else { + if (USB->RXCSRL & ALD_USB_RXCSRL_RXRDY) + USB->RXCSRL |= ALD_USB_RXCSRL_FLUSH; + } + } + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group6 Interrupt functions + * @brief Interrupt functions + * @{ + */ +/** + * @brief Disable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable(uint32_t flags) +{ + if (flags & ALD_USB_IDR_STATUS) + USB->IDR |= (uint8_t)(flags & ALD_USB_IDR_STATUS); + + return; +} + +/** + * @brief Enable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable(uint32_t flags) +{ + if (flags & ALD_USB_IER_STATUS) + USB->IER |= (uint8_t)(flags & ALD_USB_IER_STATUS); + + return; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_get(void) +{ + uint32_t Status; + + Status = USB->IFM & 0x7F; + USB->ICR |= Status; + + return Status; +} + +/** + * @brief Disable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable_ep(uint32_t flags) +{ + USB->TXIDR |= (uint8_t)(flags & (ALD_USB_INTEP_HOST_OUT | ALD_USB_INTEP_DEV_IN | ALD_USB_INTEP_0)); + USB->RXIDR |= (uint8_t)((flags & (ALD_USB_INTEP_HOST_IN | ALD_USB_INTEP_DEV_OUT)) >> ALD_USB_INTEP_RX_SHIFT); + return; +} + +/** + * @brief Enable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable_ep(uint32_t flags) +{ + USB->TXIER |= (uint8_t)(flags & (ALD_USB_INTEP_HOST_OUT | ALD_USB_INTEP_DEV_IN | ALD_USB_INTEP_0)); + USB->RXIER |= (uint8_t)((flags & (ALD_USB_INTEP_HOST_IN | ALD_USB_INTEP_DEV_OUT)) >> ALD_USB_INTEP_RX_SHIFT); + return; +} + +/** + * @brief Gets the ststus of the endpoint interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_ep_get(void) +{ + uint32_t status; + + status = USB->TXIFM; + status |= (USB->RXIFM << ALD_USB_INTEP_RX_SHIFT); + + USB->TXICR |= (uint8_t)(status & 0xFF); + USB->RXICR |= (uint8_t)((status >> ALD_USB_INTEP_RX_SHIFT) & 0xFF); + + return status; +} + +/** + * @brief Register USB's interrupt. + * @retval None + */ +void ald_usb_int_register(void) +{ + //ald_mcu_irq_config(USB_IRQn, 2, ENABLE); + csi_vic_set_prio(USB_IRQn, 3); + csi_vic_enable_sirq(USB_IRQn); + return; +} + +/** + * @brief Unregister USB's interrupt. + * @retval None + */ +void ald_usb_int_unregister(void) +{ + //ald_mcu_irq_config(USB_IRQn, 2, DISABLE); + csi_vic_disable_sirq(USB_IRQn); + return; +} + +/** + * @brief Get USB's interrupt number. + * @retval None + */ +uint32_t ald_usb_int_num_get(void) +{ + return USB_IRQn; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group7 DMA functions + * @brief DMA functions + * @{ + */ +#if defined(__ALD_MDA_H__) +/** + * @brief Configure DMA's channel. + * @param ch: Channel. + * @param addr: Address. + * @param count: Size of the data to be moved. + * @param ctrl: Parameters of the DMA's controler + * @retval None + */ +void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl) +{ + return; +} + +/** + * @brief Start multiple receive. + * @param ep_idx: Index of the endpoint + * @retval None + */ +void ald_usb_dma_mult_recv_start(uint32_t ep_idx) +{ + return; +} + +/** + * @brief Start DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_start(uint8_t ch) +{ + return; +} + +/** + * @brief Stop DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_stop(uint8_t ch) +{ + return; +} + +/** + * @brief Gets flags of the interrupt. + * @retval Flags of the interrupt. + */ +uint32_t ald_usb_dma_get_interrupt_flag(void) +{ + return; +} + +/** + * @brief Gets the status of the error. + * @param ch: Channel. + * @retval Status. + */ +uint32_t ald_usb_dma_get_channel_error(uint8_t ch) +{ + return 0; +} + +/** + * @brief Clear the status of the error. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_clear_channel_error(uint8_t ch) +{ + return; +} + +#endif +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group8 LPM functions + * @brief LPM functions + * @{ + */ +/** + * @brief Gets status of remote wakeup. + * @retval Status. + */ +uint32_t ald_usb_lpm_remote_wake_is_enable(void) +{ + return 1; +} + +/** + * @brief Gets the link status + * @retval Status + */ +uint32_t ald_usb_lpm_link_status_get(void) +{ + return 0; +} + +/** + * @brief Gets the index of the endpoint. + * @retval Index of the endpoint. + */ +uint32_t ald_usb_lpm_ep_get(void) +{ + return 0; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_lpm_int_status_get(void) +{ + return 0; +} + +/** + * @brief Disable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_disable(uint32_t ints) +{ + return; +} + +/** + * @brief Enable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_enable(uint32_t ints) +{ + return; +} + +/** + * @brief Transmit a LPM transaction in host mode. + * @param addr: Address. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx) +{ + return; +} + +/** + * @brief Configure the LPM parameters in host mode. + * @param resume_time: Resume time. + * @param config: Parameters + * @retval None + */ +void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config) +{ + return; +} + +/** + * @brief Initiate a RESUME from the L1 state in host mode. + * @retval None + */ +void ald_usb_host_lpm_resume(void) +{ + return; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_remote_wake(void) +{ + return; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_config(uint32_t config) +{ + return; +} + +/** + * @brief Enable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_enable(void) +{ + return; +} + +/** + * @brief Disable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_disable(void) +{ + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group10 LPM functions + * @brief USB SWVBUS control + * @{ + */ +/** + * @brief Selet the control mode of VBUS. + * @param sigctl: 0, indicates that use the hardware control + * sigctl: 1, indicates that use the software control. + * @retval Status. + */ +void ald_usb_swvbus_sigctl_set(uint8_t sigctl) +{ + if (sigctl == 1) + { + USB->SWVBUS |= 0x01 << 0; + } + else + { + USB->SWVBUS &= ~(0x01 << 0); + } + return; +} + +/** + * @brief Selet the control mode of VBUS. + * @param None. + * @retval Status: 0, indicates that use the hardware control + * Status: 1, indicates that use the software control. + */ +uint8_t ald_usb_swvbus_sigctl_get(void) +{ + return (USB->SWVBUS & (0x01 << 0)); +} + +/** + * @brief Set session end threshold. + * @param thd: 0, indicates that lower than the session end threshold + * thd: 1, indicates that higher than the session end threshold. + * @retval Status. + */ +void ald_usb_swvbus_sesendth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 1; + } + else + { + USB->SWVBUS &= ~(0x01 << 1); + } + return; +} + +/** + * @brief Set session end threshold. + * @param None. + * @retval Status: 0, indicates that lower than the session end threshold + * Status: 1, indicates that higher than the session end threshold. + */ +uint8_t ald_usb_swvbus_sesendth_get(void) +{ + return (USB->SWVBUS & (0x01 << 1)); +} + +/** + * @brief Set session valid threshold. + * @param thd: 0, indicates that lower than the session valid threshold + thd: 1, indicates that higher than the session valid threshold. + * @retval Status. + */ +void ald_usb_swvbus_sesvalth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 2; + } + else + { + USB->SWVBUS &= ~(0x01 << 2); + } + return; +} + +/** + * @brief Set session valid threshold. + * @param None. + * @retval Status: 0, indicates that lower than the session valid threshold + Status: 1, indicates that higher than the session valid threshold. + */ +uint8_t ald_usb_swvbus_sesvalth_get(void) +{ + return (USB->SWVBUS & (0x01 << 2)); +} + +/** + * @brief Set VBUS valid threshold. + * @param thd: 0, indicates that lower than the vbus valid threshold + thd: 1, indicates that higher than the vbus valid threshold. + * @retval Status. + */ +void ald_usb_swvbus_valth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 3; + } + else + { + USB->SWVBUS &= ~(0x01 << 3); + } + return; +} + +/** + * @brief Set VBUS valid threshold. + * @param None. + * @retval Status: 0, indicates that lower than the vbus valid threshold + Status:thd: 1, indicates that higher than the vbus valid threshold. + */ +uint8_t ald_usb_swvbus_valth_get(void) +{ + return (USB->SWVBUS & (0x01 << 3)); +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group11 components initialization functions + * @brief USB components initialization + * @{ + */ +/** + * @brief Initialize usb host components. + * @retval None + */ +void ald_usb_host_components_init(void) +{ + WRITE_REG(SYSCFG->PROT, 0x55AA6996U); + RMU->AHB1RSTR |= 0x40; + RMU->AHB1RSTR &= 0xFFFFFFBF; + WRITE_REG(SYSCFG->PROT, 0x0); + + /* Config EP0 */ + ald_usb_host_ep_config(ALD_USB_EP_0, 64, 0, 0, (ALD_USB_EP_MODE_CTRL | ALD_USB_EP_SPEED_FULL | ALD_USB_EP_HOST_OUT)); + + /* Clear interrupts */ + + + /* Enable PHY power */ + ald_usb_host_pwr_enable(); + /* clear hnp session */ + ald_usb_otg_session_request(false); + + /* set vbus control mode and threshold value */ + ald_usb_swvbus_sigctl_set(1); + ald_usb_swvbus_sesendth_set(1); + ald_usb_swvbus_sesvalth_set(1); + ald_usb_swvbus_valth_set(1); + /* Pull down DP and DM */ + ald_usb_dppud_set(ALD_USB_DPDM_PUSH_DOWN); + ald_usb_dmpud_set(ALD_USB_DPDM_PUSH_DOWN); + /* software control CID */ + ald_usb_swcid_cidctrl(1); + /* force to host mode */ + ald_usb_swcid_host(0); + /* start host request */ + ald_usb_mode_host_req(); + /* Start hnp */ + ald_usb_otg_session_request(true); + + /* Clear interrupts */ + ald_usb_int_status_get(); + /* Init interrupts */ + ald_usb_int_enable(ALD_USB_INTCTRL_SESSION | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_CONNECT | ALD_USB_INTCTRL_SOF | + ALD_USB_INTCTRL_BABBLE | ALD_USB_INTCTRL_RESUME); + ald_usb_int_enable_ep(ALD_USB_INTEP_ALL); + ald_usb_int_register(); + + return; +} + +/** + * @brief Initialize usb device components. + * @retval None + */ +void ald_usb_device_components_init(void) +{ + ald_usb_otg_session_request(true); +#if (defined(ES32VF2264)) + ald_usb_dppud_set(ALD_USB_DPDM_FLOATING);/*测试板的USBDP(PA12)，上拉到3.3V。具体情况请参考ReadMe.txt*/ +#else + ald_usb_dppud_set(USB_DPDM_PUSH_UP); +#endif /* ES32VF2264 */ + /* software control CID */ + ald_usb_swcid_cidctrl(1); + /* force to dev mode */ + ald_usb_swcid_host(1); + ald_usb_dev_suspend_enable(); + + return; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_USB */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_utils.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_utils.c new file mode 100644 index 0000000000..dce542324c --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_utils.c @@ -0,0 +1,414 @@ +/** + ********************************************************************************* + * + * @file ald_utils.c + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 8 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 8 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include +#include "ald_conf.h" + +/** @defgroup EASTSOFT ES32VF2264 ALD + * @brief Shanghai Eastsoft Microelectronics E902 Chip Abstraction Layer Driver(ALD) + * @{ + */ + +/** @defgroup UTILS Utils + * @brief Utils module driver + * @{ + */ + +/** @defgroup ALD_Private_Constants Private Constants + * @brief ALD Private Constants + * @{ + */ + +/** + * @brief ALD version number + */ +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) +/** + * @} + */ + +/** @defgroup ALD_Private_Variables Private Variables + * @{ + */ +/** @brief lib_tick: Increase by one millisecond + */ +__IO uint32_t lib_tick; +uint32_t __systick_interval = ALD_SYSTICK_INTERVAL_1MS; +/** + * @} + */ + + +/** @defgroup ALD_Public_Functions Public Functions + * @{ + */ + +/** @defgroup ALD_Public_Functions_Group1 Initialization Function + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms. + (++) Time base configuration function (ald_tick_init()) is called automatically + at the beginning of the program after reset by ald_cmu_init() or at + any time when clock is configured. + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if ald_delay_ms() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. + (+) Configure the interval of Systick interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief This function Configures time base source, CLINT and DMA. + * @note This function is called at the beginning of program after reset and before + * the clock configuration. + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation, Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval None + */ +void ald_cmu_init(void) +{ + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); +#ifdef ALD_DMA + ald_cmu_perh_clock_config(ALD_CMU_PERH_DMA, ENABLE); + ald_dma_init(); +#endif + return; +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param prio: Tick interrupt priority. + * @retval None + */ +__weak void ald_tick_init(uint32_t prio) +{ + /* Configure the SysTick IRQ */ + csi_coret_config(ald_cmu_get_sys_clock() / ALD_SYSTICK_INTERVAL_1MS, CLINT_IRQn); + csi_vic_set_prio(CLINT_IRQn, prio); + csi_vic_enable_sirq(CLINT_IRQn); + + return; +} + +/** + * @brief Selects the interval of systick interrupt. + * @param value: The value of interval: + * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond + * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds + * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds + * @arg @ref SYSTICK_INTERVAL_1000MS 1 second + * @retval None + */ +void ald_systick_interval_select(ald_systick_interval_t value) +{ + assert_param(IS_SYSTICK_INTERVAL(value)); + + if (value == 0) + return; + + csi_coret_config(ald_cmu_get_sys_clock() / value, CLINT_IRQn); + __systick_interval = value; + + if (TICK_INT_PRIORITY != 15) + csi_vic_set_prio(CLINT_IRQn, TICK_INT_PRIORITY); + + return; +} +/** + * @} + */ + +/** @defgroup ALD_Public_Functions_Group2 Control functions + * @brief Control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the ALD version + (+) Waiting for flag + (+) Configure the interrupt + (+) Provide system tick value + (+) Initialize core timestamp + (+) Get core timestamp + (+) Get CPU ID + (+) Get UID + (+) Get CHIPID + + @endverbatim + * @{ + */ + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__weak void ald_systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function is called to increment a global variable "lib_tick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_inc_tick(void) +{ + ++lib_tick; + ald_systick_irq_cbk(); +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t ald_get_tick(void) +{ + return lib_tick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void ald_delay_1ms(__IO uint32_t delay) +{ + uint32_t tick, __delay; + + switch (__systick_interval) { + case ALD_SYSTICK_INTERVAL_1MS: + __delay = delay; + break; + + case ALD_SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; + + case ALD_SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; + + case ALD_SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; + + default: + __delay = delay; + break; + } + + tick = ald_get_tick(); + __delay = __delay == 0 ? 1 : __delay; + + while ((ald_get_tick() - tick) < __delay) + ; +} + +/** + * @brief This function provides accurate delay (in microseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in microseconds(us). + * @retval None + */ +__weak void ald_delay_1us(__IO uint32_t delay) +{ + uint32_t start, now, delta, us_tick; + start = CORET->MTIME; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; + do + { + now = CORET->MTIME; + delta = now - start; + } + while (delta < (us_tick * delay)); +} + +/** + * @brief This method returns the ALD revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t ald_get_ald_version(void) +{ + return __ALD_VERSION; +} + +/** + * @brief Configure the flash wait period. + * @param cycle: The period. + * @retval None + */ +void ald_flash_wait_config(uint8_t cycle) +{ + uint32_t tmp; + + tmp = MSC->MEMWAIT; + MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS); + MSC->MEMWAIT = tmp; + + return; +} + +/** + * @brief Waiting the specified bit in the register change to SET/RESET. + * @param reg: The register address. + * @param bit: The specified bit. + * @param status: The status for waiting. + * @param timeout: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + if (status == SET) { + while (!(IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + else { + while ((IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + + return ALD_OK; +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param prio: preempt priority(0-7). The larger the prio value, the higher the priority. + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) + { + csi_vic_set_prio(irq, prio); + csi_vic_enable_sirq(irq); + } + else + { + csi_vic_disable_sirq(irq); + } + + return; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_wdt.c b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_wdt.c new file mode 100644 index 0000000000..f5570b6e08 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/ald_wdt.c @@ -0,0 +1,228 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.c + * @brief WDT module driver. + * + * @version V1.0 + * @date 07 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ +#include "ald_wdt.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT module driver + * @{ + */ +/** @defgroup WWDT_Public_Functions WWDT Public Functions + * @brief Init and configure WWDT function + * @{ + */ +/** + * @brief Initializes the WWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref WWDT_WIN_25 No dog window size: 25% + * @arg @ref WWDT_WIN_50 No dog window size: 50% + * @arg @ref WWDT_WIN_75 No dog window size: 75% + * @arg @ref WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_wwdt_init(uint32_t load, ald_wwdt_win_t win, type_func_t interrupt) +{ + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Start the WWDT + * @retval None + */ +void ald_wwdt_start(void) +{ + ALD_WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_wwdt_get_value(void) +{ + return WWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_wwdt_get_flag_status(void) +{ + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_wwdt_clear_flag_status(void) +{ + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x55AA); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_wwdt_feed_dog(void) +{ + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0xFFFFFFFF); + ALD_WWDT_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup IWDT_Public_Functions IWDT Public Functions + * @brief Init and configure IWDT function + * @{ + */ +/** + * @brief Initializes the IWDG according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + ALD_IWDT_LOCK(); + + return; +} + +/** + * @brief Start the IWDT + * @retval None + */ +void ald_iwdt_start(void) +{ + ALD_IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + ALD_IWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_iwdt_get_value(void) +{ + return IWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_iwdt_get_flag_status(void) +{ + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_iwdt_clear_flag_status(void) +{ + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 0x55AA); + ALD_IWDT_LOCK(); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_iwdt_feed_dog(void) +{ + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 0xFFFFFFFF); + ALD_IWDT_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_adc.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_adc.h new file mode 100644 index 0000000000..28a31ce292 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_adc.h @@ -0,0 +1,416 @@ +/********************************************************************************** + * + * @file reg_adc.h + * @brief ADC Head File + * + * @date 26 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_ADC_H__ +#define __REG_ADC_H__ + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_CNTW_POSS 16U +#define ADC_CON0_CNTW_POSE 18U +#define ADC_CON0_CNTW_MSK BITS(ADC_CON0_CNTW_POSS,ADC_CON0_CNTW_POSE) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_NETS_POSS 28U +#define ADC_CON1_NETS_POSE 29U +#define ADC_CON1_NETS_MSK BITS(ADC_CON1_NETS_POSS,ADC_CON1_NETS_POSE) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_IETS_POSS 20U +#define ADC_CON1_IETS_POSE 21U +#define ADC_CON1_IETS_MSK BITS(ADC_CON1_IETS_POSS,ADC_CON1_IETS_POSE) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_DMA_POS 8U +#define ADC_CON1_DMA_MSK BIT(ADC_CON1_DMA_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 31U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_SMPT3 register ************************/ + +#define ADC_SMPT3_SMP_POSS 0U +#define ADC_SMPT3_SMP_POSE 31U +#define ADC_SMPT3_SMP_MSK BITS(ADC_SMPT3_SMP_POSS,ADC_SMPT3_SMP_POSE) + +/****************** Bit definition for ADC_NCHOFF register ************************/ + +#define ADC_NCHOFF_NOFF_POSS 0U +#define ADC_NCHOFF_NOFF_POSE 11U +#define ADC_NCHOFF_NOFF_MSK BITS(ADC_NCHOFF_NOFF_POSS,ADC_NCHOFF_NOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF1_POSS 0U +#define ADC_ICHOFF1_IOFF1_POSE 11U +#define ADC_ICHOFF1_IOFF1_MSK BITS(ADC_ICHOFF1_IOFF1_POSS,ADC_ICHOFF1_IOFF1_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF2_POSS 0U +#define ADC_ICHOFF2_IOFF2_POSE 11U +#define ADC_ICHOFF2_IOFF2_MSK BITS(ADC_ICHOFF2_IOFF2_POSS,ADC_ICHOFF2_IOFF2_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF3_POSS 0U +#define ADC_ICHOFF3_IOFF3_POSE 11U +#define ADC_ICHOFF3_IOFF3_MSK BITS(ADC_ICHOFF3_IOFF3_POSS,ADC_ICHOFF3_IOFF3_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF4_POSS 0U +#define ADC_ICHOFF4_IOFF4_POSE 11U +#define ADC_ICHOFF4_IOFF4_MSK BITS(ADC_ICHOFF4_IOFF4_POSS,ADC_ICHOFF4_IOFF4_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_CALZERO_POS 29U +#define ADC_CCR_CALZERO_MSK BIT(ADC_CCR_CALZERO_POS) + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_TSEN_POS 20U +#define ADC_CCR_TSEN_MSK BIT(ADC_CCR_TSEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POS 17U +#define ADC_CCR_VRPSEL_MSK BIT(ADC_CCR_VRPSEL_POS) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_PREDIV_POS 3U +#define ADC_CCR_PREDIV_MSK BIT(ADC_CCR_PREDIV_POS) + +#define ADC_CCR_POSDIV_POSS 0U +#define ADC_CCR_POSDIV_POSE 2U +#define ADC_CCR_POSDIV_MSK BITS(ADC_CCR_POSDIV_POSS,ADC_CCR_POSDIV_POSE) + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t SMPT3; + __IO uint32_t NCHOFF; + __IO uint32_t ICHOFF1; + __IO uint32_t ICHOFF2; + __IO uint32_t ICHOFF3; + __IO uint32_t ICHOFF4; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __I uint32_t ICHDR1; + __I uint32_t ICHDR2; + __I uint32_t ICHDR3; + __I uint32_t ICHDR4; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + + + + + +#endif /* __REG_ADC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_cmu.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_cmu.h new file mode 100644 index 0000000000..a04580962e --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_cmu.h @@ -0,0 +1,354 @@ +/********************************************************************************** + * + * @file reg_cmu.h + * @brief CMU Head File + * + * @date 14 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 14 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_CMU_H__ +#define __REG_CMU_H__ + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_PCLKDIV_POSS 16U +#define CMU_CFGR_PCLKDIV_POSE 19U +#define CMU_CFGR_PCLKDIV_MSK BITS(CMU_CFGR_PCLKDIV_POSS,CMU_CFGR_PCLKDIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_USBSW_POS 4U +#define CMU_CFGR_USBSW_MSK BIT(CMU_CFGR_USBSW_POS) + +#define CMU_CFGR_I2SSW_POS 0U +#define CMU_CFGR_I2SSW_MSK BIT(CMU_CFGR_I2SSW_POS) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_HOSCFLYBPS_POS 10U +#define CMU_CLKENR_HOSCFLYBPS_MSK BIT(CMU_CLKENR_HOSCFLYBPS_POS) + +#define CMU_CLKENR_HOSCBPS_POS 9U +#define CMU_CLKENR_HOSCBPS_MSK BIT(CMU_CLKENR_HOSCBPS_POS) + +#define CMU_CLKENR_HOSC32K_POS 8U +#define CMU_CLKENR_HOSC32K_MSK BIT(CMU_CLKENR_HOSC32K_POS) + +#define CMU_CLKENR_USBCKEN_POS 7U +#define CMU_CLKENR_USBCKEN_MSK BIT(CMU_CLKENR_USBCKEN_POS) + +#define CMU_CLKENR_I2SCKEN_POS 6U +#define CMU_CLKENR_I2SCKEN_MSK BIT(CMU_CLKENR_I2SCKEN_POS) + +#define CMU_CLKENR_HRC48MFLYBPS_POS 4U +#define CMU_CLKENR_HRC48MFLYBPS_MSK BIT(CMU_CLKENR_HRC48MFLYBPS_POS) + +#define CMU_CLKENR_PLLEN_POS 3U +#define CMU_CLKENR_PLLEN_MSK BIT(CMU_CLKENR_PLLEN_POS) + +#define CMU_CLKENR_HRC4MEN_POS 2U +#define CMU_CLKENR_HRC4MEN_MSK BIT(CMU_CLKENR_HRC4MEN_POS) + +#define CMU_CLKENR_HRC48MEN_POS 1U +#define CMU_CLKENR_HRC48MEN_MSK BIT(CMU_CLKENR_HRC48MEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLLRDY_POS 24U +#define CMU_CLKSR_PLLRDY_MSK BIT(CMU_CLKSR_PLLRDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRC48MRDY_POS 18U +#define CMU_CLKSR_HRC48MRDY_MSK BIT(CMU_CLKSR_HRC48MRDY_POS) + +#define CMU_CLKSR_HRC4MRDY_POS 17U +#define CMU_CLKSR_HRC4MRDY_MSK BIT(CMU_CLKSR_HRC4MRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_HRC48MACT_POS 3U +#define CMU_CLKSR_HRC48MACT_MSK BIT(CMU_CLKSR_HRC48MACT_POS) + +#define CMU_CLKSR_HRC4MACT_POS 2U +#define CMU_CLKSR_HRC4MACT_MSK BIT(CMU_CLKSR_HRC4MACT_POS) + +#define CMU_CLKSR_PLLACT_POS 1U +#define CMU_CLKSR_PLLACT_MSK BIT(CMU_CLKSR_PLLACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_REFS_POSS 2U +#define CMU_PLLCFG_REFS_POSE 3U +#define CMU_PLLCFG_REFS_MSK BITS(CMU_PLLCFG_REFS_POSS,CMU_PLLCFG_REFS_POSE) + +#define CMU_PLLCFG_CLKOS_POSS 0U +#define CMU_PLLCFG_CLKOS_POSE 1U +#define CMU_PLLCFG_CLKOS_MSK BITS(CMU_PLLCFG_CLKOS_POSS,CMU_PLLCFG_CLKOS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 2U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_FLAG_POS 1U +#define CMU_HOSMCR_FLAG_MSK BIT(CMU_HOSMCR_FLAG_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 25U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 11U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHBENR register ************************/ +#define CMU_AHBENR_CSUEN_POS 7U +#define CMU_AHBENR_CSUEN_MSK BIT(CMU_AHBENR_CSUEN_POS) + +#define CMU_AHBENR_USBEN_POS 6U +#define CMU_AHBENR_USBEN_MSK BIT(CMU_AHBENR_USBEN_POS) + +#define CMU_AHBENR_PISEN_POS 5U +#define CMU_AHBENR_PISEN_MSK BIT(CMU_AHBENR_PISEN_POS) + +#define CMU_AHBENR_DMAEN_POS 2U +#define CMU_AHBENR_DMAEN_MSK BIT(CMU_AHBENR_DMAEN_POS) + +#define CMU_AHBENR_CRCEN_POS 1U +#define CMU_AHBENR_CRCEN_MSK BIT(CMU_AHBENR_CRCEN_POS) + +#define CMU_AHBENR_GPIOEN_POS 0U +#define CMU_AHBENR_GPIOEN_MSK BIT(CMU_AHBENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APBENR register ************************/ + +#define CMU_APBENR_ADCEN_POS 25U +#define CMU_APBENR_ADCEN_MSK BIT(CMU_APBENR_ADCEN_POS) + +#define CMU_APBENR_DBGCEN_POS 24U +#define CMU_APBENR_DBGCEN_MSK BIT(CMU_APBENR_DBGCEN_POS) + +#define CMU_APBENR_IWDTEN_POS 23U +#define CMU_APBENR_IWDTEN_MSK BIT(CMU_APBENR_IWDTEN_POS) + +#define CMU_APBENR_WWDTEN_POS 22U +#define CMU_APBENR_WWDTEN_MSK BIT(CMU_APBENR_WWDTEN_POS) + +#define CMU_APBENR_I2C1EN_POS 21U +#define CMU_APBENR_I2C1EN_MSK BIT(CMU_APBENR_I2C1EN_POS) + +#define CMU_APBENR_I2C0EN_POS 20U +#define CMU_APBENR_I2C0EN_MSK BIT(CMU_APBENR_I2C0EN_POS) + +#define CMU_APBENR_SPI1EN_POS 17U +#define CMU_APBENR_SPI1EN_MSK BIT(CMU_APBENR_SPI1EN_POS) + +#define CMU_APBENR_SPI0EN_POS 16U +#define CMU_APBENR_SPI0EN_MSK BIT(CMU_APBENR_SPI0EN_POS) + +#define CMU_APBENR_CUART2EN_POS 14U +#define CMU_APBENR_CUART2EN_MSK BIT(CMU_APBENR_CUART2EN_POS) + +#define CMU_APBENR_CUART1EN_POS 13U +#define CMU_APBENR_CUART1EN_MSK BIT(CMU_APBENR_CUART1EN_POS) + +#define CMU_APBENR_CUART0EN_POS 12U +#define CMU_APBENR_CUART0EN_MSK BIT(CMU_APBENR_CUART0EN_POS) + +#define CMU_APBENR_EUART1EN_POS 9U +#define CMU_APBENR_EUART1EN_MSK BIT(CMU_APBENR_EUART1EN_POS) + +#define CMU_APBENR_EUART0EN_POS 8U +#define CMU_APBENR_EUART0EN_MSK BIT(CMU_APBENR_EUART0EN_POS) + +#define CMU_APBENR_GP16C4T2EN_POS 4U +#define CMU_APBENR_GP16C4T2EN_MSK BIT(CMU_APBENR_GP16C4T2EN_POS) + +#define CMU_APBENR_GP16C4T1EN_POS 3U +#define CMU_APBENR_GP16C4T1EN_MSK BIT(CMU_APBENR_GP16C4T1EN_POS) + +#define CMU_APBENR_GP16C4T0EN_POS 2U +#define CMU_APBENR_GP16C4T0EN_MSK BIT(CMU_APBENR_GP16C4T0EN_POS) + +#define CMU_APBENR_BS16T0EN_POS 1U +#define CMU_APBENR_BS16T0EN_MSK BIT(CMU_APBENR_BS16T0EN_POS) + +#define CMU_APBENR_AD16C4T0EN_POS 0U +#define CMU_APBENR_AD16C4T0EN_MSK BIT(CMU_APBENR_AD16C4T0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRC48MEN_POS 2U +#define CMU_LPENR_HRC48MEN_MSK BIT(CMU_LPENR_HRC48MEN_POS) + +#define CMU_LPENR_HRC4MEN_POS 2U +#define CMU_LPENR_HRC4MEN_MSK BIT(CMU_LPENR_HRC4MEN_POS) + +#define CMU_LPENR_PLLEN_POS 0U +#define CMU_LPENR_PLLEN_MSK BIT(CMU_LPENR_PLLEN_POS) + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + uint32_t RESERVED1[1] ; + __IO uint32_t PULMCR; + uint32_t RESERVED2[1] ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED3[2] ; + __IO uint32_t AHBENR; + uint32_t RESERVED4[3] ; + __IO uint32_t APBENR; + uint32_t RESERVED5[3] ; + __IO uint32_t LPENR; +} CMU_TypeDef; + + + + + +#endif /*__REG_CMU_H__*/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_crc.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_crc.h new file mode 100644 index 0000000000..9361168ac7 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_crc.h @@ -0,0 +1,105 @@ +/********************************************************************************** + * + * @file reg_crc.h + * @brief CRC Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_CRC_H__ +#define __REG_CRC_H__ + +/****************** Bit definition for CRC_CR register ************************/ + +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + + + + + +#endif /* __REG_CRC_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_csu.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_csu.h new file mode 100644 index 0000000000..f71b4bc009 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_csu.h @@ -0,0 +1,225 @@ +/********************************************************************************** + * + * @file reg_csu.h + * @brief CSU Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_CSU_H__ +#define __REG_CSU_H__ + +/****************** Bit definition for CSU_CON register ************************/ + +#define CSU_CON_TRIM_POSS 8U +#define CSU_CON_TRIM_POSE 16U +#define CSU_CON_TRIM_MSK BITS(CSU_CON_TRIM_POSS,CSU_CON_TRIM_POSE) + +#define CSU_CON_SYNCGEN_POS 2U +#define CSU_CON_SYNCGEN_MSK BIT(CSU_CON_SYNCGEN_POS) + +#define CSU_CON_AUTOEN_POS 1U +#define CSU_CON_AUTOEN_MSK BIT(CSU_CON_AUTOEN_POS) + +#define CSU_CON_CNTEN_POS 0U +#define CSU_CON_CNTEN_MSK BIT(CSU_CON_CNTEN_POS) + +/****************** Bit definition for CSU_CFG register ************************/ + +#define CSU_CFG_TRIMSEL_POS 31U +#define CSU_CFG_TRIMSEL_MSK BIT(CSU_CFG_TRIMSEL_POS) + +#define CSU_CFG_POLSEL_POS 30U +#define CSU_CFG_POLSEL_MSK BIT(CSU_CFG_POLSEL_POS) + +#define CSU_CFG_SYNCSRC_POSS 28U +#define CSU_CFG_SYNCSRC_POSE 29U +#define CSU_CFG_SYNCSRC_MSK BITS(CSU_CFG_SYNCSRC_POSS,CSU_CFG_SYNCSRC_POSE) + +#define CSU_CFG_SYNCDIV_POSS 24U +#define CSU_CFG_SYNCDIV_POSE 26U +#define CSU_CFG_SYNCDIV_MSK BITS(CSU_CFG_SYNCDIV_POSS,CSU_CFG_SYNCDIV_POSE) + +#define CSU_CFG_CNTTH_POSS 16U +#define CSU_CFG_CNTTH_POSE 23U +#define CSU_CFG_CNTTH_MSK BITS(CSU_CFG_CNTTH_POSS,CSU_CFG_CNTTH_POSE) + +#define CSU_CFG_RELOAD_POSS 0U +#define CSU_CFG_RELOAD_POSE 15U +#define CSU_CFG_RELOAD_MSK BITS(CSU_CFG_RELOAD_POSS,CSU_CFG_RELOAD_POSE) + +/****************** Bit definition for CSU_STAT register ************************/ + +#define CSU_STAT_OPT_TRIM_POSS 23U +#define CSU_STAT_OPT_TRIM_POSE 31U +#define CSU_STAT_OPT_TRIM_MSK BITS(CSU_STAT_OPT_TRIM_POSS,CSU_STAT_OPT_TRIM_POSE) + +#define CSU_STAT_CNTDIR_POS 16U +#define CSU_STAT_CNTDIR_MSK BIT(CSU_STAT_CNTDIR_POS) + +#define CSU_STAT_CNTCAP_POSS 0U +#define CSU_STAT_CNTCAP_POSE 15U +#define CSU_STAT_CNTCAP_MSK BITS(CSU_STAT_CNTCAP_POSS,CSU_STAT_CNTCAP_POSE) + +/****************** Bit definition for CSU_IER register ************************/ + +#define CSU_IER_FHIT_POS 5U +#define CSU_IER_FHIT_MSK BIT(CSU_IER_FHIT_POS) + +#define CSU_IER_TRIMERR_POS 4U +#define CSU_IER_TRIMERR_MSK BIT(CSU_IER_TRIMERR_POS) + +#define CSU_IER_FFAULT_POS 3U +#define CSU_IER_FFAULT_MSK BIT(CSU_IER_FFAULT_POS) + +#define CSU_IER_FERROR_POS 2U +#define CSU_IER_FERROR_MSK BIT(CSU_IER_FERROR_POS) + +#define CSU_IER_FWARN_POS 1U +#define CSU_IER_FWARN_MSK BIT(CSU_IER_FWARN_POS) + +#define CSU_IER_FMATCH_POS 0U +#define CSU_IER_FMATCH_MSK BIT(CSU_IER_FMATCH_POS) + +/****************** Bit definition for CSU_IDR register ************************/ + +#define CSU_IDR_FHIT_POS 5U +#define CSU_IDR_FHIT_MSK BIT(CSU_IDR_FHIT_POS) + +#define CSU_IDR_TRIMERR_POS 4U +#define CSU_IDR_TRIMERR_MSK BIT(CSU_IDR_TRIMERR_POS) + +#define CSU_IDR_FFAULT_POS 3U +#define CSU_IDR_FFAULT_MSK BIT(CSU_IDR_FFAULT_POS) + +#define CSU_IDR_FERROR_POS 2U +#define CSU_IDR_FERROR_MSK BIT(CSU_IDR_FERROR_POS) + +#define CSU_IDR_FWARN_POS 1U +#define CSU_IDR_FWARN_MSK BIT(CSU_IDR_FWARN_POS) + +#define CSU_IDR_FMATCH_POS 0U +#define CSU_IDR_FMATCH_MSK BIT(CSU_IDR_FMATCH_POS) + +/****************** Bit definition for CSU_IVS register ************************/ + +#define CSU_IVS_FHIT_POS 5U +#define CSU_IVS_FHIT_MSK BIT(CSU_IVS_FHIT_POS) + +#define CSU_IVS_TRIMERR_POS 4U +#define CSU_IVS_TRIMERR_MSK BIT(CSU_IVS_TRIMERR_POS) + +#define CSU_IVS_FFAULT_POS 3U +#define CSU_IVS_FFAULT_MSK BIT(CSU_IVS_FFAULT_POS) + +#define CSU_IVS_FERROR_POS 2U +#define CSU_IVS_FERROR_MSK BIT(CSU_IVS_FERROR_POS) + +#define CSU_IVS_FWARN_POS 1U +#define CSU_IVS_FWARN_MSK BIT(CSU_IVS_FWARN_POS) + +#define CSU_IVS_FMATCH_POS 0U +#define CSU_IVS_FMATCH_MSK BIT(CSU_IVS_FMATCH_POS) + +/****************** Bit definition for CSU_RIF register ************************/ + +#define CSU_RIF_FHIT_POS 5U +#define CSU_RIF_FHIT_MSK BIT(CSU_RIF_FHIT_POS) + +#define CSU_RIF_TRIMERR_POS 4U +#define CSU_RIF_TRIMERR_MSK BIT(CSU_RIF_TRIMERR_POS) + +#define CSU_RIF_FFAULT_POS 3U +#define CSU_RIF_FFAULT_MSK BIT(CSU_RIF_FFAULT_POS) + +#define CSU_RIF_FERROR_POS 2U +#define CSU_RIF_FERROR_MSK BIT(CSU_RIF_FERROR_POS) + +#define CSU_RIF_FWARN_POS 1U +#define CSU_RIF_FWARN_MSK BIT(CSU_RIF_FWARN_POS) + +#define CSU_RIF_FMATCH_POS 0U +#define CSU_RIF_FMATCH_MSK BIT(CSU_RIF_FMATCH_POS) + +/****************** Bit definition for CSU_IFM register ************************/ + +#define CSU_IFM_FHIT_POS 5U +#define CSU_IFM_FHIT_MSK BIT(CSU_IFM_FHIT_POS) + +#define CSU_IFM_TRIMERR_POS 4U +#define CSU_IFM_TRIMERR_MSK BIT(CSU_IFM_TRIMERR_POS) + +#define CSU_IFM_FFAULT_POS 3U +#define CSU_IFM_FFAULT_MSK BIT(CSU_IFM_FFAULT_POS) + +#define CSU_IFM_FERROR_POS 2U +#define CSU_IFM_FERROR_MSK BIT(CSU_IFM_FERROR_POS) + +#define CSU_IFM_FWARN_POS 1U +#define CSU_IFM_FWARN_MSK BIT(CSU_IFM_FWARN_POS) + +#define CSU_IFM_FMATCH_POS 0U +#define CSU_IFM_FMATCH_MSK BIT(CSU_IFM_FMATCH_POS) + +/****************** Bit definition for CSU_ICR register ************************/ + +#define CSU_ICR_FHIT_POS 5U +#define CSU_ICR_FHIT_MSK BIT(CSU_ICR_FHIT_POS) + +#define CSU_ICR_TRIMERR_POS 4U +#define CSU_ICR_TRIMERR_MSK BIT(CSU_ICR_TRIMERR_POS) + +#define CSU_ICR_FFAULT_POS 3U +#define CSU_ICR_FFAULT_MSK BIT(CSU_ICR_FFAULT_POS) + +#define CSU_ICR_FERROR_POS 2U +#define CSU_ICR_FERROR_MSK BIT(CSU_ICR_FERROR_POS) + +#define CSU_ICR_FWARN_POS 1U +#define CSU_ICR_FWARN_MSK BIT(CSU_ICR_FWARN_POS) + +#define CSU_ICR_FMATCH_POS 0U +#define CSU_ICR_FMATCH_MSK BIT(CSU_ICR_FMATCH_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __I uint32_t STAT; + uint32_t RESERVED0 ; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} CSU_TypeDef; + + + + + +#endif /* __REG_CSU_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dbg.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dbg.h new file mode 100644 index 0000000000..dedda8d8a0 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dbg.h @@ -0,0 +1,91 @@ +/********************************************************************************** + * + * @file reg_dbg.h + * @brief DBG Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_DBG_H__ +#define __REG_DBG_H__ + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_GP16C2T2_STOP_POS 4U +#define DBGC_APB1FZ_GP16C2T2_STOP_MSK BIT(DBGC_APB1FZ_GP16C2T2_STOP_POS) + +#define DBGC_APB1FZ_GP16C2T1_STOP_POS 3U +#define DBGC_APB1FZ_GP16C2T1_STOP_MSK BIT(DBGC_APB1FZ_GP16C2T1_STOP_POS) + +#define DBGC_APB1FZ_GP16C2T0_STOP_POS 2U +#define DBGC_APB1FZ_GP16C2T0_STOP_MSK BIT(DBGC_APB1FZ_GP16C2T0_STOP_POS) + +#define DBGC_APB1FZ_BS16T0_STOP_POS 1U +#define DBGC_APB1FZ_BS16T0_STOP_MSK BIT(DBGC_APB1FZ_BS16T0_STOP_POS) + +#define DBGC_APB1FZ_AD16C4T0_STOP_POS 0U +#define DBGC_APB1FZ_AD16C4T0_STOP_MSK BIT(DBGC_APB1FZ_AD16C4T0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_I2C0_STOP_POS 0U +#define DBGC_APB2FZ_I2C0_STOP_MSK BIT(DBGC_APB2FZ_I2C0_STOP_POS) + +typedef struct +{ + __I uint32_t IDCODE; + uint32_t RESERVED0 ; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + + + + + +#endif /* __REG_DBG_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dma.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dma.h new file mode 100644 index 0000000000..d617e7cd63 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_dma.h @@ -0,0 +1,149 @@ +/********************************************************************************** + * + * @file reg_dma.h + * @brief DMA Head File + * + * @date 19 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 12 July 2022 Lisq the first version + * 19 July 2022 Shiwa the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_DMA_H__ +#define __REG_DMA_H__ + +#define DMA_CHANNELS 7 + +#define DMA_CH0_TC_POS 0U +#define DMA_CH0_TC_MSK BIT(DMA_CH0_TC_POS) +#define DMA_CH0_HT_POS 1U +#define DMA_CH0_HT_MSK BIT(DMA_CH0_HT_POS) + +#define DMA_CH1_TC_POS 2U +#define DMA_CH1_TC_MSK BIT(DMA_CH1_TC_POS) +#define DMA_CH1_HT_POS 3U +#define DMA_CH1_HT_MSK BIT(DMA_CH1_HT_POS) + +#define DMA_CH2_TC_POS 4U +#define DMA_CH2_TC_MSK BIT(DMA_CH2_TC_POS) +#define DMA_CH2_HT_POS 5U +#define DMA_CH2_HT_MSK BIT(DMA_CH2_HT_POS) + +#define DMA_CH3_TC_POS 6U +#define DMA_CH3_TC_MSK BIT(DMA_CH3_TC_POS) +#define DMA_CH3_HT_POS 7U +#define DMA_CH3_HT_MSK BIT(DMA_CH3_HT_POS) + +#define DMA_CH4_TC_POS 8U +#define DMA_CH4_TC_MSK BIT(DMA_CH4_TC_POS) +#define DMA_CH4_HT_POS 9U +#define DMA_CH4_HT_MSK BIT(DMA_CH4_HT_POS) + +#define DMA_CH5_TC_POS 10U +#define DMA_CH5_TC_MSK BIT(DMA_CH5_TC_POS) +#define DMA_CH5_HT_POS 11U +#define DMA_CH5_HT_MSK BIT(DMA_CH5_HT_POS) + +#define DMA_CH6_TC_POS 12U +#define DMA_CH6_TC_MSK BIT(DMA_CH6_TC_POS) +#define DMA_CH6_HT_POS 13U +#define DMA_CH6_HT_MSK BIT(DMA_CH6_HT_POS) + +#define DMA_SELCON_MSEL_POSS 8U +#define DMA_SELCON_MSEL_POSE 12U +#define DMA_SELCON_MSEL_MSK BITS(DMA_SELCON_MSEL_POSS,DMA_SELCON_MSEL_POSE) + +#define DMA_SELCON_MSIGSEL_POSS 0U +#define DMA_SELCON_MSIGSEL_POSE 3U +#define DMA_SELCON_MSIGSEL_MSK BITS(DMA_SELCON_MSIGSEL_POSS,DMA_SELCON_MSIGSEL_POSE) + +#define DMA_CON_MAX_BURST_POSS 16U +#define DMA_CON_MAX_BURST_POSE 19U +#define DMA_CON_MAX_BURST_MSK BITS(DMA_CON_MAX_BURST_POSS,DMA_CON_MAX_BURST_POSE) + +#define DMA_CON_DDWSEL_POSS 13U +#define DMA_CON_DDWSEL_POSE 14U +#define DMA_CON_DDWSEL_MSK BITS(DMA_CON_DDWSEL_POSS,DMA_CON_DDWSEL_POSE) + +#define DMA_CON_DINC_POS 12U +#define DMA_CON_DINC_MSK BIT(DMA_CON_DINC_POS) + +#define DMA_CON_SDWSEL_POSS 9U +#define DMA_CON_SDWSEL_POSE 10U +#define DMA_CON_SDWSEL_MSK BITS(DMA_CON_SDWSEL_POSS,DMA_CON_SDWSEL_POSE) + +#define DMA_CON_SINC_POS 8U +#define DMA_CON_SINC_MSK BIT(DMA_CON_SINC_POS) + +#define DMA_CON_CHPRI_POSS 4U +#define DMA_CON_CHPRI_POSE 5U +#define DMA_CON_CHPRI_MSK BITS(DMA_CON_CHPRI_POSS,DMA_CON_CHPRI_POSE) + +#define DMA_CON_M2M_POS 3U +#define DMA_CON_M2M_MSK BIT(DMA_CON_M2M_POS) + +#define DMA_CON_DIR_POS 2U +#define DMA_CON_DIR_MSK BIT(DMA_CON_DIR_POS) + +#define DMA_CON_CIRC_POS 1U +#define DMA_CON_CIRC_MSK BIT(DMA_CON_CIRC_POS) + +#define DMA_CON_CHEN_POS 0U +#define DMA_CON_CHEN_MSK BIT(DMA_CON_CHEN_POS) + +#define DMA_NDT_NRDT_POSS 16U +#define DMA_NDT_NRDT_POSE 31U +#define DMA_NDT_NRDT_MSK BITS(DMA_NDT_NRDT_POSS,DMA_NDT_NRDT_POSE) + +#define DMA_NDT_TNDT_POSS 0U +#define DMA_NDT_TNDT_POSE 15U +#define DMA_NDT_TNDT_MSK BITS(DMA_NDT_TNDT_POSS,DMA_NDT_TNDT_POSE) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t SAR; + __IO uint32_t DAR; + __IO uint32_t NDT; +} DMA_CHANNEL_Typedef; +typedef struct +{ + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __I uint32_t RESERVED[2]; + DMA_CHANNEL_Typedef CHANNEL[DMA_CHANNELS]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CH_SELCON[DMA_CHANNELS]; +} DMA_MUX_Typedef; + + + +#endif /* __REG_DMA_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_gpio.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_gpio.h new file mode 100644 index 0000000000..0d34992f61 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_gpio.h @@ -0,0 +1,334 @@ +/********************************************************************************** + * + * @file reg_gpio.h + * @brief gpio Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_GPIO_H__ +#define __REG_GPIO_H__ + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_OD register ************************/ + +#define GPIO_OD_OD_POSS 0U +#define GPIO_OD_OD_POSE 31U +#define GPIO_OD_OD_MSK BITS(GPIO_OD_OD_POSS,GPIO_OD_OD_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_ODRV register ************************/ + +#define GPIO_ODRV_ODRV_POSS 0U +#define GPIO_ODRV_ODRV_POSE 31U +#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 31U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 27U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 23U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 19U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 15U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 11U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 7U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 3U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 31U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 27U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 23U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 19U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 15U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 11U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 7U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 3U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t OD; + __IO uint32_t PUPD; + __IO uint32_t ODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED2 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED3 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED4 ; + __O uint32_t EXTISFR; + uint32_t RESERVED5 ; + __O uint32_t EXTICFR; + uint32_t RESERVED6 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED7[2] ; + __IO uint32_t EXTIFLTCR; +}EXTI_TypeDef; + + + + + +#endif /* __REG_GPIO_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_i2c.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_i2c.h new file mode 100644 index 0000000000..295c668dbc --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_i2c.h @@ -0,0 +1,564 @@ +/********************************************************************************** + * + * @file reg_i2c.h + * @brief I2C Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + +/****************** Bit definition for I2C_CON1 register ************************/ + +# define I2C_CON1_NBYTES_POSS 24U +# define I2C_CON1_NBYTES_POSE 31U +# define I2C_CON1_NBYTES_MSK BITS(I2C_CON1_NBYTES_POSS, I2C_CON1_NBYTES_POSE) + +# define I2C_CON1_PECEN_POS 23U +# define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +# define I2C_CON1_ALERTEN_POS 22U +# define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) + +# define I2C_CON1_SMBDEN_POS 21U +# define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) + +# define I2C_CON1_SMBHEN_POS 20U +# define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) + +# define I2C_CON1_GCEN_POS 19U +# define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +# define I2C_CON1_NOSTRETCH_POS 17U +# define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) + +# define I2C_CON1_SBC_POS 16U +# define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) + +# define I2C_CON1_RXDMAEN_POS 15U +# define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) + +# define I2C_CON1_TXDMAEN_POS 14U +# define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) + +# define I2C_CON1_DNF_POSS 8U +# define I2C_CON1_DNF_POSE 11U +# define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS, I2C_CON1_DNF_POSE) + +# define I2C_CON1_PE_POS 0U +# define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +# define I2C_CON2_ACK_UPD_POS 29U +# define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) + +# define I2C_CON2_HOLDACK_POS 28U +# define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) + +# define I2C_CON2_PECBYTE_POS 26U +# define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) + +# define I2C_CON2_AUTOEND_POS 25U +# define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) + +# define I2C_CON2_RELOAD_POS 24U +# define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) + +# define I2C_CON2_NBYTES_POSS 16U +# define I2C_CON2_NBYTES_POSE 23U +# define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS, I2C_CON2_NBYTES_POSE) + +# define I2C_CON2_NACK_POS 15U +# define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) + +# define I2C_CON2_STOP_POS 14U +# define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) + +# define I2C_CON2_START_POS 13U +# define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) + +# define I2C_CON2_HEAD10R_POS 12U +# define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) + +# define I2C_CON2_ADD10_POS 11U +# define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) + +# define I2C_CON2_RD_WRN_POS 10U +# define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) + +# define I2C_CON2_SADD_POSS 0U +# define I2C_CON2_SADD_POSE 9U +# define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS, I2C_CON2_SADD_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +# define I2C_ADDR1_OA1EN_POS 15U +# define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) + +# define I2C_ADDR1_OA1MODE_POS 10U +# define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) + +# define I2C_ADDR1_OA1_POSS 0U +# define I2C_ADDR1_OA1_POSE 9U +# define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS, I2C_ADDR1_OA1_POSE) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +# define I2C_ADDR2_OA2EN_POS 15U +# define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) + +# define I2C_ADDR2_OA2MSK_POSS 8U +# define I2C_ADDR2_OA2MSK_POSE 10U +# define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS, I2C_ADDR2_OA2MSK_POSE) + +# define I2C_ADDR2_OA2_POSS 1U +# define I2C_ADDR2_OA2_POSE 7U +# define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS, I2C_ADDR2_OA2_POSE) + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +# define I2C_TIMINGR_PRESC_POSS 28U +# define I2C_TIMINGR_PRESC_POSE 31U +# define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS, I2C_TIMINGR_PRESC_POSE) + +# define I2C_TIMINGR_SCLDEL_POSS 20U +# define I2C_TIMINGR_SCLDEL_POSE 23U +# define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS, I2C_TIMINGR_SCLDEL_POSE) + +# define I2C_TIMINGR_SDADEL_POSS 16U +# define I2C_TIMINGR_SDADEL_POSE 19U +# define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS, I2C_TIMINGR_SDADEL_POSE) + +# define I2C_TIMINGR_SCLH_POSS 8U +# define I2C_TIMINGR_SCLH_POSE 15U +# define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS, I2C_TIMINGR_SCLH_POSE) + +# define I2C_TIMINGR_SCLL_POSS 0U +# define I2C_TIMINGR_SCLL_POSE 7U +# define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS, I2C_TIMINGR_SCLL_POSE) + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +# define I2C_TIMEOUTR_TEXTEN_POS 31U +# define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) + +# define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +# define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +# define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS, I2C_TIMEOUTR_TIMEOUTB_POSE) + +# define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +# define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) + +# define I2C_TIMEOUTR_TIDLE_POS 12U +# define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) + +# define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +# define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +# define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS, I2C_TIMEOUTR_TIMEOUTA_POSE) + +/****************** Bit definition for I2C_STAT register ************************/ + +# define I2C_STAT_ADDCODE_POSS 17U +# define I2C_STAT_ADDCODE_POSE 23U +# define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS, I2C_STAT_ADDCODE_POSE) + +# define I2C_STAT_DIR_POS 16U +# define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) + +# define I2C_STAT_BUSY_POS 15U +# define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) + +# define I2C_STAT_TCR_POS 11U +# define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) + +# define I2C_STAT_TC_POS 10U +# define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) + +# define I2C_STAT_RXUD_POS 8U +# define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) + +# define I2C_STAT_RXOV_POS 7U +# define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) + +# define I2C_STAT_RXNE_POS 5U +# define I2C_STAT_RXNE_MSK BIT(I2C_STAT_RXNE_POS) + +# define I2C_STAT_TXUD_POS 3U +# define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) + +# define I2C_STAT_TXOV_POS 2U +# define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) + +# define I2C_STAT_TXE_POS 0U +# define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) + +/****************** Bit definition for I2C_PECR register ************************/ + +# define I2C_PECR_PEC_POSS 0U +# define I2C_PECR_PEC_POSE 7U +# define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS, I2C_PECR_PEC_POSE) + +/****************** Bit definition for I2C_RXDATA register ************************/ + +# define I2C_RXDATA_RXDATA_POSS 0U +# define I2C_RXDATA_RXDATA_POSE 7U +# define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS, I2C_RXDATA_RXDATA_POSE) + +/****************** Bit definition for I2C_TXDATA register ************************/ + +# define I2C_TXDATA_TXDATA_POSS 0U +# define I2C_TXDATA_TXDATA_POSE 7U +# define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS, I2C_TXDATA_TXDATA_POSE) + +/****************** Bit definition for I2C_IER register ************************/ + +# define I2C_IER_ALERT_POS 20U +# define I2C_IER_ALERT_MSK BIT(I2C_IER_ALERT_POS) + +# define I2C_IER_TOUT_POS 19U +# define I2C_IER_TOUT_MSK BIT(I2C_IER_TOUT_POS) + +# define I2C_IER_PECE_POS 18U +# define I2C_IER_PECE_MSK BIT(I2C_IER_PECE_POS) + +# define I2C_IER_ARLO_POS 17U +# define I2C_IER_ARLO_MSK BIT(I2C_IER_ARLO_POS) + +# define I2C_IER_BERR_POS 16U +# define I2C_IER_BERR_MSK BIT(I2C_IER_BERR_POS) + +# define I2C_IER_STOP_POS 14U +# define I2C_IER_STOP_MSK BIT(I2C_IER_STOP_POS) + +# define I2C_IER_NACK_POS 13U +# define I2C_IER_NACK_MSK BIT(I2C_IER_NACK_POS) + +# define I2C_IER_ADDR_POS 12U +# define I2C_IER_ADDR_MSK BIT(I2C_IER_ADDR_POS) + +# define I2C_IER_TCR_POS 11U +# define I2C_IER_TCR_MSK BIT(I2C_IER_TCR_POS) + +# define I2C_IER_TC_POS 10U +# define I2C_IER_TC_MSK BIT(I2C_IER_TC_POS) + +# define I2C_IER_RXUD_POS 8U +# define I2C_IER_RXUD_MSK BIT(I2C_IER_RXUD_POS) + +# define I2C_IER_RXOV_POS 7U +# define I2C_IER_RXOV_MSK BIT(I2C_IER_RXOV_POS) + +# define I2C_IER_RXNE_POS 5U +# define I2C_IER_RXNE_MSK BIT(I2C_IER_RXNE_POS) + +# define I2C_IER_TXUD_POS 3U +# define I2C_IER_TXUD_MSK BIT(I2C_IER_TXUD_POS) + +# define I2C_IER_TXOV_POS 2U +# define I2C_IER_TXOV_MSK BIT(I2C_IER_TXOV_POS) + +# define I2C_IER_TXE_POS 0U +# define I2C_IER_TXE_MSK BIT(I2C_IER_TXE_POS) + +/****************** Bit definition for I2C_IDR register ************************/ + +# define I2C_IDR_ALERT_POS 20U +# define I2C_IDR_ALERT_MSK BIT(I2C_IDR_ALERT_POS) + +# define I2C_IDR_TOUT_POS 19U +# define I2C_IDR_TOUT_MSK BIT(I2C_IDR_TOUT_POS) + +# define I2C_IDR_PECE_POS 18U +# define I2C_IDR_PECE_MSK BIT(I2C_IDR_PECE_POS) + +# define I2C_IDR_ARLO_POS 17U +# define I2C_IDR_ARLO_MSK BIT(I2C_IDR_ARLO_POS) + +# define I2C_IDR_BERR_POS 16U +# define I2C_IDR_BERR_MSK BIT(I2C_IDR_BERR_POS) + +# define I2C_IDR_STOP_POS 14U +# define I2C_IDR_STOP_MSK BIT(I2C_IDR_STOP_POS) + +# define I2C_IDR_NACK_POS 13U +# define I2C_IDR_NACK_MSK BIT(I2C_IDR_NACK_POS) + +# define I2C_IDR_ADDR_POS 12U +# define I2C_IDR_ADDR_MSK BIT(I2C_IDR_ADDR_POS) + +# define I2C_IDR_TCR_POS 11U +# define I2C_IDR_TCR_MSK BIT(I2C_IDR_TCR_POS) + +# define I2C_IDR_TC_POS 10U +# define I2C_IDR_TC_MSK BIT(I2C_IDR_TC_POS) + +# define I2C_IDR_RXUD_POS 8U +# define I2C_IDR_RXUD_MSK BIT(I2C_IDR_RXUD_POS) + +# define I2C_IDR_RXOV_POS 7U +# define I2C_IDR_RXOV_MSK BIT(I2C_IDR_RXOV_POS) + +# define I2C_IDR_RXNE_POS 5U +# define I2C_IDR_RXNE_MSK BIT(I2C_IDR_RXNE_POS) + +# define I2C_IDR_TXUD_POS 3U +# define I2C_IDR_TXUD_MSK BIT(I2C_IDR_TXUD_POS) + +# define I2C_IDR_TXOV_POS 2U +# define I2C_IDR_TXOV_MSK BIT(I2C_IDR_TXOV_POS) + +# define I2C_IDR_TXE_POS 0U +# define I2C_IDR_TXE_MSK BIT(I2C_IDR_TXE_POS) +/****************** Bit definition for I2C_IVS register ************************/ + +# define I2C_IVS_ALERT_POS 20U +# define I2C_IVS_ALERT_MSK BIT(I2C_IVS_ALERT_POS) + +# define I2C_IVS_TOUT_POS 19U +# define I2C_IVS_TOUT_MSK BIT(I2C_IVS_TOUT_POS) + +# define I2C_IVS_PECE_POS 18U +# define I2C_IVS_PECE_MSK BIT(I2C_IVS_PECE_POS) + +# define I2C_IVS_ARLO_POS 17U +# define I2C_IVS_ARLO_MSK BIT(I2C_IVS_ARLO_POS) + +# define I2C_IVS_BERR_POS 16U +# define I2C_IVS_BERR_MSK BIT(I2C_IVS_BERR_POS) + +# define I2C_IVS_STOP_POS 14U +# define I2C_IVS_STOP_MSK BIT(I2C_IVS_STOP_POS) + +# define I2C_IVS_NACK_POS 13U +# define I2C_IVS_NACK_MSK BIT(I2C_IVS_NACK_POS) + +# define I2C_IVS_ADDR_POS 12U +# define I2C_IVS_ADDR_MSK BIT(I2C_IVS_ADDR_POS) + +# define I2C_IVS_TCR_POS 11U +# define I2C_IVS_TCR_MSK BIT(I2C_IVS_TCR_POS) + +# define I2C_IVS_TC_POS 10U +# define I2C_IVS_TC_MSK BIT(I2C_IVS_TC_POS) + +# define I2C_IVS_RXUD_POS 8U +# define I2C_IVS_RXUD_MSK BIT(I2C_IVS_RXUD_POS) + +# define I2C_IVS_RXOV_POS 7U +# define I2C_IVS_RXOV_MSK BIT(I2C_IVS_RXOV_POS) + +# define I2C_IVS_RXNE_POS 5U +# define I2C_IVS_RXNE_MSK BIT(I2C_IVS_RXNE_POS) + +# define I2C_IVS_TXUD_POS 3U +# define I2C_IVS_TXUD_MSK BIT(I2C_IVS_TXUD_POS) + +# define I2C_IVS_TXOV_POS 2U +# define I2C_IVS_TXOV_MSK BIT(I2C_IVS_TXOV_POS) + +# define I2C_IVS_TXE_POS 0U +# define I2C_IVS_TXE_MSK BIT(I2C_IVS_TXE_POS) + +/****************** Bit definition for I2C_RIF register ************************/ + +# define I2C_RIF_ALERT_POS 20U +# define I2C_RIF_ALERT_MSK BIT(I2C_RIF_ALERT_POS) + +# define I2C_RIF_TOUT_POS 19U +# define I2C_RIF_TOUT_MSK BIT(I2C_RIF_TOUT_POS) + +# define I2C_RIF_PECE_POS 18U +# define I2C_RIF_PECE_MSK BIT(I2C_RIF_PECE_POS) + +# define I2C_RIF_ARLO_POS 17U +# define I2C_RIF_ARLO_MSK BIT(I2C_RIF_ARLO_POS) + +# define I2C_RIF_BERR_POS 16U +# define I2C_RIF_BERR_MSK BIT(I2C_RIF_BERR_POS) + +# define I2C_RIF_STOP_POS 14U +# define I2C_RIF_STOP_MSK BIT(I2C_RIF_STOP_POS) + +# define I2C_RIF_NACK_POS 13U +# define I2C_RIF_NACK_MSK BIT(I2C_RIF_NACK_POS) + +# define I2C_RIF_ADDR_POS 12U +# define I2C_RIF_ADDR_MSK BIT(I2C_RIF_ADDR_POS) + +# define I2C_RIF_TCR_POS 11U +# define I2C_RIF_TCR_MSK BIT(I2C_RIF_TCR_POS) + +# define I2C_RIF_TC_POS 10U +# define I2C_RIF_TC_MSK BIT(I2C_RIF_TC_POS) + +# define I2C_RIF_RXUD_POS 8U +# define I2C_RIF_RXUD_MSK BIT(I2C_RIF_RXUD_POS) + +# define I2C_RIF_RXOV_POS 7U +# define I2C_RIF_RXOV_MSK BIT(I2C_RIF_RXOV_POS) + +# define I2C_RIF_RXNE_POS 5U +# define I2C_RIF_RXNE_MSK BIT(I2C_RIF_RXNE_POS) + +# define I2C_RIF_TXUD_POS 3U +# define I2C_RIF_TXUD_MSK BIT(I2C_RIF_TXUD_POS) + +# define I2C_RIF_TXOV_POS 2U +# define I2C_RIF_TXOV_MSK BIT(I2C_RIF_TXOV_POS) + +# define I2C_RIF_TXE_POS 0U +# define I2C_RIF_TXE_MSK BIT(I2C_RIF_TXE_POS) + +/****************** Bit definition for I2C_IFM register ************************/ + +# define I2C_IFM_ALERT_POS 20U +# define I2C_IFM_ALERT_MSK BIT(I2C_IFM_ALERT_POS) + +# define I2C_IFM_TOUT_POS 19U +# define I2C_IFM_TOUT_MSK BIT(I2C_IFM_TOUT_POS) + +# define I2C_IFM_PECE_POS 18U +# define I2C_IFM_PECE_MSK BIT(I2C_IFM_PECE_POS) + +# define I2C_IFM_ARLO_POS 17U +# define I2C_IFM_ARLO_MSK BIT(I2C_IFM_ARLO_POS) + +# define I2C_IFM_BERR_POS 16U +# define I2C_IFM_BERR_MSK BIT(I2C_IFM_BERR_POS) + +# define I2C_IFM_STOP_POS 14U +# define I2C_IFM_STOP_MSK BIT(I2C_IFM_STOP_POS) + +# define I2C_IFM_NACK_POS 13U +# define I2C_IFM_NACK_MSK BIT(I2C_IFM_NACK_POS) + +# define I2C_IFM_ADDR_POS 12U +# define I2C_IFM_ADDR_MSK BIT(I2C_IFM_ADDR_POS) + +# define I2C_IFM_TCR_POS 11U +# define I2C_IFM_TCR_MSK BIT(I2C_IFM_TCR_POS) + +# define I2C_IFM_TC_POS 10U +# define I2C_IFM_TC_MSK BIT(I2C_IFM_TC_POS) + +# define I2C_IFM_RXUD_POS 8U +# define I2C_IFM_RXUD_MSK BIT(I2C_IFM_RXUD_POS) + +# define I2C_IFM_RXOV_POS 7U +# define I2C_IFM_RXOV_MSK BIT(I2C_IFM_RXOV_POS) + +# define I2C_IFM_RXNE_POS 5U +# define I2C_IFM_RXNE_MSK BIT(I2C_IFM_RXNE_POS) + +# define I2C_IFM_TXUD_POS 3U +# define I2C_IFM_TXUD_MSK BIT(I2C_IFM_TXUD_POS) + +# define I2C_IFM_TXOV_POS 2U +# define I2C_IFM_TXOV_MSK BIT(I2C_IFM_TXOV_POS) + +# define I2C_IFM_TXE_POS 0U +# define I2C_IFM_TXE_MSK BIT(I2C_IFM_TXE_POS) + +/****************** Bit definition for I2C_ICR register ************************/ + +# define I2C_ICR_ALERT_POS 20U +# define I2C_ICR_ALERT_MSK BIT(I2C_ICR_ALERT_POS) + +# define I2C_ICR_TOUT_POS 19U +# define I2C_ICR_TOUT_MSK BIT(I2C_ICR_TOUT_POS) + +# define I2C_ICR_PECE_POS 18U +# define I2C_ICR_PECE_MSK BIT(I2C_ICR_PECE_POS) + +# define I2C_ICR_ARLO_POS 17U +# define I2C_ICR_ARLO_MSK BIT(I2C_ICR_ARLO_POS) + +# define I2C_ICR_BERR_POS 16U +# define I2C_ICR_BERR_MSK BIT(I2C_ICR_BERR_POS) + +# define I2C_ICR_STOP_POS 14U +# define I2C_ICR_STOP_MSK BIT(I2C_ICR_STOP_POS) + +# define I2C_ICR_NACK_POS 13U +# define I2C_ICR_NACK_MSK BIT(I2C_ICR_NACK_POS) + +# define I2C_ICR_ADDR_POS 12U +# define I2C_ICR_ADDR_MSK BIT(I2C_ICR_ADDR_POS) + +# define I2C_ICR_TCR_POS 11U +# define I2C_ICR_TCR_MSK BIT(I2C_ICR_TCR_POS) + +# define I2C_ICR_TC_POS 10U +# define I2C_ICR_TC_MSK BIT(I2C_ICR_TC_POS) + +# define I2C_ICR_RXUD_POS 8U +# define I2C_ICR_RXUD_MSK BIT(I2C_ICR_RXUD_POS) + +# define I2C_ICR_RXOV_POS 7U +# define I2C_ICR_RXOV_MSK BIT(I2C_ICR_RXOV_POS) + +# define I2C_ICR_RXNE_POS 5U +# define I2C_ICR_RXNE_MSK BIT(I2C_ICR_RXNE_POS) + +# define I2C_ICR_TXUD_POS 3U +# define I2C_ICR_TXUD_MSK BIT(I2C_ICR_TXUD_POS) + +# define I2C_ICR_TXOV_POS 2U +# define I2C_ICR_TXOV_MSK BIT(I2C_ICR_TXOV_POS) + +# define I2C_ICR_TXE_POS 0U +# define I2C_ICR_TXE_MSK BIT(I2C_ICR_TXE_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __I uint32_t STAT; + __IO uint32_t RESERVED0; + __IO uint32_t PECR; + __I uint32_t RXDATA; + __O uint32_t TXDATA; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} I2C_TypeDef; + + + + + +#endif /* __REG_I2C_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_iwdt.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_iwdt.h new file mode 100644 index 0000000000..ee2239654d --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_iwdt.h @@ -0,0 +1,94 @@ +/********************************************************************************** + * + * @file reg_iwdt.h + * @brief IWDT Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_IWDT_H__ +#define __REG_IWDT_H__ + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + + + + + +#endif /* __REG_IWDT_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_msc.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_msc.h new file mode 100644 index 0000000000..94e313b386 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_msc.h @@ -0,0 +1,176 @@ +/********************************************************************************** + * + * @file reg_msc.h + * @brief MSC Head File + * + * @date 27 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 27 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_MSC_H__ +#define __REG_MSC_H__ + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 18U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 17U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDR register ************************/ + +#define MSC_FLASHDR_DATA_POSS 0U +#define MSC_FLASHDR_DATA_POSE 31U +#define MSC_FLASHDR_DATA_MSK BITS(MSC_FLASHDR_DATA_POSS,MSC_FLASHDR_DATA_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_PGSZ_POS 8U +#define MSC_FLASHCR_PGSZ_MSK BIT(MSC_FLASHCR_PGSZ_POS) + +#define MSC_FLASHCR_FIFODF_POS 7U +#define MSC_FLASHCR_FIFODF_MSK BIT(MSC_FLASHCR_FIFODF_POS) + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_OTFEN_POS 2U +#define MSC_FLASHCR_OTFEN_MSK BIT(MSC_FLASHCR_OTFEN_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_UPCEUL_POS 25U +#define MSC_FLASHSR_UPCEUL_MSK BIT(MSC_FLASHSR_UPCEUL_POS) + +#define MSC_FLASHSR_MASEUL_POS 24U +#define MSC_FLASHSR_MASEUL_MSK BIT(MSC_FLASHSR_MASEUL_POS) + +#define MSC_FLASHSR_ADDERR_POS 23U +#define MSC_FLASHSR_ADDERR_MSK BIT(MSC_FLASHSR_ADDERR_POS) + +#define MSC_FLASHSR_UPCEDONE_POS 17U +#define MSC_FLASHSR_UPCEDONE_MSK BIT(MSC_FLASHSR_UPCEDONE_POS) + +#define MSC_FLASHSR_UPCEBUSY_POS 16U +#define MSC_FLASHSR_UPCEBUSY_MSK BIT(MSC_FLASHSR_UPCEBUSY_POS) + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_WAE_POS 3U +#define MSC_FLASHSR_WAE_MSK BIT(MSC_FLASHSR_WAE_POS) + +#define MSC_FLASHSR_WPE_POS 2U +#define MSC_FLASHSR_WPE_MSK BIT(MSC_FLASHSR_WPE_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 1U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +/****************** Bit definition for MSC_FLASHADDINV register ************************/ + +#define MSC_FLASHADDINV_ADDRINV_POSS 0U +#define MSC_FLASHADDINV_ADDRINV_POSE 17U +#define MSC_FLASHADDINV_ADDRINV_MSK BITS(MSC_FLASHADDINV_ADDRINV_POSS,MSC_FLASHADDINV_ADDRINV_POSE) + +typedef struct +{ + __IO uint32_t FLASHKEY; + __I uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDR; + uint32_t RESERVED0 ; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + uint32_t RESERVED1 ; + __IO uint32_t MEMWAIT; + __IO uint32_t FLASHADDINV; +} MSC_TypeDef; + + + + + +#endif /* __REG_MSC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pis.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pis.h new file mode 100644 index 0000000000..32a43e160f --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pis.h @@ -0,0 +1,465 @@ +/********************************************************************************** + * + * @file reg_pis.h + * @brief PIS Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_PIS_H__ +#define __REG_PIS_H__ + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_LEVEL_POS 31U +#define PIS_CH0_CON_LEVEL_MSK BIT(PIS_CH0_CON_LEVEL_POS) + +#define PIS_CH0_CON_PULSE_POS 30U +#define PIS_CH0_CON_PULSE_MSK BIT(PIS_CH0_CON_PULSE_POS) + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_TSCKS_POSS 18U +#define PIS_CH0_CON_TSCKS_POSE 19U +#define PIS_CH0_CON_TSCKS_MSK BITS(PIS_CH0_CON_TSCKS_POSS,PIS_CH0_CON_TSCKS_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH1_CON register ************************/ + +#define PIS_CH1_CON_LEVEL_POS 31U +#define PIS_CH1_CON_LEVEL_MSK BIT(PIS_CH1_CON_LEVEL_POS) + +#define PIS_CH1_CON_PULSE_POS 30U +#define PIS_CH1_CON_PULSE_MSK BIT(PIS_CH1_CON_PULSE_POS) + +#define PIS_CH1_CON_SYNCSEL_POSS 24U +#define PIS_CH1_CON_SYNCSEL_POSE 26U +#define PIS_CH1_CON_SYNCSEL_MSK BITS(PIS_CH1_CON_SYNCSEL_POSS,PIS_CH1_CON_SYNCSEL_POSE) + +#define PIS_CH1_CON_TSCKS_POSS 18U +#define PIS_CH1_CON_TSCKS_POSE 19U +#define PIS_CH1_CON_TSCKS_MSK BITS(PIS_CH1_CON_TSCKS_POSS,PIS_CH1_CON_TSCKS_POSE) + +#define PIS_CH1_CON_EDGS_POSS 16U +#define PIS_CH1_CON_EDGS_POSE 17U +#define PIS_CH1_CON_EDGS_MSK BITS(PIS_CH1_CON_EDGS_POSS,PIS_CH1_CON_EDGS_POSE) + +#define PIS_CH1_CON_SRCS_POSS 8U +#define PIS_CH1_CON_SRCS_POSE 13U +#define PIS_CH1_CON_SRCS_MSK BITS(PIS_CH1_CON_SRCS_POSS,PIS_CH1_CON_SRCS_POSE) + +#define PIS_CH1_CON_MSIGS_POSS 0U +#define PIS_CH1_CON_MSIGS_POSE 3U +#define PIS_CH1_CON_MSIGS_MSK BITS(PIS_CH1_CON_MSIGS_POSS,PIS_CH1_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH2_CON register ************************/ + +#define PIS_CH2_CON_LEVEL_POS 31U +#define PIS_CH2_CON_LEVEL_MSK BIT(PIS_CH2_CON_LEVEL_POS) + +#define PIS_CH2_CON_PULSE_POS 30U +#define PIS_CH2_CON_PULSE_MSK BIT(PIS_CH2_CON_PULSE_POS) + +#define PIS_CH2_CON_SYNCSEL_POSS 24U +#define PIS_CH2_CON_SYNCSEL_POSE 26U +#define PIS_CH2_CON_SYNCSEL_MSK BITS(PIS_CH2_CON_SYNCSEL_POSS,PIS_CH2_CON_SYNCSEL_POSE) + +#define PIS_CH2_CON_TSCKS_POSS 18U +#define PIS_CH2_CON_TSCKS_POSE 19U +#define PIS_CH2_CON_TSCKS_MSK BITS(PIS_CH2_CON_TSCKS_POSS,PIS_CH2_CON_TSCKS_POSE) + +#define PIS_CH2_CON_EDGS_POSS 16U +#define PIS_CH2_CON_EDGS_POSE 17U +#define PIS_CH2_CON_EDGS_MSK BITS(PIS_CH2_CON_EDGS_POSS,PIS_CH2_CON_EDGS_POSE) + +#define PIS_CH2_CON_SRCS_POSS 8U +#define PIS_CH2_CON_SRCS_POSE 13U +#define PIS_CH2_CON_SRCS_MSK BITS(PIS_CH2_CON_SRCS_POSS,PIS_CH2_CON_SRCS_POSE) + +#define PIS_CH2_CON_MSIGS_POSS 0U +#define PIS_CH2_CON_MSIGS_POSE 3U +#define PIS_CH2_CON_MSIGS_MSK BITS(PIS_CH2_CON_MSIGS_POSS,PIS_CH2_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH3_CON register ************************/ + +#define PIS_CH3_CON_LEVEL_POS 31U +#define PIS_CH3_CON_LEVEL_MSK BIT(PIS_CH3_CON_LEVEL_POS) + +#define PIS_CH3_CON_PULSE_POS 30U +#define PIS_CH3_CON_PULSE_MSK BIT(PIS_CH3_CON_PULSE_POS) + +#define PIS_CH3_CON_SYNCSEL_POSS 24U +#define PIS_CH3_CON_SYNCSEL_POSE 26U +#define PIS_CH3_CON_SYNCSEL_MSK BITS(PIS_CH3_CON_SYNCSEL_POSS,PIS_CH3_CON_SYNCSEL_POSE) + +#define PIS_CH3_CON_TSCKS_POSS 18U +#define PIS_CH3_CON_TSCKS_POSE 19U +#define PIS_CH3_CON_TSCKS_MSK BITS(PIS_CH3_CON_TSCKS_POSS,PIS_CH3_CON_TSCKS_POSE) + +#define PIS_CH3_CON_EDGS_POSS 16U +#define PIS_CH3_CON_EDGS_POSE 17U +#define PIS_CH3_CON_EDGS_MSK BITS(PIS_CH3_CON_EDGS_POSS,PIS_CH3_CON_EDGS_POSE) + +#define PIS_CH3_CON_SRCS_POSS 8U +#define PIS_CH3_CON_SRCS_POSE 13U +#define PIS_CH3_CON_SRCS_MSK BITS(PIS_CH3_CON_SRCS_POSS,PIS_CH3_CON_SRCS_POSE) + +#define PIS_CH3_CON_MSIGS_POSS 0U +#define PIS_CH3_CON_MSIGS_POSE 3U +#define PIS_CH3_CON_MSIGS_MSK BITS(PIS_CH3_CON_MSIGS_POSS,PIS_CH3_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH4_CON register ************************/ + +#define PIS_CH4_CON_LEVEL_POS 31U +#define PIS_CH4_CON_LEVEL_MSK BIT(PIS_CH4_CON_LEVEL_POS) + +#define PIS_CH4_CON_PULSE_POS 30U +#define PIS_CH4_CON_PULSE_MSK BIT(PIS_CH4_CON_PULSE_POS) + +#define PIS_CH4_CON_SYNCSEL_POSS 24U +#define PIS_CH4_CON_SYNCSEL_POSE 26U +#define PIS_CH4_CON_SYNCSEL_MSK BITS(PIS_CH4_CON_SYNCSEL_POSS,PIS_CH4_CON_SYNCSEL_POSE) + +#define PIS_CH4_CON_TSCKS_POSS 18U +#define PIS_CH4_CON_TSCKS_POSE 19U +#define PIS_CH4_CON_TSCKS_MSK BITS(PIS_CH4_CON_TSCKS_POSS,PIS_CH4_CON_TSCKS_POSE) + +#define PIS_CH4_CON_EDGS_POSS 16U +#define PIS_CH4_CON_EDGS_POSE 17U +#define PIS_CH4_CON_EDGS_MSK BITS(PIS_CH4_CON_EDGS_POSS,PIS_CH4_CON_EDGS_POSE) + +#define PIS_CH4_CON_SRCS_POSS 8U +#define PIS_CH4_CON_SRCS_POSE 13U +#define PIS_CH4_CON_SRCS_MSK BITS(PIS_CH4_CON_SRCS_POSS,PIS_CH4_CON_SRCS_POSE) + +#define PIS_CH4_CON_MSIGS_POSS 0U +#define PIS_CH4_CON_MSIGS_POSE 3U +#define PIS_CH4_CON_MSIGS_MSK BITS(PIS_CH4_CON_MSIGS_POSS,PIS_CH4_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH5_CON register ************************/ + +#define PIS_CH5_CON_LEVEL_POS 31U +#define PIS_CH5_CON_LEVEL_MSK BIT(PIS_CH5_CON_LEVEL_POS) + +#define PIS_CH5_CON_PULSE_POS 30U +#define PIS_CH5_CON_PULSE_MSK BIT(PIS_CH5_CON_PULSE_POS) + +#define PIS_CH5_CON_SYNCSEL_POSS 24U +#define PIS_CH5_CON_SYNCSEL_POSE 26U +#define PIS_CH5_CON_SYNCSEL_MSK BITS(PIS_CH5_CON_SYNCSEL_POSS,PIS_CH5_CON_SYNCSEL_POSE) + +#define PIS_CH5_CON_TSCKS_POSS 18U +#define PIS_CH5_CON_TSCKS_POSE 19U +#define PIS_CH5_CON_TSCKS_MSK BITS(PIS_CH5_CON_TSCKS_POSS,PIS_CH5_CON_TSCKS_POSE) + +#define PIS_CH5_CON_EDGS_POSS 16U +#define PIS_CH5_CON_EDGS_POSE 17U +#define PIS_CH5_CON_EDGS_MSK BITS(PIS_CH5_CON_EDGS_POSS,PIS_CH5_CON_EDGS_POSE) + +#define PIS_CH5_CON_SRCS_POSS 8U +#define PIS_CH5_CON_SRCS_POSE 13U +#define PIS_CH5_CON_SRCS_MSK BITS(PIS_CH5_CON_SRCS_POSS,PIS_CH5_CON_SRCS_POSE) + +#define PIS_CH5_CON_MSIGS_POSS 0U +#define PIS_CH5_CON_MSIGS_POSE 3U +#define PIS_CH5_CON_MSIGS_MSK BITS(PIS_CH5_CON_MSIGS_POSS,PIS_CH5_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH6_CON register ************************/ + +#define PIS_CH6_CON_LEVEL_POS 31U +#define PIS_CH6_CON_LEVEL_MSK BIT(PIS_CH6_CON_LEVEL_POS) + +#define PIS_CH6_CON_PULSE_POS 30U +#define PIS_CH6_CON_PULSE_MSK BIT(PIS_CH6_CON_PULSE_POS) + +#define PIS_CH6_CON_SYNCSEL_POSS 24U +#define PIS_CH6_CON_SYNCSEL_POSE 26U +#define PIS_CH6_CON_SYNCSEL_MSK BITS(PIS_CH6_CON_SYNCSEL_POSS,PIS_CH6_CON_SYNCSEL_POSE) + +#define PIS_CH6_CON_TSCKS_POSS 18U +#define PIS_CH6_CON_TSCKS_POSE 19U +#define PIS_CH6_CON_TSCKS_MSK BITS(PIS_CH6_CON_TSCKS_POSS,PIS_CH6_CON_TSCKS_POSE) + +#define PIS_CH6_CON_EDGS_POSS 16U +#define PIS_CH6_CON_EDGS_POSE 17U +#define PIS_CH6_CON_EDGS_MSK BITS(PIS_CH6_CON_EDGS_POSS,PIS_CH6_CON_EDGS_POSE) + +#define PIS_CH6_CON_SRCS_POSS 8U +#define PIS_CH6_CON_SRCS_POSE 13U +#define PIS_CH6_CON_SRCS_MSK BITS(PIS_CH6_CON_SRCS_POSS,PIS_CH6_CON_SRCS_POSE) + +#define PIS_CH6_CON_MSIGS_POSS 0U +#define PIS_CH6_CON_MSIGS_POSE 3U +#define PIS_CH6_CON_MSIGS_MSK BITS(PIS_CH6_CON_MSIGS_POSS,PIS_CH6_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH7_CON register ************************/ + +#define PIS_CH7_CON_LEVEL_POS 31U +#define PIS_CH7_CON_LEVEL_MSK BIT(PIS_CH7_CON_LEVEL_POS) + +#define PIS_CH7_CON_PULSE_POS 30U +#define PIS_CH7_CON_PULSE_MSK BIT(PIS_CH7_CON_PULSE_POS) + +#define PIS_CH7_CON_SYNCSEL_POSS 24U +#define PIS_CH7_CON_SYNCSEL_POSE 26U +#define PIS_CH7_CON_SYNCSEL_MSK BITS(PIS_CH7_CON_SYNCSEL_POSS,PIS_CH7_CON_SYNCSEL_POSE) + +#define PIS_CH7_CON_TSCKS_POSS 18U +#define PIS_CH7_CON_TSCKS_POSE 19U +#define PIS_CH7_CON_TSCKS_MSK BITS(PIS_CH7_CON_TSCKS_POSS,PIS_CH7_CON_TSCKS_POSE) + +#define PIS_CH7_CON_EDGS_POSS 16U +#define PIS_CH7_CON_EDGS_POSE 17U +#define PIS_CH7_CON_EDGS_MSK BITS(PIS_CH7_CON_EDGS_POSS,PIS_CH7_CON_EDGS_POSE) + +#define PIS_CH7_CON_SRCS_POSS 8U +#define PIS_CH7_CON_SRCS_POSE 13U +#define PIS_CH7_CON_SRCS_MSK BITS(PIS_CH7_CON_SRCS_POSS,PIS_CH7_CON_SRCS_POSE) + +#define PIS_CH7_CON_MSIGS_POSS 0U +#define PIS_CH7_CON_MSIGS_POSE 3U +#define PIS_CH7_CON_MSIGS_MSK BITS(PIS_CH7_CON_MSIGS_POSS,PIS_CH7_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH7OE_POS 7U +#define PIS_CH_OER_CH7OE_MSK BIT(PIS_CH_OER_CH7OE_POS) + +#define PIS_CH_OER_CH6OE_POS 6U +#define PIS_CH_OER_CH6OE_MSK BIT(PIS_CH_OER_CH6OE_POS) + +#define PIS_CH_OER_CH5OE_POS 5U +#define PIS_CH_OER_CH5OE_MSK BIT(PIS_CH_OER_CH5OE_POS) + +#define PIS_CH_OER_CH4OE_POS 4U +#define PIS_CH_OER_CH4OE_MSK BIT(PIS_CH_OER_CH4OE_POS) + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_ETRIN_SEL_POS 28U +#define PIS_TAR_CON0_TIM3_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_POS 27U +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_POS 26U +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_ETRIN_SEL_POS 20U +#define PIS_TAR_CON0_TIM2_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_POS 19U +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_POS 18U +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_ETRIN_SEL_POS 12U +#define PIS_TAR_CON0_TIM1_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_POS 11U +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_POS 10U +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_POS 9U +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_POS 8U +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_ETRIN_SEL_POS 5U +#define PIS_TAR_CON0_TIM0_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_UART4_RXD_SEL_POS 4U +#define PIS_TAR_CON1_UART4_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART4_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_UART0_TXMCR register ************************/ + +#define PIS_UART0_TXMCR_TXMLVLS_POS 8U +#define PIS_UART0_TXMCR_TXMLVLS_MSK BIT(PIS_UART0_TXMCR_TXMLVLS_POS) + +#define PIS_UART0_TXMCR_TXMSS_POSS 4U +#define PIS_UART0_TXMCR_TXMSS_POSE 7U +#define PIS_UART0_TXMCR_TXMSS_MSK BITS(PIS_UART0_TXMCR_TXMSS_POSS,PIS_UART0_TXMCR_TXMSS_POSE) + +#define PIS_UART0_TXMCR_TXSIGS_POSS 0U +#define PIS_UART0_TXMCR_TXSIGS_POSE 3U +#define PIS_UART0_TXMCR_TXSIGS_MSK BITS(PIS_UART0_TXMCR_TXSIGS_POSS,PIS_UART0_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART1_TXMCR register ************************/ + +#define PIS_UART1_TXMCR_TXMLVLS_POS 8U +#define PIS_UART1_TXMCR_TXMLVLS_MSK BIT(PIS_UART1_TXMCR_TXMLVLS_POS) + +#define PIS_UART1_TXMCR_TXMSS_POSS 4U +#define PIS_UART1_TXMCR_TXMSS_POSE 7U +#define PIS_UART1_TXMCR_TXMSS_MSK BITS(PIS_UART1_TXMCR_TXMSS_POSS,PIS_UART1_TXMCR_TXMSS_POSE) + +#define PIS_UART1_TXMCR_TXSIGS_POSS 0U +#define PIS_UART1_TXMCR_TXSIGS_POSE 3U +#define PIS_UART1_TXMCR_TXSIGS_MSK BITS(PIS_UART1_TXMCR_TXSIGS_POSS,PIS_UART1_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART2_TXMCR register ************************/ + +#define PIS_UART2_TXMCR_TXMLVLS_POS 8U +#define PIS_UART2_TXMCR_TXMLVLS_MSK BIT(PIS_UART2_TXMCR_TXMLVLS_POS) + +#define PIS_UART2_TXMCR_TXMSS_POSS 4U +#define PIS_UART2_TXMCR_TXMSS_POSE 7U +#define PIS_UART2_TXMCR_TXMSS_MSK BITS(PIS_UART2_TXMCR_TXMSS_POSS,PIS_UART2_TXMCR_TXMSS_POSE) + +#define PIS_UART2_TXMCR_TXSIGS_POSS 0U +#define PIS_UART2_TXMCR_TXSIGS_POSE 3U +#define PIS_UART2_TXMCR_TXSIGS_MSK BITS(PIS_UART2_TXMCR_TXSIGS_POSS,PIS_UART2_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART3_TXMCR register ************************/ + +#define PIS_UART3_TXMCR_TXMLVLS_POS 8U +#define PIS_UART3_TXMCR_TXMLVLS_MSK BIT(PIS_UART3_TXMCR_TXMLVLS_POS) + +#define PIS_UART3_TXMCR_TXMSS_POSS 4U +#define PIS_UART3_TXMCR_TXMSS_POSE 7U +#define PIS_UART3_TXMCR_TXMSS_MSK BITS(PIS_UART3_TXMCR_TXMSS_POSS,PIS_UART3_TXMCR_TXMSS_POSE) + +#define PIS_UART3_TXMCR_TXSIGS_POSS 0U +#define PIS_UART3_TXMCR_TXSIGS_POSE 3U +#define PIS_UART3_TXMCR_TXSIGS_MSK BITS(PIS_UART3_TXMCR_TXSIGS_POSS,PIS_UART3_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART4_TXMCR register ************************/ + +#define PIS_UART4_TXMCR_TXMLVLS_POS 8U +#define PIS_UART4_TXMCR_TXMLVLS_MSK BIT(PIS_UART4_TXMCR_TXMLVLS_POS) + +#define PIS_UART4_TXMCR_TXMSS_POSS 4U +#define PIS_UART4_TXMCR_TXMSS_POSE 7U +#define PIS_UART4_TXMCR_TXMSS_MSK BITS(PIS_UART4_TXMCR_TXMSS_POSS,PIS_UART4_TXMCR_TXMSS_POSE) + +#define PIS_UART4_TXMCR_TXSIGS_POSS 0U +#define PIS_UART4_TXMCR_TXSIGS_POSE 3U +#define PIS_UART4_TXMCR_TXSIGS_MSK BITS(PIS_UART4_TXMCR_TXSIGS_POSS,PIS_UART4_TXMCR_TXSIGS_POSE) + +typedef struct +{ + __IO uint32_t CH_CON[8]; + uint32_t RESERVED0[8] ; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED1[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t UART4_TXMCR; +} PIS_TypeDef; + + + + + +#endif /* __REG_PIS_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pmu.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pmu.h new file mode 100644 index 0000000000..cba0ba1d15 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_pmu.h @@ -0,0 +1,127 @@ +/********************************************************************************** + * + * @file reg_pmu.h + * @brief PMU Head File + * + * @date 15 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_PMU_H__ +#define __REG_PMU_H__ + +/****************** Bit definition for PMU_CR register ************************/ + +#define PMU_CR_WKEVNSEL_POSS 24U +#define PMU_CR_WKEVNSEL_POSE 28U +#define PMU_CR_WKEVNSEL_MSK BITS(PMU_CR_WKEVNSEL_POSS,PMU_CR_WKEVNSEL_POSE) + +#define PMU_CR_FSTOP_POS 23U +#define PMU_CR_FSTOP_MSK BIT(PMU_CR_FSTOP_POS) + +#define PMU_CR_BGSTOP_POS 21U +#define PMU_CR_BGSTOP_MSK BIT(PMU_CR_BGSTOP_POS) + +#define PMU_CR_LPSTOP_POS 20U +#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) + +#define PMU_CR_LPRUN_POS 19U +#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) + +#define PMU_CR_LPVS_POSS 16U +#define PMU_CR_LPVS_POSE 17U +#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) + +#define PMU_CR_VROSCEN_POS 7U +#define PMU_CR_VROSCEN_MSK BIT(PMU_CR_VROSCEN_POS) + +#define PMU_CR_NORRTNEN_POS 6U +#define PMU_CR_NORRTNEN_MSK BIT(PMU_CR_NORRTNEN_POS) + +#define PMU_CR_STPRTNEN_POS 5U +#define PMU_CR_STPRTNEN_MSK BIT(PMU_CR_STPRTNEN_POS) + +#define PMU_CR_CWUF_POS 2U +#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) + +#define PMU_CR_LPM_POSS 0U +#define PMU_CR_LPM_POSE 1U +#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVDIFS_POSS 8U +#define PMU_LVDCR_LVDIFS_POSE 10U +#define PMU_LVDCR_LVDIFS_MSK BITS(PMU_LVDCR_LVDIFS_POSS,PMU_LVDCR_LVDIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_TWUR register ************************/ + +#define PMU_TWUR_TWU_POSS 0U +#define PMU_TWUR_TWU_POSE 11U +#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __IO uint32_t LVDCR; + uint32_t RESERVED0 ; + __IO uint32_t TWUR; +} PMU_TypeDef; + + + + + +#endif /* __REG_PMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_rmu.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_rmu.h new file mode 100644 index 0000000000..bd963c0ba0 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_rmu.h @@ -0,0 +1,220 @@ +/********************************************************************************** + * + * @file reg_rmu.h + * @brief RMU Head File + * + * @date 16 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_RMU_H__ +#define __REG_RMU_H__ + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 6U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ +#define RMU_AHB1RSTR_CSURST_POS 7U +#define RMU_AHB1RSTR_CSURST_MSK BIT(RMU_AHB1RSTR_CSURST_POS) + +#define RMU_AHB1RSTR_USBRST_POS 6U +#define RMU_AHB1RSTR_USBRST_MSK BIT(RMU_AHB1RSTR_USBRST_POS) + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_DMARST_POS 2U +#define RMU_AHB1RSTR_DMARST_MSK BIT(RMU_AHB1RSTR_DMARST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APBRSTR register ************************/ + +#define RMU_APBRSTR_ADCRST_POS 25U +#define RMU_APBRSTR_ADCRST_MSK BIT(RMU_APBRSTR_ADCRST_POS) + +#define RMU_APBRSTR_DBGCONRST_POS 24U +#define RMU_APBRSTR_DBGCONRST_MSK BIT(RMU_APBRSTR_DBGCONRST_POS) + +#define RMU_APBRSTR_IWDTRST_POS 23U +#define RMU_APBRSTR_IWDTRST_MSK BIT(RMU_APBRSTR_IWDTRST_POS) + +#define RMU_APBRSTR_WWDTRST_POS 22U +#define RMU_APBRSTR_WWDTRST_MSK BIT(RMU_APBRSTR_WWDTRST_POS) + +#define RMU_APBRSTR_I2C1RST_POS 21U +#define RMU_APBRSTR_I2C1RST_MSK BIT(RMU_APBRSTR_I2C1RST_POS) + +#define RMU_APBRSTR_I2C0RST_POS 20U +#define RMU_APBRSTR_I2C0RST_MSK BIT(RMU_APBRSTR_I2C0RST_POS) + +#define RMU_APBRSTR_SPI1RST_POS 17U +#define RMU_APBRSTR_SPI1RST_MSK BIT(RMU_APBRSTR_SPI1RST_POS) + +#define RMU_APBRSTR_SPI0RST_POS 16U +#define RMU_APBRSTR_SPI0RST_MSK BIT(RMU_APBRSTR_SPI0RST_POS) + +#define RMU_APBRSTR_CUART2RST_POS 14U +#define RMU_APBRSTR_CUART2RST_MSK BIT(RMU_APBRSTR_CUART2RST_POS) + +#define RMU_APBRSTR_CUART1RST_POS 13U +#define RMU_APBRSTR_CUART1RST_MSK BIT(RMU_APBRSTR_CUART1RST_POS) + +#define RMU_APBRSTR_CUART0RST_POS 12U +#define RMU_APBRSTR_CUART0RST_MSK BIT(RMU_APBRSTR_CUART0RST_POS) + +#define RMU_APBRSTR_EUART1RST_POS 9U +#define RMU_APBRSTR_EUART1RST_MSK BIT(RMU_APBRSTR_EUART1RST_POS) + +#define RMU_APBRSTR_EUART0RST_POS 8U +#define RMU_APBRSTR_EUART0RST_MSK BIT(RMU_APBRSTR_EUART0RST_POS) + +#define RMU_APBRSTR_GP16C4T2RST_POS 4U +#define RMU_APBRSTR_GP16C4T2RST_MSK BIT(RMU_APBRSTR_GP16C4T2RST_POS) + +#define RMU_APBRSTR_GP16C4T1RST_POS 3U +#define RMU_APBRSTR_GP16C4T1RST_MSK BIT(RMU_APBRSTR_GP16C4T1RST_POS) + +#define RMU_APBRSTR_GP16C4T0RST_POS 2U +#define RMU_APBRSTR_GP16C4T0RST_MSK BIT(RMU_APBRSTR_GP16C4T0RST_POS) + +#define RMU_APBRSTR_BS16T0RST_POS 1U +#define RMU_APBRSTR_BS16T0RST_MSK BIT(RMU_APBRSTR_BS16T0RST_POS) + +#define RMU_APBRSTR_AD16C4T0RST_POS 0U +#define RMU_APBRSTR_AD16C4T0RST_MSK BIT(RMU_APBRSTR_AD16C4T0RST_POS) + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __IO uint32_t AHB1RSTR; + __IO uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __IO uint32_t APBRSTR; +} RMU_TypeDef; + + + + + +#endif /* __REG_RMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_spi.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_spi.h new file mode 100644 index 0000000000..c5569b6a69 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_spi.h @@ -0,0 +1,472 @@ +/********************************************************************************** + * + * @file reg_spi.h + * @brief SPI Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_SPI_H__ +#define __REG_SPI_H__ + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_RXFTH_POSS 14U +#define SPI_CON2_RXFTH_POSE 15U +#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) + +#define SPI_CON2_TXFTH_POSS 12U +#define SPI_CON2_TXFTH_POSE 13U +#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) + +#define SPI_CON2_FRF_POS 4U +#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) + +#define SPI_CON2_NSSP_POS 3U +#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_RXFLV_POSS 24U +#define SPI_STAT_RXFLV_POSE 28U +#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) + +#define SPI_STAT_TXFLV_POSS 16U +#define SPI_STAT_TXFLV_POSE 20U +#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) + +#define SPI_STAT_BUSY_POS 15U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_CHSIDE_POS 14U +#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) + +#define SPI_STAT_RXTH_POS 12U +#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) + +#define SPI_STAT_RXUD_POS 11U +#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) + +#define SPI_STAT_RXOV_POS 10U +#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) + +#define SPI_STAT_RXF_POS 9U +#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) + +#define SPI_STAT_RXNE_POS 8U +#define SPI_STAT_RXNE_MSK BIT(SPI_STAT_RXNE_POS) + +#define SPI_STAT_TXTH_POS 4U +#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) + +#define SPI_STAT_TXUD_POS 3U +#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) + +#define SPI_STAT_TXOV_POS 2U +#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) + +#define SPI_STAT_TXF_POS 1U +#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) + +#define SPI_STAT_TXE_POS 0U +#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_DATA_POSS 0U +#define SPI_DATA_DATA_POSE 15U +#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_CRCPOLY_POSS 0U +#define SPI_CRCPOLY_CRCPOLY_POSE 15U +#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_RXCRC_POSS 0U +#define SPI_RXCRC_RXCRC_POSE 15U +#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_TXCRC_POSS 0U +#define SPI_TXCRC_TXCRC_POSE 15U +#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +#define SPI_I2SCFG_I2SMOD_POS 12U +#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) + +#define SPI_I2SCFG_I2SE_POS 11U +#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) + +#define SPI_I2SCFG_I2SCFG_POSS 8U +#define SPI_I2SCFG_I2SCFG_POSE 10U +#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) + +#define SPI_I2SCFG_PCMSYNC_POS 7U +#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) + +#define SPI_I2SCFG_I2SSTD_POSS 4U +#define SPI_I2SCFG_I2SSTD_POSE 5U +#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) + +#define SPI_I2SCFG_CKPOL_POS 3U +#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) + +#define SPI_I2SCFG_DATLEN_POSS 1U +#define SPI_I2SCFG_DATLEN_POSE 2U +#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) + +#define SPI_I2SCFG_CHLEN_POS 0U +#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) + +/****************** Bit definition for SPI_I2SPR register ************************/ + +#define SPI_I2SPR_EXTCKEN_POS 10U +#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) + +#define SPI_I2SPR_MCKOE_POS 9U +#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) + +#define SPI_I2SPR_ODD_POS 8U +#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) + +#define SPI_I2SPR_I2SDIV_POSS 0U +#define SPI_I2SPR_I2SDIV_POSE 7U +#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) + +/****************** Bit definition for SPI_IER register ************************/ + +#define SPI_IER_FRE_POS 18U +#define SPI_IER_FRE_MSK BIT(SPI_IER_FRE_POS) + +#define SPI_IER_MODF_POS 17U +#define SPI_IER_MODF_MSK BIT(SPI_IER_MODF_POS) + +#define SPI_IER_CRCERR_POS 16U +#define SPI_IER_CRCERR_MSK BIT(SPI_IER_CRCERR_POS) + +#define SPI_IER_RXTH_POS 12U +#define SPI_IER_RXTH_MSK BIT(SPI_IER_RXTH_POS) + +#define SPI_IER_RXUD_POS 11U +#define SPI_IER_RXUD_MSK BIT(SPI_IER_RXUD_POS) + +#define SPI_IER_RXOV_POS 10U +#define SPI_IER_RXOV_MSK BIT(SPI_IER_RXOV_POS) + +#define SPI_IER_RXF_POS 9U +#define SPI_IER_RXF_MSK BIT(SPI_IER_RXF_POS) + +#define SPI_IER_RXNE_POS 8U +#define SPI_IER_RXNE_MSK BIT(SPI_IER_RXNE_POS) + +#define SPI_IER_TXTH_POS 4U +#define SPI_IER_TXTH_MSK BIT(SPI_IER_TXTH_POS) + +#define SPI_IER_TXUD_POS 3U +#define SPI_IER_TXUD_MSK BIT(SPI_IER_TXUD_POS) + +#define SPI_IER_TXOV_POS 2U +#define SPI_IER_TXOV_MSK BIT(SPI_IER_TXOV_POS) + +#define SPI_IER_TXE_POS 0U +#define SPI_IER_TXE_MSK BIT(SPI_IER_TXE_POS) + +/****************** Bit definition for SPI_IDR register ************************/ + +#define SPI_IDR_FRE_POS 18U +#define SPI_IDR_FRE_MSK BIT(SPI_IDR_FRE_POS) + +#define SPI_IDR_MODF_POS 17U +#define SPI_IDR_MODF_MSK BIT(SPI_IDR_MODF_POS) + +#define SPI_IDR_CRCERR_POS 16U +#define SPI_IDR_CRCERR_MSK BIT(SPI_IDR_CRCERR_POS) + +#define SPI_IDR_RXTH_POS 12U +#define SPI_IDR_RXTH_MSK BIT(SPI_IDR_RXTH_POS) + +#define SPI_IDR_RXUD_POS 11U +#define SPI_IDR_RXUD_MSK BIT(SPI_IDR_RXUD_POS) + +#define SPI_IDR_RXOV_POS 10U +#define SPI_IDR_RXOV_MSK BIT(SPI_IDR_RXOV_POS) + +#define SPI_IDR_RXF_POS 9U +#define SPI_IDR_RXF_MSK BIT(SPI_IDR_RXF_POS) + +#define SPI_IDR_RXNE_POS 8U +#define SPI_IDR_RXNE_MSK BIT(SPI_IDR_RXNE_POS) + +#define SPI_IDR_TXTH_POS 4U +#define SPI_IDR_TXTH_MSK BIT(SPI_IDR_TXTH_POS) + +#define SPI_IDR_TXUD_POS 3U +#define SPI_IDR_TXUD_MSK BIT(SPI_IDR_TXUD_POS) + +#define SPI_IDR_TXOV_POS 2U +#define SPI_IDR_TXOV_MSK BIT(SPI_IDR_TXOV_POS) + +#define SPI_IDR_TXE_POS 0U +#define SPI_IDR_TXE_MSK BIT(SPI_IDR_TXE_POS) + +/****************** Bit definition for SPI_IVS register ************************/ + +#define SPI_IVS_FRE_POS 18U +#define SPI_IVS_FRE_MSK BIT(SPI_IVS_FRE_POS) + +#define SPI_IVS_MODF_POS 17U +#define SPI_IVS_MODF_MSK BIT(SPI_IVS_MODF_POS) + +#define SPI_IVS_CRCERR_POS 16U +#define SPI_IVS_CRCERR_MSK BIT(SPI_IVS_CRCERR_POS) + +#define SPI_IVS_RXTH_POS 12U +#define SPI_IVS_RXTH_MSK BIT(SPI_IVS_RXTH_POS) + +#define SPI_IVS_RXUD_POS 11U +#define SPI_IVS_RXUD_MSK BIT(SPI_IVS_RXUD_POS) + +#define SPI_IVS_RXOV_POS 10U +#define SPI_IVS_RXOV_MSK BIT(SPI_IVS_RXOV_POS) + +#define SPI_IVS_RXF_POS 9U +#define SPI_IVS_RXF_MSK BIT(SPI_IVS_RXF_POS) + +#define SPI_IVS_RXNE_POS 8U +#define SPI_IVS_RXNE_MSK BIT(SPI_IVS_RXNE_POS) + +#define SPI_IVS_TXTH_POS 4U +#define SPI_IVS_TXTH_MSK BIT(SPI_IVS_TXTH_POS) + +#define SPI_IVS_TXUD_POS 3U +#define SPI_IVS_TXUD_MSK BIT(SPI_IVS_TXUD_POS) + +#define SPI_IVS_TXOV_POS 2U +#define SPI_IVS_TXOV_MSK BIT(SPI_IVS_TXOV_POS) + +#define SPI_IVS_TXE_POS 0U +#define SPI_IVS_TXE_MSK BIT(SPI_IVS_TXE_POS) + +/****************** Bit definition for SPI_RIF register ************************/ + +#define SPI_RIF_FRE_POS 18U +#define SPI_RIF_FRE_MSK BIT(SPI_RIF_FRE_POS) + +#define SPI_RIF_MODF_POS 17U +#define SPI_RIF_MODF_MSK BIT(SPI_RIF_MODF_POS) + +#define SPI_RIF_CRCERR_POS 16U +#define SPI_RIF_CRCERR_MSK BIT(SPI_RIF_CRCERR_POS) + +#define SPI_RIF_RXTH_POS 12U +#define SPI_RIF_RXTH_MSK BIT(SPI_RIF_RXTH_POS) + +#define SPI_RIF_RXUD_POS 11U +#define SPI_RIF_RXUD_MSK BIT(SPI_RIF_RXUD_POS) + +#define SPI_RIF_RXOV_POS 10U +#define SPI_RIF_RXOV_MSK BIT(SPI_RIF_RXOV_POS) + +#define SPI_RIF_RXF_POS 9U +#define SPI_RIF_RXF_MSK BIT(SPI_RIF_RXF_POS) + +#define SPI_RIF_RXNE_POS 8U +#define SPI_RIF_RXNE_MSK BIT(SPI_RIF_RXNE_POS) + +#define SPI_RIF_TXTH_POS 4U +#define SPI_RIF_TXTH_MSK BIT(SPI_RIF_TXTH_POS) + +#define SPI_RIF_TXUD_POS 3U +#define SPI_RIF_TXUD_MSK BIT(SPI_RIF_TXUD_POS) + +#define SPI_RIF_TXOV_POS 2U +#define SPI_RIF_TXOV_MSK BIT(SPI_RIF_TXOV_POS) + +#define SPI_RIF_TXE_POS 0U +#define SPI_RIF_TXE_MSK BIT(SPI_RIF_TXE_POS) + +/****************** Bit definition for SPI_IFM register ************************/ + +#define SPI_IFM_FRE_POS 18U +#define SPI_IFM_FRE_MSK BIT(SPI_IFM_FRE_POS) + +#define SPI_IFM_MODF_POS 17U +#define SPI_IFM_MODF_MSK BIT(SPI_IFM_MODF_POS) + +#define SPI_IFM_CRCERR_POS 16U +#define SPI_IFM_CRCERR_MSK BIT(SPI_IFM_CRCERR_POS) + +#define SPI_IFM_RXTH_POS 12U +#define SPI_IFM_RXTH_MSK BIT(SPI_IFM_RXTH_POS) + +#define SPI_IFM_RXUD_POS 11U +#define SPI_IFM_RXUD_MSK BIT(SPI_IFM_RXUD_POS) + +#define SPI_IFM_RXOV_POS 10U +#define SPI_IFM_RXOV_MSK BIT(SPI_IFM_RXOV_POS) + +#define SPI_IFM_RXF_POS 9U +#define SPI_IFM_RXF_MSK BIT(SPI_IFM_RXF_POS) + +#define SPI_IFM_RXNE_POS 8U +#define SPI_IFM_RXNE_MSK BIT(SPI_IFM_RXNE_POS) + +#define SPI_IFM_TXTH_POS 4U +#define SPI_IFM_TXTH_MSK BIT(SPI_IFM_TXTH_POS) + +#define SPI_IFM_TXUD_POS 3U +#define SPI_IFM_TXUD_MSK BIT(SPI_IFM_TXUD_POS) + +#define SPI_IFM_TXOV_POS 2U +#define SPI_IFM_TXOV_MSK BIT(SPI_IFM_TXOV_POS) + +#define SPI_IFM_TXE_POS 0U +#define SPI_IFM_TXE_MSK BIT(SPI_IFM_TXE_POS) + +/****************** Bit definition for SPI_ICR register ************************/ + +#define SPI_ICR_FRE_POS 18U +#define SPI_ICR_FRE_MSK BIT(SPI_ICR_FRE_POS) + +#define SPI_ICR_MODF_POS 17U +#define SPI_ICR_MODF_MSK BIT(SPI_ICR_MODF_POS) + +#define SPI_ICR_CRCERR_POS 16U +#define SPI_ICR_CRCERR_MSK BIT(SPI_ICR_CRCERR_POS) + +#define SPI_ICR_RXTH_POS 12U +#define SPI_ICR_RXTH_MSK BIT(SPI_ICR_RXTH_POS) + +#define SPI_ICR_RXUD_POS 11U +#define SPI_ICR_RXUD_MSK BIT(SPI_ICR_RXUD_POS) + +#define SPI_ICR_RXOV_POS 10U +#define SPI_ICR_RXOV_MSK BIT(SPI_ICR_RXOV_POS) + +#define SPI_ICR_RXF_POS 9U +#define SPI_ICR_RXF_MSK BIT(SPI_ICR_RXF_POS) + +#define SPI_ICR_RXNE_POS 8U +#define SPI_ICR_RXNE_MSK BIT(SPI_ICR_RXNE_POS) + +#define SPI_ICR_TXTH_POS 4U +#define SPI_ICR_TXTH_MSK BIT(SPI_ICR_TXTH_POS) + +#define SPI_ICR_TXUD_POS 3U +#define SPI_ICR_TXUD_MSK BIT(SPI_ICR_TXUD_POS) + +#define SPI_ICR_TXOV_POS 2U +#define SPI_ICR_TXOV_MSK BIT(SPI_ICR_TXOV_POS) + +#define SPI_ICR_TXE_POS 0U +#define SPI_ICR_TXE_MSK BIT(SPI_ICR_TXE_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __I uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; + __IO uint32_t I2SCFG; + __IO uint32_t I2SPR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} SPI_I2S_TypeDef; + + + + + +#endif /* __REG_SPI_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_syscfg.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_syscfg.h new file mode 100644 index 0000000000..9724532800 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_syscfg.h @@ -0,0 +1,142 @@ +/********************************************************************************** + * + * @file reg_syscfg.h + * @brief SYSCFG Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_SYSCFG_H__ +#define __REG_SYSCFG_H__ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 1U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_BTADDR register ************************/ + +#define SYSCFG_BTADDR_BTADDR_POSS 0U +#define SYSCFG_BTADDR_BTADDR_POSE 17U +#define SYSCFG_BTADDR_BTADDR_MSK BITS(SYSCFG_BTADDR_BTADDR_POSS,SYSCFG_BTADDR_BTADDR_POSE) + +/****************** Bit definition for SYSCFG_TBKCFG register ************************/ + +#define SYSCFG_TBKCFG_CLUBKE_POS 2U +#define SYSCFG_TBKCFG_CLUBKE_MSK BIT(SYSCFG_TBKCFG_CLUBKE_POS) + +#define SYSCFG_TBKCFG_LVDBKE_POS 1U +#define SYSCFG_TBKCFG_LVDBKE_MSK BIT(SYSCFG_TBKCFG_LVDBKE_POS) + +#define SYSCFG_TBKCFG_CCSBKE_POS 0U +#define SYSCFG_TBKCFG_CCSBKE_MSK BIT(SYSCFG_TBKCFG_CCSBKE_POS) + +/****************** Bit definition for SYSCFG_PISIOCFG register ************************/ + +#define SYSCFG_PISIOCFG_IO15SEL_POSS 30U +#define SYSCFG_PISIOCFG_IO15SEL_POSE 31U +#define SYSCFG_PISIOCFG_IO15SEL_MSK BITS(SYSCFG_PISIOCFG_IO15SEL_POSS,SYSCFG_PISIOCFG_IO15SEL_POSE) + +#define SYSCFG_PISIOCFG_IO14SEL_POSS 28U +#define SYSCFG_PISIOCFG_IO14SEL_POSE 29U +#define SYSCFG_PISIOCFG_IO14SEL_MSK BITS(SYSCFG_PISIOCFG_IO14SEL_POSS,SYSCFG_PISIOCFG_IO14SEL_POSE) + +#define SYSCFG_PISIOCFG_IO13SEL_POSS 26U +#define SYSCFG_PISIOCFG_IO13SEL_POSE 27U +#define SYSCFG_PISIOCFG_IO13SEL_MSK BITS(SYSCFG_PISIOCFG_IO13SEL_POSS,SYSCFG_PISIOCFG_IO13SEL_POSE) + +#define SYSCFG_PISIOCFG_IO12SEL_POSS 24U +#define SYSCFG_PISIOCFG_IO12SEL_POSE 25U +#define SYSCFG_PISIOCFG_IO12SEL_MSK BITS(SYSCFG_PISIOCFG_IO12SEL_POSS,SYSCFG_PISIOCFG_IO12SEL_POSE) + +#define SYSCFG_PISIOCFG_IO11SEL_POSS 22U +#define SYSCFG_PISIOCFG_IO11SEL_POSE 23U +#define SYSCFG_PISIOCFG_IO11SEL_MSK BITS(SYSCFG_PISIOCFG_IO11SEL_POSS,SYSCFG_PISIOCFG_IO11SEL_POSE) + +#define SYSCFG_PISIOCFG_IO10SEL_POSS 20U +#define SYSCFG_PISIOCFG_IO10SEL_POSE 21U +#define SYSCFG_PISIOCFG_IO10SEL_MSK BITS(SYSCFG_PISIOCFG_IO10SEL_POSS,SYSCFG_PISIOCFG_IO10SEL_POSE) + +#define SYSCFG_PISIOCFG_IO9SEL_POSS 18U +#define SYSCFG_PISIOCFG_IO9SEL_POSE 19U +#define SYSCFG_PISIOCFG_IO9SEL_MSK BITS(SYSCFG_PISIOCFG_IO9SEL_POSS,SYSCFG_PISIOCFG_IO9SEL_POSE) + +#define SYSCFG_PISIOCFG_IO8SEL_POSS 16U +#define SYSCFG_PISIOCFG_IO8SEL_POSE 17U +#define SYSCFG_PISIOCFG_IO8SEL_MSK BITS(SYSCFG_PISIOCFG_IO8SEL_POSS,SYSCFG_PISIOCFG_IO8SEL_POSE) + +#define SYSCFG_PISIOCFG_IO7SEL_POSS 14U +#define SYSCFG_PISIOCFG_IO7SEL_POSE 15U +#define SYSCFG_PISIOCFG_IO7SEL_MSK BITS(SYSCFG_PISIOCFG_IO7SEL_POSS,SYSCFG_PISIOCFG_IO7SEL_POSE) + +#define SYSCFG_PISIOCFG_IO6SEL_POSS 12U +#define SYSCFG_PISIOCFG_IO6SEL_POSE 13U +#define SYSCFG_PISIOCFG_IO6SEL_MSK BITS(SYSCFG_PISIOCFG_IO6SEL_POSS,SYSCFG_PISIOCFG_IO6SEL_POSE) + +#define SYSCFG_PISIOCFG_IO5SEL_POSS 10U +#define SYSCFG_PISIOCFG_IO5SEL_POSE 11U +#define SYSCFG_PISIOCFG_IO5SEL_MSK BITS(SYSCFG_PISIOCFG_IO5SEL_POSS,SYSCFG_PISIOCFG_IO5SEL_POSE) + +#define SYSCFG_PISIOCFG_IO4SEL_POSS 8U +#define SYSCFG_PISIOCFG_IO4SEL_POSE 9U +#define SYSCFG_PISIOCFG_IO4SEL_MSK BITS(SYSCFG_PISIOCFG_IO4SEL_POSS,SYSCFG_PISIOCFG_IO4SEL_POSE) + +#define SYSCFG_PISIOCFG_IO3SEL_POSS 6U +#define SYSCFG_PISIOCFG_IO3SEL_POSE 7U +#define SYSCFG_PISIOCFG_IO3SEL_MSK BITS(SYSCFG_PISIOCFG_IO3SEL_POSS,SYSCFG_PISIOCFG_IO3SEL_POSE) + +#define SYSCFG_PISIOCFG_IO2SEL_POSS 4U +#define SYSCFG_PISIOCFG_IO2SEL_POSE 5U +#define SYSCFG_PISIOCFG_IO2SEL_MSK BITS(SYSCFG_PISIOCFG_IO2SEL_POSS,SYSCFG_PISIOCFG_IO2SEL_POSE) + +#define SYSCFG_PISIOCFG_IO1SEL_POSS 2U +#define SYSCFG_PISIOCFG_IO1SEL_POSE 3U +#define SYSCFG_PISIOCFG_IO1SEL_MSK BITS(SYSCFG_PISIOCFG_IO1SEL_POSS,SYSCFG_PISIOCFG_IO1SEL_POSE) + +#define SYSCFG_PISIOCFG_IO0SEL_POSS 0U +#define SYSCFG_PISIOCFG_IO0SEL_POSE 1U +#define SYSCFG_PISIOCFG_IO0SEL_MSK BITS(SYSCFG_PISIOCFG_IO0SEL_POSS,SYSCFG_PISIOCFG_IO0SEL_POSE) + +typedef struct +{ + __IO uint32_t PROT; + uint32_t RESERVED0 ; + __IO uint32_t BTADDR; + __IO uint32_t TBKCFG; + __IO uint32_t PISIOCFG; +} SYSCFG_TypeDef; + + + + + +#endif /* __REG_SYSCFG_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_timer.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_timer.h new file mode 100644 index 0000000000..ab18f54264 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_timer.h @@ -0,0 +1,634 @@ +/********************************************************************************** + * + * @file reg_timer.h + * @brief TIMER Head File + * + * @date 06 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_TIMER_H__ +#define __REG_TIMER_H__ + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DBGSEL_POS 15U +#define TIMER_CON1_DBGSEL_MSK BIT(TIMER_CON1_DBGSEL_POS) + +#define TIMER_CON1_OCCISS_POSS 11U +#define TIMER_CON1_OCCISS_POSE 13U +#define TIMER_CON1_OCCISS_MSK BITS(TIMER_CON1_OCCISS_POSS,TIMER_CON1_OCCISS_POSE) + +#define TIMER_CON1_OCCISP_POS 10U +#define TIMER_CON1_OCCISP_MSK BIT(TIMER_CON1_OCCISP_POS) + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_OCCS_POS 3U +#define TIMER_SMCON_OCCS_MSK BIT(TIMER_SMCON_OCCS_POS) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_IER register ************************/ + +#define TIMER_IER_BRKIT_POS 7U +#define TIMER_IER_BRKIT_MSK BIT(TIMER_IER_BRKIT_POS) + +#define TIMER_IER_TRGIT_POS 6U +#define TIMER_IER_TRGIT_MSK BIT(TIMER_IER_TRGIT_POS) + +#define TIMER_IER_COMIT_POS 5U +#define TIMER_IER_COMIT_MSK BIT(TIMER_IER_COMIT_POS) + +#define TIMER_IER_CC4IT_POS 4U +#define TIMER_IER_CC4IT_MSK BIT(TIMER_IER_CC4IT_POS) + +#define TIMER_IER_CC3IT_POS 3U +#define TIMER_IER_CC3IT_MSK BIT(TIMER_IER_CC3IT_POS) + +#define TIMER_IER_CC2IT_POS 2U +#define TIMER_IER_CC2IT_MSK BIT(TIMER_IER_CC2IT_POS) + +#define TIMER_IER_CC1IT_POS 1U +#define TIMER_IER_CC1IT_MSK BIT(TIMER_IER_CC1IT_POS) + +#define TIMER_IER_UIT_POS 0U +#define TIMER_IER_UIT_MSK BIT(TIMER_IER_UIT_POS) + +/****************** Bit definition for TIMER_IDR register ************************/ + +#define TIMER_IDR_BRKI_POS 7U +#define TIMER_IDR_BRKI_MSK BIT(TIMER_IDR_BRKI_POS) + +#define TIMER_IDR_TRGI_POS 6U +#define TIMER_IDR_TRGI_MSK BIT(TIMER_IDR_TRGI_POS) + +#define TIMER_IDR_COMI_POS 5U +#define TIMER_IDR_COMI_MSK BIT(TIMER_IDR_COMI_POS) + +#define TIMER_IDR_CC4I_POS 4U +#define TIMER_IDR_CC4I_MSK BIT(TIMER_IDR_CC4I_POS) + +#define TIMER_IDR_CC3I_POS 3U +#define TIMER_IDR_CC3I_MSK BIT(TIMER_IDR_CC3I_POS) + +#define TIMER_IDR_CC2I_POS 2U +#define TIMER_IDR_CC2I_MSK BIT(TIMER_IDR_CC2I_POS) + +#define TIMER_IDR_CC1I_POS 1U +#define TIMER_IDR_CC1I_MSK BIT(TIMER_IDR_CC1I_POS) + +#define TIMER_IDR_UI_POS 0U +#define TIMER_IDR_UI_MSK BIT(TIMER_IDR_UI_POS) + +/****************** Bit definition for TIMER_IVS register ************************/ + +#define TIMER_IVS_BKI_POS 7U +#define TIMER_IVS_BKI_MSK BIT(TIMER_IVS_BKI_POS) + +#define TIMER_IVS_TRGI_POS 6U +#define TIMER_IVS_TRGI_MSK BIT(TIMER_IVS_TRGI_POS) + +#define TIMER_IVS_COMI_POS 5U +#define TIMER_IVS_COMI_MSK BIT(TIMER_IVS_COMI_POS) + +#define TIMER_IVS_CC4I_POS 4U +#define TIMER_IVS_CC4I_MSK BIT(TIMER_IVS_CC4I_POS) + +#define TIMER_IVS_CC3I_POS 3U +#define TIMER_IVS_CC3I_MSK BIT(TIMER_IVS_CC3I_POS) + +#define TIMER_IVS_CC2I_POS 2U +#define TIMER_IVS_CC2I_MSK BIT(TIMER_IVS_CC2I_POS) + +#define TIMER_IVS_CC1I_POS 1U +#define TIMER_IVS_CC1I_MSK BIT(TIMER_IVS_CC1I_POS) + +#define TIMER_IVS_UEI_POS 0U +#define TIMER_IVS_UEI_MSK BIT(TIMER_IVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SEL_POSS 8U +#define TIMER_CHMR1_CC2SEL_POSE 9U +#define TIMER_CHMR1_CC2SEL_MSK BITS(TIMER_CHMR1_CC2SEL_POSS,TIMER_CHMR1_CC2SEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NE_POS 10U +#define TIMER_CCEP_CC3NE_MSK BIT(TIMER_CCEP_CC3NE_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NE_POS 6U +#define TIMER_CCEP_CC2NE_MSK BIT(TIMER_CCEP_CC2NE_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NE_POS 2U +#define TIMER_CCEP_CC1NE_MSK BIT(TIMER_CCEP_CC1NE_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +/****************** Bit definition for TIMER_DMAEN register ************************/ + +#define TIMER_DMAEN_TDS_POS 6U +#define TIMER_DMAEN_TDS_MSK BIT(TIMER_DMAEN_TDS_POS) + +#define TIMER_DMAEN_COMDS_POS 5U +#define TIMER_DMAEN_COMDS_MSK BIT(TIMER_DMAEN_COMDS_POS) + +#define TIMER_DMAEN_CC4DS_POS 4U +#define TIMER_DMAEN_CC4DS_MSK BIT(TIMER_DMAEN_CC4DS_POS) + +#define TIMER_DMAEN_CC3DS_POS 3U +#define TIMER_DMAEN_CC3DS_MSK BIT(TIMER_DMAEN_CC3DS_POS) + +#define TIMER_DMAEN_CC2DS_POS 2U +#define TIMER_DMAEN_CC2DS_MSK BIT(TIMER_DMAEN_CC2DS_POS) + +#define TIMER_DMAEN_CC1DS_POS 1U +#define TIMER_DMAEN_CC1DS_MSK BIT(TIMER_DMAEN_CC1DS_POS) + +#define TIMER_DMAEN_UDS_POS 0U +#define TIMER_DMAEN_UDS_MSK BIT(TIMER_DMAEN_UDS_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; + __IO uint32_t DMAEN; +} TIMER_TypeDef; + + + + + +#endif /* __REG_TIMER_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_uart.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_uart.h new file mode 100644 index 0000000000..8177df348d --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_uart.h @@ -0,0 +1,547 @@ +/********************************************************************************** + * + * @file reg_uart.h + * @brief UART Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_UART_H__ +#define __REG_UART_H__ + +/****************** Bit definition for UART_RXBUF register ************************/ + +#define UART_RXBUF_RXBUF_POSS 0U +#define UART_RXBUF_RXBUF_POSE 8U +#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) + +/****************** Bit definition for UART_TXBUF register ************************/ + +#define UART_TXBUF_TXBUF_POSS 0U +#define UART_TXBUF_TXBUF_POSE 8U +#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCON register ************************/ + +#define UART_LCON_TXEN_POS 15U +#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) + +#define UART_LCON_RXEN_POS 14U +#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) + +#define UART_LCON_DBCEN_POS 13U +#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) + +#define UART_LCON_BREAK_POS 10U +#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) + +#define UART_LCON_SWAP_POS 9U +#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) + +#define UART_LCON_TXINV_POS 8U +#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) + +#define UART_LCON_RXINV_POS 7U +#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) + +#define UART_LCON_DATAINV_POS 6U +#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) + +#define UART_LCON_MSB_POS 5U +#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) + +#define UART_LCON_PS_POS 4U +#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) + +#define UART_LCON_PE_POS 3U +#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) + +#define UART_LCON_STOP_POS 2U +#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) + +#define UART_LCON_DLS_POSS 0U +#define UART_LCON_DLS_POSE 1U +#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) + +/****************** Bit definition for UART_MCON register ************************/ + +#define UART_MCON_TXFLOAT_POS 16U +#define UART_MCON_TXFLOAT_MSK BIT(UART_MCON_TXFLOAT_POS) + +#define UART_MCON_TXDMAEN_POS 15U +#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) + +#define UART_MCON_RXDMAEN_POS 14U +#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) + +#define UART_MCON_ABRREPT_POS 11U +#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) + +#define UART_MCON_ABRMOD_POSS 9U +#define UART_MCON_ABRMOD_POSE 10U +#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) + +#define UART_MCON_ABREN_POS 8U +#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) + +#define UART_MCON_BKREQ_POS 5U +#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) + +#define UART_MCON_HDEN_POS 4U +#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) + +#define UART_MCON_IREN_POS 3U +#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) + +#define UART_MCON_AFCEN_POS 2U +#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) + +#define UART_MCON_RTSSET_POS 1U +#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) + +#define UART_MCON_LPBKEN_POS 0U +#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) + +/****************** Bit definition for UART_RS485 register ************************/ + +#define UART_RS485_DLY_POSS 16U +#define UART_RS485_DLY_POSE 23U +#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) + +#define UART_RS485_ADDR_POSS 8U +#define UART_RS485_ADDR_POSE 15U +#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) + +#define UART_RS485_AADINV_POS 3U +#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) + +#define UART_RS485_AADACEN_POS 2U +#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) + +#define UART_RS485_AADNEN_POS 1U +#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) + +#define UART_RS485_AADEN_POS 0U +#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) + +/****************** Bit definition for UART_SCARD register ************************/ + +#define UART_SCARD_BLEN_POSS 24U +#define UART_SCARD_BLEN_POSE 31U +#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) + +#define UART_SCARD_GT_POSS 16U +#define UART_SCARD_GT_POSE 23U +#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) + +#define UART_SCARD_PSC_POSS 8U +#define UART_SCARD_PSC_POSE 15U +#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) + +#define UART_SCARD_SCCNT_POSS 3U +#define UART_SCARD_SCCNT_POSE 5U +#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) + +#define UART_SCARD_SCLKEN_POS 2U +#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) + +#define UART_SCARD_SCNACK_POS 1U +#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) + +#define UART_SCARD_SCEN_POS 0U +#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) + +/****************** Bit definition for UART_LIN register ************************/ + +#define UART_LIN_LINBKREQ_POS 2U +#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) + +#define UART_LIN_LINBDL_POS 1U +#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) + +#define UART_LIN_LINEN_POS 0U +#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_RTOEN_POS 24U +#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_STAT register ************************/ + +#define UART_STAT_TFOERR_POS 18U +#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) + +#define UART_STAT_TFEMPTY_POS 16U +#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) + +#define UART_STAT_TSBUSY_POS 14U +#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) + +#define UART_STAT_RFUERR_POS 13U +#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) + +#define UART_STAT_RFOERR_POS 12U +#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) + +#define UART_STAT_RFNEMPTY_POS 10U +#define UART_STAT_RFNEMPTY_MSK BIT(UART_STAT_RFNEMPTY_POS) + +#define UART_STAT_RSBUSY_POS 8U +#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) + +#define UART_STAT_CTSSTA_POS 3U +#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) + +#define UART_STAT_BKERR_POS 2U +#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) + +#define UART_STAT_FERR_POS 1U +#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) + +#define UART_STAT_PERR_POS 0U +#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_TFOERR_POS 18U +#define UART_IER_TFOERR_MSK BIT(UART_IER_TFOERR_POS) + +#define UART_IER_TFEMPTY_POS 16U +#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) + +#define UART_IER_TBC_POS 14U +#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) + +#define UART_IER_RFUERR_POS 13U +#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) + +#define UART_IER_RFOERR_POS 12U +#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) + +#define UART_IER_RFNEMPTY_POS 10U +#define UART_IER_RFNEMPTY_MSK BIT(UART_IER_RFNEMPTY_POS) + +#define UART_IER_NOISE_POS 8U +#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) + +#define UART_IER_EOB_POS 7U +#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) + +#define UART_IER_LINBK_POS 6U +#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) + +#define UART_IER_ADDRM_POS 5U +#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) + +#define UART_IER_RXTO_POS 4U +#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) + +#define UART_IER_DCTS_POS 3U +#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) + +#define UART_IER_ABTO_POS 2U +#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) + +#define UART_IER_ABEND_POS 1U +#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) + +#define UART_IER_RXBERR_POS 0U +#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_TFOVER_POS 18U +#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) + +#define UART_IDR_TFEMPTY_POS 16U +#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) + +#define UART_IDR_TBC_POS 14U +#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) + +#define UART_IDR_RFUERR_POS 13U +#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) + +#define UART_IDR_RFOERR_POS 12U +#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) + +#define UART_IDR_RFNEMPTY_POS 10U +#define UART_IDR_RFNEMPTY_MSK BIT(UART_IDR_RFNEMPTY_POS) + +#define UART_IDR_NOISE_POS 8U +#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) + +#define UART_IDR_EOB_POS 7U +#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) + +#define UART_IDR_LINBK_POS 6U +#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) + +#define UART_IDR_ADDRM_POS 5U +#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) + +#define UART_IDR_RXTO_POS 4U +#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) + +#define UART_IDR_DCTS_POS 3U +#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) + +#define UART_IDR_ABTO_POS 2U +#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) + +#define UART_IDR_ABEND_POS 1U +#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) + +#define UART_IDR_RXBERR_POS 0U +#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_TFOVER_POS 18U +#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) + +#define UART_IVS_TFEMPTY_POS 16U +#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) + +#define UART_IVS_TBC_POS 14U +#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) + +#define UART_IVS_RFUERR_POS 13U +#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) + +#define UART_IVS_RFOERR_POS 12U +#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) + +#define UART_IVS_RFNEMPTY_POS 10U +#define UART_IVS_RFNEMPTY_MSK BIT(UART_IVS_RFNEMPTY_POS) + +#define UART_IVS_NOISE_POS 8U +#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) + +#define UART_IVS_EOB_POS 7U +#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) + +#define UART_IVS_LINBK_POS 6U +#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) + +#define UART_IVS_ADDRM_POS 5U +#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) + +#define UART_IVS_RXTO_POS 4U +#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) + +#define UART_IVS_DCTS_POS 3U +#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) + +#define UART_IVS_ABTO_POS 2U +#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) + +#define UART_IVS_ABEND_POS 1U +#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) + +#define UART_IVS_RXBERR_POS 0U +#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_TFOVER_POS 18U +#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) + +#define UART_RIF_TFEMPTY_POS 16U +#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) + +#define UART_RIF_TBC_POS 14U +#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) + +#define UART_RIF_RFUERR_POS 13U +#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) + +#define UART_RIF_RFOERR_POS 12U +#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) + +#define UART_RIF_RFNEMPTY_POS 10U +#define UART_RIF_RFNEMPTY_MSK BIT(UART_RIF_RFNEMPTY_POS) + +#define UART_RIF_NOISE_POS 8U +#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) + +#define UART_RIF_EOB_POS 7U +#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) + +#define UART_RIF_LINBK_POS 6U +#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) + +#define UART_RIF_ADDRM_POS 5U +#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) + +#define UART_RIF_RXTO_POS 4U +#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) + +#define UART_RIF_DCTS_POS 3U +#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) + +#define UART_RIF_ABTO_POS 2U +#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) + +#define UART_RIF_ABEND_POS 1U +#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) + +#define UART_RIF_RXBERR_POS 0U +#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_TFOVER_POS 18U +#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) + +#define UART_IFM_TFEMPTY_POS 16U +#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) + +#define UART_IFM_TBC_POS 14U +#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) + +#define UART_IFM_RFUERR_POS 13U +#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) + +#define UART_IFM_RFOERR_POS 12U +#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) + +#define UART_IFM_RFNEMPTY_POS 10U +#define UART_IFM_RFNEMPTY_MSK BIT(UART_IFM_RFNEMPTY_POS) + +#define UART_IFM_NOISE_POS 8U +#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) + +#define UART_IFM_EOB_POS 7U +#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) + +#define UART_IFM_LINBK_POS 6U +#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) + +#define UART_IFM_ADDRM_POS 5U +#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) + +#define UART_IFM_RXTO_POS 4U +#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) + +#define UART_IFM_DCTS_POS 3U +#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) + +#define UART_IFM_ABTO_POS 2U +#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) + +#define UART_IFM_ABEND_POS 1U +#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) + +#define UART_IFM_RXBERR_POS 0U +#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_TFOVER_POS 18U +#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) + +#define UART_ICR_TFEMPTY_POS 16U +#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) + +#define UART_ICR_TBC_POS 14U +#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) + +#define UART_ICR_RFUERC_W1_POS 13U +#define UART_ICR_RFUERC_W1_MSK BIT(UART_ICR_RFUERC_W1_POS) + +#define UART_ICR_RFOERC_W1_POS 12U +#define UART_ICR_RFOERC_W1_MSK BIT(UART_ICR_RFOERC_W1_POS) + +#define UART_ICR_RFNEMPTY_POS 10U +#define UART_ICR_RFNEMPTY_MSK BIT(UART_ICR_RFNEMPTY_POS) + +#define UART_ICR_NOISE_POS 8U +#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) + +#define UART_ICR_EOB_POS 7U +#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) + +#define UART_ICR_LINBK_POS 6U +#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) + +#define UART_ICR_ADDRM_POS 5U +#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) + +#define UART_ICR_RXTO_POS 4U +#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) + +#define UART_ICR_DCTS_POS 3U +#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) + +#define UART_ICR_ABTO_POS 2U +#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) + +#define UART_ICR_ABEND_POS 1U +#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) + +#define UART_ICR_RXBERR_POS 0U +#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) + +typedef struct +{ + __I uint32_t RXBUF; + __IO uint32_t TXBUF; + __IO uint32_t BRR; + __IO uint32_t LCON; + __IO uint32_t MCON; + __IO uint32_t RS485; + __IO uint32_t SCARD; + __IO uint32_t LIN; + __IO uint32_t RTOR; + uint32_t RESERVED0 ; + __I uint32_t STAT; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + + + + + +#endif /* __REG_UART_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_usb.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_usb.h new file mode 100644 index 0000000000..43bbead28f --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_usb.h @@ -0,0 +1,969 @@ +/** + ************************************************************************************** + * @file reg_usb.h + * @brief USB Head File + * @data 5/22/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_USB_H__ +#define __REG_USB_H__ + + +/******************************************************************************/ +/* 特殊结构体定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_ADDR_POSS 0U +#define USB_FADDR_ADDR_POSE 6U +#define USB_FADDR_ADDR_MSK BITS(USB_FADDR_ADDR_POSS,USB_FADDR_ADDR_POSE) + +/****************** Bit definition for USB_POWER register ************************/ + +/* device/host mode */ +#define USB_POWER_ISOUDT_POS 7U +#define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POS) + +/* device mode */ +#define USB_POWER_RESET_POS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POS) + +#define USB_POWER_RESUME_POS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POS) + +#define USB_POWER_SUSPEND_POS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POS) + +/* device mode */ +#define USB_POWER_SUSPENDEN_POS 0U +#define USB_POWER_SUSPENDEN_MSK BIT(USB_POWER_SUSPENDEN_POS) + +/****************** Bit definition for USB_DPDMCON register ************************/ + +#define USB_DPDMCON_DPPUD_POSS 3U +#define USB_DPDMCON_DPPUD_POSE 4U +#define USB_DPDMCON_DPPUD_MSK BITS(USB_DPDMCON_DPPUD_POSS,USB_DPDMCON_DPPUD_POSE) + +#define USB_DPDMCON_DMPUD_POSS 1U +#define USB_DPDMCON_DMPUD_POSE 2U +#define USB_DPDMCON_DMPUD_MSK BITS(USB_DPDMCON_DMPUD_POSS,USB_DPDMCON_DMPUD_POSE) + +#define USB_DPDMCON_PHYPWREN_POS 0U +#define USB_DPDMCON_PHYPWREN_MSK BIT(USB_DPDMCON_PHYPWREN_POS) + +/****************** Bit definition for USB_SWCID register ************************/ + +#define USB_SWCID_HOST_POS 1U +#define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POS) + +#define USB_SWCID_CIDCTRL_POS 0U +#define USB_SWCID_CIDCTRL_MSK BIT(USB_SWCID_CIDCTRL_POS) + +/****************** Bit definition for USB_SWVBUS register ************************/ + +#define USB_SWVBUS_VALTH_POS 3U +#define USB_SWVBUS_VALTH_MSK BIT(USB_SWVBUS_VALTH_POS) + +#define USB_SWVBUS_SESVALTH_POS 2U +#define USB_SWVBUS_SESVALTH_MSK BIT(USB_SWVBUS_SESVALTH_POS) + +#define USB_SWVBUS_SESENDTH_POS 1U +#define USB_SWVBUS_SESENDTH_MSK BIT(USB_SWVBUS_SESENDTH_POS) + +#define USB_SWVBUS_SIGCTRL_POS 0U +#define USB_SWVBUS_SIGCTRL_MSK BIT(USB_SWVBUS_SIGCTRL_POS) + +/****************** Bit definition for USB_TMODE register ************************/ + +#define USB_TMODE_PROTECT_POSS 2U +#define USB_TMODE_PROTECT_POSE 7U +#define USB_TMODE_PROTECT_MSK BITS(USB_TMODE_PROTECT_POSS,USB_TMODE_PROTECT_POSE) + +#define USB_TMODE_MEMTST_EN_POS 1U +#define USB_TMODE_MEMTST_EN_MSK BIT(USB_TMODE_MEMTST_EN_POS) +#define USB_TMODE_MEMTST_EN USB_TMODE_MEMTST_EN_MSK + +#define USB_TMODE_ENABLE_POS 0U +#define USB_TMODE_ENABLE_MSK BIT(USB_TMODE_ENABLE_POS) + +/****************** Bit definition for USB_FRAME1 register ************************/ + +#define USB_FRAME1_LOWFRAME_POSS 0U +#define USB_FRAME1_LOWFRAME_POSE 7U +#define USB_FRAME1_LOWFRAME_MSK BITS(USB_FRAME1_LOWFRAME_POSS,USB_FRAME1_LOWFRAME_POSE) + +/****************** Bit definition for USB_FRAME2 register ************************/ + +#define USB_FRAME2_UPFRAME_POSS 0U +#define USB_FRAME2_UPFRAME_POSE 2U +#define USB_FRAME2_UPFRAME_MSK BITS(USB_FRAME2_UPFRAME_POSS,USB_FRAME2_UPFRAME_POSE) + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EPTIDX_POSS 0U +#define USB_INDEX_EPTIDX_POSE 3U +#define USB_INDEX_EPTIDX_MSK BITS(USB_INDEX_EPTIDX_POSS,USB_INDEX_EPTIDX_POSE) + +/****************** Bit definition for USB_DEVCON register ************************/ + +#define USB_DEVCON_FSDEV_POS 6U +#define USB_DEVCON_FSDEV_MSK BIT(USB_DEVCON_FSDEV_POS) + +#define USB_DEVCON_LSDEV_POS 5U +#define USB_DEVCON_LSDEV_MSK BIT(USB_DEVCON_LSDEV_POS) + +#define USB_DEVCON_HOST_POS 2U +#define USB_DEVCON_HOST_MSK BIT(USB_DEVCON_HOST_POS) + +#define USB_DEVCON_HOSTREQ_POS 1U +#define USB_DEVCON_HOSTREQ_MSK BIT(USB_DEVCON_HOSTREQ_POS) + +#define USB_DEVCON_SESSION_POS 0U +#define USB_DEVCON_SESSION_MSK BIT(USB_DEVCON_SESSION_POS) + +/****************** Bit definition for USB_TXMAXP register ************************/ + +#define USB_TXMAXP_MAXSIZE_POSS 0U +#define USB_TXMAXP_MAXSIZE_POSE 7U +#define USB_TXMAXP_MAXSIZE_MSK BITS(USB_TXMAXP_MAXSIZE_POSS,USB_TXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_CSR0L_TXCSRL register ************************/ + +/* Endpoint 0 */ +/* device mode */ +#define USB_CSR0L_SETENDC_POS 7U +#define USB_CSR0L_SETENDC_MSK BIT(USB_CSR0L_SETENDC_POS) + +#define USB_CSR0L_RXRDYC_POS 6U +#define USB_CSR0L_RXRDYC_MSK BIT(USB_CSR0L_RXRDYC_POS) + +#define USB_CSR0L_STALL_POS 5U +#define USB_CSR0L_STALL_MSK BIT(USB_CSR0L_STALL_POS) + +#define USB_CSR0L_SETEND_POS 4U +#define USB_CSR0L_SETEND_MSK BIT(USB_CSR0L_SETEND_POS) + +#define USB_CSR0L_DATAEND_POS 3U +#define USB_CSR0L_DATAEND_MSK BIT(USB_CSR0L_DATAEND_POS) + +/* host mode */ +#define USB_CSR0L_NAKTO_POS 7U +#define USB_CSR0L_NAKTO_MSK BIT(USB_CSR0L_NAKTO_POS) + +#define USB_CSR0L_STATUSPKT_POS 6U +#define USB_CSR0L_STATUSPKT_MSK BIT(USB_CSR0L_STATUSPKT_POS) + +#define USB_CSR0L_REQPKT_POS 5U +#define USB_CSR0L_REQPKT_MSK BIT(USB_CSR0L_REQPKT_POS) + +#define USB_CSR0L_ERROR_POS 4U +#define USB_CSR0L_ERROR_MSK BIT(USB_CSR0L_ERROR_POS) + +#define USB_CSR0L_SETUPPKT_POS 3U +#define USB_CSR0L_SETUPPKT_MSK BIT(USB_CSR0L_SETUPPKT_POS) + +/* device/host mode */ +#define USB_CSR0L_STALLED_POS 2U +#define USB_CSR0L_STALLED_MSK BIT(USB_CSR0L_STALLED_POS) + +#define USB_CSR0L_TXRDY_POS 1U +#define USB_CSR0L_TXRDY_MSK BIT(USB_CSR0L_TXRDY_POS) + +#define USB_CSR0L_RXRDY_POS 0U +#define USB_CSR0L_RXRDY_MSK BIT(USB_CSR0L_RXRDY_POS) + +/* Endpoint 1-6 */ +/* host mode */ +#define USB_TXCSRL_NAKTO_POS 7U +#define USB_TXCSRL_NAKTO_MSK BIT(USB_TXCSRL_NAKTO_POS) + +/* device/host mode */ +#define USB_TXCSRL_CLRDT_POS 6U +#define USB_TXCSRL_CLRDT_MSK BIT(USB_TXCSRL_CLRDT_POS) + +#define USB_TXCSRL_STALLED_POS 5U +#define USB_TXCSRL_STALLED_MSK BIT(USB_TXCSRL_STALLED_POS) + +/* device mode */ +#define USB_TXCSRL_STALL_POS 4U +#define USB_TXCSRL_STALL_MSK BIT(USB_TXCSRL_STALL_POS) + +/* device/host mode */ +#define USB_TXCSRL_FLUSH_POS 3U +#define USB_TXCSRL_FLUSH_MSK BIT(USB_TXCSRL_FLUSH_POS) + +/* device mode */ +#define USB_TXCSRL_UNDRUN_POS 2U +#define USB_TXCSRL_UNDRUN_MSK BIT(USB_TXCSRL_UNDRUN_POS) + +/* host mode */ +#define USB_TXCSRL_ERROR_POS 2U +#define USB_TXCSRL_ERROR_MSK BIT(USB_TXCSRL_ERROR_POS) + +/* device/host mode */ +#define USB_TXCSRL_FIFONE_POS 1U +#define USB_TXCSRL_FIFONE_MSK BIT(USB_TXCSRL_FIFONE_POS) + +#define USB_TXCSRL_TXRDY_POS 0U +#define USB_TXCSRL_TXRDY_MSK BIT(USB_TXCSRL_TXRDY_POS) + +/****************** Bit definition for USB_CSR0H_TXCSRH register ************************/ + +/* Endpoint 0 */ +/* device/host mode */ +#define USB_CSR0H_FLUSH_POS 0U +#define USB_CSR0H_FLUSH_MSK BIT(USB_CSR0H_FLUSH_POS) + +/* For endpoint 1-6 */ +/* device/host mode */ +#define USB_TXCSRH_AUTOSET_POS 7U +#define USB_TXCSRH_AUTOSET_MSK BIT(USB_TXCSRH_AUTOSET_POS) + +#define USB_TXCSRH_ISO_POS 6U +#define USB_TXCSRH_ISO_MSK BIT(USB_TXCSRH_ISO_POS) + +#define USB_TXCSRH_MODE_POS 5U +#define USB_TXCSRH_MODE_MSK BIT(USB_TXCSRH_MODE_POS) + +#define USB_TXCSRH_FDT_POS 3U +#define USB_TXCSRH_FDT_MSK BIT(USB_TXCSRH_FDT_POS) + +/****************** Bit definition for USB_RXMAXP register ************************/ + +#define USB_RXMAXP_MAXSIZE_POSS 0U +#define USB_RXMAXP_MAXSIZE_POSE 7U +#define USB_RXMAXP_MAXSIZE_MSK BITS(USB_RXMAXP_MAXSIZE_POSS,USB_RXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_RXCSRL register ************************/ + +/* device/host mode */ +#define USB_RXCSRL_CLRDT_POS 7U +#define USB_RXCSRL_CLRDT_MSK BIT(USB_RXCSRL_CLRDT_POS) + +#define USB_RXCSRL_STALLED_POS 6U +#define USB_RXCSRL_STALLED_MSK BIT(USB_RXCSRL_STALLED_POS) + +/* device mode */ +#define USB_RXCSRL_STALL_POS 5U +#define USB_RXCSRL_STALL_MSK BIT(USB_RXCSRL_STALL_POS) + +/* host mode */ +#define USB_RXCSRL_REQPKT_POS 5U +#define USB_RXCSRL_REQPKT_MSK BIT(USB_RXCSRL_REQPKT_POS) + +/* device/host mode */ +#define USB_RXCSRL_FLUSH_POS 4U +#define USB_RXCSRL_FLUSH_MSK BIT(USB_RXCSRL_FLUSH_POS) + +/* device/host mode */ +#define USB_RXCSRL_DATAERR_POS 3U +#define USB_RXCSRL_DATAERR_MSK BIT(USB_RXCSRL_DATAERR_POS) + +/* host mode */ +#define USB_RXCSRL_NAKTO_POS 3U +#define USB_RXCSRL_NAKTO_MSK BIT(USB_RXCSRL_NAKTO_POS) + +/* device mode */ +#define USB_RXCSRL_OVERRUN_POS 2U +#define USB_RXCSRL_OVERRUN_MSK BIT(USB_RXCSRL_OVERRUN_POS) + +/* host mode */ +#define USB_RXCSRL_ERROR_POS 2U +#define USB_RXCSRL_ERROR_MSK BIT(USB_RXCSRL_ERROR_POS) + +/* device/host mode */ +#define USB_RXCSRL_FULL_POS 1U +#define USB_RXCSRL_FULL_MSK BIT(USB_RXCSRL_FULL_POS) + +#define USB_RXCSRL_RXRDY_POS 0U +#define USB_RXCSRL_RXRDY_MSK BIT(USB_RXCSRL_RXRDY_POS) + +/****************** Bit definition for USB_RXCSRH register ************************/ + +/* device/host mode */ +#define USB_RXCSRH_AUTOCLR_POS 7U +#define USB_RXCSRH_AUTOCLR_MSK BIT(USB_RXCSRH_AUTOCLR_POS) + +/* device mode */ +#define USB_RXCSRH_ISO_POS 6U +#define USB_RXCSRH_ISO_MSK BIT(USB_RXCSRH_ISO_POS) + +/* host mode */ +#define USB_RXCSRH_AUTOREQ_POS 6U +#define USB_RXCSRH_AUTOREQ_MSK BIT(USB_RXCSRH_AUTOREQ_POS) + +/****************** Bit definition for USB_COUNT0_RX1 register ************************/ + +/* Endpoint 0 */ +#define USB_COUNT0_COUNT_POSS 0U +#define USB_COUNT0_COUNT_POSE 6U +#define USB_COUNT0_COUNT_MSK BITS(USB_COUNT0_COUNT_POSS,USB_COUNT0_COUNT_POSE) + +// +//For endpoint 1-6 +// +#define USB_RX1_PKTLOW_POSS 0U +#define USB_RX1_PKTLOW_POSE 7U +#define USB_RX1_PKTLOW_MSK BITS(USB_RX1_PKTLOW_POSS,USB_RX1_PKTLOW_POSE) + +/****************** Bit definition for USB_RXCOUNT2 register ************************/ + +#define USB_RXCOUNT2_PKTHIGH_POSS 0U +#define USB_RXCOUNT2_PKTHIGH_POSE 2U +#define USB_RXCOUNT2_PKTHIGH_MSK BITS(USB_RXCOUNT2_PKTHIGH_POSS,USB_RXCOUNT2_PKTHIGH_POSE) + +/****************** Bit definition for USB_TXTYPE register ************************/ + +#define USB_TXTYPE_PROTOCOL_POSS 4U +#define USB_TXTYPE_PROTOCOL_POSE 5U +#define USB_TXTYPE_PROTOCOL_MSK BITS(USB_TXTYPE_PROTOCOL_POSS,USB_TXTYPE_PROTOCOL_POSE) + +#define USB_TXTYPE_TEPN_POSS 0U +#define USB_TXTYPE_TEPN_POSE 3U +#define USB_TXTYPE_TEPN_MSK BITS(USB_TXTYPE_TEPN_POSS,USB_TXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_NAKLIMIT0_TXINTERVAL register ************************/ + +/* Endpoint 0 */ +#define USB_NAKLIMIT0_NAKLMT_POSS 0U +#define USB_NAKLIMIT0_NAKLMT_POSE 7U +#define USB_NAKLIMIT0_NAKLMT_MSK BITS(USB_NAKLIMIT0_NAKLMT_POSS,USB_NAKLIMIT0_NAKLMT_POSE) + +/* For endpoint 1-6 */ +#define USB_TXINTERVAL_TXPOLL_POSS 0U +#define USB_TXINTERVAL_TXPOLL_POSE 7U +#define USB_TXINTERVAL_TXPOLL_MSK BITS(USB_TXINTERVAL_TXPOLL_POSS,USB_TXINTERVAL_TXPOLL_POSE) + +#define USB_TXINTERVAL_NAKLMT_POSS 0U +#define USB_TXINTERVAL_NAKLMT_POSE 7U +#define USB_TXINTERVAL_NAKLMT_MSK BITS(USB_TXINTERVAL_NAKLMT_POSS,USB_TXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_RXTYPE register ************************/ + +#define USB_RXTYPE_PROTOCOL_POSS 4U +#define USB_RXTYPE_PROTOCOL_POSE 5U +#define USB_RXTYPE_PROTOCOL_MSK BITS(USB_RXTYPE_PROTOCOL_POSS,USB_RXTYPE_PROTOCOL_POSE) + +#define USB_RXTYPE_TEPN_POSS 0U +#define USB_RXTYPE_TEPN_POSE 3U +#define USB_RXTYPE_TEPN_MSK BITS(USB_RXTYPE_TEPN_POSS,USB_RXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_RXINTERVAL register ************************/ + +#define USB_RXINTERVAL_RXPOLL_POSS 0U +#define USB_RXINTERVAL_RXPOLL_POSE 7U +#define USB_RXINTERVAL_RXPOLL_MSK BITS(USB_RXINTERVAL_RXPOLL_POSS,USB_RXINTERVAL_RXPOLL_POSE) + +#define USB_RXINTERVAL_NAKLMT_POSS 0U +#define USB_RXINTERVAL_NAKLMT_POSE 7U +#define USB_RXINTERVAL_NAKLMT_MSK BITS(USB_RXINTERVAL_NAKLMT_POSS,USB_RXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_TXFIFO1 register ************************/ + +#define USB_TXFIFO1_ADDRL_POSS 0U +#define USB_TXFIFO1_ADDRL_POSE 7U +#define USB_TXFIFO1_ADDRL_MSK BITS(USB_TXFIFO1_ADDRL_POSS,USB_TXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_TXFIFO2 register ************************/ + +#define USB_TXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_TXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_TXFIFO2_MAXPKTSIZE_MSK BITS(USB_TXFIFO2_MAXPKTSIZE_POSS,USB_TXFIFO2_MAXPKTSIZE_POSE) + +#define USB_TXFIFO2_DPB_POS 4U +#define USB_TXFIFO2_DPB_MSK BIT(USB_TXFIFO2_DPB_POS) + +#define USB_TXFIFO2_ADDRH_POSS 0U +#define USB_TXFIFO2_ADDRH_POSE 3U +#define USB_TXFIFO2_ADDRH_MSK BITS(USB_TXFIFO2_ADDRH_POSS,USB_TXFIFO2_ADDRH_POSE) + +/****************** Bit definition for USB_RXFIFO1 register ************************/ + +#define USB_RXFIFO1_ADDRL_POSS 0U +#define USB_RXFIFO1_ADDRL_POSE 7U +#define USB_RXFIFO1_ADDRL_MSK BITS(USB_RXFIFO1_ADDRL_POSS,USB_RXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_RXFIFO2 register ************************/ + +#define USB_RXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_RXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_RXFIFO2_MAXPKTSIZE_MSK BITS(USB_RXFIFO2_MAXPKTSIZE_POSS,USB_RXFIFO2_MAXPKTSIZE_POSE) + +#define USB_RXFIFO2_DPB_POS 4U +#define USB_RXFIFO2_DPB_MSK BIT(USB_RXFIFO2_DPB_POS) + +#define USB_RXFIFO2_ADDRH_POSS 0U +#define USB_RXFIFO2_ADDRH_POSE 3U +#define USB_RXFIFO2_ADDRH_MSK BITS(USB_RXFIFO2_ADDRH_POSS,USB_RXFIFO2_ADDRH_POSE) + +/************* Bit definition for USB_EP0FIFO/USB_EPxFIFO register *****************/ + +#define USB_EP0FIFO_FIFO0_POSS 0U +#define USB_EP0FIFO_FIFO0_POSE 7U +#define USB_EP0FIFO_FIFO0_MSK BITS(USB_EP0FIFO_FIFO0_POSS,USB_EP0FIFO_FIFO0_POSE) + +#define USB_EP1FIFO_FIFO1_POSS 0U +#define USB_EP1FIFO_FIFO1_POSE 7U +#define USB_EP1FIFO_FIFO1_MSK BITS(USB_EP1FIFO_FIFO1_POSS,USB_EP1FIFO_FIFO1_POSE) + +#define USB_EP2FIFO_FIFO2_POSS 0U +#define USB_EP2FIFO_FIFO2_POSE 7U +#define USB_EP2FIFO_FIFO2_MSK BITS(USB_EP2FIFO_FIFO2_POSS,USB_EP2FIFO_FIFO2_POSE) + +#define USB_EP3FIFO_FIFO3_POSS 0U +#define USB_EP3FIFO_FIFO3_POSE 7U +#define USB_EP3FIFO_FIFO3_MSK BITS(USB_EP3FIFO_FIFO3_POSS,USB_EP3FIFO_FIFO3_POSE) + +#define USB_EP4FIFO_FIFO4_POSS 0U +#define USB_EP4FIFO_FIFO4_POSE 7U +#define USB_EP4FIFO_FIFO4_MSK BITS(USB_EP4FIFO_FIFO4_POSS,USB_EP4FIFO_FIFO4_POSE) + +#define USB_EP5FIFO_FIFO5_POSS 0U +#define USB_EP5FIFO_FIFO5_POSE 7U +#define USB_EP5FIFO_FIFO5_MSK BITS(USB_EP5FIFO_FIFO5_POSS,USB_EP5FIFO_FIFO5_POSE) + +#define USB_EP6FIFO_FIFO6_POSS 0U +#define USB_EP6FIFO_FIFO6_POSE 7U +#define USB_EP6FIFO_FIFO6_MSK BITS(USB_EP6FIFO_FIFO6_POSS,USB_EP6FIFO_FIFO6_POSE) + +#define USB_EPxFIFO_FIFOx_POSS 0U +#define USB_EPxFIFO_FIFOx_POSE 7U +#define USB_EPxFIFO_FIFOx_MSK BITS(USB_EPxFIFO_FIFOx_POSS,USB_EPxFIFO_FIFOx_POSE) + +/****************** Bit definition for USB_TXIER register ************************/ + +#define USB_TXIER_EP6IE_POS 6U +#define USB_TXIER_EP6IE_MSK BIT(USB_TXIER_EP6IE_POS) + +#define USB_TXIER_EP5IE_POS 5U +#define USB_TXIER_EP5IE_MSK BIT(USB_TXIER_EP5IE_POS) + +#define USB_TXIER_EP4IE_POS 4U +#define USB_TXIER_EP4IE_MSK BIT(USB_TXIER_EP4IE_POS) + +#define USB_TXIER_EP3IE_POS 3U +#define USB_TXIER_EP3IE_MSK BIT(USB_TXIER_EP3IE_POS) + +#define USB_TXIER_EP2IE_POS 2U +#define USB_TXIER_EP2IE_MSK BIT(USB_TXIER_EP2IE_POS) + +#define USB_TXIER_EP1IE_POS 1U +#define USB_TXIER_EP1IE_MSK BIT(USB_TXIER_EP1IE_POS) + +#define USB_TXIER_EP0IE_POS 0U +#define USB_TXIER_EP0IE_MSK BIT(USB_TXIER_EP0IE_POS) + +/****************** Bit definition for USB_RXIER register ************************/ + +#define USB_RXIER_EP6IE_POS 6U +#define USB_RXIER_EP6IE_MSK BIT(USB_RXIER_EP6IE_POS) + +#define USB_RXIER_EP5IE_POS 5U +#define USB_RXIER_EP5IE_MSK BIT(USB_RXIER_EP5IE_POS) + +#define USB_RXIER_EP4IE_POS 4U +#define USB_RXIER_EP4IE_MSK BIT(USB_RXIER_EP4IE_POS) + +#define USB_RXIER_EP3IE_POS 3U +#define USB_RXIER_EP3IE_MSK BIT(USB_RXIER_EP3IE_POS) + +#define USB_RXIER_EP2IE_POS 2U +#define USB_RXIER_EP2IE_MSK BIT(USB_RXIER_EP2IE_POS) + +#define USB_RXIER_EP1IE_POS 1U +#define USB_RXIER_EP1IE_MSK BIT(USB_RXIER_EP1IE_POS) + +/****************** Bit definition for USB_TXIDR register ************************/ + +#define USB_TXIDR_EP6ID_POS 6U +#define USB_TXIDR_EP6ID_MSK BIT(USB_TXIDR_EP6ID_POS) + +#define USB_TXIDR_EP5ID_POS 5U +#define USB_TXIDR_EP5ID_MSK BIT(USB_TXIDR_EP5ID_POS) + +#define USB_TXIDR_EP4ID_POS 4U +#define USB_TXIDR_EP4ID_MSK BIT(USB_TXIDR_EP4ID_POS) + +#define USB_TXIDR_EP3ID_POS 3U +#define USB_TXIDR_EP3ID_MSK BIT(USB_TXIDR_EP3ID_POS) + +#define USB_TXIDR_EP2ID_POS 2U +#define USB_TXIDR_EP2ID_MSK BIT(USB_TXIDR_EP2ID_POS) + +#define USB_TXIDR_EP1ID_POS 1U +#define USB_TXIDR_EP1ID_MSK BIT(USB_TXIDR_EP1ID_POS) + +#define USB_TXIDR_EP0ID_POS 0U +#define USB_TXIDR_EP0ID_MSK BIT(USB_TXIDR_EP0ID_POS) + +/****************** Bit definition for USB_RXIDR register ************************/ + +#define USB_RXIDR_EP6ID_POS 6U +#define USB_RXIDR_EP6ID_MSK BIT(USB_RXIDR_EP6ID_POS) + +#define USB_RXIDR_EP5ID_POS 5U +#define USB_RXIDR_EP5ID_MSK BIT(USB_RXIDR_EP5ID_POS) + +#define USB_RXIDR_EP4ID_POS 4U +#define USB_RXIDR_EP4ID_MSK BIT(USB_RXIDR_EP4ID_POS) + +#define USB_RXIDR_EP3ID_POS 3U +#define USB_RXIDR_EP3ID_MSK BIT(USB_RXIDR_EP3ID_POS) + +#define USB_RXIDR_EP2ID_POS 2U +#define USB_RXIDR_EP2ID_MSK BIT(USB_RXIDR_EP2ID_POS) + +#define USB_RXIDR_EP1ID_POS 1U +#define USB_RXIDR_EP1ID_MSK BIT(USB_RXIDR_EP1ID_POS) + +/****************** Bit definition for USB_TXIVS register ************************/ + +#define USB_TXIVS_EP6IVS_POS 6U +#define USB_TXIVS_EP6IVS_MSK BIT(USB_TXIVS_EP6IVS_POS) + +#define USB_TXIVS_EP5IVS_POS 5U +#define USB_TXIVS_EP5IVS_MSK BIT(USB_TXIVS_EP5IVS_POS) + +#define USB_TXIVS_EP4IVS_POS 4U +#define USB_TXIVS_EP4IVS_MSK BIT(USB_TXIVS_EP4IVS_POS) + +#define USB_TXIVS_EP3IVS_POS 3U +#define USB_TXIVS_EP3IVS_MSK BIT(USB_TXIVS_EP3IVS_POS) + +#define USB_TXIVS_EP2IVS_POS 2U +#define USB_TXIVS_EP2IVS_MSK BIT(USB_TXIVS_EP2IVS_POS) + +#define USB_TXIVS_EP1IVS_POS 1U +#define USB_TXIVS_EP1IVS_MSK BIT(USB_TXIVS_EP1IVS_POS) + +#define USB_TXIVS_EP0IVS_POS 0U +#define USB_TXIVS_EP0IVS_MSK BIT(USB_TXIVS_EP0IVS_POS) + +/****************** Bit definition for USB_RXIVS register ************************/ + +#define USB_RXIVS_EP6IVS_POS 6U +#define USB_RXIVS_EP6IVS_MSK BIT(USB_RXIVS_EP6IVS_POS) + +#define USB_RXIVS_EP5IVS_POS 5U +#define USB_RXIVS_EP5IVS_MSK BIT(USB_RXIVS_EP5IVS_POS) + +#define USB_RXIVS_EP4IVS_POS 4U +#define USB_RXIVS_EP4IVS_MSK BIT(USB_RXIVS_EP4IVS_POS) + +#define USB_RXIVS_EP3IVS_POS 3U +#define USB_RXIVS_EP3IVS_MSK BIT(USB_RXIVS_EP3IVS_POS) + +#define USB_RXIVS_EP2IVS_POS 2U +#define USB_RXIVS_EP2IVS_MSK BIT(USB_RXIVS_EP2IVS_POS) + +#define USB_RXIVS_EP1IVS_POS 1U +#define USB_RXIVS_EP1IVS_MSK BIT(USB_RXIVS_EP1IVS_POS) + +/****************** Bit definition for USB_TXRIF register ************************/ + +#define USB_TXRIF_EP6RIF_POS 6U +#define USB_TXRIF_EP6RIF_MSK BIT(USB_TXRIF_EP6RIF_POS) + +#define USB_TXRIF_EP5RIF_POS 5U +#define USB_TXRIF_EP5RIF_MSK BIT(USB_TXRIF_EP5RIF_POS) + +#define USB_TXRIF_EP4RIF_POS 4U +#define USB_TXRIF_EP4RIF_MSK BIT(USB_TXRIF_EP4RIF_POS) + +#define USB_TXRIF_EP3RIF_POS 3U +#define USB_TXRIF_EP3RIF_MSK BIT(USB_TXRIF_EP3RIF_POS) + +#define USB_TXRIF_EP2RIF_POS 2U +#define USB_TXRIF_EP2RIF_MSK BIT(USB_TXRIF_EP2RIF_POS) + +#define USB_TXRIF_EP1RIF_POS 1U +#define USB_TXRIF_EP1RIF_MSK BIT(USB_TXRIF_EP1RIF_POS) + +#define USB_TXRIF_EP0RIF_POS 0U +#define USB_TXRIF_EP0RIF_MSK BIT(USB_TXRIF_EP0RIF_POS) + +/****************** Bit definition for USB_RXRIF register ************************/ + +#define USB_RXRIF_EP6RIF_POS 6U +#define USB_RXRIF_EP6RIF_MSK BIT(USB_RXRIF_EP6RIF_POS) + +#define USB_RXRIF_EP5RIF_POS 5U +#define USB_RXRIF_EP5RIF_MSK BIT(USB_RXRIF_EP5RIF_POS) + +#define USB_RXRIF_EP4RIF_POS 4U +#define USB_RXRIF_EP4RIF_MSK BIT(USB_RXRIF_EP4RIF_POS) + +#define USB_RXRIF_EP3RIF_POS 3U +#define USB_RXRIF_EP3RIF_MSK BIT(USB_RXRIF_EP3RIF_POS) + +#define USB_RXRIF_EP2RIF_POS 2U +#define USB_RXRIF_EP2RIF_MSK BIT(USB_RXRIF_EP2RIF_POS) + +#define USB_RXRIF_EP1RIF_POS 1U +#define USB_RXRIF_EP1RIF_MSK BIT(USB_RXRIF_EP1RIF_POS) + +/****************** Bit definition for USB_TXIFM register ************************/ + +#define USB_TXIFM_EP6IFM_POS 6U +#define USB_TXIFM_EP6IFM_MSK BIT(USB_TXIFM_EP6IFM_POS) + +#define USB_TXIFM_EP5IFM_POS 5U +#define USB_TXIFM_EP5IFM_MSK BIT(USB_TXIFM_EP5IFM_POS) + +#define USB_TXIFM_EP4IFM_POS 4U +#define USB_TXIFM_EP4IFM_MSK BIT(USB_TXIFM_EP4IFM_POS) + +#define USB_TXIFM_EP3IFM_POS 3U +#define USB_TXIFM_EP3IFM_MSK BIT(USB_TXIFM_EP3IFM_POS) + +#define USB_TXIFM_EP2IFM_POS 2U +#define USB_TXIFM_EP2IFM_MSK BIT(USB_TXIFM_EP2IFM_POS) + +#define USB_TXIFM_EP1IFM_POS 1U +#define USB_TXIFM_EP1IFM_MSK BIT(USB_TXIFM_EP1IFM_POS) + +#define USB_TXIFM_EP0IFM_POS 0U +#define USB_TXIFM_EP0IFM_MSK BIT(USB_TXIFM_EP0IFM_POS) + +/****************** Bit definition for USB_RXIFM register ************************/ + +#define USB_RXIFM_EP6IFM_POS 6U +#define USB_RXIFM_EP6IFM_MSK BIT(USB_RXIFM_EP6IFM_POS) + +#define USB_RXIFM_EP5IFM_POS 5U +#define USB_RXIFM_EP5IFM_MSK BIT(USB_RXIFM_EP5IFM_POS) + +#define USB_RXIFM_EP4IFM_POS 4U +#define USB_RXIFM_EP4IFM_MSK BIT(USB_RXIFM_EP4IFM_POS) + +#define USB_RXIFM_EP3IFM_POS 3U +#define USB_RXIFM_EP3IFM_MSK BIT(USB_RXIFM_EP3IFM_POS) + +#define USB_RXIFM_EP2IFM_POS 2U +#define USB_RXIFM_EP2IFM_MSK BIT(USB_RXIFM_EP2IFM_POS) + +#define USB_RXIFM_EP1IFM_POS 1U +#define USB_RXIFM_EP1IFM_MSK BIT(USB_RXIFM_EP1IFM_POS) + +/****************** Bit definition for USB_TXICR register ************************/ + +#define USB_TXICR_EP6ICR_POS 6U +#define USB_TXICR_EP6ICR_MSK BIT(USB_TXICR_EP6ICR_POS) + +#define USB_TXICR_EP5ICR_POS 5U +#define USB_TXICR_EP5ICR_MSK BIT(USB_TXICR_EP5ICR_POS) + +#define USB_TXICR_EP4ICR_POS 4U +#define USB_TXICR_EP4ICR_MSK BIT(USB_TXICR_EP4ICR_POS) + +#define USB_TXICR_EP3ICR_POS 3U +#define USB_TXICR_EP3ICR_MSK BIT(USB_TXICR_EP3ICR_POS) + +#define USB_TXICR_EP2ICR_POS 2U +#define USB_TXICR_EP2ICR_MSK BIT(USB_TXICR_EP2ICR_POS) + +#define USB_TXICR_EP1ICR_POS 1U +#define USB_TXICR_EP1ICR_MSK BIT(USB_TXICR_EP1ICR_POS) + +#define USB_TXICR_EP0ICR_POS 0U +#define USB_TXICR_EP0ICR_MSK BIT(USB_TXICR_EP0ICR_POS) + +/****************** Bit definition for USB_RXICR register ************************/ + +#define USB_RXICR_EP6ICR_POS 6U +#define USB_RXICR_EP6ICR_MSK BIT(USB_RXICR_EP6ICR_POS) + +#define USB_RXICR_EP5ICR_POS 5U +#define USB_RXICR_EP5ICR_MSK BIT(USB_RXICR_EP5ICR_POS) + +#define USB_RXICR_EP4ICR_POS 4U +#define USB_RXICR_EP4ICR_MSK BIT(USB_RXICR_EP4ICR_POS) + +#define USB_RXICR_EP3ICR_POS 3U +#define USB_RXICR_EP3ICR_MSK BIT(USB_RXICR_EP3ICR_POS) + +#define USB_RXICR_EP2ICR_POS 2U +#define USB_RXICR_EP2ICR_MSK BIT(USB_RXICR_EP2ICR_POS) + +#define USB_RXICR_EP1ICR_POS 1U +#define USB_RXICR_EP1ICR_MSK BIT(USB_RXICR_EP1ICR_POS) + +/****************** Bit definition for USB_IER register ************************/ + +/* device/host mode */ +#define USB_IER_SESREQIE_POS 6U +#define USB_IER_SESREQIE_MSK BIT(USB_IER_SESREQIE_POS) + +#define USB_IER_DISCONIE_POS 5U +#define USB_IER_DISCONIE_MSK BIT(USB_IER_DISCONIE_POS) + +/* host mode */ +#define USB_IER_CONIE_POS 4U +#define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS) + +/* device/host mode */ +#define USB_IER_SOFIE_POS 3U +#define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS) + +/* device mode */ +#define USB_IER_RESTIE_POS 2U +#define USB_IER_RESTIE_MSK BIT(USB_IER_RESTIE_POS) + +/* host mode */ +#define USB_IER_BABIE_POS 2U +#define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS) + +/* device/host mode */ +#define USB_IER_RESIE_POS 1U +#define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS) + +#define USB_IER_SUSPDIE_POS 0U +#define USB_IER_SUSPDIE_MSK BIT(USB_IER_SUSPDIE_POS) + +/****************** Bit definition for USB_IDR register ************************/ + +/* device/host mode */ +#define USB_IDR_SESREQID_POS 6U +#define USB_IDR_SESREQID_MSK BIT(USB_IDR_SESREQID_POS) + +#define USB_IDR_DISCONID_POS 5U +#define USB_IDR_DISCONID_MSK BIT(USB_IDR_DISCONID_POS) + +/* host mode */ +#define USB_IDR_CONID_POS 4U +#define USB_IDR_CONID_MSK BIT(USB_IDR_CONID_POS) + +/* device/host mode */ +#define USB_IDR_SOFID_POS 3U +#define USB_IDR_SOFID_MSK BIT(USB_IDR_SOFID_POS) + +/* device mode */ +#define USB_IDR_RESTID_POS 2U +#define USB_IDR_RESTID_MSK BIT(USB_IDR_RESTID_POS) + +/* host mode */ +#define USB_IDR_BABID_POS 2U +#define USB_IDR_BABID_MSK BIT(USB_IDR_BABID_POS) + +/* device/host mode */ +#define USB_IDR_RESID_POS 1U +#define USB_IDR_RESID_MSK BIT(USB_IDR_RESID_POS) + +#define USB_IDR_SUSPDID_POS 0U +#define USB_IDR_SUSPDID_MSK BIT(USB_IDR_SUSPDID_POS) + +/****************** Bit definition for USB_IVS register ************************/ + +/* device/host mode */ +#define USB_IVS_SESREQIVS_POS 6U +#define USB_IVS_SESREQIVS_MSK BIT(USB_IVS_SESREQIVS_POS) + +#define USB_IVS_DISCONIVS_POS 5U +#define USB_IVS_DISCONIVS_MSK BIT(USB_IVS_DISCONIVS_POS) + +/* host mode */ +#define USB_IVS_CONIVS_POS 4U +#define USB_IVS_CONIVS_MSK BIT(USB_IVS_CONIVS_POS) + +/* device/host mode */ +#define USB_IVS_SOFIVS_POS 3U +#define USB_IVS_SOFIVS_MSK BIT(USB_IVS_SOFIVS_POS) + +/* device mode */ +#define USB_IVS_RESTIVS_POS 2U +#define USB_IVS_RESTIVS_MSK BIT(USB_IVS_RESTIVS_POS) + +/* host mode */ +#define USB_IVS_BABIVS_POS 2U +#define USB_IVS_BABIVS_MSK BIT(USB_IVS_BABIVS_POS) + +/* device/host mode */ +#define USB_IVS_RESIVS_POS 1U +#define USB_IVS_RESIVS_MSK BIT(USB_IVS_RESIVS_POS) + +#define USB_IVS_SUSPDIVS_POS 0U +#define USB_IVS_SUSPDIVS_MSK BIT(USB_IVS_SUSPDIVS_POS) + +/****************** Bit definition for USB_RIF register ************************/ + +/* device/host mode */ +#define USB_RIF_SESREQRIF_POS 6U +#define USB_RIF_SESREQRIF_MSK BIT(USB_RIF_SESREQRIF_POS) + +#define USB_RIF_DISCONRIF_POS 5U +#define USB_RIF_DISCONRIF_MSK BIT(USB_RIF_DISCONRIF_POS) + +/* host mode */ +#define USB_RIF_CONRIF_POS 4U +#define USB_RIF_CONRIF_MSK BIT(USB_RIF_CONRIF_POS) + +/* device/host mode */ +#define USB_RIF_SOFRIF_POS 3U +#define USB_RIF_SOFRIF_MSK BIT(USB_RIF_SOFRIF_POS) + +/* device mode */ +#define USB_RIF_RESTRIF_POS 2U +#define USB_RIF_RESTRIF_MSK BIT(USB_RIF_RESTRIF_POS) + +/* host mode */ +#define USB_RIF_BABRIF_POS 2U +#define USB_RIF_BABRIF_MSK BIT(USB_RIF_BABRIF_POS) + +/* device/host mode */ +#define USB_RIF_RESRIF_POS 1U +#define USB_RIF_RESRIF_MSK BIT(USB_RIF_RESRIF_POS) + +#define USB_RIF_SUSPDRIF_POS 0U +#define USB_RIF_SUSPDRIF_MSK BIT(USB_RIF_SUSPDRIF_POS) + +/****************** Bit definition for USB_IFM register ************************/ + +/* device/host mode */ +#define USB_IFM_SESREQIFM_POS 6U +#define USB_IFM_SESREQIFM_MSK BIT(USB_IFM_SESREQIFM_POS) + +#define USB_IFM_DISCONIFM_POS 5U +#define USB_IFM_DISCONIFM_MSK BIT(USB_IFM_DISCONIFM_POS) + +/* host mode */ +#define USB_IFM_CONIFM_POS 4U +#define USB_IFM_CONIFM_MSK BIT(USB_IFM_CONIFM_POS) + +/* device/host mode */ +#define USB_IFM_SOFIFM_POS 3U +#define USB_IFM_SOFIFM_MSK BIT(USB_IFM_SOFIFM_POS) + +/* device mode */ +#define USB_IFM_RESTIFM_POS 2U +#define USB_IFM_RESTIFM_MSK BIT(USB_IFM_RESTIFM_POS) + +/* host mode */ +#define USB_IFM_BABIFM_POS 2U +#define USB_IFM_BABIFM_MSK BIT(USB_IFM_BABIFM_POS) + +/* device/host mode */ +#define USB_IFM_RESIFM_POS 1U +#define USB_IFM_RESIFM_MSK BIT(USB_IFM_RESIFM_POS) + +#define USB_IFM_SUSPDIFM_POS 0U +#define USB_IFM_SUSPDIFM_MSK BIT(USB_IFM_SUSPDIFM_POS) + +/****************** Bit definition for USB_ICR register ************************/ + +/* device/host mode */ +#define USB_ICR_SESREQICR_POS 6U +#define USB_ICR_SESREQICR_MSK BIT(USB_ICR_SESREQICR_POS) + +#define USB_ICR_DISCONICR_POS 5U +#define USB_ICR_DISCONICR_MSK BIT(USB_ICR_DISCONICR_POS) + +/* host mode */ +#define USB_ICR_CONICR_POS 4U +#define USB_ICR_CONICR_MSK BIT(USB_ICR_CONICR_POS) + +/* device/host mode */ +#define USB_ICR_SOFICR_POS 3U +#define USB_ICR_SOFICR_MSK BIT(USB_ICR_SOFICR_POS) + +/* device mode */ +#define USB_ICR_RESTICR_POS 2U +#define USB_ICR_RESTICR_MSK BIT(USB_ICR_RESTICR_POS) + +/* host mode */ +#define USB_ICR_BABICR_POS 2U +#define USB_ICR_BABICR_MSK BIT(USB_ICR_BABICR_POS) + +/* device/host mode */ +#define USB_ICR_RESICR_POS 1U +#define USB_ICR_RESICR_MSK BIT(USB_ICR_RESICR_POS) + +#define USB_ICR_SUSPDICR_POS 0U +#define USB_ICR_SUSPDICR_MSK BIT(USB_ICR_SUSPDICR_POS) + +typedef struct +{ + __IO uint8_t FADDR ; //0x0000 Function address register. + __IO uint8_t POWER ; //0x0001 Power management register. + __IO uint8_t DPDMCON ; //0x0002 DP DM Control register. + __IO uint8_t SWCID ; //0x0003 Softwave CID register. + __IO uint8_t SWVBUS ; //0x0004 Softwave VBUS register. + __IO uint8_t TMODE ; //0x0005 Test Mode register. + __IO uint8_t RES002[6] ; //0x0006~0x0B, Reserved + __IO uint8_t FRAME1 ; //0x000C, Frame number bits 0 to 7. + __IO uint8_t FRAME2 ; //0x000D, Frame number bits 8 to 10. + __IO uint8_t INDEX ; //0x000E, Index register for selecting the endp + __IO uint8_t DEVCON ; //0x000F, USB device control register. + __IO uint8_t TXMAXP ; //0x0010, Peripheral mode - Maximum packet size + __IO uint8_t CSR0L_TXCSRL ;//0x0011, Peripheral mode - Control Status regi + __IO uint8_t CSR0H_TXCSRH ;//0x0012, Peripheral mode - Control Status regi + __IO uint8_t RXMAXP ; //0x0013, Peripheral mode - Maximum packet size + __IO uint8_t RXCSRL ; //0x0014, Peripheral mode - Control Status regi + __IO uint8_t RXCSRH ; //0x0015, Peripheral mode - Control Status regi + __IO uint8_t COUNT0_RX1 ; //0x0016, Peripheral mode - Number of bytes in + __IO uint8_t RXCOUNT2 ; //0x0017, Peripheral mode - Number of bytes in + __IO uint8_t TXTYPE ; //0x0018, Peripheral mode - // + __IO uint8_t NAKLIMIT0_TXINTERVAL ; //0x0019, Peripheral mode - // + __IO uint8_t RXTYPE ; //0x001A, Peripheral mode - // + __IO uint8_t RXINTERVAL ; //0x001B, Peripheral mode - // + __IO uint8_t TXFIFO1 ; //0x001C, Tx Endpoint FIFO details + __IO uint8_t TXFIFO2 ; //0x001D, Tx Endpoint FIFO details + __IO uint8_t RXFIFO1 ; //0x001E, Rx Endpoint FIFO details + __IO uint8_t RXFIFO2 ; //0x001F, Rx Endpoint FIFO details + __IO uint8_t EP0FIFO ; //0x0020, FIFOs for Endpoints 0. + __IO uint8_t RES021[3] ; //0x0021~0x23, Reserved + __IO uint8_t EP1FIFO ; //0x0024, FIFOs for Endpoints 1. + __IO uint8_t RES025[3] ; //0x0025~0x27, Reserved + __IO uint8_t EP2FIFO ; //0x0028, FIFOs for Endpoints 2. + __IO uint8_t RES029[3] ; //0x0029~0x2B, Reserved + __IO uint8_t EP3FIFO ; //0x002C, FIFOs for Endpoints 3. + __IO uint8_t RES02D[3] ; //0x002D~0x2F, Reserved + __IO uint8_t EP4FIFO ; //0x0030, FIFOs for Endpoints 4. + __IO uint8_t RES031[3] ; //0x0031~0x33, Reserved + __IO uint8_t EP5FIFO ; //0x0034, FIFOs for Endpoints 5. + __IO uint8_t RES035[3] ; //0x0035~0x37, Reserved + __IO uint8_t EP6FIFO ; //0x0038, FIFOs for Endpoints 6. + __IO uint8_t RES039[71] ; //0x0039~0x7C, Reserved + __IO uint8_t TXIER ; //0x0080, TX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES081 ; //0x0081, Reserved + __IO uint8_t RXIER ; //0x0082, RX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES083 ; //0x0083, Reserved + __IO uint8_t TXIDR ; //0x0084, TX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES085 ; //0x0085, Reserved + __IO uint8_t RXIDR ; //0x0086, RX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES087 ; //0x0087, Reserved + __IO uint8_t TXIVS ; //0x0088, TX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES089 ; //0x0089, Reserved + __IO uint8_t RXIVS ; //0x008A, RX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES08B ; //0x008B, Reserved + __IO uint8_t TXRIF ; //0x008C, TX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08D ; //0x008D, Reserved + __IO uint8_t RXRIF ; //0x008E, RX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08F ; //0x008F, Reserved + __IO uint8_t TXIFM ; //0x0090, TX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES091 ; //0x0091, Reserved + __IO uint8_t RXIFM ; //0x0092, RX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES093 ; //0x0093, Reserved + __IO uint8_t TXICR ; //0x0094, TX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES095 ; //0x0095, Reserved + __IO uint8_t RXICR ; //0x0096, RX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES097[9] ; //0x0097~0x9C, Reserved + __O uint32_t IER ; //0x00A0, USB Interrupt Enable Register + __O uint32_t IDR ; //0x00A4, USB Interrupt Disable Register + __I uint32_t IVS ; //0x00A8, USB Interrupt Valid Register + __I uint32_t RIF ; //0x00AC, USB Raw Interrupt Flag Status Register + __I uint32_t IFM ; //0x00B0, USB Interrupt Flag Masked Status + __O uint32_t ICR ; //0x00B4, USB Interrupt Clear Register +} USB_TypeDef; + + +#endif diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_wwdt.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_wwdt.h new file mode 100644 index 0000000000..a38bb02b4a --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/reg_wwdt.h @@ -0,0 +1,98 @@ +/********************************************************************************** + * + * @file reg_wwdt.h + * @brief WWDT Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_WWDT_H__ +#define __REG_WWDT_H__ + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} WWDT_TypeDef; + + + + + +#endif /* __REG_WWDT_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/es32vf2264.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/es32vf2264.h new file mode 100644 index 0000000000..c9a050019e --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/es32vf2264.h @@ -0,0 +1,177 @@ +/********************************************************************************** + * + * @file es32vf2264.h + * @brief ES32VF2264 Head File + * + * @date 13 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __ES32VF2264_H__ +#define __ES32VF2264_H__ + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + + +typedef enum IRQn +{ + /* ES32VF2264 specific Interrupt Numbers */ + MACHINE_MODE_SOFT_IRQn =3 , // 12 + CLINT_IRQn =7 , // 28 + MACHINE_MODE_EXTERNAL_IRQn =11 , // 44 //no used in m602@20200218 + WWDT_IRQn =16 , // 0 64 + IWDT_IRQn =17 , // 1 68 + LVD_IRQn =18 , // 2 72 + CSU_IRQn =19 , // 3 + CMU_IRQn =20 , // 4 80 + EXTI0_3_IRQn =21 , // 5 84 + EXTI4_7_IRQn =22 , // 6 88 + EXTI8_11_IRQn =23 , // 7 92 + EXTI12_15_IRQn =24 , // 8 96 + DMA_IRQn =25 , // 9 100 + USB_IRQn =27 , // 11 108 + ADC_IRQn =28 , // 12 112 + AD16C4T_UP_TRIG_COM_IRQn =29 , // 13 116 + AD16C4T_CC_IRQn =30 , // 14 120 + BSTIM0_IRQn =31 , // 15 124 + GPTIMB0_IRQn =33 , // 17 132 + GPTIMB1_IRQn =34 , // 18 136 + GPTIMB2_IRQn =35 , // 19 140 + AD16C4T_IRQn =37 , // 21 148 + I2C0_IRQn =39 , // 23 156 + I2C1_IRQn =40 , // 24 + SPI0_I2S0_IRQn =41 , // 25 164 + SPI1_I2S1_IRQn =42 , // 26 + EUART0_IRQn =43 , // 27 + EUART1_IRQn =44 , // 28 + CUART0_IRQn =45 , // 29 180 + CUART1_IRQn =46 , // 30 184 + CUART2_IRQn =47 , // 31 188 +} IRQn_Type; + +#include +#include "core_rv32.h" + +#include "./ES32VF2264/reg_adc.h" +#include "./ES32VF2264/reg_cmu.h" +#include "./ES32VF2264/reg_crc.h" +#include "./ES32VF2264/reg_csu.h" +#include "./ES32VF2264/reg_dbg.h" +#include "./ES32VF2264/reg_dma.h" +#include "./ES32VF2264/reg_gpio.h" +#include "./ES32VF2264/reg_i2c.h" +#include "./ES32VF2264/reg_iwdt.h" +#include "./ES32VF2264/reg_msc.h" +#include "./ES32VF2264/reg_pis.h" +#include "./ES32VF2264/reg_pmu.h" +#include "./ES32VF2264/reg_rmu.h" +#include "./ES32VF2264/reg_spi.h" +#include "./ES32VF2264/reg_syscfg.h" +#include "./ES32VF2264/reg_timer.h" +#include "./ES32VF2264/reg_uart.h" +#include "./ES32VF2264/reg_wwdt.h" +#include "./ES32VF2264/reg_usb.h" + +#define SRAM_BASE (0x20000000UL) +#define APB_BASE (0x40000000UL) +#define AHB_BASE (0x40080000UL) + +#define SYSCFG_BASE (AHB_BASE + 0x0000) +#define CMU_BASE (AHB_BASE + 0x0400) +#define RMU_BASE (AHB_BASE + 0x0800) +#define PMU_BASE (AHB_BASE + 0x0C00) +#define MSC_BASE (AHB_BASE + 0x1000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define DMA_BASE (AHB_BASE + 0x5400) +#define CSU_BASE (AHB_BASE + 0x5C00) +#define PIS_BASE (AHB_BASE + 0x6000) +#define USB_BASE (AHB_BASE + 0x6400) + +#define AD16C4T_BASE (APB_BASE + 0x0000) +#define BS16T_BASE (APB_BASE + 0x0400) +#define GP16C4T0_BASE (APB_BASE + 0x0800) +#define GP16C4T1_BASE (APB_BASE + 0x0C00) +#define GP16C4T2_BASE (APB_BASE + 0x1000) +#define EUART0_BASE (APB_BASE + 0x4000) +#define EUART1_BASE (APB_BASE + 0x4400) +#define CUART0_BASE (APB_BASE + 0x5000) +#define CUART1_BASE (APB_BASE + 0x5400) +#define CUART2_BASE (APB_BASE + 0x5800) +#define SPI0_I2S0_BASE (APB_BASE + 0x6000) +#define SPI1_I2S1_BASE (APB_BASE + 0x6400) +#define I2C0_BASE (APB_BASE + 0x8000) +#define I2C1_BASE (APB_BASE + 0x8400) +#define WWDT_BASE (APB_BASE + 0x8800) +#define IWDT_BASE (APB_BASE + 0x8C00) +#define DBGC_BASE (APB_BASE + 0x9000) +#define ADC_BASE (APB_BASE + 0x9400) +#define DMA_MUX_BASE (APB_BASE + 0xD000) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define CMU ((CMU_TypeDef *) CMU_BASE) +#define RMU ((RMU_TypeDef *) RMU_BASE) +#define PMU ((PMU_TypeDef *) PMU_BASE) +#define MSC ((MSC_TypeDef *) MSC_BASE ) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define PIS ((PIS_TypeDef *) PIS_BASE) +#define AD16C4T ((TIMER_TypeDef *) AD16C4T_BASE) +#define BS16T ((TIMER_TypeDef *) BS16T_BASE) +#define GP16C4T0 ((TIMER_TypeDef *) GP16C4T0_BASE) +#define GP16C4T1 ((TIMER_TypeDef *) GP16C4T1_BASE) +#define GP16C4T2 ((TIMER_TypeDef *) GP16C4T2_BASE) +#define EUART0 ((UART_TypeDef *) EUART0_BASE) +#define EUART1 ((UART_TypeDef *) EUART1_BASE) +#define CUART0 ((UART_TypeDef *) CUART0_BASE) +#define CUART1 ((UART_TypeDef *) CUART1_BASE) +#define CUART2 ((UART_TypeDef *) CUART2_BASE) +#define SPI0 ((SPI_I2S_TypeDef *) SPI0_I2S0_BASE) +#define SPI1 ((SPI_I2S_TypeDef *) SPI1_I2S1_BASE) +#define I2S0 ((SPI_I2S_TypeDef *) SPI0_I2S0_BASE) +#define I2S1 ((SPI_I2S_TypeDef *) SPI1_I2S1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define WWDT ((WWDT_TypeDef *) WWDT_BASE) +#define IWDT ((IWDT_TypeDef *) IWDT_BASE) +#define DBGC ((DBGC_TypeDef *) DBGC_BASE) +#define ADC ((ADC_TypeDef *) ADC_BASE) +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define DMA_MUX ((DMA_MUX_Typedef *) DMA_MUX_BASE) +#define CSU ((CSU_TypeDef *) CSU_BASE) +#define USB ((USB_TypeDef *) USB_BASE) + +#endif /* __ES32VF2264_H__ */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/SConscript b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/SConscript new file mode 100644 index 0000000000..ebcc880fd6 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/SConscript @@ -0,0 +1,26 @@ +from building import * +import esconfig +#1.生成group_startup（对应project里面的startup） +cwd = GetCurrentDir() + +#add *.s file +if esconfig.CROSS_TOOL == 'gcc': + stup = Glob('Startup/*.s') +#elif esconfig.CROSS_TOOL == 'keil': +# stup = Glob('Startup/keil/*.s') +#elif esconfig.CROSS_TOOL == 'iar': +# stup = Glob('Startup/iar/*.s') + + +#add include path,其实startup没有对应的.h文件，但是这里的操作是把内核相关的.h文件以及芯片寄存器的.h文件以及芯片寄存器的.h文件 +#include在魔法棒c/c++里面的include paths里 +include_path = [cwd + '..\..\..\..\Include'] +include_path += [cwd + '/Include', cwd + '/Include/ES32VF2264'] + +#if esconfig.CROSS_TOOL == 'keil': +# include_path += [cwd + '/Startup/keil'] + +group_startup = DefineGroup('startup', stup, depend = [''], CPPPATH = include_path) + +#返回group_startup +Return('group_startup') diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/startup_es32vf2264.S b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/startup_es32vf2264.S new file mode 100644 index 0000000000..13f4b4f291 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/startup_es32vf2264.S @@ -0,0 +1,363 @@ +# define LREG lw +# define SREG sw +# define REGBYTES 4 + +// <<< Use Configuration Wizard in Context Menu >>> + +#define MSTATUS_PRV1 0x1880 + +.global __initial_sp + +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:4> +// Config the stack size for the application +#define StackSize 0x400 + + +.section .app_stack,"aw",@nobits +.align 2 +Stack_Mem: +.space StackSize +__initial_sp: + + +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Config the heap size for the application +#define HeapSize 0x200 + +.global __heap_start +.global __heap_end +.section .bss,"aw",@nobits +.align 2 +Heap_Mem: +__heap_start: +.space HeapSize +__heap_end: + + +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: //#totally 0~63 entries + .rept 3 // + .long 0 // + .endr // + .long SW_handler // ##3 + .rept 3 // + .long 0 // + .endr // + .long CLINT_Handler // ##7 + .rept 3 // + .long 0 // + .endr // + .long MACHINE_MODE_EXTERNAL_Handler // ##11 no used + .rept 4 // ##12~15 reserved + .long 0 // + .endr // + +/* External interrupts */ +//##------------------------------------------------------------ + .long WWDT_Handler // ##16 0 + .long IWDT_Handler // ##17 1 + .long LVD_Handler // ##18 2 + .long CSU_Handler // ##19 3 + .long CMU_Handler // ##20 4 + .long EXTI0_3_Handler // ##21 5 + .long EXTI4_7_Handler // ##22 6 + .long EXTI8_11_Handler // ##23 7 + .long EXTI12_15_Handler // ##24 8 + .long DMA_Handler // ##25 9 + .long 0 // ##26 10 + .long USB_Handler // ##27 11 + .long ADC_Handler // ##28 12 + .long AD16C4T_UP_TRIG_COM_Handler // ##29 13 + .long AD16C4T_CC_Handler // ##30 14 + .long BSTIM0_Handler // ##31 15 + .long 0 // ## 16 + .long GPTIMB0_Handler // ##33 17 + .long GPTIMB1_Handler // ##34 18 + .long GPTIMB2_Handler // ##35 19 + .long 0 // ## 20 + .long AD16C4T_Handler // ##37 21 + .long 0 // ## 22 + .long I2C0_Handler // ##39 23 + .long I2C1_Handler // ##40 24 + .long SPI0_I2S0_Handler // ##41 25 + .long SPI1_I2S1_Handler // ##42 26 + .long EUART0_Handler // ##43 27 + .long EUART1_Handler // ##44 28 + .long CUART0_Handler // ##45 29 + .long CUART1_Handler // ##46 30 + .long CUART2_Handler // ##47 31 +//##--------------------------------------------------- + +/* + * For importing variable or functions from other c or assemble files. + */ +.global __main +.global handle_trap + + .section ".text.init" + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la a0, Default_Handler + ori a0, a0, 3 + csrw mtvec, a0 + + la a0, __Vectors + csrw mtvt, a0 + + la sp, g_top_irqstack + + /* Load data section */ + la a0, __erodata + la a1, __data_start__ + la a2, __data_end__ + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start__ + la a1, __bss_end__ + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + jal entry + + .size Reset_Handler, . - Reset_Handler + + .align 6 + .weak Default_Handler + .global Default_Handler + .type Default_Handler, %function +Default_Handler: + addi sp, sp, -272 + + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + + # Remain in M-mode after eret + li t0, MSTATUS_PRV1 + csrs mstatus, t0 + + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + + addi sp, sp, 272 + mret + + .weak SW_handler + .globl SW_handler + .type SW_handler, %function +SW_handler: + + .weak CLINT_Handler + .globl CLINT_Handler + .type CLINT_Handler, %function +CLINT_Handler: + + .weak MACHINE_MODE_EXTERNAL_Handler + .globl MACHINE_MODE_EXTERNAL_Handler + .type MACHINE_MODE_EXTERNAL_Handler, %function +MACHINE_MODE_EXTERNAL_Handler: + + .weak WWDT_Handler + .globl WWDT_Handler + .type WWDT_Handler, %function +WWDT_Handler: + + .weak IWDT_Handler + .globl IWDT_Handler + .type IWDT_Handler, %function +IWDT_Handler: + + .weak LVD_Handler + .globl LVD_Handler + .type LVD_Handler, %function +LVD_Handler: + + .weak CSU_Handler + .globl CSU_Handler + .type CSU_Handler, %function +CSU_Handler: + + .weak CMU_Handler + .globl CMU_Handler + .type CMU_Handler, %function +CMU_Handler: + + .weak EXTI0_3_Handler + .globl EXTI0_3_Handler + .type EXTI0_3_Handler, %function +EXTI0_3_Handler: + + .weak EXTI4_7_Handler + .globl EXTI4_7_Handler + .type EXTI4_7_Handler, %function +EXTI4_7_Handler: + + .weak EXTI8_11_Handler + .globl EXTI8_11_Handler + .type EXTI8_11_Handler, %function +EXTI8_11_Handler: + + .weak EXTI12_15_Handler + .globl EXTI12_15_Handler + .type EXTI12_15_Handler, %function +EXTI12_15_Handler: + + .weak DMA_Handler + .globl DMA_Handler + .type DMA_Handler, %function +DMA_Handler: + + .weak USB_Handler + .globl USB_Handler + .type USB_Handler, %function +USB_Handler: + + .weak ADC_Handler + .globl ADC_Handler + .type ADC_Handler, %function +ADC_Handler: + + .weak AD16C4T_UP_TRIG_COM_Handler + .globl AD16C4T_UP_TRIG_COM_Handler + .type AD16C4T_UP_TRIG_COM_Handler, %function +AD16C4T_UP_TRIG_COM_Handler: + + .weak AD16C4T_CC_Handler + .globl AD16C4T_CC_Handler + .type AD16C4T_CC_Handler, %function +AD16C4T_CC_Handler: + + .weak BSTIM0_Handler + .globl BSTIM0_Handler + .type BSTIM0_Handler, %function +BSTIM0_Handler: + + .weak GPTIMB0_Handler + .globl GPTIMB0_Handler + .type GPTIMB0_Handler, %function +GPTIMB0_Handler: + + .weak GPTIMB1_Handler + .globl GPTIMB1_Handler + .type GPTIMB1_Handler, %function +GPTIMB1_Handler: + + .weak GPTIMB2_Handler + .globl GPTIMB2_Handler + .type GPTIMB2_Handler, %function +GPTIMB2_Handler: + + .weak AD16C4T_Handler + .globl AD16C4T_Handler + .type AD16C4T_Handler, %function +AD16C4T_Handler: + + .weak I2C0_Handler + .globl I2C0_Handler + .type I2C0_Handler, %function +I2C0_Handler: + + .weak I2C1_Handler + .globl I2C1_Handler + .type I2C1_Handler, %function +I2C1_Handler: + + .weak SPI0_I2S0_Handler + .globl SPI0_I2S0_Handler + .type SPI0_I2S0_Handler, %function +SPI0_I2S0_Handler: + + .weak SPI1_I2S1_Handler + .globl SPI1_I2S1_Handler + .type SPI1_I2S1_Handler, %function +SPI1_I2S1_Handler: + + .weak EUART0_Handler + .globl EUART0_Handler + .type EUART0_Handler, %function +EUART0_Handler: + + .weak EUART1_Handler + .globl EUART1_Handler + .type EUART1_Handler, %function +EUART1_Handler: + + .weak CUART0_Handler + .globl CUART0_Handler + .type CUART0_Handler, %function +CUART0_Handler: + + .weak CUART1_Handler + .globl CUART1_Handler + .type CUART1_Handler, %function +CUART1_Handler: + + .weak CUART2_Handler + .globl CUART2_Handler + .type CUART2_Handler, %function +CUART2_Handler: + +__exit: + j __exit + +//##--------------------------------------------------- +.section .bss + + .align 3 + .global g_base_irqstack + .global g_top_irqstack +g_base_irqstack: + .space StackSize //CONFIG_ARCH_INTERRUPTSTACK +g_top_irqstack: diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/trap_c.c b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/trap_c.c new file mode 100644 index 0000000000..bfc74489b5 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Startup/trap_c.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + +/****************************************************************************** + * @file trap_c.c + * @brief source file for the trap process + * @version V1.0 + * @date 12. December 2017 + ******************************************************************************/ + +#include +#include +#include +#include + +void handle_trap(uint32_t *regs) +{ + while (1); +} diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Svc/es32vf2264.svc b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Svc/es32vf2264.svc new file mode 100644 index 0000000000..7299f7a67a --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Svc/es32vf2264.svc @@ -0,0 +1,3997 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/System/system_es32vf2264.c b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/System/system_es32vf2264.c new file mode 100644 index 0000000000..71d846aa03 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/System/system_es32vf2264.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2022 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file system.c + * @brief CSI Device System Source File + * @version V1.0 + * @date June 27 2022 + ******************************************************************************/ + +#include + +void board_init(void) +{ + + return; + +} + +int fputc(int ch, FILE *stream) +{ + (void)stream; + + return 0; +} + + +void SystemInit(void) +{ + return; +} diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/core_rv32.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/core_rv32.h new file mode 100644 index 0000000000..84d55b0f00 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/core_rv32.h @@ -0,0 +1,1187 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + + +/****************************************************************************** + * @file core_rv32.h + * @brief CSI RV32 Core Peripheral Access Layer Header File + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef __CORE_RV32_H_GENERIC +#define __CORE_RV32_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * CSI definitions + ******************************************************************************/ +/** + \ingroup RV32 + @{ + */ + +#ifndef __RV32 +#define __RV32 (0x01U) +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_GENERIC */ + +#ifndef __CSI_GENERIC + +#ifndef __CORE_RV32_H_DEPENDANT +#define __CORE_RV32_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#ifndef __RV32_REV +#define __RV32_REV 0x0000U +#endif + +#ifndef __VIC_PRIO_BITS +#define __VIC_PRIO_BITS 2U +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 1U +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 1U +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 1U +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 1U +#endif + +#include + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CSI_glob_defs CSI Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group CK802 */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core CLIC Register + ******************************************************************************/ +/** + \defgroup CSI_core_register Defines and Type Definitions + \brief Type definitions and defines for CK80X processor based devices. +*/ + +/** + \ingroup CSI_core_register + \defgroup CSI_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \ingroup CSI_core_register + \defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC) + \brief Type definitions for the CLIC Registers + @{ + */ + +/** + \brief Access to the structure of a vector interrupt controller. + */ +typedef struct { + __IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ + __IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */ + __IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */ + __IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */ +} CLIC_INT_Control; + +typedef struct { + __IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */ + __IM uint32_t CLICINFO; + __IOM uint32_t MINTTHRESH; + uint32_t RESERVED[1021]; + CLIC_INT_Control CLICINT[4096]; +} CLIC_Type; + +#define CLIC_INFO_CLICINTCTLBITS_Pos 21U +#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos) + +#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ +#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ + +#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ +#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ + +#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */ +#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */ + +#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ +#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ + +#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ +#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ + +#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */ +#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */ + +#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */ +#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */ + +#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */ +#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */ + +#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ +#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ + +#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */ +#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */ + +/*@} end of group CSI_CLIC */ + +/** + \ingroup CSI_core_register + \defgroup CSI_PMP Physical Memory Protection (PMP) + \brief Type definitions for the PMP Registers + @{ + */ + +#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */ +#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */ + +#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */ +#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */ + +#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */ +#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */ + +#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */ +#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */ + +#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */ +#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */ + +typedef enum { + REGION_SIZE_4B = -1, + REGION_SIZE_8B = 0, + REGION_SIZE_16B = 1, + REGION_SIZE_32B = 2, + REGION_SIZE_64B = 3, + REGION_SIZE_128B = 4, + REGION_SIZE_256B = 5, + REGION_SIZE_512B = 6, + REGION_SIZE_1KB = 7, + REGION_SIZE_2KB = 8, + REGION_SIZE_4KB = 9, + REGION_SIZE_8KB = 10, + REGION_SIZE_16KB = 11, + REGION_SIZE_32KB = 12, + REGION_SIZE_64KB = 13, + REGION_SIZE_128KB = 14, + REGION_SIZE_256KB = 15, + REGION_SIZE_512KB = 16, + REGION_SIZE_1MB = 17, + REGION_SIZE_2MB = 18, + REGION_SIZE_4MB = 19, + REGION_SIZE_8MB = 20, + REGION_SIZE_16MB = 21, + REGION_SIZE_32MB = 22, + REGION_SIZE_64MB = 23, + REGION_SIZE_128MB = 24, + REGION_SIZE_256MB = 25, + REGION_SIZE_512MB = 26, + REGION_SIZE_1GB = 27, + REGION_SIZE_2GB = 28, + REGION_SIZE_4GB = 29, + REGION_SIZE_8GB = 30, + REGION_SIZE_16GB = 31 +} region_size_e; + +typedef enum { + ADDRESS_MATCHING_NONE = 0, + ADDRESS_MATCHING_TOR = 1, + ADDRESS_MATCHING_NA4 = 2, + ADDRESS_MATCHING_NAPOT = 3 +} address_matching_e; + +typedef struct { + uint32_t r: 1; /* readable enable */ + uint32_t w: 1; /* writeable enable */ + uint32_t x: 1; /* execable enable */ + address_matching_e a: 2; /* address matching mode */ + uint32_t reserved: 2; /* reserved */ + uint32_t l: 1; /* lock enable */ +} mpu_region_attr_t; + +/*@} end of group CSI_PMP */ + +/* CACHE Register Definitions */ +#define CACHE_MHCR_L0BTB_Pos 12U /*!< CACHE MHCR: L0BTB Position */ +#define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */ +#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */ + +#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */ +#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */ + +#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */ +#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */ +#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */ + +#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */ +#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */ + +#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */ +#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */ + +#define CACHE_INV_ADDR_Pos 5U +#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos) + +/*@} end of group CSI_CACHE */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_SysTick System Tick Timer (CORET) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief The data structure of the access system timer. + */ +typedef struct { + __IOM unsigned long long MTIMECMP; /*!< Offset: 0x000 (R/W) Timer compare register */ + uint32_t RESERVED[8187]; + __IM unsigned long long MTIME; /*!< Offset: 0x7FFC (R) Timer current register */ +} CORET_Type; + +/*@} end of group CSI_SysTick */ + +/** + \ingroup CSI_core_register + \defgroup CSI_DCC + \brief Type definitions for the DCC. + @{ + */ + +/** + \brief Access to the data structure of DCC. + */ +typedef struct { + uint32_t RESERVED0[13U]; + __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */ + __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */ + uint32_t RESERVED1[6U]; + union { + __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/ + __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/ + }; + +} DCC_Type; + +#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */ +#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */ + +#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */ +#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */ + +#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */ +#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */ + +#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */ +#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */ + +/*@} end of group CSI_DCC */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CSI_core_bitfield */ + +/** + \ingroup CSI_core_register + \defgroup CSI_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of CK802 Hardware */ +#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */ +#define CORET_BASE (0xE0004000UL) /*!< CORET Base Address */ +#define CLIC_BASE (0xE0800000UL) /*!< CLIC Base Address */ +#define DCC_BASE (0xE4010000UL) /*!< DCC Base Address */ +#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */ + +#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */ +#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */ +#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */ +#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */ + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core VIC Functions + - Core CORET Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference +*/ + +/* ########################## VIC functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_VICFunctions VIC Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) ) +#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +/** + \brief Enable External Interrupt + \details Enable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk; +} + +/** + \brief Disable External Interrupt + \details Disable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk; +} + +/** + \brief Enable External Secure Interrupt + \details Enable a secure device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk); + CLIC->CLICINT[IRQn].ATTR |= CLIC_INTATTR_SHV_Msk; +} + +/** + \brief Disable External Secure Interrupt + \details Disable a secure device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk); +} + +/** + \brief Check Interrupt is Enabled or not + \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not enabled. + \return 1 Interrupt status is enabled. + */ +__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk); +} + +/** + \brief Check Interrupt is Pending or not + \details Read the pending register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk); +} + +/** + \brief Set Pending Interrupt + \details Set the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk; +} + +/** + \brief Clear Pending Interrupt + \details Clear the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk; +} + +/** + \brief Set Interrupt Priority + \details Set the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority) +{ + CLIC->CLICCFG |= 0x6; /* NLBITS = 3 */ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits)); +} + +/** + \brief Get Interrupt Priority + \details Read the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn) +{ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits); +} + +/** + \brief Set interrupt handler + \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors. + \param [in] IRQn Interrupt number. + \param [in] handler Interrupt handler. + */ +__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler) +{ + if (IRQn >= 0 && IRQn < 1024) { + uint32_t *vectors = (uint32_t *)__get_MTVT(); + vectors[IRQn] = handler; + } +} + +/** + \brief Get interrupt handler + \details Get the address of interrupt handler function. + \param [in] IRQn Interrupt number. + */ +__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn) +{ + if (IRQn >= 0 && IRQn < 1024) { + uint32_t *vectors = (uint32_t *)__get_MTVT(); + return (uint32_t)vectors[IRQn]; + } + + return 0; +} + +/*@} end of CSI_Core_VICFunctions */ + +/* ########################## PMP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_PMPFunctions PMP Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/** + \brief configure memory protected region. + \details + \param [in] idx memory protected region (0, 1, 2, ..., 15). + \param [in] base_addr base address must be aligned with page size. + \param [in] size \ref region_size_e. memory protected region size. + \param [in] attr \ref region_size_t. memory protected region attribute. + \param [in] enable enable or disable memory protected region. + */ +__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, + mpu_region_attr_t attr, uint32_t enable) +{ + uint8_t pmpxcfg = 0; + uint32_t addr = 0; + + if (idx > 15) { + return; + } + + if (!enable) { + attr.a = ADDRESS_MATCHING_NONE; + } + + if (attr.a == ADDRESS_MATCHING_TOR) { + addr = base_addr >> 2; + } else { + if (size == REGION_SIZE_4B) { + addr = base_addr >> 2; + attr.a = ADDRESS_MATCHING_NA4; + } else { + addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); + } + } + + __set_PMPADDRx(idx, addr); + + pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) | + (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) | + (attr.l << PMP_PMPCFG_L_Pos); + + __set_PMPxCFG(idx, pmpxcfg); +} + +/** + \brief disable mpu region by idx. + \details + \param [in] idx memory protected region (0, 1, 2, ..., 15). + */ +__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx) +{ + __set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk)); +} + +/*@} end of CSI_Core_PMPFunctions */ + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + + +/** + \brief CORE timer Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \param [in] IRQn core timer Interrupt number. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn) +{ + if (CORET->MTIMECMP) + CORET->MTIMECMP = CORET->MTIMECMP + ticks; + else + CORET->MTIMECMP = CORET->MTIME + ticks; + + return (0UL); +} + +__STATIC_INLINE uint32_t csi_coret_clr(uint32_t ticks, int32_t IRQn) +{ + CORET->MTIMECMP = CORET->MTIME + ticks; + + return (0UL); +} + +/** + \brief get CORE timer reload value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_load(void) +{ + return CORET->MTIMECMP & 0xFFFFFFFF; +} + +/** + \brief get CORE timer reload high value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_loadh(void) +{ + return (CORET->MTIMECMP >> 32) & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_value(void) +{ + return CORET->MTIME & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter high value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_valueh(void) +{ + return (CORET->MTIME >> 32) & 0xFFFFFFFF; +} + +/*@} end of CSI_Core_SysTickFunctions */ + +/* ##################################### DCC function ########################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_core_DebugFunctions HAD Functions + \brief Functions that access the HAD debug interface. + @{ + */ + +/** + \brief HAD Send Character + \details Transmits a character via the HAD channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch) +{ + DCC->DERJR = (uint8_t)ch; + + return (ch); +} + + +/** + \brief HAD Receive Character + \details Inputs a character via the external variable \ref HAD_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t csi_had_receive_char(void) +{ + int32_t ch = -1; /* no character available */ + + if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) { + ch = DCC->DERJW; + } + + return (ch); +} + + +/** + \brief HAD Check Character + \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t csi_had_check_char(void) +{ + return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */ +} + +/*@} end of CSI_core_DebugFunctions */ + + +/* ########################## sleep and Reset functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SleepAndResetFunctions Sleep and Reset Functions + \brief Functions that configure Sleep and Reset. + @{ + */ + + +/* MEXSTATUS Register Definitions */ +#define MEXSTATUS_RESET_Pos 0U +#define MEXSTATUS_RESET_Msk (0x3UL << MEXSTATUS_RESET_Pos) /*!< MEXSTATUS: RESET Position */ +#define MEXSTATUS_SLEEP_Pos 2U +#define MEXSTATUS_SLEEP_Msk (0x3UL << MEXSTATUS_SLEEP_Pos) /*!< MEXSTATUS: RESET Position */ +#define MEXSTATUS_WFE_Pos 4U +#define MEXSTATUS_WFE_Msk (0x1UL << MEXSTATUS_WFE_Pos) + +typedef enum { + MEXSTATUS_RESET_CORE = 1, /* Reset CPU Core, But Not Reset Debug System */ + MEXSTATUS_RESET_CPUSYS = 2 /* Reset CPU Core and Reset Debug System */ +} mexstatus_reset_e; + +typedef enum { + MEXSTATUS_SLEEP_LIGHT = 1, + MEXSTATUS_SLEEP_DEEP = 0 +} mexstatus_sleep_e; + + +/*@} end of group CSI_MEXSTATUS */ + +/** + \brief CPU Reset + \details Triggle CPU Reset + */ +__STATIC_INLINE uint32_t csi_cpu_get_reset_addr (void) +{ + uint32_t result; + result = __get_MRADDR(); + + return result; +} + +/** + \brief CPU Reset + \details Triggle CPU Reset + */ +__STATIC_INLINE void csi_cpu_reset (mexstatus_reset_e reset_mode) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_RESET_Msk)); + mexstatus |= (uint32_t)(reset_mode << MEXSTATUS_RESET_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief CPU Sleep WFI mode + \details Triggle CPU Sleep + */ +__STATIC_INLINE void csi_cpu_sleep_wfi (mexstatus_sleep_e sleep_mode) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_SLEEP_Msk)); + mexstatus &= (~(MEXSTATUS_WFE_Msk)); /* WFI mode */ + mexstatus |= (uint32_t)(sleep_mode << MEXSTATUS_SLEEP_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief CPU Sleep WFE mode + \details Triggle CPU Sleep + */ +__STATIC_INLINE void csi_cpu_sleep_wfe (mexstatus_sleep_e sleep_mode) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_SLEEP_Msk)); + mexstatus |= MEXSTATUS_WFE_Msk; /* WFE mode */ + mexstatus |= (uint32_t)(sleep_mode << MEXSTATUS_SLEEP_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief Get CPU Sleep Status + \details Get CPU Sleep Status + */ +__STATIC_INLINE uint32_t csi_cpu_get_sleep_status (void) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus = (mexstatus_sleep_e)((mexstatus & MEXSTATUS_SLEEP_Msk) >> MEXSTATUS_SLEEP_Pos); + return mexstatus; +} + +/* ########################## Cache functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void csi_icache_enable (void) +{ +#if (__ICACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + __ICACHE_IALL(); + cache = __get_MHCR(); + cache |= CACHE_MHCR_IE_Msk; + __set_MHCR(cache); + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void csi_icache_disable (void) +{ +#if (__ICACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + cache = __get_MHCR(); + cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */ + __set_MHCR(cache); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void csi_icache_invalid (void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + \note I-Cache also turns on. + */ +__STATIC_INLINE void csi_dcache_enable (void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + __DCACHE_IALL(); /* invalidate all dcache */ + cache = __get_MHCR(); + cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */ + __set_MHCR(cache); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + \note I-Cache also turns off. + */ +__STATIC_INLINE void csi_dcache_disable (void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + cache = __get_MHCR(); + cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */ + __set_MHCR(cache); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + \note I-Cache also invalid + */ +__STATIC_INLINE void csi_dcache_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + \note I-Cache also cleans + */ +__STATIC_INLINE void csi_dcache_clean (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_CALL(); /* clean all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + \note I-Cache also flush. + */ +__STATIC_INLINE void csi_dcache_clean_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_CIALL(); /* clean and inv all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_IPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize) +{ + +#if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif + +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 16-byte boundary) + \param[in] dsize size of memory block (aligned to 16-byte boundary) +*/ +__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CIPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + +/** + \brief setup cacheable range Cache + \details setup Cache range + */ +__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable) +{ + ; +} + +/** + \brief Enable cache profile + \details Turns on Cache profile + */ +__STATIC_INLINE void csi_cache_enable_profile (void) +{ + ; +} + +/** + \brief Disable cache profile + \details Turns off Cache profile + */ +__STATIC_INLINE void csi_cache_disable_profile (void) +{ + ; +} + +/** + \brief Reset cache profile + \details Reset Cache profile + */ +__STATIC_INLINE void csi_cache_reset_profile (void) +{ + ; +} + +/** + \brief cache access times + \details Cache access times + \note every 256 access add 1. + \return cache access times, actual times should be multiplied by 256 + */ +__STATIC_INLINE uint32_t csi_cache_get_access_time (void) +{ + return 0; +} + +/** + \brief cache miss times + \details Cache miss times + \note every 256 miss add 1. + \return cache miss times, actual times should be multiplied by 256 + */ +__STATIC_INLINE uint32_t csi_cache_get_miss_time (void) +{ + return 0; +} + +/*@} end of CSI_Core_CacheFunctions */ + +/*@} end of CSI_core_DebugFunctions */ + +/* ################################## IRQ Functions ############################################ */ + +/** + \brief Save the Irq context + \details save the psr result before disable irq. + */ +__STATIC_INLINE uint32_t csi_irq_save(void) +{ + uint32_t result; + result = __get_MSTATUS(); + __disable_irq(); + return(result); +} + +/** + \brief Restore the Irq context + \details restore saved primask state. + \param [in] irq_state psr irq state. + */ +__STATIC_INLINE void csi_irq_restore(uint32_t irq_state) +{ + __set_MSTATUS(irq_state); +} + +/*@} end of IRQ Functions */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_DEPENDANT */ + +#endif /* __CSI_GENERIC */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_core.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_core.h new file mode 100644 index 0000000000..d8e95b8cc5 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_core.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + + +/****************************************************************************** + * @file csi_core.h + * @brief CSI Core Layer Header File + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ + +#ifndef _CORE_H_ +#define _CORE_H_ + +#include + +#if defined(__CK801__) || defined(__E801__) +#include +#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__) +#include +#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__) +#include +#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__) +#include +#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__) +#include +#elif defined(__CK610__) +#include +#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__) +#include +#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__) +#include +#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM) +#include +#elif defined(__riscv) +#include +#endif + +#ifdef __riscv +#include +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _CORE_H_ */ diff --git a/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_rv32_gcc.h b/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_rv32_gcc.h new file mode 100644 index 0000000000..b27e799889 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/csi_rv32_gcc.h @@ -0,0 +1,2829 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + + +/****************************************************************************** + * @file csi_rv32_gcc.h + * @brief CSI Header File for GCC. + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef _CSI_RV32_GCC_H_ +#define _CSI_RV32_GCC_H_ + +#include + +#ifndef __ASM +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#endif + +#ifndef __INLINE +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#endif + +#ifndef __ALWAYS_STATIC_INLINE +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline +#endif + +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions + @{ + */ +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("csrs mstatus, 8"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrc mstatus, 8"); +} + +/** + \brief Get MXSTATUS + \details Returns the content of the MXSTATUS Register. + \return MXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MXSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mxstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MXSTATUS + \details Writes the given value to the MXSTATUS Register. + \param [in] mxstatus MXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MXSTATUS(uint32_t mxstatus) +{ + __ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus)); +} + +/** + \brief Get MEXSTATUS + \details Returns the content of the MEXSTATUS Register. + \return MEXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEXSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mexstatus" : "=r"(result)); + return (result); +} + + +/** + \brief Get MRADDR + \details Returns the content of the MRADDR Register. + \return MRADDR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MRADDR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mraddr" : "=r"(result)); + return (result); +} + +/** + \brief Set MEXSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] mexstatus MSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEXSTATUS(uint32_t mexstatus) +{ + __ASM volatile("csrw mexstatus, %0" : : "r"(mexstatus)); +} + + + +/** + \brief Get MSTATUS + \details Returns the content of the MSTATUS Register. + \return MSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] mstatus MSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATUS(uint32_t mstatus) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(mstatus)); +} + +/** + \brief Get MHCR + \details Returns the content of the MHCR Register. + \return MHCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHCR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MHCR + \details Writes the given value to the MHCR Register. + \param [in] mstatus MHCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr) +{ + __ASM volatile("csrw mhcr, %0" : : "r"(mhcr)); +} + +/** + \brief Get MISA Register + \details Returns the content of the MISA Register. + \return MISA Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, misa" : "=r"(result)); + return (result); +} + +/** + \brief Set MISA + \details Writes the given value to the MISA Register. + \param [in] misa MISA Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MISA(uint32_t misa) +{ + __ASM volatile("csrw misa, %0" : : "r"(misa)); +} + +/** + \brief Get MIE Register + \details Returns the content of the MIE Register. + \return MIE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mie" : "=r"(result)); + return (result); +} + +/** + \brief Set MIE + \details Writes the given value to the MIE Register. + \param [in] mie MIE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIE(uint32_t mie) +{ + __ASM volatile("csrw mie, %0" : : "r"(mie)); +} + +/** + \brief Get MTVEC Register + \details Returns the content of the MTVEC Register. + \return MTVEC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtvec" : "=r"(result)); + return (result); +} + +/** + \brief Set MTVEC + \details Writes the given value to the MTVEC Register. + \param [in] mtvec MTVEC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVEC(uint32_t mtvec) +{ + __ASM volatile("csrw mtvec, %0" : : "r"(mtvec)); +} + +/** + \brief Set MTVT + \details Writes the given value to the MTVT Register. + \param [in] mtvt MTVT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVT(uint32_t mtvt) +{ + __ASM volatile("csrw mtvt, %0" : : "r"(mtvt)); +} + +/** + \brief Get MTVT Register + \details Returns the content of the MTVT Register. + \return MTVT Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVT(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtvt" : "=r"(result)); + return (result); +} + +/** + \brief Get SP + \details Returns the content of the SP Register. + \return SP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0, sp" : "=r"(result)); + return (result); +} + +/** + \brief Set SP + \details Writes the given value to the SP Register. + \param [in] sp SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp) +{ + __ASM volatile("mv sp, %0" : : "r"(sp): "sp"); +} + +/** + \brief Get MSCRATCH Register + \details Returns the content of the MSCRATCH Register. + \return MSCRATCH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mscratch" : "=r"(result)); + return (result); +} + +/** + \brief Set MSCRATCH + \details Writes the given value to the MSCRATCH Register. + \param [in] mscratch MSCRATCH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSCRATCH(uint32_t mscratch) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(mscratch)); +} + +/** + \brief Get MEPC Register + \details Returns the content of the MEPC Register. + \return MEPC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mepc" : "=r"(result)); + return (result); +} + +/** + \brief Set MEPC + \details Writes the given value to the MEPC Register. + \param [in] mepc MEPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEPC(uint32_t mepc) +{ + __ASM volatile("csrw mepc, %0" : : "r"(mepc)); +} + +/** + \brief Get MCAUSE Register + \details Returns the content of the MCAUSE Register. + \return MCAUSE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcause" : "=r"(result)); + return (result); +} + +/** + \brief Get MNXTI Register + \details Returns the content of the MNXTI Register. + \return MNXTI Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MNXTI(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mnxti" : "=r"(result)); + return (result); +} + +/** + \brief Set MNXTI + \details Writes the given value to the MNXTI Register. + \param [in] mnxti MNXTI Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MNXTI(uint32_t mnxti) +{ + __ASM volatile("csrw mnxti, %0" : : "r"(mnxti)); +} + +/** + \brief Get MINTSTATUS Register + \details Returns the content of the MINTSTATUS Register. + \return MINTSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINTSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mintstatus" : "=r"(result)); + return (result); +} + +/** + \brief Get MTVAL Register + \details Returns the content of the MTVAL Register. + \return MTVAL Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtval" : "=r"(result)); + return (result); +} + +/** + \brief Get MIP Register + \details Returns the content of the MIP Register. + \return MIP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIP(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mip" : "=r"(result)); + return (result); +} + +/** + \brief Set MIP + \details Writes the given value to the MIP Register. + \param [in] mip MIP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIP(uint32_t mip) +{ + __ASM volatile("csrw mip, %0" : : "r"(mip)); +} + +/** + \brief Get MCYCLEL Register + \details Returns the content of the MCYCLEL Register. + \return MCYCLE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcycle" : "=r"(result)); + return (result); +} + +/** + \brief Get MCYCLEH Register + \details Returns the content of the MCYCLEH Register. + \return MCYCLEH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLEH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcycleh" : "=r"(result)); + return (result); +} + +/** + \brief Get MINSTRET Register + \details Returns the content of the MINSTRET Register. + \return MINSTRET Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRET(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, minstret" : "=r"(result)); + return (result); +} + +/** + \brief Get MINSTRETH Register + \details Returns the content of the MINSTRETH Register. + \return MINSTRETH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRETH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, minstreth" : "=r"(result)); + return (result); +} + +/** + \brief Get MVENDORID Register + \details Returns the content of the MVENDROID Register. + \return MVENDORID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mvendorid" : "=r"(result)); + return (result); +} + +/** + \brief Get MARCHID Register + \details Returns the content of the MARCHID Register. + \return MARCHID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, marchid" : "=r"(result)); + return (result); +} + +/** + \brief Get MIMPID Register + \details Returns the content of the MIMPID Register. + \return MIMPID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mimpid" : "=r"(result)); + return (result); +} + +/** + \brief Get MHARTID Register + \details Returns the content of the MHARTID Register. + \return MHARTID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhartid" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPCFGx Register + \details Returns the content of the PMPCFGx Register. + \return PMPCFGx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG0(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG1(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG2(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG3(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg3" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPxCFG Register by index + \details Returns the content of the PMPxCFG Register. + \param [in] idx PMP region index + \return PMPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) +{ + uint32_t pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + } else { + return 0; + } + + return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3)); +} + +/** + \brief Set PMPCFGx + \details Writes the given value to the PMPCFGx Register. + \param [in] pmpcfg PMPCFGx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPCFG0(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG1(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG2(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG3(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg)); +} + +/** + \brief Set PMPxCFG by index + \details Writes the given value to the PMPxCFG Register. + \param [in] idx PMPx region index + \param [in] pmpxcfg PMPxCFG Register value to set + */ +__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) +{ + uint32_t pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG0(pmpcfgx); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG1(pmpcfgx); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG2(pmpcfgx); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG3(pmpcfgx); + } else { + return; + } +} + +/** + \brief Get PMPADDRx Register + \details Returns the content of the PMPADDRx Register. + \return PMPADDRx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR0(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR1(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR2(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR3(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr3" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR4(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr4" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR5(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr5" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR6(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr6" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR7(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr7" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR8(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr8" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR9(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr9" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR10(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr10" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR11(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr11" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR12(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr12" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR13(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr13" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR14(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr14" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR15(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr15" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPADDRx Register by index + \details Returns the content of the PMPADDRx Register. + \param [in] idx PMP region index + \return PMPADDRx Register value + */ +__STATIC_INLINE uint32_t __get_PMPADDRx(uint32_t idx) +{ + switch (idx) { + case 0: return __get_PMPADDR0(); + case 1: return __get_PMPADDR1(); + case 2: return __get_PMPADDR2(); + case 3: return __get_PMPADDR3(); + case 4: return __get_PMPADDR4(); + case 5: return __get_PMPADDR5(); + case 6: return __get_PMPADDR6(); + case 7: return __get_PMPADDR7(); + case 8: return __get_PMPADDR8(); + case 9: return __get_PMPADDR9(); + case 10: return __get_PMPADDR10(); + case 11: return __get_PMPADDR11(); + case 12: return __get_PMPADDR12(); + case 13: return __get_PMPADDR13(); + case 14: return __get_PMPADDR14(); + case 15: return __get_PMPADDR15(); + default: return 0; + } +} + +/** + \brief Set PMPADDRx + \details Writes the given value to the PMPADDRx Register. + \param [in] pmpaddr PMPADDRx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPADDR0(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR1(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR2(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR3(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR4(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR5(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR6(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR7(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR8(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR9(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR10(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR11(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR12(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR13(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR14(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR15(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr)); +} + +/** + \brief Set PMPADDRx by index + \details Writes the given value to the PMPADDRx Register. + \param [in] idx PMP region index + \param [in] pmpaddr PMPADDRx Register value to set + */ +__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, uint32_t pmpaddr) +{ + switch (idx) { + case 0: __set_PMPADDR0(pmpaddr); break; + case 1: __set_PMPADDR1(pmpaddr); break; + case 2: __set_PMPADDR2(pmpaddr); break; + case 3: __set_PMPADDR3(pmpaddr); break; + case 4: __set_PMPADDR4(pmpaddr); break; + case 5: __set_PMPADDR5(pmpaddr); break; + case 6: __set_PMPADDR6(pmpaddr); break; + case 7: __set_PMPADDR7(pmpaddr); break; + case 8: __set_PMPADDR8(pmpaddr); break; + case 9: __set_PMPADDR9(pmpaddr); break; + case 10: __set_PMPADDR10(pmpaddr); break; + case 11: __set_PMPADDR11(pmpaddr); break; + case 12: __set_PMPADDR12(pmpaddr); break; + case 13: __set_PMPADDR13(pmpaddr); break; + case 14: __set_PMPADDR14(pmpaddr); break; + case 15: __set_PMPADDR15(pmpaddr); break; + default: return; + } +} + +/** + \brief Enable interrupts and exceptions + \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) +{ + __enable_irq(); +} + + +/** + \brief Disable interrupts and exceptions + \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) +{ + __disable_irq(); +} + +#define __CSI_GCC_OUT_REG(r) "=r" (r) +#define __CSI_GCC_USE_REG(r) "r" (r) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__ALWAYS_STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__ALWAYS_STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __WAIT(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Doze For Interrupt + \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __DOZE(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Stop For Interrupt + \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __STOP(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__ALWAYS_STATIC_INLINE void __ISB(void) +{ + __ASM volatile("fence"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __DSB(void) +{ + __ASM volatile("fence"); +} + +/** + \brief Invalid all icache + \details invalid all icache. + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) +{ + __ASM volatile("icache.iall"); +} + +/** + \brief Invalid Icache by addr + \details Invalid Icache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint32_t addr) +{ + __ASM volatile("icache.ipa %0" : : "r"(addr)); +} + +/** + \brief Invalid all dcache + \details invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void) +{ + __ASM volatile("dcache.iall"); +} + +/** + \brief Clear all dcache + \details clear all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void) +{ + __ASM volatile("dcache.call"); +} + +/** + \brief Clear&invalid all dcache + \details clear & invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void) +{ + __ASM volatile("dcache.ciall"); +} + +/** + \brief Invalid Dcache by addr + \details Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint32_t addr) +{ + __ASM volatile("dcache.ipa %0" : : "r"(addr)); +} + +/** + \brief Clear Dcache by addr + \details Clear Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint32_t addr) +{ + __ASM volatile("dcache.cpa %0" : : "r"(addr)); +} + +/** + \brief Clear & Invalid Dcache by addr + \details Clear & Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint32_t addr) +{ + __ASM volatile("dcache.cipa %0" : : "r"(addr)); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__ALWAYS_STATIC_INLINE void __DMB(void) +{ + __ASM volatile("fence"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | + ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); + + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value) +{ + return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + */ +__ALWAYS_STATIC_INLINE void __BKPT(void) +{ + __ASM volatile("ebreak"); +} + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz +/** + \details This function saturates a signed value. + \param [in] x Value to be saturated + \param [in] y Bit position to saturate to [1..32] + \return Saturated value. + */ +__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + +// x &= (posMax * 2 + 1); + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + +// x &= (posMax * 2 - 1); + } + + return (x); +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Unsigned Saturate for internal use + \details Saturates an unsigned value, should not call directly. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if (value & 0x80000000) { /* only overflow set bit-31 */ + result = 0; + } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Rotate Right with Extend + \details This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \note carry input will always 0. + \param [in] op1 Value to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1) +{ + return 0; +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] addr Pointer to location + \return value of type uint8_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] addr Pointer to location + \return value of type uint16_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] addr Pointer to location + \return value of type uint32_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory"); +} + +/*@}*/ /* end of group CSI_Core_InstructionInterface */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics + Access to dedicated SIMD instructions \n + Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. + + @{ +*/ + +/** + \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] + of val2 levitated with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be left-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for left-shifting val2. Value range [0..31]. + \return the combination of halfwords. + \remark + res[15:0] = val1[15:0] \n + res[31:16] = val2[31:16] << val3 + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); +} + +/** + \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] + of val2 right-shifted with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be right-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for right-shifting val2. Value range [1..32]. + \return the combination of halfwords. + \remark + res[15:0] = val2[15:0] >> val3 \n + res[31:16] = val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); +} + +/** + \brief Dual 16-bit signed saturate. + \details This function saturates a signed value. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n + the signed saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the signed saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; + s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturate. + \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the saturation of the two signed 16-bit values, as non-negative values: + the saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; + s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit saturating addition. + \details This function enables you to perform four 8-bit integer additions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating addition. + \details This function enables you to perform four unsigned 8-bit integer additions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed addition. + \details This function performs four 8-bit signed integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition. + \details This function performs four unsigned 8-bit integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit saturating subtract. + \details This function enables you to perform four 8-bit integer subtractions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating subtraction. + \details This function enables you to perform four unsigned 8-bit integer subtractions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed subtraction. + \details This function enables you to perform four 8-bit signed integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtract. + \details This function enables you to perform four 8-bit unsigned integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences together, returning the result as a single unsigned integer. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n + The sum is returned as a single unsigned integer. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 + */ +__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return (u + t + s + r); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences to a 32-bit accumulate operand. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \param [in] sum accumulation value. + \return the sum of the absolute differences of the following bytes, added to the accumulation value: + the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n + res[31:0] = sum[31:0] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum) +{ + int32_t r, s, t, u; + +#ifdef __cplusplus + r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#else + r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#endif + return (u + t + s + r + sum); +} + +/** + \brief Dual 16-bit saturating addition. + \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition. + \details This function enables you to perform two unsigned 16-bit integer additions, saturating + the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition. + \details This function enables you to perform two 16-bit signed integer additions. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition + \details This function enables you to perform two 16-bit unsigned integer additions. + \param [in] x first two 16-bit summands for each addition. + \param [in] y second two 16-bit summands for each addition. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + + +/** + \brief Dual 16-bit signed addition with halved results. + \details This function enables you to perform two signed 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition with halved results. + \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition with halved results. + \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit saturating subtract. + \details This function enables you to perform two 16-bit integer subtractions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction. + \details This function enables you to perform two unsigned 16-bit integer subtractions, + saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit operands for each subtraction. + \param [in] y second two 16-bit operands for each subtraction. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction. + \details This function enables you to perform two 16-bit signed integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtract. + \details This function enables you to perform two 16-bit unsigned integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction with halved results. + \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction with halved results. + \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtraction with halved results. + \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit add and subtract with exchange. + \details This function enables you to exchange the halfwords of the one operand, + then add the high halfwords and subtract the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. + \details This function enables you to exchange the halfwords of the second operand and + perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, + saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit addition and subtraction with exchange. + \details It enables you to exchange the halfwords of the second operand, add the high halfwords + and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with exchange. + \details This function enables you to exchange the two halfwords of the second operand, + add the high halfwords and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition and subtraction with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + add the high halfwords and subtract the low halfwords, halving the results. + \param [in] x first operand for the subtraction in the low halfword, and + the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, and + the second operand for the addition in the low halfword. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit subtract and add with exchange. + \details This function enables you to exchange the halfwords of one operand, + then subtract the high halfwords and add the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. + \details This function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating + the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit unsigned subtract and add with exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction and addition with exchange. + \details This function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition. + \param [in] x first operand for the addition in the low halfword, and the first operand + for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and the second + operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/** + \brief Dual 16-bit signed subtraction and addition with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one signed + 16-bit integer subtraction and one signed 16-bit addition, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords, halving the results. + \param [in] x first operand for the addition in the low halfword, and + the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and + the second operand for the subtraction in the low halfword. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed multiply with exchange returning difference. + \details This function enables you to perform two 16-bit signed multiplications, subtracting + one of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top multiplication. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + +/** + \brief Sum of dual 16-bit signed multiply with exchange. + \details This function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + + +/** + \brief Saturating add. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 + SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) +{ + int32_t result; + + if (y >= 0) { + if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) { + result = x + y; + } else { + result = 0x7FFFFFFF; + } + } else { + if ((int32_t)((uint32_t)x + (uint32_t)y) < x) { + result = x + y; + } else { + result = 0x80000000; + } + } + + return result; +} + +/** + \brief Saturating subtract. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 - SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) +{ + int64_t tmp; + int32_t result; + + tmp = (int64_t)x - (int64_t)y; + + if (tmp > 0x7fffffff) { + tmp = 0x7fffffff; + } else if (tmp < (-2147483647 - 1)) { + tmp = -2147483647 - 1; + } + + result = tmp; + return result; +} + +/** + \brief Dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, + adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication with exchanged halfwords of the second + operand added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low + halfword product, and add the difference to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit + signed multiplications. The difference of the products is added to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with single 64-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, adding both results + to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. + This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. + \details This function enables you to exchange the halfwords of the second operand, and perform two + signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow + is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. + Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief dual 16-bit signed multiply subtract with 64-bit accumulate. + \details This function It enables you to perform two 16-bit signed multiplications, take the difference + of the products, subtracting the high halfword product from the low halfword product, and add the + difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the + subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not + detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. + \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, + adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the + multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow + is not detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief 32-bit signed multiply with 32-bit truncated accumulator. + \details This function enables you to perform a signed 32-bit multiplications, adding the most + significant 32 bits of the 64-bit result to a 32-bit accumulate operand. + \param [in] x first operand for multiplication. + \param [in] y second operand for multiplication. + \param [in] sum accumulate value. + \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. + \remark + p = val1 * val2 \n + res[31:0] = p[63:32] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum); +} + +/** + \brief Sum of dual 16-bit signed multiply. + \details This function enables you to perform two 16-bit signed multiplications, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual 16-bit signed multiply returning difference. + \details This function enables you to perform two 16-bit signed multiplications, taking the difference + of the products by subtracting the high halfword product from the low halfword product. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual extracted 8-bit to 16-bit signed addition. + \details This function enables you to extract two 8-bit values from the second operand (at bit positions + [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. + \param [in] x values added to the sign-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and sign-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and sign-extended prior to the addition. + \remark + res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | + (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); +} + +/** + \brief Extracted 16-bit to 32-bit unsigned addition. + \details This function enables you to extract two 8-bit values from one operand, zero-extend + them to 16 bits each, and add the results to two 16-bit values from another operand. + \param [in] x values added to the zero-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and zero-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and zero-extended prior to the addition. + \remark + res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | + ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and sign extend each to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x) +{ + return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | + ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and zero-extend to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x) +{ + return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000))); +} + +#endif /* _CSI_RV32_GCC_H_ */ diff --git a/bsp/essemi/es32vf2264/libraries/SConscript b/bsp/essemi/es32vf2264/libraries/SConscript new file mode 100644 index 0000000000..ed635a0f07 --- /dev/null +++ b/bsp/essemi/es32vf2264/libraries/SConscript @@ -0,0 +1,25 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = [] + +src += Glob('ALD/ES32VF2264/Source/*.c') + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['RV_CORE/Device/EastSoft/ES32VF2264/Startup/startup_es32vf2264.S'] + src = src + ['RV_CORE/Device/EastSoft/ES32VF2264/Startup/trap_c.c'] + src = src + ['RV_CORE/Device/EastSoft/ES32VF2264/Svc/es32vf2264.svc'] + +path = [cwd + '/RV_CORE/Device/EastSoft/ES32VF2264/Include', + cwd + '/RV_CORE/Include', + cwd + '/ALD/ES32VF2264/Include'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = ['ES32VF2264']) + +Return('group') diff --git a/bsp/essemi/es32vf2264/project.cdkproj b/bsp/essemi/es32vf2264/project.cdkproj new file mode 100644 index 0000000000..1c9a539441 --- /dev/null +++ b/bsp/essemi/es32vf2264/project.cdkproj @@ -0,0 +1,320 @@ + + + CPU: e902 +Chip: smartl_rv32 +Board: smartl_rv32_evb +BareMetal: Without RTOS + + + + 96 + 106 + + + + NULL + + + + XTGccElfNewlib + latest + + + + g_rx_buf:0 + 0;;; + ;;32;;MHZ; + + 1 + 0 + + 100:4;100:8;100:8;100:8; + + + + + + + no + + + + + no + + + + + no + + + + + no + + + + + no + + + + + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + e902m + yes + little + no + no + no + no + + + $(ProjectName) + Executable + yes + no + no + yes + no + no + + + + no + + + + no + + + + no + + + + + + __SYS_SELECT_H__, __RTTHREAD__, ES32VF2264 + + None (-O0) + Maximum (-g3) + applications;.;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\risc-v\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;drivers\ES;..\..\..\components\finsh;.;..\..\..\include;libraries\RV_CORE\Device\EastSoft\ES32VF2264\Include;libraries\RV_CORE\Include;libraries\ALD\ES32VF2264\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + no + no + no + no + no + no + yes + no + no + no + no + + + + + applications;.;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\risc-v\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;drivers\ES;..\..\..\components\finsh;.;..\..\..\include;libraries\RV_CORE\Device\EastSoft\ES32VF2264\Include;libraries\RV_CORE\Include;libraries\ALD\ES32VF2264\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + gdwarf2 + + + yes + yes + $(ProjectPath)drivers/es32vf2264.ld + m + + + no + + no + + + yes + ICE + yes + main + + + + yes + Hard Reset + 1 + no + + no + $(ProjectPath)/$(ProjectName).cdkcore + + localhost + 1025 + 0 + 12000 + 10 + 100 + 50 + no + no + no + no + Normal + Hard Reset + 0 + Bare Metal + yes + yes + + Local + -vid 0x30cc -pid 0x9528 -prereset + no + 1000 + yes + 1026 + latest + no + + + soccfg/riscv32/smartl_902_cfg.xml + + yes + no + no + latest + + + + no + 4444 + no + 6666 + + 5000 + openocd-sifive + latest + + + + + + Erase Sectors + es32vf2264.elf + yes + yes + no + Soft Reset + 1 + no + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/essemi/es32vf2264/project.cdkws b/bsp/essemi/es32vf2264/project.cdkws new file mode 100644 index 0000000000..d1d63e556d --- /dev/null +++ b/bsp/essemi/es32vf2264/project.cdkws @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/bsp/essemi/es32vf2264/rtconfig.h b/bsp/essemi/es32vf2264/rtconfig.h new file mode 100644 index 0000000000..2982c60de7 --- /dev/null +++ b/bsp/essemi/es32vf2264/rtconfig.h @@ -0,0 +1,251 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define IDLE_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "cuart1" +#define RT_VER_NUM 0x50001 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_ES32VF2264 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_CUART1 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* ADC Drivers */ + + +/* HWTIMER Drivers */ + + +/* PWM Drivers */ + + +/* PM Drivers */ + + +/* DMA Drivers */ + + +/* Onboard Peripheral Drivers */ + + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/essemi/es32vf2264/rtconfig.py b/bsp/essemi/es32vf2264/rtconfig.py new file mode 100644 index 0000000000..55d3045902 --- /dev/null +++ b/bsp/essemi/es32vf2264/rtconfig.py @@ -0,0 +1,104 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH ='risc-v' +VENDOR ='t-head' +CPU ='e9xx' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/applications' + +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'csky-abiv2-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/es32vf2264.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu e9xx' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/essemi/es32vf2264/template.cdkproj b/bsp/essemi/es32vf2264/template.cdkproj new file mode 100644 index 0000000000..5e44e4cdee --- /dev/null +++ b/bsp/essemi/es32vf2264/template.cdkproj @@ -0,0 +1,244 @@ + + + CPU: e902 +Chip: smartl_rv32 +Board: smartl_rv32_evb +BareMetal: Without RTOS + + + + 96 + 106 + + + + NULL + + + + XTGccElfNewlib + latest + + + + g_rx_buf:0 + 0;;; + ;;32;;MHZ; + + 1 + 0 + + 100:4;100:8;100:8;100:8; + + + + + + + no + + + + + no + + + + + no + + + + + no + + + + + no + + + + + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + e902m + yes + little + no + no + no + no + + + $(ProjectName) + Executable + yes + no + no + yes + no + no + + + + no + + + + no + + + + no + + + + + + USE_ASSERT;ES32VF2264 + + None (-O0) + Maximum (-g3) + + -ffunction-sections -fdata-sections + no + no + no + no + no + no + yes + no + no + no + no + + + + + + + gdwarf2 + + + yes + yes + $(ProjectPath)drivers/es32vf2264.ld + m + + -Wl,-zmax-page-size=1024 -specs=nosys.specs -mccrt + no + + no + + + yes + ICE + yes + main + + + + yes + Hard Reset + 1 + no + + no + $(ProjectPath)/$(ProjectName).cdkcore + + localhost + 1025 + 0 + 12000 + 10 + 100 + 50 + no + no + no + no + Normal + Hard Reset + 0 + Bare Metal + yes + yes + + Local + -vid 0x30cc -pid 0x9528 -prereset + no + 1000 + yes + 1026 + latest + no + + + soccfg/riscv32/smartl_902_cfg.xml + + yes + no + no + latest + + + + no + 4444 + no + 6666 + + 5000 + openocd-sifive + latest + + + + + + Erase Sectors + es32vf2264.elf + yes + yes + no + Soft Reset + 1 + no + + + + + + diff --git a/bsp/essemi/es32vf2264/template.cdkws b/bsp/essemi/es32vf2264/template.cdkws new file mode 100644 index 0000000000..0c04be663e --- /dev/null +++ b/bsp/essemi/es32vf2264/template.cdkws @@ -0,0 +1,11 @@ + + + $(CDKWS)\__workspace_pack__ + + + + + + + +