[ht32][drv]新增了CAN、USB和SDIO的驱动文件

.github/workflows/bsp_buildings.yml

@@ -101,6 +101,7 @@ jobs:
                 - "rm48x50"
                 - "ht32/ht32f52352"
                 - "ht32/ht32f12366"
+                - "ht32/ht32f53252"
                 - "w60x"
                 - "essemi/es32f0654"
                 - "essemi/es32f365x"

bsp/ht32/ht32f12366/README.md

@@ -41,8 +41,8 @@ ESK32-30105使用32位ARM® Cortex®-M3高性能、低功耗单片机HT32F12366
 | UART | 支持  | UART0/1 |
 | SPI | 支持  | SPI0/1 |
 | I2C | 支持  | 硬件 I2C0/1 |
-| ADC | 暂不支持  |     |
-| WDT | 暂不支持  |     |
+| ADC | 支持  |     |
+| WDT | 支持  |     |
 
 ## 使用说明
 

bsp/ht32/ht32f12366/SConstruct

@@ -53,6 +53,9 @@ rtconfig.BSP_LIBRARY_TYPE = ht32_library
 # include libraries
 objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
 
+# include usb libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbd_library', 'SConscript')))
+
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
 

bsp/ht32/ht32f12366/applications/test.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2025, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -58,10 +58,18 @@ static struct rt_semaphore rx_sem;
 static rt_mutex_t task_mutex = RT_NULL; /* task mutex */
 
 /* device handle */
+#ifdef BSP_USING_UART
 static rt_device_t serial;
+#endif
+#ifdef BSP_USING_WDT
 static rt_device_t wdt_dev;
+#endif
+#ifdef BSP_USING_I2C
 struct rt_i2c_bus_device *i2c_dev;
+#endif
+#ifdef BSP_USING_SPI
 static struct rt_spi_device *spi_dev;
+#endif
 
 /* In-file function declarations */
 static void sys_run_dir(void *parameter);
@@ -90,6 +98,7 @@ int task_registration(void)
 INIT_BOARD_EXPORT(task_registration);
 
 /* System operation indicator */
+#ifdef BSP_USING_GPIO
 static void sys_run_dir(void *parameter)
 {
     rt_uint32_t e;
@@ -301,7 +310,9 @@ static int gpio_input_task(int argc, char *argv[])
     return -1;
 }
 MSH_CMD_EXPORT(gpio_input_task, gpio input task operation);
+#endif
 /* uart test */
+#ifdef BSP_USING_UART
 static rt_err_t uart_iqr_handle(rt_device_t dev, rt_size_t size)
 {
     /* Serial port callback function */
@@ -396,7 +407,9 @@ static int uart_task(int argc, char *argv[])
     return ret;
 }
 MSH_CMD_EXPORT(uart_task, uart device sample);
+#endif
 /* hw/sw iic test */
+#ifdef BSP_USING_I2C
 static void i2c_thread(void *parameter)
 {
     uint8_t write_addr = 0x00;
@@ -497,7 +510,9 @@ static int i2c_task(int argc, char *argv[])
     return ret;
 }
 MSH_CMD_EXPORT(i2c_task, i2c device sample);
+#endif
 /* spi test */
+#ifdef BSP_USING_SPI
 static void spi_thread(void *parameter)
 {
     rt_uint8_t w25x_read_id = 0x9F;
@@ -584,7 +599,9 @@ static int spi_task(int argc, char *argv[])
     return ret;
 }
 MSH_CMD_EXPORT(spi_task, spi device sample);
+#endif
 /* adc test */
+#ifdef BSP_USING_ADC
 static void adc_test(void *parameter)
 {
     rt_uint32_t adc0_ch11_val,adc0_ch12_val;
@@ -640,8 +657,9 @@ static int adc_task(int argc, char *argv[])
     return -1;
 }
 MSH_CMD_EXPORT(adc_task, adc task operation);
-
+#endif
 /* wdt test */
+#ifdef BSP_USING_WDT
 static void wdt_test(void)
 {
     rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
@@ -712,5 +730,106 @@ static int wdt_task(int argc, char *argv[])
     return -1;
 }
 MSH_CMD_EXPORT(wdt_task, wdt task operation);
+#endif
+/* usbd test */
+#ifdef BSP_USING_USBD
+static void usbd_test(void *parameter)
+{
+    rt_device_t dev = RT_NULL;
+    char dev_name[] = "vcom";
+    char buf[] = "usbd vcom test!\r\n";
 
+    dev = rt_device_find(dev_name);
+
+    if (dev)
+    {
+        rt_device_open(dev, RT_DEVICE_FLAG_RDWR);
+    }
+    else
+    {
+        rt_kprintf("Device with name %s not found.\n",dev_name);
+        rt_thread_t tid = rt_thread_self();
+        rt_thread_delete(tid);
+    }
+    while (1)
+    {
+        rt_device_write(dev, 0, buf, rt_strlen(buf));
+        rt_thread_mdelay(500);
+    }
+}
+
+static int usbd_task(int argc, char *argv[])
+{
+    rt_err_t ret = -RT_ERROR;
+
+    if(argc == 2)
+    {
+        if(rt_strcmp(argv[1],"start") == 0)
+        {
+            /* Gpio input test tasks */
+            rt_thread_t usbd_vcom_task = rt_thread_create("usbd_vcom_task",
+                                            usbd_test, RT_NULL,
+                                            THREAD_STACK_SIZE,
+                                            THREAD_PRIORITY, THREAD_TIMESLICE);
+            if (usbd_vcom_task != RT_NULL)
+            {
+                rt_thread_startup(usbd_vcom_task);
+                rt_kprintf("The usbd vcom task is registered.\n");
+            }
+            else
+            {
+                rt_kprintf("usbd vcom task registration failed.\n");
+            }
+            ret = RT_EOK;
+        }
+        else if(rt_strcmp(argv[1],"stop") == 0)
+        {
+            ret = RT_EOK;
+        }
+    }
+    else
+    {
+        rt_kprintf("Necessary parameters are missing.\n");
+        rt_kprintf("You can use the following commands.\n");
+        rt_kprintf("%s start\n",__func__);
+        rt_kprintf("%s stop\n",__func__);
+    }
+    return ret;
+}
+MSH_CMD_EXPORT(usbd_task, usbd task operation);
+#endif
+#ifdef BSP_USING_SDIO
+int mnt_init(void)
+{
+    rt_device_t dev = RT_NULL;
+    char dev_name[] = BSP_USING_SDIO_NAME;
+    rt_thread_mdelay(1000);
+
+    dev = rt_device_find(dev_name);
+    if(dev)
+    {
+        if(dfs_mount("sd0","/","elm",0,0) == RT_EOK)
+        {
+            rt_kprintf("dfs mount success!\r\n");
+        }
+        else
+        {
+            rt_kprintf("dfs mount failed!\r\n");
+            rt_kprintf("Formatting the SD card!\r\n");
+            dfs_mkfs("elm",dev_name);
+            if(dfs_mount("sd0","/","elm",0,0) == RT_EOK)
+            {
+                rt_kprintf("dfs mount success!\r\n");
+            }
+            else
+            {
+                rt_kprintf("dfs mount failed!\r\n");
+                rt_kprintf("Exit SD card mount!\r\n");
+            }
+        }
+    }
+    return 0;
+}
+INIT_FS_EXPORT(mnt_init);
+#endif /* BSP_USING_SDIO */
 #endif /* BSP_USING_TEST */

bsp/ht32/ht32f12366/board/Kconfig

@@ -126,7 +126,7 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_UART
         bool "Enable UART"
         default n
-        select RT_USING_SERIAL
+        select RT_USING_SERIAL if BSP_USING_UART
         if BSP_USING_UART
             config BSP_USING_USART0
                 bool "Enable USART0"
@@ -306,6 +306,141 @@ menu "On-chip Peripheral Drivers"
         depends on BSP_USING_WDT
         string "wdt device name"
         default "wdt"
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        depends on SOC_HT32F53241 || SOC_HT32F53242 || SOC_HT32F53252
+        default n
+        select RT_USING_CAN if BSP_USING_CAN
+        config BSP_USING_CAN_NAME
+        depends on BSP_USING_CAN
+        string "can device name"
+        default "can"
+        if BSP_USING_CAN
+            config CAN_DEFAULT_BASE_CONFIGURATION  
+                choice
+                    prompt "Default CAN baud rate"
+                    default BSP_USING_CAN500kBaud
+                    config BSP_USING_CAN1MBaud
+                        bool "CAN1MBaud"
+                    config BSP_USING_CAN800kBaud
+                        bool "CAN800kBaud"
+                    config BSP_USING_CAN500kBaud
+                        bool "CAN500kBaud"
+                    config BSP_USING_CAN250kBaud
+                        bool "CAN250kBaud"
+                    config BSP_USING_CAN125kBaud
+                        bool "CAN125kBaud"
+                    config BSP_USING_CAN100kBaud
+                        bool "CAN100kBaud"
+                    config BSP_USING_CAN50kBaud
+                        bool "CAN50kBaud"
+                    config BSP_USING_CAN20kBaud
+                        bool "CAN20kBaud"
+                    config BSP_USING_CAN10kBaud
+                        bool "CAN10kBaud"
+                endchoice
+                choice
+                    prompt "Default CAN mode"
+                    default BSP_USING_RT_CAN_MODE_NORMAL
+                    config BSP_USING_RT_CAN_MODE_NORMAL
+                        bool "RT_CAN_MODE_NORMAL"
+                    config BSP_USING_RT_CAN_MODE_LISTEN
+                        bool "RT_CAN_MODE_LISTEN"
+                    config BSP_USING_RT_CAN_MODE_LOOPBACK
+                        bool "RT_CAN_MODE_LOOPBACK"
+                    config BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN
+                        bool "RT_CAN_MODE_LOOPBACKANLISTEN"
+                endchoice
+
+                config BSP_USING_CAN_BAUD
+                int
+                default 1000000 if BSP_USING_CAN1MBaud
+                default 800000 if BSP_USING_CAN800kBaud
+                default 500000 if BSP_USING_CAN500kBaud
+                default 250000 if BSP_USING_CAN250kBaud
+                default 125000 if BSP_USING_CAN125kBaud
+                default 100000 if BSP_USING_CAN100kBaud
+                default 50000 if BSP_USING_CAN50kBaud
+                default 20000 if BSP_USING_CAN20kBaud
+                default 10000 if BSP_USING_CAN10kBaud
+
+                config BSP_USING_CAN_MODE
+                int
+                default 0 if BSP_USING_RT_CAN_MODE_NORMAL
+                default 1 if BSP_USING_RT_CAN_MODE_LISTEN
+                default 2 if BSP_USING_RT_CAN_MODE_LOOPBACK
+                default 3 if BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN
+            
+            config CAN_DEFAULT_FILTER_TABLE_CONFIGURATION
+                choice
+                    prompt "Default filter id mode"
+                    default BSP_USING_CAN_STD_ID
+                    config BSP_USING_CAN_STD_ID
+                        bool "CAN_STD_ID"
+                    config BSP_USING_CAN_EXT_ID
+                        bool "CAN_EXT_ID"
+                endchoice
+
+                choice
+                    prompt "Default filter frame mode"
+                    default BSP_USING_CAN_DATA_FRAME
+                    config BSP_USING_CAN_DATA_FRAME
+                        bool "CAN_DATA_FRAME"
+                    config BSP_USING_CAN_REMOTE_FRAME
+                        bool "CAN_REMOTE_FRAME"
+                endchoice
+
+                config BSP_USING_CAN_ID_MODE
+                int
+                default 0 if BSP_USING_CAN_STD_ID
+                default 1 if BSP_USING_CAN_EXT_ID
+
+                config BSP_USING_CAN_FRAME_MODE
+                int
+                default 0 if BSP_USING_CAN_REMOTE_FRAME
+                default 1 if BSP_USING_CAN_DATA_FRAME
+
+                config BSP_USING_CAN_MSG_NUM
+                int "Default filter table number"
+                range 0 31
+                default 0
+
+                config BSP_USING_CAN_ID
+                hex "Default filter arbitration bit(ID)"
+                range 0 0x7FF if BSP_USING_CAN_STD_ID
+                default 0x541 if BSP_USING_CAN_STD_ID
+                range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+                default 0x541 if BSP_USING_CAN_EXT_ID
+
+                config BSP_USING_CAN_MASK
+                hex "Default filter mask bit(MASK)"
+                range 0 0x7FF if BSP_USING_CAN_STD_ID
+                default 0x7FF if BSP_USING_CAN_STD_ID
+                range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+                default 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+
+        endif
+
+    menuconfig BSP_USING_SDIO
+        bool "Enable SDIO"
+        depends on SOC_HT32F12345 || SOC_HT32F12365 || SOC_HT32F12366
+        default n
+        select RT_USING_SDIO if BSP_USING_SDIO
+        select RT_USING_DFS if BSP_USING_SDIO
+        config BSP_USING_SDIO_NAME
+        depends on BSP_USING_SDIO
+        string "sdio device name"
+        default "sd0"
+
+    menuconfig BSP_USING_USBD
+        bool "Enable USB BUS"
+        default n
+        select RT_USING_USB_DEVICE if BSP_USING_USBD
+        config BSP_USING_USBD_NAME
+        depends on BSP_USING_USBD
+        string "usbd device name"
+        default "usbd"
 endmenu
 
 menu "Board extended module Drivers"

bsp/ht32/ht32f12366/board/inc/board.h

@@ -23,6 +23,10 @@
     #include "drv_spi.h"
 #endif
 
+#ifdef BSP_USING_SDIO
+#include "dfs_fs.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif

bsp/ht32/ht32f12366/board/inc/ht32_msp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2025, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -100,7 +100,7 @@ extern "C" {
     #define HTCFG_UART1_RX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_UART1_RX_GPION)
 
 #endif
-#endif
+#endif  /* BSP_USING_UART */
 
 /* SPI gpio */
 #ifdef BSP_USING_SPI
@@ -156,7 +156,7 @@ extern "C" {
     #define HTCFG_SPI1_MOSI_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SPI1_MOSI_GPION)
 
 #endif
-#endif
+#endif  /* BSP_USING_SPI */
 
 /* I2C gpio */
 #ifdef BSP_USING_I2C_HW
@@ -198,7 +198,8 @@ extern "C" {
     #define HTCFG_I2C1_SDA_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_I2C1_SDA_GPION)
 
 #endif
-#endif
+#endif  /* BSP_USING_I2C_HW */
+
 /* ADC gpio */
 #ifdef BSP_USING_ADC
 #ifdef BSP_USING_ADC0
@@ -335,12 +336,66 @@ extern "C" {
 #define HTCFG_ADC1CH7_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH7_AFION)
 
 #endif
-#endif
+#endif  /* BSP_USING_ADC */
 
+/* SDIO gpio */
+#ifdef BSP_USING_SDIO
+    #define HTCFG_SDIO_IPN                           SDIO
+
+    #define _HTCFG_SDIO_CLK_GPIOX                    A
+    #define _HTCFG_SDIO_CLK_GPION                    5
+
+    #define _HTCFG_SDIO_CMD_GPIOX                    A
+    #define _HTCFG_SDIO_CMD_GPION                    4
+
+    #define _HTCFG_SDIO_DAT0_GPIOX                   C
+    #define _HTCFG_SDIO_DAT0_GPION                   9
+
+    #define _HTCFG_SDIO_DAT1_GPIOX                   C
+    #define _HTCFG_SDIO_DAT1_GPION                   10
+
+    #define _HTCFG_SDIO_DAT2_GPIOX                   C
+    #define _HTCFG_SDIO_DAT2_GPION                   11
+
+    #define _HTCFG_SDIO_DAT3_GPIOX                   C
+    #define _HTCFG_SDIO_DAT3_GPION                   12
+
+    #define HTCFG_SDIO_CLK_GPIO_CLK                  STRCAT2(P,              _HTCFG_SDIO_CLK_GPIOX)
+    #define HTCFG_SDIO_CLK_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_SDIO_CLK_GPIOX)
+    #define HTCFG_SDIO_CLK_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_SDIO_CLK_GPIOX)
+    #define HTCFG_SDIO_CLK_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_SDIO_CLK_GPION)
+
+    #define HTCFG_SDIO_CMD_GPIO_CLK                  STRCAT2(P,              _HTCFG_SDIO_CMD_GPIOX)
+    #define HTCFG_SDIO_CMD_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_SDIO_CMD_GPIOX)
+    #define HTCFG_SDIO_CMD_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_SDIO_CMD_GPIOX)
+    #define HTCFG_SDIO_CMD_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_SDIO_CMD_GPION)
+
+    #define HTCFG_SDIO_DAT0_GPIO_CLK                 STRCAT2(P,              _HTCFG_SDIO_DAT0_GPIOX)
+    #define HTCFG_SDIO_DAT0_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SDIO_DAT0_GPIOX)
+    #define HTCFG_SDIO_DAT0_GPIO_PORT                STRCAT2(HT_GPIO,        _HTCFG_SDIO_DAT0_GPIOX)
+    #define HTCFG_SDIO_DAT0_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SDIO_DAT0_GPION)
+
+    #define HTCFG_SDIO_DAT1_GPIO_CLK                 STRCAT2(P,              _HTCFG_SDIO_DAT1_GPIOX)
+    #define HTCFG_SDIO_DAT1_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SDIO_DAT1_GPIOX)
+    #define HTCFG_SDIO_DAT1_GPIO_PORT                STRCAT2(HT_GPIO,        _HTCFG_SDIO_DAT1_GPIOX)
+    #define HTCFG_SDIO_DAT1_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SDIO_DAT1_GPION)
+
+    #define HTCFG_SDIO_DAT2_GPIO_CLK                 STRCAT2(P,              _HTCFG_SDIO_DAT2_GPIOX)
+    #define HTCFG_SDIO_DAT2_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SDIO_DAT2_GPIOX)
+    #define HTCFG_SDIO_DAT2_GPIO_PORT                STRCAT2(HT_GPIO,        _HTCFG_SDIO_DAT2_GPIOX)
+    #define HTCFG_SDIO_DAT2_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SDIO_DAT2_GPION)
+
+    #define HTCFG_SDIO_DAT3_GPIO_CLK                 STRCAT2(P,              _HTCFG_SDIO_DAT3_GPIOX)
+    #define HTCFG_SDIO_DAT3_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SDIO_DAT3_GPIOX)
+    #define HTCFG_SDIO_DAT3_GPIO_PORT                STRCAT2(HT_GPIO,        _HTCFG_SDIO_DAT3_GPIOX)
+    #define HTCFG_SDIO_DAT3_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SDIO_DAT3_GPION)
+
+#endif  /* BSP_USING_SDIO */
 void ht32_usart_gpio_init(void *instance);
 void ht32_spi_gpio_init(void *instance);
 void ht32_hardware_i2c_gpio_init(void *instance);
 void ht32_adc_gpio_init(void *instance,int8_t channel);
+void ht32_sdio_gpio_init(void *instance);
 
 #ifdef __cplusplus
 }

bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h

@@ -58,7 +58,7 @@
 //    <o0.13> Endpoint5 Interrupt Enable (EP5IE)
 //    <o0.14> Endpoint6 Interrupt Enable (EP6IE)
 //    <o0.15> Endpoint7 Interrupt Enable (EP7IE)
-#define _UIER               (0x011D)
+#define _UIER               (0xFF1D)
 //  </h>
 
 
@@ -96,7 +96,7 @@
 /* Endpoint1 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint1 Configuration
-#define _EP1_ENABLE         (0)
+#define _EP1_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -114,7 +114,7 @@
 //    <o0> Endpoint Transfer Type
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP1_TYPR           (3)
+#define _EP1_TYPR           (2)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -123,7 +123,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
                             /* Maximum: 64 Bytes                                                            */
-#define _EP1LEN_TMP         (8)
+#define _EP1LEN_TMP         (64)
 
 //    <h> Endpoint Interrupt Enable Settings (EPIER)
 //      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
@@ -135,7 +135,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP1_IER            (0x10)
+#define _EP1_IER            (0x12)
 // </h>
 // </e>
 
@@ -144,7 +144,7 @@
 /* Endpoint2 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint2 Configuration
-#define _EP2_ENABLE         (0)
+#define _EP2_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -162,7 +162,7 @@
 //    <o0> Endpoint Transfer Type
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP2_TYPR           (3)
+#define _EP2_TYPR           (2)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -171,7 +171,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
                             /* Maximum: 64 Bytes                                                            */
-#define _EP2LEN_TMP         (8)
+#define _EP2LEN_TMP         (64)
 
 //    <h> Endpoint Interrupt Enable Settings (EPIER)
 //      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
@@ -183,7 +183,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP2_IER            (0x002)
+#define _EP2_IER            (0x012)
 // </h>
 // </e>
 
@@ -191,7 +191,7 @@
 /* Endpoint3 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint3 Configuration
-#define _EP3_ENABLE         (0)
+#define _EP3_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -218,7 +218,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
                             /* Maximum: 64 Bytes                                                            */
-#define _EP3LEN_TMP         (8)
+#define _EP3LEN_TMP         (64)
 
 //    <h> Endpoint Interrupt Enable Settings (EPIER)
 //      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
@@ -230,7 +230,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP3_IER            (0x10)
+#define _EP3_IER            (0x12)
 // </h>
 // </e>
 
@@ -238,7 +238,7 @@
 /* Endpoint4 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint4 Configuration
-#define _EP4_ENABLE         (0)
+#define _EP4_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -266,7 +266,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP4LEN_TMP         (8)
+#define _EP4LEN_TMP         (64)
 
 //    <o0> Single/Double Buffer Selection (SDBS)
 //      <0=> Single Buffer
@@ -283,7 +283,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP4_IER            (0x02)
+#define _EP4_IER            (0x12)
 // </h>
 // </e>
 
@@ -292,7 +292,7 @@
 /* Endpoint5 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint5 Configuration
-#define _EP5_ENABLE         (0)
+#define _EP5_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -311,7 +311,7 @@
 //      <1=> Isochronous
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP5_TYPR           (3)
+#define _EP5_TYPR           (1)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -320,7 +320,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP5LEN_TMP         (8)
+#define _EP5LEN_TMP         (64)
 
 
 //    <o0> Single/Double Buffer Selection (SDBS)
@@ -338,7 +338,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP5_IER            (0x10)
+#define _EP5_IER            (0x12)
 // </h>
 // </e>
 
@@ -347,7 +347,7 @@
 /* Endpoint6 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint6 Configuration
-#define _EP6_ENABLE         (0)
+#define _EP6_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -366,7 +366,7 @@
 //      <1=> Isochronous
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP6_TYPR           (3)
+#define _EP6_TYPR           (1)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -375,7 +375,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP6LEN_TMP         (8)
+#define _EP6LEN_TMP         (64)
 
 //    <o0> Single/Double Buffer Selection (SDBS)
 //      <0=> Single Buffer
@@ -392,7 +392,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP6_IER            (0x02)
+#define _EP6_IER            (0x12)
 // </h>
 // </e>
 
@@ -401,7 +401,7 @@
 /* Endpoint7 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint7 Configuration
-#define _EP7_ENABLE         (0)
+#define _EP7_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -429,7 +429,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP7LEN_TMP         (8)
+#define _EP7LEN_TMP         (64)
 
 //    <o0> Single/Double Buffer Selection (SDBS)
 //      <0=> Single Buffer
@@ -446,7 +446,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP7_IER            (0x10)
+#define _EP7_IER            (0x12)
 // </h>
 // </e>
 

bsp/ht32/ht32f12366/board/src/ht32_msp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2025, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -69,7 +69,7 @@ void ht32_usart_gpio_init(void *instance)
     }
 #endif
 }
-#endif
+#endif  /* BSP_USING_UART */
 
 /* GPIO configuration for SPI */
 #ifdef BSP_USING_SPI
@@ -104,7 +104,7 @@ void ht32_spi_gpio_init(void *instance)
     }
 #endif
 }
-#endif
+#endif  /* BSP_USING_SPI */
 
 /* GPIO configuration for I2C */
 #ifdef BSP_USING_I2C_HW
@@ -135,7 +135,7 @@ void ht32_hardware_i2c_gpio_init(void *instance)
     }
 #endif
 }
-#endif
+#endif  /* BSP_USING_I2C_HW */
 /* GPIO configuration for ADC */
 #ifdef BSP_USING_ADC
 void ht32_adc_gpio_init(void *instance,int8_t channel)
@@ -247,4 +247,42 @@ void ht32_adc_gpio_init(void *instance,int8_t channel)
     }
 #endif
 }
-#endif
+#endif  /* BSP_USING_ADC */
+
+/* GPIO configuration for SDIO */
+#ifdef BSP_USING_SDIO
+void ht32_sdio_gpio_init(void *instance)
+{
+    CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
+    HT_SDIO_TypeDef *sdio_x = (HT_SDIO_TypeDef *)instance;
+    if(HT_SDIO == sdio_x)
+    {
+        CKCUClock.Bit.HTCFG_SDIO_CLK_GPIO_CLK   = 1;
+        CKCUClock.Bit.HTCFG_SDIO_CMD_GPIO_CLK   = 1;
+        CKCUClock.Bit.HTCFG_SDIO_DAT0_GPIO_CLK  = 1;
+        CKCUClock.Bit.HTCFG_SDIO_DAT1_GPIO_CLK  = 1;
+        CKCUClock.Bit.HTCFG_SDIO_DAT2_GPIO_CLK  = 1;
+        CKCUClock.Bit.HTCFG_SDIO_DAT3_GPIO_CLK  = 1;
+        CKCUClock.Bit.SDIO                      = 1;
+        CKCUClock.Bit.PDMA                      = 1;
+        CKCUClock.Bit.AFIO                      = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+
+        /* Configure SDIO pins                                                                                    */
+        AFIO_GPxConfig(HTCFG_SDIO_CLK_GPIO_ID, HTCFG_SDIO_CLK_GPIO_PIN, AFIO_FUN_SDIO);
+        AFIO_GPxConfig(HTCFG_SDIO_CMD_GPIO_ID, HTCFG_SDIO_CMD_GPIO_PIN, AFIO_FUN_SDIO);
+        AFIO_GPxConfig(HTCFG_SDIO_DAT0_GPIO_ID, HTCFG_SDIO_DAT0_GPIO_PIN, AFIO_FUN_SDIO);
+        AFIO_GPxConfig(HTCFG_SDIO_DAT1_GPIO_ID, HTCFG_SDIO_DAT1_GPIO_PIN, AFIO_FUN_SDIO);
+        AFIO_GPxConfig(HTCFG_SDIO_DAT2_GPIO_ID, HTCFG_SDIO_DAT2_GPIO_PIN, AFIO_FUN_SDIO);
+        AFIO_GPxConfig(HTCFG_SDIO_DAT3_GPIO_ID, HTCFG_SDIO_DAT3_GPIO_PIN, AFIO_FUN_SDIO);
+        /* 配置SDIO引脚驱动能力 */
+        GPIO_DriveConfig(HTCFG_SDIO_CLK_GPIO_PORT, HTCFG_SDIO_CLK_GPIO_PIN, GPIO_DV_8MA);
+        GPIO_DriveConfig(HTCFG_SDIO_CMD_GPIO_PORT, HTCFG_SDIO_CMD_GPIO_PIN, GPIO_DV_8MA);
+        GPIO_DriveConfig(HTCFG_SDIO_DAT0_GPIO_PORT, HTCFG_SDIO_DAT0_GPIO_PIN, GPIO_DV_8MA);
+        GPIO_DriveConfig(HTCFG_SDIO_DAT1_GPIO_PORT, HTCFG_SDIO_DAT1_GPIO_PIN, GPIO_DV_8MA);
+        GPIO_DriveConfig(HTCFG_SDIO_DAT2_GPIO_PORT, HTCFG_SDIO_DAT2_GPIO_PIN, GPIO_DV_8MA);
+        GPIO_DriveConfig(HTCFG_SDIO_DAT3_GPIO_PORT, HTCFG_SDIO_DAT3_GPIO_PIN, GPIO_DV_8MA);
+
+    }
+}
+#endif /* BSP_USING_SDIO */

bsp/ht32/ht32f12366/rtconfig.h

@@ -1,29 +1,81 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
 /* RT-Thread Kernel */
 
+/* klibc options */
+
+/* rt_vsnprintf options */
+
+/* end of rt_vsnprintf options */
+
+/* rt_vsscanf options */
+
+/* end of rt_vsscanf options */
+
+/* rt_memset options */
+
+/* end of rt_memset options */
+
+/* rt_memcpy options */
+
+/* end of rt_memcpy options */
+
+/* rt_memmove options */
+
+/* end of rt_memmove options */
+
+/* rt_memcmp options */
+
+/* end of rt_memcmp options */
+
+/* rt_strstr options */
+
+/* end of rt_strstr options */
+
+/* rt_strcasecmp options */
+
+/* end of rt_strcasecmp options */
+
+/* rt_strncpy options */
+
+/* end of rt_strncpy options */
+
+/* rt_strcpy options */
+
+/* end of rt_strcpy options */
+
+/* rt_strncmp options */
+
+/* end of rt_strncmp options */
+
+/* rt_strcmp options */
+
+/* end of rt_strcmp options */
+
+/* rt_strlen options */
+
+/* end of rt_strlen options */
+
+/* rt_strnlen options */
+
+/* end of rt_strnlen options */
+/* end of klibc options */
 #define RT_NAME_MAX 8
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_HOOK_USING_FUNC_PTR
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
+#define IDLE_THREAD_STACK_SIZE 512
 
-/* kservice optimization */
+/* kservice options */
 
-#define RT_USING_DEBUG
-#define RT_DEBUGING_COLOR
-#define RT_DEBUGING_CONTEXT
+/* end of kservice options */
 
 /* Inter-Thread communication */
 
@@ -32,6 +84,7 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
 
 /* Memory Management */
 
@@ -41,12 +94,14 @@
 #define RT_MEMHEAP_FAST_MODE
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
+/* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "usart0"
 #define RT_VER_NUM 0x50200
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
 #define RT_USING_HW_ATOMIC
 #define RT_USING_CPU_FFS
 #define ARCH_ARM
@@ -76,6 +131,7 @@
 
 /* DFS: device virtual file system */
 
+/* end of DFS: device virtual file system */
 
 /* Device Drivers */
 
@@ -85,15 +141,8 @@
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_ADC
-#define RT_USING_SPI
-#define RT_USING_WDT
 #define RT_USING_PIN
-
-/* Using USB */
-
+/* end of Device Drivers */
 
 /* C/C++ and POSIX layer */
 
@@ -105,6 +154,8 @@
 #define RT_LIBC_TZ_DEFAULT_HOUR 8
 #define RT_LIBC_TZ_DEFAULT_MIN 0
 #define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
 
 /* POSIX (Portable Operating System Interface) layer */
 
@@ -114,18 +165,30 @@
 
 /* Socket is in the 'Network' category */
 
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
 
 /* Network */
 
+/* end of Network */
 
 /* Memory protection */
 
+/* end of Memory protection */
 
 /* Utilities */
 
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
 
 /* RT-Thread Utestcases */
 
+/* end of RT-Thread Utestcases */
 
 /* RT-Thread online packages */
 
@@ -136,57 +199,78 @@
 
 /* Marvell WiFi */
 
+/* end of Marvell WiFi */
 
 /* Wiced WiFi */
 
+/* end of Wiced WiFi */
 
 /* CYW43012 WiFi */
 
+/* end of CYW43012 WiFi */
 
 /* BL808 WiFi */
 
+/* end of BL808 WiFi */
 
 /* CYW43439 WiFi */
 
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
 
 /* IoT Cloud */
 
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
 
 /* security packages */
 
+/* end of security packages */
 
 /* language packages */
 
 /* JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
 /* XML: Extensible Markup Language */
 
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
 
 /* multimedia packages */
 
 /* LVGL: powerful and easy-to-use embedded GUI library */
 
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
 
 /* u8g2: a monochrome graphic library */
 
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
 
 /* tools packages */
 
+/* end of tools packages */
 
 /* system packages */
 
 /* enhanced kernel services */
 
+/* end of enhanced kernel services */
 
 /* acceleration: Assembly language or algorithmic acceleration packages */
 
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
 
 /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
 
 /* peripheral libraries and drivers */
 
@@ -194,69 +278,94 @@
 
 /* STM32 HAL & SDK Drivers */
 
+/* end of STM32 HAL & SDK Drivers */
 
 /* Infineon HAL Packages */
 
+/* end of Infineon HAL Packages */
 
 /* Kendryte SDK */
 
+/* end of Kendryte SDK */
+/* end of HAL & SDK Drivers */
 
 /* sensors drivers */
 
+/* end of sensors drivers */
 
 /* touch drivers */
 
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
 
 /* AI packages */
 
+/* end of AI packages */
 
 /* Signal Processing and Control Algorithm Packages */
 
+/* end of Signal Processing and Control Algorithm Packages */
 
 /* miscellaneous packages */
 
 /* project laboratory */
 
+/* end of project laboratory */
+
 /* samples: kernel and components samples */
 
+/* end of samples: kernel and components samples */
 
 /* entertainment: terminal games and other interesting software packages */
 
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
 
 /* Arduino libraries */
 
 
 /* Projects and Demos */
 
+/* end of Projects and Demos */
 
 /* Sensors */
 
+/* end of Sensors */
 
 /* Display */
 
+/* end of Display */
 
 /* Timing */
 
+/* end of Timing */
 
 /* Data Processing */
 
+/* end of Data Processing */
 
 /* Data Storage */
 
 /* Communication */
 
+/* end of Communication */
 
 /* Device Control */
 
+/* end of Device Control */
 
 /* Other */
 
+/* end of Other */
 
 /* Signal IO */
 
+/* end of Signal IO */
 
 /* Uncategorized */
 
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
 #define SOC_FAMILY_HT32
 #define SOC_SERIES_HT32F1
 
@@ -267,9 +376,11 @@
 #define SOC_KERNEL
 #define CORTEX_M3
 #define SOC_HT32F12366
+/* end of Chip Configuration */
 
 /* Onboard Peripheral Drivers */
 
+/* end of Onboard Peripheral Drivers */
 
 /* On-chip Peripheral Drivers */
 
@@ -277,8 +388,10 @@
 #define BSP_USING_UART
 #define BSP_USING_USART0
 #define BSP_USING_USART0_NAME "usart0"
+/* end of On-chip Peripheral Drivers */
 
 /* Board extended module Drivers */
 
+/* end of Hardware Drivers Config */
 
 #endif

bsp/ht32/ht32f12366/template.uvoptx

@@ -73,7 +73,7 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>1</tvExp>
+        <tvExp>0</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>

bsp/ht32/ht32f12366/template.uvprojx

@@ -15,8 +15,8 @@
         <TargetCommonOption>
           <Device>HT32F12366</Device>
           <Vendor>Holtek</Vendor>
-          <PackID>Holtek.HT32_DFP.1.0.19</PackID>
-          <PackURL>http://mcu.holtek.com.tw/pack</PackURL>
+          <PackID>Holtek.HT32_DFP.1.0.55</PackID>
+          <PackURL>https://mcu.holtek.com.tw/pack</PackURL>
           <Cpu>IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
@@ -332,7 +332,7 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls></MiscControls>
+              <MiscControls>--gnu</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>

bsp/ht32/ht32f52352/README.md

@@ -41,8 +41,8 @@ ESK32-30501使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F52352
 | UART | 支持  | UART0/1 |
 | SPI | 支持  | SPI0/1 |
 | I2C | 支持  | 硬件 I2C0/1 |
-| ADC | 暂不支持  |     |
-| WDT | 暂不支持  |     |
+| ADC | 支持  |     |
+| WDT | 支持  |     |
 
 ## 使用说明
 

bsp/ht32/ht32f52352/SConstruct

@@ -53,6 +53,9 @@ rtconfig.BSP_LIBRARY_TYPE = ht32_library
 # include libraries
 objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
 
+# include usb libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbd_library', 'SConscript')))
+
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
 

bsp/ht32/ht32f52352/applications/test.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2025, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -58,20 +58,29 @@ static struct rt_semaphore rx_sem;
 static rt_mutex_t task_mutex = RT_NULL; /* task mutex */
 
 /* device handle */
+#ifdef BSP_USING_UART
 static rt_device_t serial;
+#endif
+#ifdef BSP_USING_WDT
 static rt_device_t wdt_dev;
-struct rt_i2c_bus_device *i2c_dev;
+#endif
+#ifdef BSP_USING_I2C
+static struct rt_i2c_bus_device *i2c_dev;
+#endif
+#ifdef BSP_USING_SPI
 static struct rt_spi_device *spi_dev;
+#endif
 
 /* In-file function declarations */
-static void sys_run_dir(void *parameter);
-static void gpio_output_test(void *parameter);
-static void gpio_input_test(void *parameter);
-static void key_iqr_handle(void *args);
+//static void sys_run_dir(void *parameter);
+//static void gpio_output_test(void *parameter);
+//static void gpio_input_test(void *parameter);
+//static void key_iqr_handle(void *args);
 
 /* Task registration */
 int task_registration(void)
 {
+//    USB_Configuration(RT_NULL);
     /* Create a dynamic mutex */
     task_mutex = rt_mutex_create("task_mutex", RT_IPC_FLAG_FIFO);
     if (task_mutex == RT_NULL)
@@ -90,6 +99,7 @@ int task_registration(void)
 INIT_BOARD_EXPORT(task_registration);
 
 /* System operation indicator */
+#ifdef BSP_USING_GPIO
 static void sys_run_dir(void *parameter)
 {
     rt_uint32_t e;
@@ -301,7 +311,9 @@ static int gpio_input_task(int argc, char *argv[])
     return -1;
 }
 MSH_CMD_EXPORT(gpio_input_task, gpio input task operation);
+#endif
 /* uart test */
+#ifdef BSP_USING_UART
 static rt_err_t uart_iqr_handle(rt_device_t dev, rt_size_t size)
 {
     /* Serial port callback function */
@@ -396,7 +408,9 @@ static int uart_task(int argc, char *argv[])
     return ret;
 }
 MSH_CMD_EXPORT(uart_task, uart device sample);
+#endif
 /* hw/sw iic test */
+#ifdef BSP_USING_I2C
 static void i2c_thread(void *parameter)
 {
     uint8_t write_addr = 0x00;
@@ -497,7 +511,9 @@ static int i2c_task(int argc, char *argv[])
     return ret;
 }
 MSH_CMD_EXPORT(i2c_task, i2c device sample);
+#endif
 /* spi test */
+#ifdef BSP_USING_SPI
 static void spi_thread(void *parameter)
 {
     rt_uint8_t w25x_read_id = 0x9F;
@@ -584,7 +600,9 @@ static int spi_task(int argc, char *argv[])
     return ret;
 }
 MSH_CMD_EXPORT(spi_task, spi device sample);
+#endif
 /* adc test */
+#ifdef BSP_USING_ADC
 static void adc_test(void *parameter)
 {
     rt_uint32_t adc0_ch6_val,adc0_ch7_val;
@@ -640,8 +658,9 @@ static int adc_task(int argc, char *argv[])
     return -1;
 }
 MSH_CMD_EXPORT(adc_task, adc task operation);
-
+#endif
 /* wdt test */
+#ifdef BSP_USING_WDT
 static void wdt_test(void)
 {
     rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
@@ -712,5 +731,74 @@ static int wdt_task(int argc, char *argv[])
     return -1;
 }
 MSH_CMD_EXPORT(wdt_task, wdt task operation);
+#endif
+/* usbd test */
+#ifdef BSP_USING_USBD
+static void usbd_test(void *parameter)
+{
+    rt_device_t dev = RT_NULL;
+    char dev_name[] = "vcom";
+    char buf[] = "usbd vcom test!\r\n";
 
+    dev = rt_device_find(dev_name);
+
+    if (dev)
+    {
+        rt_device_open(dev, RT_DEVICE_FLAG_RDWR);
+    }
+    else
+    {
+        rt_kprintf("Device with name %s not found.\n",dev_name);
+        rt_thread_t tid = rt_thread_self();
+        rt_thread_delete(tid);
+    }
+    while (1)
+    {
+        rt_device_write(dev, 0, buf, rt_strlen(buf));
+        rt_thread_mdelay(500);
+    }
+}
+
+static int usbd_task(int argc, char *argv[])
+{
+    rt_err_t ret = -RT_ERROR;
+
+    if(argc == 2)
+    {
+        if(rt_strcmp(argv[1],"start") == 0)
+        {
+            /* Gpio input test tasks */
+            rt_thread_t usbd_vcom_task = rt_thread_create("usbd_vcom_task",
+                                            usbd_test, RT_NULL,
+                                            THREAD_STACK_SIZE,
+                                            THREAD_PRIORITY, THREAD_TIMESLICE);
+            if (usbd_vcom_task != RT_NULL)
+            {
+                rt_thread_startup(usbd_vcom_task);
+                rt_kprintf("The usbd vcom task is registered.\n");
+            }
+            else
+            {
+                rt_kprintf("usbd vcom task registration failed.\n");
+            }
+            ret = RT_EOK;
+        }
+        else if(rt_strcmp(argv[1],"stop") == 0)
+        {
+            ret = RT_EOK;
+        }
+    }
+    else
+    {
+        rt_kprintf("Necessary parameters are missing.\n");
+        rt_kprintf("You can use the following commands.\n");
+        rt_kprintf("%s start\n",__func__);
+        rt_kprintf("%s stop\n",__func__);
+    }
+    return ret;
+}
+MSH_CMD_EXPORT(usbd_task, usbd task operation);
+
+
+#endif
 #endif /* BSP_USING_TEST */

bsp/ht32/ht32f52352/board/Kconfig

@@ -306,6 +306,140 @@ menu "On-chip Peripheral Drivers"
         depends on BSP_USING_WDT
         string "wdt device name"
         default "wdt"
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        depends on SOC_HT32F53241 || SOC_HT32F53242 || SOC_HT32F53252
+        default n
+        select RT_USING_CAN if BSP_USING_CAN
+        config BSP_USING_CAN_NAME
+        depends on BSP_USING_CAN
+        string "can device name"
+        default "can"
+        if BSP_USING_CAN
+            config CAN_DEFAULT_BASE_CONFIGURATION  
+                choice
+                    prompt "Default CAN baud rate"
+                    default BSP_USING_CAN500kBaud
+                    config BSP_USING_CAN1MBaud
+                        bool "CAN1MBaud"
+                    config BSP_USING_CAN800kBaud
+                        bool "CAN800kBaud"
+                    config BSP_USING_CAN500kBaud
+                        bool "CAN500kBaud"
+                    config BSP_USING_CAN250kBaud
+                        bool "CAN250kBaud"
+                    config BSP_USING_CAN125kBaud
+                        bool "CAN125kBaud"
+                    config BSP_USING_CAN100kBaud
+                        bool "CAN100kBaud"
+                    config BSP_USING_CAN50kBaud
+                        bool "CAN50kBaud"
+                    config BSP_USING_CAN20kBaud
+                        bool "CAN20kBaud"
+                    config BSP_USING_CAN10kBaud
+                        bool "CAN10kBaud"
+                endchoice
+                choice
+                    prompt "Default CAN mode"
+                    default BSP_USING_RT_CAN_MODE_NORMAL
+                    config BSP_USING_RT_CAN_MODE_NORMAL
+                        bool "RT_CAN_MODE_NORMAL"
+                    config BSP_USING_RT_CAN_MODE_LISTEN
+                        bool "RT_CAN_MODE_LISTEN"
+                    config BSP_USING_RT_CAN_MODE_LOOPBACK
+                        bool "RT_CAN_MODE_LOOPBACK"
+                    config BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN
+                        bool "RT_CAN_MODE_LOOPBACKANLISTEN"
+                endchoice
+
+                config BSP_USING_CAN_BAUD
+                int
+                default 1000000 if BSP_USING_CAN1MBaud
+                default 800000 if BSP_USING_CAN800kBaud
+                default 500000 if BSP_USING_CAN500kBaud
+                default 250000 if BSP_USING_CAN250kBaud
+                default 125000 if BSP_USING_CAN125kBaud
+                default 100000 if BSP_USING_CAN100kBaud
+                default 50000 if BSP_USING_CAN50kBaud
+                default 20000 if BSP_USING_CAN20kBaud
+                default 10000 if BSP_USING_CAN10kBaud
+
+                config BSP_USING_CAN_MODE
+                int
+                default 0 if BSP_USING_RT_CAN_MODE_NORMAL
+                default 1 if BSP_USING_RT_CAN_MODE_LISTEN
+                default 2 if BSP_USING_RT_CAN_MODE_LOOPBACK
+                default 3 if BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN
+            
+            config CAN_DEFAULT_FILTER_TABLE_CONFIGURATION
+                choice
+                    prompt "Default filter id mode"
+                    default BSP_USING_CAN_STD_ID
+                    config BSP_USING_CAN_STD_ID
+                        bool "CAN_STD_ID"
+                    config BSP_USING_CAN_EXT_ID
+                        bool "CAN_EXT_ID"
+                endchoice
+
+                choice
+                    prompt "Default filter frame mode"
+                    default BSP_USING_CAN_DATA_FRAME
+                    config BSP_USING_CAN_DATA_FRAME
+                        bool "CAN_DATA_FRAME"
+                    config BSP_USING_CAN_REMOTE_FRAME
+                        bool "CAN_REMOTE_FRAME"
+                endchoice
+
+                config BSP_USING_CAN_ID_MODE
+                int
+                default 0 if BSP_USING_CAN_STD_ID
+                default 1 if BSP_USING_CAN_EXT_ID
+
+                config BSP_USING_CAN_FRAME_MODE
+                int
+                default 0 if BSP_USING_CAN_REMOTE_FRAME
+                default 1 if BSP_USING_CAN_DATA_FRAME
+
+                config BSP_USING_CAN_MSG_NUM
+                int "Default filter table number"
+                range 0 31
+                default 0
+
+                config BSP_USING_CAN_ID
+                hex "Default filter arbitration bit(ID)"
+                range 0 0x7FF if BSP_USING_CAN_STD_ID
+                default 0x541 if BSP_USING_CAN_STD_ID
+                range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+                default 0x541 if BSP_USING_CAN_EXT_ID
+
+                config BSP_USING_CAN_MASK
+                hex "Default filter mask bit(MASK)"
+                range 0 0x7FF if BSP_USING_CAN_STD_ID
+                default 0x7FF if BSP_USING_CAN_STD_ID
+                range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+                default 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+
+        endif
+
+    menuconfig BSP_USING_SDIO
+        bool "Enable SDIO"
+        depends on SOC_HT32F12345 || SOC_HT32F12365 || SOC_HT32F12366
+        default n
+        select RT_USING_SDIO if BSP_USING_SDIO
+        config BSP_USING_SDIO_NAME
+        depends on BSP_USING_SDIO
+        string "sdio device name"
+        default "sdio"
+
+    menuconfig BSP_USING_USBD
+        bool "Enable USB BUS"
+        default n
+        select RT_USING_USB_DEVICE if BSP_USING_USBD
+        config BSP_USING_USBD_NAME
+        depends on BSP_USING_USBD
+        string "usbd device name"
+        default "usbd"
 endmenu
 
 menu "Board extended module Drivers"

bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h

@@ -58,7 +58,7 @@
 //    <o0.13> Endpoint5 Interrupt Enable (EP5IE)
 //    <o0.14> Endpoint6 Interrupt Enable (EP6IE)
 //    <o0.15> Endpoint7 Interrupt Enable (EP7IE)
-#define _UIER               (0x011D)
+#define _UIER               (0xFF1D)
 //  </h>
 
 
@@ -96,7 +96,7 @@
 /* Endpoint1 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint1 Configuration
-#define _EP1_ENABLE         (0)
+#define _EP1_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -114,7 +114,7 @@
 //    <o0> Endpoint Transfer Type
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP1_TYPR           (3)
+#define _EP1_TYPR           (2)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -123,7 +123,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
                             /* Maximum: 64 Bytes                                                            */
-#define _EP1LEN_TMP         (8)
+#define _EP1LEN_TMP         (64)
 
 //    <h> Endpoint Interrupt Enable Settings (EPIER)
 //      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
@@ -135,7 +135,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP1_IER            (0x10)
+#define _EP1_IER            (0x12)
 // </h>
 // </e>
 
@@ -144,7 +144,7 @@
 /* Endpoint2 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint2 Configuration
-#define _EP2_ENABLE         (0)
+#define _EP2_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -162,7 +162,7 @@
 //    <o0> Endpoint Transfer Type
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP2_TYPR           (3)
+#define _EP2_TYPR           (2)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -171,7 +171,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
                             /* Maximum: 64 Bytes                                                            */
-#define _EP2LEN_TMP         (8)
+#define _EP2LEN_TMP         (64)
 
 //    <h> Endpoint Interrupt Enable Settings (EPIER)
 //      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
@@ -183,7 +183,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP2_IER            (0x002)
+#define _EP2_IER            (0x012)
 // </h>
 // </e>
 
@@ -191,7 +191,7 @@
 /* Endpoint3 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint3 Configuration
-#define _EP3_ENABLE         (0)
+#define _EP3_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -218,7 +218,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
                             /* Maximum: 64 Bytes                                                            */
-#define _EP3LEN_TMP         (8)
+#define _EP3LEN_TMP         (64)
 
 //    <h> Endpoint Interrupt Enable Settings (EPIER)
 //      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
@@ -230,7 +230,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP3_IER            (0x10)
+#define _EP3_IER            (0x12)
 // </h>
 // </e>
 
@@ -238,7 +238,7 @@
 /* Endpoint4 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint4 Configuration
-#define _EP4_ENABLE         (0)
+#define _EP4_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -266,7 +266,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP4LEN_TMP         (8)
+#define _EP4LEN_TMP         (64)
 
 //    <o0> Single/Double Buffer Selection (SDBS)
 //      <0=> Single Buffer
@@ -283,7 +283,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP4_IER            (0x02)
+#define _EP4_IER            (0x12)
 // </h>
 // </e>
 
@@ -292,7 +292,7 @@
 /* Endpoint5 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint5 Configuration
-#define _EP5_ENABLE         (0)
+#define _EP5_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -311,7 +311,7 @@
 //      <1=> Isochronous
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP5_TYPR           (3)
+#define _EP5_TYPR           (1)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -320,7 +320,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP5LEN_TMP         (8)
+#define _EP5LEN_TMP         (64)
 
 
 //    <o0> Single/Double Buffer Selection (SDBS)
@@ -338,7 +338,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP5_IER            (0x10)
+#define _EP5_IER            (0x12)
 // </h>
 // </e>
 
@@ -347,7 +347,7 @@
 /* Endpoint6 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint6 Configuration
-#define _EP6_ENABLE         (0)
+#define _EP6_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -366,7 +366,7 @@
 //      <1=> Isochronous
 //      <2=> Bulk
 //      <3=> Interrupt
-#define _EP6_TYPR           (3)
+#define _EP6_TYPR           (1)
 
 //    <o0> Endpoint Direction (EPDIR)
 //      <1=> IN
@@ -375,7 +375,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP6LEN_TMP         (8)
+#define _EP6LEN_TMP         (64)
 
 //    <o0> Single/Double Buffer Selection (SDBS)
 //      <0=> Single Buffer
@@ -392,7 +392,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP6_IER            (0x02)
+#define _EP6_IER            (0x12)
 // </h>
 // </e>
 
@@ -401,7 +401,7 @@
 /* Endpoint7 Configuration Setting                                                                          */
 /*----------------------------------------------------------------------------------------------------------*/
 //  <e0> Endpoint7 Configuration
-#define _EP7_ENABLE         (0)
+#define _EP7_ENABLE         (1)
 
 //    <o0> Endpoint Address (EPADR)
 //      <1=> 1
@@ -429,7 +429,7 @@
 
 //    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
                             /* Maximum: 1000 Bytes                                                          */
-#define _EP7LEN_TMP         (8)
+#define _EP7LEN_TMP         (64)
 
 //    <o0> Single/Double Buffer Selection (SDBS)
 //      <0=> Single Buffer
@@ -446,7 +446,7 @@
 //      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
 //      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
 //      <o0.7> USB Error Interrupt Enable (UERIE)
-#define _EP7_IER            (0x10)
+#define _EP7_IER            (0x12)
 // </h>
 // </e>
 

bsp/ht32/ht32f52352/rtconfig.h

@@ -1,26 +1,81 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
 /* RT-Thread Kernel */
 
+/* klibc options */
+
+/* rt_vsnprintf options */
+
+/* end of rt_vsnprintf options */
+
+/* rt_vsscanf options */
+
+/* end of rt_vsscanf options */
+
+/* rt_memset options */
+
+/* end of rt_memset options */
+
+/* rt_memcpy options */
+
+/* end of rt_memcpy options */
+
+/* rt_memmove options */
+
+/* end of rt_memmove options */
+
+/* rt_memcmp options */
+
+/* end of rt_memcmp options */
+
+/* rt_strstr options */
+
+/* end of rt_strstr options */
+
+/* rt_strcasecmp options */
+
+/* end of rt_strcasecmp options */
+
+/* rt_strncpy options */
+
+/* end of rt_strncpy options */
+
+/* rt_strcpy options */
+
+/* end of rt_strcpy options */
+
+/* rt_strncmp options */
+
+/* end of rt_strncmp options */
+
+/* rt_strcmp options */
+
+/* end of rt_strcmp options */
+
+/* rt_strlen options */
+
+/* end of rt_strlen options */
+
+/* rt_strnlen options */
+
+/* end of rt_strnlen options */
+/* end of klibc options */
 #define RT_NAME_MAX 8
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_HOOK_USING_FUNC_PTR
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
+#define IDLE_THREAD_STACK_SIZE 512
 
-/* kservice optimization */
+/* kservice options */
 
+/* end of kservice options */
 
 /* Inter-Thread communication */
 
@@ -29,6 +84,7 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
 
 /* Memory Management */
 
@@ -38,12 +94,14 @@
 #define RT_MEMHEAP_FAST_MODE
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
+/* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "usart1"
 #define RT_VER_NUM 0x50200
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M0
@@ -52,7 +110,7 @@
 
 #define RT_USING_COMPONENTS_INIT
 #define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_STACK_SIZE 1024
 #define RT_MAIN_THREAD_PRIORITY 10
 #define RT_USING_MSH
 #define RT_USING_FINSH
@@ -71,6 +129,7 @@
 
 /* DFS: device virtual file system */
 
+/* end of DFS: device virtual file system */
 
 /* Device Drivers */
 
@@ -79,15 +138,8 @@
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_ADC
-#define RT_USING_SPI
-#define RT_USING_WDT
 #define RT_USING_PIN
-
-/* Using USB */
-
+/* end of Device Drivers */
 
 /* C/C++ and POSIX layer */
 
@@ -99,6 +151,8 @@
 #define RT_LIBC_TZ_DEFAULT_HOUR 8
 #define RT_LIBC_TZ_DEFAULT_MIN 0
 #define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
 
 /* POSIX (Portable Operating System Interface) layer */
 
@@ -108,18 +162,30 @@
 
 /* Socket is in the 'Network' category */
 
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
 
 /* Network */
 
+/* end of Network */
 
 /* Memory protection */
 
+/* end of Memory protection */
 
 /* Utilities */
 
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
 
 /* RT-Thread Utestcases */
 
+/* end of RT-Thread Utestcases */
 
 /* RT-Thread online packages */
 
@@ -130,57 +196,78 @@
 
 /* Marvell WiFi */
 
+/* end of Marvell WiFi */
 
 /* Wiced WiFi */
 
+/* end of Wiced WiFi */
 
 /* CYW43012 WiFi */
 
+/* end of CYW43012 WiFi */
 
 /* BL808 WiFi */
 
+/* end of BL808 WiFi */
 
 /* CYW43439 WiFi */
 
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
 
 /* IoT Cloud */
 
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
 
 /* security packages */
 
+/* end of security packages */
 
 /* language packages */
 
 /* JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
 /* XML: Extensible Markup Language */
 
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
 
 /* multimedia packages */
 
 /* LVGL: powerful and easy-to-use embedded GUI library */
 
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
 
 /* u8g2: a monochrome graphic library */
 
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
 
 /* tools packages */
 
+/* end of tools packages */
 
 /* system packages */
 
 /* enhanced kernel services */
 
+/* end of enhanced kernel services */
 
 /* acceleration: Assembly language or algorithmic acceleration packages */
 
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
 
 /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
 
 /* peripheral libraries and drivers */
 
@@ -188,69 +275,94 @@
 
 /* STM32 HAL & SDK Drivers */
 
+/* end of STM32 HAL & SDK Drivers */
 
 /* Infineon HAL Packages */
 
+/* end of Infineon HAL Packages */
 
 /* Kendryte SDK */
 
+/* end of Kendryte SDK */
+/* end of HAL & SDK Drivers */
 
 /* sensors drivers */
 
+/* end of sensors drivers */
 
 /* touch drivers */
 
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
 
 /* AI packages */
 
+/* end of AI packages */
 
 /* Signal Processing and Control Algorithm Packages */
 
+/* end of Signal Processing and Control Algorithm Packages */
 
 /* miscellaneous packages */
 
 /* project laboratory */
 
+/* end of project laboratory */
+
 /* samples: kernel and components samples */
 
+/* end of samples: kernel and components samples */
 
 /* entertainment: terminal games and other interesting software packages */
 
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
 
 /* Arduino libraries */
 
 
 /* Projects and Demos */
 
+/* end of Projects and Demos */
 
 /* Sensors */
 
+/* end of Sensors */
 
 /* Display */
 
+/* end of Display */
 
 /* Timing */
 
+/* end of Timing */
 
 /* Data Processing */
 
+/* end of Data Processing */
 
 /* Data Storage */
 
 /* Communication */
 
+/* end of Communication */
 
 /* Device Control */
 
+/* end of Device Control */
 
 /* Other */
 
+/* end of Other */
 
 /* Signal IO */
 
+/* end of Signal IO */
 
 /* Uncategorized */
 
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
 #define SOC_FAMILY_HT32
 #define SOC_SERIES_HT32F5
 
@@ -261,9 +373,11 @@
 #define SOC_KERNEL
 #define CORTEX_M0
 #define SOC_HT32F52352
+/* end of Chip Configuration */
 
 /* Onboard Peripheral Drivers */
 
+/* end of Onboard Peripheral Drivers */
 
 /* On-chip Peripheral Drivers */
 
@@ -271,8 +385,10 @@
 #define BSP_USING_UART
 #define BSP_USING_USART1
 #define BSP_USING_USART1_NAME "usart1"
+/* end of On-chip Peripheral Drivers */
 
 /* Board extended module Drivers */
 
+/* end of Hardware Drivers Config */
 
 #endif

bsp/ht32/ht32f52352/template.uvprojx

@@ -15,8 +15,8 @@
         <TargetCommonOption>
           <Device>HT32F52352</Device>
           <Vendor>Holtek</Vendor>
-          <PackID>Holtek.HT32_DFP.1.0.19</PackID>
-          <PackURL>http://mcu.holtek.com.tw/pack</PackURL>
+          <PackID>Holtek.HT32_DFP.1.0.55</PackID>
+          <PackURL>https://mcu.holtek.com.tw/pack</PackURL>
           <Cpu>IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
@@ -332,7 +332,7 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls></MiscControls>
+              <MiscControls>--gnu</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>

bsp/ht32/ht32f53252/.ci/attachconfig/ci.attachconfig.yml

@@ -0,0 +1,18 @@
+devices.strict:
+    depend_scons_arg:
+      - '--strict'
+devices.gpio:
+    depends:
+      - devices.strict
+    kconfig:
+      - CONFIG_BSP_USING_GPIO=y
+devices.uart:
+    kconfig:
+      - CONFIG_BSP_USING_UART=y
+      - CONFIG_BSP_USING_USART1=y
+# ------ SEGGER CI ------
+segger:
+    kconfig:
+      - CONFIG_BSP_USING_GPIO=y
+      - CONFIG_BSP_USING_UART=y
+      - CONFIG_BSP_USING_USART1=y

bsp/ht32/ht32f53252/Kconfig

@@ -0,0 +1,12 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+rsource "board/Kconfig"

bsp/ht32/ht32f53252/README.md

@@ -0,0 +1,108 @@
+# HT32F53252 BSP 说明
+
+## 简介
+
+ESK32-30522是合泰基于HT32F53252芯片并针对Cortex®-M0+入门而设计的评估板。本文档是为ESK32-30522开发板提供的BSP(板级支持包)说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+## 开发板介绍
+
+ESK32-30522使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F53252，针对Cortex®-M0+入门而设计。开发板外观如下图所示：
+
+![board.png](figures/board.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：HT32F53252，主频 60MHz，128KB FLASH ，16KB SRAM
+- 常用外设
+    - LED：2个，（绿色，PC14、PC15）
+- 常用接口：USB 转串口 、USB SLAVE
+- 调试接口：板载的 e-Link32 Lite SWD 下载
+
+开发板更多详细信息请参考合泰官网的相关文档[ESK32-30522](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30522)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注** |
+| :--- | :---: | :--- |
+| USB 转串口 | 支持  | 使用 USART1 |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO | 支持  | PA0, PA1...PD3 ---> PIN: 0, 1...51 |
+| USART | 支持  | USART0/1 |
+| UART | 支持  | UART0/1 |
+| SPI | 支持  | SPI0/1 |
+| I2C | 支持  | 硬件 I2C0/1 |
+| ADC | 暂不支持  |     |
+| WDT | 暂不支持  |     |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+    
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+    
+- 进阶使用
+    
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。
+    
+
+### 快速上手
+
+本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。
+
+连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
+
+> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.1.0 build Apr 10 2024 14:39:43
+ 2006 - 2024 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 USART1 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1.  在 bsp 下打开 env 工具。
+    
+2.  输入`menuconfig`命令配置工程，配置好之后保存退出。
+  
+3.  输入`scons --target=mdk5` 命令重新生成工程。
+
+## 注意事项
+
+开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。
+
+## 联系人信息
+
+维护人:
+
+- [QT-one](https://github.com/QT-one)

bsp/ht32/ht32f53252/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os                   #包含os库
+Import('RTT_ROOT')          #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包）
+from building import *      #把building模块的所有内容都导入到当前模块中
+
+cwd = GetCurrentDir()       #获取当前路径，并将该路径信息保存到变量cwd中
+objs = []                   #创建一个list型变量objs
+list = os.listdir(cwd)      #得到当前目录下的所有子目录，并保存到变量list中
+
+for d in list:              #for循环用d记录循环的次数，直到寻遍所有路径
+    path = os.path.join(cwd, d)            #根据d获取到不同的路径
+    if os.path.isfile(os.path.join(path, 'SConscript')):       #如果该路径下存在名为SConscript的文件
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))     #将路径中SConscript文件内的源码读取到objs中
+
+Return('objs')              #将objs返回出去

bsp/ht32/ht32f53252/SConstruct

@@ -0,0 +1,63 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ht32_library = 'HT32_STD_5xxxx_FWLib' 
+rtconfig.BSP_LIBRARY_TYPE = ht32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
+
+# include usb libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbd_library', 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/ht32/ht32f53252/applications/SConscript

@@ -0,0 +1,26 @@
+#导入其他模块的变量
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#导入使用到的模块
+from building import *
+
+#获取当前目录的路径
+cwd = GetCurrentDir()
+
+#创建一个列表，用于保存需要使用到的C文件路径
+#src = Glob('*.c')
+src = Split("""
+main.c
+""")
+if GetDepend(['BSP_USING_TEST']):
+    src += ['test.c']
+
+#创建一个列表，用于保存需要包含的H文件路径
+path = [cwd]
+
+#创建一个组别
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+#返回创建好的组别
+Return('group')

bsp/ht32/ht32f53252/applications/main.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-04-08     QT-one       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+
+/* defined the led1 pin: pc14 */
+#define LED1_PIN    GET_PIN(C, 14)
+/* defined the led2 pin: pc15 */
+#define LED2_PIN    GET_PIN(C, 15)
+
+int main(void)
+{
+    rt_uint32_t speed = 200;
+    /* set led1 pin mode to output */
+    rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+    /* set led2 pin mode to output */
+    rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED1_PIN, PIN_LOW);
+        rt_pin_write(LED2_PIN, PIN_HIGH);
+        rt_thread_mdelay(speed);
+        rt_pin_write(LED1_PIN, PIN_HIGH);
+        rt_pin_write(LED2_PIN, PIN_LOW);
+        rt_thread_mdelay(speed);
+    }
+}

bsp/ht32/ht32f53252/board/Kconfig

@@ -0,0 +1,449 @@
+menu "Hardware Drivers Config"
+
+menu "Chip Configuration"
+    config SOC_KERNEL
+        bool
+        select SOC_SERIES_HT32F5 if CORTEX_M0
+        select SOC_SERIES_HT32F1 if CORTEX_M3
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
+        default y
+        choice
+            prompt "Select the kernel"
+            default CORTEX_M0
+            config CORTEX_M0
+                bool "CORTEX_M0"
+            config CORTEX_M3
+                bool "CORTEX_M3" 
+        endchoice
+
+    choice
+        prompt "Select the chip you are using"
+        depends on CORTEX_M0
+        default HT32F52352
+            config SOC_HT32F0006
+                bool "HT32F0006"
+            config SOC_HT32F0008
+                bool "HT32F0008"
+            config SOC_HT32F50241
+                bool "HT32F50241"
+            config SOC_HT32F50343
+                bool "HT32F50343"
+            config SOC_HT32F50441
+                bool "HT32F50441"
+            config SOC_HT32F50452
+                bool "HT32F50452"
+            config SOC_HT32F52241
+                bool "HT32F52241"
+            config SOC_HT32F52244
+                bool "HT32F52244"
+            config SOC_HT32F52253
+                bool "HT32F52253"
+            config SOC_HT32F52341
+                bool "HT32F52341"
+            config SOC_HT32F52352
+                bool "HT32F52352"
+            config SOC_HT32F52354
+                bool "HT32F52354"
+            config SOC_HT32F52367
+                bool "HT32F52367"
+            config SOC_HT32F53241
+                bool "HT32F53241"
+            config SOC_HT32F53252
+                bool "HT32F53252"
+            config SOC_HT32F54241
+                bool "HT32F54241"
+            config SOC_HT32F54253
+                bool "HT32F54253"
+            config SOC_HT32F57341
+                bool "HT32F57341"
+            config SOC_HT32F57352
+                bool "HT32F57352"
+            config SOC_HT32F5828
+                bool "HT32F5828"
+            config SOC_HT32F59041
+                bool "HT32F59041"
+            config SOC_HT32F59741
+                bool "HT32F59741"
+            config SOC_HT32F61141
+                bool "HT32F61141"
+            config SOC_HT32F61245
+                bool "HT32F61245"
+            config SOC_HT32F61355
+                bool "HT32F61355"
+            config SOC_HT32F61356
+                bool "HT32F61356"
+            config SOC_HT32F61357
+                bool "HT32F61357"
+            config SOC_HT32F61641
+                bool "HT32F61641"
+            config SOC_HT32F65240
+                bool "HT32F65240"
+            config SOC_HT32F67051
+                bool "HT32F67051"
+            config SOC_HT32F67741
+                bool "HT32F67741"
+    endchoice
+    
+    choice
+        prompt "Select the chip you are using"
+        depends on CORTEX_M3
+        default HT32F52352
+        config SOC_HT32F1654
+            bool "HT32F1654"
+        config SOC_HT32F1656
+            bool "HT32F1656"
+        config SOC_HT32F12345
+            bool "HT32F12345"
+        config SOC_HT32F12364
+            bool "HT32F12364"
+        config SOC_HT32F12366
+            bool "HT32F12366"
+    endchoice
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_TEST
+        bool "Enable test"
+        default n
+
+    if RT_USING_CONSOLE
+		config RT_CONSOLE_DEVICE_NAME
+		string "the device name for console"
+		default "usart1"
+	endif
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN if BSP_USING_GPIO
+        default n
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default n
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_USART0
+                bool "Enable USART0"
+                default n
+                config BSP_USING_USART0_NAME
+                depends on BSP_USING_USART0
+                string "usart0 bus name"
+                default "usart0"
+
+            config BSP_USING_USART1
+                bool "Enable USART1"
+                default n
+                config BSP_USING_USART1_NAME
+                depends on BSP_USING_USART1
+                string "usart1 bus name"
+                default "usart1"
+
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+                config BSP_USING_UART0_NAME
+                depends on BSP_USING_UART0
+                string "uart0 bus name"
+                default "uart0"
+
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+                config BSP_USING_UART1_NAME
+                depends on BSP_USING_UART1
+                string "uart1 bus name"
+                default "uart1"
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI Bus"
+        default n
+        select RT_USING_SPI if BSP_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0 Bus"
+                default n
+                config BSP_USING_SPI0_NAME
+                depends on BSP_USING_SPI0
+                string "spi0 bus name"
+                default "spi0"
+
+            config BSP_USING_SPI1
+                bool "Enable SPI1 Bus"
+                default n
+                config BSP_USING_SPI1_NAME
+                depends on BSP_USING_SPI1
+                string "spi1 bus name"
+                default "spi1"
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C Bus"
+        default n
+        if BSP_USING_I2C
+            menuconfig BSP_USING_I2C_HW
+                bool "Enable I2C Bus(hardware)"
+                default n
+                select RT_USING_I2C if BSP_USING_I2C_HW
+                if BSP_USING_I2C_HW
+                    config BSP_USING_I2C0_HW
+                    bool "Enable Hardware I2C0 Bus"
+                    default n
+                    config BSP_USING_I2C0_HW_NAME
+                    depends on BSP_USING_I2C0_HW
+                    string "hardware i2c0 name"
+                    default "hw_i2c0"
+
+                    config BSP_USING_I2C1_HW
+                    bool "Enable Hardware I2C1 Bus"
+                    default n
+                    config BSP_USING_I2C1_HW_NAME
+                    depends on BSP_USING_I2C1_HW
+                    string "hardware i2c1 name"
+                    default "hw_i2c1"
+                endif
+
+            menuconfig BSP_USING_I2C_SW
+                bool "Enable I2C Bus(software)"
+                default n
+                select BSP_USING_GPIO if BSP_USING_I2C_SW
+                select RT_USING_I2C if BSP_USING_I2C_SW
+                
+                if BSP_USING_I2C_SW
+                    config BSP_USING_I2C0_SW
+                    bool "Enable Software I2C0 Bus"
+                    default n
+                    config BSP_USING_I2C0_SW_NAME
+                    depends on BSP_USING_I2C0_SW
+                    string "software i2c0 name"
+                    default "sw_i2c0"
+                    if BSP_USING_I2C0_SW
+                            config BSP_I2C0_SLC_PIN
+                            int "i2c0 slc pin number"
+                            range 0 51
+                            default 22
+
+                            config BSP_I2C0_SDA_PIN
+                            int "i2c0 sda pin number"
+                            range 0 51
+                            default 23
+                    endif
+                    
+                    config BSP_USING_I2C1_SW
+                    bool "Enable Software I2C1 Bus"
+                    default n
+                    config BSP_USING_I2C1_SW_NAME
+                    depends on BSP_USING_I2C1_SW
+                    string "software i2c1 name"
+                    default "sw_i2c1"
+                    if BSP_USING_I2C1_SW
+                            config BSP_I2C1_SLC_PIN
+                            int "i2c1 slc pin number"
+                            range 0 51
+                            default 24
+
+                            config BSP_I2C1_SDA_PIN
+                            int "i2c1 sda pin number"
+                            range 0 51
+                            default 25
+                    endif
+                    
+                    config BSP_USING_I2C2_SW
+                    bool "Enable Software I2C2 Bus"
+                    default n
+                    config BSP_USING_I2C2_SW_NAME
+                    depends on BSP_USING_I2C2_SW
+                    string "software i2c2 name"
+                    default "sw_i2c2"
+                    if BSP_USING_I2C2_SW
+                            config BSP_I2C2_SLC_PIN
+                            int "i2c2 slc pin number"
+                            range 0 51
+                            default 26
+
+                            config BSP_I2C2_SDA_PIN
+                            int "i2c2 sda pin number"
+                            range 0 51
+                            default 27
+                    endif
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC if BSP_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC0
+            bool "Enable ADC0"
+            default n
+            config BSP_USING_ADC0_NAME
+            depends on BSP_USING_ADC0
+            string "adc0 device name"
+            default "adc0"
+
+            config BSP_USING_ADC1
+            bool "Enable ADC1"
+            depends on SOC_HT32F65240
+            default n
+            config BSP_USING_ADC1_NAME
+            depends on BSP_USING_ADC1
+            string "adc1 device name"
+            default "adc1"
+        endif
+
+    menuconfig BSP_USING_WDT
+        bool "Enable WDT"
+        default n
+        select RT_USING_WDT if BSP_USING_WDT
+        config BSP_USING_WDT_NAME
+        depends on BSP_USING_WDT
+        string "wdt device name"
+        default "wdt"
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        depends on SOC_HT32F53241 || SOC_HT32F53242 || SOC_HT32F53252
+        default n
+        select RT_USING_CAN if BSP_USING_CAN
+        config BSP_USING_CAN_NAME
+        depends on BSP_USING_CAN
+        string "can device name"
+        default "can"
+        if BSP_USING_CAN
+            config CAN_DEFAULT_BASE_CONFIGURATION  
+                choice
+                    prompt "Default CAN baud rate"
+                    default BSP_USING_CAN500kBaud
+                    config BSP_USING_CAN1MBaud
+                        bool "CAN1MBaud"
+                    config BSP_USING_CAN800kBaud
+                        bool "CAN800kBaud"
+                    config BSP_USING_CAN500kBaud
+                        bool "CAN500kBaud"
+                    config BSP_USING_CAN250kBaud
+                        bool "CAN250kBaud"
+                    config BSP_USING_CAN125kBaud
+                        bool "CAN125kBaud"
+                    config BSP_USING_CAN100kBaud
+                        bool "CAN100kBaud"
+                    config BSP_USING_CAN50kBaud
+                        bool "CAN50kBaud"
+                    config BSP_USING_CAN20kBaud
+                        bool "CAN20kBaud"
+                    config BSP_USING_CAN10kBaud
+                        bool "CAN10kBaud"
+                endchoice
+                choice
+                    prompt "Default CAN mode"
+                    default BSP_USING_RT_CAN_MODE_NORMAL
+                    config BSP_USING_RT_CAN_MODE_NORMAL
+                        bool "RT_CAN_MODE_NORMAL"
+                    config BSP_USING_RT_CAN_MODE_LISTEN
+                        bool "RT_CAN_MODE_LISTEN"
+                    config BSP_USING_RT_CAN_MODE_LOOPBACK
+                        bool "RT_CAN_MODE_LOOPBACK"
+                    config BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN
+                        bool "RT_CAN_MODE_LOOPBACKANLISTEN"
+                endchoice
+
+                config BSP_USING_CAN_BAUD
+                int
+                default 1000000 if BSP_USING_CAN1MBaud
+                default 800000 if BSP_USING_CAN800kBaud
+                default 500000 if BSP_USING_CAN500kBaud
+                default 250000 if BSP_USING_CAN250kBaud
+                default 125000 if BSP_USING_CAN125kBaud
+                default 100000 if BSP_USING_CAN100kBaud
+                default 50000 if BSP_USING_CAN50kBaud
+                default 20000 if BSP_USING_CAN20kBaud
+                default 10000 if BSP_USING_CAN10kBaud
+
+                config BSP_USING_CAN_MODE
+                int
+                default 0 if BSP_USING_RT_CAN_MODE_NORMAL
+                default 1 if BSP_USING_RT_CAN_MODE_LISTEN
+                default 2 if BSP_USING_RT_CAN_MODE_LOOPBACK
+                default 3 if BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN
+            
+            config CAN_DEFAULT_FILTER_TABLE_CONFIGURATION
+                choice
+                    prompt "Default filter id mode"
+                    default BSP_USING_CAN_STD_ID
+                    config BSP_USING_CAN_STD_ID
+                        bool "CAN_STD_ID"
+                    config BSP_USING_CAN_EXT_ID
+                        bool "CAN_EXT_ID"
+                endchoice
+
+                choice
+                    prompt "Default filter frame mode"
+                    default BSP_USING_CAN_DATA_FRAME
+                    config BSP_USING_CAN_DATA_FRAME
+                        bool "CAN_DATA_FRAME"
+                    config BSP_USING_CAN_REMOTE_FRAME
+                        bool "CAN_REMOTE_FRAME"
+                endchoice
+
+                config BSP_USING_CAN_ID_MODE
+                int
+                default 0 if BSP_USING_CAN_STD_ID
+                default 1 if BSP_USING_CAN_EXT_ID
+
+                config BSP_USING_CAN_FRAME_MODE
+                int
+                default 0 if BSP_USING_CAN_REMOTE_FRAME
+                default 1 if BSP_USING_CAN_DATA_FRAME
+
+                config BSP_USING_CAN_MSG_NUM
+                int "Default filter table number"
+                range 0 31
+                default 0
+
+                config BSP_USING_CAN_ID
+                hex "Default filter arbitration bit(ID)"
+                range 0 0x7FF if BSP_USING_CAN_STD_ID
+                default 0x541 if BSP_USING_CAN_STD_ID
+                range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+                default 0x541 if BSP_USING_CAN_EXT_ID
+
+                config BSP_USING_CAN_MASK
+                hex "Default filter mask bit(MASK)"
+                range 0 0x7FF if BSP_USING_CAN_STD_ID
+                default 0x7FF if BSP_USING_CAN_STD_ID
+                range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+                default 0x1FFFFFFF if BSP_USING_CAN_EXT_ID
+
+        endif
+
+    menuconfig BSP_USING_SDIO
+        bool "Enable SDIO"
+        depends on SOC_HT32F12345 || SOC_HT32F12365 || SOC_HT32F12366
+        default n
+        select RT_USING_SDIO if BSP_USING_SDIO
+        config BSP_USING_SDIO_NAME
+        depends on BSP_USING_SDIO
+        string "sdio device name"
+        default "sdio"
+
+    menuconfig BSP_USING_USBD
+        bool "Enable USB BUS"
+        default n
+        select RT_USING_USB_DEVICE if BSP_USING_USBD
+        config BSP_USING_USBD_NAME
+        depends on BSP_USING_USBD
+        string "usbd device name"
+        default "usbd"
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/ht32/ht32f53252/board/SConscript

@@ -0,0 +1,27 @@
+
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+src = Glob('src/*.c')
+
+startup_path_prefix = SDK_LIB
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s']
+
+path = [cwd]
+path = [cwd + '/inc']
+
+CPPDEFINES = ['USE_HT32F53252_SK, USE_HT32F53242_52, USE_MEM_HT32F53252']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/ht32/ht32f53252/board/inc/board.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-04-08     QT-one       first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "ht32.h"
+#include "ht32_msp.h"
+
+#ifdef BSP_USING_GPIO
+    #include "drv_gpio.h"
+#endif
+
+#ifdef BSP_USING_SPI
+    #include "drv_spi.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* whether use board external SRAM memory */
+#define HT32_EXT_SRAM 0
+#define HT32_EXT_SRAM_BEGIN 0x68000000
+#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024)
+
+/* internal sram memory size */
+#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE)
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+#define HEAP_END    HT32_SRAM_END
+
+void rt_hw_board_clock_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */

bsp/ht32/ht32f53252/board/inc/ht32_can_config.h

@@ -0,0 +1,111 @@
+/*********************************************************************************************************//**
+ * @file    CAN/Send_DATA/ht32_can_config.h
+ * @version $Rev:: 8164         $
+ * @date    $Date:: 2024-09-20 #$
+ * @brief   The header file of CAN baudrate configuration.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ *    code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ *    proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ *    other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ *    code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ *    other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ *    only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ *    the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ *    the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
+ ************************************************************************************************************/
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32_CAN_CONFIG_H
+#define __HT32_CAN_CONFIG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+//  <q0> Enable CAN Config Check
+//     <i> Display related setting by printf().
+#define HTCFG_CAN_CONF_CHECK_ENABLE               (0)
+
+//  <h> Core Clock Setting
+//  </h>
+//  <o0> -- Core Clock Calculation Setting
+//     <i> HTCFG_CAN_CORECLKSEL
+//     <i> Define the Core Clock by default maximum clock setting or manual input.
+//     <i> 0 = Default Maximum (LIBCFG_MAX_SPEED)
+//     <i> 1 = Manual Input (HTCFG_CAN_CORECLK_MANUAL)
+//       <0=> Default Maximum (LIBCFG_MAX_SPEED)
+//       <1=> Manual Input (HTCFG_CAN_CORECLK_MANUAL)
+//     <i> Note: CK_CAN = (Core Clock) / (CAN Peripheral Clock Prescaler)
+//  <o1> -- Core Clock Manual Input (Hz)
+//     <i> HTCFG_CAN_CORECLK_MANUAL
+//     <i> Only meaningful when HTCFG_CAN_CLKSEL = 1 (Manual Input)
+#define HTCFG_CAN_CORECLKSEL                      (0)         // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_CAN_CORECLK_MANUAL)
+#define HTCFG_CAN_CORECLK_MANUAL                  (8000000)  // Only meaningful when HTCFG_CAN_CORECLKSEL = 1 (Manual Input)
+
+//  <h> ------------------------------------------
+//  </h>
+
+//  <h> CAN Config 0 Setting
+//  </h>
+//  <o0> CAN Peripheral Clock Selection (CANnPCLK)
+//     <i> HTCFG_CAN_CLK_PRESCALER
+//       <0=> Div 1
+//       <1=> Div 2
+//       <2=> Div 4
+//       <3=> Div 8
+#define HTCFG_CAN_CF0_CLK_DIV                     (0)         // 0 = /1, 1 = /2, 2 = /4, 3 = /8
+
+/*
+//  <o> CAN Baudrate
+//    <i> HTCFG_CAN_BAUDRATE
+//      <1000000=> 1000 kbps
+//      <800000=>   800 kbps
+//      <500000=>   500 kbps
+//      <250000=>   250 kbps
+//      <125000=>   125 kbps
+//      <100000=>   100 kbps
+//      <50000=>     50 kbps
+//      <20000=>     20 kbps
+//      <10000=>     10 kbps
+//      <5000=>       5 kbps
+//    <i> The CAN baudrate specifies the frequency of transitions occurring per second.
+*/
+#define HTCFG_CAN_CF0_BAUDRATE                    (500000)
+
+/*
+//  <o> CAN Sample Point Target (%) <50-90:1>
+//    <i> HTCFG_CAN_SAMPLE_POINT
+//    <i> The Sample Point is the specific location within each bit period where the CAN_Core samples the CAN bus's state (dominant or recessive).
+//    <i> Notice: The real calculation result may small than the HTCFG_CAN_SAMPLE_POINT setting.
+*/
+#define HTCFG_CAN_CF0_SAMPLE_POINT                (70)
+
+//  <o> CAN SJW (Synchronisation Jump Width)
+//    <i> HTCFG_CAN_BIT_TIME_SJW
+//    <i> The (Re-)Synchronisation Jump Width.
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+#define HTCFG_CAN_CF0_BIT_TIME_SJW                (1)       // 1 ~ 4
+
+#include "ht32_can_config0_calc.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ht32/ht32f53252/board/inc/ht32_msp.h

@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-04-08     QT-one       first version
+ */
+
+#ifndef __HT32_MSP_H__
+#define __HT32_MSP_H__
+
+#include <rtthread.h>
+#include "ht32.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* UART gpio */
+#ifdef BSP_USING_UART
+#ifdef BSP_USING_USART0
+#define HTCFG_USART0_IPN                          USART0
+
+#define _HTCFG_USART0_TX_GPIOX                    A
+#define _HTCFG_USART0_TX_GPION                    2
+#define _HTCFG_USART0_RX_GPIOX                    A
+#define _HTCFG_USART0_RX_GPION                    3
+
+#define HTCFG_USART0_TX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_USART0_TX_GPIOX)
+#define HTCFG_USART0_TX_GPIO_CLK                  STRCAT2(P,              _HTCFG_USART0_TX_GPIOX)
+#define HTCFG_USART0_TX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_USART0_TX_GPIOX)
+#define HTCFG_USART0_TX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_USART0_TX_GPION)
+
+#define HTCFG_USART0_RX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_USART0_RX_GPIOX)
+#define HTCFG_USART0_RX_GPIO_CLK                  STRCAT2(P,              _HTCFG_USART0_RX_GPIOX)
+#define HTCFG_USART0_RX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_USART0_RX_GPIOX)
+#define HTCFG_USART0_RX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_USART0_RX_GPION)
+
+#endif
+#ifdef BSP_USING_USART1
+
+#define HTCFG_USART1_IPN                          USART1
+
+#define _HTCFG_USART1_TX_GPIOX                    A
+#define _HTCFG_USART1_TX_GPION                    4
+#define _HTCFG_USART1_RX_GPIOX                    A
+#define _HTCFG_USART1_RX_GPION                    5
+
+#define HTCFG_USART1_TX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_USART1_TX_GPIOX)
+#define HTCFG_USART1_TX_GPIO_CLK                  STRCAT2(P,              _HTCFG_USART1_TX_GPIOX)
+#define HTCFG_USART1_TX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_USART1_TX_GPIOX)
+#define HTCFG_USART1_TX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_USART1_TX_GPION)
+
+#define HTCFG_USART1_RX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_USART1_RX_GPIOX)
+#define HTCFG_USART1_RX_GPIO_CLK                  STRCAT2(P,              _HTCFG_USART1_RX_GPIOX)
+#define HTCFG_USART1_RX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_USART1_RX_GPIOX)
+#define HTCFG_USART1_RX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_USART1_RX_GPION)
+
+#endif
+#ifdef BSP_USING_UART0
+
+#define HTCFG_UART0_IPN                          UART0
+
+#define _HTCFG_UART0_TX_GPIOX                    B
+#define _HTCFG_UART0_TX_GPION                    2
+#define _HTCFG_UART0_RX_GPIOX                    B
+#define _HTCFG_UART0_RX_GPION                    3
+
+#define HTCFG_UART0_TX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_UART0_TX_GPIOX)
+#define HTCFG_UART0_TX_GPIO_CLK                  STRCAT2(P,              _HTCFG_UART0_TX_GPIOX)
+#define HTCFG_UART0_TX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_UART0_TX_GPIOX)
+#define HTCFG_UART0_TX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_UART0_TX_GPION)
+
+#define HTCFG_UART0_RX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_UART0_RX_GPIOX)
+#define HTCFG_UART0_RX_GPIO_CLK                  STRCAT2(P,              _HTCFG_UART0_RX_GPIOX)
+#define HTCFG_UART0_RX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_UART0_RX_GPIOX)
+#define HTCFG_UART0_RX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_UART0_RX_GPION)
+
+#endif
+#ifdef BSP_USING_UART1
+
+#define HTCFG_UART1_IPN                          UART1
+
+#define _HTCFG_UART1_TX_GPIOX                    B
+#define _HTCFG_UART1_TX_GPION                    4
+#define _HTCFG_UART1_RX_GPIOX                    B
+#define _HTCFG_UART1_RX_GPION                    5
+
+#define HTCFG_UART1_TX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_UART1_TX_GPIOX)
+#define HTCFG_UART1_TX_GPIO_CLK                  STRCAT2(P,              _HTCFG_UART1_TX_GPIOX)
+#define HTCFG_UART1_TX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_UART1_TX_GPIOX)
+#define HTCFG_UART1_TX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_UART1_TX_GPION)
+
+#define HTCFG_UART1_RX_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_UART1_RX_GPIOX)
+#define HTCFG_UART1_RX_GPIO_CLK                  STRCAT2(P,              _HTCFG_UART1_RX_GPIOX)
+#define HTCFG_UART1_RX_GPIO_PORT                 STRCAT2(HT_GPIO,        _HTCFG_UART1_RX_GPIOX)
+#define HTCFG_UART1_RX_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_UART1_RX_GPION)
+
+#endif
+#endif
+
+/* SPI gpio */
+#ifdef BSP_USING_SPI
+#ifdef BSP_USING_SPI0
+
+#define HTCFG_SPI0_IPN                           SPI0
+
+#define _HTCFG_SPI0_SCK_GPIOX                    C
+#define _HTCFG_SPI0_SCK_GPION                    0
+
+#define _HTCFG_SPI0_MISO_GPIOX                   A
+#define _HTCFG_SPI0_MISO_GPION                   11
+
+#define _HTCFG_SPI0_MOSI_GPIOX                   A
+#define _HTCFG_SPI0_MOSI_GPION                   9
+
+#define HTCFG_SPI0_SCK_GPIO_CLK                  STRCAT2(P,              _HTCFG_SPI0_SCK_GPIOX)
+#define HTCFG_SPI0_SCK_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_SPI0_SCK_GPIOX)
+#define HTCFG_SPI0_SCK_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_SPI0_SCK_GPION)
+
+#define HTCFG_SPI0_MISO_GPIO_CLK                 STRCAT2(P,              _HTCFG_SPI0_MISO_GPIOX)
+#define HTCFG_SPI0_MISO_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SPI0_MISO_GPIOX)
+#define HTCFG_SPI0_MISO_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SPI0_MISO_GPION)
+
+#define HTCFG_SPI0_MOSI_GPIO_CLK                 STRCAT2(P,              _HTCFG_SPI0_MOSI_GPIOX)
+#define HTCFG_SPI0_MOSI_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SPI0_MOSI_GPIOX)
+#define HTCFG_SPI0_MOSI_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SPI0_MOSI_GPION)
+
+#endif
+#ifdef BSP_USING_SPI1
+
+#define HTCFG_SPI1_IPN                           SPI1
+
+#define _HTCFG_SPI1_SCK_GPIOX                    C
+#define _HTCFG_SPI1_SCK_GPION                    5
+
+#define _HTCFG_SPI1_MISO_GPIOX                   C
+#define _HTCFG_SPI1_MISO_GPION                   9
+
+#define _HTCFG_SPI1_MOSI_GPIOX                   C
+#define _HTCFG_SPI1_MOSI_GPION                   8
+
+#define HTCFG_SPI1_SCK_GPIO_CLK                  STRCAT2(P,              _HTCFG_SPI1_SCK_GPIOX)
+#define HTCFG_SPI1_SCK_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_SPI1_SCK_GPIOX)
+#define HTCFG_SPI1_SCK_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_SPI1_SCK_GPION)
+
+#define HTCFG_SPI1_MISO_GPIO_CLK                 STRCAT2(P,              _HTCFG_SPI1_MISO_GPIOX)
+#define HTCFG_SPI1_MISO_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SPI1_MISO_GPIOX)
+#define HTCFG_SPI1_MISO_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SPI1_MISO_GPION)
+
+#define HTCFG_SPI1_MOSI_GPIO_CLK                 STRCAT2(P,              _HTCFG_SPI1_MOSI_GPIOX)
+#define HTCFG_SPI1_MOSI_GPIO_ID                  STRCAT2(GPIO_P,         _HTCFG_SPI1_MOSI_GPIOX)
+#define HTCFG_SPI1_MOSI_GPIO_PIN                 STRCAT2(GPIO_PIN_,      _HTCFG_SPI1_MOSI_GPION)
+
+#endif
+#endif
+
+/* I2C gpio */
+#ifdef BSP_USING_I2C_HW
+#ifdef BSP_USING_I2C0_HW
+
+#define HTCFG_I2C0_IPN                           I2C0
+
+#define _HTCFG_I2C0_SCL_GPIOX                    C
+#define _HTCFG_I2C0_SCL_GPION                    12
+
+#define _HTCFG_I2C0_SDA_GPIOX                    C
+#define _HTCFG_I2C0_SDA_GPION                    13
+
+#define HTCFG_I2C0_SCL_GPIO_CLK                  STRCAT2(P,              _HTCFG_I2C0_SCL_GPIOX)
+#define HTCFG_I2C0_SCL_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_I2C0_SCL_GPIOX)
+#define HTCFG_I2C0_SCL_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_I2C0_SCL_GPION)
+
+#define HTCFG_I2C0_SDA_GPIO_CLK                  STRCAT2(P,              _HTCFG_I2C0_SDA_GPIOX)
+#define HTCFG_I2C0_SDA_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_I2C0_SDA_GPIOX)
+#define HTCFG_I2C0_SDA_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_I2C0_SDA_GPION)
+
+#endif
+#ifdef BSP_USING_I2C1_HW
+
+#define HTCFG_I2C1_IPN                           I2C1
+
+#define _HTCFG_I2C1_SCL_GPIOX                    A
+#define _HTCFG_I2C1_SCL_GPION                    0
+
+#define _HTCFG_I2C1_SDA_GPIOX                    A
+#define _HTCFG_I2C1_SDA_GPION                    1
+
+#define HTCFG_I2C1_SCL_GPIO_CLK                  STRCAT2(P,              _HTCFG_I2C1_SCL_GPIOX)
+#define HTCFG_I2C1_SCL_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_I2C1_SCL_GPIOX)
+#define HTCFG_I2C1_SCL_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_I2C1_SCL_GPION)
+
+#define HTCFG_I2C1_SDA_GPIO_CLK                  STRCAT2(P,              _HTCFG_I2C1_SDA_GPIOX)
+#define HTCFG_I2C1_SDA_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_I2C1_SDA_GPIOX)
+#define HTCFG_I2C1_SDA_GPIO_PIN                  STRCAT2(GPIO_PIN_,      _HTCFG_I2C1_SDA_GPION)
+
+#endif
+#endif
+
+/* ADC gpio */
+#ifdef BSP_USING_ADC
+#ifdef BSP_USING_ADC0
+
+#define HTCFG_ADC0_IPN                           ADC0
+
+#define _HTCFG_ADC0CH0_GPIOX                     A
+#define _HTCFG_ADC0CH0_AFION                     0
+
+#define _HTCFG_ADC0CH1_GPIOX                     A
+#define _HTCFG_ADC0CH1_AFION                     1
+
+#define _HTCFG_ADC0CH2_GPIOX                     A
+#define _HTCFG_ADC0CH2_AFION                     2
+
+#define _HTCFG_ADC0CH3_GPIOX                     A
+#define _HTCFG_ADC0CH3_AFION                     3
+
+#define _HTCFG_ADC0CH4_GPIOX                     A
+#define _HTCFG_ADC0CH4_AFION                     4
+
+#define _HTCFG_ADC0CH5_GPIOX                     A
+#define _HTCFG_ADC0CH5_AFION                     5
+
+#define _HTCFG_ADC0CH6_GPIOX                     A
+#define _HTCFG_ADC0CH6_AFION                     6
+
+#define _HTCFG_ADC0CH7_GPIOX                     A
+#define _HTCFG_ADC0CH7_AFION                     7
+
+#define _HTCFG_ADC0CH8_GPIOX                     C
+#define _HTCFG_ADC0CH8_AFION                     4
+
+#define _HTCFG_ADC0CH9_GPIOX                     C
+#define _HTCFG_ADC0CH9_AFION                     5
+
+#define _HTCFG_ADC0CH10_GPIOX                    C
+#define _HTCFG_ADC0CH10_AFION                    8
+
+#define _HTCFG_ADC0CH11_GPIOX                    C
+#define _HTCFG_ADC0CH11_AFION                    9
+
+#define _HTCFG_ADC0CH12_GPIOX                    C
+#define _HTCFG_ADC0CH12_AFION                    1
+
+#define _HTCFG_ADC0CH13_GPIOX                    C
+#define _HTCFG_ADC0CH13_AFION                    1
+
+#define _HTCFG_ADC0CH14_GPIOX                    C
+#define _HTCFG_ADC0CH14_AFION                    1
+
+#define _HTCFG_ADC0CH15_GPIOX                    C
+#define _HTCFG_ADC0CH15_AFION                    1
+
+#define HTCFG_ADC0CH0_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH0_GPIOX)
+#define HTCFG_ADC0CH1_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH1_GPIOX)
+#define HTCFG_ADC0CH2_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH2_GPIOX)
+#define HTCFG_ADC0CH3_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH3_GPIOX)
+#define HTCFG_ADC0CH4_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH4_GPIOX)
+#define HTCFG_ADC0CH5_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH5_GPIOX)
+#define HTCFG_ADC0CH6_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH6_GPIOX)
+#define HTCFG_ADC0CH7_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH7_GPIOX)
+#define HTCFG_ADC0CH8_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH8_GPIOX)
+#define HTCFG_ADC0CH9_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC0CH9_GPIOX)
+#define HTCFG_ADC0CH10_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_ADC0CH10_GPIOX)
+#define HTCFG_ADC0CH11_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_ADC0CH11_GPIOX)
+#define HTCFG_ADC0CH12_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_ADC0CH12_GPIOX)
+#define HTCFG_ADC0CH13_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_ADC0CH13_GPIOX)
+#define HTCFG_ADC0CH14_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_ADC0CH14_GPIOX)
+#define HTCFG_ADC0CH15_GPIO_ID                   STRCAT2(GPIO_P,         _HTCFG_ADC0CH15_GPIOX)
+
+#define HTCFG_ADC0CH0_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH0_AFION)
+#define HTCFG_ADC0CH1_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH1_AFION)
+#define HTCFG_ADC0CH2_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH2_AFION)
+#define HTCFG_ADC0CH3_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH3_AFION)
+#define HTCFG_ADC0CH4_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH4_AFION)
+#define HTCFG_ADC0CH5_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH5_AFION)
+#define HTCFG_ADC0CH6_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH6_AFION)
+#define HTCFG_ADC0CH7_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH7_AFION)
+#define HTCFG_ADC0CH8_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH8_AFION)
+#define HTCFG_ADC0CH9_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH9_AFION)
+#define HTCFG_ADC0CH10_AFIO_PIN                  STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH10_AFION)
+#define HTCFG_ADC0CH11_AFIO_PIN                  STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH11_AFION)
+#define HTCFG_ADC0CH12_AFIO_PIN                  STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH12_AFION)
+#define HTCFG_ADC0CH13_AFIO_PIN                  STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH13_AFION)
+#define HTCFG_ADC0CH14_AFIO_PIN                  STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH14_AFION)
+#define HTCFG_ADC0CH15_AFIO_PIN                  STRCAT2(AFIO_PIN_,      _HTCFG_ADC0CH15_AFION)
+
+#endif
+#ifdef BSP_USING_ADC1
+
+#define HTCFG_ADC1_IPN                           ADC1
+
+#define _HTCFG_ADC1CH0_GPIOX                     B
+#define _HTCFG_ADC1CH0_AFION                     8
+
+#define _HTCFG_ADC1CH1_GPIOX                     A
+#define _HTCFG_ADC1CH1_AFION                     0
+
+#define _HTCFG_ADC1CH2_GPIOX                     A
+#define _HTCFG_ADC1CH2_AFION                     1
+
+#define _HTCFG_ADC1CH3_GPIOX                     A
+#define _HTCFG_ADC1CH3_AFION                     2
+
+#define _HTCFG_ADC1CH4_GPIOX                     A
+#define _HTCFG_ADC1CH4_AFION                     3
+
+#define _HTCFG_ADC1CH5_GPIOX                     A
+#define _HTCFG_ADC1CH5_AFION                     4
+
+#define _HTCFG_ADC1CH6_GPIOX                     A
+#define _HTCFG_ADC1CH6_AFION                     5
+
+#define _HTCFG_ADC1CH7_GPIOX                     A
+#define _HTCFG_ADC1CH7_AFION                     6
+
+#define HTCFG_ADC1CH0_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH0_GPIOX)
+#define HTCFG_ADC1CH1_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH1_GPIOX)
+#define HTCFG_ADC1CH2_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH2_GPIOX)
+#define HTCFG_ADC1CH3_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH3_GPIOX)
+#define HTCFG_ADC1CH4_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH4_GPIOX)
+#define HTCFG_ADC1CH5_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH5_GPIOX)
+#define HTCFG_ADC1CH6_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH6_GPIOX)
+#define HTCFG_ADC1CH7_GPIO_ID                    STRCAT2(GPIO_P,         _HTCFG_ADC1CH7_GPIOX)
+
+#define HTCFG_ADC1CH0_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH0_AFION)
+#define HTCFG_ADC1CH1_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH1_AFION)
+#define HTCFG_ADC1CH2_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH2_AFION)
+#define HTCFG_ADC1CH3_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH3_AFION)
+#define HTCFG_ADC1CH4_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH4_AFION)
+#define HTCFG_ADC1CH5_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH5_AFION)
+#define HTCFG_ADC1CH6_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH6_AFION)
+#define HTCFG_ADC1CH7_AFIO_PIN                   STRCAT2(AFIO_PIN_,      _HTCFG_ADC1CH7_AFION)
+
+#endif
+#endif
+/* CAN gpio */
+#ifdef BSP_USING_CAN
+#define HTCFG_CAN_IPN                            CAN0
+
+#define _HTCFG_CAN_TX_GPIOX                      C
+#define _HTCFG_CAN_TX_GPION                      6
+
+#define _HTCFG_CAN_RX_GPIOX                      C
+#define _HTCFG_CAN_RX_GPION                      7
+
+#define HTCFG_CAN_TX_GPIO_CLK                    STRCAT2(P,              _HTCFG_CAN_TX_GPIOX)
+#define HTCFG_CAN_TX_GPIO_ID                     STRCAT2(GPIO_P,         _HTCFG_CAN_TX_GPIOX)
+#define HTCFG_CAN_TX_GPIO_PIN                    STRCAT2(GPIO_PIN_,      _HTCFG_CAN_TX_GPION)
+
+#define HTCFG_CAN_RX_GPIO_CLK                    STRCAT2(P,              _HTCFG_CAN_RX_GPIOX)
+#define HTCFG_CAN_RX_GPIO_ID                     STRCAT2(GPIO_P,         _HTCFG_CAN_RX_GPIOX)
+#define HTCFG_CAN_RX_GPIO_PIN                    STRCAT2(GPIO_PIN_,      _HTCFG_CAN_RX_GPION)
+#endif
+
+void ht32_usart_gpio_init(void *instance);
+void ht32_spi_gpio_init(void *instance);
+void ht32_hardware_i2c_gpio_init(void *instance);
+void ht32_adc_gpio_init(void *instance,int8_t channel);
+void ht32_can_gpio_init(void *instance);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HT32_MSP_H__ */

bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_01_usbdconf.h

@@ -0,0 +1,453 @@
+/*********************************************************************************************************//**
+ * @file    IP/Example/ht32f5xxxx_01_usbdconf.h
+ * @version $Rev:: 2390         $
+ * @date    $Date:: 2017-12-21 #$
+ * @brief   The configuration file of USB Device Driver.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ *    code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ *    proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ *    other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ *    code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ *    other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ *    only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ *    the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ *    the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
+ ************************************************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32F5XXXX_01_USBDCONF_H
+#define __HT32F5XXXX_01_USBDCONF_H
+
+// <e0> Enter Low Power mode when Suspended
+#define USBDCORE_ENABLE_LOW_POWER   (0)
+// </e>
+
+#if (USBDCORE_ENABLE_LOW_POWER == 1)
+  #define USBDCore_LowPower()      PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
+#else
+  #define USBDCore_LowPower(...)
+#endif
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* USB Interrupt Enable                                                                                     */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <h> USB Interrupt Setting (UIER)
+//    <o0.0> USB Global Interrupt Enable (UGIE) (Default)
+//    <o0.1> Start Of Frame Interrupt Enable (SOFIE)
+//    <o0.2> USB Reset Interrupt Enable (URSTIE) (Default)
+//    <o0.3> Resume Interrupt Enable (RSMIE) (Default)
+//    <o0.4> Suspend Interrupt Enable (SUSPIE) (Default)
+//    <o0.5> Expected Start of Frame Interrupt Enable (ESOFE)
+//    <o0.8> Control Endpoint Interrupt Enable (EP0IE) (Default)
+//    <o0.9> Endpoint1 Interrupt Enable (EP1IE)
+//    <o0.10> Endpoint2 Interrupt Enable (EP2IE)
+//    <o0.11> Endpoint3 Interrupt Enable (EP3IE)
+//    <o0.12> Endpoint4 Interrupt Enable (EP4IE)
+//    <o0.13> Endpoint5 Interrupt Enable (EP5IE)
+//    <o0.14> Endpoint6 Interrupt Enable (EP6IE)
+//    <o0.15> Endpoint7 Interrupt Enable (EP7IE)
+#define _UIER               (0xFF1D)
+//  </h>
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint0 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <h> Control Endpoint0 Configuration
+//    <o0> Endpoint Buffer Length (EPLEN)
+//      <8=> 8 bytes
+//      <16=> 16 bytes
+//      <32=> 32 bytes
+//      <64=> 64 bytes
+                            /* Maximum: 64 Bytes                                                            */
+#define _EP0LEN             (64)
+
+
+//    <h> Control Endpoint0 Interrupt Enable Settings (EP0IER)
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+//      <o0.8> SETUP Token Packet Received Interrupt Enable (STRXIE)
+//      <o0.9> SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
+//      <o0.10> SETUP Data Error Interrupt Enable (SDERIE)
+//      <o0.11> Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
+#define _EP0_IER            (0x212)
+//    </h>
+//  </h>
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint1 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint1 Configuration
+#define _EP1_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP1_CFG_EPADR      (1)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP1_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP1_TYPR           (2)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP1_CFG_EPDIR      (1)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+                            /* Maximum: 64 Bytes                                                            */
+#define _EP1LEN_TMP         (64)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP1_IER            (0x12)
+// </h>
+// </e>
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint2 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint2 Configuration
+#define _EP2_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP2_CFG_EPADR      (2)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP2_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP2_TYPR           (2)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP2_CFG_EPDIR      (0)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+                            /* Maximum: 64 Bytes                                                            */
+#define _EP2LEN_TMP         (64)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP2_IER            (0x012)
+// </h>
+// </e>
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint3 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint3 Configuration
+#define _EP3_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP3_CFG_EPADR      (3)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP3_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP3_TYPR           (3)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP3_CFG_EPDIR      (1)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+                            /* Maximum: 64 Bytes                                                            */
+#define _EP3LEN_TMP         (64)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP3_IER            (0x12)
+// </h>
+// </e>
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint4 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint4 Configuration
+#define _EP4_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP4_CFG_EPADR      (4)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP4_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <1=> Isochronous
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP4_TYPR           (3)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP4_CFG_EPDIR      (0)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+                            /* Maximum: 1000 Bytes                                                          */
+#define _EP4LEN_TMP         (64)
+
+//    <o0> Single/Double Buffer Selection (SDBS)
+//      <0=> Single Buffer
+//      <1=> Double Buffer
+#define _EP4_CFG_SDBS       (0)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP4_IER            (0x12)
+// </h>
+// </e>
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint5 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint5 Configuration
+#define _EP5_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP5_CFG_EPADR      (5)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP5_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <1=> Isochronous
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP5_TYPR           (1)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP5_CFG_EPDIR      (1)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+                            /* Maximum: 1000 Bytes                                                          */
+#define _EP5LEN_TMP         (64)
+
+
+//    <o0> Single/Double Buffer Selection (SDBS)
+//      <0=> Single Buffer
+//      <1=> Double Buffer
+#define _EP5_CFG_SDBS       (0)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP5_IER            (0x12)
+// </h>
+// </e>
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint6 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint6 Configuration
+#define _EP6_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP6_CFG_EPADR      (6)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP6_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <1=> Isochronous
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP6_TYPR           (1)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP6_CFG_EPDIR      (0)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+                            /* Maximum: 1000 Bytes                                                          */
+#define _EP6LEN_TMP         (64)
+
+//    <o0> Single/Double Buffer Selection (SDBS)
+//      <0=> Single Buffer
+//      <1=> Double Buffer
+#define _EP6_CFG_SDBS       (0)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP6_IER            (0x12)
+// </h>
+// </e>
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint7 Configuration Setting                                                                          */
+/*----------------------------------------------------------------------------------------------------------*/
+//  <e0> Endpoint7 Configuration
+#define _EP7_ENABLE         (1)
+
+//    <o0> Endpoint Address (EPADR)
+//      <1=> 1
+//      <2=> 2
+//      <3=> 3
+//      <4=> 4
+//      <5=> 5
+//      <6=> 6
+//      <7=> 7
+#define _EP7_CFG_EPADR      (7)
+
+//    <o0.0> Endpoint Enable (EPEN)
+#define _EP7_CFG_EPEN_TMP   (1)
+
+//    <o0> Endpoint Transfer Type
+//      <1=> Isochronous
+//      <2=> Bulk
+//      <3=> Interrupt
+#define _EP7_TYPR           (3)
+
+//    <o0> Endpoint Direction (EPDIR)
+//      <1=> IN
+//      <0=> OUT
+#define _EP7_CFG_EPDIR      (1)
+
+//    <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+                            /* Maximum: 1000 Bytes                                                          */
+#define _EP7LEN_TMP         (64)
+
+//    <o0> Single/Double Buffer Selection (SDBS)
+//      <0=> Single Buffer
+//      <1=> Double Buffer
+#define _EP7_CFG_SDBS       (0)
+
+//    <h> Endpoint Interrupt Enable Settings (EPIER)
+//      <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+//      <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
+//      <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
+//      <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+//      <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
+//      <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+//      <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
+//      <o0.6> STALL Transmitted Interrupt Enable (STLIE)
+//      <o0.7> USB Error Interrupt Enable (UERIE)
+#define _EP7_IER            (0x12)
+// </h>
+// </e>
+
+#endif

bsp/ht32/ht32f53252/board/linker_scripts/link.icf

@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

bsp/ht32/ht32f53252/board/linker_scripts/link.lds

@@ -0,0 +1,156 @@
+/*
+ * linker script for AT32 with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  96k /* 96K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4); 
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+        
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/ht32/ht32f53252/board/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x0001FE00  {    ; load region size_region
+  ER_IROM1 0x00000000 0x0001FE00  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/ht32/ht32f53252/board/src/board.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-04-08     QT-one       first version
+ */
+
+#include "board.h"
+
+/* This feature will initialize the HT32 chip clock */
+void rt_hw_board_clock_init(void)
+{
+
+}

bsp/ht32/ht32f53252/board/src/ht32_msp.c

@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-04-08     QT-one       first version
+ */
+
+#include "ht32_msp.h"
+
+/* GPIO configuration for UART */
+#ifdef BSP_USING_UART
+void ht32_usart_gpio_init(void *instance)
+{
+    CKCU_PeripClockConfig_TypeDef   CKCUClock = {{0}};
+    HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance;
+#ifdef BSP_USING_USART0
+    if (HT_USART0 == usart_x)
+    {
+        CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+        GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT, HTCFG_USART0_RX_GPIO_PIN, GPIO_PR_UP);
+        /* Config AFIO mode as UxART function */
+        AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID, HTCFG_USART0_TX_GPIO_PIN, AFIO_FUN_USART_UART);
+        AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID, HTCFG_USART0_RX_GPIO_PIN, AFIO_FUN_USART_UART);
+    }
+#endif
+#ifdef BSP_USING_USART1
+    if (HT_USART1 == usart_x)
+    {
+        CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+        GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT, HTCFG_USART1_RX_GPIO_PIN, GPIO_PR_UP);
+        /* Config AFIO mode as UxART function */
+        AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID, HTCFG_USART1_TX_GPIO_PIN, AFIO_FUN_USART_UART);
+        AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID, HTCFG_USART1_RX_GPIO_PIN, AFIO_FUN_USART_UART);
+    }
+#endif
+#ifdef BSP_USING_UART0
+    if (HT_UART0 == usart_x)
+    {
+        CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+        GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT, HTCFG_UART0_RX_GPIO_PIN, GPIO_PR_UP);
+        /* Config AFIO mode as UxART function */
+        AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID, HTCFG_UART0_TX_GPIO_PIN, AFIO_FUN_USART_UART);
+        AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID, HTCFG_UART0_RX_GPIO_PIN, AFIO_FUN_USART_UART);
+    }
+#endif
+#ifdef BSP_USING_UART1
+    if (HT_UART1 == usart_x)
+    {
+        CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+        GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT, HTCFG_UART1_RX_GPIO_PIN, GPIO_PR_UP);
+        /* Config AFIO mode as UxART function */
+        AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID, HTCFG_UART1_TX_GPIO_PIN, AFIO_FUN_USART_UART);
+        AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID, HTCFG_UART1_RX_GPIO_PIN, AFIO_FUN_USART_UART);
+    }
+#endif
+}
+#endif
+
+/* GPIO configuration for SPI */
+#ifdef BSP_USING_SPI
+void ht32_spi_gpio_init(void *instance)
+{
+    CKCU_PeripClockConfig_TypeDef   CKCUClock = {{0}};
+    HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance;
+#ifdef BSP_USING_SPI0
+    if (HT_SPI0 == spi_x)
+    {
+        CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+
+        AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI);
+        AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI);
+        AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI);
+    }
+#endif
+#ifdef BSP_USING_SPI1
+    if (HT_SPI1 == spi_x)
+    {
+        CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+
+        AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI);
+        AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI);
+        AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI);
+    }
+#endif
+}
+#endif
+
+/* GPIO configuration for I2C */
+#ifdef BSP_USING_I2C_HW
+void ht32_hardware_i2c_gpio_init(void *instance)
+{
+    CKCU_PeripClockConfig_TypeDef   CKCUClock = {{0}};
+    HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance;
+#ifdef BSP_USING_I2C0_HW
+    if (HT_I2C0 == i2c_x)
+    {
+        CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Configure GPIO to I2C mode */
+        AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID, HTCFG_I2C0_SCL_GPIO_PIN, AFIO_FUN_I2C);
+        AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID, HTCFG_I2C0_SDA_GPIO_PIN, AFIO_FUN_I2C);
+    }
+#endif
+#ifdef BSP_USING_I2C1_HW
+    if (HT_I2C1 == i2c_x)
+    {
+        CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Configure GPIO to I2C mode */
+        AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID, HTCFG_I2C1_SCL_GPIO_PIN, AFIO_FUN_I2C);
+        AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID, HTCFG_I2C1_SDA_GPIO_PIN, AFIO_FUN_I2C);
+    }
+#endif
+}
+#endif
+
+/* GPIO configuration for ADC */
+#ifdef BSP_USING_ADC
+void ht32_adc_gpio_init(void *instance,int8_t channel)
+{
+    CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }};
+    HT_ADC_TypeDef *adc_x = (HT_ADC_TypeDef *)instance;
+#ifdef BSP_USING_ADC0
+    if (HT_ADC0 == adc_x)
+    {
+        /* Enable peripheral clock */
+        CKCUClock.Bit.AFIO = 1;
+        CKCUClock.Bit.ADC0 = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+
+        /* Configure AFIO mode as ADC function */
+        switch(channel)
+        {
+            case 0:
+                AFIO_GPxConfig(HTCFG_ADC0CH0_GPIO_ID, HTCFG_ADC0CH0_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 1:
+                AFIO_GPxConfig(HTCFG_ADC0CH1_GPIO_ID, HTCFG_ADC0CH1_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 2:
+                AFIO_GPxConfig(HTCFG_ADC0CH2_GPIO_ID, HTCFG_ADC0CH2_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 3:
+                AFIO_GPxConfig(HTCFG_ADC0CH3_GPIO_ID, HTCFG_ADC0CH3_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 4:
+                AFIO_GPxConfig(HTCFG_ADC0CH4_GPIO_ID, HTCFG_ADC0CH4_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 5:
+                AFIO_GPxConfig(HTCFG_ADC0CH5_GPIO_ID, HTCFG_ADC0CH5_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 6:
+                AFIO_GPxConfig(HTCFG_ADC0CH6_GPIO_ID, HTCFG_ADC0CH6_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 7:
+                AFIO_GPxConfig(HTCFG_ADC0CH7_GPIO_ID, HTCFG_ADC0CH7_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 8:
+                AFIO_GPxConfig(HTCFG_ADC0CH8_GPIO_ID, HTCFG_ADC0CH8_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 9:
+                AFIO_GPxConfig(HTCFG_ADC0CH9_GPIO_ID, HTCFG_ADC0CH9_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 10:
+                AFIO_GPxConfig(HTCFG_ADC0CH10_GPIO_ID, HTCFG_ADC0CH10_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 11:
+                AFIO_GPxConfig(HTCFG_ADC0CH11_GPIO_ID, HTCFG_ADC0CH11_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 12:
+                AFIO_GPxConfig(HTCFG_ADC0CH12_GPIO_ID, HTCFG_ADC0CH12_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 13:
+                AFIO_GPxConfig(HTCFG_ADC0CH13_GPIO_ID, HTCFG_ADC0CH13_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 14:
+                AFIO_GPxConfig(HTCFG_ADC0CH14_GPIO_ID, HTCFG_ADC0CH14_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 15:
+                AFIO_GPxConfig(HTCFG_ADC0CH15_GPIO_ID, HTCFG_ADC0CH15_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            default:
+                break;
+        }
+    }
+#endif
+#ifdef BSP_USING_ADC1
+    if (HT_ADC1 == adc_x)
+    {
+        /* Enable peripheral clock */
+        CKCUClock.Bit.AFIO = 1;
+        CKCUClock.Bit.ADC1 = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+
+        /* Configure AFIO mode as ADC function */
+        switch(channel)
+        {
+            case 0:
+                AFIO_GPxConfig(HTCFG_ADC1CH0_GPIO_ID, HTCFG_ADC1CH0_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 1:
+                AFIO_GPxConfig(HTCFG_ADC1CH1_GPIO_ID, HTCFG_ADC1CH1_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 2:
+                AFIO_GPxConfig(HTCFG_ADC1CH2_GPIO_ID, HTCFG_ADC1CH2_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 3:
+                AFIO_GPxConfig(HTCFG_ADC1CH3_GPIO_ID, HTCFG_ADC1CH3_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 4:
+                AFIO_GPxConfig(HTCFG_ADC1CH4_GPIO_ID, HTCFG_ADC1CH4_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 5:
+                AFIO_GPxConfig(HTCFG_ADC1CH5_GPIO_ID, HTCFG_ADC1CH5_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 6:
+                AFIO_GPxConfig(HTCFG_ADC1CH6_GPIO_ID, HTCFG_ADC1CH6_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            case 7:
+                AFIO_GPxConfig(HTCFG_ADC1CH7_GPIO_ID, HTCFG_ADC1CH7_AFIO_PIN, AFIO_FUN_ADC0);
+                break;
+            default:
+                break;
+        }
+    }
+#endif
+}
+#endif
+/* GPIO configuration for ADC */
+#ifdef BSP_USING_CAN
+void ht32_can_gpio_init(void *instance)
+{
+    CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }};
+    HT_CAN_TypeDef *can_x = (HT_CAN_TypeDef *)instance;
+
+    if (HT_CAN0 == can_x)
+    {
+        CKCUClock.Bit.HTCFG_CAN_TX_GPIO_CLK = 1;
+        CKCUClock.Bit.HTCFG_CAN_RX_GPIO_CLK = 1;
+        CKCU_PeripClockConfig(CKCUClock, ENABLE);
+        /* Configure GPIO to CAN mode */
+        AFIO_GPxConfig(HTCFG_CAN_TX_GPIO_ID, HTCFG_CAN_TX_GPIO_PIN, AFIO_FUN_CAN);
+        AFIO_GPxConfig(HTCFG_CAN_RX_GPIO_ID, HTCFG_CAN_RX_GPIO_PIN, AFIO_FUN_CAN);
+    }
+
+}
+#endif
+
+