From 3436aa64cbf02ab77268c8343a07e0de89e9bf47 Mon Sep 17 00:00:00 2001 From: QTbin <52951453+QT-one@users.noreply.github.com> Date: Mon, 13 Jan 2025 10:32:15 +0800 Subject: [PATCH] =?UTF-8?q?[ht32][drv]=E6=96=B0=E5=A2=9E=E4=BA=86CAN?= =?UTF-8?q?=E3=80=81USB=E5=92=8CSDIO=E7=9A=84=E9=A9=B1=E5=8A=A8=E6=96=87?= =?UTF-8?q?=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/bsp_buildings.yml | 1 + bsp/ht32/ht32f12366/.config | 262 +- bsp/ht32/ht32f12366/README.md | 4 +- bsp/ht32/ht32f12366/SConstruct | 3 + bsp/ht32/ht32f12366/applications/test.c | 123 +- bsp/ht32/ht32f12366/board/Kconfig | 137 +- bsp/ht32/ht32f12366/board/inc/board.h | 4 + bsp/ht32/ht32f12366/board/inc/ht32_msp.h | 65 +- .../board/inc/ht32f1xxxx_01_usbdconf.h | 52 +- bsp/ht32/ht32f12366/board/src/ht32_msp.c | 48 +- bsp/ht32/ht32f12366/project.uvoptx | 876 ++++--- bsp/ht32/ht32f12366/project.uvprojx | 843 ++----- bsp/ht32/ht32f12366/rtconfig.h | 147 +- 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bsp/ht32/ht32f53252/rtconfig.py create mode 100644 bsp/ht32/ht32f53252/template.uvoptx create mode 100644 bsp/ht32/ht32f53252/template.uvprojx create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57541.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57552.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59045.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61052.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61730.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61741.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62140.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200u.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52231.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52352.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_nw32f61242.s create mode 100644 bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_can_config0_calc.h create mode 100644 bsp/ht32/libraries/ht32_drivers/cpuport.h create mode 100644 bsp/ht32/libraries/ht32_drivers/drv_can.c create mode 100644 bsp/ht32/libraries/ht32_drivers/drv_can.h create mode 100644 bsp/ht32/libraries/ht32_drivers/drv_sdio.c create mode 100644 bsp/ht32/libraries/ht32_drivers/drv_sdio.h create mode 100644 bsp/ht32/libraries/ht32_drivers/drv_usbd.c create mode 100644 bsp/ht32/libraries/ht32_drivers/drv_usbd.h create mode 100644 bsp/ht32/libraries/usbd_library/SConscript create mode 100644 bsp/ht32/libraries/usbd_library/checkout.py create mode 100644 bsp/ht32/libraries/usbd_library/inc/ht32_usbd_core.h create mode 100644 bsp/ht32/libraries/usbd_library/inc/ht32_usbd_int.h create mode 100644 bsp/ht32/libraries/usbd_library/inc/usb_port.h create mode 100644 bsp/ht32/libraries/usbd_library/inc/usbd_code.h create mode 100644 bsp/ht32/libraries/usbd_library/src/ht32_usbd_core.c create mode 100644 bsp/ht32/libraries/usbd_library/src/ht32_usbd_int.c create mode 100644 bsp/ht32/libraries/usbd_library/src/usb_port.c create mode 100644 bsp/ht32/libraries/usbd_library/src/usbd_code.c diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index fcd219d33b..488583e39b 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -101,6 +101,7 @@ jobs: - "rm48x50" - "ht32/ht32f52352" - "ht32/ht32f12366" + - "ht32/ht32f53252" - "w60x" - "essemi/es32f0654" - "essemi/es32f365x" diff --git a/bsp/ht32/ht32f12366/.config b/bsp/ht32/ht32f12366/.config index 80ce545f3d..f0a158b051 100644 --- a/bsp/ht32/ht32f12366/.config +++ b/bsp/ht32/ht32f12366/.config @@ -1,15 +1,117 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# # # RT-Thread Kernel # + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_CPUS_NR=1 @@ -19,26 +121,24 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y +# CONFIG_RT_USING_OVERFLOW_CHECK is not set CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # -# kservice optimization +# kservice options # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# end of kservice options + +# CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set # # Inter-Thread communication @@ -50,6 +150,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -68,21 +169,21 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_THREADSAFE_PRINTF is not set -# CONFIG_RT_USING_SCHED_THREAD_CTX is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart0" CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -# CONFIG_RT_USING_CACHE is not set +# end of RT-Thread Kernel + CONFIG_RT_USING_HW_ATOMIC=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -117,12 +218,15 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # DFS: device virtual file system # # CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set @@ -131,53 +235,40 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers # # C/C++ and POSIX layer @@ -195,6 +286,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer @@ -216,7 +309,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network @@ -225,12 +322,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -242,12 +341,25 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -256,7 +368,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -279,27 +390,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -322,6 +441,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -365,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set # CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -375,6 +497,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -390,18 +513,22 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -413,12 +540,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -438,6 +568,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -487,6 +618,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_RT_TRACE is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -498,6 +630,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + # CONFIG_PKG_USING_AUNITY is not set # @@ -506,6 +640,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -516,6 +651,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -526,6 +662,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -573,6 +711,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers @@ -589,6 +728,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers # # Infineon HAL Packages @@ -603,6 +743,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_INFINEON_CSDIDAC is not set # CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set # CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -612,9 +754,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers # # sensors drivers @@ -684,6 +829,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -698,6 +844,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -771,6 +919,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -785,6 +934,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages @@ -795,6 +945,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -803,6 +954,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -811,6 +963,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -827,6 +980,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set # CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -860,6 +1015,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages # # Arduino libraries @@ -875,6 +1031,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -1015,6 +1172,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set # CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -1026,6 +1184,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -1034,6 +1193,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1042,6 +1202,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set # CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1052,6 +1213,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1063,12 +1225,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1081,10 +1245,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages + CONFIG_SOC_FAMILY_HT32=y CONFIG_SOC_SERIES_HT32F1=y @@ -1103,11 +1271,13 @@ CONFIG_CORTEX_M3=y # CONFIG_SOC_HT32F12345 is not set # CONFIG_SOC_HT32F12364 is not set CONFIG_SOC_HT32F12366=y +# end of Chip Configuration # # Onboard Peripheral Drivers # # CONFIG_BSP_USING_TEST is not set +# end of Onboard Peripheral Drivers # # On-chip Peripheral Drivers @@ -1123,7 +1293,11 @@ CONFIG_BSP_USING_USART0_NAME="usart0" # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_USBD is not set +# end of On-chip Peripheral Drivers # # Board extended module Drivers # +# end of Hardware Drivers Config diff --git a/bsp/ht32/ht32f12366/README.md b/bsp/ht32/ht32f12366/README.md index 04de7527d7..4f07d115d2 100644 --- a/bsp/ht32/ht32f12366/README.md +++ b/bsp/ht32/ht32f12366/README.md @@ -41,8 +41,8 @@ ESK32-30105使用32位ARM® Cortex®-M3高性能、低功耗单片机HT32F12366 | UART | 支持 | UART0/1 | | SPI | 支持 | SPI0/1 | | I2C | 支持 | 硬件 I2C0/1 | -| ADC | 暂不支持 | | -| WDT | 暂不支持 | | +| ADC | 支持 | | +| WDT | 支持 | | ## 使用说明 diff --git a/bsp/ht32/ht32f12366/SConstruct b/bsp/ht32/ht32f12366/SConstruct index 5fcd0e3860..218a226a5f 100644 --- a/bsp/ht32/ht32f12366/SConstruct +++ b/bsp/ht32/ht32f12366/SConstruct @@ -53,6 +53,9 @@ rtconfig.BSP_LIBRARY_TYPE = ht32_library # include libraries objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) +# include usb libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbd_library', 'SConscript'))) + # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) diff --git a/bsp/ht32/ht32f12366/applications/test.c b/bsp/ht32/ht32f12366/applications/test.c index 1146f0aec6..50ab776ca1 100644 --- a/bsp/ht32/ht32f12366/applications/test.c +++ b/bsp/ht32/ht32f12366/applications/test.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -58,10 +58,18 @@ static struct rt_semaphore rx_sem; static rt_mutex_t task_mutex = RT_NULL; /* task mutex */ /* device handle */ +#ifdef BSP_USING_UART static rt_device_t serial; +#endif +#ifdef BSP_USING_WDT static rt_device_t wdt_dev; +#endif +#ifdef BSP_USING_I2C struct rt_i2c_bus_device *i2c_dev; +#endif +#ifdef BSP_USING_SPI static struct rt_spi_device *spi_dev; +#endif /* In-file function declarations */ static void sys_run_dir(void *parameter); @@ -90,6 +98,7 @@ int task_registration(void) INIT_BOARD_EXPORT(task_registration); /* System operation indicator */ +#ifdef BSP_USING_GPIO static void sys_run_dir(void *parameter) { rt_uint32_t e; @@ -301,7 +310,9 @@ static int gpio_input_task(int argc, char *argv[]) return -1; } MSH_CMD_EXPORT(gpio_input_task, gpio input task operation); +#endif /* uart test */ +#ifdef BSP_USING_UART static rt_err_t uart_iqr_handle(rt_device_t dev, rt_size_t size) { /* Serial port callback function */ @@ -396,7 +407,9 @@ static int uart_task(int argc, char *argv[]) return ret; } MSH_CMD_EXPORT(uart_task, uart device sample); +#endif /* hw/sw iic test */ +#ifdef BSP_USING_I2C static void i2c_thread(void *parameter) { uint8_t write_addr = 0x00; @@ -497,7 +510,9 @@ static int i2c_task(int argc, char *argv[]) return ret; } MSH_CMD_EXPORT(i2c_task, i2c device sample); +#endif /* spi test */ +#ifdef BSP_USING_SPI static void spi_thread(void *parameter) { rt_uint8_t w25x_read_id = 0x9F; @@ -584,7 +599,9 @@ static int spi_task(int argc, char *argv[]) return ret; } MSH_CMD_EXPORT(spi_task, spi device sample); +#endif /* adc test */ +#ifdef BSP_USING_ADC static void adc_test(void *parameter) { rt_uint32_t adc0_ch11_val,adc0_ch12_val; @@ -640,8 +657,9 @@ static int adc_task(int argc, char *argv[]) return -1; } MSH_CMD_EXPORT(adc_task, adc task operation); - +#endif /* wdt test */ +#ifdef BSP_USING_WDT static void wdt_test(void) { rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL); @@ -712,5 +730,106 @@ static int wdt_task(int argc, char *argv[]) return -1; } MSH_CMD_EXPORT(wdt_task, wdt task operation); +#endif +/* usbd test */ +#ifdef BSP_USING_USBD +static void usbd_test(void *parameter) +{ + rt_device_t dev = RT_NULL; + char dev_name[] = "vcom"; + char buf[] = "usbd vcom test!\r\n"; + dev = rt_device_find(dev_name); + + if (dev) + { + rt_device_open(dev, RT_DEVICE_FLAG_RDWR); + } + else + { + rt_kprintf("Device with name %s not found.\n",dev_name); + rt_thread_t tid = rt_thread_self(); + rt_thread_delete(tid); + } + while (1) + { + rt_device_write(dev, 0, buf, rt_strlen(buf)); + rt_thread_mdelay(500); + } +} + +static int usbd_task(int argc, char *argv[]) +{ + rt_err_t ret = -RT_ERROR; + + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + /* Gpio input test tasks */ + rt_thread_t usbd_vcom_task = rt_thread_create("usbd_vcom_task", + usbd_test, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (usbd_vcom_task != RT_NULL) + { + rt_thread_startup(usbd_vcom_task); + rt_kprintf("The usbd vcom task is registered.\n"); + } + else + { + rt_kprintf("usbd vcom task registration failed.\n"); + } + ret = RT_EOK; + } + else if(rt_strcmp(argv[1],"stop") == 0) + { + ret = RT_EOK; + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s stop\n",__func__); + } + return ret; +} +MSH_CMD_EXPORT(usbd_task, usbd task operation); +#endif +#ifdef BSP_USING_SDIO +int mnt_init(void) +{ + rt_device_t dev = RT_NULL; + char dev_name[] = BSP_USING_SDIO_NAME; + rt_thread_mdelay(1000); + + dev = rt_device_find(dev_name); + if(dev) + { + if(dfs_mount("sd0","/","elm",0,0) == RT_EOK) + { + rt_kprintf("dfs mount success!\r\n"); + } + else + { + rt_kprintf("dfs mount failed!\r\n"); + rt_kprintf("Formatting the SD card!\r\n"); + dfs_mkfs("elm",dev_name); + if(dfs_mount("sd0","/","elm",0,0) == RT_EOK) + { + rt_kprintf("dfs mount success!\r\n"); + } + else + { + rt_kprintf("dfs mount failed!\r\n"); + rt_kprintf("Exit SD card mount!\r\n"); + } + } + } + return 0; +} +INIT_FS_EXPORT(mnt_init); +#endif /* BSP_USING_SDIO */ #endif /* BSP_USING_TEST */ diff --git a/bsp/ht32/ht32f12366/board/Kconfig b/bsp/ht32/ht32f12366/board/Kconfig index 0623d4e30e..78fde32927 100644 --- a/bsp/ht32/ht32f12366/board/Kconfig +++ b/bsp/ht32/ht32f12366/board/Kconfig @@ -126,7 +126,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_UART bool "Enable UART" default n - select RT_USING_SERIAL + select RT_USING_SERIAL if BSP_USING_UART if BSP_USING_UART config BSP_USING_USART0 bool "Enable USART0" @@ -306,6 +306,141 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_WDT string "wdt device name" default "wdt" + + menuconfig BSP_USING_CAN + bool "Enable CAN" + depends on SOC_HT32F53241 || SOC_HT32F53242 || SOC_HT32F53252 + default n + select RT_USING_CAN if BSP_USING_CAN + config BSP_USING_CAN_NAME + depends on BSP_USING_CAN + string "can device name" + default "can" + if BSP_USING_CAN + config CAN_DEFAULT_BASE_CONFIGURATION + choice + prompt "Default CAN baud rate" + default BSP_USING_CAN500kBaud + config BSP_USING_CAN1MBaud + bool "CAN1MBaud" + config BSP_USING_CAN800kBaud + bool "CAN800kBaud" + config BSP_USING_CAN500kBaud + bool "CAN500kBaud" + config BSP_USING_CAN250kBaud + bool "CAN250kBaud" + config BSP_USING_CAN125kBaud + bool "CAN125kBaud" + config BSP_USING_CAN100kBaud + bool "CAN100kBaud" + config BSP_USING_CAN50kBaud + bool "CAN50kBaud" + config BSP_USING_CAN20kBaud + bool "CAN20kBaud" + config BSP_USING_CAN10kBaud + bool "CAN10kBaud" + endchoice + choice + prompt "Default CAN mode" + default BSP_USING_RT_CAN_MODE_NORMAL + config BSP_USING_RT_CAN_MODE_NORMAL + bool "RT_CAN_MODE_NORMAL" + config BSP_USING_RT_CAN_MODE_LISTEN + bool "RT_CAN_MODE_LISTEN" + config BSP_USING_RT_CAN_MODE_LOOPBACK + bool "RT_CAN_MODE_LOOPBACK" + config BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN + bool "RT_CAN_MODE_LOOPBACKANLISTEN" + endchoice + + config BSP_USING_CAN_BAUD + int + default 1000000 if BSP_USING_CAN1MBaud + default 800000 if BSP_USING_CAN800kBaud + default 500000 if BSP_USING_CAN500kBaud + default 250000 if BSP_USING_CAN250kBaud + default 125000 if BSP_USING_CAN125kBaud + default 100000 if BSP_USING_CAN100kBaud + default 50000 if BSP_USING_CAN50kBaud + default 20000 if BSP_USING_CAN20kBaud + default 10000 if BSP_USING_CAN10kBaud + + config BSP_USING_CAN_MODE + int + default 0 if BSP_USING_RT_CAN_MODE_NORMAL + default 1 if BSP_USING_RT_CAN_MODE_LISTEN + default 2 if BSP_USING_RT_CAN_MODE_LOOPBACK + default 3 if BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN + + config CAN_DEFAULT_FILTER_TABLE_CONFIGURATION + choice + prompt "Default filter id mode" + default BSP_USING_CAN_STD_ID + config BSP_USING_CAN_STD_ID + bool "CAN_STD_ID" + config BSP_USING_CAN_EXT_ID + bool "CAN_EXT_ID" + endchoice + + choice + prompt "Default filter frame mode" + default BSP_USING_CAN_DATA_FRAME + config BSP_USING_CAN_DATA_FRAME + bool "CAN_DATA_FRAME" + config BSP_USING_CAN_REMOTE_FRAME + bool "CAN_REMOTE_FRAME" + endchoice + + config BSP_USING_CAN_ID_MODE + int + default 0 if BSP_USING_CAN_STD_ID + default 1 if BSP_USING_CAN_EXT_ID + + config BSP_USING_CAN_FRAME_MODE + int + default 0 if BSP_USING_CAN_REMOTE_FRAME + default 1 if BSP_USING_CAN_DATA_FRAME + + config BSP_USING_CAN_MSG_NUM + int "Default filter table number" + range 0 31 + default 0 + + config BSP_USING_CAN_ID + hex "Default filter arbitration bit(ID)" + range 0 0x7FF if BSP_USING_CAN_STD_ID + default 0x541 if BSP_USING_CAN_STD_ID + range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + default 0x541 if BSP_USING_CAN_EXT_ID + + config BSP_USING_CAN_MASK + hex "Default filter mask bit(MASK)" + range 0 0x7FF if BSP_USING_CAN_STD_ID + default 0x7FF if BSP_USING_CAN_STD_ID + range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + default 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + depends on SOC_HT32F12345 || SOC_HT32F12365 || SOC_HT32F12366 + default n + select RT_USING_SDIO if BSP_USING_SDIO + select RT_USING_DFS if BSP_USING_SDIO + config BSP_USING_SDIO_NAME + depends on BSP_USING_SDIO + string "sdio device name" + default "sd0" + + menuconfig BSP_USING_USBD + bool "Enable USB BUS" + default n + select RT_USING_USB_DEVICE if BSP_USING_USBD + config BSP_USING_USBD_NAME + depends on BSP_USING_USBD + string "usbd device name" + default "usbd" endmenu menu "Board extended module Drivers" diff --git a/bsp/ht32/ht32f12366/board/inc/board.h b/bsp/ht32/ht32f12366/board/inc/board.h index c4a817d79b..91b93e424e 100644 --- a/bsp/ht32/ht32f12366/board/inc/board.h +++ b/bsp/ht32/ht32f12366/board/inc/board.h @@ -23,6 +23,10 @@ #include "drv_spi.h" #endif +#ifdef BSP_USING_SDIO +#include "dfs_fs.h" +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/bsp/ht32/ht32f12366/board/inc/ht32_msp.h b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h index 3b6a4624e4..ba94061427 100644 --- a/bsp/ht32/ht32f12366/board/inc/ht32_msp.h +++ b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -100,7 +100,7 @@ extern "C" { #define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION) #endif -#endif +#endif /* BSP_USING_UART */ /* SPI gpio */ #ifdef BSP_USING_SPI @@ -156,7 +156,7 @@ extern "C" { #define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION) #endif -#endif +#endif /* BSP_USING_SPI */ /* I2C gpio */ #ifdef BSP_USING_I2C_HW @@ -198,7 +198,8 @@ extern "C" { #define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION) #endif -#endif +#endif /* BSP_USING_I2C_HW */ + /* ADC gpio */ #ifdef BSP_USING_ADC #ifdef BSP_USING_ADC0 @@ -335,12 +336,66 @@ extern "C" { #define HTCFG_ADC1CH7_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH7_AFION) #endif -#endif +#endif /* BSP_USING_ADC */ +/* SDIO gpio */ +#ifdef BSP_USING_SDIO + #define HTCFG_SDIO_IPN SDIO + + #define _HTCFG_SDIO_CLK_GPIOX A + #define _HTCFG_SDIO_CLK_GPION 5 + + #define _HTCFG_SDIO_CMD_GPIOX A + #define _HTCFG_SDIO_CMD_GPION 4 + + #define _HTCFG_SDIO_DAT0_GPIOX C + #define _HTCFG_SDIO_DAT0_GPION 9 + + #define _HTCFG_SDIO_DAT1_GPIOX C + #define _HTCFG_SDIO_DAT1_GPION 10 + + #define _HTCFG_SDIO_DAT2_GPIOX C + #define _HTCFG_SDIO_DAT2_GPION 11 + + #define _HTCFG_SDIO_DAT3_GPIOX C + #define _HTCFG_SDIO_DAT3_GPION 12 + + #define HTCFG_SDIO_CLK_GPIO_CLK STRCAT2(P, _HTCFG_SDIO_CLK_GPIOX) + #define HTCFG_SDIO_CLK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SDIO_CLK_GPIOX) + #define HTCFG_SDIO_CLK_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_SDIO_CLK_GPIOX) + #define HTCFG_SDIO_CLK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SDIO_CLK_GPION) + + #define HTCFG_SDIO_CMD_GPIO_CLK STRCAT2(P, _HTCFG_SDIO_CMD_GPIOX) + #define HTCFG_SDIO_CMD_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SDIO_CMD_GPIOX) + #define HTCFG_SDIO_CMD_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_SDIO_CMD_GPIOX) + #define HTCFG_SDIO_CMD_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SDIO_CMD_GPION) + + #define HTCFG_SDIO_DAT0_GPIO_CLK STRCAT2(P, _HTCFG_SDIO_DAT0_GPIOX) + #define HTCFG_SDIO_DAT0_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SDIO_DAT0_GPIOX) + #define HTCFG_SDIO_DAT0_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_SDIO_DAT0_GPIOX) + #define HTCFG_SDIO_DAT0_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SDIO_DAT0_GPION) + + #define HTCFG_SDIO_DAT1_GPIO_CLK STRCAT2(P, _HTCFG_SDIO_DAT1_GPIOX) + #define HTCFG_SDIO_DAT1_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SDIO_DAT1_GPIOX) + #define HTCFG_SDIO_DAT1_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_SDIO_DAT1_GPIOX) + #define HTCFG_SDIO_DAT1_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SDIO_DAT1_GPION) + + #define HTCFG_SDIO_DAT2_GPIO_CLK STRCAT2(P, _HTCFG_SDIO_DAT2_GPIOX) + #define HTCFG_SDIO_DAT2_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SDIO_DAT2_GPIOX) + #define HTCFG_SDIO_DAT2_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_SDIO_DAT2_GPIOX) + #define HTCFG_SDIO_DAT2_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SDIO_DAT2_GPION) + + #define HTCFG_SDIO_DAT3_GPIO_CLK STRCAT2(P, _HTCFG_SDIO_DAT3_GPIOX) + #define HTCFG_SDIO_DAT3_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SDIO_DAT3_GPIOX) + #define HTCFG_SDIO_DAT3_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_SDIO_DAT3_GPIOX) + #define HTCFG_SDIO_DAT3_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SDIO_DAT3_GPION) + +#endif /* BSP_USING_SDIO */ void ht32_usart_gpio_init(void *instance); void ht32_spi_gpio_init(void *instance); void ht32_hardware_i2c_gpio_init(void *instance); void ht32_adc_gpio_init(void *instance,int8_t channel); +void ht32_sdio_gpio_init(void *instance); #ifdef __cplusplus } diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h index 432b323d7a..e617b95e8a 100644 --- a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h +++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h @@ -58,7 +58,7 @@ // Endpoint5 Interrupt Enable (EP5IE) // Endpoint6 Interrupt Enable (EP6IE) // Endpoint7 Interrupt Enable (EP7IE) -#define _UIER (0x011D) +#define _UIER (0xFF1D) // @@ -96,7 +96,7 @@ /* Endpoint1 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint1 Configuration -#define _EP1_ENABLE (0) +#define _EP1_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -114,7 +114,7 @@ // Endpoint Transfer Type // <2=> Bulk // <3=> Interrupt -#define _EP1_TYPR (3) +#define _EP1_TYPR (2) // Endpoint Direction (EPDIR) // <1=> IN @@ -123,7 +123,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> /* Maximum: 64 Bytes */ -#define _EP1LEN_TMP (8) +#define _EP1LEN_TMP (64) // Endpoint Interrupt Enable Settings (EPIER) // Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> @@ -135,7 +135,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP1_IER (0x10) +#define _EP1_IER (0x12) // // @@ -144,7 +144,7 @@ /* Endpoint2 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint2 Configuration -#define _EP2_ENABLE (0) +#define _EP2_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -162,7 +162,7 @@ // Endpoint Transfer Type // <2=> Bulk // <3=> Interrupt -#define _EP2_TYPR (3) +#define _EP2_TYPR (2) // Endpoint Direction (EPDIR) // <1=> IN @@ -171,7 +171,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> /* Maximum: 64 Bytes */ -#define _EP2LEN_TMP (8) +#define _EP2LEN_TMP (64) // Endpoint Interrupt Enable Settings (EPIER) // Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> @@ -183,7 +183,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP2_IER (0x002) +#define _EP2_IER (0x012) // // @@ -191,7 +191,7 @@ /* Endpoint3 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint3 Configuration -#define _EP3_ENABLE (0) +#define _EP3_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -218,7 +218,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> /* Maximum: 64 Bytes */ -#define _EP3LEN_TMP (8) +#define _EP3LEN_TMP (64) // Endpoint Interrupt Enable Settings (EPIER) // Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> @@ -230,7 +230,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP3_IER (0x10) +#define _EP3_IER (0x12) // // @@ -238,7 +238,7 @@ /* Endpoint4 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint4 Configuration -#define _EP4_ENABLE (0) +#define _EP4_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -266,7 +266,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP4LEN_TMP (8) +#define _EP4LEN_TMP (64) // Single/Double Buffer Selection (SDBS) // <0=> Single Buffer @@ -283,7 +283,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP4_IER (0x02) +#define _EP4_IER (0x12) // // @@ -292,7 +292,7 @@ /* Endpoint5 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint5 Configuration -#define _EP5_ENABLE (0) +#define _EP5_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -311,7 +311,7 @@ // <1=> Isochronous // <2=> Bulk // <3=> Interrupt -#define _EP5_TYPR (3) +#define _EP5_TYPR (1) // Endpoint Direction (EPDIR) // <1=> IN @@ -320,7 +320,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP5LEN_TMP (8) +#define _EP5LEN_TMP (64) // Single/Double Buffer Selection (SDBS) @@ -338,7 +338,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP5_IER (0x10) +#define _EP5_IER (0x12) // // @@ -347,7 +347,7 @@ /* Endpoint6 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint6 Configuration -#define _EP6_ENABLE (0) +#define _EP6_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -366,7 +366,7 @@ // <1=> Isochronous // <2=> Bulk // <3=> Interrupt -#define _EP6_TYPR (3) +#define _EP6_TYPR (1) // Endpoint Direction (EPDIR) // <1=> IN @@ -375,7 +375,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP6LEN_TMP (8) +#define _EP6LEN_TMP (64) // Single/Double Buffer Selection (SDBS) // <0=> Single Buffer @@ -392,7 +392,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP6_IER (0x02) +#define _EP6_IER (0x12) // // @@ -401,7 +401,7 @@ /* Endpoint7 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint7 Configuration -#define _EP7_ENABLE (0) +#define _EP7_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -429,7 +429,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP7LEN_TMP (8) +#define _EP7LEN_TMP (64) // Single/Double Buffer Selection (SDBS) // <0=> Single Buffer @@ -446,7 +446,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP7_IER (0x10) +#define _EP7_IER (0x12) // // diff --git a/bsp/ht32/ht32f12366/board/src/ht32_msp.c b/bsp/ht32/ht32f12366/board/src/ht32_msp.c index d8d055ef4e..0208647be3 100644 --- a/bsp/ht32/ht32f12366/board/src/ht32_msp.c +++ b/bsp/ht32/ht32f12366/board/src/ht32_msp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -69,7 +69,7 @@ void ht32_usart_gpio_init(void *instance) } #endif } -#endif +#endif /* BSP_USING_UART */ /* GPIO configuration for SPI */ #ifdef BSP_USING_SPI @@ -104,7 +104,7 @@ void ht32_spi_gpio_init(void *instance) } #endif } -#endif +#endif /* BSP_USING_SPI */ /* GPIO configuration for I2C */ #ifdef BSP_USING_I2C_HW @@ -135,7 +135,7 @@ void ht32_hardware_i2c_gpio_init(void *instance) } #endif } -#endif +#endif /* BSP_USING_I2C_HW */ /* GPIO configuration for ADC */ #ifdef BSP_USING_ADC void ht32_adc_gpio_init(void *instance,int8_t channel) @@ -247,4 +247,42 @@ void ht32_adc_gpio_init(void *instance,int8_t channel) } #endif } -#endif +#endif /* BSP_USING_ADC */ + +/* GPIO configuration for SDIO */ +#ifdef BSP_USING_SDIO +void ht32_sdio_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_SDIO_TypeDef *sdio_x = (HT_SDIO_TypeDef *)instance; + if(HT_SDIO == sdio_x) + { + CKCUClock.Bit.HTCFG_SDIO_CLK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SDIO_CMD_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SDIO_DAT0_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SDIO_DAT1_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SDIO_DAT2_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SDIO_DAT3_GPIO_CLK = 1; + CKCUClock.Bit.SDIO = 1; + CKCUClock.Bit.PDMA = 1; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* Configure SDIO pins */ + AFIO_GPxConfig(HTCFG_SDIO_CLK_GPIO_ID, HTCFG_SDIO_CLK_GPIO_PIN, AFIO_FUN_SDIO); + AFIO_GPxConfig(HTCFG_SDIO_CMD_GPIO_ID, HTCFG_SDIO_CMD_GPIO_PIN, AFIO_FUN_SDIO); + AFIO_GPxConfig(HTCFG_SDIO_DAT0_GPIO_ID, HTCFG_SDIO_DAT0_GPIO_PIN, AFIO_FUN_SDIO); + AFIO_GPxConfig(HTCFG_SDIO_DAT1_GPIO_ID, HTCFG_SDIO_DAT1_GPIO_PIN, AFIO_FUN_SDIO); + AFIO_GPxConfig(HTCFG_SDIO_DAT2_GPIO_ID, HTCFG_SDIO_DAT2_GPIO_PIN, AFIO_FUN_SDIO); + AFIO_GPxConfig(HTCFG_SDIO_DAT3_GPIO_ID, HTCFG_SDIO_DAT3_GPIO_PIN, AFIO_FUN_SDIO); + /* 配置SDIO引脚驱动能力 */ + GPIO_DriveConfig(HTCFG_SDIO_CLK_GPIO_PORT, HTCFG_SDIO_CLK_GPIO_PIN, GPIO_DV_8MA); + GPIO_DriveConfig(HTCFG_SDIO_CMD_GPIO_PORT, HTCFG_SDIO_CMD_GPIO_PIN, GPIO_DV_8MA); + GPIO_DriveConfig(HTCFG_SDIO_DAT0_GPIO_PORT, HTCFG_SDIO_DAT0_GPIO_PIN, GPIO_DV_8MA); + GPIO_DriveConfig(HTCFG_SDIO_DAT1_GPIO_PORT, HTCFG_SDIO_DAT1_GPIO_PIN, GPIO_DV_8MA); + GPIO_DriveConfig(HTCFG_SDIO_DAT2_GPIO_PORT, HTCFG_SDIO_DAT2_GPIO_PIN, GPIO_DV_8MA); + GPIO_DriveConfig(HTCFG_SDIO_DAT3_GPIO_PORT, HTCFG_SDIO_DAT3_GPIO_PIN, GPIO_DV_8MA); + + } +} +#endif /* BSP_USING_SDIO */ diff --git a/bsp/ht32/ht32f12366/project.uvoptx b/bsp/ht32/ht32f12366/project.uvoptx index 5e3bbba332..06f3300cfb 100644 --- a/bsp/ht32/ht32f12366/project.uvoptx +++ b/bsp/ht32/ht32f12366/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -186,18 +186,6 @@ 0 0 - - 1 - 2 - 1 - 0 - 0 - 0 - applications\test.c - test.c - 0 - 0 - @@ -208,7 +196,7 @@ 0 2 - 3 + 2 1 0 0 @@ -220,7 +208,7 @@ 2 - 4 + 3 1 0 0 @@ -232,7 +220,7 @@ 2 - 5 + 4 1 0 0 @@ -244,7 +232,7 @@ 2 - 6 + 5 1 0 0 @@ -256,7 +244,7 @@ 2 - 7 + 6 1 0 0 @@ -268,7 +256,7 @@ 2 - 8 + 7 1 0 0 @@ -280,7 +268,7 @@ 2 - 9 + 8 1 0 0 @@ -292,7 +280,7 @@ 2 - 10 + 9 1 0 0 @@ -312,7 +300,7 @@ 0 3 - 11 + 10 1 0 0 @@ -322,6 +310,18 @@ 0 0 + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + 3 12 @@ -329,8 +329,8 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - i2c-bit-ops.c + ..\..\..\components\drivers\ipc\completion_up.c + completion_up.c 0 0 @@ -341,42 +341,6 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c_core.c - i2c_core.c - 0 - 0 - - - 3 - 14 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c - 0 - 0 - - - 3 - 15 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\ipc\completion.c - completion.c - 0 - 0 - - - 3 - 16 - 1 - 0 - 0 - 0 ..\..\..\components\drivers\ipc\condvar.c condvar.c 0 @@ -384,7 +348,7 @@ 3 - 17 + 14 1 0 0 @@ -396,7 +360,7 @@ 3 - 18 + 15 1 0 0 @@ -408,7 +372,7 @@ 3 - 19 + 16 1 0 0 @@ -420,7 +384,7 @@ 3 - 20 + 17 1 0 0 @@ -432,7 +396,7 @@ 3 - 21 + 18 1 0 0 @@ -444,7 +408,7 @@ 3 - 22 + 19 1 0 0 @@ -456,73 +420,25 @@ 3 - 23 + 20 1 0 0 0 - ..\..\..\components\drivers\misc\adc.c - adc.c + ..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c 0 0 3 - 24 + 21 1 0 0 0 - ..\..\..\components\drivers\pin\pin.c - pin.c - 0 - 0 - - - 3 - 25 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 3 - 26 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_core.c - spi_core.c - 0 - 0 - - - 3 - 27 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_dev.c - spi_dev.c - 0 - 0 - - - 3 - 28 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\watchdog\watchdog.c - watchdog.c + ..\..\..\components\drivers\serial\dev_serial.c + dev_serial.c 0 0 @@ -536,7 +452,7 @@ 0 4 - 29 + 22 1 0 0 @@ -548,7 +464,7 @@ 4 - 30 + 23 1 0 0 @@ -560,7 +476,7 @@ 4 - 31 + 24 2 0 0 @@ -572,7 +488,7 @@ 4 - 32 + 25 1 0 0 @@ -584,7 +500,7 @@ 4 - 33 + 26 1 0 0 @@ -596,7 +512,7 @@ 4 - 34 + 27 1 0 0 @@ -616,7 +532,19 @@ 0 5 - 35 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 29 1 0 0 @@ -628,19 +556,7 @@ 5 - 36 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - 5 - 37 + 30 1 0 0 @@ -652,13 +568,13 @@ 5 - 38 + 31 1 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\components\finsh\msh.c + msh.c 0 0 @@ -672,7 +588,7 @@ 0 6 - 39 + 32 1 0 0 @@ -684,7 +600,7 @@ 6 - 40 + 33 1 0 0 @@ -696,7 +612,31 @@ 6 - 41 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\defunct.c + defunct.c + 0 + 0 + + + 6 + 36 1 0 0 @@ -708,7 +648,7 @@ 6 - 42 + 37 1 0 0 @@ -720,7 +660,7 @@ 6 - 43 + 38 1 0 0 @@ -732,31 +672,7 @@ 6 - 44 - 1 - 0 - 0 - 0 - ..\..\..\src\klibc\kstdio.c - kstdio.c - 0 - 0 - - - 6 - 45 - 1 - 0 - 0 - 0 - ..\..\..\src\klibc\kstring.c - kstring.c - 0 - 0 - - - 6 - 46 + 39 1 0 0 @@ -768,7 +684,7 @@ 6 - 47 + 40 1 0 0 @@ -780,7 +696,7 @@ 6 - 48 + 41 1 0 0 @@ -792,7 +708,7 @@ 6 - 49 + 42 1 0 0 @@ -804,7 +720,7 @@ 6 - 50 + 43 1 0 0 @@ -816,7 +732,7 @@ 6 - 51 + 44 1 0 0 @@ -828,7 +744,7 @@ 6 - 52 + 45 1 0 0 @@ -840,7 +756,7 @@ 6 - 53 + 46 1 0 0 @@ -852,7 +768,7 @@ 6 - 54 + 47 1 0 0 @@ -865,14 +781,82 @@ - libcpu + klibc 0 0 0 0 7 - 55 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + libcpu + 0 + 0 + 0 + 0 + + 8 + 53 1 0 0 @@ -883,8 +867,8 @@ 0 - 7 - 56 + 8 + 54 1 0 0 @@ -895,8 +879,8 @@ 0 - 7 - 57 + 8 + 55 1 0 0 @@ -907,8 +891,8 @@ 0 - 7 - 58 + 8 + 56 2 0 0 @@ -919,8 +903,8 @@ 0 - 7 - 59 + 8 + 57 1 0 0 @@ -939,43 +923,67 @@ 0 0 - 8 + 9 + 58 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c + ht32f1xxxx_i2s.c + 0 + 0 + + + 9 + 59 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_mctm.c + ht32f1xxxx_mctm.c + 0 + 0 + + + 9 60 1 0 0 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_wdt.c - ht32f1xxxx_wdt.c + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_bftm.c + ht32f1xxxx_bftm.c 0 0 - 8 + 9 61 1 0 0 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sci.c - ht32f1xxxx_sci.c + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_flash.c + ht32f1xxxx_flash.c 0 0 - 8 + 9 62 1 0 0 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rstcu.c - ht32f1xxxx_rstcu.c + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_tm.c + ht32f1xxxx_tm.c 0 0 - 8 + 9 63 1 0 @@ -987,260 +995,20 @@ 0 - 8 + 9 64 1 0 0 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_tm.c - ht32f1xxxx_tm.c - 0 - 0 - - - 8 - 65 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ckcu.c - ht32f1xxxx_ckcu.c - 0 - 0 - - - 8 - 66 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usart.c - ht32f1xxxx_usart.c - 0 - 0 - - - 8 - 67 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_aes.c - ht32f1xxxx_aes.c - 0 - 0 - - - 8 - 68 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_flash.c - ht32f1xxxx_flash.c - 0 - 0 - - - 8 - 69 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_gpio.c - ht32f1xxxx_gpio.c - 0 - 0 - - - 8 - 70 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32_cm3_misc.c - ht32_cm3_misc.c - 0 - 0 - - - 8 - 71 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_crc.c - ht32f1xxxx_crc.c - 0 - 0 - - - 8 - 72 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c - ht32f1xxxx_sdio.c - 0 - 0 - - - 8 - 73 - 1 - 0 - 0 - 0 ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ebi.c ht32f1xxxx_ebi.c 0 0 - 8 - 74 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c - ht32f1xxxx_cmp.c - 0 - 0 - - - 8 - 75 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f2xxxx_csif.c - ht32f2xxxx_csif.c - 0 - 0 - - - 8 - 76 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c - ht32f1xxxx_i2c.c - 0 - 0 - - - 8 - 77 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c - ht32f1xxxx_adc.c - 0 - 0 - - - 8 - 78 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c - ht32f1xxxx_pwrcu.c - 0 - 0 - - - 8 - 79 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c - ht32f1xxxx_pdma.c - 0 - 0 - - - 8 - 80 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c - system_ht32f1xxxx_02.c - 0 - 0 - - - 8 - 81 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_mctm.c - ht32f1xxxx_mctm.c - 0 - 0 - - - 8 - 82 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c - ht32f1xxxx_spi.c - 0 - 0 - - - 8 - 83 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_bftm.c - ht32f1xxxx_bftm.c - 0 - 0 - - - 8 - 84 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c - ht32f1xxxx_i2s.c - 0 - 0 - - - 8 - 85 + 9 + 65 1 0 0 @@ -1251,8 +1019,20 @@ 0 - 8 - 86 + 9 + 66 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_crc.c + ht32f1xxxx_crc.c + 0 + 0 + + + 9 + 67 1 0 0 @@ -1262,6 +1042,210 @@ 0 0 + + 9 + 68 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rstcu.c + ht32f1xxxx_rstcu.c + 0 + 0 + + + 9 + 69 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_aes.c + ht32f1xxxx_aes.c + 0 + 0 + + + 9 + 70 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c + system_ht32f1xxxx_02.c + 0 + 0 + + + 9 + 71 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c + ht32f1xxxx_cmp.c + 0 + 0 + + + 9 + 72 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32_cm3_misc.c + ht32_cm3_misc.c + 0 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sci.c + ht32f1xxxx_sci.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c + ht32f1xxxx_pwrcu.c + 0 + 0 + + + 9 + 75 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c + ht32f1xxxx_spi.c + 0 + 0 + + + 9 + 76 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c + ht32f1xxxx_adc.c + 0 + 0 + + + 9 + 77 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c + ht32f1xxxx_sdio.c + 0 + 0 + + + 9 + 78 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usart.c + ht32f1xxxx_usart.c + 0 + 0 + + + 9 + 79 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ckcu.c + ht32f1xxxx_ckcu.c + 0 + 0 + + + 9 + 80 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_gpio.c + ht32f1xxxx_gpio.c + 0 + 0 + + + 9 + 81 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c + ht32f1xxxx_pdma.c + 0 + 0 + + + 9 + 82 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f2xxxx_csif.c + ht32f2xxxx_csif.c + 0 + 0 + + + 9 + 83 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_wdt.c + ht32f1xxxx_wdt.c + 0 + 0 + + + 9 + 84 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c + ht32f1xxxx_i2c.c + 0 + 0 + diff --git a/bsp/ht32/ht32f12366/project.uvprojx b/bsp/ht32/ht32f12366/project.uvprojx index 0bf964bce3..578dcd6fca 100644 --- a/bsp/ht32/ht32f12366/project.uvprojx +++ b/bsp/ht32/ht32f12366/project.uvprojx @@ -15,8 +15,8 @@ HT32F12366 Holtek - Holtek.HT32_DFP.1.0.19 - http://mcu.holtek.com.tw/pack + Holtek.HT32_DFP.1.0.55 + https://mcu.holtek.com.tw/pack IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -332,10 +332,10 @@ 0 0 - - __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366, __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, __RTTHREAD__ + --gnu + __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366, __RTTHREAD__, __STDC_LIMIT_MACROS, RT_USING_LIBC, RT_USING_ARMLIBC - ..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\include;..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\inc;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\libraries\ht32_drivers;board\inc;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;applications;..\libraries\HT32_STD_1xxxx_FWLib\library\CMSIS\Include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;.;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Include;..\..\..\components\finsh;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m3 + ..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\eventfd;board\inc;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\finsh;..\..\..\components\libc\posix\ipc;..\libraries\usbd_library\inc;..\libraries\ht32_drivers;applications;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\include;..\..\..\components\drivers\smp_call;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\inc;.;..\libraries\HT32_STD_1xxxx_FWLib\library\CMSIS\Include;..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Include;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\phy;..\..\..\components\drivers\include @@ -384,11 +384,6 @@ 1 applications\main.c - - test.c - 1 - applications\test.c - @@ -495,9 +490,9 @@ - i2c-bit-ops.c + completion_comm.c 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c + ..\..\..\components\drivers\ipc\completion_comm.c 2 @@ -550,119 +545,9 @@ - i2c_core.c + completion_up.c 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - completion.c - 1 - ..\..\..\components\drivers\ipc\completion.c + ..\..\..\components\drivers\ipc\completion_up.c 2 @@ -1100,9 +985,9 @@ - adc.c + dev_pin.c 1 - ..\..\..\components\drivers\misc\adc.c + ..\..\..\components\drivers\pin\dev_pin.c 2 @@ -1155,229 +1040,9 @@ - pin.c + dev_serial.c 1 - ..\..\..\components\drivers\pin\pin.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - watchdog.c - 1 - ..\..\..\components\drivers\watchdog\watchdog.c + ..\..\..\components\drivers\serial\dev_serial.c 2 @@ -1469,25 +1134,25 @@ Finsh + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + shell.c 1 ..\..\..\components\finsh\shell.c - - msh.c - 1 - ..\..\..\components\finsh\msh.c - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - cmd.c + msh.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\msh.c @@ -1604,6 +1269,116 @@ + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + idle.c 1 @@ -1769,116 +1544,6 @@ - - kstdio.c - 1 - ..\..\..\src\klibc\kstdio.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_KERNEL_SOURCE__ - - - - - - - - - kstring.c - 1 - ..\..\..\src\klibc\kstring.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_KERNEL_SOURCE__ - - - - - - - kservice.c 1 @@ -2376,6 +2041,36 @@ + + klibc + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + libcpu @@ -2410,140 +2105,140 @@ Libraries - ht32f1xxxx_wdt.c + ht32f1xxxx_i2s.c 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_wdt.c - - - ht32f1xxxx_sci.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sci.c - - - ht32f1xxxx_rstcu.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rstcu.c - - - ht32f1xxxx_usbd.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usbd.c - - - ht32f1xxxx_tm.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_tm.c - - - ht32f1xxxx_ckcu.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ckcu.c - - - ht32f1xxxx_usart.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usart.c - - - ht32f1xxxx_aes.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_aes.c - - - ht32f1xxxx_flash.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_flash.c - - - ht32f1xxxx_gpio.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_gpio.c - - - ht32_cm3_misc.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32_cm3_misc.c - - - ht32f1xxxx_crc.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_crc.c - - - ht32f1xxxx_sdio.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c - - - ht32f1xxxx_ebi.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ebi.c - - - ht32f1xxxx_cmp.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c - - - ht32f2xxxx_csif.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f2xxxx_csif.c - - - ht32f1xxxx_i2c.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c - - - ht32f1xxxx_adc.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c - - - ht32f1xxxx_pwrcu.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c - - - ht32f1xxxx_pdma.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c - - - system_ht32f1xxxx_02.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c ht32f1xxxx_mctm.c 1 ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_mctm.c - - ht32f1xxxx_spi.c - 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c - ht32f1xxxx_bftm.c 1 ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_bftm.c - ht32f1xxxx_i2s.c + ht32f1xxxx_flash.c 1 - ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_flash.c + + + ht32f1xxxx_tm.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_tm.c + + + ht32f1xxxx_usbd.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usbd.c + + + ht32f1xxxx_ebi.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ebi.c ht32f1xxxx_exti.c 1 ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_exti.c + + ht32f1xxxx_crc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_crc.c + ht32f1xxxx_rtc.c 1 ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rtc.c + + ht32f1xxxx_rstcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rstcu.c + + + ht32f1xxxx_aes.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_aes.c + + + system_ht32f1xxxx_02.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c + + + ht32f1xxxx_cmp.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c + + + ht32_cm3_misc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32_cm3_misc.c + + + ht32f1xxxx_sci.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sci.c + + + ht32f1xxxx_pwrcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c + + + ht32f1xxxx_spi.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c + + + ht32f1xxxx_adc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c + + + ht32f1xxxx_sdio.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c + + + ht32f1xxxx_usart.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usart.c + + + ht32f1xxxx_ckcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ckcu.c + + + ht32f1xxxx_gpio.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_gpio.c + + + ht32f1xxxx_pdma.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c + + + ht32f2xxxx_csif.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f2xxxx_csif.c + + + ht32f1xxxx_wdt.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_wdt.c + + + ht32f1xxxx_i2c.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c + diff --git a/bsp/ht32/ht32f12366/rtconfig.h b/bsp/ht32/ht32f12366/rtconfig.h index 39d7f03646..fa25b0a78e 100644 --- a/bsp/ht32/ht32f12366/rtconfig.h +++ b/bsp/ht32/ht32f12366/rtconfig.h @@ -1,29 +1,81 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - /* RT-Thread Kernel */ +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ #define RT_NAME_MAX 8 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 -/* kservice optimization */ +/* kservice options */ -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT +/* end of kservice options */ /* Inter-Thread communication */ @@ -32,6 +84,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ @@ -41,12 +94,14 @@ #define RT_MEMHEAP_FAST_MODE #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart0" #define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS #define ARCH_ARM @@ -76,6 +131,7 @@ /* DFS: device virtual file system */ +/* end of DFS: device virtual file system */ /* Device Drivers */ @@ -85,15 +141,8 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS -#define RT_USING_ADC -#define RT_USING_SPI -#define RT_USING_WDT #define RT_USING_PIN - -/* Using USB */ - +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -105,6 +154,8 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ @@ -114,18 +165,30 @@ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -136,57 +199,78 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ @@ -194,69 +278,94 @@ /* STM32 HAL & SDK Drivers */ +/* end of STM32 HAL & SDK Drivers */ /* Infineon HAL Packages */ +/* end of Infineon HAL Packages */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ /* sensors drivers */ +/* end of sensors drivers */ /* touch drivers */ +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ #define SOC_FAMILY_HT32 #define SOC_SERIES_HT32F1 @@ -267,9 +376,11 @@ #define SOC_KERNEL #define CORTEX_M3 #define SOC_HT32F12366 +/* end of Chip Configuration */ /* Onboard Peripheral Drivers */ +/* end of Onboard Peripheral Drivers */ /* On-chip Peripheral Drivers */ @@ -277,8 +388,10 @@ #define BSP_USING_UART #define BSP_USING_USART0 #define BSP_USING_USART0_NAME "usart0" +/* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ +/* end of Hardware Drivers Config */ #endif diff --git a/bsp/ht32/ht32f12366/template.uvoptx b/bsp/ht32/ht32f12366/template.uvoptx index 4c6655f9dd..bca728b9ba 100644 --- a/bsp/ht32/ht32f12366/template.uvoptx +++ b/bsp/ht32/ht32f12366/template.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 diff --git a/bsp/ht32/ht32f12366/template.uvprojx b/bsp/ht32/ht32f12366/template.uvprojx index 9b24487b53..cc3940694f 100644 --- a/bsp/ht32/ht32f12366/template.uvprojx +++ b/bsp/ht32/ht32f12366/template.uvprojx @@ -15,8 +15,8 @@ HT32F12366 Holtek - Holtek.HT32_DFP.1.0.19 - http://mcu.holtek.com.tw/pack + Holtek.HT32_DFP.1.0.55 + https://mcu.holtek.com.tw/pack IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -332,7 +332,7 @@ 0 0 - + --gnu diff --git a/bsp/ht32/ht32f52352/.config b/bsp/ht32/ht32f52352/.config index 6ee81a5871..8456d0fbe7 100644 --- a/bsp/ht32/ht32f52352/.config +++ b/bsp/ht32/ht32f52352/.config @@ -1,15 +1,117 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# # # RT-Thread Kernel # + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_CPUS_NR=1 @@ -19,23 +121,24 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y +# CONFIG_RT_USING_OVERFLOW_CHECK is not set CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # -# kservice optimization +# kservice options # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice options + # CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set # # Inter-Thread communication @@ -47,6 +150,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -65,22 +169,20 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_THREADSAFE_PRINTF is not set -# CONFIG_RT_USING_SCHED_THREAD_CTX is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set +# end of RT-Thread Kernel + CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M0=y @@ -90,7 +192,7 @@ CONFIG_ARCH_ARM_CORTEX_M0=y # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 CONFIG_RT_MAIN_THREAD_PRIORITY=10 # CONFIG_RT_USING_LEGACY is not set CONFIG_RT_USING_MSH=y @@ -114,12 +216,15 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # DFS: device virtual file system # # CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set @@ -128,53 +233,40 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers # # C/C++ and POSIX layer @@ -192,6 +284,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer @@ -213,7 +307,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network @@ -222,12 +320,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -239,12 +339,25 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -253,7 +366,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -276,27 +388,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -319,6 +439,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -362,6 +484,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set # CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -372,6 +495,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -387,18 +511,22 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -410,12 +538,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -435,6 +566,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -484,6 +616,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_RT_TRACE is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -495,6 +628,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + # CONFIG_PKG_USING_AUNITY is not set # @@ -503,6 +638,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -513,6 +649,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -523,6 +660,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -570,6 +709,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers @@ -586,6 +726,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers # # Infineon HAL Packages @@ -600,6 +741,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_INFINEON_CSDIDAC is not set # CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set # CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -609,9 +752,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers # # sensors drivers @@ -681,6 +827,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -695,6 +842,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -767,6 +916,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -781,6 +931,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages @@ -791,6 +942,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -799,6 +951,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -807,6 +960,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -823,6 +977,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set # CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -856,6 +1012,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages # # Arduino libraries @@ -871,6 +1028,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -1011,6 +1169,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set # CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -1022,6 +1181,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -1030,6 +1190,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1038,6 +1199,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set # CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1048,6 +1210,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1059,12 +1222,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1077,10 +1242,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages + CONFIG_SOC_FAMILY_HT32=y CONFIG_SOC_SERIES_HT32F5=y @@ -1125,11 +1294,13 @@ CONFIG_SOC_HT32F52352=y # CONFIG_SOC_HT32F65240 is not set # CONFIG_SOC_HT32F67051 is not set # CONFIG_SOC_HT32F67741 is not set +# end of Chip Configuration # # Onboard Peripheral Drivers # # CONFIG_BSP_USING_TEST is not set +# end of Onboard Peripheral Drivers # # On-chip Peripheral Drivers @@ -1145,7 +1316,10 @@ CONFIG_BSP_USING_USART1_NAME="usart1" # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_USBD is not set +# end of On-chip Peripheral Drivers # # Board extended module Drivers # +# end of Hardware Drivers Config diff --git a/bsp/ht32/ht32f52352/README.md b/bsp/ht32/ht32f52352/README.md index 10644a76a4..2b80c781f3 100644 --- a/bsp/ht32/ht32f52352/README.md +++ b/bsp/ht32/ht32f52352/README.md @@ -41,8 +41,8 @@ ESK32-30501使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F52352 | UART | 支持 | UART0/1 | | SPI | 支持 | SPI0/1 | | I2C | 支持 | 硬件 I2C0/1 | -| ADC | 暂不支持 | | -| WDT | 暂不支持 | | +| ADC | 支持 | | +| WDT | 支持 | | ## 使用说明 diff --git a/bsp/ht32/ht32f52352/SConstruct b/bsp/ht32/ht32f52352/SConstruct index 9f16ec63d2..26ac123a47 100644 --- a/bsp/ht32/ht32f52352/SConstruct +++ b/bsp/ht32/ht32f52352/SConstruct @@ -53,6 +53,9 @@ rtconfig.BSP_LIBRARY_TYPE = ht32_library # include libraries objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) +# include usb libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbd_library', 'SConscript'))) + # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) diff --git a/bsp/ht32/ht32f52352/applications/test.c b/bsp/ht32/ht32f52352/applications/test.c index 85e86ac883..967217b656 100644 --- a/bsp/ht32/ht32f52352/applications/test.c +++ b/bsp/ht32/ht32f52352/applications/test.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -58,20 +58,29 @@ static struct rt_semaphore rx_sem; static rt_mutex_t task_mutex = RT_NULL; /* task mutex */ /* device handle */ +#ifdef BSP_USING_UART static rt_device_t serial; +#endif +#ifdef BSP_USING_WDT static rt_device_t wdt_dev; -struct rt_i2c_bus_device *i2c_dev; +#endif +#ifdef BSP_USING_I2C +static struct rt_i2c_bus_device *i2c_dev; +#endif +#ifdef BSP_USING_SPI static struct rt_spi_device *spi_dev; +#endif /* In-file function declarations */ -static void sys_run_dir(void *parameter); -static void gpio_output_test(void *parameter); -static void gpio_input_test(void *parameter); -static void key_iqr_handle(void *args); +//static void sys_run_dir(void *parameter); +//static void gpio_output_test(void *parameter); +//static void gpio_input_test(void *parameter); +//static void key_iqr_handle(void *args); /* Task registration */ int task_registration(void) { +// USB_Configuration(RT_NULL); /* Create a dynamic mutex */ task_mutex = rt_mutex_create("task_mutex", RT_IPC_FLAG_FIFO); if (task_mutex == RT_NULL) @@ -90,6 +99,7 @@ int task_registration(void) INIT_BOARD_EXPORT(task_registration); /* System operation indicator */ +#ifdef BSP_USING_GPIO static void sys_run_dir(void *parameter) { rt_uint32_t e; @@ -301,7 +311,9 @@ static int gpio_input_task(int argc, char *argv[]) return -1; } MSH_CMD_EXPORT(gpio_input_task, gpio input task operation); +#endif /* uart test */ +#ifdef BSP_USING_UART static rt_err_t uart_iqr_handle(rt_device_t dev, rt_size_t size) { /* Serial port callback function */ @@ -396,7 +408,9 @@ static int uart_task(int argc, char *argv[]) return ret; } MSH_CMD_EXPORT(uart_task, uart device sample); +#endif /* hw/sw iic test */ +#ifdef BSP_USING_I2C static void i2c_thread(void *parameter) { uint8_t write_addr = 0x00; @@ -497,7 +511,9 @@ static int i2c_task(int argc, char *argv[]) return ret; } MSH_CMD_EXPORT(i2c_task, i2c device sample); +#endif /* spi test */ +#ifdef BSP_USING_SPI static void spi_thread(void *parameter) { rt_uint8_t w25x_read_id = 0x9F; @@ -584,7 +600,9 @@ static int spi_task(int argc, char *argv[]) return ret; } MSH_CMD_EXPORT(spi_task, spi device sample); +#endif /* adc test */ +#ifdef BSP_USING_ADC static void adc_test(void *parameter) { rt_uint32_t adc0_ch6_val,adc0_ch7_val; @@ -640,8 +658,9 @@ static int adc_task(int argc, char *argv[]) return -1; } MSH_CMD_EXPORT(adc_task, adc task operation); - +#endif /* wdt test */ +#ifdef BSP_USING_WDT static void wdt_test(void) { rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL); @@ -712,5 +731,74 @@ static int wdt_task(int argc, char *argv[]) return -1; } MSH_CMD_EXPORT(wdt_task, wdt task operation); +#endif +/* usbd test */ +#ifdef BSP_USING_USBD +static void usbd_test(void *parameter) +{ + rt_device_t dev = RT_NULL; + char dev_name[] = "vcom"; + char buf[] = "usbd vcom test!\r\n"; + dev = rt_device_find(dev_name); + + if (dev) + { + rt_device_open(dev, RT_DEVICE_FLAG_RDWR); + } + else + { + rt_kprintf("Device with name %s not found.\n",dev_name); + rt_thread_t tid = rt_thread_self(); + rt_thread_delete(tid); + } + while (1) + { + rt_device_write(dev, 0, buf, rt_strlen(buf)); + rt_thread_mdelay(500); + } +} + +static int usbd_task(int argc, char *argv[]) +{ + rt_err_t ret = -RT_ERROR; + + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + /* Gpio input test tasks */ + rt_thread_t usbd_vcom_task = rt_thread_create("usbd_vcom_task", + usbd_test, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (usbd_vcom_task != RT_NULL) + { + rt_thread_startup(usbd_vcom_task); + rt_kprintf("The usbd vcom task is registered.\n"); + } + else + { + rt_kprintf("usbd vcom task registration failed.\n"); + } + ret = RT_EOK; + } + else if(rt_strcmp(argv[1],"stop") == 0) + { + ret = RT_EOK; + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s stop\n",__func__); + } + return ret; +} +MSH_CMD_EXPORT(usbd_task, usbd task operation); + + +#endif #endif /* BSP_USING_TEST */ diff --git a/bsp/ht32/ht32f52352/board/Kconfig b/bsp/ht32/ht32f52352/board/Kconfig index 57aed30985..8ba20cd72d 100644 --- a/bsp/ht32/ht32f52352/board/Kconfig +++ b/bsp/ht32/ht32f52352/board/Kconfig @@ -306,6 +306,140 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_WDT string "wdt device name" default "wdt" + + menuconfig BSP_USING_CAN + bool "Enable CAN" + depends on SOC_HT32F53241 || SOC_HT32F53242 || SOC_HT32F53252 + default n + select RT_USING_CAN if BSP_USING_CAN + config BSP_USING_CAN_NAME + depends on BSP_USING_CAN + string "can device name" + default "can" + if BSP_USING_CAN + config CAN_DEFAULT_BASE_CONFIGURATION + choice + prompt "Default CAN baud rate" + default BSP_USING_CAN500kBaud + config BSP_USING_CAN1MBaud + bool "CAN1MBaud" + config BSP_USING_CAN800kBaud + bool "CAN800kBaud" + config BSP_USING_CAN500kBaud + bool "CAN500kBaud" + config BSP_USING_CAN250kBaud + bool "CAN250kBaud" + config BSP_USING_CAN125kBaud + bool "CAN125kBaud" + config BSP_USING_CAN100kBaud + bool "CAN100kBaud" + config BSP_USING_CAN50kBaud + bool "CAN50kBaud" + config BSP_USING_CAN20kBaud + bool "CAN20kBaud" + config BSP_USING_CAN10kBaud + bool "CAN10kBaud" + endchoice + choice + prompt "Default CAN mode" + default BSP_USING_RT_CAN_MODE_NORMAL + config BSP_USING_RT_CAN_MODE_NORMAL + bool "RT_CAN_MODE_NORMAL" + config BSP_USING_RT_CAN_MODE_LISTEN + bool "RT_CAN_MODE_LISTEN" + config BSP_USING_RT_CAN_MODE_LOOPBACK + bool "RT_CAN_MODE_LOOPBACK" + config BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN + bool "RT_CAN_MODE_LOOPBACKANLISTEN" + endchoice + + config BSP_USING_CAN_BAUD + int + default 1000000 if BSP_USING_CAN1MBaud + default 800000 if BSP_USING_CAN800kBaud + default 500000 if BSP_USING_CAN500kBaud + default 250000 if BSP_USING_CAN250kBaud + default 125000 if BSP_USING_CAN125kBaud + default 100000 if BSP_USING_CAN100kBaud + default 50000 if BSP_USING_CAN50kBaud + default 20000 if BSP_USING_CAN20kBaud + default 10000 if BSP_USING_CAN10kBaud + + config BSP_USING_CAN_MODE + int + default 0 if BSP_USING_RT_CAN_MODE_NORMAL + default 1 if BSP_USING_RT_CAN_MODE_LISTEN + default 2 if BSP_USING_RT_CAN_MODE_LOOPBACK + default 3 if BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN + + config CAN_DEFAULT_FILTER_TABLE_CONFIGURATION + choice + prompt "Default filter id mode" + default BSP_USING_CAN_STD_ID + config BSP_USING_CAN_STD_ID + bool "CAN_STD_ID" + config BSP_USING_CAN_EXT_ID + bool "CAN_EXT_ID" + endchoice + + choice + prompt "Default filter frame mode" + default BSP_USING_CAN_DATA_FRAME + config BSP_USING_CAN_DATA_FRAME + bool "CAN_DATA_FRAME" + config BSP_USING_CAN_REMOTE_FRAME + bool "CAN_REMOTE_FRAME" + endchoice + + config BSP_USING_CAN_ID_MODE + int + default 0 if BSP_USING_CAN_STD_ID + default 1 if BSP_USING_CAN_EXT_ID + + config BSP_USING_CAN_FRAME_MODE + int + default 0 if BSP_USING_CAN_REMOTE_FRAME + default 1 if BSP_USING_CAN_DATA_FRAME + + config BSP_USING_CAN_MSG_NUM + int "Default filter table number" + range 0 31 + default 0 + + config BSP_USING_CAN_ID + hex "Default filter arbitration bit(ID)" + range 0 0x7FF if BSP_USING_CAN_STD_ID + default 0x541 if BSP_USING_CAN_STD_ID + range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + default 0x541 if BSP_USING_CAN_EXT_ID + + config BSP_USING_CAN_MASK + hex "Default filter mask bit(MASK)" + range 0 0x7FF if BSP_USING_CAN_STD_ID + default 0x7FF if BSP_USING_CAN_STD_ID + range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + default 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + depends on SOC_HT32F12345 || SOC_HT32F12365 || SOC_HT32F12366 + default n + select RT_USING_SDIO if BSP_USING_SDIO + config BSP_USING_SDIO_NAME + depends on BSP_USING_SDIO + string "sdio device name" + default "sdio" + + menuconfig BSP_USING_USBD + bool "Enable USB BUS" + default n + select RT_USING_USB_DEVICE if BSP_USING_USBD + config BSP_USING_USBD_NAME + depends on BSP_USING_USBD + string "usbd device name" + default "usbd" endmenu menu "Board extended module Drivers" diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h index a512579519..d1ef029d1b 100644 --- a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h @@ -58,7 +58,7 @@ // Endpoint5 Interrupt Enable (EP5IE) // Endpoint6 Interrupt Enable (EP6IE) // Endpoint7 Interrupt Enable (EP7IE) -#define _UIER (0x011D) +#define _UIER (0xFF1D) // @@ -96,7 +96,7 @@ /* Endpoint1 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint1 Configuration -#define _EP1_ENABLE (0) +#define _EP1_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -114,7 +114,7 @@ // Endpoint Transfer Type // <2=> Bulk // <3=> Interrupt -#define _EP1_TYPR (3) +#define _EP1_TYPR (2) // Endpoint Direction (EPDIR) // <1=> IN @@ -123,7 +123,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> /* Maximum: 64 Bytes */ -#define _EP1LEN_TMP (8) +#define _EP1LEN_TMP (64) // Endpoint Interrupt Enable Settings (EPIER) // Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> @@ -135,7 +135,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP1_IER (0x10) +#define _EP1_IER (0x12) // // @@ -144,7 +144,7 @@ /* Endpoint2 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint2 Configuration -#define _EP2_ENABLE (0) +#define _EP2_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -162,7 +162,7 @@ // Endpoint Transfer Type // <2=> Bulk // <3=> Interrupt -#define _EP2_TYPR (3) +#define _EP2_TYPR (2) // Endpoint Direction (EPDIR) // <1=> IN @@ -171,7 +171,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> /* Maximum: 64 Bytes */ -#define _EP2LEN_TMP (8) +#define _EP2LEN_TMP (64) // Endpoint Interrupt Enable Settings (EPIER) // Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> @@ -183,7 +183,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP2_IER (0x002) +#define _EP2_IER (0x012) // // @@ -191,7 +191,7 @@ /* Endpoint3 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint3 Configuration -#define _EP3_ENABLE (0) +#define _EP3_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -218,7 +218,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> /* Maximum: 64 Bytes */ -#define _EP3LEN_TMP (8) +#define _EP3LEN_TMP (64) // Endpoint Interrupt Enable Settings (EPIER) // Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> @@ -230,7 +230,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP3_IER (0x10) +#define _EP3_IER (0x12) // // @@ -238,7 +238,7 @@ /* Endpoint4 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint4 Configuration -#define _EP4_ENABLE (0) +#define _EP4_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -266,7 +266,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP4LEN_TMP (8) +#define _EP4LEN_TMP (64) // Single/Double Buffer Selection (SDBS) // <0=> Single Buffer @@ -283,7 +283,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP4_IER (0x02) +#define _EP4_IER (0x12) // // @@ -292,7 +292,7 @@ /* Endpoint5 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint5 Configuration -#define _EP5_ENABLE (0) +#define _EP5_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -311,7 +311,7 @@ // <1=> Isochronous // <2=> Bulk // <3=> Interrupt -#define _EP5_TYPR (3) +#define _EP5_TYPR (1) // Endpoint Direction (EPDIR) // <1=> IN @@ -320,7 +320,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP5LEN_TMP (8) +#define _EP5LEN_TMP (64) // Single/Double Buffer Selection (SDBS) @@ -338,7 +338,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP5_IER (0x10) +#define _EP5_IER (0x12) // // @@ -347,7 +347,7 @@ /* Endpoint6 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint6 Configuration -#define _EP6_ENABLE (0) +#define _EP6_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -366,7 +366,7 @@ // <1=> Isochronous // <2=> Bulk // <3=> Interrupt -#define _EP6_TYPR (3) +#define _EP6_TYPR (1) // Endpoint Direction (EPDIR) // <1=> IN @@ -375,7 +375,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP6LEN_TMP (8) +#define _EP6LEN_TMP (64) // Single/Double Buffer Selection (SDBS) // <0=> Single Buffer @@ -392,7 +392,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP6_IER (0x02) +#define _EP6_IER (0x12) // // @@ -401,7 +401,7 @@ /* Endpoint7 Configuration Setting */ /*----------------------------------------------------------------------------------------------------------*/ // Endpoint7 Configuration -#define _EP7_ENABLE (0) +#define _EP7_ENABLE (1) // Endpoint Address (EPADR) // <1=> 1 @@ -429,7 +429,7 @@ // Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> /* Maximum: 1000 Bytes */ -#define _EP7LEN_TMP (8) +#define _EP7LEN_TMP (64) // Single/Double Buffer Selection (SDBS) // <0=> Single Buffer @@ -446,7 +446,7 @@ // NAK Transmitted Interrupt Enable (NAKIE) // STALL Transmitted Interrupt Enable (STLIE) // USB Error Interrupt Enable (UERIE) -#define _EP7_IER (0x10) +#define _EP7_IER (0x12) // // diff --git a/bsp/ht32/ht32f52352/project.uvoptx b/bsp/ht32/ht32f52352/project.uvoptx index f767ec2636..50637f5197 100644 --- a/bsp/ht32/ht32f52352/project.uvoptx +++ b/bsp/ht32/ht32f52352/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -170,7 +170,7 @@ Applications - 1 + 0 0 0 0 @@ -317,8 +317,8 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - i2c-bit-ops.c + ..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c 0 0 @@ -329,8 +329,8 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c_core.c - i2c_core.c + ..\..\..\components\drivers\ipc\completion_up.c + completion_up.c 0 0 @@ -341,30 +341,6 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c - 0 - 0 - - - 3 - 14 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\ipc\completion.c - completion.c - 0 - 0 - - - 3 - 15 - 1 - 0 - 0 - 0 ..\..\..\components\drivers\ipc\condvar.c condvar.c 0 @@ -372,7 +348,7 @@ 3 - 16 + 14 1 0 0 @@ -384,7 +360,7 @@ 3 - 17 + 15 1 0 0 @@ -396,7 +372,7 @@ 3 - 18 + 16 1 0 0 @@ -408,7 +384,7 @@ 3 - 19 + 17 1 0 0 @@ -420,7 +396,7 @@ 3 - 20 + 18 1 0 0 @@ -432,7 +408,7 @@ 3 - 21 + 19 1 0 0 @@ -444,73 +420,25 @@ 3 - 22 + 20 1 0 0 0 - ..\..\..\components\drivers\misc\adc.c - adc.c + ..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c 0 0 3 - 23 + 21 1 0 0 0 - ..\..\..\components\drivers\pin\pin.c - pin.c - 0 - 0 - - - 3 - 24 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 3 - 25 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_core.c - spi_core.c - 0 - 0 - - - 3 - 26 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_dev.c - spi_dev.c - 0 - 0 - - - 3 - 27 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\watchdog\watchdog.c - watchdog.c + ..\..\..\components\drivers\serial\dev_serial.c + dev_serial.c 0 0 @@ -518,13 +446,13 @@ Drivers - 1 + 0 0 0 0 4 - 28 + 22 1 0 0 @@ -536,7 +464,7 @@ 4 - 29 + 23 1 0 0 @@ -548,7 +476,7 @@ 4 - 30 + 24 2 0 0 @@ -560,7 +488,7 @@ 4 - 31 + 25 1 0 0 @@ -572,7 +500,7 @@ 4 - 32 + 26 1 0 0 @@ -584,7 +512,7 @@ 4 - 33 + 27 1 0 0 @@ -604,19 +532,7 @@ 0 5 - 34 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 5 - 35 + 28 1 0 0 @@ -628,7 +544,19 @@ 5 - 36 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 30 1 0 0 @@ -640,13 +568,13 @@ 5 - 37 + 31 1 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\components\finsh\shell.c + shell.c 0 0 @@ -660,7 +588,7 @@ 0 6 - 38 + 32 1 0 0 @@ -672,7 +600,7 @@ 6 - 39 + 33 1 0 0 @@ -684,7 +612,31 @@ 6 - 40 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\defunct.c + defunct.c + 0 + 0 + + + 6 + 36 1 0 0 @@ -696,7 +648,7 @@ 6 - 41 + 37 1 0 0 @@ -708,7 +660,7 @@ 6 - 42 + 38 1 0 0 @@ -720,31 +672,7 @@ 6 - 43 - 1 - 0 - 0 - 0 - ..\..\..\src\klibc\kstdio.c - kstdio.c - 0 - 0 - - - 6 - 44 - 1 - 0 - 0 - 0 - ..\..\..\src\klibc\kstring.c - kstring.c - 0 - 0 - - - 6 - 45 + 39 1 0 0 @@ -756,7 +684,7 @@ 6 - 46 + 40 1 0 0 @@ -768,7 +696,7 @@ 6 - 47 + 41 1 0 0 @@ -780,7 +708,7 @@ 6 - 48 + 42 1 0 0 @@ -792,7 +720,7 @@ 6 - 49 + 43 1 0 0 @@ -804,7 +732,7 @@ 6 - 50 + 44 1 0 0 @@ -816,7 +744,7 @@ 6 - 51 + 45 1 0 0 @@ -828,7 +756,7 @@ 6 - 52 + 46 1 0 0 @@ -840,7 +768,7 @@ 6 - 53 + 47 1 0 0 @@ -853,14 +781,82 @@ - libcpu + klibc 0 0 0 0 7 - 54 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + libcpu + 0 + 0 + 0 + 0 + + 8 + 53 1 0 0 @@ -871,8 +867,8 @@ 0 - 7 - 55 + 8 + 54 1 0 0 @@ -883,8 +879,8 @@ 0 - 7 - 56 + 8 + 55 2 0 0 @@ -895,8 +891,8 @@ 0 - 7 - 57 + 8 + 56 1 0 0 @@ -915,200 +911,8 @@ 0 0 - 8 - 58 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_sci.c - ht32f5xxxx_sci.c - 0 - 0 - - - 8 - 59 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c - ht32f5xxxx_rstcu.c - 0 - 0 - - - 8 - 60 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c - ht32f5xxxx_adc.c - 0 - 0 - - - 8 - 61 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c - ht32f5xxxx_cmp.c - 0 - 0 - - - 8 - 62 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32_cm0plus_misc.c - ht32_cm0plus_misc.c - 0 - 0 - - - 8 - 63 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_crc.c - ht32f5xxxx_crc.c - 0 - 0 - - - 8 - 64 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_spi.c - ht32f5xxxx_spi.c - 0 - 0 - - - 8 - 65 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c - ht32f5xxxx_pwrcu.c - 0 - 0 - - - 8 - 66 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c - ht32f5xxxx_pdma.c - 0 - 0 - - - 8 - 67 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c - ht32f5xxxx_mctm.c - 0 - 0 - - - 8 - 68 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c - ht32f5xxxx_rtc.c - 0 - 0 - - - 8 - 69 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2s.c - ht32f5xxxx_i2s.c - 0 - 0 - - - 8 - 70 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usbd.c - ht32f5xxxx_usbd.c - 0 - 0 - - - 8 - 71 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_wdt.c - ht32f5xxxx_wdt.c - 0 - 0 - - - 8 - 72 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ebi.c - ht32f5xxxx_ebi.c - 0 - 0 - - - 8 - 73 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_tm.c - ht32f5xxxx_tm.c - 0 - 0 - - - 8 - 74 + 9 + 57 1 0 0 @@ -1119,7 +923,211 @@ 0 - 8 + 9 + 58 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c + ht32f5xxxx_pwrcu.c + 0 + 0 + + + 9 + 59 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_wdt.c + ht32f5xxxx_wdt.c + 0 + 0 + + + 9 + 60 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c + ht32f5xxxx_mctm.c + 0 + 0 + + + 9 + 61 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usart.c + ht32f5xxxx_usart.c + 0 + 0 + + + 9 + 62 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ebi.c + ht32f5xxxx_ebi.c + 0 + 0 + + + 9 + 63 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c + ht32f5xxxx_exti.c + 0 + 0 + + + 9 + 64 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_crc.c + ht32f5xxxx_crc.c + 0 + 0 + + + 9 + 65 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_spi.c + ht32f5xxxx_spi.c + 0 + 0 + + + 9 + 66 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_sci.c + ht32f5xxxx_sci.c + 0 + 0 + + + 9 + 67 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2c.c + ht32f5xxxx_i2c.c + 0 + 0 + + + 9 + 68 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_tm.c + ht32f5xxxx_tm.c + 0 + 0 + + + 9 + 69 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c + ht32f5xxxx_pdma.c + 0 + 0 + + + 9 + 70 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c + ht32f5xxxx_adc.c + 0 + 0 + + + 9 + 71 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usbd.c + ht32f5xxxx_usbd.c + 0 + 0 + + + 9 + 72 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\system_ht32f5xxxx_01.c + system_ht32f5xxxx_01.c + 0 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c + ht32f5xxxx_rstcu.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_flash.c + ht32f5xxxx_flash.c + 0 + 0 + + + 9 75 1 0 @@ -1131,19 +1139,19 @@ 0 - 8 + 9 76 1 0 0 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c - ht32f5xxxx_exti.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32_cm0plus_misc.c + ht32_cm0plus_misc.c 0 0 - 8 + 9 77 1 0 @@ -1155,50 +1163,38 @@ 0 - 8 + 9 78 1 0 0 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usart.c - ht32f5xxxx_usart.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2s.c + ht32f5xxxx_i2s.c 0 0 - 8 + 9 79 1 0 0 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2c.c - ht32f5xxxx_i2c.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c + ht32f5xxxx_rtc.c 0 0 - 8 + 9 80 1 0 0 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_flash.c - ht32f5xxxx_flash.c - 0 - 0 - - - 8 - 81 - 1 - 0 - 0 - 0 - ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\system_ht32f5xxxx_01.c - system_ht32f5xxxx_01.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c + ht32f5xxxx_cmp.c 0 0 diff --git a/bsp/ht32/ht32f52352/project.uvprojx b/bsp/ht32/ht32f52352/project.uvprojx index 602e06a775..8f9e53c870 100644 --- a/bsp/ht32/ht32f52352/project.uvprojx +++ b/bsp/ht32/ht32f52352/project.uvprojx @@ -15,8 +15,8 @@ HT32F52352 Holtek - Holtek.HT32_DFP.1.0.19 - http://mcu.holtek.com.tw/pack + Holtek.HT32_DFP.1.0.55 + https://mcu.holtek.com.tw/pack IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE @@ -332,10 +332,10 @@ 0 0 - - __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, __RTTHREAD__, USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352 + --gnu + RT_USING_LIBC, RT_USING_ARMLIBC, __RTTHREAD__, USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, USE_HT32_DRIVER - ..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\include;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\libraries\ht32_drivers;..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Include;..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\inc;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\HT32_STD_5xxxx_FWLib\library\CMSIS\Include;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;board\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;.;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;applications;..\..\..\components\drivers\spi;..\..\..\libcpu\arm\cortex-m0 + ..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\inc;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\libc\posix\ipc;..\libraries\ht32_drivers;..\..\..\components\libc\posix\io\poll;..\libraries\usbd_library\inc;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;.;..\..\..\components\drivers\phy;board\inc;..\..\..\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\finsh;applications;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\HT32_STD_5xxxx_FWLib\library\CMSIS\Include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\eventfd;..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Include @@ -490,9 +490,9 @@ - i2c-bit-ops.c + completion_comm.c 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c + ..\..\..\components\drivers\ipc\completion_comm.c 2 @@ -545,119 +545,9 @@ - i2c_core.c + completion_up.c 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - completion.c - 1 - ..\..\..\components\drivers\ipc\completion.c + ..\..\..\components\drivers\ipc\completion_up.c 2 @@ -1095,9 +985,9 @@ - adc.c + dev_pin.c 1 - ..\..\..\components\drivers\misc\adc.c + ..\..\..\components\drivers\pin\dev_pin.c 2 @@ -1150,229 +1040,9 @@ - pin.c + dev_serial.c 1 - ..\..\..\components\drivers\pin\pin.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_IPC_SOURCE__ - - - - - - - - - watchdog.c - 1 - ..\..\..\components\drivers\watchdog\watchdog.c + ..\..\..\components\drivers\serial\dev_serial.c 2 @@ -1464,25 +1134,25 @@ Finsh - - shell.c - 1 - ..\..\..\components\finsh\shell.c - msh.c 1 ..\..\..\components\finsh\msh.c + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - cmd.c + shell.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\shell.c @@ -1599,6 +1269,116 @@ + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + idle.c 1 @@ -1764,116 +1544,6 @@ - - kstdio.c - 1 - ..\..\..\src\klibc\kstdio.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_KERNEL_SOURCE__ - - - - - - - - - kstring.c - 1 - ..\..\..\src\klibc\kstring.c - - - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - __RT_KERNEL_SOURCE__ - - - - - - - kservice.c 1 @@ -2371,6 +2041,36 @@ + + klibc + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + libcpu @@ -2400,29 +2100,39 @@ Libraries - ht32f5xxxx_sci.c + ht32f5xxxx_ckcu.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_sci.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ckcu.c - ht32f5xxxx_rstcu.c + ht32f5xxxx_pwrcu.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c - ht32f5xxxx_adc.c + ht32f5xxxx_wdt.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_wdt.c - ht32f5xxxx_cmp.c + ht32f5xxxx_mctm.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c - ht32_cm0plus_misc.c + ht32f5xxxx_usart.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32_cm0plus_misc.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usart.c + + + ht32f5xxxx_ebi.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ebi.c + + + ht32f5xxxx_exti.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c ht32f5xxxx_crc.c @@ -2435,74 +2145,9 @@ ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_spi.c - ht32f5xxxx_pwrcu.c + ht32f5xxxx_sci.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c - - - ht32f5xxxx_pdma.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c - - - ht32f5xxxx_mctm.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c - - - ht32f5xxxx_rtc.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c - - - ht32f5xxxx_i2s.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2s.c - - - ht32f5xxxx_usbd.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usbd.c - - - ht32f5xxxx_wdt.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_wdt.c - - - ht32f5xxxx_ebi.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ebi.c - - - ht32f5xxxx_tm.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_tm.c - - - ht32f5xxxx_ckcu.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ckcu.c - - - ht32f5xxxx_gpio.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_gpio.c - - - ht32f5xxxx_exti.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c - - - ht32f5xxxx_bftm.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_bftm.c - - - ht32f5xxxx_usart.c - 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usart.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_sci.c ht32f5xxxx_i2c.c @@ -2510,15 +2155,70 @@ ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2c.c - ht32f5xxxx_flash.c + ht32f5xxxx_tm.c 1 - ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_flash.c + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_tm.c + + + ht32f5xxxx_pdma.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c + + + ht32f5xxxx_adc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c + + + ht32f5xxxx_usbd.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usbd.c system_ht32f5xxxx_01.c 1 ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\system_ht32f5xxxx_01.c + + ht32f5xxxx_rstcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c + + + ht32f5xxxx_flash.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_flash.c + + + ht32f5xxxx_gpio.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_gpio.c + + + ht32_cm0plus_misc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32_cm0plus_misc.c + + + ht32f5xxxx_bftm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_bftm.c + + + ht32f5xxxx_i2s.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2s.c + + + ht32f5xxxx_rtc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c + + + ht32f5xxxx_cmp.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c + diff --git a/bsp/ht32/ht32f52352/rtconfig.h b/bsp/ht32/ht32f52352/rtconfig.h index a2410d0967..b7406d9fc7 100644 --- a/bsp/ht32/ht32f52352/rtconfig.h +++ b/bsp/ht32/ht32f52352/rtconfig.h @@ -1,26 +1,81 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - /* RT-Thread Kernel */ +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ #define RT_NAME_MAX 8 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 -/* kservice optimization */ +/* kservice options */ +/* end of kservice options */ /* Inter-Thread communication */ @@ -29,6 +84,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ @@ -38,12 +94,14 @@ #define RT_MEMHEAP_FAST_MODE #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" #define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M0 @@ -52,7 +110,7 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_STACK_SIZE 1024 #define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH @@ -71,6 +129,7 @@ /* DFS: device virtual file system */ +/* end of DFS: device virtual file system */ /* Device Drivers */ @@ -79,15 +138,8 @@ #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS -#define RT_USING_ADC -#define RT_USING_SPI -#define RT_USING_WDT #define RT_USING_PIN - -/* Using USB */ - +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -99,6 +151,8 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ @@ -108,18 +162,30 @@ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -130,57 +196,78 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ @@ -188,69 +275,94 @@ /* STM32 HAL & SDK Drivers */ +/* end of STM32 HAL & SDK Drivers */ /* Infineon HAL Packages */ +/* end of Infineon HAL Packages */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ /* sensors drivers */ +/* end of sensors drivers */ /* touch drivers */ +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ #define SOC_FAMILY_HT32 #define SOC_SERIES_HT32F5 @@ -261,9 +373,11 @@ #define SOC_KERNEL #define CORTEX_M0 #define SOC_HT32F52352 +/* end of Chip Configuration */ /* Onboard Peripheral Drivers */ +/* end of Onboard Peripheral Drivers */ /* On-chip Peripheral Drivers */ @@ -271,8 +385,10 @@ #define BSP_USING_UART #define BSP_USING_USART1 #define BSP_USING_USART1_NAME "usart1" +/* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ +/* end of Hardware Drivers Config */ #endif diff --git a/bsp/ht32/ht32f52352/template.uvprojx b/bsp/ht32/ht32f52352/template.uvprojx index 2530ad2a7e..039f087c17 100644 --- a/bsp/ht32/ht32f52352/template.uvprojx +++ b/bsp/ht32/ht32f52352/template.uvprojx @@ -15,8 +15,8 @@ HT32F52352 Holtek - Holtek.HT32_DFP.1.0.19 - http://mcu.holtek.com.tw/pack + Holtek.HT32_DFP.1.0.55 + https://mcu.holtek.com.tw/pack IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE @@ -332,7 +332,7 @@ 0 0 - + --gnu diff --git a/bsp/ht32/ht32f53252/.ci/attachconfig/ci.attachconfig.yml b/bsp/ht32/ht32f53252/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 0000000000..817cf4e3d0 --- /dev/null +++ b/bsp/ht32/ht32f53252/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,18 @@ +devices.strict: + depend_scons_arg: + - '--strict' +devices.gpio: + depends: + - devices.strict + kconfig: + - CONFIG_BSP_USING_GPIO=y +devices.uart: + kconfig: + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_USART1=y +# ------ SEGGER CI ------ +segger: + kconfig: + - CONFIG_BSP_USING_GPIO=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_USART1=y \ No newline at end of file diff --git a/bsp/ht32/ht32f53252/.config b/bsp/ht32/ht32f53252/.config new file mode 100644 index 0000000000..7dc7e334d3 --- /dev/null +++ b/bsp/ht32/ht32f53252/.config @@ -0,0 +1,1326 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +# CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=32 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HT32=y +CONFIG_SOC_SERIES_HT32F5=y + +# +# Hardware Drivers Config +# + +# +# Chip Configuration +# +CONFIG_SOC_KERNEL=y +CONFIG_CORTEX_M0=y +# CONFIG_CORTEX_M3 is not set +# CONFIG_SOC_HT32F0006 is not set +# CONFIG_SOC_HT32F0008 is not set +# CONFIG_SOC_HT32F50241 is not set +# CONFIG_SOC_HT32F50343 is not set +# CONFIG_SOC_HT32F50441 is not set +# CONFIG_SOC_HT32F50452 is not set +# CONFIG_SOC_HT32F52241 is not set +# CONFIG_SOC_HT32F52244 is not set +# CONFIG_SOC_HT32F52253 is not set +# CONFIG_SOC_HT32F52341 is not set +# CONFIG_SOC_HT32F52352 is not set +# CONFIG_SOC_HT32F52354 is not set +# CONFIG_SOC_HT32F52367 is not set +# CONFIG_SOC_HT32F53241 is not set +CONFIG_SOC_HT32F53252=y +# CONFIG_SOC_HT32F54241 is not set +# CONFIG_SOC_HT32F54253 is not set +# CONFIG_SOC_HT32F57341 is not set +# CONFIG_SOC_HT32F57352 is not set +# CONFIG_SOC_HT32F5828 is not set +# CONFIG_SOC_HT32F59041 is not set +# CONFIG_SOC_HT32F59741 is not set +# CONFIG_SOC_HT32F61141 is not set +# CONFIG_SOC_HT32F61245 is not set +# CONFIG_SOC_HT32F61355 is not set +# CONFIG_SOC_HT32F61356 is not set +# CONFIG_SOC_HT32F61357 is not set +# CONFIG_SOC_HT32F61641 is not set +# CONFIG_SOC_HT32F65240 is not set +# CONFIG_SOC_HT32F67051 is not set +# CONFIG_SOC_HT32F67741 is not set +# end of Chip Configuration + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_TEST is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_USART0 is not set +CONFIG_BSP_USING_USART1=y +CONFIG_BSP_USING_USART1_NAME="usart1" +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_USBD is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/ht32/ht32f53252/Kconfig b/bsp/ht32/ht32f53252/Kconfig new file mode 100644 index 0000000000..73238d3a13 --- /dev/null +++ b/bsp/ht32/ht32f53252/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/ht32/ht32f53252/README.md b/bsp/ht32/ht32f53252/README.md new file mode 100644 index 0000000000..e35b8f00b3 --- /dev/null +++ b/bsp/ht32/ht32f53252/README.md @@ -0,0 +1,108 @@ +# HT32F53252 BSP 说明 + +## 简介 + +ESK32-30522是合泰基于HT32F53252芯片并针对Cortex®-M0+入门而设计的评估板。本文档是为ESK32-30522开发板提供的BSP(板级支持包)说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +ESK32-30522使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F53252，针对Cortex®-M0+入门而设计。开发板外观如下图所示： + +![board.png](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：HT32F53252，主频 60MHz，128KB FLASH ，16KB SRAM +- 常用外设 + - LED：2个，（绿色，PC14、PC15） +- 常用接口：USB 转串口 、USB SLAVE +- 调试接口：板载的 e-Link32 Lite SWD 下载 + +开发板更多详细信息请参考合泰官网的相关文档[ESK32-30522](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30522)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :--- | :---: | :--- | +| USB 转串口 | 支持 | 使用 USART1 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1...PD3 ---> PIN: 0, 1...51 | +| USART | 支持 | USART0/1 | +| UART | 支持 | UART0/1 | +| SPI | 支持 | SPI0/1 | +| I2C | 支持 | 硬件 I2C0/1 | +| ADC | 暂不支持 | | +| WDT | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。 + +连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:39:43 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 USART1 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。 + +## 联系人信息 + +维护人: + +- [QT-one](https://github.com/QT-one) \ No newline at end of file diff --git a/bsp/ht32/ht32f53252/SConscript b/bsp/ht32/ht32f53252/SConscript new file mode 100644 index 0000000000..682f94215c --- /dev/null +++ b/bsp/ht32/ht32f53252/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os #包含os库 +Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包） +from building import * #把building模块的所有内容都导入到当前模块中 + +cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中 +objs = [] #创建一个list型变量objs +list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中 + +for d in list: #for循环用d记录循环的次数，直到寻遍所有路径 + path = os.path.join(cwd, d) #根据d获取到不同的路径 + if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件 + objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中 + +Return('objs') #将objs返回出去 diff --git a/bsp/ht32/ht32f53252/SConstruct b/bsp/ht32/ht32f53252/SConstruct new file mode 100644 index 0000000000..26ac123a47 --- /dev/null +++ b/bsp/ht32/ht32f53252/SConstruct @@ -0,0 +1,63 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +ht32_library = 'HT32_STD_5xxxx_FWLib' +rtconfig.BSP_LIBRARY_TYPE = ht32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) + +# include usb libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbd_library', 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ht32/ht32f53252/applications/SConscript b/bsp/ht32/ht32f53252/applications/SConscript new file mode 100644 index 0000000000..395a120290 --- /dev/null +++ b/bsp/ht32/ht32f53252/applications/SConscript @@ -0,0 +1,26 @@ +#导入其他模块的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +#src = Glob('*.c') +src = Split(""" +main.c +""") +if GetDepend(['BSP_USING_TEST']): + src += ['test.c'] + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f53252/applications/main.c b/bsp/ht32/ht32f53252/applications/main.c new file mode 100644 index 0000000000..8e5d2d47c6 --- /dev/null +++ b/bsp/ht32/ht32f53252/applications/main.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include +#include "board.h" + +/* defined the led1 pin: pc14 */ +#define LED1_PIN GET_PIN(C, 14) +/* defined the led2 pin: pc15 */ +#define LED2_PIN GET_PIN(C, 15) + +int main(void) +{ + rt_uint32_t speed = 200; + /* set led1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set led2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_LOW); + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(speed); + } +} diff --git a/bsp/ht32/ht32f53252/applications/test.c b/bsp/ht32/ht32f53252/applications/test.c new file mode 100644 index 0000000000..894f7a1898 --- /dev/null +++ b/bsp/ht32/ht32f53252/applications/test.c @@ -0,0 +1,941 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-06-17 QT-one first version + */ + +#include "board.h" + +#ifdef BSP_USING_TEST + +/* Task stack */ +#define THREAD_PRIORITY 25 +#define THREAD_STACK_SIZE 512 +#define THREAD_TIMESLICE 5 + +/* Test pins */ +#define TEST_LED0_PIN GET_PIN(C, 14) +#define TEST_LED1_PIN GET_PIN(C, 15) +#define TEST_LED2_PIN GET_PIN(C, 1) + +#define TEST_WAKEUP_PIN GET_PIN(B, 12) +#define TEST_KEY1_PIN GET_PIN(D, 1) +#define TEST_KEY2_PIN GET_PIN(D, 2) + +#define TEST_OTHER_PIN GET_PIN(B, 12) +#define TEST_OUTPUT_PIN GET_PIN(C, 1) + +#define TEST_INPUT_PIN GET_PIN(D, 1) +#define TEST_INT_PIN GET_PIN(D, 2) +#define TEST_RES_PIN GET_PIN(C, 1) + + +/* Event flags */ +#define TEST_GPIO_INT_ENV (1 << 10) +#define TEST_GPIO_KEY_ENV (1 << 15) +static struct rt_event led_event; /* LED event */ +#define TASK_KILL_FLAG (1 << 10) +static struct rt_event task_event; /* Task event */ + +/* EEPROM Read/Write Data Structure */ +typedef union +{ + rt_uint8_t data[30]; + struct + { + rt_uint8_t write_addr; + char write_date[29]; + }in_data; +}eeprom_write_type; +/* Semaphore variables */ +static struct rt_semaphore rx_sem; + +/* Mutually exclusive variables */ +static rt_mutex_t task_mutex = RT_NULL; /* task mutex */ + +/* device handle */ +#ifdef BSP_USING_UART +static rt_device_t serial; +#endif +#ifdef BSP_USING_WDT +static rt_device_t wdt_dev; +#endif +#ifdef BSP_USING_I2C +static struct rt_i2c_bus_device *i2c_dev; +#endif +#ifdef BSP_USING_SPI +static struct rt_spi_device *spi_dev; +#endif + +/* In-file function declarations */ +//static void sys_run_dir(void *parameter); +//static void gpio_output_test(void *parameter); +//static void gpio_input_test(void *parameter); +//static void key_iqr_handle(void *args); + +/* Task registration */ +int task_registration(void) +{ +// USB_Configuration(RT_NULL); + /* Create a dynamic mutex */ + task_mutex = rt_mutex_create("task_mutex", RT_IPC_FLAG_FIFO); + if (task_mutex == RT_NULL) + { + rt_kprintf("rt_mutex_create error.\n"); + return -1; + } + /* Create a task event */ + if(rt_event_init(&task_event,"task_event",RT_IPC_FLAG_FIFO) != RT_EOK) + { + rt_kprintf("rt_mutex_create error.\n"); + return -1; + } + return 0; +} +INIT_BOARD_EXPORT(task_registration); + +/* System operation indicator */ +#ifdef BSP_USING_GPIO +static void sys_run_dir(void *parameter) +{ + rt_uint32_t e; + rt_pin_mode(TEST_LED2_PIN, PIN_MODE_OUTPUT); + while(1) + { + if(rt_event_recv(&task_event,TASK_KILL_FLAG, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_NO, &e) == RT_EOK) + { + rt_thread_t tid = rt_thread_self(); + rt_thread_delete(tid); + } + rt_pin_write(TEST_LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + rt_pin_write(TEST_LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + } +} + +static int sys_run_task(int argc, char *argv[]) +{ + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + if(rt_mutex_take(task_mutex, RT_WAITING_NO) != RT_EOK) + { + rt_kprintf("The test thread is occupied.\n"); + return -RT_ERROR; + } + else + { + /* Register the system indicator task */ + rt_thread_t sys_led_task = rt_thread_create("sys_led_task", + sys_run_dir, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (sys_led_task != RT_NULL) + rt_thread_startup(sys_led_task); + rt_kprintf("The sys run task is registered.\n"); + } + } + else if(rt_strcmp(argv[1],"end") == 0) + { + rt_event_send(&task_event,TASK_KILL_FLAG); + rt_mutex_release(task_mutex); + rt_kprintf("The sys run task has been deleted.\n"); + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + return -1; +} +MSH_CMD_EXPORT(sys_run_task, sys run task operation); + +/* Gpio output test */ +static void gpio_output_test(void *parameter) +{ + rt_uint32_t e; + rt_pin_mode(TEST_OUTPUT_PIN, PIN_MODE_OUTPUT); + while(1) + { + if(rt_event_recv(&task_event,TASK_KILL_FLAG, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_NO, &e) == RT_EOK) + { + rt_thread_t tid = rt_thread_self(); + rt_thread_delete(tid); + } + rt_pin_write(TEST_OUTPUT_PIN, PIN_LOW); + rt_thread_mdelay(500); + rt_pin_write(TEST_OUTPUT_PIN, PIN_HIGH); + rt_thread_mdelay(500); + } +} + +static int gpio_output_task(int argc, char *argv[]) +{ + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + if(rt_mutex_take(task_mutex, RT_WAITING_NO) != RT_EOK) + { + rt_kprintf("The test thread is occupied.\n"); + return -RT_ERROR; + } + else + { + /* Gpio output test tasks */ + rt_thread_t gpio_output_task = rt_thread_create("gpio_output_task", + gpio_output_test, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (gpio_output_task != RT_NULL) + rt_thread_startup(gpio_output_task); + rt_kprintf("The gpio output task is registered.\n"); + } + } + else if(rt_strcmp(argv[1],"end") == 0) + { + rt_event_send(&task_event,TASK_KILL_FLAG); + rt_mutex_release(task_mutex); + rt_kprintf("The gpio output task has been deleted.\n"); + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + return -1; +} +MSH_CMD_EXPORT(gpio_output_task, gpio output task operation); +/* Gpio input test */ +static void key_iqr_handle(void *args) +{ + /* gpio iqr fun */ + rt_event_send(&led_event,TEST_GPIO_INT_ENV); +} + +static void gpio_input_test(void *parameter) +{ + uint8_t led_flag = PIN_LOW; + rt_uint32_t e; + + rt_pin_mode(TEST_RES_PIN, PIN_MODE_OUTPUT); + rt_pin_write(TEST_RES_PIN, PIN_LOW); + + rt_pin_mode(TEST_WAKEUP_PIN,PIN_MODE_INPUT_PULLDOWN); + rt_pin_mode(TEST_INPUT_PIN,PIN_MODE_INPUT_PULLUP); + + rt_pin_attach_irq(TEST_INT_PIN,PIN_IRQ_MODE_FALLING,key_iqr_handle,RT_NULL); + rt_pin_irq_enable(TEST_INT_PIN,PIN_IRQ_ENABLE); + + if(rt_event_init(&led_event,"led_event",RT_IPC_FLAG_FIFO) != RT_EOK) + { + rt_kprintf("rt_mutex_create error.\n"); + } + while(1) + { + if(PIN_LOW == rt_pin_read(TEST_INPUT_PIN)) + { + while(PIN_LOW == rt_pin_read(TEST_INPUT_PIN)); + rt_event_send(&led_event,TEST_GPIO_KEY_ENV); + } + if(rt_event_recv(&led_event,(TEST_GPIO_INT_ENV|TEST_GPIO_KEY_ENV), + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_NO, &e) == RT_EOK) + { + led_flag = (led_flag == PIN_LOW)?PIN_HIGH:PIN_LOW; + rt_pin_write(TEST_RES_PIN, led_flag); + } + if(rt_event_recv(&task_event,TASK_KILL_FLAG, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_NO, &e) == RT_EOK) + { + rt_thread_t tid = rt_thread_self(); + rt_thread_delete(tid); + } + } +} + +static int gpio_input_task(int argc, char *argv[]) +{ + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + if(rt_mutex_take(task_mutex, RT_WAITING_NO) != RT_EOK) + { + rt_kprintf("The test thread is occupied.\n"); + return -RT_ERROR; + } + /* Gpio input test tasks */ + rt_thread_t gpio_input_task = rt_thread_create("gpio_input_task", + gpio_input_test, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (gpio_input_task != RT_NULL) + rt_thread_startup(gpio_input_task); + rt_kprintf("The gpio input task is registered.\n"); + } + else if(rt_strcmp(argv[1],"end") == 0) + { + rt_event_send(&task_event,TASK_KILL_FLAG); + rt_mutex_release(task_mutex); + rt_kprintf("The gpio input task has been deleted.\n"); + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + return -1; +} +MSH_CMD_EXPORT(gpio_input_task, gpio input task operation); +#endif +/* uart test */ +#ifdef BSP_USING_UART +static rt_err_t uart_iqr_handle(rt_device_t dev, rt_size_t size) +{ + /* Serial port callback function */ + rt_sem_release(&rx_sem); + return RT_EOK; +} + +static void uart_thread(void *parameter) +{ + char ch; + while (1) + { + /* Serial port readout */ + while (rt_device_read(serial, -1, &ch, 1) != 1) + { + /* semaphore blocking */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + /* Output the data obtained from the serial port */ + rt_device_write(serial, 0, &ch, 1); + rt_device_write(serial,0,"\n",1); + } +} + +static int uart_task(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + + char uart_name[RT_NAME_MAX] = "uart1"; + char str[] = "hello RT-Thread!\r\n"; + if (argc == 3) + { + if(rt_strcmp(argv[2],"start") == 0) + { + rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + } + else if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + } + else + { + rt_kprintf("Incomplete instruction.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start/end\n",__func__); + rt_kprintf("or\n"); + rt_kprintf("%s start/end\n",__func__); + return -1; + } + /* Find Serial Devices */ + serial = rt_device_find(uart_name); + if (!serial) + { + rt_kprintf("find %s failed!\n", uart_name); + return -RT_ERROR; + } + /* Initializing a Signal */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + /* Open the serial device with read/write and interrupt reception. */ + rt_device_open(serial, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* Setting the receive callback function */ + rt_device_set_rx_indicate(serial, uart_iqr_handle); + /* Send String */ + rt_device_write(serial, 0, str, (sizeof(str) - 1)); + /* Creating a serial thread */ + rt_thread_t thread = rt_thread_create("serial", + uart_thread, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (thread != RT_NULL) + rt_thread_startup(thread); + + return ret; +} +MSH_CMD_EXPORT(uart_task, uart device sample); +#endif +/* hw/sw iic test */ +#ifdef BSP_USING_I2C +static void i2c_thread(void *parameter) +{ + uint8_t write_addr = 0x00; + eeprom_write_type eeprom_date; + char send_dat[] = "i2c write eeprom"; + char read_dat[20] = {0}; + struct rt_i2c_msg msg1[2]; + + eeprom_date.in_data.write_addr = write_addr; + rt_strncpy(eeprom_date.in_data.write_date, send_dat, rt_strlen(send_dat)); + + msg1[0].addr = 0x51; + msg1[0].flags = RT_I2C_WR; + msg1[0].buf = eeprom_date.data; + msg1[0].len = (rt_strlen(send_dat) + 1); + if (rt_i2c_transfer(i2c_dev, msg1, 1) == 1) + { + rt_kprintf("eeprom write succeed!\n"); + rt_kprintf("write_dat = %s\r\n",send_dat); + } + else + { + rt_kprintf("eeprom write error!\n"); + } + msg1[0].addr = 0x51; + msg1[0].flags = RT_I2C_WR; + msg1[0].buf = &write_addr; + msg1[0].len = 1; + + msg1[1].addr = 0x51; + msg1[1].flags = RT_I2C_RD; + msg1[1].buf = (uint8_t *)read_dat; + msg1[1].len = rt_strlen(send_dat); + + if (rt_i2c_transfer(i2c_dev, msg1, 2) == 2) + { + rt_kprintf("eeprom read succeed!\n"); + rt_kprintf("read_dat = %s\r\n",read_dat); + } + else + { + rt_kprintf("eeprom read error!\n"); + } +} + +static int i2c_task(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + + char i2c_name[RT_NAME_MAX] = "hw_i2c1"; + if (argc == 3) + { + if(rt_strcmp(argv[2],"start") == 0) + { + rt_strncpy(i2c_name, argv[1], RT_NAME_MAX); + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + } + else if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + } + else + { + rt_kprintf("Incomplete instruction.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start/end\n",__func__); + rt_kprintf("or\n"); + rt_kprintf("%s start/end\n",__func__); + return -1; + } + /* Find I2C Devices */ + i2c_dev = (struct rt_i2c_bus_device *)rt_device_find(i2c_name); + if (!i2c_dev) + { + rt_kprintf("find %s failed!\n", i2c_name); + return -RT_ERROR; + } + /* Execute I2C read/write eeprom function */ + i2c_thread(RT_NULL); + return ret; +} +MSH_CMD_EXPORT(i2c_task, i2c device sample); +#endif +/* spi test */ +#ifdef BSP_USING_SPI +static void spi_thread(void *parameter) +{ + rt_uint8_t w25x_read_id = 0x9F; + rt_uint8_t id[5] = {0}; + + /* Use rt_spi_send_then_recv() to send commands to read IDs */ + rt_spi_take_bus(spi_dev); + rt_spi_take(spi_dev); + rt_spi_send_then_recv(spi_dev, &w25x_read_id, 1, id, 3); + rt_spi_release(spi_dev); + rt_spi_release_bus(spi_dev); + rt_kprintf("use rt_spi_send_then_recv() read MX25L6406 ID is:0x%X%X%X\n", id[0], id[1], id[2]); +} + +static int spi_task(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + struct rt_spi_configuration cfg; + char spi_name[RT_NAME_MAX] = "spi1"; + char flash_name[RT_NAME_MAX] = "flash"; + + if (argc == 3) + { + if(rt_strcmp(argv[2],"start") == 0) + { + rt_strncpy(spi_name, argv[1], RT_NAME_MAX); + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + } + else if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + } + else + { + rt_kprintf("Incomplete instruction.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start/end\n",__func__); + rt_kprintf("or\n"); + rt_kprintf("%s start/end\n",__func__); + return -1; + } + /* Binding CS pin */ + ret = rt_hw_spi_device_attach(spi_name,flash_name,HT_GPIOD,GPIO_PIN_0); + if(ret != RT_EOK) + { + rt_kprintf("Failed CS pin binding for %s!\n", spi_name); + return -RT_ERROR; + } + /* Find flash devices */ + spi_dev = (struct rt_spi_device*)rt_device_find(flash_name); + if (!spi_dev) + { + rt_kprintf("find %s failed!\n", spi_name); + return -RT_ERROR; + } + /* Configuring the SPI Bus */ + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_3 | RT_SPI_MSB; + cfg.max_hz = 8; + rt_spi_configure(spi_dev,&cfg); + rt_kprintf("SPI0 initialization succeeded!\n"); + + /* Execute flash read and write functions */ + spi_thread(RT_NULL); + rt_device_unregister((rt_device_t)spi_dev); + return ret; +} +MSH_CMD_EXPORT(spi_task, spi device sample); +#endif +/* adc test */ +#ifdef BSP_USING_ADC +static void adc_test(void *parameter) +{ + rt_uint32_t adc0_ch6_val,adc0_ch7_val; + rt_adc_device_t adc_dev = (rt_adc_device_t)rt_device_find("adc0"); + if (!adc_dev) + { + rt_kprintf("No ADC0 device found!\n"); + } + else + { + rt_adc_enable(adc_dev,ADC_CH_6); + rt_adc_enable(adc_dev,ADC_CH_7); + } + while(1) + { + adc0_ch6_val = rt_adc_read(adc_dev,6); + adc0_ch7_val = rt_adc_read(adc_dev,7); + rt_kprintf("adc0_ch6_val = %d\n",adc0_ch6_val); + rt_kprintf("adc0_ch7_val = %d\n",adc0_ch7_val); + rt_thread_mdelay(50); + } +} + +static int adc_task(int argc, char *argv[]) +{ + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + /* Adc test tasks */ + rt_thread_t adc_task = rt_thread_create("adc_task", + adc_test, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (adc_task != RT_NULL) + rt_thread_startup(adc_task); + rt_kprintf("The adc task is registered.\n"); + } + else if(rt_strcmp(argv[1],"end") == 0) + { + rt_event_send(&task_event,TASK_KILL_FLAG); + rt_kprintf("The adc task has been deleted.\n"); + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s end\n",__func__); + return -1; + } + return -1; +} +MSH_CMD_EXPORT(adc_task, adc task operation); +#endif +/* wdt test */ +#ifdef BSP_USING_WDT +static void wdt_test(void) +{ + rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL); +} + +static int wdt_task(int argc, char *argv[]) +{ + rt_err_t ret = -RT_ERROR; + rt_uint16_t wdt_time = 5; + char dev_name[] = "wdt"; + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + /* Find wdt devices */ + wdt_dev = rt_device_find(dev_name); + if(wdt_dev == RT_NULL) + { + rt_kprintf("No corresponding equipment found.\n"); + return -1; + } + /* Configuring the Watchdog */ + ret = rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &wdt_time); + if(ret != RT_EOK) + { + rt_kprintf("wdt configuration failed.\n"); + return -1; + } + /* Start the Watchdog */ + ret = rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL); + if(ret != RT_EOK) + { + rt_kprintf("wdt start failed.\n"); + return -1; + } + /* Setting up idle threads */ + rt_thread_idle_sethook(wdt_test); + rt_kprintf("Watchdog started successfully.\n"); + } + else if(rt_strcmp(argv[1],"stop") == 0) + { + /* Verify device handle */ + if(wdt_dev == RT_NULL) + { + rt_kprintf("Device handle does not exist.\n"); + return -1; + } + /* Stop the Watchdog */ + ret = rt_device_control(wdt_dev, RT_DEVICE_CTRL_WDT_STOP, RT_NULL); + if(ret != RT_EOK) + { + rt_kprintf("wdt start failed.\n"); + return -1; + } + /* Hook function to delete idle threads */ + rt_thread_idle_delhook(wdt_test); + rt_kprintf("Watchdog has stopped.\n"); + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s stop\n",__func__); + return -1; + } + return -1; +} +MSH_CMD_EXPORT(wdt_task, wdt task operation); +#endif +/* usbd test */ +#ifdef BSP_USING_USBD +static void usbd_test(void *parameter) +{ + rt_device_t dev = RT_NULL; + char dev_name[] = "vcom"; + char buf[] = "usbd vcom test!\r\n"; + + dev = rt_device_find(dev_name); + + if (dev) + { + rt_device_open(dev, RT_DEVICE_FLAG_RDWR); + } + else + { + rt_kprintf("Device with name %s not found.\n",dev_name); + rt_thread_t tid = rt_thread_self(); + rt_thread_delete(tid); + } + while (1) + { + rt_device_write(dev, 0, buf, rt_strlen(buf)); + rt_thread_mdelay(500); + } +} + +static int usbd_task(int argc, char *argv[]) +{ + rt_err_t ret = -RT_ERROR; + + if(argc == 2) + { + if(rt_strcmp(argv[1],"start") == 0) + { + /* Gpio input test tasks */ + rt_thread_t usbd_vcom_task = rt_thread_create("usbd_vcom_task", + usbd_test, RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, THREAD_TIMESLICE); + if (usbd_vcom_task != RT_NULL) + { + rt_thread_startup(usbd_vcom_task); + rt_kprintf("The usbd vcom task is registered.\n"); + } + else + { + rt_kprintf("usbd vcom task registration failed.\n"); + } + ret = RT_EOK; + } + else if(rt_strcmp(argv[1],"stop") == 0) + { + ret = RT_EOK; + } + } + else + { + rt_kprintf("Necessary parameters are missing.\n"); + rt_kprintf("You can use the following commands.\n"); + rt_kprintf("%s start\n",__func__); + rt_kprintf("%s stop\n",__func__); + } + return ret; +} +MSH_CMD_EXPORT(usbd_task, usbd task operation); + +#endif /* BSP_USING_USBD */ + +#ifdef BSP_USING_CAN + +#define CAN_DEV_NAME BSP_USING_CAN_NAME + +static struct rt_semaphore rx_sem; +static rt_device_t can_dev; + +static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) +{ + rt_sem_release(&rx_sem); + return RT_EOK; +} +static rt_err_t can_tx_data(void) +{ + struct rt_can_msg msg = {0}; + rt_size_t size; + + msg.id = 0x540; + msg.ide = RT_CAN_STDID; + msg.rtr = RT_CAN_DTR; + msg.len = 8; + + msg.data[0] = 0x00; + msg.data[1] = 0x01; + msg.data[2] = 0x02; + msg.data[3] = 0x03; + msg.data[4] = 0x04; + msg.data[5] = 0x05; + msg.data[6] = 0x06; + msg.data[7] = 0x07; + + size = rt_device_write(can_dev, 0, &msg, sizeof(msg)); + if (size == 0) + { + rt_kprintf("can dev write data failed!\n"); + } + return 0; +} + +static void can_rx_thread(void *parameter) +{ + int i; + rt_size_t size; + rt_uint8_t send_cut = 0; + struct rt_can_msg rxmsg = {0}; + + /* Setting the receive callback function */ + rt_device_set_rx_indicate(can_dev, can_rx_call); + + /* Setting the Hardware Filter Table */ + struct rt_can_filter_item items[1] = + { /* id ide rtr mode mask */ + RT_CAN_FILTER_ITEM_INIT(0x541, RT_CAN_STDID, RT_CAN_DTR, 0, 0x7ff), + }; + struct rt_can_filter_config cfg = {1, 1, items}; + rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); + + can_tx_data(); + while (1) + { + + rxmsg.hdr_index = -1; + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); + + rt_kprintf("ID:%x ", rxmsg.id); + for (i = 0; i < 8; i++) + { + rt_kprintf(" %2x", rxmsg.data[i]); + rxmsg.data[i] += 1; + } + rt_kprintf(" \n"); + rxmsg.id = 0x540; + rxmsg.ide = RT_CAN_STDID; + rxmsg.rtr = RT_CAN_DTR; + rxmsg.len = 8; + rt_thread_mdelay(1000); + if(send_cut < 10) + { + size = rt_device_write(can_dev, 0, &rxmsg, sizeof(rxmsg)); + send_cut++; + if (size == 0) + { + rt_kprintf("can dev write data failed!\n"); + } + } + } +} + +int can_test(int argc, char *argv[]) +{ + rt_err_t res; + rt_thread_t thread; + char can_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(can_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX); + } + + /* Find a CAN Device */ + can_dev = rt_device_find(can_name); + if (!can_dev) + { + rt_kprintf("find %s failed!\n", can_name); + return -RT_ERROR; + } + + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + + res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); + RT_ASSERT(res == RT_EOK); + + res = rt_device_control(can_dev, RT_CAN_CMD_SET_BAUD, (void *)CAN500kBaud); + RT_ASSERT(res == RT_EOK); + + thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10); + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create can_rx thread failed!\n"); + } + + return res; +} + +MSH_CMD_EXPORT(can_test, can device sample); + +#endif /* BSP_USING_CAN */ + +#endif /* BSP_USING_TEST */ diff --git a/bsp/ht32/ht32f53252/board/Kconfig b/bsp/ht32/ht32f53252/board/Kconfig new file mode 100644 index 0000000000..8ba20cd72d --- /dev/null +++ b/bsp/ht32/ht32f53252/board/Kconfig @@ -0,0 +1,449 @@ +menu "Hardware Drivers Config" + +menu "Chip Configuration" + config SOC_KERNEL + bool + select SOC_SERIES_HT32F5 if CORTEX_M0 + select SOC_SERIES_HT32F1 if CORTEX_M3 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + choice + prompt "Select the kernel" + default CORTEX_M0 + config CORTEX_M0 + bool "CORTEX_M0" + config CORTEX_M3 + bool "CORTEX_M3" + endchoice + + choice + prompt "Select the chip you are using" + depends on CORTEX_M0 + default HT32F52352 + config SOC_HT32F0006 + bool "HT32F0006" + config SOC_HT32F0008 + bool "HT32F0008" + config SOC_HT32F50241 + bool "HT32F50241" + config SOC_HT32F50343 + bool "HT32F50343" + config SOC_HT32F50441 + bool "HT32F50441" + config SOC_HT32F50452 + bool "HT32F50452" + config SOC_HT32F52241 + bool "HT32F52241" + config SOC_HT32F52244 + bool "HT32F52244" + config SOC_HT32F52253 + bool "HT32F52253" + config SOC_HT32F52341 + bool "HT32F52341" + config SOC_HT32F52352 + bool "HT32F52352" + config SOC_HT32F52354 + bool "HT32F52354" + config SOC_HT32F52367 + bool "HT32F52367" + config SOC_HT32F53241 + bool "HT32F53241" + config SOC_HT32F53252 + bool "HT32F53252" + config SOC_HT32F54241 + bool "HT32F54241" + config SOC_HT32F54253 + bool "HT32F54253" + config SOC_HT32F57341 + bool "HT32F57341" + config SOC_HT32F57352 + bool "HT32F57352" + config SOC_HT32F5828 + bool "HT32F5828" + config SOC_HT32F59041 + bool "HT32F59041" + config SOC_HT32F59741 + bool "HT32F59741" + config SOC_HT32F61141 + bool "HT32F61141" + config SOC_HT32F61245 + bool "HT32F61245" + config SOC_HT32F61355 + bool "HT32F61355" + config SOC_HT32F61356 + bool "HT32F61356" + config SOC_HT32F61357 + bool "HT32F61357" + config SOC_HT32F61641 + bool "HT32F61641" + config SOC_HT32F65240 + bool "HT32F65240" + config SOC_HT32F67051 + bool "HT32F67051" + config SOC_HT32F67741 + bool "HT32F67741" + endchoice + + choice + prompt "Select the chip you are using" + depends on CORTEX_M3 + default HT32F52352 + config SOC_HT32F1654 + bool "HT32F1654" + config SOC_HT32F1656 + bool "HT32F1656" + config SOC_HT32F12345 + bool "HT32F12345" + config SOC_HT32F12364 + bool "HT32F12364" + config SOC_HT32F12366 + bool "HT32F12366" + endchoice +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_TEST + bool "Enable test" + default n + + if RT_USING_CONSOLE + config RT_CONSOLE_DEVICE_NAME + string "the device name for console" + default "usart1" + endif + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_USART0 + bool "Enable USART0" + default n + config BSP_USING_USART0_NAME + depends on BSP_USING_USART0 + string "usart0 bus name" + default "usart0" + + config BSP_USING_USART1 + bool "Enable USART1" + default n + config BSP_USING_USART1_NAME + depends on BSP_USING_USART1 + string "usart1 bus name" + default "usart1" + + config BSP_USING_UART0 + bool "Enable UART0" + default n + config BSP_USING_UART0_NAME + depends on BSP_USING_UART0 + string "uart0 bus name" + default "uart0" + + config BSP_USING_UART1 + bool "Enable UART1" + default n + config BSP_USING_UART1_NAME + depends on BSP_USING_UART1 + string "uart1 bus name" + default "uart1" + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI Bus" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 Bus" + default n + config BSP_USING_SPI0_NAME + depends on BSP_USING_SPI0 + string "spi0 bus name" + default "spi0" + + config BSP_USING_SPI1 + bool "Enable SPI1 Bus" + default n + config BSP_USING_SPI1_NAME + depends on BSP_USING_SPI1 + string "spi1 bus name" + default "spi1" + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Bus" + default n + if BSP_USING_I2C + menuconfig BSP_USING_I2C_HW + bool "Enable I2C Bus(hardware)" + default n + select RT_USING_I2C if BSP_USING_I2C_HW + if BSP_USING_I2C_HW + config BSP_USING_I2C0_HW + bool "Enable Hardware I2C0 Bus" + default n + config BSP_USING_I2C0_HW_NAME + depends on BSP_USING_I2C0_HW + string "hardware i2c0 name" + default "hw_i2c0" + + config BSP_USING_I2C1_HW + bool "Enable Hardware I2C1 Bus" + default n + config BSP_USING_I2C1_HW_NAME + depends on BSP_USING_I2C1_HW + string "hardware i2c1 name" + default "hw_i2c1" + endif + + menuconfig BSP_USING_I2C_SW + bool "Enable I2C Bus(software)" + default n + select BSP_USING_GPIO if BSP_USING_I2C_SW + select RT_USING_I2C if BSP_USING_I2C_SW + + if BSP_USING_I2C_SW + config BSP_USING_I2C0_SW + bool "Enable Software I2C0 Bus" + default n + config BSP_USING_I2C0_SW_NAME + depends on BSP_USING_I2C0_SW + string "software i2c0 name" + default "sw_i2c0" + if BSP_USING_I2C0_SW + config BSP_I2C0_SLC_PIN + int "i2c0 slc pin number" + range 0 51 + default 22 + + config BSP_I2C0_SDA_PIN + int "i2c0 sda pin number" + range 0 51 + default 23 + endif + + config BSP_USING_I2C1_SW + bool "Enable Software I2C1 Bus" + default n + config BSP_USING_I2C1_SW_NAME + depends on BSP_USING_I2C1_SW + string "software i2c1 name" + default "sw_i2c1" + if BSP_USING_I2C1_SW + config BSP_I2C1_SLC_PIN + int "i2c1 slc pin number" + range 0 51 + default 24 + + config BSP_I2C1_SDA_PIN + int "i2c1 sda pin number" + range 0 51 + default 25 + endif + + config BSP_USING_I2C2_SW + bool "Enable Software I2C2 Bus" + default n + config BSP_USING_I2C2_SW_NAME + depends on BSP_USING_I2C2_SW + string "software i2c2 name" + default "sw_i2c2" + if BSP_USING_I2C2_SW + config BSP_I2C2_SLC_PIN + int "i2c2 slc pin number" + range 0 51 + default 26 + + config BSP_I2C2_SDA_PIN + int "i2c2 sda pin number" + range 0 51 + default 27 + endif + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC0_NAME + depends on BSP_USING_ADC0 + string "adc0 device name" + default "adc0" + + config BSP_USING_ADC1 + bool "Enable ADC1" + depends on SOC_HT32F65240 + default n + config BSP_USING_ADC1_NAME + depends on BSP_USING_ADC1 + string "adc1 device name" + default "adc1" + endif + + menuconfig BSP_USING_WDT + bool "Enable WDT" + default n + select RT_USING_WDT if BSP_USING_WDT + config BSP_USING_WDT_NAME + depends on BSP_USING_WDT + string "wdt device name" + default "wdt" + + menuconfig BSP_USING_CAN + bool "Enable CAN" + depends on SOC_HT32F53241 || SOC_HT32F53242 || SOC_HT32F53252 + default n + select RT_USING_CAN if BSP_USING_CAN + config BSP_USING_CAN_NAME + depends on BSP_USING_CAN + string "can device name" + default "can" + if BSP_USING_CAN + config CAN_DEFAULT_BASE_CONFIGURATION + choice + prompt "Default CAN baud rate" + default BSP_USING_CAN500kBaud + config BSP_USING_CAN1MBaud + bool "CAN1MBaud" + config BSP_USING_CAN800kBaud + bool "CAN800kBaud" + config BSP_USING_CAN500kBaud + bool "CAN500kBaud" + config BSP_USING_CAN250kBaud + bool "CAN250kBaud" + config BSP_USING_CAN125kBaud + bool "CAN125kBaud" + config BSP_USING_CAN100kBaud + bool "CAN100kBaud" + config BSP_USING_CAN50kBaud + bool "CAN50kBaud" + config BSP_USING_CAN20kBaud + bool "CAN20kBaud" + config BSP_USING_CAN10kBaud + bool "CAN10kBaud" + endchoice + choice + prompt "Default CAN mode" + default BSP_USING_RT_CAN_MODE_NORMAL + config BSP_USING_RT_CAN_MODE_NORMAL + bool "RT_CAN_MODE_NORMAL" + config BSP_USING_RT_CAN_MODE_LISTEN + bool "RT_CAN_MODE_LISTEN" + config BSP_USING_RT_CAN_MODE_LOOPBACK + bool "RT_CAN_MODE_LOOPBACK" + config BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN + bool "RT_CAN_MODE_LOOPBACKANLISTEN" + endchoice + + config BSP_USING_CAN_BAUD + int + default 1000000 if BSP_USING_CAN1MBaud + default 800000 if BSP_USING_CAN800kBaud + default 500000 if BSP_USING_CAN500kBaud + default 250000 if BSP_USING_CAN250kBaud + default 125000 if BSP_USING_CAN125kBaud + default 100000 if BSP_USING_CAN100kBaud + default 50000 if BSP_USING_CAN50kBaud + default 20000 if BSP_USING_CAN20kBaud + default 10000 if BSP_USING_CAN10kBaud + + config BSP_USING_CAN_MODE + int + default 0 if BSP_USING_RT_CAN_MODE_NORMAL + default 1 if BSP_USING_RT_CAN_MODE_LISTEN + default 2 if BSP_USING_RT_CAN_MODE_LOOPBACK + default 3 if BSP_USING_RT_CAN_MODE_LOOPBACKANLISTEN + + config CAN_DEFAULT_FILTER_TABLE_CONFIGURATION + choice + prompt "Default filter id mode" + default BSP_USING_CAN_STD_ID + config BSP_USING_CAN_STD_ID + bool "CAN_STD_ID" + config BSP_USING_CAN_EXT_ID + bool "CAN_EXT_ID" + endchoice + + choice + prompt "Default filter frame mode" + default BSP_USING_CAN_DATA_FRAME + config BSP_USING_CAN_DATA_FRAME + bool "CAN_DATA_FRAME" + config BSP_USING_CAN_REMOTE_FRAME + bool "CAN_REMOTE_FRAME" + endchoice + + config BSP_USING_CAN_ID_MODE + int + default 0 if BSP_USING_CAN_STD_ID + default 1 if BSP_USING_CAN_EXT_ID + + config BSP_USING_CAN_FRAME_MODE + int + default 0 if BSP_USING_CAN_REMOTE_FRAME + default 1 if BSP_USING_CAN_DATA_FRAME + + config BSP_USING_CAN_MSG_NUM + int "Default filter table number" + range 0 31 + default 0 + + config BSP_USING_CAN_ID + hex "Default filter arbitration bit(ID)" + range 0 0x7FF if BSP_USING_CAN_STD_ID + default 0x541 if BSP_USING_CAN_STD_ID + range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + default 0x541 if BSP_USING_CAN_EXT_ID + + config BSP_USING_CAN_MASK + hex "Default filter mask bit(MASK)" + range 0 0x7FF if BSP_USING_CAN_STD_ID + default 0x7FF if BSP_USING_CAN_STD_ID + range 0 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + default 0x1FFFFFFF if BSP_USING_CAN_EXT_ID + + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + depends on SOC_HT32F12345 || SOC_HT32F12365 || SOC_HT32F12366 + default n + select RT_USING_SDIO if BSP_USING_SDIO + config BSP_USING_SDIO_NAME + depends on BSP_USING_SDIO + string "sdio device name" + default "sdio" + + menuconfig BSP_USING_USBD + bool "Enable USB BUS" + default n + select RT_USING_USB_DEVICE if BSP_USING_USBD + config BSP_USING_USBD_NAME + depends on BSP_USING_USBD + string "usbd device name" + default "usbd" +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ht32/ht32f53252/board/SConscript b/bsp/ht32/ht32f53252/board/SConscript new file mode 100644 index 0000000000..e92da4da29 --- /dev/null +++ b/bsp/ht32/ht32f53252/board/SConscript @@ -0,0 +1,27 @@ + +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +src = Glob('src/*.c') + +startup_path_prefix = SDK_LIB +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s'] + +path = [cwd] +path = [cwd + '/inc'] + +CPPDEFINES = ['USE_HT32F53252_SK, USE_HT32F53242_52, USE_MEM_HT32F53252'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f53252/board/inc/board.h b/bsp/ht32/ht32f53252/board/inc/board.h new file mode 100644 index 0000000000..c4a817d79b --- /dev/null +++ b/bsp/ht32/ht32f53252/board/inc/board.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ht32.h" +#include "ht32_msp.h" + +#ifdef BSP_USING_GPIO + #include "drv_gpio.h" +#endif + +#ifdef BSP_USING_SPI + #include "drv_spi.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* whether use board external SRAM memory */ +#define HT32_EXT_SRAM 0 +#define HT32_EXT_SRAM_BEGIN 0x68000000 +#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024) + +/* internal sram memory size */ +#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END HT32_SRAM_END + +void rt_hw_board_clock_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ht32/ht32f53252/board/inc/ht32_can_config.h b/bsp/ht32/ht32f53252/board/inc/ht32_can_config.h new file mode 100644 index 0000000000..bbef2115c9 --- /dev/null +++ b/bsp/ht32/ht32f53252/board/inc/ht32_can_config.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************//** + * @file CAN/Send_DATA/ht32_can_config.h + * @version $Rev:: 8164 $ + * @date $Date:: 2024-09-20 #$ + * @brief The header file of CAN baudrate configuration. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CAN_CONFIG_H +#define __HT32_CAN_CONFIG_H + +#ifdef __cplusplus + extern "C" { +#endif + + +// Enable CAN Config Check +// Display related setting by printf(). +#define HTCFG_CAN_CONF_CHECK_ENABLE (0) + +// Core Clock Setting +// +// -- Core Clock Calculation Setting +// HTCFG_CAN_CORECLKSEL +// Define the Core Clock by default maximum clock setting or manual input. +// 0 = Default Maximum (LIBCFG_MAX_SPEED) +// 1 = Manual Input (HTCFG_CAN_CORECLK_MANUAL) +// <0=> Default Maximum (LIBCFG_MAX_SPEED) +// <1=> Manual Input (HTCFG_CAN_CORECLK_MANUAL) +// Note: CK_CAN = (Core Clock) / (CAN Peripheral Clock Prescaler) +// -- Core Clock Manual Input (Hz) +// HTCFG_CAN_CORECLK_MANUAL +// Only meaningful when HTCFG_CAN_CLKSEL = 1 (Manual Input) +#define HTCFG_CAN_CORECLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_CAN_CORECLK_MANUAL) +#define HTCFG_CAN_CORECLK_MANUAL (8000000) // Only meaningful when HTCFG_CAN_CORECLKSEL = 1 (Manual Input) + +// ------------------------------------------ +// + +// CAN Config 0 Setting +// +// CAN Peripheral Clock Selection (CANnPCLK) +// HTCFG_CAN_CLK_PRESCALER +// <0=> Div 1 +// <1=> Div 2 +// <2=> Div 4 +// <3=> Div 8 +#define HTCFG_CAN_CF0_CLK_DIV (0) // 0 = /1, 1 = /2, 2 = /4, 3 = /8 + +/* +// CAN Baudrate +// HTCFG_CAN_BAUDRATE +// <1000000=> 1000 kbps +// <800000=> 800 kbps +// <500000=> 500 kbps +// <250000=> 250 kbps +// <125000=> 125 kbps +// <100000=> 100 kbps +// <50000=> 50 kbps +// <20000=> 20 kbps +// <10000=> 10 kbps +// <5000=> 5 kbps +// The CAN baudrate specifies the frequency of transitions occurring per second. +*/ +#define HTCFG_CAN_CF0_BAUDRATE (500000) + +/* +// CAN Sample Point Target (%) <50-90:1> +// HTCFG_CAN_SAMPLE_POINT +// The Sample Point is the specific location within each bit period where the CAN_Core samples the CAN bus's state (dominant or recessive). +// Notice: The real calculation result may small than the HTCFG_CAN_SAMPLE_POINT setting. +*/ +#define HTCFG_CAN_CF0_SAMPLE_POINT (70) + +// CAN SJW (Synchronisation Jump Width) +// HTCFG_CAN_BIT_TIME_SJW +// The (Re-)Synchronisation Jump Width. +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +#define HTCFG_CAN_CF0_BIT_TIME_SJW (1) // 1 ~ 4 + +#include "ht32_can_config0_calc.h" + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/ht32f53252/board/inc/ht32_msp.h b/bsp/ht32/ht32f53252/board/inc/ht32_msp.h new file mode 100644 index 0000000000..e45294becb --- /dev/null +++ b/bsp/ht32/ht32f53252/board/inc/ht32_msp.h @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __HT32_MSP_H__ +#define __HT32_MSP_H__ + +#include +#include "ht32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART gpio */ +#ifdef BSP_USING_UART +#ifdef BSP_USING_USART0 +#define HTCFG_USART0_IPN USART0 + +#define _HTCFG_USART0_TX_GPIOX A +#define _HTCFG_USART0_TX_GPION 2 +#define _HTCFG_USART0_RX_GPIOX A +#define _HTCFG_USART0_RX_GPION 3 + +#define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION) + +#define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION) + +#endif +#ifdef BSP_USING_USART1 + +#define HTCFG_USART1_IPN USART1 + +#define _HTCFG_USART1_TX_GPIOX A +#define _HTCFG_USART1_TX_GPION 4 +#define _HTCFG_USART1_RX_GPIOX A +#define _HTCFG_USART1_RX_GPION 5 + +#define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION) + +#define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION) + +#endif +#ifdef BSP_USING_UART0 + +#define HTCFG_UART0_IPN UART0 + +#define _HTCFG_UART0_TX_GPIOX B +#define _HTCFG_UART0_TX_GPION 2 +#define _HTCFG_UART0_RX_GPIOX B +#define _HTCFG_UART0_RX_GPION 3 + +#define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION) + +#define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION) + +#endif +#ifdef BSP_USING_UART1 + +#define HTCFG_UART1_IPN UART1 + +#define _HTCFG_UART1_TX_GPIOX B +#define _HTCFG_UART1_TX_GPION 4 +#define _HTCFG_UART1_RX_GPIOX B +#define _HTCFG_UART1_RX_GPION 5 + +#define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION) + +#define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION) + +#endif +#endif + +/* SPI gpio */ +#ifdef BSP_USING_SPI +#ifdef BSP_USING_SPI0 + +#define HTCFG_SPI0_IPN SPI0 + +#define _HTCFG_SPI0_SCK_GPIOX C +#define _HTCFG_SPI0_SCK_GPION 0 + +#define _HTCFG_SPI0_MISO_GPIOX A +#define _HTCFG_SPI0_MISO_GPION 11 + +#define _HTCFG_SPI0_MOSI_GPIOX A +#define _HTCFG_SPI0_MOSI_GPION 9 + +#define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX) +#define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX) +#define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION) + +#define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX) +#define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX) +#define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION) + +#define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX) +#define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX) +#define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION) + +#endif +#ifdef BSP_USING_SPI1 + +#define HTCFG_SPI1_IPN SPI1 + +#define _HTCFG_SPI1_SCK_GPIOX C +#define _HTCFG_SPI1_SCK_GPION 5 + +#define _HTCFG_SPI1_MISO_GPIOX C +#define _HTCFG_SPI1_MISO_GPION 9 + +#define _HTCFG_SPI1_MOSI_GPIOX C +#define _HTCFG_SPI1_MOSI_GPION 8 + +#define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX) +#define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX) +#define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION) + +#define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX) +#define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX) +#define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION) + +#define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX) +#define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX) +#define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION) + +#endif +#endif + +/* I2C gpio */ +#ifdef BSP_USING_I2C_HW +#ifdef BSP_USING_I2C0_HW + +#define HTCFG_I2C0_IPN I2C0 + +#define _HTCFG_I2C0_SCL_GPIOX C +#define _HTCFG_I2C0_SCL_GPION 12 + +#define _HTCFG_I2C0_SDA_GPIOX C +#define _HTCFG_I2C0_SDA_GPION 13 + +#define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX) +#define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX) +#define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION) + +#define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX) +#define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX) +#define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION) + +#endif +#ifdef BSP_USING_I2C1_HW + +#define HTCFG_I2C1_IPN I2C1 + +#define _HTCFG_I2C1_SCL_GPIOX A +#define _HTCFG_I2C1_SCL_GPION 0 + +#define _HTCFG_I2C1_SDA_GPIOX A +#define _HTCFG_I2C1_SDA_GPION 1 + +#define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX) +#define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX) +#define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION) + +#define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX) +#define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX) +#define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION) + +#endif +#endif + +/* ADC gpio */ +#ifdef BSP_USING_ADC +#ifdef BSP_USING_ADC0 + +#define HTCFG_ADC0_IPN ADC0 + +#define _HTCFG_ADC0CH0_GPIOX A +#define _HTCFG_ADC0CH0_AFION 0 + +#define _HTCFG_ADC0CH1_GPIOX A +#define _HTCFG_ADC0CH1_AFION 1 + +#define _HTCFG_ADC0CH2_GPIOX A +#define _HTCFG_ADC0CH2_AFION 2 + +#define _HTCFG_ADC0CH3_GPIOX A +#define _HTCFG_ADC0CH3_AFION 3 + +#define _HTCFG_ADC0CH4_GPIOX A +#define _HTCFG_ADC0CH4_AFION 4 + +#define _HTCFG_ADC0CH5_GPIOX A +#define _HTCFG_ADC0CH5_AFION 5 + +#define _HTCFG_ADC0CH6_GPIOX A +#define _HTCFG_ADC0CH6_AFION 6 + +#define _HTCFG_ADC0CH7_GPIOX A +#define _HTCFG_ADC0CH7_AFION 7 + +#define _HTCFG_ADC0CH8_GPIOX C +#define _HTCFG_ADC0CH8_AFION 4 + +#define _HTCFG_ADC0CH9_GPIOX C +#define _HTCFG_ADC0CH9_AFION 5 + +#define _HTCFG_ADC0CH10_GPIOX C +#define _HTCFG_ADC0CH10_AFION 8 + +#define _HTCFG_ADC0CH11_GPIOX C +#define _HTCFG_ADC0CH11_AFION 9 + +#define _HTCFG_ADC0CH12_GPIOX C +#define _HTCFG_ADC0CH12_AFION 1 + +#define _HTCFG_ADC0CH13_GPIOX C +#define _HTCFG_ADC0CH13_AFION 1 + +#define _HTCFG_ADC0CH14_GPIOX C +#define _HTCFG_ADC0CH14_AFION 1 + +#define _HTCFG_ADC0CH15_GPIOX C +#define _HTCFG_ADC0CH15_AFION 1 + +#define HTCFG_ADC0CH0_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH0_GPIOX) +#define HTCFG_ADC0CH1_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH1_GPIOX) +#define HTCFG_ADC0CH2_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH2_GPIOX) +#define HTCFG_ADC0CH3_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH3_GPIOX) +#define HTCFG_ADC0CH4_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH4_GPIOX) +#define HTCFG_ADC0CH5_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH5_GPIOX) +#define HTCFG_ADC0CH6_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH6_GPIOX) +#define HTCFG_ADC0CH7_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH7_GPIOX) +#define HTCFG_ADC0CH8_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH8_GPIOX) +#define HTCFG_ADC0CH9_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH9_GPIOX) +#define HTCFG_ADC0CH10_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH10_GPIOX) +#define HTCFG_ADC0CH11_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH11_GPIOX) +#define HTCFG_ADC0CH12_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH12_GPIOX) +#define HTCFG_ADC0CH13_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH13_GPIOX) +#define HTCFG_ADC0CH14_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH14_GPIOX) +#define HTCFG_ADC0CH15_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC0CH15_GPIOX) + +#define HTCFG_ADC0CH0_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH0_AFION) +#define HTCFG_ADC0CH1_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH1_AFION) +#define HTCFG_ADC0CH2_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH2_AFION) +#define HTCFG_ADC0CH3_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH3_AFION) +#define HTCFG_ADC0CH4_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH4_AFION) +#define HTCFG_ADC0CH5_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH5_AFION) +#define HTCFG_ADC0CH6_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH6_AFION) +#define HTCFG_ADC0CH7_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH7_AFION) +#define HTCFG_ADC0CH8_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH8_AFION) +#define HTCFG_ADC0CH9_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH9_AFION) +#define HTCFG_ADC0CH10_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH10_AFION) +#define HTCFG_ADC0CH11_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH11_AFION) +#define HTCFG_ADC0CH12_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH12_AFION) +#define HTCFG_ADC0CH13_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH13_AFION) +#define HTCFG_ADC0CH14_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH14_AFION) +#define HTCFG_ADC0CH15_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC0CH15_AFION) + +#endif +#ifdef BSP_USING_ADC1 + +#define HTCFG_ADC1_IPN ADC1 + +#define _HTCFG_ADC1CH0_GPIOX B +#define _HTCFG_ADC1CH0_AFION 8 + +#define _HTCFG_ADC1CH1_GPIOX A +#define _HTCFG_ADC1CH1_AFION 0 + +#define _HTCFG_ADC1CH2_GPIOX A +#define _HTCFG_ADC1CH2_AFION 1 + +#define _HTCFG_ADC1CH3_GPIOX A +#define _HTCFG_ADC1CH3_AFION 2 + +#define _HTCFG_ADC1CH4_GPIOX A +#define _HTCFG_ADC1CH4_AFION 3 + +#define _HTCFG_ADC1CH5_GPIOX A +#define _HTCFG_ADC1CH5_AFION 4 + +#define _HTCFG_ADC1CH6_GPIOX A +#define _HTCFG_ADC1CH6_AFION 5 + +#define _HTCFG_ADC1CH7_GPIOX A +#define _HTCFG_ADC1CH7_AFION 6 + +#define HTCFG_ADC1CH0_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH0_GPIOX) +#define HTCFG_ADC1CH1_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH1_GPIOX) +#define HTCFG_ADC1CH2_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH2_GPIOX) +#define HTCFG_ADC1CH3_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH3_GPIOX) +#define HTCFG_ADC1CH4_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH4_GPIOX) +#define HTCFG_ADC1CH5_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH5_GPIOX) +#define HTCFG_ADC1CH6_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH6_GPIOX) +#define HTCFG_ADC1CH7_GPIO_ID STRCAT2(GPIO_P, _HTCFG_ADC1CH7_GPIOX) + +#define HTCFG_ADC1CH0_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH0_AFION) +#define HTCFG_ADC1CH1_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH1_AFION) +#define HTCFG_ADC1CH2_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH2_AFION) +#define HTCFG_ADC1CH3_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH3_AFION) +#define HTCFG_ADC1CH4_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH4_AFION) +#define HTCFG_ADC1CH5_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH5_AFION) +#define HTCFG_ADC1CH6_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH6_AFION) +#define HTCFG_ADC1CH7_AFIO_PIN STRCAT2(AFIO_PIN_, _HTCFG_ADC1CH7_AFION) + +#endif +#endif +/* CAN gpio */ +#ifdef BSP_USING_CAN +#define HTCFG_CAN_IPN CAN0 + +#define _HTCFG_CAN_TX_GPIOX C +#define _HTCFG_CAN_TX_GPION 6 + +#define _HTCFG_CAN_RX_GPIOX C +#define _HTCFG_CAN_RX_GPION 7 + +#define HTCFG_CAN_TX_GPIO_CLK STRCAT2(P, _HTCFG_CAN_TX_GPIOX) +#define HTCFG_CAN_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_CAN_TX_GPIOX) +#define HTCFG_CAN_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_CAN_TX_GPION) + +#define HTCFG_CAN_RX_GPIO_CLK STRCAT2(P, _HTCFG_CAN_RX_GPIOX) +#define HTCFG_CAN_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_CAN_RX_GPIOX) +#define HTCFG_CAN_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_CAN_RX_GPION) +#endif + +void ht32_usart_gpio_init(void *instance); +void ht32_spi_gpio_init(void *instance); +void ht32_hardware_i2c_gpio_init(void *instance); +void ht32_adc_gpio_init(void *instance,int8_t channel); +void ht32_can_gpio_init(void *instance); + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_MSP_H__ */ diff --git a/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_01_usbdconf.h b/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_01_usbdconf.h new file mode 100644 index 0000000000..d1ef029d1b --- /dev/null +++ b/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_01_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_01_usbdconf.h + * @version $Rev:: 2390 $ + * @date $Date:: 2017-12-21 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_01_USBDCONF_H +#define __HT32F5XXXX_01_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0xFF1D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (2) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x12) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (2) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x012) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x12) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (64) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x12) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (1) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (64) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x12) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (1) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (64) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x12) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (64) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x12) +// +// + +#endif diff --git a/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_02_usbdconf.h b/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_02_usbdconf.h new file mode 100644 index 0000000000..272e8cd127 --- /dev/null +++ b/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_02_usbdconf.h @@ -0,0 +1,569 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_02_usbdconf.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_02_USBDCONF_H +#define __HT32F5XXXX_02_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +// Endpoint8 Interrupt Enable (EP8IE) +// Endpoint9 Interrupt Enable (EP9IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint8 Configuration +#define _EP8_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP8_CFG_EPADR (8) + +// Endpoint Enable (EPEN) +#define _EP8_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP8_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP8_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP8LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP8_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint9 Configuration +#define _EP9_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP9_CFG_EPADR (9) + +// Endpoint Enable (EPEN) +#define _EP9_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP9_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP9_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP9LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP9_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_conf.h b/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_conf.h new file mode 100644 index 0000000000..c78b9bb75d --- /dev/null +++ b/bsp/ht32/ht32f53252/board/inc/ht32f5xxxx_conf.h @@ -0,0 +1,556 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_conf.h + * @version $Rev:: 7109 $ + * @date $Date:: 2023-08-10 #$ + * @brief Library configuration file. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CONF_H +#define __HT32F5XXXX_CONF_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + +#define RETARGET_USB 1 +#define RETARGET_SYSLOG 2 +#define RETARGET_COM1 10 +#define RETARGET_COM2 11 +#define RETARGET_USART0 12 +#define RETARGET_USART1 13 +#define RETARGET_UART0 14 +#define RETARGET_UART1 15 +#define RETARGET_UART2 16 +#define RETARGET_UART3 17 + + +/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */ +/* +// Enable Retarget +// Retarget Port +// <1=> USB Virtual COM +// <2=> Syslog +// <10=> COM1 +// <11=> COM2 +// <12=> USART0 +// <13=> USART1 +// <14=> UART0 +// <15=> UART1 +// <16=> UART2 +// <17=> UART3 +// Enable Auto Return +// Auto Return function adds "\r" before "\n" automatically when print message by Retarget. +*/ +#define _RETARGET 1 +#define RETARGET_PORT 10 +#define _AUTO_RETURN 0 + +#ifndef AUTO_RETURN +#if (_AUTO_RETURN == 1) +#define AUTO_RETURN +#endif +#endif + +/* Enable Interrupt Mode for UxART Retarget +// Retarget COM/UxART Setting +// UxART Baudrate +// Enable Interrupt Mode for UxART Tx Retarget +// Define UxARTn_IRQHandler By Retarget (ht32_serial.c) +// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler. +// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable. +// Tx Buffer Length (in byte) +// +*/ +#define RETARGET_UxART_BAUDRATE 115200 +#define RETARGET_INT_MODE 0 +#define RETARGET_DEFINE_HANDLER 1 +#define RETARGET_INT_BUFFER_SIZE 64 + +#if (_RETARGET == 1) +#if (RETARGET_PORT == RETARGET_USB) + #define RETARGET_IS_USB +// Retarget USB Virtual COM Setting +// Communication (Interrupt IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Rx (Bulk OUT) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Tx (Bulk IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Communication Endpoint Buffer Length (in byte) <4-64:4> +// Data Rx Endpoint Buffer Length (in byte) <4-64:4> +// Data Tx Endpoint Buffer Length (in byte) <4-64:4> +// Rx Buffer Length (in byte) <64-1024:4> +// Tx Buffer Length (in byte) <1-63:1> +// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. +// USB Tx Mode (BULK IN) +// <0=> Block Mode (Wait until both USB and terminal software are ready) +// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready) +// Enable HSI Auto Trim By USB Function +// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source). + #define RETARGET_CTRL_EPT (5) + #define RETARGET_RX_EPT (6) + #define RETARGET_TX_EPT (7) + #define RETARGET_CTRL_EPTLEN (8) + #define RETARGET_RX_EPTLEN (64) + #define RETARGET_TX_EPTLEN (64) + #define RETARGET_BUFFER_SIZE (64) + #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. + #define RETARGET_USB_MODE (0) + #define RETARGET_HSI_ATM (1) +// +#elif (RETARGET_PORT == RETARGET_COM1) + #define RETARGET_COM_PORT COM1 + #define RETARGET_USART_PORT COM1_PORT + #define RETARGET_UART_IRQn COM1_IRQn + #define RETARGET_UART_IRQHandler COM1_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_COM2) + #define RETARGET_COM_PORT COM2 + #define RETARGET_USART_PORT COM2_PORT + #define RETARGET_UART_IRQn COM2_IRQn + #define RETARGET_UART_IRQHandler COM2_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART0) + #define RETARGET_UxART_IPN USART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART1) + #define RETARGET_UxART_IPN USART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART0) + #define RETARGET_UxART_IPN UART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART1) + #define RETARGET_UxART_IPN UART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART2) + #define RETARGET_UxART_IPN UART2 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART3) + #define RETARGET_UxART_IPN UART3 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#endif + extern void RETARGET_Configuration(void); +#else + #define RETARGET_Configuration(...) + #undef printf + #undef getchar + #define printf(...) + #define getchar() (0) +#endif + +#if (RETARGET_DEFINE_HANDLER == 0) +#undef RETARGET_UART_IRQHandler +#endif + +/* +// Enable HT32 Time Function +// Provide "Time_GetTick()" and "Time_Dealy()" functions. + +// Timer Selection +// <0=> BFTM0 +// <1=> BFTM1 +// <2=> SCTM0 +// <3=> SCTM1 +// <4=> SCTM2 +// <5=> SCTM3 +// <6=> PWM0 +// <7=> PWM1 +// <8=> PWM2 +// <9=> GPTM0 +// <10=> GPTM1 +// <11=> MCTM0 + +// Timer Clock Setting +// +// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) +// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV) +// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + +// -- Core Clock Setting (CK_AHB) +// HTCFG_TIME_CLKSEL +// 0 = Default Maximum (LIBCFG_MAX_SPEED) +// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL) +// <0=> Default Maximum (LIBCFG_MAX_SPEED) +// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL) + +// -- Core Clock Manual Input (Hz) +// HTCFG_TIME_CLK_MANUAL +// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1) + +// -- APB Peripheral Clock Prescaler +// HTCFG_TIME_PCLK_DIV +// <0=> /1 +// <1=> /2 +// <2=> /4 +// <3=> /8 + +// Time Tick (Hz, not applicable for BFTM) <1-1000000:100> +// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM. +*/ +#if (0) // Enable HT32 Time Function +#define HTCFG_TIME_IPSEL (0) +#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC) +#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input) +#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8) +#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM +#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM. +/* + + Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) + HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV) + where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second + (Interrupt Time is not applicable for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second) +*/ +#endif +/* +// +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file (this file). +*/ +/* +// Enable User Define HSE Value +// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h". +// HSE Value (Hz) +*/ +#if (0) +#define HSE_VALUE 16000000 +#endif +/* +// +*/ + +/* +// Enable CKOUT Function +*/ +#define ENABLE_CKOUT 0 + +/* +// Enable Get CK_ADC of "CKCU_GetClocksFrequency()" +// Enable ADC0_Freq and ADC1_Freq of the "CKCU_GetClocksFrequency()" function. It required the division calculation (by C Library) and increased the code size. +*/ +#define HT32_LIB_ENABLE_GET_CK_ADC 0 + +/* The DEBUG definition to enter debug mode for library */ +/* +// Library Debug Mode +*/ +#define HT32_LIB_DEBUG 0 + + +/* Enable/disable the specific peripheral inclusion */ + +// Library Inclusion Configuration +/* ADC -----------------------------------------------------------------------------------------------------*/ +/* +// ADC Library +*/ +#define _ADC 1 + +/* AES -----------------------------------------------------------------------------------------------------*/ +/* +// AES Library +*/ +#define _AES 1 + +/* BFTM ----------------------------------------------------------------------------------------------------*/ +/* +// BFTM Library +*/ +#define _BFTM 1 + +/* CAN -----------------------------------------------------------------------------------------------------*/ +/* +// CAN Library +*/ +#define _CAN 1 + +/* Clock Control -------------------------------------------------------------------------------------------*/ +/* +// Clock Control Library +*/ +#define _CKCU 1 + +/* Comparator ----------------------------------------------------------------------------------------------*/ +/* +// Comparator Library +*/ +#define _CMP 1 + +/* CRC -----------------------------------------------------------------------------------------------------*/ +/* +// CRC Library +*/ +#define _CRC 1 + +/* DAC -----------------------------------------------------------------------------------------------------*/ +/* +// DAC Library +*/ +#define _DAC 1 + +/* DAC Dual 16-bit -----------------------------------------------------------------------------------------*/ +/* +// DAC_Dual16 Library +*/ +#define _DAC_DUAL16 1 + +/* DIV -----------------------------------------------------------------------------------------------------*/ +/* +// DIV Library +*/ +#define _DIV 1 + +/* EBI -----------------------------------------------------------------------------------------------------*/ +/* +// EBI Library +*/ +#define _EBI 1 + +/* EXTI ----------------------------------------------------------------------------------------------------*/ +/* +// EXTI Library +*/ +#define _EXTI 1 + +/* Flash ---------------------------------------------------------------------------------------------------*/ +/* +// Flash Library +*/ +#define _FLASH 1 + +/* GPIO ----------------------------------------------------------------------------------------------------*/ +/* +// GPIO Library +*/ +#define _GPIO 1 + +/* GPTM ----------------------------------------------------------------------------------------------------*/ +/* +// GPTM Library +*/ +#define _GPTM 1 + +/* I2C -----------------------------------------------------------------------------------------------------*/ +/* +// I2C Library +*/ +#define _I2C 1 + +/* I2S -----------------------------------------------------------------------------------------------------*/ +/* +// I2S Library +*/ +#define _I2S 1 + +/* LCD -----------------------------------------------------------------------------------------------------*/ +/* +// LCD Library +*/ +#define _LCD 1 + +/* LEDC ----------------------------------------------------------------------------------------------------*/ +/* +// LEDC Library +*/ +#define _LEDC 1 + +/* MCTM ----------------------------------------------------------------------------------------------------*/ +/* +// MCTM Library +*/ +#define _MCTM 1 + +/* MIDI ----------------------------------------------------------------------------------------------------*/ +/* +// MIDI Library +*/ +#define _MIDI 1 + +/* OPA -----------------------------------------------------------------------------------------------------*/ +/* +// OPA +*/ +#define _OPA 1 + +/* PDMA ----------------------------------------------------------------------------------------------------*/ +/* +// PDMA Library +*/ +#define _PDMA 1 + +/* PWM -----------------------------------------------------------------------------------------------------*/ +/* +// PWM Library +*/ +#define _PWM 1 + +/* PWRCU ---------------------------------------------------------------------------------------------------*/ +/* +// PWRCU Library +*/ +#define _PWRCU 1 + +/* RSTCU ---------------------------------------------------------------------------------------------------*/ +/* +// RSTCU Library +*/ +#define _RSTCU 1 + +/* RTC -----------------------------------------------------------------------------------------------------*/ +/* +// RTC Library +*/ +#define _RTC 1 + +/* SCI -----------------------------------------------------------------------------------------------------*/ +/* +// SCI Library +*/ +#define _SCI 1 + +/* SCTM ----------------------------------------------------------------------------------------------------*/ +/* +// SCTM Library +*/ +#define _SCTM 1 + +/* SLED ----------------------------------------------------------------------------------------------------*/ +/* +// SLED Library +*/ +#define _SLED 1 + +/* SPI -----------------------------------------------------------------------------------------------------*/ +/* +// SPI Library +*/ +#define _SPI 1 + +/* TKEY ----------------------------------------------------------------------------------------------------*/ +/* +// TKEY Library +*/ +#define _TKEY 1 + +/* USART ---------------------------------------------------------------------------------------------------*/ +/* +// USART/UART Library +*/ +#define _USART 1 + +/* USBD ----------------------------------------------------------------------------------------------------*/ +/* +// USB Library +*/ +#define _USB 1 + +/* WDT -----------------------------------------------------------------------------------------------------*/ +/* +// WDT Library +*/ +#define _WDT 1 + +/* Misc ----------------------------------------------------------------------------------------------------*/ +/* +// Misc Library +*/ +#define _MISC 1 + +/* Serial --------------------------------------------------------------------------------------------------*/ +/* +// Serial Library +*/ +#define _SERIAL 1 + +/* Software DIV --------------------------------------------------------------------------------------------*/ +/* +// Software Divider Library +*/ +#define _SWDIV 1 + +/* Software Random Number ----------------------------------------------------------------------------------*/ +/* +// Software Random Number Library +*/ +#define _SWRAND 1 + + +// + +#endif diff --git a/bsp/ht32/ht32f53252/board/linker_scripts/link.icf b/bsp/ht32/ht32f53252/board/linker_scripts/link.icf new file mode 100644 index 0000000000..65c2bfc8b7 --- /dev/null +++ b/bsp/ht32/ht32f53252/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/ht32/ht32f53252/board/linker_scripts/link.lds b/bsp/ht32/ht32f53252/board/linker_scripts/link.lds new file mode 100644 index 0000000000..27269dd77e --- /dev/null +++ b/bsp/ht32/ht32f53252/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for AT32 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ht32/ht32f53252/board/linker_scripts/link.sct b/bsp/ht32/ht32f53252/board/linker_scripts/link.sct new file mode 100644 index 0000000000..ece577cb3e --- /dev/null +++ b/bsp/ht32/ht32f53252/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0001FE00 { ; load region size_region + ER_IROM1 0x00000000 0x0001FE00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ht32/ht32f53252/board/src/board.c b/bsp/ht32/ht32f53252/board/src/board.c new file mode 100644 index 0000000000..e0160468e9 --- /dev/null +++ b/bsp/ht32/ht32f53252/board/src/board.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "board.h" + +/* This feature will initialize the HT32 chip clock */ +void rt_hw_board_clock_init(void) +{ + +} diff --git a/bsp/ht32/ht32f53252/board/src/ht32_msp.c b/bsp/ht32/ht32f53252/board/src/ht32_msp.c new file mode 100644 index 0000000000..6d57bd4d4b --- /dev/null +++ b/bsp/ht32/ht32f53252/board/src/ht32_msp.c @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "ht32_msp.h" + +/* GPIO configuration for UART */ +#ifdef BSP_USING_UART +void ht32_usart_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance; +#ifdef BSP_USING_USART0 + if (HT_USART0 == usart_x) + { + CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT, HTCFG_USART0_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID, HTCFG_USART0_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID, HTCFG_USART0_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_USART1 + if (HT_USART1 == usart_x) + { + CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT, HTCFG_USART1_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID, HTCFG_USART1_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID, HTCFG_USART1_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART0 + if (HT_UART0 == usart_x) + { + CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT, HTCFG_UART0_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID, HTCFG_UART0_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID, HTCFG_UART0_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART1 + if (HT_UART1 == usart_x) + { + CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT, HTCFG_UART1_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID, HTCFG_UART1_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID, HTCFG_UART1_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +} +#endif + +/* GPIO configuration for SPI */ +#ifdef BSP_USING_SPI +void ht32_spi_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance; +#ifdef BSP_USING_SPI0 + if (HT_SPI0 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +#ifdef BSP_USING_SPI1 + if (HT_SPI1 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +} +#endif + +/* GPIO configuration for I2C */ +#ifdef BSP_USING_I2C_HW +void ht32_hardware_i2c_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance; +#ifdef BSP_USING_I2C0_HW + if (HT_I2C0 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID, HTCFG_I2C0_SCL_GPIO_PIN, AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID, HTCFG_I2C0_SDA_GPIO_PIN, AFIO_FUN_I2C); + } +#endif +#ifdef BSP_USING_I2C1_HW + if (HT_I2C1 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID, HTCFG_I2C1_SCL_GPIO_PIN, AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID, HTCFG_I2C1_SDA_GPIO_PIN, AFIO_FUN_I2C); + } +#endif +} +#endif + +/* GPIO configuration for ADC */ +#ifdef BSP_USING_ADC +void ht32_adc_gpio_init(void *instance,int8_t channel) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + HT_ADC_TypeDef *adc_x = (HT_ADC_TypeDef *)instance; +#ifdef BSP_USING_ADC0 + if (HT_ADC0 == adc_x) + { + /* Enable peripheral clock */ + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.ADC0 = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* Configure AFIO mode as ADC function */ + switch(channel) + { + case 0: + AFIO_GPxConfig(HTCFG_ADC0CH0_GPIO_ID, HTCFG_ADC0CH0_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 1: + AFIO_GPxConfig(HTCFG_ADC0CH1_GPIO_ID, HTCFG_ADC0CH1_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 2: + AFIO_GPxConfig(HTCFG_ADC0CH2_GPIO_ID, HTCFG_ADC0CH2_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 3: + AFIO_GPxConfig(HTCFG_ADC0CH3_GPIO_ID, HTCFG_ADC0CH3_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 4: + AFIO_GPxConfig(HTCFG_ADC0CH4_GPIO_ID, HTCFG_ADC0CH4_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 5: + AFIO_GPxConfig(HTCFG_ADC0CH5_GPIO_ID, HTCFG_ADC0CH5_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 6: + AFIO_GPxConfig(HTCFG_ADC0CH6_GPIO_ID, HTCFG_ADC0CH6_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 7: + AFIO_GPxConfig(HTCFG_ADC0CH7_GPIO_ID, HTCFG_ADC0CH7_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 8: + AFIO_GPxConfig(HTCFG_ADC0CH8_GPIO_ID, HTCFG_ADC0CH8_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 9: + AFIO_GPxConfig(HTCFG_ADC0CH9_GPIO_ID, HTCFG_ADC0CH9_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 10: + AFIO_GPxConfig(HTCFG_ADC0CH10_GPIO_ID, HTCFG_ADC0CH10_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 11: + AFIO_GPxConfig(HTCFG_ADC0CH11_GPIO_ID, HTCFG_ADC0CH11_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 12: + AFIO_GPxConfig(HTCFG_ADC0CH12_GPIO_ID, HTCFG_ADC0CH12_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 13: + AFIO_GPxConfig(HTCFG_ADC0CH13_GPIO_ID, HTCFG_ADC0CH13_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 14: + AFIO_GPxConfig(HTCFG_ADC0CH14_GPIO_ID, HTCFG_ADC0CH14_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 15: + AFIO_GPxConfig(HTCFG_ADC0CH15_GPIO_ID, HTCFG_ADC0CH15_AFIO_PIN, AFIO_FUN_ADC0); + break; + default: + break; + } + } +#endif +#ifdef BSP_USING_ADC1 + if (HT_ADC1 == adc_x) + { + /* Enable peripheral clock */ + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.ADC1 = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* Configure AFIO mode as ADC function */ + switch(channel) + { + case 0: + AFIO_GPxConfig(HTCFG_ADC1CH0_GPIO_ID, HTCFG_ADC1CH0_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 1: + AFIO_GPxConfig(HTCFG_ADC1CH1_GPIO_ID, HTCFG_ADC1CH1_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 2: + AFIO_GPxConfig(HTCFG_ADC1CH2_GPIO_ID, HTCFG_ADC1CH2_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 3: + AFIO_GPxConfig(HTCFG_ADC1CH3_GPIO_ID, HTCFG_ADC1CH3_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 4: + AFIO_GPxConfig(HTCFG_ADC1CH4_GPIO_ID, HTCFG_ADC1CH4_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 5: + AFIO_GPxConfig(HTCFG_ADC1CH5_GPIO_ID, HTCFG_ADC1CH5_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 6: + AFIO_GPxConfig(HTCFG_ADC1CH6_GPIO_ID, HTCFG_ADC1CH6_AFIO_PIN, AFIO_FUN_ADC0); + break; + case 7: + AFIO_GPxConfig(HTCFG_ADC1CH7_GPIO_ID, HTCFG_ADC1CH7_AFIO_PIN, AFIO_FUN_ADC0); + break; + default: + break; + } + } +#endif +} +#endif +/* GPIO configuration for ADC */ +#ifdef BSP_USING_CAN +void ht32_can_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + HT_CAN_TypeDef *can_x = (HT_CAN_TypeDef *)instance; + + if (HT_CAN0 == can_x) + { + CKCUClock.Bit.HTCFG_CAN_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_CAN_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to CAN mode */ + AFIO_GPxConfig(HTCFG_CAN_TX_GPIO_ID, HTCFG_CAN_TX_GPIO_PIN, AFIO_FUN_CAN); + AFIO_GPxConfig(HTCFG_CAN_RX_GPIO_ID, HTCFG_CAN_RX_GPIO_PIN, AFIO_FUN_CAN); + } + +} +#endif + + diff --git a/bsp/ht32/ht32f53252/figures/board.jpg b/bsp/ht32/ht32f53252/figures/board.jpg new file mode 100644 index 0000000000000000000000000000000000000000..8905a38e996a27915bcd2d39c449dbf590d1bf45 GIT binary patch literal 477663 zcmd>n2V7HE|M$5W1R~p@fPi61f{PK9AYhONLLiU%*u8cn9;pXAxQLXpRyovS^UB&3CosD&0LT&)qRTFRNy-^Gi5=-rwcR4@e3D;mioCoJo=3b zS(NDKGTV#e#z_fWC={`>(iRG`!Xp#1K24w}y3F)9BKl_fWG+crvM^%-IdjS4rRhGI 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### uVision Project, (C) Keil Software
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b/bsp/ht32/ht32f53252/project.uvprojx @@ -0,0 +1,2234 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F53252 + Holtek + Holtek.HT32_DFP.1.0.55 + https://mcu.holtek.com.tw/pack + IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0001FBFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") + + "STARTUP\Holtek\HT32F5xxxx\startup_ht32f53242_52.s" ("Holtek HT32F5xxxx Startup Code") + UL2CM3(-O142 -S0 -C0 -FO7 -FD20000000 -FC800 -FN2 -FF0HT32F -FS00 -FL01FC00 -FF1HT32F_OPT -FS11FF00000 -FL1400) + 0 + HT32F5xxxx_01.h + + + + + + + + + + SFD\Holtek\HT32F5xxxx\HT32F53242_52.SFR + 0 + 0 + + + + Holtek\HT32F5xxxx\ + Holtek\HT32F5xxxx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x1fc00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x1fc00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, USE_HT32F53252_SK, USE_HT32F53242_52, USE_MEM_HT32F53252, __RTTHREAD__, RT_USING_LIBC + + ..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\HT32_STD_5xxxx_FWLib\library\CMSIS\Include;..\..\..\components\drivers\phy;..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Include;..\..\..\components\drivers\include;.;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\finsh;board\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\libraries\ht32_drivers;applications;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\smp_call;..\..\..\components\drivers\include;..\libraries\usbd_library\inc;..\..\..\components\libc\compilers\common\extension;..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\inc;..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 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1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_div.c + + + ht32f5xxxx_pwrcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c + + + ht32f5xxxx_i2c.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2c.c + + + ht32f5xxxx_cmp.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c + + + ht32f5xxxx_pdma.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c + + + ht32f5xxxx_can.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_can.c + + + ht32f5xxxx_crc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_crc.c + + + ht32f5xxxx_rtc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c + + + ht32f5xxxx_mctm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c + + + ht32f5xxxx_adc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c + + + system_ht32f5xxxx_15.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\system_ht32f5xxxx_15.c + + + ht32f5xxxx_exti.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c + + + ht32f5xxxx_rstcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c + + + ht32f5xxxx_spi.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_spi.c + + + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f53252/rtconfig.h b/bsp/ht32/ht32f53252/rtconfig.h new file mode 100644 index 0000000000..54fac2e6db --- /dev/null +++ b/bsp/ht32/ht32f53252/rtconfig.h @@ -0,0 +1,394 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "usart1" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 32 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HT32 +#define SOC_SERIES_HT32F5 + +/* Hardware Drivers Config */ + +/* Chip Configuration */ + +#define SOC_KERNEL +#define CORTEX_M0 +#define SOC_HT32F53252 +/* end of Chip Configuration */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_USART1 +#define BSP_USING_USART1_NAME "usart1" +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/ht32/ht32f53252/rtconfig.py b/bsp/ht32/ht32f53252/rtconfig.py new file mode 100644 index 0000000000..6f853dccc2 --- /dev/null +++ b/bsp/ht32/ht32f53252/rtconfig.py @@ -0,0 +1,152 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='keil' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' +# EXEC_PATH = r'D:\keil5\keil_v532\UV4' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + CFLAGS += ' -D USE_HT32F53242_52' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ht32/ht32f53252/template.uvoptx b/bsp/ht32/ht32f53252/template.uvoptx new file mode 100644 index 0000000000..dd685d044b --- /dev/null +++ b/bsp/ht32/ht32f53252/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F53252$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F53252$ARM\Flash\HT32F_OPT.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S8 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN2 -FF0HT32F -FS00 -FL01FC00 -FF1HT32F_OPT -FS11FF00000 -FL1400 + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f53252/template.uvprojx b/bsp/ht32/ht32f53252/template.uvprojx new file mode 100644 index 0000000000..f799045dfb --- /dev/null +++ b/bsp/ht32/ht32f53252/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + + + HT32F53252 + Holtek + Holtek.HT32_DFP.1.0.55 + https://mcu.holtek.com.tw/pack + IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0001FBFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") + + "STARTUP\Holtek\HT32F5xxxx\startup_ht32f53242_52.s" ("Holtek HT32F5xxxx Startup Code") + UL2CM3(-O142 -S0 -C0 -FO7 -FD20000000 -FC800 -FN2 -FF0HT32F -FS00 -FL01FC00 -FF1HT32F_OPT -FS11FF00000 -FL1400) + 0 + HT32F5xxxx_01.h + + + + + + + + + + SFD\Holtek\HT32F5xxxx\HT32F53242_52.SFR + 0 + 0 + + + + Holtek\HT32F5xxxx\ + Holtek\HT32F5xxxx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x1fc00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x1fc00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=28 + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ht32/libraries/.ignore_format.yml b/bsp/ht32/libraries/.ignore_format.yml index 65b2f1a156..265fe03243 100644 --- a/bsp/ht32/libraries/.ignore_format.yml +++ b/bsp/ht32/libraries/.ignore_format.yml @@ -5,3 +5,4 @@ dir_path: - HT32_STD_1xxxx_FWLib - HT32_STD_5xxxx_FWLib +- usbd_library \ No newline at end of file diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt index 20ad57f3fc..322af83bff 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file Release_Notes.txt - * @version V1.4.1 - * @date 2023-10-31 + * @version V1.5.1 + * @date 2023-11-08 * @brief The Release notes of HT32 Firmware Library. ************************************************************************************************************* * @attention @@ -34,6 +34,83 @@ // HT32F12365, HT32F12366 // HT32F22366 +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.5.1_3190 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-11-08 + + Main Changes + + Add new examples: + - "Tips/Checksum_CRC16" + - "Tips/StackOnTop" + + Add HT32 Stack Usage Analysis feature. + - Modify "ht32f1xxxx_conf.h", add "HTCFG_STACK_USAGE_ANALYSIS" setting for enabling HT32 Stack Usage + Analysis. + - Update project templates and "ht32_cm3_misc.c/.h", add "StackUsageAnalysisInit()" function to + initialize stack. + - Update project files, add HT32 Stack Usage Analysis component viewer. + - Update and sync "startup_ht32f1xxxx_nn.s" for the "Stack On Top" and "Stack Usage Analysis" feature." + - Add "USE_LIBCFG_RAM_SIZE" define in Keil project files for the "Stack On Top" feature. + + Rename WDT parameters. + - Old Name | New Name + - --------------------------------- | ---------------------------- + - "MODE0_WDTSHLT_BOTH" | "WDT_SLEEP_HALT_NONE" + - "MODE0_WDTSHLT_SLEEP" | "WDT_SLEEP_HALT_DEEPSLEEP" + - "MODE0_WDTSHLT_SLEEP" | "WDT_SLEEP_HALT_ALL" + + Fix "AES_SetKeyTable()" and "AES_SetVectorTable()" Key and Vector index errors, which cause incorrect AES + encryption and decryption. + + Update example, add "__ALIGN4" to variables and enforced type conversion for 4 bytes read/write API calls. + - "AES/CBC" + - "AES/CTR" + - "AES/ECB" + + Modify "ht32f5xxxx_01.h", fix the MCTM alias mismatch. + - "MCTMn_IRQHandler" alias from "MCTM0_G_IRQHandler" to "MCTM0_UP_IRQHandler" + + Update USB example, add the process of detecting USB bus status before USBDCore_LowPower(). + - "CKCU/HSI_AutoTrim_By_USB" + - "USBD/*" + + Improve the thread-safe capability of "utilities/common/ring_buffer.c". + + Modify "ht32f1xxxx_01.h" to add alignment and packing attributes for ARM compiler versions, with GCC fallback. + + Update "ht32f1xxxx_rtc.c", modify the RTC_LSECmd() related flow. + + Modify "WDT/Auto_Enable" example to change the mechanism of the example. + + Update "ht32f12366_sk.h" to share EBI_BL pin with LED3. + + Others + + Update comment, format, typing error, and coding style. + + Update project related file and setting. + + Update CKCU API. Enhanced program stability with robustness settings for parameter "PCLKPrescaler" + in "CKCU_SetPeripPrescaler(..., CKCU_APBCLKPRE_TypeDef PCLKPrescaler)". + + Modify "void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x);". Changed parameter name from + "RemapMode" to "FLASH_BOOT_x". + + Update "SPI_DUALCmd()" and "SPI_SoftwareSELCmd()" make sure the SPI Bus is not busy + before changing the settings. + + Modify "ht32_dependency.h",to change the preprocessors for dependency check. + + Update the following middleware. + "utilities/middleware/eeprom_emulation.c" + "utilities/middleware/i2c_master.c" + "utilities/middleware/i2c_master.h" + "utilities/middleware/spi_module.c" + "utilities/middleware/spi_module.h" + "utilities/middleware/spi_module_config_templet.h" + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Update AES examples. + - Change the key, IV, and plain text from hex array to string, making the result easier to compare with + online tools. + - Add expected cipher text and compare it with the MCU's H/W AES result as an error-proofing mechanism." + + Update the following readme file. + - "CKCU/CKCU_HSI_AutoTrim_By_USB" + - "CKCU/CKCU_HSI_AutoTrim_By_LSE" + - "USBD/*" + + Modify "afterbuild.bat" to add logic to use ARMCC or ARMCLANG fromelf tool based on available toolchain. + + Add "_ProjectConfig.ini" in the "CKCU/HSI_AutoTrim_By_LSE" example. + + Update "project_template/Script" for improving script mechanism. + - "Script/_CreateProjectConfScript.bat" + - "Script/_CreateProjectScript.bat" + - "Script/_ht32_ic_name.ini" + + Update e-Link32 Pro/Lite Command line tool as "V1.20" ("utilities/elink32pro/eLink32pro.exe"). + + Change path of the "Holtek.HT32_DFP.latest.pack". + + /*----------------------------------------------------------------------------------------------------------*/ /* HT32_STD_1xxxx_FWLib_V1.4.1_2982 */ /*----------------------------------------------------------------------------------------------------------*/ @@ -45,9 +122,9 @@ + Modify examples below, add volatile qualifiers on some variables (in the for loop usage) to fix the Arm Compiler Version 6 optimization issue. ("u32" to "vu32", unsigned int to volatile unsigned int). - - “PWRCU/PowerDown_WAKEUPPin” - - “PWRCU/PowerDown_RTC” - - “TM/PWM” + - "PWRCU/PowerDown_WAKEUPPin" + - "PWRCU/PowerDown_RTC" + - "TM/PWM" + Modify examples below, use separate "if" statements instead of "if-else" to avoid double-entry ISR. - "PWRCU/DeepSleepMode1" - "PWRCU/DeepSleepMode2" diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript index ef04fa4fa9..7e3699bd21 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript @@ -2,37 +2,11 @@ import os import sys import rtconfig from building import * - -def get_source(ic_model, file_path, system_path, base_path): - source_path = [] - files_list = [] - readafter = 0 - if not os.path.isfile(file_path): - return - - with open(file_path, 'r') as file: - # content = file.read() - for line in file: - if readafter == 2 and line.find('>') != -1: - break - if readafter == 2: - files_list.append(line.strip()) - if line.find(ic_model) != -1: - readafter = 1 - if readafter == 1 and line.find('<') != -1: - readafter = 2 - for line in files_list: - if line.find('system') != -1: - source_path.append(os.path.join(system_path, line.strip())) - else: - source_path.append(os.path.join(base_path, line.strip())) - return source_path - Import('rtconfig') tools_path = os.path.normpath(os.getcwd() + '../../..' + '/tools') sys.path.append(tools_path) - +from sdk_dist import get_source source_file_path = os.path.join(os.getcwd(), 'Source_file') base_path = 'library/HT32F1xxxx_Driver/src/' diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h index f2bcf5de2a..d8500195d4 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h @@ -1,8 +1,8 @@ /***************************************************************************//** * @file ht32f1xxxx_01.h * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * @version $Rev:: 2914 $ - * @date $Date:: 2023-05-18 #$ + * @version $Rev:: 3097 $ + * @date $Date:: 2024-06-20 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -156,14 +156,14 @@ typedef enum IRQn #endif ADC0_IRQn = 25, /*!< ADC Interrupt */ #if !defined(USE_HT32F12364) - MCTM0BRK_IRQn = 27, /*!< MCTM0 BRK interrupt */ - MCTM0UP_IRQn = 28, /*!< MCTM0 UP interrupt */ - MCTM0TR_IRQn = 29, /*!< MCTM0 TR interrupt */ - MCTM0CC_IRQn = 30, /*!< MCTM0 CC interrupt */ - MCTM1BRK_IRQn = 31, /*!< MCTM1 BRK interrupt */ - MCTM1UP_IRQn = 32, /*!< MCTM1 UP interrupt */ - MCTM1TR_IRQn = 33, /*!< MCTM1 TR interrupt */ - MCTM1CC_IRQn = 34, /*!< MCTM1 CC interrupt */ + MCTM0_BRK_IRQn = 27, /*!< MCTM0 BRK interrupt */ + MCTM0_UP_IRQn = 28, /*!< MCTM0 UP interrupt */ + MCTM0_TR_IRQn = 29, /*!< MCTM0 TR interrupt */ + MCTM0_CC_IRQn = 30, /*!< MCTM0 CC interrupt */ + MCTM1_BRK_IRQn = 31, /*!< MCTM1 BRK interrupt */ + MCTM1_UP_IRQn = 32, /*!< MCTM1 UP interrupt */ + MCTM1_TR_IRQn = 33, /*!< MCTM1 TR interrupt */ + MCTM1_CC_IRQn = 34, /*!< MCTM1 CC interrupt */ #endif GPTM0_IRQn = 35, /*!< General-Purpose Timer0 Interrupt */ #if !defined(USE_HT32F12364) @@ -223,10 +223,10 @@ typedef enum IRQn #endif } IRQn_Type; -#define MCTM0_IRQn MCTM0UP_IRQn -#define MCTM0_IRQHandler MCTM0UP_IRQHandler -#define MCTM1_IRQn MCTM1UP_IRQn -#define MCTM1_IRQHandler MCTM1UP_IRQHandler +#define MCTM0_IRQn MCTM0_UP_IRQn +#define MCTM0_IRQHandler MCTM0_UP_IRQHandler +#define MCTM1_IRQn MCTM1_UP_IRQn +#define MCTM1_IRQHandler MCTM1_UP_IRQHandler /** @@ -303,13 +303,18 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #if defined (__CC_ARM) #define __ALIGN4 __align(4) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #define __ALIGN4 __attribute__((aligned(4))) #elif defined (__ICCARM__) #define __ALIGN4 _Pragma("data_alignment = 4") #elif defined (__GNUC__) #define __ALIGN4 __attribute__((aligned(4))) #endif -#if defined (__GNUC__) +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #define __PACKED_H + #define __PACKED_F __attribute__ ((packed)) +#elif defined (__GNUC__) #define __PACKED_H #define __PACKED_F __attribute__ ((packed)) #elif defined (__ICCARM__) || (__CC_ARM) diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s index f3f24a1faf..aaea73066f 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_01.s -; Version : $Rev:: 2524 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 3052 $ +; Date : $Date:: 2024-02-26 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -49,13 +49,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-131072:8> Heap_Size EQU 0 @@ -125,14 +136,14 @@ __Vectors DCD COMP_IRQHandler ; 24, 40, 0x0A0, DCD ADC_IRQHandler ; 25, 41, 0x0A4, DCD _RESERVED ; 26, 42, 0x0A8, - DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, - DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, - DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, - DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, - DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, - DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, - DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, - DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD MCTM0_BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0_UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0_TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0_CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1_BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1_UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1_TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1_CC_IRQHandler ; 34, 50, 0x0C8, DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, DCD _RESERVED ; 37, 53, 0x0D4, @@ -330,14 +341,14 @@ Default_Handler PROC EXPORT EXTI15_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] - EXPORT MCTM0BRK_IRQHandler [WEAK] - EXPORT MCTM0UP_IRQHandler [WEAK] - EXPORT MCTM0TR_IRQHandler [WEAK] - EXPORT MCTM0CC_IRQHandler [WEAK] - EXPORT MCTM1BRK_IRQHandler [WEAK] - EXPORT MCTM1UP_IRQHandler [WEAK] - EXPORT MCTM1TR_IRQHandler [WEAK] - EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT MCTM1_BRK_IRQHandler [WEAK] + EXPORT MCTM1_UP_IRQHandler [WEAK] + EXPORT MCTM1_TR_IRQHandler [WEAK] + EXPORT MCTM1_CC_IRQHandler [WEAK] EXPORT GPTM0_IRQHandler [WEAK] EXPORT GPTM1_IRQHandler [WEAK] EXPORT BFTM0_IRQHandler [WEAK] @@ -395,14 +406,14 @@ EXTI14_IRQHandler EXTI15_IRQHandler COMP_IRQHandler ADC_IRQHandler -MCTM0BRK_IRQHandler -MCTM0UP_IRQHandler -MCTM0TR_IRQHandler -MCTM0CC_IRQHandler -MCTM1BRK_IRQHandler -MCTM1UP_IRQHandler -MCTM1TR_IRQHandler -MCTM1CC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_IRQHandler +MCTM0_CC_IRQHandler +MCTM1_BRK_IRQHandler +MCTM1_UP_IRQHandler +MCTM1_TR_IRQHandler +MCTM1_CC_IRQHandler GPTM0_IRQHandler GPTM1_IRQHandler BFTM0_IRQHandler @@ -442,10 +453,11 @@ AES_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -456,14 +468,22 @@ AES_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN ENDIF - END + END \ No newline at end of file diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s index a1a24ab522..dd77afac01 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_03.s -; Version : $Rev:: 2524 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 3052 $ +; Date : $Date:: 2024-02-26 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,13 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-131072:8> Heap_Size EQU 0 @@ -366,10 +377,11 @@ AES_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -380,11 +392,19 @@ AES_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s index 3381f58240..0ee3a5b64d 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_01.s -; Version : $Rev:: 2524 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 3052 $ +; Date : $Date:: 2024-02-26 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -49,13 +49,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-131072:8> Heap_Size EQU 0 @@ -125,14 +136,14 @@ __Vectors DCD COMP_IRQHandler ; 24, 40, 0x0A0, DCD ADC_IRQHandler ; 25, 41, 0x0A4, DCD _RESERVED ; 26, 42, 0x0A8, - DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, - DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, - DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, - DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, - DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, - DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, - DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, - DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD MCTM0_BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0_UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0_TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0_CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1_BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1_UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1_TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1_CC_IRQHandler ; 34, 50, 0x0C8, DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, DCD _RESERVED ; 37, 53, 0x0D4, @@ -330,14 +341,14 @@ Default_Handler PROC EXPORT EXTI15_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] - EXPORT MCTM0BRK_IRQHandler [WEAK] - EXPORT MCTM0UP_IRQHandler [WEAK] - EXPORT MCTM0TR_IRQHandler [WEAK] - EXPORT MCTM0CC_IRQHandler [WEAK] - EXPORT MCTM1BRK_IRQHandler [WEAK] - EXPORT MCTM1UP_IRQHandler [WEAK] - EXPORT MCTM1TR_IRQHandler [WEAK] - EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT MCTM1_BRK_IRQHandler [WEAK] + EXPORT MCTM1_UP_IRQHandler [WEAK] + EXPORT MCTM1_TR_IRQHandler [WEAK] + EXPORT MCTM1_CC_IRQHandler [WEAK] EXPORT GPTM0_IRQHandler [WEAK] EXPORT GPTM1_IRQHandler [WEAK] EXPORT BFTM0_IRQHandler [WEAK] @@ -395,14 +406,14 @@ EXTI14_IRQHandler EXTI15_IRQHandler COMP_IRQHandler ADC_IRQHandler -MCTM0BRK_IRQHandler -MCTM0UP_IRQHandler -MCTM0TR_IRQHandler -MCTM0CC_IRQHandler -MCTM1BRK_IRQHandler -MCTM1UP_IRQHandler -MCTM1TR_IRQHandler -MCTM1CC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_IRQHandler +MCTM0_CC_IRQHandler +MCTM1_BRK_IRQHandler +MCTM1_UP_IRQHandler +MCTM1_TR_IRQHandler +MCTM1_CC_IRQHandler GPTM0_IRQHandler GPTM1_IRQHandler BFTM0_IRQHandler @@ -442,10 +453,11 @@ AES_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -456,14 +468,22 @@ AES_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN ENDIF - END + END \ No newline at end of file diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s index 9a0fd83e61..f4c626c658 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_01.s -; Version : $Rev:: 2524 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 3052 $ +; Date : $Date:: 2024-02-26 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -49,13 +49,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-131072:8> Heap_Size EQU 0 @@ -125,14 +136,14 @@ __Vectors DCD COMP_IRQHandler ; 24, 40, 0x0A0, DCD ADC_IRQHandler ; 25, 41, 0x0A4, DCD _RESERVED ; 26, 42, 0x0A8, - DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, - DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, - DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, - DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, - DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, - DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, - DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, - DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD MCTM0_BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0_UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0_TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0_CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1_BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1_UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1_TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1_CC_IRQHandler ; 34, 50, 0x0C8, DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, DCD _RESERVED ; 37, 53, 0x0D4, @@ -330,14 +341,14 @@ Default_Handler PROC EXPORT EXTI15_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] - EXPORT MCTM0BRK_IRQHandler [WEAK] - EXPORT MCTM0UP_IRQHandler [WEAK] - EXPORT MCTM0TR_IRQHandler [WEAK] - EXPORT MCTM0CC_IRQHandler [WEAK] - EXPORT MCTM1BRK_IRQHandler [WEAK] - EXPORT MCTM1UP_IRQHandler [WEAK] - EXPORT MCTM1TR_IRQHandler [WEAK] - EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT MCTM1_BRK_IRQHandler [WEAK] + EXPORT MCTM1_UP_IRQHandler [WEAK] + EXPORT MCTM1_TR_IRQHandler [WEAK] + EXPORT MCTM1_CC_IRQHandler [WEAK] EXPORT GPTM0_IRQHandler [WEAK] EXPORT GPTM1_IRQHandler [WEAK] EXPORT BFTM0_IRQHandler [WEAK] @@ -395,14 +406,14 @@ EXTI14_IRQHandler EXTI15_IRQHandler COMP_IRQHandler ADC_IRQHandler -MCTM0BRK_IRQHandler -MCTM0UP_IRQHandler -MCTM0TR_IRQHandler -MCTM0CC_IRQHandler -MCTM1BRK_IRQHandler -MCTM1UP_IRQHandler -MCTM1TR_IRQHandler -MCTM1CC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_IRQHandler +MCTM0_CC_IRQHandler +MCTM1_BRK_IRQHandler +MCTM1_UP_IRQHandler +MCTM1_TR_IRQHandler +MCTM1_CC_IRQHandler GPTM0_IRQHandler GPTM1_IRQHandler BFTM0_IRQHandler @@ -442,10 +453,11 @@ AES_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -456,14 +468,22 @@ AES_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN ENDIF - END + END \ No newline at end of file diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s index 481edd75d0..aa08b6c860 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_01.s -; Version : $Rev:: 2524 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 3052 $ +; Date : $Date:: 2024-02-26 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -49,13 +49,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-131072:8> Heap_Size EQU 0 @@ -125,14 +136,14 @@ __Vectors DCD COMP_IRQHandler ; 24, 40, 0x0A0, DCD ADC_IRQHandler ; 25, 41, 0x0A4, DCD _RESERVED ; 26, 42, 0x0A8, - DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, - DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, - DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, - DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, - DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, - DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, - DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, - DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD MCTM0_BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0_UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0_TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0_CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1_BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1_UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1_TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1_CC_IRQHandler ; 34, 50, 0x0C8, DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, DCD _RESERVED ; 37, 53, 0x0D4, @@ -330,14 +341,14 @@ Default_Handler PROC EXPORT EXTI15_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] - EXPORT MCTM0BRK_IRQHandler [WEAK] - EXPORT MCTM0UP_IRQHandler [WEAK] - EXPORT MCTM0TR_IRQHandler [WEAK] - EXPORT MCTM0CC_IRQHandler [WEAK] - EXPORT MCTM1BRK_IRQHandler [WEAK] - EXPORT MCTM1UP_IRQHandler [WEAK] - EXPORT MCTM1TR_IRQHandler [WEAK] - EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT MCTM1_BRK_IRQHandler [WEAK] + EXPORT MCTM1_UP_IRQHandler [WEAK] + EXPORT MCTM1_TR_IRQHandler [WEAK] + EXPORT MCTM1_CC_IRQHandler [WEAK] EXPORT GPTM0_IRQHandler [WEAK] EXPORT GPTM1_IRQHandler [WEAK] EXPORT BFTM0_IRQHandler [WEAK] @@ -395,14 +406,14 @@ EXTI14_IRQHandler EXTI15_IRQHandler COMP_IRQHandler ADC_IRQHandler -MCTM0BRK_IRQHandler -MCTM0UP_IRQHandler -MCTM0TR_IRQHandler -MCTM0CC_IRQHandler -MCTM1BRK_IRQHandler -MCTM1UP_IRQHandler -MCTM1TR_IRQHandler -MCTM1CC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_IRQHandler +MCTM0_CC_IRQHandler +MCTM1_BRK_IRQHandler +MCTM1_UP_IRQHandler +MCTM1_TR_IRQHandler +MCTM1_CC_IRQHandler GPTM0_IRQHandler GPTM1_IRQHandler BFTM0_IRQHandler @@ -442,10 +453,11 @@ AES_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -456,14 +468,22 @@ AES_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN ENDIF - END + END \ No newline at end of file diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s index 323e76c6b6..41df8c40c1 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_03.s -; Version : $Rev:: 2524 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 3052 $ +; Date : $Date:: 2024-02-26 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,13 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-131072:8> Heap_Size EQU 0 @@ -366,10 +377,11 @@ AES_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -380,11 +392,19 @@ AES_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s index 0e11813688..2e47e3309e 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_cs3_01.s -; Version : $Rev:: 1578 $ -; Date : $Date:: 2019-03-29 #$ +; Version : $Rev:: 3030 $ +; Date : $Date:: 2024-01-31 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -139,14 +139,14 @@ __cs3_interrupt_vector_cortex_m: .long COMP_IRQHandler /* 24, 40, 0x0A0, */ .long ADC_IRQHandler /* 25, 41, 0x0A4, */ .long _RESERVED /* 26, 42, 0x0A8, */ - .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ - .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ - .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ - .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ - .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ - .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ - .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ - .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long MCTM0_BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0_UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0_TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0_CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1_BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1_UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1_TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1_CC_IRQHandler /* 34, 50, 0x0C8, */ .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ .long _RESERVED /* 37, 53, 0x0D4, */ @@ -384,14 +384,14 @@ Default_Handler: IRQ EXTI15_IRQHandler IRQ COMP_IRQHandler IRQ ADC_IRQHandler - IRQ MCTM0BRK_IRQHandler - IRQ MCTM0UP_IRQHandler - IRQ MCTM0TR_IRQHandler - IRQ MCTM0CC_IRQHandler - IRQ MCTM1BRK_IRQHandler - IRQ MCTM1UP_IRQHandler - IRQ MCTM1TR_IRQHandler - IRQ MCTM1CC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ MCTM1_BRK_IRQHandler + IRQ MCTM1_UP_IRQHandler + IRQ MCTM1_TR_IRQHandler + IRQ MCTM1_CC_IRQHandler IRQ GPTM0_IRQHandler IRQ GPTM1_IRQHandler IRQ BFTM0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s index 623ce3b725..aede8caf55 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_gcc_01.s -; Version : $Rev:: 1578 $ -; Date : $Date:: 2019-03-29 #$ +; Version : $Rev:: 3030 $ +; Date : $Date:: 2024-01-31 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -163,14 +163,14 @@ __interrupt_vector_cortex_m: .long COMP_IRQHandler /* 24, 40, 0x0A0, */ .long ADC_IRQHandler /* 25, 41, 0x0A4, */ .long _RESERVED /* 26, 42, 0x0A8, */ - .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ - .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ - .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ - .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ - .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ - .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ - .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ - .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long MCTM0_BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0_UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0_TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0_CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1_BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1_UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1_TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1_CC_IRQHandler /* 34, 50, 0x0C8, */ .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ .long _RESERVED /* 37, 53, 0x0D4, */ @@ -442,14 +442,14 @@ Default_Handler: IRQ EXTI15_IRQHandler IRQ COMP_IRQHandler IRQ ADC_IRQHandler - IRQ MCTM0BRK_IRQHandler - IRQ MCTM0UP_IRQHandler - IRQ MCTM0TR_IRQHandler - IRQ MCTM0CC_IRQHandler - IRQ MCTM1BRK_IRQHandler - IRQ MCTM1UP_IRQHandler - IRQ MCTM1TR_IRQHandler - IRQ MCTM1CC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ MCTM1_BRK_IRQHandler + IRQ MCTM1_UP_IRQHandler + IRQ MCTM1_TR_IRQHandler + IRQ MCTM1_CC_IRQHandler IRQ GPTM0_IRQHandler IRQ GPTM1_IRQHandler IRQ BFTM0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s index 331f561dc0..1c37c2d79f 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_iar_01.s -; Version : $Rev:: 1774 $ -; Date : $Date:: 2019-07-25 #$ +; Version : $Rev:: 3030 $ +; Date : $Date:: 2024-01-31 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -104,14 +104,14 @@ __vector_table DCD COMP_IRQHandler ; 24, 40, 0x0A0, DCD ADC_IRQHandler ; 25, 41, 0x0A4, DCD _RESERVED ; 26, 42, 0x0A8, - DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, - DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, - DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, - DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, - DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, - DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, - DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, - DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD MCTM0_BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0_UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0_TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0_CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1_BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1_UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1_TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1_CC_IRQHandler ; 34, 50, 0x0C8, DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, DCD _RESERVED ; 37, 53, 0x0D4, @@ -306,14 +306,14 @@ SysTick_Handler PUBWEAK EXTI15_IRQHandler PUBWEAK COMP_IRQHandler PUBWEAK ADC_IRQHandler - PUBWEAK MCTM0BRK_IRQHandler - PUBWEAK MCTM0UP_IRQHandler - PUBWEAK MCTM0TR_IRQHandler - PUBWEAK MCTM0CC_IRQHandler - PUBWEAK MCTM1BRK_IRQHandler - PUBWEAK MCTM1UP_IRQHandler - PUBWEAK MCTM1TR_IRQHandler - PUBWEAK MCTM1CC_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK MCTM1_BRK_IRQHandler + PUBWEAK MCTM1_UP_IRQHandler + PUBWEAK MCTM1_TR_IRQHandler + PUBWEAK MCTM1_CC_IRQHandler PUBWEAK GPTM0_IRQHandler PUBWEAK GPTM1_IRQHandler PUBWEAK BFTM0_IRQHandler @@ -372,14 +372,14 @@ EXTI14_IRQHandler EXTI15_IRQHandler COMP_IRQHandler ADC_IRQHandler -MCTM0BRK_IRQHandler -MCTM0UP_IRQHandler -MCTM0TR_IRQHandler -MCTM0CC_IRQHandler -MCTM1BRK_IRQHandler -MCTM1UP_IRQHandler -MCTM1TR_IRQHandler -MCTM1CC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_IRQHandler +MCTM0_CC_IRQHandler +MCTM1_BRK_IRQHandler +MCTM1_UP_IRQHandler +MCTM1_TR_IRQHandler +MCTM1_CC_IRQHandler GPTM0_IRQHandler GPTM1_IRQHandler BFTM0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s index 5f60bca990..ed4a812438 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f1xxxx_es_01.s -; Version : $Rev:: 1578 $ -; Date : $Date:: 2019-03-29 #$ +; Version : $Rev:: 3030 $ +; Date : $Date:: 2024-01-31 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -109,14 +109,14 @@ _vectors: .long COMP_IRQHandler /* 24, 40, 0x0A0, */ .long ADC_IRQHandler /* 25, 41, 0x0A4, */ .long _RESERVED /* 26, 42, 0x0A8, */ - .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ - .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ - .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ - .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ - .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ - .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ - .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ - .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long MCTM0_BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0_UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0_TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0_CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1_BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1_UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1_TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1_CC_IRQHandler /* 34, 50, 0x0C8, */ .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ .long _RESERVED /* 37, 53, 0x0D4, */ @@ -348,14 +348,14 @@ Default_Handler: IRQ EXTI15_IRQHandler IRQ COMP_IRQHandler IRQ ADC_IRQHandler - IRQ MCTM0BRK_IRQHandler - IRQ MCTM0UP_IRQHandler - IRQ MCTM0TR_IRQHandler - IRQ MCTM0CC_IRQHandler - IRQ MCTM1BRK_IRQHandler - IRQ MCTM1UP_IRQHandler - IRQ MCTM1TR_IRQHandler - IRQ MCTM1CC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ MCTM1_BRK_IRQHandler + IRQ MCTM1_UP_IRQHandler + IRQ MCTM1_TR_IRQHandler + IRQ MCTM1_CC_IRQHandler IRQ GPTM0_IRQHandler IRQ GPTM1_IRQHandler IRQ BFTM0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h index 2acc00f77a..66345b6f9b 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_cm3_misc.h - * @version $Rev:: 5 $ - * @date $Date:: 2017-05-11 #$ + * @version $Rev:: 3143 $ + * @date $Date:: 2024-07-04 #$ * @brief All the function prototypes for the miscellaneous firmware library. ************************************************************************************************************* * @attention @@ -112,6 +112,11 @@ void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource); void SYSTICK_CounterCmd(u32 SysTick_Counter); void SYSTICK_IntConfig(ControlStatus NewState); void SYSTICK_SetReloadValue(u32 SysTick_Reload); +#if (HTCFG_STACK_USAGE_ANALYSIS == 1) +void StackUsageAnalysisInit(u32 addr); +#else +#define StackUsageAnalysisInit(...) +#endif /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h index 46eef808e9..e33f4cbf19 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_dependency.h - * @version $Rev:: 2971 $ - * @date $Date:: 2023-10-25 #$ + * @version $Rev:: 3048 $ + * @date $Date:: 2024-02-22 #$ * @brief The header file of dependency check. ************************************************************************************************************* * @attention @@ -41,14 +41,22 @@ #if 0 // Version setting example for module /* Dependency check ----------------------------------------------------------------------------------------*/ -#if (__CORTEX_M == 0) +#if defined(__HT32L5XXXX_LIB_H) +#define MIN_HT32_FWLIB_VER (0x01000000) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x209) +#endif +#if defined(__HT32F5XXXX_LIB_H) #define MIN_HT32_FWLIB_VER (0x01000024) //0xmmnnnrrr -> Vm.n.r #define MIN_HT32_FWLIB_SVN (0x5762) #endif -#if (__CORTEX_M == 3) +#if defined(__HT32F1XXXX_LIB_H) #define MIN_HT32_FWLIB_VER (0x01000009) //0xmmnnnrrr -> Vm.n.r #define MIN_HT32_FWLIB_SVN (0x2556) #endif +#if defined(__HT32F4XXXX_LIB_H) +#define MIN_HT32_FWLIB_VER (0x01000000) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x336) +#endif #include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. #endif @@ -62,7 +70,7 @@ #endif -// Check "ht32fxxxxx_lib.h" for the version of HT32 Firmwar Library +// Check "ht32f1xxxx_lib.h" for the version of HT32 Firmwar Library #if (HT32_FWLIB_VER != 999999) #if HT32_FWLIB_VER < MIN_HT32_FWLIB_VER #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h index 1fc44cdc7c..47178c1e79 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_time.h - * @version $Rev:: 2896 $ - * @date $Date:: 2023-03-04 #$ + * @version $Rev:: 3089 $ + * @date $Date:: 2024-04-02 #$ * @brief The header file of time function. ************************************************************************************************************* * @attention @@ -132,23 +132,23 @@ #define TIME_TICKDIFF(start, current) ((current >= start) ? (u32)(current - start) : (u32)(0xFFFFFFFF - start + 1 + current)) #if (HTCFG_TIME_TICKHZ < 1000000) -#define TIME_US2TICK(us) (us / (1000000UL / HTCFG_TIME_TICKHZ)) -#define TIME_TICK2US(t) (t * (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_US2TICK(us) ((us) / (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2US(t) ((t) * (1000000UL / HTCFG_TIME_TICKHZ)) #else -#define TIME_US2TICK(us) (us * (HTCFG_TIME_TICKHZ / 1000000UL)) -#define TIME_TICK2US(t) (t / (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_US2TICK(us) ((us) * (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_TICK2US(t) ((t) / (HTCFG_TIME_TICKHZ / 1000000UL)) #endif #if (HTCFG_TIME_TICKHZ < 1000) -#define TIME_MS2TICK(ms) (ms / (1000UL / HTCFG_TIME_TICKHZ)) -#define TIME_TICK2MS(t) (t * (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_MS2TICK(ms) ((ms) / (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2MS(t) ((t) * (1000UL / HTCFG_TIME_TICKHZ)) #else -#define TIME_MS2TICK(ms) (ms * (HTCFG_TIME_TICKHZ / 1000UL)) -#define TIME_TICK2MS(t) (t / (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_MS2TICK(ms) ((ms) * (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_TICK2MS(t) ((t) / (HTCFG_TIME_TICKHZ / 1000UL)) #endif -#define TIME_S2TICK(s) (s * (u32)(HTCFG_TIME_TICKHZ)) -#define TIME_TICK2S(t) (t / (HTCFG_TIME_TICKHZ)) +#define TIME_S2TICK(s) ((s) * (u32)(HTCFG_TIME_TICKHZ)) +#define TIME_TICK2S(t) ((t) / (HTCFG_TIME_TICKHZ)) #define GET_CNT() (_HTCFG_TIME_PORT->CNTR) diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h index 176bf19e72..901edaacfb 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_aes.h - * @version $Rev:: 2022 $ - * @date $Date:: 2020-02-03 #$ + * @version $Rev:: 2985 $ + * @date $Date:: 2023-12-14 #$ * @brief The header file of the ADC library. ************************************************************************************************************* * @attention @@ -159,15 +159,15 @@ typedef enum void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); -void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize); -ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize); +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, u32 *iv, u32 length, u32 *inputData, u32 *outputData); #define AES_ECB_CryptData(a, b, c, d, e) _AES_CryptData(a, b, NULL, c, d, e) #define AES_CBC_CryptData _AES_CryptData #define AES_CTR_CryptData(a, b, c, d, e) _AES_CryptData(a, AES_DIR_ENCRYPT, b, c, d, e) #if 0 -ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 length, uc8 *inputData, u8 *outputData); -ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); -ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 length, u32 *inputData, u32 *outputData); +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, u32 *iv, u32 length, u32 *inputData, u32 *outputData); #endif void AES_StartKey(HT_AES_TypeDef* HT_AESn); @@ -180,7 +180,7 @@ FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x); void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState); void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data); u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn); -void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector); +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector); void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn); /** * @} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h index cb194268c0..0371043f4b 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_flash.h - * @version $Rev:: 2971 $ - * @date $Date:: 2023-10-25 #$ + * @version $Rev:: 3145 $ + * @date $Date:: 2024-07-05 #$ * @brief The header file of the FLASH library. ************************************************************************************************************* * @attention @@ -160,7 +160,7 @@ ErrStatus FLASH_FlashHalfCycleCmd(ControlStatus NewState); #if (LIBCFG_FLASH_ZWPWESAVING) ErrStatus FLASH_FlashZwPwrSavingCmd(ControlStatus NewState); #endif -void FLASH_SetRemappingMode(FLASH_Vector RemapMode); +void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x); FLASH_State FLASH_ErasePage(u32 PageAddress); FLASH_State FLASH_EraseOptionByte(void); FLASH_State FLASH_MassErase(void); diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h index f3c09ec6c0..558ac3ed74 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h @@ -34,8 +34,8 @@ #endif /* Settings ------------------------------------------------------------------------------------------------*/ -#define HT32_FWLIB_VER (0x01004001) -#define HT32_FWLIB_SVN (0x2982) +#define HT32_FWLIB_VER (0x01005001) +#define HT32_FWLIB_SVN (0x3190) #if defined(USE_HT32F1653_54) #include "ht32f1653_54_libcfg.h" diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h index f2e50b49f9..0ee2de96d5 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_rtc.h - * @version $Rev:: 2971 $ - * @date $Date:: 2023-10-25 #$ + * @version $Rev:: 3094 $ + * @date $Date:: 2024-06-19 #$ * @brief The header file of the RTC library. ************************************************************************************************************* * @attention @@ -105,7 +105,7 @@ typedef enum RTC_ROWM_LEVEL /*!< Level mode. */ } RTC_ROWM_Enum; /** - * @brief Waveform mode of RTC output + * @brief Event selection of RTC output */ typedef enum { diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h index d69c32afbf..015344e199 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_spi.h - * @version $Rev:: 2797 $ - * @date $Date:: 2022-11-28 #$ + * @version $Rev:: 3180 $ + * @date $Date:: 2024-10-15 #$ * @brief The header file of the SPI library. ************************************************************************************************************* * @attention @@ -159,14 +159,14 @@ typedef struct #define SPI_FLAG_TOUT ((u32)0x00000080) #define SPI_FLAG_BUSY ((u32)0x00000100) -#define IS_SPI_FLAG(FLAG) ((FLAG == SPI_FLAG_TXBE) || \ - (FLAG == SPI_FLAG_TXE) || \ +#define IS_SPI_FLAG(FLAG) ((FLAG == SPI_FLAG_TXBE) || \ + (FLAG == SPI_FLAG_TXE) || \ (FLAG == SPI_FLAG_RXBNE) || \ - (FLAG == SPI_FLAG_WC) || \ - (FLAG == SPI_FLAG_RO) || \ - (FLAG == SPI_FLAG_MF) || \ - (FLAG == SPI_FLAG_SA) || \ - (FLAG == SPI_FLAG_TOUT) || \ + (FLAG == SPI_FLAG_WC) || \ + (FLAG == SPI_FLAG_RO) || \ + (FLAG == SPI_FLAG_MF) || \ + (FLAG == SPI_FLAG_SA) || \ + (FLAG == SPI_FLAG_TOUT) || \ (FLAG == SPI_FLAG_BUSY)) #define IS_SPI_FLAG_CLEAR(CLEAR) ((CLEAR == SPI_FLAG_WC) || \ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h index b15bbbdbd0..d1663c7f56 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_tm.h - * @version $Rev:: 2971 $ - * @date $Date:: 2023-10-25 #$ + * @version $Rev:: 3180 $ + * @date $Date:: 2024-10-15 #$ * @brief The header file of the TM library. ************************************************************************************************************* * @attention @@ -341,11 +341,11 @@ typedef struct * @brief Used to check parameter of the output compare mode. */ #define IS_TM_OM_CMP(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ - ((x) == TM_OM_MATCH_INACTIVE) || \ - ((x) == TM_OM_MATCH_ACTIVE) || \ - ((x) == TM_OM_MATCH_TOGGLE) || \ - ((x) == TM_OM_PWM1) || \ - ((x) == TM_OM_PWM2)) + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2)) /** * @brief Used to check parameter of the output mode. */ @@ -377,7 +377,7 @@ typedef struct /** * @brief Used to check parameter of the counter mode. */ -#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ +#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ (x == TM_CNT_MODE_CA1) || \ (x == TM_CNT_MODE_CA2) || \ (x == TM_CNT_MODE_CA3) || \ @@ -397,23 +397,23 @@ typedef struct /** * @brief Used to check parameter of the channel input selection. */ -#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ - (x == TM_CHCCS_INDIRECT) || \ - (x == TM_CHCCS_TRCED)) +#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ + (x == TM_CHCCS_INDIRECT) || \ + (x == TM_CHCCS_TRCED)) /** * @brief Used to check parameter of the channel capture prescaler. */ #define IS_TM_CHPSC(x) ((x == TM_CHPSC_OFF) || \ - (x == TM_CHPSC_2) || \ - (x == TM_CHPSC_4) || \ - (x == TM_CHPSC_8)) + (x == TM_CHPSC_2) || \ + (x == TM_CHPSC_4) || \ + (x == TM_CHPSC_8)) /** * @brief Used to check parameter of the ETI prescaler. */ #define IS_TM_ETIPSC(x) ((x == TM_ETIPSC_OFF) || \ - (x == TM_ETIPSC_2) || \ - (x == TM_ETIPSC_4) || \ - (x == TM_ETIPSC_8)) + (x == TM_ETIPSC_2) || \ + (x == TM_ETIPSC_4) || \ + (x == TM_ETIPSC_8)) /** * @brief Used to check parameter of the TM interrupt. */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h index 6e0c5332b2..bc74274296 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_usart.h - * @version $Rev:: 2797 $ - * @date $Date:: 2022-11-28 #$ + * @version $Rev:: 3180 $ + * @date $Date:: 2024-10-15 #$ * @brief The header file of the USART library. ************************************************************************************************************* * @attention @@ -459,7 +459,7 @@ typedef struct #define IS_USART_PDMA_REQ(REQ) ((REQ == USART_PDMAREQ_TX) || (REQ == USART_PDMAREQ_RX)) #define IS_USART(USART) ((USART == HT_USART0) || \ - (IS_USART1(USART)) || \ + (IS_USART1(USART)) || \ (USART == HT_UART0) || \ (USART == HT_UART1)) diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h index c0a9c03951..9919223253 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_wdt.h - * @version $Rev:: 122 $ - * @date $Date:: 2017-06-13 #$ + * @version $Rev:: 3103 $ + * @date $Date:: 2024-06-24 #$ * @brief The header file of the WDT library. ************************************************************************************************************* * @attention @@ -72,14 +72,17 @@ /* WDT runs or halts in sleep and deep sleep1 mode */ /* WDT WDTSHLT mask */ -#define MODE0_WDTSHLT_BOTH ((u32)0x00000000) -#define MODE0_WDTSHLT_SLEEP ((u32)0x00004000) -#define MODE0_WDTSHLT_HALT ((u32)0x00008000) +#define WDT_SLEEP_HALT_NONE ((u32)0x00000000) +#define WDT_SLEEP_HALT_DEEPSLEEP ((u32)0x00004000) +#define WDT_SLEEP_HALT_ALL ((u32)0x00008000) -#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == MODE0_WDTSHLT_BOTH) || \ - (WDT_Mode == MODE0_WDTSHLT_SLEEP) || \ - (WDT_Mode == MODE0_WDTSHLT_HALT)) +#define MODE0_WDTSHLT_BOTH WDT_SLEEP_HALT_NONE +#define MODE0_WDTSHLT_SLEEP WDT_SLEEP_HALT_DEEPSLEEP +#define MODE0_WDTSHLT_HALT WDT_SLEEP_HALT_ALL +#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == WDT_SLEEP_HALT_NONE) || \ + (WDT_Mode == WDT_SLEEP_HALT_DEEPSLEEP) || \ + (WDT_Mode == WDT_SLEEP_HALT_ALL)) /* WDT Flag */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c index c9632a267d..401dd331ac 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_cm3_misc.c - * @version $Rev:: 2437 $ - * @date $Date:: 2021-06-01 #$ + * @version $Rev:: 3162 $ + * @date $Date:: 2024-07-23 #$ * @brief This file provides all the miscellaneous firmware functions. ************************************************************************************************************* * @attention @@ -218,6 +218,99 @@ void SYSTICK_SetReloadValue(u32 SysTick_Reload) SysTick->LOAD = SysTick_Reload; } + +#if 0 +// Copy the code below to the begin of the main(). +// START + + #if (HTCFG_STACK_USAGE_ANALYSIS == 1) + /* !!! NOTICE !!! + Please update the Keil HT32 PACK and HT32 Firmware Library to the latest version to make sure the + Stack Usage Analysis function works properly. + */ + /* + Set HTCFG_STACK_USAGE_ANALYSIS as 1 in the "ht32xxxxxx_conf.h" to enable Stack Usage Analysis feature. + This feature is only applicable to the Keil MDK-ARM. Please call the "StackUsageAnalysisInit()" function + in the begin of the "main()". + The "StackUsageAnalysisInit()" parameter shall be the start address of the vector table. + Under Keil Debug mode, tick "View > Watch Window > HT32 Stack Usage Analysis" to show the stack usage + information. Those information is only valid after calling "StackUsageAnalysisInit()" function. + */ + StackUsageAnalysisInit(0x00000000); + #endif + +// END +#endif + +#if (HTCFG_STACK_USAGE_ANALYSIS == 1) +#if defined (__CC_ARM) +#define STACKLIMITADDR 0x20000010 +#define STACKSTART 0x20000014 +u32 _StackLimit __attribute__((at(STACKLIMITADDR)))= HT_SRAM_BASE + LIBCFG_RAM_SIZE; +u32 _StackStart __attribute__((at(STACKSTART)))= HT_SRAM_BASE; +/*********************************************************************************************************//** + * @brief Stack Usage Analysis Init + * @retval None + ***********************************************************************************************************/ +__ASM void StackUsageAnalysisInit(u32 addr) +{ + extern _StackLimit; + extern __HT_check_sp; + extern _StackStart; + LDR R0, [r0] + LDR R1, =_StackLimit + STR R0, [r1] + + LDR R0, =__HT_check_sp + LDR R1, =_StackStart + STR R0, [r1] + MOV R1, SP + LDR R2, =0xCDCDCDCD + LDR R3, =0xABABABAB + STR R3, [ R0 ] + B Loop_Check +Loop + STR R2, [ R0 ] +Loop_Check + ADDS R0, R0, #0x04 + CMP R0, R1 + BLT Loop + BX LR + ALIGN +} +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define STACKLIMITADDR "0x20000010" +#define STACKSTART "0x20000014" +u32 _StackLimit __attribute__((section(".ARM.__at_"STACKLIMITADDR))) = HT_SRAM_BASE + LIBCFG_RAM_SIZE; +u32 _StackStart __attribute__((section(".ARM.__at_"STACKSTART))) = HT_SRAM_BASE; +/*********************************************************************************************************//** + * @brief Stack Usage Analysis Init + * @retval None + ***********************************************************************************************************/ +__attribute__((noinline)) void StackUsageAnalysisInit(u32 addr) +{ + __ASM volatile (" LDR R0, [r0]"); + __ASM volatile (" LDR R1, =_StackLimit"); + __ASM volatile (" STR R0, [r1]"); + + __ASM volatile (" LDR R0, =__HT_check_sp"); + __ASM volatile (" LDR R1, =_StackStart"); + __ASM volatile (" STR R0, [r1]"); + __ASM volatile (" MOV R1, SP"); + __ASM volatile (" LDR R2, =0xCDCDCDCD"); + __ASM volatile (" LDR R3, =0xABABABAB"); + __ASM volatile (" STR R3, [ R0 ]"); + __ASM volatile (" B Loop_Check"); + __ASM volatile ("Loop:"); + __ASM volatile (" STR R2, [ R0 ]"); + __ASM volatile ("Loop_Check:"); + __ASM volatile (" ADDS R0, R0, #0x04"); + __ASM volatile (" CMP R0, R1"); + __ASM volatile (" BLT Loop"); + __ASM volatile (" BX LR"); +} +#endif +#endif /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c index c6e8ea2a5b..cb66365032 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_aes.c - * @version $Rev:: 2788 $ - * @date $Date:: 2022-11-24 #$ + * @version $Rev:: 3174 $ + * @date $Date:: 2024-08-27 #$ * @brief This file provides all the AES firmware functions. ************************************************************************************************************* * @attention @@ -331,7 +331,7 @@ u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn) * @param keySize: Key table's size * @retval None ************************************************************************************************************/ -void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize) +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize) { u32 i; u32 uCRTemp = HT_AESn->CR & (~(0x00000060UL)); @@ -353,12 +353,12 @@ void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize) } HT_AESn->CR = uCRTemp; - for (i = 0; i < keySize; i += 4) + for (i = 0; i < (keySize / 4); i++) { #if (LIBCFG_AES_SWAP) - HT_AESn->KEYR[i >> 2] = __REV(*(u32*)&Key[i]); + HT_AESn->KEYR[i] = __REV(*&Key[i]); #else - HT_AESn->KEYR[i >> 2] = *(u32*)&Key[i]; + HT_AESn->KEYR[i] = *&Key[i]; #endif } @@ -371,17 +371,17 @@ void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize) * @param Vector: * @retval None ************************************************************************************************************/ -void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector) +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector) { int i; Assert_Param(IS_AES(HT_AESn)); - for (i = 0; i < 16; i += 4) + for (i = 0; i < 4; i++) { #if (LIBCFG_AES_SWAP) - HT_AESn->IVR[i >> 2] = __REV(*(u32*)&Vector[i]); + HT_AESn->IVR[i] = __REV(*&Vector[i]); #else - HT_AESn->IVR[i >> 2] = *(u32*)&Vector[i]; + HT_AESn->IVR[i] = *&Vector[i]; #endif } } @@ -398,10 +398,10 @@ void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector) ************************************************************************************************************/ ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, - uc8 *iv, + u32 *iv, u32 length, - uc8 *inputData, - u8 *outputData) + u32 *inputData, + u32 *outputData) { /*AES Data blocks 16 byte */ if ((length % 16) != 0) @@ -423,8 +423,8 @@ ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, HT_AESn->CR = (HT_AESn->CR & 0xFFFFFFFD) | dir; /*Create input/output data */ - gpu32InputBuff = (u32*)inputData; - gpu32OutputBuff = (u32*)outputData; + gpu32InputBuff = inputData; + gpu32OutputBuff = outputData; /*Init Index */ gu32OutputIndex = 0; @@ -451,8 +451,8 @@ ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, u32 length, - uc8 *inputData, - u8 *outputData) + u32 *inputData, + u32 *outputData) { return _AES_CryptData(HT_AESn, dir, @@ -474,10 +474,10 @@ ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, ************************************************************************************************************/ ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, - uc8 *iv, + u32 *iv, u32 length, - uc8 *inputData, - u8 *outputData) + u32 *inputData, + u32 *outputData) { return _AES_CryptData(HT_AESn, dir, @@ -497,10 +497,10 @@ ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, * @retval SUCCESS or ERROR ************************************************************************************************************/ ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, - uc8 *iv, + u32 *iv, u32 length, - uc8 *inputData, - u8 *outputData) + u32 *inputData, + u32 *outputData) { return _AES_CryptData(HT_AESn, AES_DIR_ENCRYPT, diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c index 81e7f8f143..b29f74848e 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_ckcu.c - * @version $Rev:: 2972 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 3181 $ + * @date $Date:: 2024-10-15 #$ * @brief This file provides all the Clock Control Unit firmware functions. ************************************************************************************************************* * @attention @@ -432,9 +432,9 @@ void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE) /********************************************************************************************************//** * @brief Configure the CK_USART prescaler. * @param URPRE: specify the prescaler value. - * This parameter can be: - * @arg CKCU_URPRE_DIV1: USART clock divided by 1 - * @arg CKCU_URPRE_DIV2: USART clock divided by 2 + * This parameter can be: + * @arg CKCU_URPRE_DIV1: USART clock divided by 1 + * @arg CKCU_URPRE_DIV2: USART clock divided by 2 * @retval None ************************************************************************************************************/ void CKCU_SetUSARTPrescaler(CKCU_URPRE_TypeDef URPRE) @@ -574,28 +574,28 @@ u32 CKCU_GetPLLFrequency(void) /*********************************************************************************************************//** * @brief Configure the APB peripheral prescaler. * @param Perip: specify the APB peripheral. - * This parameter can be: - * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, - * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, - * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, - * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, - * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, - * CKCU_PCLK_USART0, CKCU_PCLK_USART1, - * CKCU_PCLK_UART0, CKCU_PCLK_UART1, - * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, - * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, - * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, - * CKCU_PCLK_I2S, - * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, - * CKCU_PCLK_PWM0 + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, + * CKCU_PCLK_PWM0 * @param PCLKPrescaler: specify the value of prescaler. - * This parameter can be: - * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) - * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) - * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 - * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 - * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) - * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) + * This parameter can be: + * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 + * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 + * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) + * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) * @retval None ************************************************************************************************************/ void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPrescaler) @@ -607,28 +607,28 @@ void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_Ty Prescaler -= 2; } Perip &= 0x0000001F; - CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, Prescaler); + CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, (Prescaler & 0x3)); } #endif /*********************************************************************************************************//** * @brief Return the operating frequency of the specific APB peripheral. * @param Perip: specify the APB peripheral. - * This parameter can be: - * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, - * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, - * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, - * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, - * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, - * CKCU_PCLK_USART0, CKCU_PCLK_USART1, - * CKCU_PCLK_UART0, CKCU_PCLK_UART1, - * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, - * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, - * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, - * CKCU_PCLK_I2S, - * CKCU_PCLK_I2S, - * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, - * CKCU_PCLK_PWM0 + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, + * CKCU_PCLK_PWM0 * @retval Frequency in Hz ************************************************************************************************************/ u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip) @@ -953,10 +953,10 @@ void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cm /*********************************************************************************************************//** * @brief Configure the reference clock of HSI auto-trim function. * @param CLKSRC: specify the clock source. - * This parameter can be: - * @arg CKCU_ATC_LSE: LSE is selected as reference clock - * @arg CKCU_ATC_USB: USB is selected as reference clock - * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock + * This parameter can be: + * @arg CKCU_ATC_LSE: LSE is selected as reference clock + * @arg CKCU_ATC_USB: USB is selected as reference clock + * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock * @retval None ************************************************************************************************************/ void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC) @@ -983,9 +983,9 @@ void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct) /*********************************************************************************************************//** * @brief Automatic Trimming Algorithm Mode Selection. * @param Algo: Search Algorithm. - * This parameter can be: - * @arg CKCU_ATC_BINARY_SEARCH: Auto Trimming Controller is used binary search to approach the target range - * @arg CKCU_ATC_LINEAR_SEARCH: Auto Trimming Controller is used linear search to approach the target range + * This parameter can be: + * @arg CKCU_ATC_BINARY_SEARCH: Auto Trimming Controller is used binary search to approach the target range + * @arg CKCU_ATC_LINEAR_SEARCH: Auto Trimming Controller is used linear search to approach the target range * @retval None ***********************************************************************************************************/ void CKCU_HSIAutoTrimAlgorithm(u32 Algo) @@ -996,9 +996,9 @@ void CKCU_HSIAutoTrimAlgorithm(u32 Algo) /*********************************************************************************************************//** * @brief Lock Target Range Selection. * @param Tolerance: Variation Tolerance. - * This parameter can be: - * @arg CKCU_ATC_DOUBLE_PRECISION: 0.2 % variation - * @arg CKCU_ATC_SINGLE_PRECISION: 0.1 % variation + * This parameter can be: + * @arg CKCU_ATC_DOUBLE_PRECISION: 0.2 % variation + * @arg CKCU_ATC_SINGLE_PRECISION: 0.1 % variation * @retval None ***********************************************************************************************************/ void CKCU_HSIAutoTrimFreqTolerance(u32 Tolerance) diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c index 6c8a2638a7..3c01d6a6dc 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_rtc.c - * @version $Rev:: 2233 $ - * @date $Date:: 2020-10-13 #$ + * @version $Rev:: 2984 $ + * @date $Date:: 2023-11-23 #$ * @brief This file provides all the RTC firmware functions. ************************************************************************************************************* * @attention @@ -138,12 +138,10 @@ void RTC_LSECmd(ControlStatus NewState) if (NewState == DISABLE) { BB_LSE_EN = 0; - while (HT_CKCU->GCSR & 0x10); } else { BB_LSE_EN = 1; - while ((HT_CKCU->GCSR & 0x10) == 0); } } diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c index c0e8face8c..3c3c22aa82 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_spi.c - * @version $Rev:: 2797 $ - * @date $Date:: 2022-11-28 #$ + * @version $Rev:: 3086 $ + * @date $Date:: 2024-03-28 #$ * @brief This file provides all the SPI firmware functions. ************************************************************************************************************* * @attention @@ -325,6 +325,11 @@ void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL) } else { + /* Inactive SEL pin needs to ensure the transmission has ended. If the program flow cannot guarantee */ + /* SPI transmission completion, you can enable the procedure below. */ + #if 0 + while (SPIx->SR & SPI_FLAG_BUSY); /* Wait until SPI NOT BUSY */ + #endif SPIx->CR0 &= SPI_SEL_INACTIVE; } } @@ -560,6 +565,8 @@ void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) Assert_Param(IS_SPI(SPIx)); Assert_Param(IS_CONTROL_STATUS(NewState)); + while (SPIx->SR & SPI_FLAG_BUSY); /* Wait until SPI NOT BUSY */ + (NewState == ENABLE)?(SPIx->CR0 |= CR0_DUALEN_SET):(SPIx->CR0 &= CR0_DUALEN_RESET); } diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c index 5bd9a98e77..9e7adf1bf6 100644 --- a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f1xxxx_wdt.c - * @version $Rev:: 2797 $ - * @date $Date:: 2022-11-28 #$ + * @version $Rev:: 3103 $ + * @date $Date:: 2024-06-24 #$ * @brief This file provides all the WDT firmware functions. ************************************************************************************************************* * @attention @@ -109,9 +109,9 @@ void WDT_Cmd(ControlStatus NewState) * @brief Configure the WDT to run or halt in sleep and deep sleep1 mode. * @param WDT_Mode: * This parameter can be one of the following values: - * @arg MODE0_WDTSHLT_BOTH : WDT runs in sleep and deep sleep1 mode - * @arg MODE0_WDTSHLT_SLEEP : WDT runs in sleep mode - * @arg MODE0_WDTSHLT_HALT : WDT halts in sleep and deep sleep1 mode + * @arg WDT_SLEEP_HALT_NONE : WDT no halt + * @arg WDT_SLEEP_HALT_DEEPSLEEP : WDT halts in deep sleep1 mode + * @arg WDT_SLEEP_HALT_ALL : WDT halts in sleep and deep sleep1 mode * @retval None ************************************************************************************************************/ void WDT_HaltConfig(u32 WDT_Mode) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt index 948233eafc..1a18dbff8d 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file Release_Notes.txt - * @version V1.9.1 - * @date 2023-12-22 + * @version V1.14.3 + * @date 2024-11-29 * @brief The Release notes of HT32 Firmware Library. ************************************************************************************************************* * @attention @@ -48,20 +48,24 @@ // HT32F57331, HT32F57341 // HT32F57342, HT32F57352 // HT32F59041, HT32F59741 -// HT32F59046, HT32F59746 +// HT32F59045 +// HT32F59746 // HT32F5826, HT32F5828 // HT32F0006 // HT32F0008 // HT32F52142 // HT32F61030, HT32F61041 +// HT32F61052 // HT32F61141 // HT32F61244, HT32F61245 // HT32F61352 // HT32F61355, HT32F61356, HT32F61357 // HT32F61630, HT32F61641 +// HT32F61730, HT32F61741 // HT32F62030, HT32F62040, HT32F62050 // HT32F65230, HT32F65240 // HT32F65232 +// HT32F66242, HT32F66246 // HT32F67041, HT32F67051 // HT32F67232 // HT32F67233 @@ -71,6 +75,267 @@ // HT50F3200S, HT50F3200T // HF5032 // MXTX6306 +// MXTX52231, MXTX52352 +// NW32F61242 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.14.3_8294 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-11-29 + Main Changes + + Add new device support. + - HT32F61052 + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.14.2_8286 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-11-26 + Main Changes + + Add example support of HT32F65232. + + Fix "ADC/OneShot_SWTrigger/ht32f5xxxx_01_it.h" parameter error. + - Rename "ADC_IRQHandler" to "HTCFG_ADC_IRQHandler" + + Add the "DISABLE_BOOTPIN_OUTPUT" definition in "CKCU/Clock_Configuration/ht32_board_config.h" to prevent + circuit conflicts on certain development boards. + - HT32F65232_DVB + - HT32F66242_DVB + - HT32F66246_DVB + + Modify the "OPA/OPA_Enable" example to use a single OPA and add "ht32_board_config.h". + + Add the "LED_HIGH_ACTIVE" definition to the following files and Fix "ht32f5xxxx_board_01.c" to align with + the LED circuit on the development board: + - bm18b367a_dvb.h + - bm53b367a_dvb.h + - ht32f65232_dvb.h + - ht32f65240_dvb.h + - ht32f66242_dvb.h + - ht32f66246_dvb.h + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.14.1_8273 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-11-08 + Main Changes + + Add new device support. + - HT32F66242, HT32F66246 + + Add new IP drivers. + - Programmable Gain Amplifier, "ht32f65xxx_66xxx_pga.c/h" + - Coordinate Rotation Digital Computer, "ht32f66xxx_cordic.c/h" + - Proportion Integration Differentiation driver, "ht32f66xxx_pid.c/h" + + Add new examples: + - "CORDIC/CosSin_Interrupt" + - "CORDIC/CosSin_Polling" + - "PGA/Comparator" + - "PGA/Inverting" + - "PGA/InvertingAdder" + - "PGA/NonInverting" + - "PGA/NonInvertingAdder" + - "PGA/VoltageFollower" + - "PID/ChangePara_inSameMode" + - "PID/Interrupt" + - "PID/MultiMode" + - "PID/Polling" + + Add the "LIBCFG_CKCU_NO_LPCR" definition in "ht32f65230_40_libcfg.h" and "ht32f65232_libcfg.h" to + fix the "CKCU_BKISOCmd" the redundant flow of the HT32F65230/65240 and HT32F65232 (related to the Low Power Control). + + Add the "LIBCFG_PWRCU_NO_DS2_MODE" definition in "ht32f65230_40_libcfg.h" and "ht32f65232_libcfg.h" to + fix the "PWRCU_DeepSleep2()" and "PWRCU_GetDMOSStatus()" the redundant flow + of the HT32F65230/65240 and HT32F65232 (related to the Deep-Sleep2 Mode). + + Remove the "LIBCFG_PWRCU_NO_PORF" definition in "ht32f65232_libcfg.h" to fix the "PWRCU_DeInit()" + missing flow of the HT32F65232 (related to the Power-On Reset Flag). + + Change the HTCFG_TIMER_PRESCALER value according to HTCFG_PULSE_SYS_CLK is less + than or greater than 60 MHz to ensure that the Counter-Reload value is less than 0xFFFF. + - "TM/UpdateEvent" + - "TM/SinglePulseMode" + - "TM/TriggerCounter" + + Others + + Update comment, format, typing error, and coding style. + + Change define "LIBCFG_CMP_65x_VER" to "LIBCFG_CMP_65x_66x_VER" for the HT32F65xxx and HT32F66xxx series ICs. + + Add "IS_ADC_TRIG_CMP2()" macro, for use to confirm the adc trigger is CMP2 in ht32f65xxx_66xxx_adc.h + + Fix the bit position error in the "IS_ADC_INT" macro. + + Change define "LIBCFG_TM_652XX_V1" to "LIBCFG_TM_65X_66X_V1" + + Change define "LIBCFG_TM_65232" to "LIBCFG_TM_65X_66X_BK_FROM_CMP" and "LIBCFG_TM_65X_66X_RECCDI" + + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.13.2_8218 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-10-23 + Main Changes + + Fix "CAN_Legacy/TxRxLoopback" example compiling error. + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.13.1_8190 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-09-24 + Main Changes + + Add new device support. + - NW32F61242 + + Change the CAN IP Driver, switch to the latest designed API. + + Add new examples. + "CAN/Recv_DATA" + "CAN/Recv_Interrupt" + "CAN/Recv_Mask_Filter" + "CAN/Recv_REMOTE" + "CAN/Send_DATA" + "CAN/Send_Recv_DATA" + "CAN/Send_REMOTE" + + Fix "AES_SetKeyTable()" and "AES_SetVectorTable()" Key and Vector index errors, which cause incorrect AES + encryption and decryption. + + Modify "I2C/7_bit_mode" example, fix pin assignment error of HT32F50343. + + Others + + Update comment, format, typing error, and coding style. + + Update AES examples. + - Change the key, IV, and plain text from hex array to string, making the result easier to compare with + online tools. + - Add expected cipher text and compare it with the MCU's H/W AES result as an error-proofing mechanism. + + Remove device support. + - HT32F57541, HT32F57552 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.12.1_7949 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-08-08 + Main Changes + + Add new device support. + - HT32F57541 + - HT32F57552 + + Update "uart_module.c" to fix the UART0 ~ UART3 not work issue of BM53A367A. + + Others + + Update comment, format, typing error, and coding style. + + Change path of the "Holtek.HT32_DFP.latest.pack". + + Minor changes were made to the USBD "HID_Keyboard_Virtual_COM" and "Virtual_COM" examples. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.11.1_7908 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-07-26 + Main Changes + + Add new device support. + - HT32F59045 + - MXTX52231, MXTX52352 + + Remove device support. + - HT32F59046 + + Rename WDT parameters. + - Old Name | New Name + - --------------------------------- | ---------------------------- + - "MODE0_WDTSHLT_BOTH" | "WDT_SLEEP_HALT_NONE" + - "MODE0_WDTSHLT_SLEEP" | "WDT_SLEEP_HALT_DEEPSLEEP" + - "MODE0_WDTSHLT_SLEEP" | "WDT_SLEEP_HALT_ALL" + + Update below files to support the BMduino shield/module Keil Driver. + - Modify :"utilities/bmduino_board.h". + - Add :"utilities/bmduino_check.h". + + Modify "void StackUsageAnalysisInit(void)". Added parameter "u32 addr" and reimplemented as + "void StackUsageAnalysisInit(u32 addr);" + + Fix the below examples ADC_IRQHandler define error of HT32F65232 and HT32F65240. + - "ADC/AnalogWatchdog" + - "ADC/Continuous_Potentiometer" + - "ADC/Discontinuous_EXTITrigger" + - "ADC/OneShot_PWMTrigger" + - "ADC/OneShot_PWMTrigger_with_Delay" + - "ADC/OneShot_SWTrigger" + + Modify example IO define of HT32F65232. + - "ADC/AnalogWatchdog" + - "ADC/Continuous_Potentiometer" + - "ADC/Discontinuous_EXTITrigger" + - "ADC/OneShot_PWMTrigger" + - "ADC/OneShot_PWMTrigger_with_Delay" + - "ADC/OneShot_SWTrigger" + - "ADC/OneShot_TMTrigger_PDMA" + + Others + + Update comment, format, typing error, and coding style. + + Update ht32f5xxxx_01.h. + - Modify the preprocessor define of "__ALIGN4", "__PACKED_H", "__PACKED_F" for old Arm Compiler V6. + + Modify "void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x);". Changed parameter name from + "RemapMode" to "FLASH_BOOT_x". + + Modify comments to remind users about "Stack Usage Analysis" notification. + + Remove redefined "PWRRST_SET" setting in "ht32f5xxxx_pwrcu.c". + + Update CKCU API. Enhanced program stability with robustness settings for parameter "PCLKPrescaler" + in "CKCU_SetPeripPrescaler(..., CKCU_APBCLKPRE_TypeDef PCLKPrescaler)". + + Update I2C Master middleware, improve setting way and fix minor errors. + + Update the following middleware to support the BMduino Keil Driver. + "utilities/middleware/i2c_master.c" + "utilities/middleware/i2c_master.h" + "utilities/middleware/spi_module.c" + "utilities/middleware/spi_module.h" + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Update xxTM IP Driver + - Remove redundant "TM_ClearOREFConfig()" function. + + Update "DAC_Cmd()" of "ht32f5xxxx_dac.c", remove compiler warning of the GNU compiler. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.10.1_7761 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-06-11 + Main Changes + + Add new device support. + - HT32F61730, HT32F61741 + + Add new examples. + "ADC/BandgapVoltage" + "GPIO/SinkCurrentEnhanced" + + Update related files of HT32F59046. + + Fix the "USE_HT32_CHIP" ID error of HT32F52244 (change from 33 to 35). + + Remove "LIBCFG_GPIO_SINK_CURRENT_ENHANCED" setting error for the following part number. + HT32F50431/50441 + HT32F50442/50452 + HT32F53231/53241 + HT32F53242/53252 + HT32F54231/54241 + HT32F54243/54253 + + Change the ADC API, "ADC_VREFOutputCmd()" as "ADC_VREFOutputADVREFPCmd()". + + Change the CKCU API, "CKCU_Set_HSIReadyCounter" as "CKCU_SetHSIReadyCounter()". + + Add "LIBCFG_GPIO_SINK_CURRENT_ENHANCED" setting of HT32F50020/50030. + + Improve the thread-safe capability of "utilities/common/ring_buffer.c". + + Others + + Update comment, format, typing error, and coding style. + + Update the project file of HT32F61141, change the "ht32f5xxxx_01_usbdconf.h" as ht32f5xxxx_02_usbdconf.h". + + Update "SPI_DUALCmd()", "QSPI_QuadCmd()", and "QSPI_DirectionConfig()", make sure the SPI Bus is not busy + before changing the settings. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.9.2_7624 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2024-02-29 + Main Changes + + Add new examples. + "Tips/Checksum_CRC16" + "Tips/StackOnTop" + "USART/LIN_Master" + "USART/LIN_Slave" + "CAN/TxRxLoopback" + + Add "LIBCFG_CMP_IVREF_CN_IN" define of the following parts, to fix the comparator function/feature + missing (select VREF as inverted input). + - HT32F50442/50452/53242/53252. + + Add HT32 Stack Usage Analysis feature. + - Modify "ht32f5xxxx_conf.h", add "HTCFG_STACK_USAGE_ANALYSIS" setting for enabling HT32 Stack Usage + Analysis. + - Update project templates and "ht32_cm0plus_misc.c/.h", add "StackUsageAnalysisInit()" function to + initialize stack. + - Update project files, add HT32 Stack Usage Analysis component viewer. + + Update and sync "startup_ht32f5xxxx_nn.s" for the "Stack On Top" and "Stack Usage Analysis" feature. + + Add "USE_LIBCFG_RAM_SIZE" define in Keil project files for the "Stack On Top" feature. + + Modify "ht32f5xxxx_01.h", fix the MCTM alias mismatch. + - "MCTMn_IRQHandler" alias from "MCTM0_G_IRQHandler" to "MCTM0_UP_IRQHandler" + + Update related middleware (eeprom_emulation and spi_module). + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.20" ("utilities/elink32pro/eLink32pro.exe"). + + Update "TM/PWM_Buzzer/buzzer_pwm.c" to remove redefine alias (they are also defined in "ht32f5xxxx_01.h.). + + Update Keil after build setting, add double quotes (") in the command to prevent space in the path issues. + + Remove "ht32_board_config.h" from the "PDMA/SoftwareTrigger" example. /*----------------------------------------------------------------------------------------------------------*/ /* HT32_STD_5xxxx_FWLib_V1.9.1_7446 */ @@ -386,8 +651,8 @@ - Add "gEXTIn_IRQn[]" and "EXTI_GetIRQn()"" macro to map GPIO pin number (0 ~ 15) to "EXTIn_IRQn". - Add "GPIO2EXTI()"" macro to map GPIO pin to EXTI Channel. - Change "AFIO_EXTISourceConfig()"" API, remove "AFIO_EXTI_CH_Enum" and "AFIO_ESS_Enum". - Old: "void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px);" - New: "void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px);" + Old: void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px) + New: void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) + LEDC - Fix typing error of the following define. Old New @@ -772,7 +1037,7 @@ + Update GNU project (*.uvprojx), fix the compile error when use new GNU Arm version ("gcc-arm-none-eabi-10-2020-q2-preview-win32" or above). + Fix Keil compiling error when disable both retarget and MicroLib. - + Update "ht32f1xxxx_01.h", fix the compatibility issue when user include "stdbool.h". + + Update "ht32f5xxxx_01.h", fix the compatibility issue when user include "stdbool.h". + Modify GNU compiler settings, output text file (disassembly) after building the code. + Change the startup/system supporting files of specify MCU device. Old New @@ -782,12 +1047,12 @@ startup_ht32f5xxxx_xxx_01.s to startup_ht32f5xxxx_xxx_07.s - HT32F52344/HT32F52354 startup_ht32f5xxxx_01.s to startup_ht32f5xxxx_03.s - + Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f1xxxx_lib.h" for the version information of + + Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f5xxxx_lib.h" for the version information of HT32 Firmware Library. Example: "#define HT32_FWLIB_VER (018)" "#define HT32_FWLIB_VER (5303)" - + Add new AFIO define in "ht32f1xxxx_gpio.h". + + Add new AFIO define in "ht32f5xxxx_gpio.h". - "AFIO_FUN_MCTM0", "AFIO_FUN_MCTM1" - "AFIO_FUN_GPTM0", "AFIO_FUN_GPTM1", "AFIO_FUN_GPTM2", "AFIO_FUN_GPTM3" - "AFIO_FUN_PWM0", "AFIO_FUN_PWM1", "AFIO_FUN_PWM2", "AFIO_FUN_PWM3" diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript index 32e59edc7c..2411aa028f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript @@ -2,38 +2,11 @@ import os import sys import rtconfig from building import * - -def get_source(ic_model, file_path, system_path, base_path): - source_path = [] - files_list = [] - readafter = 0 - if not os.path.isfile(file_path): - return - - with open(file_path, 'r') as file: - # content = file.read() - for line in file: - if readafter == 2 and line.find('>') != -1: - break - if readafter == 2: - files_list.append(line.strip()) - if line.find(ic_model) != -1: - readafter = 1 - if readafter == 1 and line.find('<') != -1: - readafter = 2 - for line in files_list: - if line.find('system') != -1: - source_path.append(os.path.join(system_path, line.strip())) - else: - source_path.append(os.path.join(base_path, line.strip())) - return source_path - - Import('rtconfig') tools_path = os.path.normpath(os.getcwd() + '../../..' + '/tools') sys.path.append(tools_path) - +from sdk_dist import get_source source_file_path = os.path.join(os.getcwd(), 'Source_file') base_path = 'library/HT32F5xxxx_Driver/src/' diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h index f72fd72a6f..41ea34e832 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h @@ -1,8 +1,8 @@ /***************************************************************************//** * @file ht32f5xxxx_01.h * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File - * @version $Rev:: 7319 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -255,9 +255,7 @@ typedef enum IRQn ADC0_IRQn = 8, /*!< ADC0 Interrupt */ #if defined(USE_HT32F65230_40) ADC1_IRQn = 9, /*!< ADC1 Interrupt */ - #elif defined(USE_HT32F66242) - CORDIC_IRQn = 9, /*!< CORDIC global Interrupt */ - #elif defined(USE_HT32F66246) + #elif defined(USE_HT32F66242) || defined(USE_HT32F66246) CORDIC_IRQn = 9, /*!< CORDIC global Interrupt */ #endif MCTM0_BRK_IRQn = 10, /*!< MCTM BRK Interrupt */ @@ -272,10 +270,8 @@ typedef enum IRQn CMP1_IRQn = 19, /*!< Comparator1 Interrupt */ #if defined(USE_HT32F65230_40) CMP2_IRQn = 20, /*!< Comparator2 Interrupt */ - #elif defined(USE_HT32F66242) - PID_IRQn = 20, /*!< PID global Interrupt */ - #elif defined(USE_HT32F66246) - PID_IRQn = 20, /*!< PID global Interrupt */ + #elif defined(USE_HT32F66242) || defined(USE_HT32F66246) + PID0_IRQn = 20, /*!< PID global Interrupt */ #endif I2C0_IRQn = 21, /*!< I2C global Interrupt */ SPI0_IRQn = 22, /*!< SPI global Interrupt */ @@ -538,13 +534,18 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #if defined (__CC_ARM) #define __ALIGN4 __align(4) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #define __ALIGN4 __attribute__((aligned(4))) #elif defined (__ICCARM__) #define __ALIGN4 _Pragma("data_alignment = 4") #elif defined (__GNUC__) #define __ALIGN4 __attribute__((aligned(4))) #endif -#if defined (__GNUC__) +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #define __PACKED_H + #define __PACKED_F __attribute__ ((packed)) +#elif defined (__GNUC__) #define __PACKED_H #define __PACKED_F __attribute__ ((packed)) #elif defined (__ICCARM__) || (__CC_ARM) @@ -675,14 +676,21 @@ typedef struct { /* ADC0: 0x40010000 */ /* ADC1: 0x40050000 */ - __IO uint32_t CFGR; /*!< 0x000 ADC Configuration Register (ADC1 only) */ + __IO uint32_t CFGR; /*!< 0x000 ADC Configuration Register (ADC1 only for specific */ + /*! model) */ __IO uint32_t RST; /*!< 0x004 ADC Reset Register */ __IO uint32_t CONV; /*!< 0x008 ADC Regular Conversion Mode Register */ __IO uint32_t HCONV; /*!< 0x00C ADC High-priority Conversion Mode Register */ __IO uint32_t LST[2]; /*!< 0x010 - 0x014 ADC Conversion List Register */ uint32_t RESERVE0[2]; /*!< 0x018 - 0x01C Reserved */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) __IO uint32_t HLST; /*!< 0x020 ADC High-priority Conversion List Register */ uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + #endif + #if defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t HLST[3]; /*!< 0x020 - 0x028 ADC High-priority Conversion List Register 0-2 */ + uint32_t RESERVE1[1]; /*!< 0x02C Reserved */ + #endif #if defined(USE_HT32F65230_40) __IO uint32_t OFR[12]; /*!< 0x030 - 0x05C ADC Input Offset Register 0-11 */ uint32_t RESERVE2[4]; /*!< 0x060 - 0x06C Reserved */ @@ -695,12 +703,9 @@ typedef struct __IO uint32_t STR[15]; /*!< 0x070 - 0x0A8 ADC Input Sampling Time Register 0-14 */ uint32_t RESERVE3[1]; /*!< 0x0AC Reserved */ #endif - #if defined(USE_HT32F66242) - uint32_t RESERVE2[16]; /*!< 0x030 - 0x06C Reserved */ - __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ - #endif - #if defined(USE_HT32F66246) - uint32_t RESERVE2[16]; /*!< 0x030 - 0x06C Reserved */ + #if defined(USE_HT32F66242) || defined(USE_HT32F66246) + uint32_t RESERVE2[15]; /*!< 0x030 - 0x068 Reserved */ + uint32_t RESERVE3[1]; /*!< 0x06C Reserved */ __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ #endif __IO uint32_t DR[8]; /*!< 0x0B0 - 0x0CC ADC Regular Conversion Data Register 0-7 */ @@ -726,15 +731,7 @@ typedef struct __IO uint32_t DIESR; /*!< 0x150 Dual ADC Interrupt Enable/Status Register (ADC1 only) */ __IO uint32_t DPDMAR; /*!< 0x154 Dual ADC PDMA Request Register (ADC1 only) */ #endif - #if defined(USE_HT32F66242) - uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ - __IO uint32_t VREFCR; /*!< 0x150 ADC Reference Voltage Control Register */ - uint32_t RESERVE9[3]; /*!< 0x154 - 0x15C Reserved */ - __IO uint32_t HDR4[8]; /*!< 0x160 - 0x17C ADC High-priority Conversion Data Register 4-11 */ - uint32_t RESERVE10[4]; /*!< 0x180 - 0x18C Reserved */ - __IO uint32_t STR16[2]; /*!< 0x190 - 0x194 ADC Input Sampling Time Register 16-17 */ - #endif - #if defined(USE_HT32F66246) + #if defined(USE_HT32F66242) || defined(USE_HT32F66246) uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ __IO uint32_t VREFCR; /*!< 0x150 ADC Reference Voltage Control Register */ uint32_t RESERVE9[3]; /*!< 0x154 - 0x15C Reserved */ @@ -909,7 +906,7 @@ typedef struct __IO uint32_t DOUTR; /*!< 0x020 Data Output Register */ __IO uint32_t SRR; /*!< 0x024 Output Set and Reset Control Register */ __IO uint32_t RR; /*!< 0x028 Output Reset Control Register */ - #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + #if defined(USE_HT32F50020_30) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) __IO uint32_t SCER; /*!< 0x02C Sink Current Enhanced Selection Register */ #endif } HT_GPIO_TypeDef; @@ -1055,7 +1052,7 @@ typedef struct __IO uint32_t LVDCSR; /*!< 0x010 Low Voltage/Brown Out Detect Control and Status Register*/ #if defined(USE_HT32F57342_52) uint32_t RESERVE2[2]; /*!< 0x014 ~ 0x18 Reserved */ - __IO uint32_t LDOSR ; /*!< 0x01C Power Control LDO Status Register */ + __IO uint32_t LDOSR; /*!< 0x01C Power Control LDO Status Register */ #endif #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) uint32_t RESERVE3[59]; /*!< 0x014 ~ 0x0FC Reserved */ @@ -1180,7 +1177,7 @@ typedef struct #else uint32_t RESERVED3[2]; /*!< 0x040 ~ 0x44 Reserved */ #endif - #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F66242) || defined(USE_HT32F66246) __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ uint32_t RESERVED4[173]; /*!< 0x04C ~ 0x2FC Reserved */ #elif defined(USE_HT32F52234_44) @@ -1190,7 +1187,7 @@ typedef struct #else uint32_t RESERVED4[174]; /*!< 0x048 ~ 0x2FC Reserved */ #endif - #if !defined(USE_HT32F50020_30) + #if !defined(USE_HT32F50020_30) && !defined(USE_HT32F65230_40) && !defined(USE_HT32F65232) && !defined(USE_HT32F66242) && !defined(USE_HT32F66246) __IO uint32_t LPCR; /*!< 0x300 Low Power Control Register */ #else uint32_t RESERVED5; /*!< 0x300 Reserved */ @@ -1799,6 +1796,7 @@ typedef struct __IO uint32_t DB1R; /*!< 0x028 CAN Interface Data B 1 Register */ } HT_CANIF_TypeDef; + /** * @brief Controller Area Network Global */ @@ -1830,6 +1828,7 @@ typedef struct __IO uint32_t MVR1; /*!< 0x164 Message Valid Register 1 */ } HT_CAN_TypeDef; + /** * @brief Coordinate Rotation Digital Computer */ @@ -1841,69 +1840,47 @@ typedef struct __IO uint32_t RDATA; /*!< 0x008 Result Register */ } HT_CORDIC_TypeDef; +/** + * @brief Proportional Mode parameters + */ +typedef struct +{ + + __IO uint32_t LEIR; /*!< 0x000 Last Error Input Register */ + __IO uint32_t KPIR; /*!< 0x004 KP Input Register */ + __IO uint32_t KIIR; /*!< 0x008 KI Input Register */ + __IO uint32_t KDIR; /*!< 0x00C KD Input Register */ + __IO uint32_t LIFVR; /*!< 0x010 Last Integral Function Value Register */ + __IO uint32_t IFVMAXLR; /*!< 0x014 Integral Function Value Maximum Limitation Register */ + __IO uint32_t IFVMINLR; /*!< 0x018 Integral Function Value Minimum Limitation Register */ + __IO uint32_t PIDORLR; /*!< 0x01C PID Output Result Limitation Register */ +} HT_PIDPARA_TypeDef; +/** + * @} + */ + /** * @brief Proportional Integral Derivative controller */ typedef struct { /* PID: 0x400EC000 */ - __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ - __IO uint32_t UI_INPUT; /*!< 0x004 */ - __IO uint32_t ERR_n; /*!< 0x008 */ - __IO uint32_t PID_OUT; /*!< 0x00C */ - __IO uint32_t SPD1ERR1; /*!< 0x010 */ - __IO uint32_t SPD1KP; /*!< 0x014 */ - __IO uint32_t SPD1KI; /*!< 0x018 */ - __IO uint32_t SPD1KD; /*!< 0x01C */ - __IO uint32_t SPD1UI1; /*!< 0x020 */ - __IO uint32_t SPD1UI_MAX; /*!< 0x024 */ - __IO uint32_t SPD1UI_MIN; /*!< 0x028 */ - __IO uint32_t SPD1_PIDOUT_LIM; /*!< 0x02C */ - __IO uint32_t IQ1ERR1; /*!< 0x030 */ - __IO uint32_t IQ1KP; /*!< 0x034 */ - __IO uint32_t IQ1KI; /*!< 0x038 */ - __IO uint32_t IQ1KD; /*!< 0x03C */ - __IO uint32_t IQ1UI1; /*!< 0x040 */ - __IO uint32_t IQ1UI_MAX; /*!< 0x044 */ - __IO uint32_t IQ1UI_MIN; /*!< 0x048 */ - __IO uint32_t IQ1_PIDOUT_LIM; /*!< 0x04C */ - __IO uint32_t ID1ERR1; /*!< 0x050 */ - __IO uint32_t ID1KP; /*!< 0x054 */ - __IO uint32_t ID1KI; /*!< 0x058 */ - __IO uint32_t ID1KD; /*!< 0x05C */ - __IO uint32_t ID1UI1; /*!< 0x060 */ - __IO uint32_t ID1UI_MAX; /*!< 0x064 */ - __IO uint32_t ID1UI_MIN; /*!< 0x068 */ - __IO uint32_t ID1_PIDOUT_LIM; /*!< 0x06C */ - __IO uint32_t FWNK1ERR1; /*!< 0x070 */ - __IO uint32_t FWNK1KP; /*!< 0x074 */ - __IO uint32_t FWNK1KI; /*!< 0x078 */ - __IO uint32_t FWNK1KD; /*!< 0x07C */ - __IO uint32_t FWNK1UI1; /*!< 0x080 */ - __IO uint32_t FWNK1UI_MAX; /*!< 0x084 */ - __IO uint32_t FWNK1UI_MIN; /*!< 0x088 */ - __IO uint32_t FWNK1_PIDOUT_LIM;/*!< 0x08C */ - __IO uint32_t PLL1ERR1; /*!< 0x090 */ - __IO uint32_t PLL1KP; /*!< 0x094 */ - __IO uint32_t PLL1KI; /*!< 0x098 */ - __IO uint32_t PLL1KD; /*!< 0x09C */ - __IO uint32_t PLL1UI1; /*!< 0x0A0 */ - __IO uint32_t PLL1UI_MAX; /*!< 0x0A4 */ - __IO uint32_t PLL1UI_MIN; /*!< 0x0A8 */ - __IO uint32_t PLL1_PIDOUT_LIM; /*!< 0x0AC */ - __IO uint32_t USR1ERR1; /*!< 0x0B0 */ - __IO uint32_t USR1KP; /*!< 0x0B4 */ - __IO uint32_t USR1KI; /*!< 0x0B8 */ - __IO uint32_t USR1KD; /*!< 0x0BC */ - __IO uint32_t USR1UI1; /*!< 0x0C0 */ - __IO uint32_t USR1UI_MAX; /*!< 0x0C4 */ - __IO uint32_t USR1UI_MIN; /*!< 0x0C8 */ - __IO uint32_t USR1_PIDOUT_LIM; /*!< 0x0CC */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t IFIVR; /*!< 0x004 Integral Function Input Value Register */ + __IO uint32_t EIVR; /*!< 0x008 Error Input Value Register */ + __IO uint32_t ORR; /*!< 0x00C Output Result Register */ + HT_PIDPARA_TypeDef SPD; /*!< 0x010 - 0x02C SPD Mode */ + HT_PIDPARA_TypeDef IQ; /*!< 0x030 - 0x04C IQ Mode */ + HT_PIDPARA_TypeDef ID; /*!< 0x050 - 0x06C ID Mode */ + HT_PIDPARA_TypeDef FWNK; /*!< 0x070 - 0x08C FWNK Mode */ + HT_PIDPARA_TypeDef PLL; /*!< 0x090 - 0x0AC PLL Mode */ + HT_PIDPARA_TypeDef USR; /*!< 0x0B0 - 0x0CC USR Mode */ } HT_PID_TypeDef; /** * @} */ + /** * @brief RF */ @@ -2132,7 +2109,7 @@ typedef struct #define HT_DIV_BASE (HT_AHBPERIPH_BASE + 0x4A000) /* 0x400CA000 */ #define HT_RF_BASE (HT_AHBPERIPH_BASE + 0x50000) /* 0x400D0000 */ #define HT_CORDIC_BASE (HT_AHBPERIPH_BASE + 0x5C000) /* 0x400DC000 */ -#define HT_PID_BASE (HT_AHBPERIPH_BASE + 0x5E000) /* 0x400DE000 */ +#define HT_PID0_BASE (HT_AHBPERIPH_BASE + 0x5E000) /* 0x400DE000 */ #define HT_QSPI_BASE (HT_AHBPERIPH_BASE + 0x60000) /* 0x400E0000 */ /** @@ -2596,7 +2573,7 @@ typedef struct #define HT_PGA2 ((HT_PGA0_X_TypeDef *) HT_PGA2_BASE) #define HT_PGA3 ((HT_PGA0_X_TypeDef *) HT_PGA3_BASE) #define HT_PGA ((HT_PGA_TypeDef *) HT_PGA_BASE) -#define HT_PID ((HT_LCD_TypeDef *) HT_LCD_BASE) +#define HT_PID0 ((HT_PID_TypeDef *) HT_PID0_BASE) #define HT_CORDIC ((HT_CORDIC_TypeDef *) HT_CORDIC_BASE) #define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) @@ -2618,7 +2595,7 @@ typedef struct #define HT_PGA2 ((HT_PGA0_X_TypeDef *) HT_PGA2_BASE) #define HT_PGA3 ((HT_PGA0_X_TypeDef *) HT_PGA3_BASE) #define HT_PGA ((HT_PGA_TypeDef *) HT_PGA_BASE) -#define HT_PID ((HT_LCD_TypeDef *) HT_LCD_BASE) +#define HT_PID0 ((HT_PID_TypeDef *) HT_PID0_BASE) #define HT_CORDIC ((HT_CORDIC_TypeDef *) HT_CORDIC_BASE) #define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) @@ -2689,14 +2666,14 @@ typedef struct #define UART3_IRQn UART1_UART3_IRQn #endif -#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) // Alias #define GPTM0_IRQn GPTM0_G_IRQn #define GPTM0_IRQHandler GPTM0_G_IRQHandler #define MCTM0_IRQn MCTM0_UP_IRQn - #define MCTM0_IRQHandler MCTM0_G_IRQHandler + #define MCTM0_IRQHandler MCTM0_UP_IRQHandler #define MCTM1_IRQn MCTM1_UP_IRQn - #define MCTM1_IRQHandler MCTM1_G_IRQHandler + #define MCTM1_IRQHandler MCTM1_UP_IRQHandler #endif #define AFIO_ESS_Enum u32 diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s index a86606d966..23655e6b12 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7648 $ +; Date : $Date:: 2024-03-20 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,7 +19,6 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,7 +33,6 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. @@ -47,7 +45,6 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 HT32F50220_30 EQU 7 @@ -56,7 +53,6 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 IF USE_HT32_CHIP_SET=0 @@ -72,13 +68,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +307,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +322,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s index e0b5ba76e2..1c93c451be 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_07.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -52,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -277,10 +288,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -291,11 +303,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s index db72cb363f..239d45c26f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_03.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -60,13 +60,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -376,10 +387,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -390,11 +402,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s index 45853e20f1..f5c17e8bae 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -26,6 +26,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -33,10 +34,12 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050030 ;_HT32FWID EQU 0x00061630 ;_HT32FWID EQU 0x00061030 +;_HT32FWID EQU 0x00061730 HT32F50020_30 EQU 25 HT32F61630 EQU 25 HT32F61030 EQU 25 +HT32F61730 EQU 25 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -51,13 +54,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-2048:8> Heap_Size EQU 0 @@ -208,10 +222,11 @@ LEDC_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -222,11 +237,19 @@ LEDC_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s index a86606d966..40fff3b7bd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s index 8e68952909..3c1522bed8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s index 1a58d66e73..eb2c66aeba 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_06.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,13 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-12288:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-12288:8> Heap_Size EQU 0 @@ -271,10 +282,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -285,11 +297,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s index be3f3ca0f7..c1ecefc896 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_14.s -; Version : $Rev:: 6793 $ -; Date : $Date:: 2023-03-14 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 USE_HT32_CHIP_SET EQU 30 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -31,9 +33,11 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050452 ;_HT32FWID EQU 0x00050431 ;_HT32FWID EQU 0x00050441 +;_HT32FWID EQU 0x00061052 HT32F50442_52 EQU 26 HT32F50431_41 EQU 30 +HT32F61052 EQU 26 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -48,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -237,10 +252,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -251,11 +267,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s index 214cdf9e32..152ae6ca6f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_14.s -; Version : $Rev:: 6793 $ -; Date : $Date:: 2023-03-14 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 USE_HT32_CHIP_SET EQU 26 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -31,9 +33,11 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050452 ;_HT32FWID EQU 0x00050431 ;_HT32FWID EQU 0x00050441 +;_HT32FWID EQU 0x00061052 HT32F50442_52 EQU 26 HT32F50431_41 EQU 30 +HT32F61052 EQU 26 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -48,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -237,10 +252,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -251,11 +267,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s index db72cb363f..239d45c26f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_03.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -60,13 +60,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -376,10 +387,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -390,11 +402,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s index ae562b2a89..1b71dcbac4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s index c653285b1f..ff7688a37f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s index 9f80e3bd0e..e1a1b740e3 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_17.s -; Version : $Rev:: 7027 $ -; Date : $Date:: 2023-07-18 #$ +; Version : $Rev:: 7718 $ +; Date : $Date:: 2024-05-13 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -21,14 +21,14 @@ ;// Select HT32 Device for the assembly setting. ;// Notice that the project's Asm Define has the higher priority. ;// <0=> By Project Asm Define -;// <33=> HT32F52234/44 -USE_HT32_CHIP_SET EQU 33 ; Notice that the project's Asm Define has the higher priority. +;// <35=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 35 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00052234 ;_HT32FWID EQU 0x00052244 -HT32F52234_44 EQU 33 +HT32F52234_44 EQU 35 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -43,13 +43,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -212,10 +223,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -226,11 +238,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s index e9b3a2c194..7ece1c101a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 5 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s index 8cd61fd13a..39d0d94d15 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 3 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s index 2285fed9c8..536d5252d5 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s index e745eaa803..a7fa970bc7 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_03.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -60,13 +60,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -376,10 +387,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -390,11 +402,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s index 4533138d12..ea3bd5c1dd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_03.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -60,13 +60,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -376,10 +387,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -390,11 +402,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s index e1bc80febe..46d1ded0b4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_15.s -; Version : $Rev:: 6874 $ -; Date : $Date:: 2023-05-03 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -48,13 +48,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -239,10 +250,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -253,11 +265,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s index f4dbd9cf62..3afd815b48 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_15.s -; Version : $Rev:: 6874 $ -; Date : $Date:: 2023-05-03 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -48,13 +48,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -239,10 +250,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -253,11 +265,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s index 5db17956e7..2d239879ac 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_09.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -48,13 +48,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -316,10 +327,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -330,11 +342,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s index 657d0d6523..44e996c83b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_09.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -48,13 +48,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -316,10 +327,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -330,11 +342,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s index cbaf7f3ee1..b545bc467b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s index b1d916864c..82c72c182b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57541.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57541.s new file mode 100644 index 0000000000..b545bc467b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57541.s @@ -0,0 +1,378 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +; HT32F57541 +; HT32F57552 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57552.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57552.s new file mode 100644 index 0000000000..82c72c182b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57552.s @@ -0,0 +1,378 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +; HT32F57541 +; HT32F57552 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 +USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s index eba919c13e..f4501184d1 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5826.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7596 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,25 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp - -;// Heap Size (in Bytes) <0-16384:8> -Heap_Size EQU 0 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__HT_check_heap -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB + ENDIF ;******************************************************************************* ; Fill-up the Vector Table entries with the exceptions ISR address @@ -284,10 +283,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -298,11 +298,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s index b1d916864c..82c72c182b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s index 8e68952909..3c1522bed8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59045.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59045.s new file mode 100644 index 0000000000..ff7688a37f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59045.s @@ -0,0 +1,520 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT50F3200U +; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 +; HT32F67741 +; HT32F67232 +; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT50F3200U +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT50F3200U EQU 2 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F62140 EQU 2 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s index cbaf7f3ee1..b545bc467b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s index cbaf7f3ee1..b545bc467b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s index b11048b5e0..05c1c11636 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s index de2009c868..0dd429e152 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s index 1ff2f77f4b..015d5a46df 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_03.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -60,13 +60,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -376,10 +387,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -390,11 +402,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s index 842644ceee..6e05ca4bfd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s index bf17a58ce7..780374807b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_06.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,13 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-12288:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-12288:8> Heap_Size EQU 0 @@ -271,10 +282,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -285,11 +297,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s index 10f210c5a2..b23401ff33 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_07.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -52,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -277,10 +288,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -291,11 +303,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s index 24cf68758d..6ffff354d8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_08.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s index 089c851eb1..1d2eedce91 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_09.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -48,13 +48,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -316,10 +327,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -330,11 +342,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s index 57fb44e314..d28f4c4e8c 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s @@ -6,14 +6,15 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_10.s -; Version : $Rev:: 5783 $ -; Date : $Date:: 2022-03-30 #$ +; Version : $Rev:: 8105 $ +; Date : $Date:: 2024-09-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ ; Supported Device ; ======================================== ; HT32F61244, HT32F61245 +; NW32F61242 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -22,13 +23,16 @@ ;// Notice that the project's Asm Define has the higher priority. ;// <0=> By Project Asm Define ;// <24=> HT32F61244/45 +;// <24=> NW32F61242 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00061244 ;_HT32FWID EQU 0x00061245 +;_HT32FWID EQU 0x00061242 HT32F61244_45 EQU 24 +NW32F61242 EQU 24 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -43,13 +47,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -208,10 +223,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -222,11 +238,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s index 784096cf66..5c6c48a1c4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_11.s -; Version : $Rev:: 5991 $ -; Date : $Date:: 2022-06-23 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -43,13 +43,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -218,10 +229,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -232,11 +244,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s index 45e5c70109..6a24f616fb 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_12.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,13 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ USB_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ USB_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s index f03c345a43..feec236f33 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -26,6 +27,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -33,10 +35,12 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050030 ;_HT32FWID EQU 0x00061630 ;_HT32FWID EQU 0x00061030 +;_HT32FWID EQU 0x00061730 HT32F50020_30 EQU 25 HT32F61630 EQU 25 HT32F61030 EQU 25 +HT32F61730 EQU 25 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -51,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-2048:8> Heap_Size EQU 0 @@ -208,10 +223,11 @@ LEDC_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -222,11 +238,19 @@ LEDC_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s index a76b5da417..224232f9c7 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_14.s -; Version : $Rev:: 6793 $ -; Date : $Date:: 2023-03-14 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -31,9 +33,11 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050452 ;_HT32FWID EQU 0x00050431 ;_HT32FWID EQU 0x00050441 +;_HT32FWID EQU 0x00061052 HT32F50442_52 EQU 26 HT32F50431_41 EQU 30 +HT32F61052 EQU 26 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -48,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -237,10 +252,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -251,11 +267,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s index e261fa6021..0d440d350a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_15.s -; Version : $Rev:: 6874 $ -; Date : $Date:: 2023-05-03 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -48,13 +48,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -239,10 +250,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -253,11 +265,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s index 23328ec7c4..b3aa7a1215 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_16.s -; Version : $Rev:: 7092 $ -; Date : $Date:: 2023-08-02 #$ +; Version : $Rev:: 8260 $ +; Date : $Date:: 2024-11-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ _HT32FWID EQU 0x00066242 ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -124,7 +135,7 @@ __Vectors DCD BFTM1_IRQHandler ; 17, 33, 0x084, DCD CMP0_IRQHandler ; 18, 34, 0x088, DCD CMP1_IRQHandler ; 19, 35, 0x08C, - DCD PID_IRQHandler ; 20, 36, 0x090, + DCD PID0_IRQHandler ; 20, 36, 0x090, DCD I2C0_IRQHandler ; 21, 37, 0x094, DCD SPI0_IRQHandler ; 22, 38, 0x098, DCD USART0_IRQHandler ; 23, 39, 0x09C, @@ -195,7 +206,7 @@ Default_Handler PROC EXPORT BFTM1_IRQHandler [WEAK] EXPORT CMP0_IRQHandler [WEAK] EXPORT CMP1_IRQHandler [WEAK] - EXPORT PID_IRQHandler [WEAK] + EXPORT PID0_IRQHandler [WEAK] EXPORT I2C0_IRQHandler [WEAK] EXPORT SPI0_IRQHandler [WEAK] EXPORT USART0_IRQHandler [WEAK] @@ -228,7 +239,7 @@ BFTM0_IRQHandler BFTM1_IRQHandler CMP0_IRQHandler CMP1_IRQHandler -PID_IRQHandler +PID0_IRQHandler I2C0_IRQHandler SPI0_IRQHandler USART0_IRQHandler @@ -248,10 +259,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -262,11 +274,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s index 0829021a82..6187c06586 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_17.s -; Version : $Rev:: 7027 $ -; Date : $Date:: 2023-07-18 #$ +; Version : $Rev:: 7718 $ +; Date : $Date:: 2024-05-13 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -21,14 +21,14 @@ ;// Select HT32 Device for the assembly setting. ;// Notice that the project's Asm Define has the higher priority. ;// <0=> By Project Asm Define -;// <33=> HT32F52234/44 +;// <35=> HT32F52234/44 USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00052234 ;_HT32FWID EQU 0x00052244 -HT32F52234_44 EQU 33 +HT32F52234_44 EQU 35 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -43,13 +43,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -212,10 +223,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -226,11 +238,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s index 45853e20f1..e6e528a050 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -26,6 +27,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -33,10 +35,12 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050030 ;_HT32FWID EQU 0x00061630 ;_HT32FWID EQU 0x00061030 +;_HT32FWID EQU 0x00061730 HT32F50020_30 EQU 25 HT32F61630 EQU 25 HT32F61030 EQU 25 +HT32F61730 EQU 25 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -51,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-2048:8> Heap_Size EQU 0 @@ -208,10 +223,11 @@ LEDC_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -222,11 +238,19 @@ LEDC_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s index 8e68952909..3c1522bed8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61052.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61052.s new file mode 100644 index 0000000000..152ae6ca6f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61052.s @@ -0,0 +1,288 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +; HT32F61052 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +;// <26=> HT32F61052 +USE_HT32_CHIP_SET EQU 26 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 +;_HT32FWID EQU 0x00061052 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 +HT32F61052 EQU 26 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s index e01651cc14..90ccad9f98 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_12.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -42,13 +42,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ USB_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ USB_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s index 5477d2e255..8150b2440a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s @@ -6,14 +6,15 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_10.s -; Version : $Rev:: 5783 $ -; Date : $Date:: 2022-03-30 #$ +; Version : $Rev:: 8105 $ +; Date : $Date:: 2024-09-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ ; Supported Device ; ======================================== ; HT32F61244, HT32F61245 +; NW32F61242 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -22,13 +23,16 @@ ;// Notice that the project's Asm Define has the higher priority. ;// <0=> By Project Asm Define ;// <24=> HT32F61244/45 +;// <24=> NW32F61242 USE_HT32_CHIP_SET EQU 24 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00061244 ;_HT32FWID EQU 0x00061245 +;_HT32FWID EQU 0x00061242 HT32F61244_45 EQU 24 +NW32F61242 EQU 24 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -43,13 +47,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -208,10 +223,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -222,11 +238,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s index e0b5ba76e2..1c93c451be 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_07.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -52,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -277,10 +288,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -291,11 +303,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s index 418bcfd86f..bb34fecd2a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_07.s -; Version : $Rev:: 5740 $ -; Date : $Date:: 2022-02-17 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -52,13 +52,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -277,10 +288,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -291,11 +303,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s index 45853e20f1..e6e528a050 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -26,6 +27,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -33,10 +35,12 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050030 ;_HT32FWID EQU 0x00061630 ;_HT32FWID EQU 0x00061030 +;_HT32FWID EQU 0x00061730 HT32F50020_30 EQU 25 HT32F61630 EQU 25 HT32F61030 EQU 25 +HT32F61730 EQU 25 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -51,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-2048:8> Heap_Size EQU 0 @@ -208,10 +223,11 @@ LEDC_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -222,11 +238,19 @@ LEDC_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s index 8e68952909..3c1522bed8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61730.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61730.s new file mode 100644 index 0000000000..e6e528a050 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61730.s @@ -0,0 +1,259 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +; HT32F61730 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +;// <25=> HT32F61730 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 +;_HT32FWID EQU 0x00061730 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 +HT32F61730 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61741.s new file mode 100644 index 0000000000..3c1522bed8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61741.s @@ -0,0 +1,347 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F61041 +; HT32F61741 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F61041 +;// <8=> HT32F61741 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F61041 EQU 8 +HT32F61741 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s index ae562b2a89..1b71dcbac4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s index c653285b1f..ff7688a37f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s index e9b3a2c194..7ece1c101a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 5 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62140.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62140.s new file mode 100644 index 0000000000..ff7688a37f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62140.s @@ -0,0 +1,520 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT50F3200U +; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 +; HT32F67741 +; HT32F67232 +; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT50F3200U +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT50F3200U EQU 2 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F62140 EQU 2 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s index b986536809..204d6a2150 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_08.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s index 0ec4ece850..5b0c20ca24 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_08.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s index d2f753c115..77dafb95e9 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_16.s -; Version : $Rev:: 7092 $ -; Date : $Date:: 2023-08-02 #$ +; Version : $Rev:: 7599 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ _HT32FWID EQU 0x00066242 ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -124,7 +135,7 @@ __Vectors DCD BFTM1_IRQHandler ; 17, 33, 0x084, DCD CMP0_IRQHandler ; 18, 34, 0x088, DCD CMP1_IRQHandler ; 19, 35, 0x08C, - DCD PID_IRQHandler ; 20, 36, 0x090, + DCD PID0_IRQHandler ; 20, 36, 0x090, DCD I2C0_IRQHandler ; 21, 37, 0x094, DCD SPI0_IRQHandler ; 22, 38, 0x098, DCD USART0_IRQHandler ; 23, 39, 0x09C, @@ -195,7 +206,7 @@ Default_Handler PROC EXPORT BFTM1_IRQHandler [WEAK] EXPORT CMP0_IRQHandler [WEAK] EXPORT CMP1_IRQHandler [WEAK] - EXPORT PID_IRQHandler [WEAK] + EXPORT PID0_IRQHandler [WEAK] EXPORT I2C0_IRQHandler [WEAK] EXPORT SPI0_IRQHandler [WEAK] EXPORT USART0_IRQHandler [WEAK] @@ -228,7 +239,7 @@ BFTM0_IRQHandler BFTM1_IRQHandler CMP0_IRQHandler CMP1_IRQHandler -PID_IRQHandler +PID0_IRQHandler I2C0_IRQHandler SPI0_IRQHandler USART0_IRQHandler @@ -248,10 +259,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -262,11 +274,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s index 9a02335cc6..fd226bf9c2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_16.s -; Version : $Rev:: 7092 $ -; Date : $Date:: 2023-08-02 #$ +; Version : $Rev:: 7599 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ _HT32FWID EQU 0x00066242 ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -124,7 +135,7 @@ __Vectors DCD BFTM1_IRQHandler ; 17, 33, 0x084, DCD CMP0_IRQHandler ; 18, 34, 0x088, DCD CMP1_IRQHandler ; 19, 35, 0x08C, - DCD PID_IRQHandler ; 20, 36, 0x090, + DCD PID0_IRQHandler ; 20, 36, 0x090, DCD I2C0_IRQHandler ; 21, 37, 0x094, DCD SPI0_IRQHandler ; 22, 38, 0x098, DCD USART0_IRQHandler ; 23, 39, 0x09C, @@ -195,7 +206,7 @@ Default_Handler PROC EXPORT BFTM1_IRQHandler [WEAK] EXPORT CMP0_IRQHandler [WEAK] EXPORT CMP1_IRQHandler [WEAK] - EXPORT PID_IRQHandler [WEAK] + EXPORT PID0_IRQHandler [WEAK] EXPORT I2C0_IRQHandler [WEAK] EXPORT SPI0_IRQHandler [WEAK] EXPORT USART0_IRQHandler [WEAK] @@ -228,7 +239,7 @@ BFTM0_IRQHandler BFTM1_IRQHandler CMP0_IRQHandler CMP1_IRQHandler -PID_IRQHandler +PID0_IRQHandler I2C0_IRQHandler SPI0_IRQHandler USART0_IRQHandler @@ -248,10 +259,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -262,11 +274,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s index 13c68a18ec..8035d2c44a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_11.s -; Version : $Rev:: 5991 $ -; Date : $Date:: 2022-06-23 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -43,13 +43,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -218,10 +229,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -232,11 +244,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s index ae562b2a89..1b71dcbac4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s index ae562b2a89..1b71dcbac4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s index c653285b1f..ff7688a37f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s index cbaf7f3ee1..b545bc467b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -43,6 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -50,6 +56,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -64,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -323,10 +342,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -337,11 +357,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s index a86606d966..40fff3b7bd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -47,8 +47,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -56,8 +56,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -72,13 +72,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-4096:8> Heap_Size EQU 0 @@ -300,10 +311,11 @@ UART1_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -314,11 +326,19 @@ UART1_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s index 2285fed9c8..536d5252d5 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. _HT32FWID EQU 0xFFFFFFFF @@ -69,12 +79,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -86,12 +99,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ; Use project's Asm Define setting (default) @@ -106,13 +124,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -455,10 +484,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -469,11 +499,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s index b986536809..204d6a2150 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_08.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s index 4533138d12..ea3bd5c1dd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_03.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7594 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -60,13 +60,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-16384:8> Heap_Size EQU 0 @@ -376,10 +387,11 @@ PDMA_CH2_5_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -390,11 +402,19 @@ PDMA_CH2_5_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200u.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200u.s new file mode 100644 index 0000000000..ff7688a37f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200u.s @@ -0,0 +1,520 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT50F3200U +; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 +; HT32F67741 +; HT32F67232 +; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT50F3200U +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT50F3200U EQU 2 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F62140 EQU 2 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52231.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52231.s new file mode 100644 index 0000000000..ff7688a37f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52231.s @@ -0,0 +1,520 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT50F3200U +; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 +; HT32F67741 +; HT32F67232 +; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT50F3200U +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT50F3200U EQU 2 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F62140 EQU 2 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52352.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52352.s new file mode 100644 index 0000000000..536d5252d5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx52352.s @@ -0,0 +1,520 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT50F3200U +; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 +; HT32F67741 +; HT32F67232 +; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT50F3200U +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 +USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT50F3200U EQU 2 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F62140 EQU 2 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s index b986536809..204d6a2150 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_08.s -; Version : $Rev:: 6877 $ -; Date : $Date:: 2023-05-04 #$ +; Version : $Rev:: 7595 $ +; Date : $Date:: 2024-02-23 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -55,13 +55,24 @@ USE_HT32_CHIP EQU USE_HT32_CHIP_SET ; Amount of memory (in bytes) allocated for Stack and Heap ; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + ;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). Stack_Size EQU 512 AREA STACK, NOINIT, READWRITE, ALIGN = 3 __HT_check_sp Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE __initial_sp + ENDIF ;// Heap Size (in Bytes) <0-8192:8> Heap_Size EQU 0 @@ -251,10 +262,11 @@ SCTM3_IRQHandler ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* - IF :DEF:__MICROLIB - EXPORT __HT_check_heap EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -265,11 +277,19 @@ SCTM3_IRQHandler EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDIF ALIGN diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_nw32f61242.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_nw32f61242.s new file mode 100644 index 0000000000..8150b2440a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_nw32f61242.s @@ -0,0 +1,259 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_10.s +; Version : $Rev:: 8105 $ +; Date : $Date:: 2024-09-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +; NW32F61242 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +;// <24=> NW32F61242 +USE_HT32_CHIP_SET EQU 24 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 +;_HT32FWID EQU 0x00061242 + +HT32F61244_45 EQU 24 +NW32F61242 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs + +;// Stack Location +;// <0=> After the RW/ZI/Heap (Default) +;// <1=> On the top of the SRAM (The end of the SRAM) +USE_STACK_ON_TOP EQU 0 + +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +;// Only meanful when the Stack Location = "After the RW/ZI/Heap" (USE_STACK_ON_TOP = 0). +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size + IF (USE_STACK_ON_TOP = 1) +__initial_sp EQU 0x20000000 + USE_LIBCFG_RAM_SIZE + ELSE +__initial_sp + ENDIF + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + EXPORT __HT_check_heap + EXPORT __HT_check_sp + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + IF (USE_STACK_ON_TOP = 1) + LDR R0, = Heap_Mem + LDR R1, = (0x20000000 + USE_LIBCFG_RAM_SIZE) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = (Heap_Mem + Heap_Size) + BX LR + ELSE + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s index 13adc8cdcc..f3f551a4c2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -24,10 +24,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 */ .equ USE_HT32_CHIP_SET, 0 @@ -71,12 +81,15 @@ .equ _HT32FWID, 0x00000006 .equ _HT32FWID, 0x00061352 .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x0003200F .equ _HT32FWID, 0x00062030 .equ _HT32FWID, 0x00062040 .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00062140 .equ _HT32FWID, 0x00067741 .equ _HT32FWID, 0x00067232 - .equ _HT32FWID, 0x00067233 + .equ _HT32FWID, 0x00067233 + .equ _HT32FWID, 0x00059045 */ .equ HT32F52220_30, 1 @@ -89,12 +102,17 @@ .equ HT32F0006, 10 .equ HT32F61352, 10 .equ HT50F32003, 4 + .equ HT50F3200U, 2 .equ HT32F62030, 1 .equ HT32F62040, 2 .equ HT32F62050, 5 + .equ HT32F62140, 2 .equ HT32F67741, 2 .equ HT32F67232, 1 .equ HT32F67233, 1 + .equ HT32F59045, 2 + .equ MXTX52231, 2 + .equ MXTX52352, 4 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s index 1521f84226..f35f677f24 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -20,8 +20,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 */ .equ USE_HT32_CHIP_SET, 0 @@ -49,8 +49,8 @@ .equ _HT32FWID, 0x00059041 .equ _HT32FWID, 0x000F5032 .equ _HT32FWID, 0x00061641 - .equ _HT32FWID, 0x00059046 .equ _HT32FWID, 0x00061041 + .equ _HT32FWID, 0x00061741 */ .equ HT32F50220_30, 7 @@ -59,8 +59,8 @@ .equ HT32F59041, 8 .equ HF5032, 7 .equ HT32F61641, 8 - .equ HT32F59046, 8 .equ HT32F61041, 8 + .equ HT32F61741, 8 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s index 1618d4b1c0..4bf6a4bba2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -20,6 +20,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 */ .equ USE_HT32_CHIP_SET, 0 @@ -45,6 +49,8 @@ .equ _HT32FWID, 0x00005828 .equ _HT32FWID, 0x00067742 .equ _HT32FWID, 0x00059746 + .equ _HT32FWID, 0x00057541 + .equ _HT32FWID, 0x00057552 */ .equ HT32F57331_41, 13 @@ -53,6 +59,8 @@ .equ HT32F5828, 14 .equ HT32F67742, 13 .equ HT32F59746, 13 + .equ HT32F57541, 13 + .equ HT32F57552, 14 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s index c2fb7bd028..486ddf7400 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_10.s -; Version : $Rev:: 6601 $ -; Date : $Date:: 2022-12-27 #$ +; Version : $Rev:: 8101 $ +; Date : $Date:: 2024-09-04 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; Supported Device ; ======================================== ; HT32F61244, HT32F61245 +; NW32F61242 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -22,6 +23,7 @@ ;// HT32 Device ;// <0=> By Project Asm Define ;// <24=> HT32F61244/45 +;// <24=> NW32F61242 */ .equ USE_HT32_CHIP_SET, 0 @@ -29,9 +31,11 @@ /* .equ _HT32FWID, 0x00061244 .equ _HT32FWID, 0x00061245 + .equ _HT32FWID, 0x00061242 */ .equ HT32F61244_45, 24 + .equ NW32F61242, 24 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s index 649b402684..d8e743f9c3 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -17,6 +17,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -26,6 +27,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 */ .equ USE_HT32_CHIP_SET, 0 @@ -35,11 +37,13 @@ .equ _HT32FWID, 0x00050030 .equ _HT32FWID, 0x00061630 .equ _HT32FWID, 0x00061030 + .equ _HT32FWID, 0x00061730 */ .equ HT32F50020_30, 25 .equ HT32F61630, 25 .equ HT32F61030, 25 + .equ HT32F61730, 25 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s index 335d485622..a4c44a90e7 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_14.s -; Version : $Rev:: 6793 $ -; Date : $Date:: 2023-03-14 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 */ .equ USE_HT32_CHIP_SET, 0 @@ -33,10 +35,12 @@ .equ _HT32FWID, 0x00050452 .equ _HT32FWID, 0x00050431 .equ _HT32FWID, 0x00050441 + .equ _HT32FWID, 0x00061052 */ .equ HT32F50442_52, 26 .equ HT32F50431_41, 30 + .equ HT32F61052, 26 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s index 01f644a0a3..710e4a36d2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_16.s -; Version : $Rev:: 7094 $ -; Date : $Date:: 2023-08-02 #$ +; Version : $Rev:: 8260 $ +; Date : $Date:: 2024-11-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -138,7 +138,7 @@ __cs3_interrupt_vector_cortex_m: .long BFTM1_IRQHandler /* 17, 33, 0x084, */ .long CMP0_IRQHandler /* 18, 34, 0x088, */ .long CMP1_IRQHandler /* 19, 35, 0x08C, */ - .long PID_IRQHandler /* 20, 36, 0x090, */ + .long PID0_IRQHandler /* 20, 36, 0x090, */ .long I2C0_IRQHandler /* 21, 37, 0x094, */ .long SPI0_IRQHandler /* 22, 38, 0x098, */ .long USART0_IRQHandler /* 23, 39, 0x09C, */ @@ -243,7 +243,7 @@ Default_Handler: IRQ BFTM1_IRQHandler IRQ CMP0_IRQHandler IRQ CMP1_IRQHandler - IRQ PID_IRQHandler + IRQ PID0_IRQHandler IRQ I2C0_IRQHandler IRQ SPI0_IRQHandler IRQ USART0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s index 47dac68db7..07095a16a0 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_cs3_17.s -; Version : $Rev:: 7030 $ -; Date : $Date:: 2023-07-18 #$ +; Version : $Rev:: 7718 $ +; Date : $Date:: 2024-05-13 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -21,7 +21,7 @@ /* ;// HT32 Device ;// <0=> By Project Asm Define -;// <33=> HT32F52234/44 +;// <35=> HT32F52234/44 */ .equ USE_HT32_CHIP_SET, 0 @@ -31,7 +31,7 @@ .equ _HT32FWID, 0x00052244 */ - .equ HT32F52234_44, 33 + .equ HT32F52234_44, 35 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s index 6ef935fb93..7dcf618302 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -24,10 +24,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 */ .equ USE_HT32_CHIP_SET, 0 @@ -71,12 +81,15 @@ .equ _HT32FWID, 0x00000006 .equ _HT32FWID, 0x00061352 .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x0003200F .equ _HT32FWID, 0x00062030 .equ _HT32FWID, 0x00062040 .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00062140 .equ _HT32FWID, 0x00067741 .equ _HT32FWID, 0x00067232 - .equ _HT32FWID, 0x00067233 + .equ _HT32FWID, 0x00067233 + .equ _HT32FWID, 0x00059045 */ .equ HT32F52220_30, 1 @@ -89,12 +102,17 @@ .equ HT32F0006, 10 .equ HT32F61352, 10 .equ HT50F32003, 4 + .equ HT50F3200U, 2 .equ HT32F62030, 1 .equ HT32F62040, 2 .equ HT32F62050, 5 + .equ HT32F62140, 2 .equ HT32F67741, 2 .equ HT32F67232, 1 .equ HT32F67233, 1 + .equ HT32F59045, 2 + .equ MXTX52231, 2 + .equ MXTX52352, 4 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s index 784c9cef99..b215d283ac 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -20,8 +20,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 */ .equ USE_HT32_CHIP_SET, 0 @@ -49,8 +49,8 @@ .equ _HT32FWID, 0x00059041 .equ _HT32FWID, 0x000F5032 .equ _HT32FWID, 0x00061641 - .equ _HT32FWID, 0x00059046 .equ _HT32FWID, 0x00061041 + .equ _HT32FWID, 0x00061741 */ .equ HT32F50220_30, 7 @@ -59,8 +59,8 @@ .equ HT32F59041, 8 .equ HF5032, 7 .equ HT32F61641, 8 - .equ HT32F59046, 8 .equ HT32F61041, 8 + .equ HT32F61741, 8 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s index 5aba9e9f48..1ae1798863 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -20,6 +20,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 */ .equ USE_HT32_CHIP_SET, 0 @@ -45,6 +49,8 @@ .equ _HT32FWID, 0x00005828 .equ _HT32FWID, 0x00067742 .equ _HT32FWID, 0x00059746 + .equ _HT32FWID, 0x00057541 + .equ _HT32FWID, 0x00057552 */ .equ HT32F57331_41, 13 @@ -53,6 +59,8 @@ .equ HT32F5828, 14 .equ HT32F67742, 13 .equ HT32F59746, 13 + .equ HT32F57541, 13 + .equ HT32F57552, 14 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s index d6688b4441..ab52e8f7b0 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_10.s -; Version : $Rev:: 6601 $ -; Date : $Date:: 2022-12-27 #$ +; Version : $Rev:: 8101 $ +; Date : $Date:: 2024-09-04 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; Supported Device ; ======================================== ; HT32F61244, HT32F61245 +; NW32F61242 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -22,6 +23,7 @@ ;// HT32 Device ;// <0=> By Project Asm Define ;// <24=> HT32F61244/45 +;// <24=> NW32F61242 */ .equ USE_HT32_CHIP_SET, 0 @@ -29,9 +31,11 @@ /* .equ _HT32FWID, 0x00061244 .equ _HT32FWID, 0x00061245 + .equ _HT32FWID, 0x00061242 */ .equ HT32F61244_45, 24 + .equ NW32F61242, 24 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s index 1d5b8a33b1..869e7f3537 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -17,6 +17,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -26,6 +27,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 */ .equ USE_HT32_CHIP_SET, 0 @@ -35,11 +37,13 @@ .equ _HT32FWID, 0x00050030 .equ _HT32FWID, 0x00061630 .equ _HT32FWID, 0x00061030 + .equ _HT32FWID, 0x00061730 */ .equ HT32F50020_30, 25 .equ HT32F61630, 25 .equ HT32F61030, 25 + .equ HT32F61730, 25 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s index 9a02b727d9..43ed571266 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_14.s -; Version : $Rev:: 6838 $ -; Date : $Date:: 2023-04-06 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 */ .equ USE_HT32_CHIP_SET, 0 @@ -33,10 +35,12 @@ .equ _HT32FWID, 0x00050452 .equ _HT32FWID, 0x00050431 .equ _HT32FWID, 0x00050441 + .equ _HT32FWID, 0x00061052 */ .equ HT32F50442_52, 26 .equ HT32F50431_41, 30 + .equ HT32F61052, 26 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s index 8cb1f85b48..12f0e3127f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_16.s -; Version : $Rev:: 7094 $ -; Date : $Date:: 2023-08-02 #$ +; Version : $Rev:: 8260 $ +; Date : $Date:: 2024-11-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -162,7 +162,7 @@ __interrupt_vector_cortex_m: .long BFTM1_IRQHandler /* 17, 33, 0x084, */ .long CMP0_IRQHandler /* 18, 34, 0x088, */ .long CMP1_IRQHandler /* 19, 35, 0x08C, */ - .long PID_IRQHandler /* 20, 36, 0x090, */ + .long PID0_IRQHandler /* 20, 36, 0x090, */ .long I2C0_IRQHandler /* 21, 37, 0x094, */ .long SPI0_IRQHandler /* 22, 38, 0x098, */ .long USART0_IRQHandler /* 23, 39, 0x09C, */ @@ -301,7 +301,7 @@ Default_Handler: IRQ BFTM1_IRQHandler IRQ CMP0_IRQHandler IRQ CMP1_IRQHandler - IRQ PID_IRQHandler + IRQ PID0_IRQHandler IRQ I2C0_IRQHandler IRQ SPI0_IRQHandler IRQ USART0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s index f19b45b36f..2f8ef4ead2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_gcc_17.s -; Version : $Rev:: 7030 $ -; Date : $Date:: 2023-07-18 #$ +; Version : $Rev:: 7718 $ +; Date : $Date:: 2024-05-13 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -21,7 +21,7 @@ /* ;// HT32 Device ;// <0=> By Project Asm Define -;// <33=> HT32F52234/44 +;// <35=> HT32F52234/44 */ .equ USE_HT32_CHIP_SET, 0 @@ -31,7 +31,7 @@ .equ _HT32FWID, 0x00052244 */ - .equ HT32F52234_44, 33 + .equ HT32F52234_44, 35 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s index 1fc4bed7a6..e1179462c6 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -23,10 +23,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -42,12 +47,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF @@ -67,12 +77,15 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000006 ;_HT32FWID EQU 0x00061352 ;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x0003200F ;_HT32FWID EQU 0x00062030 ;_HT32FWID EQU 0x00062040 ;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00062140 ;_HT32FWID EQU 0x00067741 ;_HT32FWID EQU 0x00067232 ;_HT32FWID EQU 0x00067233 +;_HT32FWID EQU 0x00059045 HT32F52220_30 EQU 1 HT32F52231_41 EQU 2 @@ -84,12 +97,17 @@ HT32F52344_54 EQU 9 HT32F0006 EQU 10 HT32F61352 EQU 10 HT50F32003 EQU 4 +HT50F3200U EQU 2 HT32F62030 EQU 1 HT32F62040 EQU 2 HT32F62050 EQU 5 +HT32F62140 EQU 2 HT32F67741 EQU 2 HT32F67232 EQU 1 HT32F67233 EQU 1 +HT32F59045 EQU 2 +MXTX52231 EQU 2 +MXTX52352 EQU 4 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s index 90e0090688..daf124989c 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,8 +19,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,8 +32,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF @@ -45,8 +45,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00059041 ;_HT32FWID EQU 0x000F5032 ;_HT32FWID EQU 0x00061641 -;_HT32FWID EQU 0x00059046 ;_HT32FWID EQU 0x00061041 +;_HT32FWID EQU 0x00061741 HT32F50220_30 EQU 7 HT32F50231_41 EQU 8 @@ -54,8 +54,8 @@ HT50F32002 EQU 7 HT32F59041 EQU 8 HF5032 EQU 7 HT32F61641 EQU 8 -HT32F59046 EQU 8 HT32F61041 EQU 8 +HT32F61741 EQU 8 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s index 2d5a99264b..bba37d7b67 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,6 +19,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -30,6 +32,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF @@ -41,6 +45,8 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00005828 ;_HT32FWID EQU 0x00067742 ;_HT32FWID EQU 0x00059746 +;_HT32FWID EQU 0x00057541 +;_HT32FWID EQU 0x00057552 HT32F57331_41 EQU 13 HT32F57342_52 EQU 14 @@ -48,6 +54,8 @@ HT32F59741 EQU 13 HT32F5828 EQU 14 HT32F67742 EQU 13 HT32F59746 EQU 13 +HT32F57541 EQU 13 +HT32F57552 EQU 14 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s index a8289bc68e..e930ae96a2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s @@ -6,27 +6,31 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_10.s -; Version : $Rev:: 5780 $ -; Date : $Date:: 2022-03-28 #$ +; Version : $Rev:: 8101 $ +; Date : $Date:: 2024-09-04 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ ; Supported Device ; ======================================== ; HT32F61244, HT32F61245 +; NW32F61242 ;/* <<< Use Configuration Wizard in Context Menu >>> */ ;// HT32 Device ;// <0=> By Project Asm Define ;// <24=> HT32F61244/45 +;// <24=> NW32F61242 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00061244 ;_HT32FWID EQU 0x00061245 +;_HT32FWID EQU 0x00061242 HT32F61244_45 EQU 24 +HT32F61242 EQU 24 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s index b573c7b115..45ca9e15d0 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF @@ -31,10 +33,12 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050030 ;_HT32FWID EQU 0x00061630 ;_HT32FWID EQU 0x00061030 +;_HT32FWID EQU 0x00061730 HT32F50020_30 EQU 25 HT32F61630 EQU 25 HT32F61030 EQU 25 +HT32F61730 EQU 25 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s index ffd489d97a..2f7dbec068 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_14.s -; Version : $Rev:: 6834 $ -; Date : $Date:: 2023-03-31 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -22,6 +23,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF @@ -29,9 +31,11 @@ _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00050452 ;_HT32FWID EQU 0x00050431 ;_HT32FWID EQU 0x00050441 +;_HT32FWID EQU 0x00061052 HT32F50442_52 EQU 26 HT32F50431_41 EQU 30 +HT32F61052 EQU 26 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s index 753e6eb165..6d6fa80b87 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_16.s -; Version : $Rev:: 7212 $ -; Date : $Date:: 2023-09-11 #$ +; Version : $Rev:: 8260 $ +; Date : $Date:: 2024-11-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -105,7 +105,7 @@ __vector_table DCD BFTM1_IRQHandler ; 17, 33, 0x084, DCD CMP0_IRQHandler ; 18, 34, 0x088, DCD CMP1_IRQHandler ; 19, 35, 0x08C, - DCD PID_IRQHandler ; 20, 36, 0x090, + DCD PID0_IRQHandler ; 20, 36, 0x090, DCD I2C0_IRQHandler ; 21, 37, 0x094, DCD SPI0_IRQHandler ; 22, 38, 0x098, DCD USART0_IRQHandler ; 23, 39, 0x09C, @@ -174,7 +174,7 @@ SysTick_Handler PUBWEAK BFTM1_IRQHandler PUBWEAK CMP0_IRQHandler PUBWEAK CMP1_IRQHandler - PUBWEAK PID_IRQHandler + PUBWEAK PID0_IRQHandler PUBWEAK I2C0_IRQHandler PUBWEAK SPI0_IRQHandler PUBWEAK USART0_IRQHandler @@ -207,7 +207,7 @@ BFTM0_IRQHandler BFTM1_IRQHandler CMP0_IRQHandler CMP1_IRQHandler -PID_IRQHandler +PID0_IRQHandler I2C0_IRQHandler SPI0_IRQHandler USART0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s index bfabd93ba9..9db666fdde 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s @@ -6,8 +6,8 @@ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_17.s -; Version : $Rev:: 7212 $ -; Date : $Date:: 2023-09-11 #$ +; Version : $Rev:: 7718 $ +; Date : $Date:: 2024-05-13 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -19,14 +19,14 @@ ;// HT32 Device ;// <0=> By Project Asm Define -;// <33=> HT32F52234/44 +;// <35=> HT32F52234/44 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00052234 ;_HT32FWID EQU 0x00052244 -HT32F52234_44 EQU 33 +HT32F52234_44 EQU 35 IF USE_HT32_CHIP_SET=0 ELSE diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s index a667619b58..a2805097bd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_01.s -; Version : $Rev:: 6953 $ -; Date : $Date:: 2023-05-30 #$ +; Version : $Rev:: 7848 $ +; Date : $Date:: 2024-07-16 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -24,10 +24,15 @@ ; HT32F0006 ; HT32F61352 ; HT50F32003 +; HT50F3200U ; HT32F62030, HT32F62040, HT32F62050 +; HT32F62140 ; HT32F67741 ; HT32F67232 ; HT32F67233 +; HT32F59045 +; MXTX52231 +; MXTX52352 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -44,12 +49,17 @@ ;// <10=> HT32F0006 ;// <10=> HT32F61352 ;// <4=> HT50F32003 +;// <2=> HT50F3200U ;// <2=> HT32F67741 ;// <1=> HT32F67232 ;// <1=> HT32F67233 ;// <1=> HT32F62030 ;// <2=> HT32F62040 ;// <5=> HT32F62050 +;// <2=> HT32F62140 +;// <2=> HT32F59045 +;// <2=> MXTX52231 +;// <4=> MXTX52352 */ .equ USE_HT32_CHIP_SET, 0 @@ -71,12 +81,15 @@ .equ _HT32FWID, 0x00000006 .equ _HT32FWID, 0x00061352 .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x0003200F .equ _HT32FWID, 0x00062030 .equ _HT32FWID, 0x00062040 .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00062140 .equ _HT32FWID, 0x00067741 .equ _HT32FWID, 0x00067232 - .equ _HT32FWID, 0x00067233 + .equ _HT32FWID, 0x00067233 + .equ _HT32FWID, 0x00059045 */ .equ HT32F52220_30, 1 @@ -89,12 +102,17 @@ .equ HT32F0006, 10 .equ HT32F61352, 10 .equ HT50F32003, 4 + .equ HT50F3200U, 2 .equ HT32F62030, 1 .equ HT32F62040, 2 .equ HT32F62050, 5 + .equ HT32F62140, 2 .equ HT32F67741, 2 .equ HT32F67232, 1 .equ HT32F67233, 1 + .equ HT32F59045, 2 + .equ MXTX52231, 2 + .equ MXTX52352, 4 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s index 5b5110f922..5615abd163 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_02.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -20,8 +20,8 @@ ; HT32F59041 ; HF5032 ; HT32F61641 -; HT32F59046 ; HT32F61041 +; HT32F61741 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -34,8 +34,8 @@ ;// <8=> HT32F59041 ;// <7=> HF5032 ;// <8=> HT32F61641 -;// <8=> HT32F59046 ;// <8=> HT32F61041 +;// <8=> HT32F61741 */ .equ USE_HT32_CHIP_SET, 0 @@ -49,8 +49,8 @@ .equ _HT32FWID, 0x00059041 .equ _HT32FWID, 0x000F5032 .equ _HT32FWID, 0x00061641 - .equ _HT32FWID, 0x00059046 .equ _HT32FWID, 0x00061041 + .equ _HT32FWID, 0x00061741 */ .equ HT32F50220_30, 7 @@ -59,8 +59,8 @@ .equ HT32F59041, 8 .equ HF5032, 7 .equ HT32F61641, 8 - .equ HT32F59046, 8 .equ HT32F61041, 8 + .equ HT32F61741, 8 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s index 25447b9b1f..20f3a2be81 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_05.s -; Version : $Rev:: 6993 $ -; Date : $Date:: 2023-06-26 #$ +; Version : $Rev:: 7935 $ +; Date : $Date:: 2024-08-08 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -20,6 +20,8 @@ ; HT32F5828 ; HT32F67742 ; HT32F59746 +; HT32F57541 +; HT32F57552 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -32,6 +34,8 @@ ;// <14=> HT32F5828 ;// <13=> HT32F67742 ;// <13=> HT32F59746 +;// <13=> HT32F57541 +;// <14=> HT32F57552 */ .equ USE_HT32_CHIP_SET, 0 @@ -45,6 +49,8 @@ .equ _HT32FWID, 0x00005828 .equ _HT32FWID, 0x00067742 .equ _HT32FWID, 0x00059746 + .equ _HT32FWID, 0x00057541 + .equ _HT32FWID, 0x00057552 */ .equ HT32F57331_41, 13 @@ -53,6 +59,8 @@ .equ HT32F5828, 14 .equ HT32F67742, 13 .equ HT32F59746, 13 + .equ HT32F57541, 13 + .equ HT32F57552, 14 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s index d9253dcbca..7d45a71453 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_10.s -; Version : $Rev:: 6601 $ -; Date : $Date:: 2022-12-27 #$ +; Version : $Rev:: 8101 $ +; Date : $Date:: 2024-09-04 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -15,6 +15,7 @@ ; Supported Device ; ======================================== ; HT32F61244, HT32F61245 +; NW32F61242 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -22,6 +23,7 @@ ;// HT32 Device ;// <0=> By Project Asm Define ;// <24=> HT32F61244/45 +;// <24=> NW32F61242 */ .equ USE_HT32_CHIP_SET, 0 @@ -29,9 +31,11 @@ /* .equ _HT32FWID, 0x00061244 .equ _HT32FWID, 0x00061245 + .equ _HT32FWID, 0x00061242 */ .equ HT32F61244_45, 24 + .equ NW32F61242, 24 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s index 8c3a524ef1..68cc2d3ce4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_13.s -; Version : $Rev:: 7119 $ -; Date : $Date:: 2023-08-15 #$ +; Version : $Rev:: 7704 $ +; Date : $Date:: 2024-05-10 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -17,6 +17,7 @@ ; HT32F50020, HT32F50030 ; HT32F61630 ; HT32F61030 +; HT32F61730 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -26,6 +27,7 @@ ;// <25=> HT32F50020/30 ;// <25=> HT32F61630 ;// <25=> HT32F61030 +;// <25=> HT32F61730 */ .equ USE_HT32_CHIP_SET, 0 @@ -35,11 +37,13 @@ .equ _HT32FWID, 0x00050030 .equ _HT32FWID, 0x00061630 .equ _HT32FWID, 0x00061030 + .equ _HT32FWID, 0x00061730 */ .equ HT32F50020_30, 25 .equ HT32F61630, 25 .equ HT32F61030, 25 + .equ HT32F61730, 25 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s index 530eb0949f..a55ad72c13 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_14.s -; Version : $Rev:: 6793 $ -; Date : $Date:: 2023-03-14 #$ +; Version : $Rev:: 8287 $ +; Date : $Date:: 2024-11-27 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -16,6 +16,7 @@ ; ======================================== ; HT32F50442, HT32F50452 ; HT32F50431, HT32F50441 +; HT32F61052 */ ;/* <<< Use Configuration Wizard in Context Menu >>> */ @@ -24,6 +25,7 @@ ;// <0=> By Project Asm Define ;// <26=> HT32F50442/52 ;// <30=> HT32F50431/41 +;// <26=> HT32F61052 */ .equ USE_HT32_CHIP_SET, 0 @@ -33,10 +35,12 @@ .equ _HT32FWID, 0x00050452 .equ _HT32FWID, 0x00050431 .equ _HT32FWID, 0x00050441 + .equ _HT32FWID, 0x00061052 */ .equ HT32F50442_52, 26 .equ HT32F50431_41, 30 + .equ.HT32F61052, 26 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s index 81260f6c78..da44c1d66a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_16.s -; Version : $Rev:: 7094 $ -; Date : $Date:: 2023-08-02 #$ +; Version : $Rev:: 8260 $ +; Date : $Date:: 2024-11-05 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -108,7 +108,7 @@ _vectors: .long BFTM1_IRQHandler /* 17, 33, 0x084, */ .long CMP0_IRQHandler /* 18, 34, 0x088, */ .long CMP1_IRQHandler /* 19, 35, 0x08C, */ - .long PID_IRQHandler /* 20, 36, 0x090, */ + .long PID0_IRQHandler /* 20, 36, 0x090, */ .long I2C0_IRQHandler /* 21, 37, 0x094, */ .long SPI0_IRQHandler /* 22, 38, 0x098, */ .long USART0_IRQHandler /* 23, 39, 0x09C, */ @@ -205,7 +205,7 @@ Default_Handler: IRQ BFTM1_IRQHandler IRQ CMP0_IRQHandler IRQ CMP1_IRQHandler - IRQ PID_IRQHandler + IRQ PID0_IRQHandler IRQ I2C0_IRQHandler IRQ SPI0_IRQHandler IRQ USART0_IRQHandler diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s index d5be1f4cd5..91206a4f1f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s @@ -6,8 +6,8 @@ /* */ /*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_es_17.s -; Version : $Rev:: 7030 $ -; Date : $Date:: 2023-07-18 #$ +; Version : $Rev:: 7718 $ +; Date : $Date:: 2024-05-13 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ @@ -21,7 +21,7 @@ /* ;// HT32 Device ;// <0=> By Project Asm Define -;// <33=> HT32F52234/44 +;// <35=> HT32F52234/44 */ .equ USE_HT32_CHIP_SET, 0 @@ -31,7 +31,7 @@ .equ _HT32FWID, 0x00052244 */ - .equ HT32F52234_44, 33 + .equ HT32F52234_44, 35 .if USE_HT32_CHIP_SET == 0 .else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c index e6f4c361e5..fa205a5a62 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 6597 $ - * @date $Date:: 2022-12-27 #$ + * @version $Rev:: 7848 $ + * @date $Date:: 2024-07-16 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -30,6 +30,7 @@ // HT32F52342, HT32F52352 // HT32F52243, HT32F52253 // HT50F32003 +// MXTX52352 //#define USE_HT32F52220_30 //#define USE_HT32F52231_41 @@ -37,6 +38,7 @@ //#define USE_HT32F52342_52 //#define USE_HT32F52243_53 //#define USE_HT50F32003 +//#define USE_MXTX52352 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c index f864735544..5c14d07f8e 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 6953 $ - * @date $Date:: 2023-05-30 #$ + * @version $Rev:: 7848 $ + * @date $Date:: 2024-07-16 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -30,8 +30,12 @@ // HT32F52342, HT32F52352 // HT32F52243, HT32F52253 // HT32F62030, HT32F62040, HT32F62050 +// HT32F62140, // HT32F67232, HT32F67233 // HT32F67741, +// HT50F3200U +// HT32F59045 +// MXTX52231 //#define USE_HT32F52220_30 //#define USE_HT32F52231_41 @@ -41,9 +45,13 @@ //#define USE_HT32F62030 //#define USE_HT32F62040 //#define USE_HT32F62050 +//#define USE_HT32F62140 //#define USE_HT32F67232 //#define USE_HT32F67233 //#define USE_HT32F67741 +//#define USE_HT50F3200U +//#define USE_HT32F59045 +//#define USE_MXTX52231 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c index b709d27c6f..18d8b71531 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 7119 $ - * @date $Date:: 2023-08-15 #$ + * @version $Rev:: 7704 $ + * @date $Date:: 2024-05-10 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -30,8 +30,8 @@ // HT32F59041 // HF5032 // HT32F61641 -// HT32F59046 // HT32F61041 +// HT32F61741 //#define USE_HT32F50220_30 //#define USE_HT32F50231_41 @@ -39,8 +39,8 @@ //#define USE_HT32F59041 //#define USE_HF5032 //#define USE_HT32F61641 -//#define USE_HT32F59046 //#define USE_HT32F61041 +//#define USE_HT32F61741 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c index e0460f199e..f17e3637b3 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 6993 $ - * @date $Date:: 2023-06-26 #$ + * @version $Rev:: 7935 $ + * @date $Date:: 2024-08-08 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -30,6 +30,8 @@ // HT32F5828 // HT32F67742 // HT32F59746 +// HT32F57541 +// HT32F57552 //#define USE_HT32F57331_41 //#define USE_HT32F57342_52 @@ -37,6 +39,8 @@ //#define USE_HT32F5828 //#define USE_HT32F67742 //#define USE_HT32F59746 +//#define USE_HT32F57541 +//#define USE_HT32F57552 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c index 704ebb5730..60bc450dfd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 6597 $ - * @date $Date:: 2022-12-27 #$ + * @version $Rev:: 8101 $ + * @date $Date:: 2024-09-04 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -25,8 +25,10 @@ // Supported Device // ======================================== // HT32F61244, HT32F61245 +// NW32F61242 //#define USE_HT32F61244_45 +//#define USE_NW32F61242 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c index c906eb1640..f4a0e62ce5 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 7119 $ - * @date $Date:: 2023-08-15 #$ + * @version $Rev:: 7704 $ + * @date $Date:: 2024-05-10 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -27,10 +27,12 @@ // HT32F50020, HT32F50030 // HT32F61630 // HT32F61030 +// HT32F61730 //#define USE_HT32F50020_30 //#define USE_HT32F61630 //#define USE_HT32F61030 +//#define USE_HT32F61730 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c index 2dc4216f4b..0cba0c6c51 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 6790 $ - * @date $Date:: 2023-03-13 #$ + * @version $Rev:: 8287 $ + * @date $Date:: 2024-11-27 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -26,9 +26,11 @@ // ======================================== // HT32F50442, HT32F50452 // HT32F50431, HT32F50441 +// HT32F61052 //#define USE_HT32F50442_52 //#define USE_HT32F50431_41 +//#define USE_HT32F61052 /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c index ba5073e76f..ef0dd2ec67 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c @@ -2,8 +2,8 @@ * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File * for the Holtek HT32F5xxxx Device Series - * @version $Rev:: 7413 $ - * @date $Date:: 2023-12-15 #$ + * @version $Rev:: 7610 $ + * @date $Date:: 2024-02-27 #$ * * @note * Copyright (C) Holtek Semiconductor Inc. All rights reserved. @@ -24,19 +24,10 @@ // Supported Device // ======================================== -// HT32F0008 -// HT32F52142 -// HT32F52344, HT32F52354 -// HT32F52357, HT32F52367 -// HT32F65230, HT32F65240 -// HT50F3200T +// BM18B367A + -//#define USE_HT32F0008 -//#define USE_HT32F52142 -//#define USE_HT32F52344_54 //#define USE_HT32F52357_67 -//#define USE_HT32F65230_40 -//#define USE_HT50F3200T /** @addtogroup CMSIS * @{ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_can_config0_calc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_can_config0_calc.h new file mode 100644 index 0000000000..6ff016f06c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_can_config0_calc.h @@ -0,0 +1,385 @@ +/*********************************************************************************************************//** + * @file ht32_can_config0_calc.h + * @version $Rev:: 8147 $ + * @date $Date:: 2024-09-16 #$ + * @brief The CAN config calculation features. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CAN_CONFIG0_CALC_H +#define __HT32_CAN_CONFIG0_CALC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define CAN_CF0_CALC_DEBUG (0) + +/*----------------------------------------------------------------------------------------------------------*/ +/* CAN Parameter Calculation */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (HTCFG_CAN_CORECLKSEL == 0) + #define _HTCFG_CAN_CORE_CLK (LIBCFG_MAX_SPEED) +#else + #define _HTCFG_CAN_CORE_CLK (HTCFG_CAN_CORECLK_MANUAL) +#endif + +#define _HTCFG_CF0_CK_CAN (_HTCFG_CAN_CORE_CLK / (1 << HTCFG_CAN_CF0_CLK_DIV)) + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (25UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 25 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (24UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 24 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (23UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 23 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (22UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 22 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (21UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 21 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (20UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 20 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (19UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 19 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (18UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 18 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (17UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 17 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (16UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 16 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (15UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 15 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (14UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 14 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (13UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 13 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (12UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 12 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (11UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 11 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (10UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 10 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (9UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 9 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #undef _TMP_CF0_NBT + #define _TMP_CF0_NBT (8UL) + #if (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT > 0) + #if ((_HTCFG_CF0_CK_CAN / (_HTCFG_CF0_CK_CAN / HTCFG_CAN_CF0_BAUDRATE / _TMP_CF0_NBT)) / _TMP_CF0_NBT <= HTCFG_CAN_CF0_BAUDRATE) + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME _TMP_CF0_NBT + #if (CAN_CF0_CALC_DEBUG == 1) + #warning Set HTCFG_CAN_CF0_NOMINAL_BIT_TIME as 8 + #endif + #endif + #endif +#endif + +#ifndef HTCFG_CAN_CF0_NOMINAL_BIT_TIME + #error Can't find the suitable Nominal Bit Time setting. Try to increase CK_CAN or lower the CAN Baudrate. +#endif + +/* define value for CAN_Init() */ +#define CAN_CONF0_PRESCALER (_HTCFG_CF0_CK_CAN / (HTCFG_CAN_CF0_BAUDRATE * HTCFG_CAN_CF0_NOMINAL_BIT_TIME)) +#define CAN_CONF0_BIT_TIME_TSEG1 (HTCFG_CAN_CF0_NOMINAL_BIT_TIME - (HTCFG_CAN_CF0_NOMINAL_BIT_TIME * HTCFG_CAN_CF0_SAMPLE_POINT) / 100) +#define CAN_CONF0_BIT_TIME_TSEG0 (HTCFG_CAN_CF0_NOMINAL_BIT_TIME - 1 - CAN_CONF0_BIT_TIME_TSEG1) +#define CAN_CONF0_BIT_TIME_SJW (HTCFG_CAN_CF0_BIT_TIME_SJW) + +/*----------------------------------------------------------------------------------------------------------*/ +/* CAN Parameter Checking */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (CAN_CONF0_PRESCALER < 1) + #error CAN Config 0 "Prescaler" value out of spec (must >= 1)! Try to lower the Nominal Bit Time or CAN Baudrate. +#endif + +#if (CAN_CONF0_PRESCALER > 1024) + #error CAN Config 0 "Prescaler" value out of spec (must <= 1024)! +#endif + +#if (CAN_CONF0_BIT_TIME_TSEG0 > 16) + #error CAN Config 0 "TSEG0" value out of spec (must <= 16)! +#endif + +#if (CAN_CONF0_BIT_TIME_TSEG1 > 8) + #if (HTCFG_CAN_CF0_NOMINAL_BIT_TIME < 16) + #error CAN Config 0 "TSEG1" value out of spec (must <= 8)! May try to larger the Sample Point. + #else + + // Reduce HTCFG_CAN_CF0_NOMINAL_BIT_TIME and try again + #undef CAN_CONF0_PRESCALER + #undef CAN_CONF0_BIT_TIME_TSEG1 + #undef CAN_CONF0_BIT_TIME_TSEG0 + #define HTCFG_CAN_CF0_NOMINAL_BIT_TIME2 (HTCFG_CAN_CF0_NOMINAL_BIT_TIME/2) + #define CAN_CONF0_PRESCALER (_HTCFG_CF0_CK_CAN / (HTCFG_CAN_CF0_BAUDRATE * HTCFG_CAN_CF0_NOMINAL_BIT_TIME2)) + #define CAN_CONF0_BIT_TIME_TSEG1 (HTCFG_CAN_CF0_NOMINAL_BIT_TIME2 - (HTCFG_CAN_CF0_NOMINAL_BIT_TIME2 * HTCFG_CAN_CF0_SAMPLE_POINT) / 100) + #define CAN_CONF0_BIT_TIME_TSEG0 (HTCFG_CAN_CF0_NOMINAL_BIT_TIME2 - 1 - CAN_CONF0_BIT_TIME_TSEG1) + + #if (CAN_CONF0_BIT_TIME_TSEG1 > 8) + #error CAN Config 0 "TSEG1" value out of spec (must <= 8)! May try to lager the Sample Point. + #endif + + #endif +#endif + +#if (CAN_CONF0_BIT_TIME_TSEG1 > 4) + #define CAN_CONF0_BIT_TIME_SJW_MAX (4) +#else + #define CAN_CONF0_BIT_TIME_SJW_MAX CAN_CONF0_BIT_TIME_TSEG1 +#endif + +#if (HTCFG_CAN_CF0_BIT_TIME_SJW > CAN_CONF0_BIT_TIME_SJW_MAX) + #error CAN Config 0 "SJW" value out of spec (must <= 4 and TSEG1)! +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* CAN Config Check function */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (HTCFG_CAN_CONF_CHECK_ENABLE == 1) +__STATIC_INLINE void CAN_Config0_Check(void) +{ + u32 Core_Clock = _HTCFG_CAN_CORE_CLK; + u32 IPPrescaler = (1 << HTCFG_CAN_CF0_CLK_DIV); + u32 CK_CAN = Core_Clock / IPPrescaler; + u32 BRP = CAN_CONF0_PRESCALER; + u32 ftq = CK_CAN / BRP; + u32 TSEG0 = CAN_CONF0_BIT_TIME_TSEG0; + u32 TSEG1 = CAN_CONF0_BIT_TIME_TSEG1; + u32 NBT = (1 + TSEG0 + TSEG1); + u32 SamplePoint = ((NBT - TSEG1) * 100) / NBT; + u32 Baudrate = ftq / (1 + TSEG0 + TSEG1) ; + + RETARGET_Configuration(); + + printf("HT32 CAN Config 0 Check\r\n"); + printf("---------------------------------------------\r\n"); + printf(" Core Clock (CK_AHB, Hz) = %d\r\n", Core_Clock); + printf(" CAN IP Prescaler = %d\r\n", IPPrescaler); + printf(" CAN IP Clock (CK_CAN, Hz) = %d\r\n", CK_CAN); + printf(" CAN Prescaler (BRP) = %d\r\n", BRP); + printf(" 1 / time quantum (1/tq, Hz) = %d\r\n", ftq); + printf(" Prop_Seg + Phase_Seg0 = %d\r\n", TSEG0); + printf(" Phase_Seg1 = %d\r\n", TSEG1); + printf(" Nominal Bit Time(NBT, calc) = %d tq\r\n", HTCFG_CAN_CF0_NOMINAL_BIT_TIME); + printf(" Nominal Bit Time(NBT, real) = %d tq\r\n", NBT); + printf(" Sample Point (setting) = %d %%\r\n", HTCFG_CAN_CF0_SAMPLE_POINT); + printf(" Sample Point (real) = %d %%\r\n", SamplePoint); + printf(" CAN BAUDRATE (setting, Hz) = %d\r\n", HTCFG_CAN_CF0_BAUDRATE); + printf(" CAN BAUDRATE (real, Hz) = %d\r\n", Baudrate); + printf("\r\n"); + printf("Please check the above setting is as expected....\r\n\r\n"); +} +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h index 8919d357bc..5edace51cb 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_cm0plus_misc.h - * @version $Rev:: 750 $ - * @date $Date:: 2016-05-31 #$ + * @version $Rev:: 7802 $ + * @date $Date:: 2024-07-01 #$ * @brief All the function prototypes for the miscellaneous firmware library. ************************************************************************************************************* * @attention @@ -112,6 +112,11 @@ void SYSTICK_CounterCmd(u32 SysTick_Counter); void SYSTICK_IntConfig(ControlStatus NewState); void SYSTICK_SetReloadValue(u32 SysTick_Reload); u32 RBIT(u32 in); +#if (HTCFG_STACK_USAGE_ANALYSIS == 1) +void StackUsageAnalysisInit(u32 addr); +#else +#define StackUsageAnalysisInit(...) +#endif /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h index bd4e561247..3ff43db6d6 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_config.h - * @version $Rev:: 7125 $ - * @date $Date:: 2023-08-16 #$ + * @version $Rev:: 8288 $ + * @date $Date:: 2024-11-27 #$ * @brief Configuration file of HT32. ************************************************************************************************************* * @attention @@ -200,6 +200,16 @@ #define USE_MEM_HT32F52367 #endif +#ifdef USE_HT50F3200U_SK + #define USE_HT32F62140_SK +#endif +#ifdef USE_HT50F3200U + #define USE_HT32F62140 +#endif +#ifdef USE_MEM_HT50F3200U + #define USE_MEM_HT32F62140 +#endif + #ifdef USE_HT32F62030_SK #define USE_HT32F52230_SK #endif @@ -220,6 +230,16 @@ #define USE_MEM_HT32F52241 #endif +#ifdef USE_HT32F62140_SK + #define USE_HT32F52241_SK +#endif +#ifdef USE_HT32F62140 + #define USE_HT32F52231_41 +#endif +#ifdef USE_MEM_HT32F62140 + #define USE_MEM_HT32F52241 +#endif + #ifdef USE_HT32F62050_SK #define USE_HT32F52253_SK #endif @@ -260,14 +280,14 @@ #define USE_MEM_HT32F57341 #endif -#ifdef USE_HT32F59046_SK - #define USE_HT32F50241_SK +#ifdef USE_HT32F59045_SK + #define USE_HT32F52241_SK #endif -#ifdef USE_HT32F59046 - #define USE_HT32F50231_41 +#ifdef USE_HT32F59045 + #define USE_HT32F52231_41 #endif -#ifdef USE_MEM_HT32F59046 - #define USE_MEM_HT32F50241 +#ifdef USE_MEM_HT32F59045 + #define USE_MEM_HT32F52241 #endif #ifdef USE_HT32F59746_SK @@ -300,6 +320,66 @@ #define USE_MEM_HT32F50241 #endif +#ifdef USE_HT32F61730_SK + #define USE_HT32F50030_SK +#endif +#ifdef USE_HT32F61730 + #define USE_HT32F50020_30 +#endif +#ifdef USE_MEM_HT32F61730 + #define USE_MEM_HT32F50030 +#endif + +#ifdef USE_HT32F61741_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F61741 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F61741 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_MXTX52231_SK + #define USE_HT32F52241_SK +#endif +#ifdef USE_MXTX52231 + #define USE_HT32F52231_41 +#endif +#ifdef USE_MEM_MXTX52231 + #define USE_MEM_HT32F52241 +#endif + +#ifdef USE_MXTX52352_SK + #define USE_HT32F52352_SK +#endif +#ifdef USE_MXTX52352 + #define USE_HT32F52342_52 +#endif +#ifdef USE_MEM_MXTX52352 + #define USE_MEM_HT32F52352 +#endif + +#ifdef USE_NW32F61242_SK + #define USE_HT32F61245_SK +#endif +#ifdef USE_NW32F61242 + #define USE_HT32F61244_45 +#endif +#ifdef USE_MEM_NW32F61242 + #define USE_MEM_HT32F61245 +#endif + +#ifdef USE_HT32F61052_SK + #define USE_HT32F50452_SK +#endif +#ifdef USE_HT32F61052 + #define USE_HT32F50442_52 +#endif +#ifdef USE_MEM_HT32F61052 + #define USE_MEM_HT32F50452 +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h index d96ecb9c3c..518d99be5c 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_dependency.h - * @version $Rev:: 5863 $ - * @date $Date:: 2022-05-12 #$ + * @version $Rev:: 7593 $ + * @date $Date:: 2024-02-22 #$ * @brief The header file of dependency check. ************************************************************************************************************* * @attention @@ -41,14 +41,22 @@ #if 0 // Version setting example for module /* Dependency check ----------------------------------------------------------------------------------------*/ -#if (__CORTEX_M == 0) +#if defined(__HT32L5XXXX_LIB_H) +#define MIN_HT32_FWLIB_VER (0x01000000) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x209) +#endif +#if defined(__HT32F5XXXX_LIB_H) #define MIN_HT32_FWLIB_VER (0x01000024) //0xmmnnnrrr -> Vm.n.r #define MIN_HT32_FWLIB_SVN (0x5762) #endif -#if (__CORTEX_M == 3) +#if defined(__HT32F1XXXX_LIB_H) #define MIN_HT32_FWLIB_VER (0x01000009) //0xmmnnnrrr -> Vm.n.r #define MIN_HT32_FWLIB_SVN (0x2556) #endif +#if defined(__HT32F4XXXX_LIB_H) +#define MIN_HT32_FWLIB_VER (0x01000000) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x336) +#endif #include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. #endif @@ -62,7 +70,7 @@ #endif -// Check "ht32fxxxxx_lib.h" for the version of HT32 Firmwar Library +// Check "ht32f5xxxx_lib.h" for the version of HT32 Firmwar Library #if (HT32_FWLIB_VER != 999999) #if HT32_FWLIB_VER < MIN_HT32_FWLIB_VER #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h index 51aeba2c3e..1640af5c09 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_time.h - * @version $Rev:: 6751 $ - * @date $Date:: 2023-03-02 #$ + * @version $Rev:: 7693 $ + * @date $Date:: 2024-04-02 #$ * @brief The header file of time function. ************************************************************************************************************* * @attention @@ -132,23 +132,23 @@ #define TIME_TICKDIFF(start, current) ((current >= start) ? (u32)(current - start) : (u32)(0xFFFFFFFF - start + 1 + current)) #if (HTCFG_TIME_TICKHZ < 1000000) -#define TIME_US2TICK(us) (us / (1000000UL / HTCFG_TIME_TICKHZ)) -#define TIME_TICK2US(t) (t * (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_US2TICK(us) ((us) / (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2US(t) ((t) * (1000000UL / HTCFG_TIME_TICKHZ)) #else -#define TIME_US2TICK(us) (us * (HTCFG_TIME_TICKHZ / 1000000UL)) -#define TIME_TICK2US(t) (t / (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_US2TICK(us) ((us) * (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_TICK2US(t) ((t) / (HTCFG_TIME_TICKHZ / 1000000UL)) #endif #if (HTCFG_TIME_TICKHZ < 1000) -#define TIME_MS2TICK(ms) (ms / (1000UL / HTCFG_TIME_TICKHZ)) -#define TIME_TICK2MS(t) (t * (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_MS2TICK(ms) ((ms) / (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2MS(t) ((t) * (1000UL / HTCFG_TIME_TICKHZ)) #else -#define TIME_MS2TICK(ms) (ms * (HTCFG_TIME_TICKHZ / 1000UL)) -#define TIME_TICK2MS(t) (t / (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_MS2TICK(ms) ((ms) * (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_TICK2MS(t) ((t) / (HTCFG_TIME_TICKHZ / 1000UL)) #endif -#define TIME_S2TICK(s) (s * (u32)(HTCFG_TIME_TICKHZ)) -#define TIME_TICK2S(t) (t / (HTCFG_TIME_TICKHZ)) +#define TIME_S2TICK(s) ((s) * (u32)(HTCFG_TIME_TICKHZ)) +#define TIME_TICK2S(t) ((t) / (HTCFG_TIME_TICKHZ)) #define GET_CNT() (_HTCFG_TIME_PORT->CNTR) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h index 44d05bdcc9..dddf5d4e07 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f50020_30_libcfg.h - * @version $Rev:: 6386 $ - * @date $Date:: 2022-10-27 #$ + * @version $Rev:: 7661 $ + * @date $Date:: 2024-03-21 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -52,6 +52,7 @@ #define LIBCFG_GPIOC (1) #define LIBCFG_GPIOF (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) #define LIBCFG_LEDC (1) #define LIBCFG_LSE (1) #define LIBCFG_SCTM0 (1) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h index 2e13c2bea0..c8fc4b8afe 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f50343_libcfg.h - * @version $Rev:: 6386 $ - * @date $Date:: 2022-10-27 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h index 9c3bb3bb39..44898e5dd8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f50431_41_libcfg.h - * @version $Rev:: 7265 $ - * @date $Date:: 2023-10-02 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -90,6 +90,5 @@ #define LIBCFG_ADC_MVDDA (1) #define LIBCFG_USART_LIN (1) #define LIBCFG_USART_SINGLE_WIRE (1) -#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h index 6a3cff8ab6..d601c4699a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f50442_52_libcfg.h - * @version $Rev:: 7265 $ - * @date $Date:: 2023-10-02 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -80,6 +80,7 @@ #define LIBCFG_CKCU_ATM_V01 (1) #define LIBCFG_CKCU_SYS_CK_60M (1) #define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CMP_IVREF_CN_IN (1) #define LIBCFG_PWRCU_VDD_5V (1) #define LIBCFG_PWRCU_WAKEUP1 (1) #define LIBCFG_PWRCU_WAKEUP_V01 (1) @@ -94,6 +95,5 @@ #define LIBCFG_ADC_MVDDA (1) #define LIBCFG_USART_LIN (1) #define LIBCFG_USART_SINGLE_WIRE (1) -#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h index 43068a9c12..839f61da6f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f53231_41_libcfg.h - * @version $Rev:: 7265 $ - * @date $Date:: 2023-10-02 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -91,6 +91,5 @@ #define LIBCFG_ADC_MVDDA (1) #define LIBCFG_USART_LIN (1) #define LIBCFG_USART_SINGLE_WIRE (1) -#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h index c2493ba610..bd9dc9cb51 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f53242_52_libcfg.h - * @version $Rev:: 7265 $ - * @date $Date:: 2023-10-02 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -81,6 +81,7 @@ #define LIBCFG_CKCU_ATM_V01 (1) #define LIBCFG_CKCU_SYS_CK_60M (1) #define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CMP_IVREF_CN_IN (1) #define LIBCFG_PWRCU_VDD_5V (1) #define LIBCFG_PWRCU_WAKEUP1 (1) #define LIBCFG_PWRCU_WAKEUP_V01 (1) @@ -95,6 +96,5 @@ #define LIBCFG_ADC_MVDDA (1) #define LIBCFG_USART_LIN (1) #define LIBCFG_USART_SINGLE_WIRE (1) -#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h index 671765ef1b..d5876b4d50 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f54231_41_libcfg.h - * @version $Rev:: 7184 $ - * @date $Date:: 2023-08-31 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -64,7 +64,6 @@ #define LIBCFG_FMC_PREFETCH (1) #define LIBCFG_FMC_WAIT_STATE_2 (1) #define LIBCFG_GPIOC (1) -#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) #define LIBCFG_I2C1 (1) #define LIBCFG_LEDC (1) #define LIBCFG_LEDC_NO_COM_8_11 (1) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h index 750e4fb377..d92296ea52 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f54243_53_libcfg.h - * @version $Rev:: 6896 $ - * @date $Date:: 2023-05-08 #$ + * @version $Rev:: 7664 $ + * @date $Date:: 2024-03-26 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -66,7 +66,6 @@ #define LIBCFG_FMC_WAIT_STATE_2 (1) #define LIBCFG_GPIOC (1) #define LIBCFG_GPIOD (1) -#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) #define LIBCFG_I2C1 (1) #define LIBCFG_I2C2 (1) #define LIBCFG_LEDC (1) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h index c50babaa1a..dc06ae3145 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_adc.h - * @version $Rev:: 7265 $ - * @date $Date:: 2023-10-02 #$ + * @version $Rev:: 7678 $ + * @date $Date:: 2024-04-01 #$ * @brief The header file of the ADC library. ************************************************************************************************************* * @attention @@ -634,7 +634,7 @@ void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); #endif #if (LIBCFG_ADC_VREFBUF) -void ADC_VREFOutputCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_VREFOutputADVREFPCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); #endif #if (LIBCFG_ADC_MVDDA) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h index a66d141dd7..465560807b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_can.h - * @version $Rev:: 7188 $ - * @date $Date:: 2023-08-31 #$ + * @version $Rev:: 8284 $ + * @date $Date:: 2024-11-22 #$ * @brief The header file of the CAN library. ************************************************************************************************************* * @attention @@ -44,66 +44,86 @@ * @{ */ + /* Exported types ------------------------------------------------------------------------------------------*/ /** @defgroup CAN_Exported_Types CAN exported types * @{ */ /** - * @brief CAN message structure - */ + * @brief CAN init structure definition + */ typedef struct { - u32 IdType; - u32 FrameType; - u32 Id; - u32 DLC; -} STR_CANMSG_TypeDef; + u16 CAN_BRPrescaler; /* Synchronisation Jump Width , Range: 1~1024. */ + u8 CAN_Mode; /* CAN_MODE_NORMAL : Normal mode. */ + /* CAN_MODE_BASIC : Basic mode. */ + /* CAN_MODE_SILENT : Silent mode. */ + /* CAN_MODE_LBACK : Loop Back Mode. */ + /* CAN_MODE_MONITORER : Sample Point can be monitored. */ + /* CAN_MODE_TX_DOMINANT : CAN_TX pin drives a dominant. */ + /* CAN_MODE_TX_RECESSIVE : CAN_TX pin drives a recessive. */ + u8 CAN_SJW; /* Synchronisation Jump Width , Range: 1~4. */ + u8 CAN_TSEG0; /* The time segment before the sample point. */ + u8 CAN_TSEG1; /* The time segment after the sample point. */ + ControlStatus CAN_NART; /* Set the no automatic retransmission */ +} CAN_InitTypeDef; /** - * @brief CAN TX message structure + * @brief CAN receive status structure */ -typedef struct +typedef enum { - u32 IdType; - u32 FrameType; - u32 Id; - u32 MCR; - u32 DLC; - u32 EOB; - u32 RMTEN; - u32 UMASK; - u32 Data[8]; -} STR_CANMSG_T_TypeDef; - -/** - * @brief CAN RX message structure - */ -typedef struct -{ - u32 IdType; - u32 Id; - u32 u8Xtd; - u32 u8Dir; - u32 MCR; - u32 MASK0; - u32 MASK1; - u32 EOB; - u32 UMASK; - u32 RMTEN; - u32 DIR; /* For receive remote frame. */ - } STR_CANMSG_R_TypeDef; + MSG_RX_FINISH, + MSG_OBJ_NOT_SET, + MSG_NOT_RECEIVED, + MSG_OVER_RUN +} CAN_RxStatus_TypeDef; /** * @brief CAN mask message structure */ +typedef enum +{ + NO_ERROR = 0, + STUFF_ERROR = 1, + FORM_ERROR = 2, + ACK_ERROR = 3, + BIT1_EROR = 4, + BIT0_ERROR = 5, + CRC_ERROR = 6, + NO_CHANGE = 7 +} CAN_LastErrorCode_TypeDef; + +/** + * @brief Message ID Type Constant structure + */ +typedef enum +{ + CAN_STD_ID = 0, + CAN_EXT_ID = 1 +} CAN_IdType_Enum; + +/** + * @brief Message Frame Type Constant structure + */ +typedef enum +{ + CAN_REMOTE_FRAME = 0, + CAN_DATA_FRAME = 1 +} CAN_FrameType_Enum; + +/** + * @brief CAN message structure + */ typedef struct { - u32 u8Xtd; - u32 u8Dir; - u32 u32Id; - u32 u8IdType; -} STR_CANMASK_TyprDef; + u32 Id; /* Arbitration ID. Rang 0x0 ~ 0x1FFFFFFF */ + u32 IdMask; /* Arbitration ID mask. Rang 0x0 ~ 0x1FFFFFFF */ + u8 MsgNum; /* Message number */ + CAN_IdType_Enum IdType; /* CAN_STD_ID (0x0 ~ 0x7FF) or CAN_EXT_ID (0x0 ~ 0x1FFFFFFF) */ + CAN_FrameType_Enum FrameType; /* CAN_REMOTE_FRAME or CAN_DATA_FRAME */ +} CAN_MSG_TypeDef; /** * @} */ @@ -115,336 +135,311 @@ typedef struct #define IS_CAN(x) IS_CAN0(x) #define IS_CAN0(x) (x == HT_CAN0) -/** - * @brief CAN Test Mode Constant Definitions - */ -#define CAN_NORMAL_MODE 0 -#define CAN_BASIC_MODE 0x04 -#define CAN_SILENT_MODE 0x08 -#define CAN_LBACK_MODE 0x10 -#define CAN_LBS_MODE 0x18 +#define CAN_STD_FRAME_Msk 0x7FF +#define CAN_EXT_FRAME_MSB_Msk 0x1FFF +#define CAN_EXT_FRAME_LSB_Msk 0xFFFF -/** - * @brief DMessage ID Type Constant Definitions - */ -#define CAN_STD_ID 0 -#define CAN_EXT_ID 1 -/** - * @brief Message Frame Type Constant Definitions - */ -#define CAN_REMOTE_FRAME 0 -#define CAN_DATA_FRAME 1 - -#define CAN_NBR 1 -#define CAN_VECTOR_NBR 1 -#define DATA_NBR 4 +#define CAN_MODE_NORMAL 0 +#define MSG_OBJ_TOTAL_NUM 32 /** * @brief CAN CR Bit Field Definitions */ -#define CAN_CR_TEST_Pos 7 /*!< CAN_T::CR: TEST Position */ -#define CAN_CR_TEST_Msk (1ul << CAN_CR_TEST_Pos) /*!< CAN_T::CR: TEST Mask */ +#define CAN_CR_TEST_Pos 7 /*!< CAN_T::CR: TEST Position */ +#define CAN_CR_TEST (1ul << CAN_CR_TEST_Pos) /*!< CAN_T::CR: TEST */ -#define CAN_CR_CCE_Pos 6 /*!< CAN_T::CR: CCE Position */ -#define CAN_CR_CCE_Msk (1ul << CAN_CR_CCE_Pos) /*!< CAN_T::CR: CCE Mask */ +#define CAN_CR_CCE_Pos 6 /*!< CAN_T::CR: CCE Position */ +#define CAN_CR_CCE (1ul << CAN_CR_CCE_Pos) /*!< CAN_T::CR: CCE */ -#define CAN_CR_DAR_Pos 5 /*!< CAN_T::CR: DAR Position */ -#define CAN_CR_DAR_Msk (1ul << CAN_CR_DAR_Pos) /*!< CAN_T::CR: DAR Mask */ +#define CAN_CR_DAR_Pos 5 /*!< CAN_T::CR: DAR Position */ +#define CAN_CR_DAR (1ul << CAN_CR_DAR_Pos) /*!< CAN_T::CR: DAR */ -#define CAN_CR_EIE_Pos 3 /*!< CAN_T::CR: EIE Position */ -#define CAN_CR_EIE_Msk (1ul << CAN_CR_EIE_Pos) /*!< CAN_T::CR: EIE Mask */ +#define CAN_CR_EIE_Pos 3 /*!< CAN_T::CR: EIE Position */ +#define CAN_INT_EIE (1ul << CAN_CR_EIE_Pos) /*!< CAN_T::CR: EIE */ -#define CAN_CR_SIE_Pos 2 /*!< CAN_T::CR: SIE Position */ -#define CAN_CR_SIE_Msk (1ul << CAN_CR_SIE_Pos) /*!< CAN_T::CR SIE Mask */ +#define CAN_CR_SIE_Pos 2 /*!< CAN_T::CR: SIE Position */ +#define CAN_INT_SIE (1ul << CAN_CR_SIE_Pos) /*!< CAN_T::CR SIE */ -#define CAN_CR_IE_Pos 1 /*!< CAN_T::CR: IE Position */ -#define CAN_CR_IE_Msk (1ul << CAN_CR_IE_Pos) /*!< CAN_T::CR: IE Mask */ +#define CAN_CR_IE_Pos 1 /*!< CAN_T::CR: IE Position */ +#define CAN_INT_IE (1ul << CAN_CR_IE_Pos) /*!< CAN_T::CR: IE */ -#define CAN_CR_INIT_Pos 0 /*!< CAN_T::CR: INIT Position */ -#define CAN_CR_INIT_Msk (1ul << CAN_CR_INIT_Pos) /*!< CAN_T::CR: INIT Mask */ +#define CAN_INT_ALL (CAN_INT_EIE | CAN_INT_SIE | CAN_INT_IE) + +#define CAN_CR_INIT_Pos 0 /*!< CAN_T::CR: INIT Position */ +#define CAN_CR_INIT (1ul << CAN_CR_INIT_Pos) /*!< CAN_T::CR: INIT */ /** * @brief CAN STATUS Bit Field Definitions */ -#define CAN_SR_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ -#define CAN_SR_BOFF_Msk (1ul << CAN_SR_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */ +#define CAN_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ +#define CAN_FLAG_BOFF (1ul << CAN_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Flag */ -#define CAN_SR_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ -#define CAN_SR_EWARN_Msk (1ul << CAN_SR_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */ +#define CAN_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ +#define CAN_FLAG_EWARN (1ul << CAN_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Flag */ -#define CAN_SR_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ -#define CAN_SR_EPASS_Msk (1ul << CAN_SR_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */ +#define CAN_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ +#define CAN_FLAG_EPASS (1ul << CAN_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Flag */ -#define CAN_SR_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ -#define CAN_SR_RXOK_Msk (1ul << CAN_SR_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */ +#define CAN_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ +#define CAN_FLAG_RXOK (1ul << CAN_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Flag */ -#define CAN_SR_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ -#define CAN_SR_TXOK_Msk (1ul << CAN_SR_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */ +#define CAN_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ +#define CAN_FLAG_TXOK (1ul << CAN_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Flag */ -#define CAN_SR_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ -#define CAN_SR_LEC_Msk (0x3ul << CAN_SR_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ +#define CAN_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ +#define CAN_LEC_Msk (0x7ul << CAN_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ /** * @brief CAN ECR Bit Field Definitions */ -#define CAN_ECR_RP_Pos 15 /*!< CAN_T::ECR: RP Position */ -#define CAN_ECR_RP_Msk (1ul << CAN_ECR_RP_Pos) /*!< CAN_T::ECR: RP Mask */ +#define CAN_ECR_RP_Pos 15 /*!< CAN_T::ECR: RP Position */ +#define CAN_ECR_RP_MsK (1ul << CAN_ECR_RP_Pos) /*!< CAN_T::ECR: RP */ -#define CAN_ECR_REC_Pos 8 /*!< CAN_T::ECR: REC Position */ -#define CAN_ECR_REC_Msk (0x7Ful << CAN_ECR_REC_Pos) /*!< CAN_T::ECR: REC Mask */ +#define CAN_ECR_REC_Pos 8 /*!< CAN_T::ECR: REC Position */ +#define CAN_ECR_REC_MsK (0x7Ful << CAN_ECR_REC_Pos) /*!< CAN_T::ECR: REC Mask */ -#define CAN_ECR_TEC_Pos 0 /*!< CAN_T::ECR: TEC Position */ -#define CAN_ECR_TEC_Msk (0xFFul << CAN_ECR_TEC_Pos) /*!< CAN_T::ECR: TEC Mask */ +#define CAN_ECR_TEC_Pos 0 /*!< CAN_T::ECR: TEC Position */ +#define CAN_ECR_TEC_MsK (0xFFul << CAN_ECR_TEC_Pos) /*!< CAN_T::ECR: TEC Mask */ /** * @brief CAN BTR Bit Field Definitions */ -#define CAN_BTR_TSEG1_Pos 12 /*!< CAN_T::BTR: TSEG1 Position */ -#define CAN_BTR_TSEG1_Msk (0x7ul << CAN_BTR_TSEG1_Pos) /*!< CAN_T::BTR: TSEG1 Mask */ +#define CAN_BTR_TSEG1_Pos 12 /*!< CAN_T::BTR: TSEG1 Position */ +#define CAN_BTR_TSEG1_Msk (0x7ul << CAN_BTR_TSEG1_Pos) /*!< CAN_T::BTR: TSEG1 Mask */ -#define CAN_BTR_TSEG0_Pos 8 /*!< CAN_T::BTR: TSEG0 Position */ -#define CAN_BTR_TSEG0_Msk (0xFul << CAN_BTR_TSEG0_Pos) /*!< CAN_T::BTR: TSEG0 Mask */ +#define CAN_BTR_TSEG0_Pos 8 /*!< CAN_T::BTR: TSEG0 Position */ +#define CAN_BTR_TSEG0_Msk (0xFul << CAN_BTR_TSEG0_Pos) /*!< CAN_T::BTR: TSEG0 Mask */ -#define CAN_BTR_SJW_Pos 6 /*!< CAN_T::BTR: SJW Position */ -#define CAN_BTR_SJW_Msk (0x3ul << CAN_BTR_SJW_Pos) /*!< CAN_T::BTR: SJW Mask */ +#define CAN_BTR_SJW_Pos 6 /*!< CAN_T::BTR: SJW Position */ +#define CAN_BTR_SJW_Msk (0x3ul << CAN_BTR_SJW_Pos) /*!< CAN_T::BTR: SJW Mask */ -#define CAN_BTR_BRP_Pos 0 /*!< CAN_T::BTR: BRP Position */ -#define CAN_BTR_BRP_Msk (0x3Ful << CAN_BTR_BRP_Pos) /*!< CAN_T::BTR: BRP Mask */ +#define CAN_BTR_BRP_Pos 0 /*!< CAN_T::BTR: BRP Position */ +#define CAN_BTR_BRP_Msk (0x3Ful << CAN_BTR_BRP_Pos) /*!< CAN_T::BTR: BRP Mask */ /** * @brief CAN IR Bit Field Definitions */ -#define CAN_IR_INTID_Pos 0 /*!< CAN_T::IR: INTID Position */ -#define CAN_IR_INTID_Msk (0xFFFFul << CAN_IR_INTID_Pos) /*!< CAN_T::R: INTID Mask */ +#define CAN_IR_INTID_Pos 0 /*!< CAN_T::IR: INTID Position */ +#define CAN_IR_INTID_Msk (0xFFFFul << CAN_IR_INTID_Pos) /*!< CAN_T::IR: INTID Mask */ /** * @brief CAN TEST Bit Field Definitions */ -#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ -#define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */ +#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ +#define CAN_TEST_RX (1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX */ -#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ -#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */ +#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ +#define CAN_MODE_MONITORER (0x1ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: SP monitored */ +#define CAN_MODE_TX_DOMINANT (0x2ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX dominant */ +#define CAN_MODE_TX_RECESSIVE (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX recessive */ -#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ -#define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */ +#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ +#define CAN_MODE_LBACK (1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK */ -#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ -#define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ +#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ +#define CAN_MODE_SILENT (1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent */ -#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ -#define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ +#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ +#define CAN_MODE_BASIC (1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic */ /** * @brief CAN BPRE Bit Field Definitions */ -#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ -#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ +#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ /** * @brief CAN IFn_CREQ Bit Field Definitions */ -#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_T::IFnCREQ: BUSY Position */ -#define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_T::IFnCREQ: BUSY Mask */ +#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_T::IFnCREQ: BUSY Position */ +#define CAN_FLAG_IF_BUSY (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_T::IFnCREQ: BUSY FLAG */ -#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_T::IFnCREQ: MSGNUM Position */ -#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_T::IFnCREQ: MSGNUM Mask */ +#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_T::IFnCREQ: MSGNUM Position */ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_T::IFnCREQ: MSGNUM Mask */ /** * @brief CAN IFn_CMASK Bit Field Definitions */ -#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_T::IFnCMASK: WRRD Position */ -#define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_T::IFnCMASK: WRRD Mask */ +#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_T::IFnCMASK: WRRD Position */ +#define CAN_IF_CMASK_WRRD (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_T::IFnCMASK: WRRD */ -#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_T::IFnCMASK: MASK Position */ -#define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_T::IFnCMASK: MASK Mask */ +#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_T::IFnCMASK: MASK Position */ +#define CAN_IF_CMASK_MASK (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_T::IFnCMASK: MASK */ -#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_T::IFnCMASK: ARB Position */ -#define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_T::IFnCMASK: ARB Mask */ +#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_T::IFnCMASK: ARB Position */ +#define CAN_IF_CMASK_ARB (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_T::IFnCMASK: ARB */ -#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_T::IFnCMASK: CONTROL Position */ -#define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_T::IFnCMASK: CONTROL Mask */ +#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_T::IFnCMASK: CONTROL Position */ +#define CAN_IF_CMASK_CONTROL (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_T::IFnCMASK: CONTROL */ -#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_T::IFnCMASK: CLRINTPND Position */ -#define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_T::IFnCMASK: CLRINTPND Mask */ +#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_T::IFnCMASK: CLRINTPND Position */ +#define CAN_IF_CMASK_CLRINTPND (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_T::IFnCMASK: CLRINTPND */ -#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Position */ -#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Mask */ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Position */ +#define CAN_IF_CMASK_TXRQSTNEWDAT (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT */ -#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_T::IFnCMASK: DATAA Position */ -#define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_T::IFnCMASK: DATAA Mask */ +#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_T::IFnCMASK: DATAA Position */ +#define CAN_IF_CMASK_DATAA (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_T::IFnCMASK: DATAA */ -#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_T::IFnCMASK: DATAB Position */ -#define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_T::IFnCMASK: DATAB Mask */ +#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_T::IFnCMASK: DATAB Position */ +#define CAN_IF_CMASK_DATAB (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_T::IFnCMASK: DATAB */ /** * @brief CAN IFn_MASK0 Bit Field Definitions */ -#define CAN_IF_MASK0_MSK_Pos 0 /*!< CAN_T::IFnMASK0: MSK Position */ -#define CAN_IF_MASK0_MSK_Msk (0xFFul << CAN_IF_MASK0_MSK_Pos) /*!< CAN_T::IFnMASK0: MSK Mask */ +#define CAN_IF_MASK0_MSK_Pos 0 /*!< CAN_T::IFnMASK0: MSK Position */ +#define CAN_IF_MASK0_MSK_Msk (0xFFul << CAN_IF_MASK0_MSK_Pos) /*!< CAN_T::IFnMASK0: MSK Mask */ /** * @brief CAN IFn_MASK1 Bit Field Definitions */ #define CAN_IF_MASK1_MXTD_Pos 15 /*!< CAN_T::IFnMASK1: MXTD Position */ -#define CAN_IF_MASK1_MXTD_Msk (1ul << CAN_IF_MASK1_MXTD_Pos) /*!< CAN_T::IFnMASK1: MXTD Mask */ +#define CAN_IF_MASK1_MXTD (1ul << CAN_IF_MASK1_MXTD_Pos) /*!< CAN_T::IFnMASK1: MXTD */ #define CAN_IF_MASK1_MDIR_Pos 14 /*!< CAN_T::IFnMASK1: MDIR Position */ -#define CAN_IF_MASK1_MDIR_Msk (1ul << CAN_IF_MASK1_MDIR_Pos) /*!< CAN_T::IFnMASK1: MDIR Mask */ +#define CAN_IF_MASK1_MDIR (1ul << CAN_IF_MASK1_MDIR_Pos) /*!< CAN_T::IFnMASK1: MDIR */ -#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_T::IFnMASK1: MSK Position */ -#define CAN_IF_MASK1_MSK_Msk (0x1FFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_T::IFnMASK1: MSK Mask */ +#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_T::IFnMASK1: MSK Position */ +#define CAN_IF_MASK1_MSK_Msk (0x1FFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_T::IFnMASK1: MSK Mask */ /** * @brief CAN IFn_ARB0 Bit Field Definitions */ -#define CAN_IF_ARB0_ID_Pos 0 /*!< CAN_T::IFnARB0: ID Position */ -#define CAN_IF_ARB0_ID_Msk (0xFFFFul << CAN_IF_ARB0_ID_Pos) /*!< CAN_T::IFnARB0: ID Mask */ +#define CAN_IF_ARB0_ID_Pos 0 /*!< CAN_T::IFnARB0: ID Position */ +#define CAN_IF_ARB0_ID_Msk (0xFFFFul << CAN_IF_ARB0_ID_Pos) /*!< CAN_T::IFnARB0: ID Mask */ /** * @brief CAN IFn_ARB1 Bit Field Definitions */ -#define CAN_IF_ARB1_MSGVAL_Pos 15 /*!< CAN_T::IFnARB1: MSGVAL Position */ -#define CAN_IF_ARB1_MSGVAL_Msk (1ul << CAN_IF_ARB1_MSGVAL_Pos) /*!< CAN_T::IFnARB1: MSGVAL Mask */ +#define CAN_IF_ARB1_MSGVAL_Pos 15 /*!< CAN_T::IFnARB1: MSGVAL Position */ +#define CAN_IF_ARB1_MSGVAL (1ul << CAN_IF_ARB1_MSGVAL_Pos) /*!< CAN_T::IFnARB1: MSGVAL */ -#define CAN_IF_ARB1_XTD_Pos 14 /*!< CAN_T::IFnARB1: XTD Position */ -#define CAN_IF_ARB1_XTD_Msk (1ul << CAN_IF_ARB1_XTD_Pos) /*!< CAN_T::IFnARB1: XTD Mask */ +#define CAN_IF_ARB1_XTD_Pos 14 /*!< CAN_T::IFnARB1: XTD Position */ +#define CAN_IF_ARB1_XTD (1ul << CAN_IF_ARB1_XTD_Pos) /*!< CAN_T::IFnARB1: XTD */ -#define CAN_IF_ARB1_DIR_Pos 13 /*!< CAN_T::IFnARB1: DIR Position */ -#define CAN_IF_ARB1_DIR_Msk (1ul << CAN_IF_ARB1_DIR_Pos) /*!< CAN_T::IFnARB1: DIR Mask */ +#define CAN_IF_ARB1_DIR_Pos 13 /*!< CAN_T::IFnARB1: DIR Position */ +#define CAN_IF_ARB1_DIR (1ul << CAN_IF_ARB1_DIR_Pos) /*!< CAN_T::IFnARB1: DIR */ -#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_T::IFnARB1: ID Position */ -#define CAN_IF_ARB1_ID_Msk (0x1FFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_T::IFnARB1: ID Mask */ +#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_T::IFnARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0x1FFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_T::IFnARB1: ID Mask */ /** * @brief CAN IFn_MCR Bit Field Definitions */ #define CAN_IF_MCR_NEWDAT_Pos 15 /*!< CAN_T::IFnMCON: NEWDAT Position */ -#define CAN_IF_MCR_NEWDAT_Msk (1ul << CAN_IF_MCR_NEWDAT_Pos) /*!< CAN_T::IFnMCON: NEWDAT Mask */ +#define CAN_IF_MCR_NEWDAT (1ul << CAN_IF_MCR_NEWDAT_Pos) /*!< CAN_T::IFnMCON: NEWDAT */ #define CAN_IF_MCR_MSGLST_Pos 14 /*!< CAN_T::IFnMCON: MSGLST Position */ -#define CAN_IF_MCR_MSGLST_Msk (1ul << CAN_IF_MCR_MSGLST_Pos) /*!< CAN_T::IFnMCON: MSGLST Mask */ +#define CAN_IF_MCR_MSGLST (1ul << CAN_IF_MCR_MSGLST_Pos) /*!< CAN_T::IFnMCON: MSGLST */ #define CAN_IF_MCR_INTPND_Pos 13 /*!< CAN_T::IFnMCON: INTPND Position */ -#define CAN_IF_MCR_INTPND_Msk (1ul << CAN_IF_MCR_INTPND_Pos) /*!< CAN_T::IFnMCON: INTPND Mask */ +#define CAN_IF_MCR_INTPND (1ul << CAN_IF_MCR_INTPND_Pos) /*!< CAN_T::IFnMCON: INTPND */ #define CAN_IF_MCR_UMASK_Pos 12 /*!< CAN_T::IFnMCON: UMASK Position */ -#define CAN_IF_MCR_UMASK_Msk (1ul << CAN_IF_MCR_UMASK_Pos) /*!< CAN_T::IFnMCON: UMASK Mask */ +#define CAN_IF_MCR_UMASK (1ul << CAN_IF_MCR_UMASK_Pos) /*!< CAN_T::IFnMCON: UMASK */ #define CAN_IF_MCR_TXIE_Pos 11 /*!< CAN_T::IFnMCON: TXIE Position */ -#define CAN_IF_MCR_TXIE_Msk (1ul << CAN_IF_MCR_TXIE_Pos) /*!< CAN_T::IFnMCON: TXIE Mask */ +#define CAN_IF_MCR_TXIE (1ul << CAN_IF_MCR_TXIE_Pos) /*!< CAN_T::IFnMCON: TXIE */ #define CAN_IF_MCR_RXIE_Pos 10 /*!< CAN_T::IFnMCON: RXIE Position */ -#define CAN_IF_MCR_RXIE_Msk (1ul << CAN_IF_MCR_RXIE_Pos) /*!< CAN_T::IFnMCON: RXIE Mask */ +#define CAN_IF_MCR_RXIE (1ul << CAN_IF_MCR_RXIE_Pos) /*!< CAN_T::IFnMCON: RXIE */ #define CAN_IF_MCR_RMTEN_Pos 9 /*!< CAN_T::IFnMCON: RMTEN Position */ -#define CAN_IF_MCR_RMTEN_Msk (1ul << CAN_IF_MCR_RMTEN_Pos) /*!< CAN_T::IFnMCON: RMTEN Mask */ +#define CAN_IF_MCR_RMTEN (1ul << CAN_IF_MCR_RMTEN_Pos) /*!< CAN_T::IFnMCON: RMTEN */ #define CAN_IF_MCR_TXRQST_Pos 8 /*!< CAN_T::IFnMCON: TXRQST Position */ -#define CAN_IF_MCR_TXRQST_Msk (1ul << CAN_IF_MCR_TXRQST_Pos) /*!< CAN_T::IFnMCON: TXRQST Mask */ +#define CAN_IF_MCR_TXRQST (1ul << CAN_IF_MCR_TXRQST_Pos) /*!< CAN_T::IFnMCON: TXRQST */ #define CAN_IF_MCR_EOB_Pos 7 /*!< CAN_T::IFnMCON: EOB Position */ -#define CAN_IF_MCR_EOB_Msk (1ul << CAN_IF_MCR_EOB_Pos) /*!< CAN_T::IFnMCON: EOB Mask */ +#define CAN_IF_MCR_EOB (1ul << CAN_IF_MCR_EOB_Pos) /*!< CAN_T::IFnMCON: EOB */ #define CAN_IF_MCR_DLC_Pos 0 /*!< CAN_T::IFnMCON: DLC Position */ -#define CAN_IF_MCR_DLC_Msk (0xFul << CAN_IF_MCR_DLC_Pos) /*!< CAN_T::IFnMCON: DLC Mask */ +#define CAN_IF_MCR_DLC_Msk (0xFul << CAN_IF_MCR_DLC_Pos) /*!< CAN_T::IFnMCON: DLC Mask */ /** * @brief CAN IFn_DATA_A0 Bit Field Definitions */ -#define CAN_IF_DAT_A0_DATA1_Pos 8 /*!< CAN_T::IFnDATAA0: DATA1 Position */ -#define CAN_IF_DAT_A0_DATA1_Msk (0xFFul << CAN_IF_DAT_A0_DATA1_Pos) /*!< CAN_T::IFnDATAA0: DATA1 Mask */ +#define CAN_IF_DAT_A0_DATA1_Pos 8 /*!< CAN_T::IFnDATAA0: DATA1 Position */ +#define CAN_IF_DAT_A0_DATA1_Msk (0xFFul << CAN_IF_DAT_A0_DATA1_Pos) /*!< CAN_T::IFnDATAA0: DATA1 Mask */ -#define CAN_IF_DAT_A0_DATA0_Pos 0 /*!< CAN_T::IFnDATAA0: DATA0 Position */ -#define CAN_IF_DAT_A0_DATA0_Msk (0xFFul << CAN_IF_DAT_A0_DATA0_Pos) /*!< CAN_T::IFnDATAA0: DATA0 Mask */ +#define CAN_IF_DAT_A0_DATA0_Pos 0 /*!< CAN_T::IFnDATAA0: DATA0 Position */ +#define CAN_IF_DAT_A0_DATA0_Msk (0xFFul << CAN_IF_DAT_A0_DATA0_Pos) /*!< CAN_T::IFnDATAA0: DATA0 Mask */ /** * @brief CAN IFn_DATA_A1 Bit Field Definitions */ -#define CAN_IF_DAT_A1_DATA3_Pos 8 /*!< CAN_T::IFnDATAA1: DATA3 Position */ -#define CAN_IF_DAT_A1_DATA3_Msk (0xFFul << CAN_IF_DAT_A1_DATA3_Pos) /*!< CAN_T::IFnDATAA1: DATA3 Mask */ +#define CAN_IF_DAT_A1_DATA3_Pos 8 /*!< CAN_T::IFnDATAA1: DATA3 Position */ +#define CAN_IF_DAT_A1_DATA3_Msk (0xFFul << CAN_IF_DAT_A1_DATA3_Pos) /*!< CAN_T::IFnDATAA1: DATA3 Mask */ -#define CAN_IF_DAT_A1_DATA2_Pos 0 /*!< CAN_T::IFnDATAA1: DATA2 Position */ -#define CAN_IF_DAT_A1_DATA2_Msk (0xFFul << CAN_IF_DAT_A1_DATA2_Pos) /*!< CAN_T::IFnDATAA1: DATA2 Mask */ +#define CAN_IF_DAT_A1_DATA2_Pos 0 /*!< CAN_T::IFnDATAA1: DATA2 Position */ +#define CAN_IF_DAT_A1_DATA2_Msk (0xFFul << CAN_IF_DAT_A1_DATA2_Pos) /*!< CAN_T::IFnDATAA1: DATA2 Mask */ /** * @brief CAN IFn_DATA_B0 Bit Field Definitions */ -#define CAN_IF_DAT_B0_DATA5_Pos 8 /*!< CAN_T::IFnDATAB0: DATA5 Position */ -#define CAN_IF_DAT_B0_DATA5_Msk (0xFFul << CAN_IF_DAT_B0_DATA5_Pos) /*!< CAN_T::IFnDATAB0: DATA5 Mask */ +#define CAN_IF_DAT_B0_DATA5_Pos 8 /*!< CAN_T::IFnDATAB0: DATA5 Position */ +#define CAN_IF_DAT_B0_DATA5_Msk (0xFFul << CAN_IF_DAT_B0_DATA5_Pos) /*!< CAN_T::IFnDATAB0: DATA5 Mask */ -#define CAN_IF_DAT_B0_DATA4_Pos 0 /*!< CAN_T::IFnDATAB0: DATA4 Position */ -#define CAN_IF_DAT_B0_DATA4_Msk (0xFFul << CAN_IF_DAT_B0_DATA4_Pos) /*!< CAN_T::IFnDATAB0: DATA4 Mask */ +#define CAN_IF_DAT_B0_DATA4_Pos 0 /*!< CAN_T::IFnDATAB0: DATA4 Position */ +#define CAN_IF_DAT_B0_DATA4_Msk (0xFFul << CAN_IF_DAT_B0_DATA4_Pos) /*!< CAN_T::IFnDATAB0: DATA4 Mask */ /** * @brief CAN IFn_DATA_B1 Bit Field Definitions */ -#define CAN_IF_DAT_B1_DATA7_Pos 8 /*!< CAN_T::IFnDATAB1: DATA7 Position */ -#define CAN_IF_DAT_B1_DATA7_Msk (0xFFul << CAN_IF_DAT_B1_DATA7_Pos) /*!< CAN_T::IFnDATAB1: DATA7 Mask */ +#define CAN_IF_DAT_B1_DATA7_Pos 8 /*!< CAN_T::IFnDATAB1: DATA7 Position */ +#define CAN_IF_DAT_B1_DATA7_Msk (0xFFul << CAN_IF_DAT_B1_DATA7_Pos) /*!< CAN_T::IFnDATAB1: DATA7 Mask */ -#define CAN_IF_DAT_B1_DATA6_Pos 0 /*!< CAN_T::IFnDATAB1: DATA6 Position */ -#define CAN_IF_DAT_B1_DATA6_Msk (0xFFul << CAN_IF_DAT_B1_DATA6_Pos) /*!< CAN_T::IFnDATAB1: DATA6 Mask */ +#define CAN_IF_DAT_B1_DATA6_Pos 0 /*!< CAN_T::IFnDATAB1: DATA6 Position */ +#define CAN_IF_DAT_B1_DATA6_Msk (0xFFul << CAN_IF_DAT_B1_DATA6_Pos) /*!< CAN_T::IFnDATAB1: DATA6 Mask */ /** * @brief CAN IFn_TXRQST0 Bit Field Definitions */ -#define CAN_IF_TXRQST0_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST0: TXRQST Position */ -#define CAN_IF_TXRQST0_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST0_TXRQST_Pos) /*!< CAN_T::IFnTXRQST0: TXRQST Mask */ +#define CAN_IF_TXRQST0_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST0: TXRQST Position */ +#define CAN_IF_TXRQST0_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST0_TXRQST_Pos) /*!< CAN_T::IFnTXRQST0: TXRQST Mask */ /** * @brief CAN IFn_TXRQST1 Bit Field Definitions */ -#define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST1: TXRQST Position */ -#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN_T::IFnTXRQST1: TXRQST Mask */ +#define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST1: TXRQST Position */ +#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN_T::IFnTXRQST1: TXRQST Mask */ /** * @brief CAN IFn_NDAT0 Bit Field Definitions */ -#define CAN_IF_NDAT0_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT0: NEWDATA Position */ -#define CAN_IF_NDAT0_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT0_NEWDATA_Pos) /*!< CAN_T::IFnNDAT0: NEWDATA Mask */ +#define CAN_IF_NDAT0_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT0: NEWDATA Position */ +#define CAN_IF_NDAT0_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT0_NEWDATA_Pos) /*!< CAN_T::IFnNDAT0: NEWDATA Mask */ /** * @brief CAN IFn_NDAT1 Bit Field Definitions */ -#define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT1: NEWDATA Position */ -#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN_T::IFnNDAT1: NEWDATA Mask */ +#define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT1: NEWDATA Position */ +#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN_T::IFnNDAT1: NEWDATA Mask */ /** * @brief CAN IFn_IPND0 Bit Field Definitions */ -#define CAN_IF_IPND0_INTPND_Pos 0 /*!< CAN_T::IFnIPND0: INTPND Position */ -#define CAN_IF_IPND0_INTPND_Msk (0xFFFFul << CAN_IF_IPND0_INTPND_Pos) /*!< CAN_T::IFnIPND0: INTPND Mask */ +#define CAN_IF_IPND0_INTPND_Pos 0 /*!< CAN_T::IFnIPND0: INTPND Position */ +#define CAN_IF_IPND0_INTPND_Msk (0xFFFFul << CAN_IF_IPND0_INTPND_Pos) /*!< CAN_T::IFnIPND0: INTPND Mask */ /** * @brief CAN IFn_IPND1 Bit Field Definitions */ -#define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN_T::IFnIPND1: INTPND Position */ -#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN_T::IFnIPND1: INTPND Mask */ +#define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN_T::IFnIPND1: INTPND Position */ +#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN_T::IFnIPND1: INTPND Mask */ /** * @brief CAN IFn_MVLD0 Bit Field Definitions */ -#define CAN_IF_MVLD0_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD0: MSGVAL Position */ -#define CAN_IF_MVLD0_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD0_MSGVAL_Pos) /*!< CAN_T::IFnMVLD0: MSGVAL Mask */ +#define CAN_IF_MVLD0_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD0: MSGVAL Position */ +#define CAN_IF_MVLD0_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD0_MSGVAL_Pos) /*!< CAN_T::IFnMVLD0: MSGVAL Mask */ /** * @brief CAN IFn_MVLD1 Bit Field Definitions */ -#define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD1: MSGVAL Position */ -#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN_T::IFnMVLD1: MSGVAL Mask */ - -/** - * @brief CAN WUEN Bit Field Definitions - */ -#define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WUEN: WAKUP_EN Position */ -#define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WUEN: WAKUP_EN Mask */ - -/** - * @brief CAN WUSTATUS Bit Field Definitions - */ -#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WUSTATUS: WAKUP_STS Position */ -#define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WUSTATUS: WAKUP_STS Mask */ +#define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD1: MSGVAL Position */ +#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN_T::IFnMVLD1: MSGVAL Mask */ /** * @} */ @@ -453,31 +448,45 @@ typedef struct /** @defgroup CAN_Exported_Functions CAN exported functions * @{ */ +/* Initialization functions *********************************************************************************/ void CAN_DeInit(HT_CAN_TypeDef* CANx); -u32 CAN_SetBaudRate(HT_CAN_TypeDef *CANx, u32 u32BaudRate); -void CAN_Close(HT_CAN_TypeDef *CANx); -u32 CAN_Open(HT_CAN_TypeDef *CANx, u32 u32BaudRate, u32 u32Mode); -void CAN_CLR_INT_PENDING_BIT(HT_CAN_TypeDef *CANx, u32 u32MsgNum); -void CAN_EnableInt(HT_CAN_TypeDef *CANx, u32 u32Mask); -void CAN_DisableInt(HT_CAN_TypeDef *CANx, u32 u32Mask); -s32 CAN_Transmit(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); -s32 CAN_Receive(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); -s32 CAN_SetRxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_R_TypeDef* pCanMsg); -s32 CAN_SetTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); -s32 CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum); -void CAN_EnterInitMode(HT_CAN_TypeDef *CANx); -void CAN_LeaveInitMode(HT_CAN_TypeDef *CANx); -void CAN_WaitMsg(HT_CAN_TypeDef *CANx); -u32 CAN_GetCANBitRate(HT_CAN_TypeDef *CANx); +void CAN_Init(HT_CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); + +/* Interrupts and flags management functions ****************************************************************/ +void CAN_IntConfig(HT_CAN_TypeDef *CANx, u32 CAN_Int, ControlStatus NewState); +FlagStatus CAN_GetIntStatus(HT_CAN_TypeDef* CANx, u32 CAN_Int); +FlagStatus CAN_GetFlagStatus(HT_CAN_TypeDef* CANx, uint32_t CAN_Flag); +void CAN_ClearFlag(HT_CAN_TypeDef* CANx, uint32_t CAN_Flag); + +/* Error management functions *******************************************************************************/ +CAN_LastErrorCode_TypeDef CAN_GetLastErrorCode(HT_CAN_TypeDef* CANx); +u32 CAN_GetReceiveErrorCounter(HT_CAN_TypeDef* CANx); +u32 CAN_GetLSBTransmitErrorCounter(HT_CAN_TypeDef* CANx); +void CAN_BusOffRecovery(HT_CAN_TypeDef *CANx); + +/* Test Mode functions **************************************************************************************/ void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask); void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx); -u32 CAN_IsNewDataReceived(HT_CAN_TypeDef *CANx, u32 u8MsgObj); -s32 CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg); -s32 CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg); -s32 CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* pCanMsg); -s32 CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 u8MsgObj, u32 u8Release, STR_CANMSG_T_TypeDef* pCanMsg); -s32 CAN_MsgObjMaskConfig(HT_CAN_TypeDef *tCAN, u32 u8MsgObj, STR_CANMSG_R_TypeDef* MaskMsg); -s32 CAN_SetMultiRxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , u32 u32MsgCount, STR_CANMSG_R_TypeDef* pCanMsg); +ErrStatus CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); +ErrStatus CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8* len); + +/* Transmit/Receive functions *******************************************************************************/ +ErrStatus CAN_Transmit(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); +CAN_RxStatus_TypeDef CAN_Receive(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u32* len); +ErrStatus CAN_UpdateTxMsgData(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); +ErrStatus CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); + +/* Set Rx Message Object ************************************************************************************/ +ErrStatus CAN_SetRxMsg(HT_CAN_TypeDef *CANx ,CAN_MSG_TypeDef* pCanMsg, u32 FifoDepth); + +/* Message Object status function ***************************************************************************/ +ErrStatus CAN_CancelTransmit(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg); +ErrStatus CAN_DiscardRxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); +bool CAN_NewDataReceived(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); +s32 CAN_TransmitStatus(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg); +bool CAN_GetMsgPending(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg); +ErrStatus CAN_ClearMsgPendingFlag(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); +void CAN_ClearAllMsgPendingFlag(HT_CAN_TypeDef *CANx); /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h index 531078537b..cc5dabb858 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_ckcu.h - * @version $Rev:: 7108 $ - * @date $Date:: 2023-08-09 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the Clock Control Unit library. ************************************************************************************************************* * @attention @@ -425,9 +425,9 @@ typedef union unsigned long DIV :1; // Bit 24 unsigned long QSPI :1; // Bit 25 unsigned long RF :1; // Bit 26 - unsigned long :1; // Bit 27 + unsigned long PID0 :1; // Bit 27 unsigned long :1; // Bit 28 - unsigned long :1; // Bit 29 + unsigned long CORDIC :1; // Bit 29 unsigned long :1; // Bit 30 unsigned long :1; // Bit 31 @@ -494,8 +494,11 @@ typedef union unsigned long LCDC :1; // Bit 20 unsigned long DAC0 :1; // Bit 21 unsigned long CMP :1; // Bit 22 +#if defined(USE_HT32F66242) || defined(USE_HT32F66246) + unsigned long PGA :1; // Bit 23 +#else unsigned long OPA :1; // Bit 23 - +#endif unsigned long ADC0 :1; // Bit 24 unsigned long ADC1 :1; // Bit 25 unsigned long :1; // Bit 26 @@ -565,6 +568,9 @@ typedef enum #if (LIBCFG_OPA) CKCU_PCLK_OPA = (CKCU_APBPCSR1 | 10), #endif + #if (LIBCFG_PGA) + CKCU_PCLK_PGA = (CKCU_APBPCSR1 | 10), + #endif CKCU_PCLK_WDTR = (CKCU_APBPCSR1 | 12), CKCU_PCLK_BKPR = (CKCU_APBPCSR1 | 14), #if (LIBCFG_SCI0) @@ -679,6 +685,13 @@ typedef enum #define CKCU_PLL_16M_56M ((1UL << 28) | ( 7UL << 23) | (0UL << 21)) #endif +#if (LIBCFG_CKCU_SYS_CK_80M) +#define CKCU_PLL_4M_80M ((0UL << 28) | (20UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_80M ((0UL << 28) | (10UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_78M ((1UL << 28) | (13UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_80M ((0UL << 28) | ( 5UL << 23) | (0UL << 21)) +#endif + #define IS_PLL_CFG(CFG) (((CFG & 0xE81FFFFF) == 0x0) && (CFG != 0)) #endif @@ -699,13 +712,12 @@ typedef enum #define IS_USBPLL_CFG(CFG) (((CFG & 0xFFFFF81F) == 0x0) && (CFG != 0)) #endif - - - /* Definitions of MCU debug control */ #define CKCU_DBG_SLEEP (1UL) #define CKCU_DBG_DEEPSLEEP1 (1UL << 1) +#if (!LIBCFG_PWRCU_NO_PD_MODE) #define CKCU_DBG_POWERDOWN (1UL << 2) +#endif #define CKCU_DBG_WDT_HALT (1UL << 3) #if (LIBCFG_MCTM0) @@ -828,6 +840,14 @@ typedef enum #if (LIBCFG_CKCU_HSIRDYCR) #define IS_COUNTER_VALUE(VALUE) ((VALUE) < 0x20) #endif + +/* HSE Gain mode */ +#define CKCU_HSE_LOW_GAIN_MODE (0UL << 8) +#define CKCU_HSE_HIGH_GAIN_MODE (1UL << 8) + +#define IS_GAINMODE(GanMode) ((GanMode == CKCU_HSE_LOW_GAIN_MODE) || \ + (GanMode == CKCU_HSE_HIGH_GAIN_MODE)) + /** * @} */ @@ -904,7 +924,7 @@ void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd); FlagStatus CKCU_GetIntStatus(u32 CKCU_INT); void CKCU_ClearIntFlag(u32 CKCU_INT); -#if (((LIBCFG_LSE) || (LIBCFG_USBD)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +#if (((LIBCFG_LSE) || (LIBCFG_USBD) || (LIBCFG_CKCU_REFCLK_EXT_PIN)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) #if (LIBCFG_CKCU_ATM_V01) void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct); #endif @@ -914,8 +934,11 @@ bool CKCU_HSIAutoTrimIsReady(void); #endif #if (LIBCFG_CKCU_HSIRDYCR) -void CKCU_Set_HSIReadyCounter(u8 value); +void CKCU_SetHSIReadyCounter(u8 value); #endif + +void CKCU_SetHSEGainMode(u32 GanMode); + /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h index 5869bcd21c..5213360e5e 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_cmp.h - * @version $Rev:: 7319 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the CMP library. ************************************************************************************************************* * @attention @@ -59,7 +59,7 @@ typedef struct u32 CMP_ScalerEnable; u32 CMP_CoutSync; u32 CMP_OutputPol; - #if (LIBCFG_CMP_65x_VER) + #if (LIBCFG_CMP_65x_66x_VER) u32 CMP_InputSelection; #endif u32 CMP_InvInputSelection; @@ -108,7 +108,7 @@ typedef enum /* Definitions of CMP Output Selection for IP Trigger Source */ -#if (LIBCFG_CMP_65x_VER) +#if (LIBCFG_CMP_65x_66x_VER) #define CMP_TRIG_NONE ((u32)0x0 << 11) #define CMP_TRIG_GPTM_CH0 ((u32)0x1 << 11) // CMP0 #define CMP_TRIG_GPTM_CH1 ((u32)0x1 << 11) // CMP1 @@ -198,7 +198,7 @@ typedef enum /* Definitions of CMP Inverted Input Source Selection */ -#if (LIBCFG_CMP_65x_VER) +#if (LIBCFG_CMP_65x_66x_VER) #if (LIBCFG_CMP_POS_INPUT_SEL_V2) #define CMP_INPUT_CMPnP ((u32)0x00000000) #define CMP_INPUT_CMPnP0 ((u32)0x00000000) @@ -211,6 +211,26 @@ typedef enum (x == CMP_INPUT_CMPnP1) || \ (x == CMP_INPUT_CMPnP2) || \ (x == CMP_INPUT_OPA0O)) +#elif (LIBCFG_CMP_POS_INPUT_SEL_V3) +#define CMP_INPUT_CMP0P ((u32)0x00000000) +#define CMP_INPUT_CMP0P0 ((u32)0x00000000) +#define CMP_INPUT_CMP1P0 ((u32)0x00000001) +#define CMP_INPUT_CMP1P1 ((u32)0x00000002) +#define CMP_INPUT_CMP1P2 ((u32)0x00000003) +#define CMP_INPUT_PGA0O ((u32)0x00000004) +#define CMP_INPUT_PGA1O ((u32)0x00000005) +#define CMP_INPUT_PGA2O ((u32)0x00000006) +#define CMP_INPUT_PGA3O ((u32)0x00000007) + +#define IS_CMP_InputSelection(x) ((x == CMP_INPUT_CMP0P) || \ + (x == CMP_INPUT_CMP0P0) || \ + (x == CMP_INPUT_CMP1P0) || \ + (x == CMP_INPUT_CMP1P1) || \ + (x == CMP_INPUT_CMP1P2) || \ + (x == CMP_INPUT_PGA0O) || \ + (x == CMP_INPUT_PGA1O) || \ + (x == CMP_INPUT_PGA2O) || \ + (x == CMP_INPUT_PGA3O)) #else #define CMP_INPUT_CMPnP ((u32)0x00000000) #define CMP_INPUT_OPA0O ((u32)0x00000001) @@ -223,6 +243,22 @@ typedef enum /* Definitions of CMP Inverted Input Source Selection */ #define CMP_EXTERNAL_CN_IN ((u32)0x00000000) + +#if defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define CMP0_CMP0N_CN_IN ((u32)0x00000000) +#define CMP1_CMP1N_CN_IN ((u32)0x00000000) + +#define CMP0_CMP1N_CN_IN ((u32)0x00000010) +#define CMP1_CMP0N_CN_IN ((u32)0x00000010) + +#define CMP_CVREF0_CN_IN ((u32)0x00000020) +#define CMP_CVREF1_CN_IN ((u32)0x00000030) + +#define IS_CMP_InvInputSelection(x) ((x == CMP_EXTERNAL_CN_IN) || (x == CMP0_CMP0N_CN_IN) || (x == CMP1_CMP1N_CN_IN) || \ + (x == CMP0_CMP1N_CN_IN) || (x == CMP1_CMP0N_CN_IN) || \ + (x == CMP_CVREF0_CN_IN) || \ + (x == CMP_CVREF1_CN_IN)) +#else #define CMP_SCALER_CN_IN ((u32)0x00000010) #define IS_CMP_InvInSel2(x) (0) @@ -247,6 +283,7 @@ typedef enum #endif #define IS_CMP_InvInputSelection(x) ((x == CMP_EXTERNAL_CN_IN) || (x == CMP_SCALER_CN_IN) || IS_CMP_InvInSel2(x)) +#endif /* Definitions of CMP Hysteresis Level Selection */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h index 0ee8ba77d7..d3b2c90180 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_flash.h - * @version $Rev:: 5496 $ - * @date $Date:: 2021-07-19 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the FLASH library. ************************************************************************************************************* * @attention @@ -97,8 +97,13 @@ typedef struct #if (LIBCFG_FMC_WAIT_STATE_2) #define FLASH_WAITSTATE_2 (0x00000003) /* FLASH two wait state */ #endif +#if (LIBCFG_FMC_WAIT_STATE_3) +#define FLASH_WAITSTATE_3 (0x00000004) /* FLASH three wait state */ +#endif -#if (LIBCFG_FMC_WAIT_STATE_2) +#if (LIBCFG_FMC_WAIT_STATE_3) +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_3) +#elif (LIBCFG_FMC_WAIT_STATE_2) #define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_2) #else #define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_1) @@ -159,7 +164,7 @@ void FLASH_PrefetchBufferCmd(ControlStatus NewState); #if (LIBCFG_FMC_BRANCHCACHE) void FLASH_BranchCacheCmd(ControlStatus NewState); #endif -void FLASH_SetRemappingMode(FLASH_Vector RemapMode); +void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x); FLASH_State FLASH_ErasePage(u32 PageAddress); FLASH_State FLASH_EraseOptionByte(void); FLASH_State FLASH_MassErase(void); diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h index 42f274c4e7..8d0bc22df9 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_gpio.h - * @version $Rev:: 7115 $ - * @date $Date:: 2023-08-11 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the GPIO and AFIO library. ************************************************************************************************************* * @attention @@ -166,7 +166,15 @@ typedef enum #else #define AFIO_FUN_LEDC AFIO_MODE_14 /*!< AFIO mode LEDC */ #endif +#if ((LIBCFG_CMP) && (LIBCFG_OPA)) +#define AFIO_FUN_CMP AFIO_FUN_CMP_OPA /*!< AFIO mode CMP */ +#define AFIO_FUN_OPA AFIO_FUN_CMP_OPA /*!< AFIO mode OPA */ +#elif ((LIBCFG_CMP) && (LIBCFG_PGA)) +#define AFIO_FUN_CMP AFIO_FUN_CMP_PGA /*!< AFIO mode CMP */ +#define AFIO_FUN_PGA AFIO_FUN_CMP_PGA /*!< AFIO mode PGA */ +#elif (LIBCFG_CMP) #define AFIO_FUN_CMP AFIO_MODE_3 /*!< AFIO mode CMP */ +#endif #define AFIO_FUN_MCTM_GPTM AFIO_MODE_4 /*!< AFIO mode MCTM/GPTM */ #if (LIBCFG_AFIO_SCTM_MODE4) #define AFIO_FUN_SCTM AFIO_MODE_4 /*!< AFIO mode SCTM */ @@ -184,7 +192,11 @@ typedef enum #define AFIO_FUN_USART_UART AFIO_MODE_6 /*!< AFIO mode USART/UART */ #define AFIO_FUN_I2C AFIO_MODE_7 /*!< AFIO mode I2C */ #define AFIO_FUN_SCI AFIO_MODE_8 /*!< AFIO mode SCI */ +#if ((LIBCFG_CMP) && (LIBCFG_OPA)) #define AFIO_FUN_CMP_OPA AFIO_MODE_8 /*!< AFIO mode CMP/OPA */ +#elif ((LIBCFG_CMP) && (LIBCFG_PGA)) +#define AFIO_FUN_CMP_PGA AFIO_MODE_8 /*!< AFIO mode CMP/PGA */ +#endif #define AFIO_FUN_EBI AFIO_MODE_9 /*!< AFIO mode EBI */ #define AFIO_FUN_I2S AFIO_MODE_10 /*!< AFIO mode I2S */ #define AFIO_FUN_CAN AFIO_MODE_12 /*!< AFIO mode CAN */ @@ -465,7 +477,7 @@ void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GP void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA); void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); -#if LIBCFG_GPIO_SINK_CURRENT_ENHANCED +#if (LIBCFG_GPIO_SINK_CURRENT_ENHANCED) void GPIO_SinkConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n, ControlStatus Cmd); #endif FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h index 1f822f93d6..af864739f4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_i2c.h - * @version $Rev:: 7104 $ - * @date $Date:: 2023-08-08 #$ + * @version $Rev:: 7698 $ + * @date $Date:: 2024-04-15 #$ * @brief The header file of the I2C library. ************************************************************************************************************* * @attention @@ -347,7 +347,7 @@ typedef enum #define SEQ_FILTER_2_PCLK ((u32)0x00008000) #define IS_I2C_SEQ_FILTER_MASK(CONFIG) ((CONFIG == SEQ_FILTER_DISABLE) || \ - (CONFIG == SEQ_FILTER_1_PCLK) || \ + (CONFIG == SEQ_FILTER_1_PCLK) || \ (CONFIG == SEQ_FILTER_2_PCLK)) /** * @} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h index b04cdb33a4..d49a8a111d 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_lib.h - * @version $Rev:: 7319 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 7924 $ + * @date $Date:: 2024-08-07 #$ * @brief The header file includes all the header files of the libraries. ************************************************************************************************************* * @attention @@ -34,8 +34,8 @@ #endif /* Settings ------------------------------------------------------------------------------------------------*/ -#define HT32_FWLIB_VER (0x01009001) -#define HT32_FWLIB_SVN (0x7446) +#define HT32_FWLIB_VER (0x01014003) +#define HT32_FWLIB_SVN (0x8294) #if defined(USE_HT32F52220_30) #include "ht32f52220_30_libcfg.h" @@ -179,6 +179,10 @@ void assert_error(u8* file, u32 line); #include "ht32f5xxxx_cmp.h" #endif +#if _CORDIC && LIBCFG_CORDIC + #include "ht32f66xxx_cordic.h" +#endif + #if _CRC && LIBCFG_CRC #include "ht32f5xxxx_crc.h" #endif @@ -253,6 +257,14 @@ void assert_error(u8* file, u32 line); #include "ht32f5xxxx_pdma.h" #endif +#if _PGA && LIBCFG_PGA + #include "ht32f65xxx_66xxx_pga.h" +#endif + +#if _PID && LIBCFG_PID + #include "ht32f66xxx_pid.h" +#endif + #if _PWRCU #include "ht32f5xxxx_pwrcu.h" #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h index cbea7b628b..42da0d5588 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_mctm.h - * @version $Rev:: 5258 $ - * @date $Date:: 2021-02-04 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the MCTM library. ************************************************************************************************************* * @attention @@ -75,7 +75,7 @@ typedef union /* Definitions of CHBRKCTR */ unsigned long Break0 :1; // BK0E unsigned long Break0Polarity :1; // BK0P - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) unsigned long Break1 :1; // BK1E unsigned long Break1Polarity :1; // BK1E #else @@ -84,7 +84,7 @@ typedef union #endif unsigned long :1; // CHMOE unsigned long AutomaticOutput :1; // CHAOE - #if (LIBCFG_TM_65232) + #if (LIBCFG_TM_BK_FROM_CMP) unsigned long Break0FromCMP0 :1; // BK0CMP0 unsigned long Break0FromCMP1 :1; // BK0CMP1 #else @@ -92,7 +92,7 @@ typedef union unsigned long :1; #endif - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) unsigned long Break0EventCount :2; // BK0FN unsigned long Break0FDiv :2; // BK0FF unsigned long Break1EventCount :2; // BK1FN @@ -103,11 +103,11 @@ typedef union #endif unsigned long LockLevel :2; // LOCKLV - unsigned long DeglitchFilte :1; // GFSEL + unsigned long DeglitchFilter :1; // GFSEL unsigned long :1; unsigned long OSSIState :1; // CHOSSI unsigned long OSSRState :1; // CHOSSR - #if (LIBCFG_TM_65232) + #if (LIBCFG_TM_BK_FROM_CMP) unsigned long Break1FromCMP0 :1; // BK1CMP0 unsigned long Break1FromCMP1 :1; // BK1CMP1 #else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h index 1dbea97ba3..35cba593cd 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_pdma.h - * @version $Rev:: 7319 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the PDMA library. ************************************************************************************************************* * @attention @@ -134,7 +134,7 @@ typedef struct #define PDMA_DAC1_CH1 PDMA_CH5 /*!< DAC1 CH1 PDMA channel number */ #endif -#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F0006) || defined(USE_HT32F61244_45) +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F0006) || defined(USE_HT32F61244_45) || defined(USE_HT32F66242) || defined (USE_HT32F66246) #define PDMA_SPI0_RX PDMA_CH4 /*!< SPI0_RX PDMA channel number */ #define PDMA_SPI0_TX PDMA_CH5 /*!< SPI0_TX PDMA channel number */ #elif defined(USE_HT32F57342_52) || defined(USE_HT32F52357_67) || defined(USE_HT32F67041_51) || defined(USE_HT32F52234_44) @@ -196,6 +196,7 @@ typedef struct #endif #endif +#if (LIBCFG_I2C2) #if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) #define PDMA_I2C2_RX PDMA_CH0 /*!< I2C2_RX PDMA channel number */ #define PDMA_I2C2_TX PDMA_CH1 /*!< I2C2_TX PDMA channel number */ @@ -203,6 +204,7 @@ typedef struct #define PDMA_I2C2_RX PDMA_CH4 /*!< I2C2_RX PDMA channel number */ #define PDMA_I2C2_TX PDMA_CH5 /*!< I2C2_TX PDMA channel number */ #endif +#endif #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F57342_52) || defined(USE_HT32F52357_67) #define PDMA_SCI0_TX PDMA_CH5 /*!< SCI0_TX PDMA channel number */ @@ -228,7 +230,7 @@ typedef struct #if (LIBCFG_NO_GPTM0) #else -#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined (USE_HT32F66246) #define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ #define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ #define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ @@ -254,7 +256,7 @@ typedef struct #define PDMA_GPTM1_TRIG PDMA_CH5 /*!< GPTM1_TRIG PDMA channel number */ #endif -#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined (USE_HT32F66246) #define PDMA_SCTM0_CH0 PDMA_CH0 /*!< SCTM0_CH0 PDMA channel number */ #define PDMA_SCTM0_CH1 PDMA_CH1 /*!< SCTM0_CH1 PDMA channel number */ #define PDMA_SCTM1_CH0 PDMA_CH2 /*!< SCTM1_CH0 PDMA channel number */ @@ -318,6 +320,11 @@ typedef struct #define PDMA_MIDI_OUT PDMA_CH4 /*!< MIDI_OUT PDMA channel number */ #endif +#if (LIBCFG_CORDIC) +#define PDMA_CORDIC_WR PDMA_CH4 /*!< CORDIC_WR PDMA channel number */ +#define PDMA_CORDIC_RD PDMA_CH5 /*!< CORDIC_RD PDMA channel number */ +#endif + /* flag */ #define PDMA_FLAG_GE (1UL << 0) /*!< PDMA channel global event flag */ #define PDMA_FLAG_BE (1UL << 1) /*!< PDMA channel block end flag */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h index a98fb16289..45eba73ee5 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_pwrcu.h - * @version $Rev:: 7054 $ - * @date $Date:: 2023-07-24 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the Power Control Unit library. ************************************************************************************************************* * @attention @@ -64,6 +64,7 @@ typedef enum PWRCU_WAKEUP_PIN_1 #endif } PWRCU_WUP_Enum; + /** * @brief Wakeup pin trigger type selection */ @@ -82,6 +83,8 @@ typedef enum PWRCU_TIMEOUT, /*!< Time out */ PWRCU_ERROR /*!< Error */ } PWRCU_Status; + +#if (!LIBCFG_PWRCU_NO_DS2_MODE) /** * @brief DMOS status */ @@ -91,6 +94,8 @@ typedef enum PWRCU_DMOS_STS_OFF, /*!< DMOS off */ PWRCU_DMOS_STS_OFF_BY_BODRESET /*!< DMOS off caused by brow out reset */ } PWRCU_DMOSStatus; +#endif + /** * @brief LVD level selection */ @@ -105,6 +110,7 @@ typedef enum PWRCU_LVDS_LV7 = 0x00440000, /*!< LVD level 7 */ PWRCU_LVDS_LV8 = 0x00460000 /*!< LVD level 8 */ } PWRCU_LVDS_Enum; + #if (LIBCFG_PWRCU_VDD_5V) #define PWRCU_LVDS_2V65 PWRCU_LVDS_LV1 #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV2 @@ -133,6 +139,7 @@ typedef enum #define PWRCU_LVDS_2V95 PWRCU_LVDS_LV7 #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV8 #endif + /** * @brief BOD reset or interrupt selection */ @@ -141,6 +148,7 @@ typedef enum PWRCU_BODRIS_RESET = 0, /*!< Reset the whole chip */ PWRCU_BODRIS_INT = 1, /*!< Assert interrupt */ } PWRCU_BODRIS_Enum; + /** * @brief Sleep entry instruction selection */ @@ -149,6 +157,7 @@ typedef enum PWRCU_SLEEP_ENTRY_WFE = 0, /*!< Sleep then wait for event */ PWRCU_SLEEP_ENTRY_WFI /*!< Sleep then wait for interrupt */ } PWRCU_SLEEP_ENTRY_Enum; + #if (LIBCFG_BAKREG) /** * @brief Backup register selection @@ -167,6 +176,8 @@ typedef enum PWRCU_BAKREG_9 } PWRCU_BAKREG_Enum; #endif + +#if (LIBCFG_PWRCU_V15_READY_SOURCE) /** * @brief Vdd15 power good source selection */ @@ -175,6 +186,8 @@ typedef enum PWRCU_V15RDYSC_V33ISO = 0, /*!< Vdd15 power good source come from BK_ISO bit in CKCU unit */ PWRCU_V15RDYSC_V15POR /*!< Vdd15 power good source come from Vdd15 power on reset */ } PWRCU_V15RDYSC_Enum; +#endif + /** * @brief LDO operation mode selection */ @@ -183,6 +196,7 @@ typedef enum PWRCU_LDO_NORMAL = 0, /*!< The LDO is operated in normal current mode */ PWRCU_LDO_LOWCURRENT /*!< The LDO is operated in low current mode */ } PWRCU_LDOMODE_Enum; + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) /** * @brief HSI ready counter bit length selection @@ -195,6 +209,7 @@ typedef enum PWRCU_HSIRCBL_7 /*!< 7 bits (Default) */ } PWRCU_HSIRCBL_Enum; #endif + #if (LIBCFG_PWRCU_VREG) /** * @brief VREG output voltage selection @@ -210,6 +225,7 @@ typedef enum PWRCU_VREG_3V0 = 0x04000000, /*!< VREG output voltage is 3.0 V */ PWRCU_VREG_1V8 = 0x0C000000, /*!< VREG output voltage is 1.8 V */ } PWRCU_VREG_VOLT_Enum; + /** * @brief VREG operation mode */ @@ -220,6 +236,7 @@ typedef enum PWRCU_VREG_BYPASS = 0x02000000, /*!< VREG is bypassed */ } PWRCU_VREG_MODE_Enum; #endif + /** * @} */ @@ -254,17 +271,23 @@ typedef enum /* check PWRCU_BODRIS parameter */ #define IS_PWRCU_BODRIS(x) ((x == PWRCU_BODRIS_RESET) || (x == PWRCU_BODRIS_INT)) +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) /* check PWRCU_HSIRCBL parameter */ #define IS_PWRCU_HSIRCBL(x) (x <= 3) +#endif /* check PWRCU_SLEEP_ENTRY parameter */ #define IS_PWRCU_SLEEP_ENTRY(x) ((x == PWRCU_SLEEP_ENTRY_WFI) || (x == PWRCU_SLEEP_ENTRY_WFE)) +#if (LIBCFG_BAKREG) /* check PWRCU_BAKREG parameter */ #define IS_PWRCU_BAKREG(x) (x < 10) +#endif +#if (LIBCFG_PWRCU_V15_READY_SOURCE) /* check PWRCU_V15RDY_SRC parameter */ #define IS_PWRCU_V15RDYSC(x) ((x == PWRCU_V15RDYSC_V33ISO) || (x == PWRCU_V15RDYSC_V15POR)) +#endif /* check PWRCU_LDOMODE parameter */ #define IS_PWRCU_LDOMODE(x) ((x == PWRCU_LDO_NORMAL) || (x == PWRCU_LDO_LOWCURRENT)) @@ -324,10 +347,12 @@ void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA); #endif void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry); void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +#if (!LIBCFG_PWRCU_NO_DS2_MODE) void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry); #if !defined(USE_HT32F52220_30) void PWRCU_DeepSleep2Ex(PWRCU_SLEEP_ENTRY_Enum SleepEntry); #endif +#endif #if (!LIBCFG_PWRCU_NO_PD_MODE) void PWRCU_PowerDown(void); #endif @@ -338,8 +363,10 @@ void PWRCU_BODCmd(ControlStatus NewState); void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection); FlagStatus PWRCU_GetLVDFlagStatus(void); FlagStatus PWRCU_GetBODFlagStatus(void); +#if (!LIBCFG_PWRCU_NO_DS2_MODE) PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void); void PWRCU_DMOSCmd(ControlStatus NewState); +#endif #if (LIBCFG_PWRCU_V15_READY_SOURCE) void PWRCU_V15RDYSourceConfig(PWRCU_V15RDYSC_Enum Sel); #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h index 60eabde780..907452261a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_rstcu.h - * @version $Rev:: 7115 $ - * @date $Date:: 2023-08-11 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the Reset Control Unit library. ************************************************************************************************************* * @attention @@ -87,7 +87,7 @@ typedef union unsigned long :1; // Bit 14 unsigned long AES :1; // Bit 15 - #ifdef USE_HT32F65230_40 + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) unsigned long DIV :1; // Bit 16 #else unsigned long :1; // Bit 16 @@ -100,7 +100,7 @@ typedef union unsigned long :1; // Bit 22 unsigned long :1; // Bit 23 - #ifndef USE_HT32F65230_40 + #if !defined(USE_HT32F65230_40) && !defined(USE_HT32F65232) unsigned long DIV :1; // Bit 24 #else unsigned long :1; // Bit 24 @@ -108,8 +108,8 @@ typedef union unsigned long QSPI :1; // Bit 25 unsigned long RF :1; // Bit 26 unsigned long :1; // Bit 27 - unsigned long :1; // Bit 28 - unsigned long :1; // Bit 29 + unsigned long CORDIC :1; // Bit 28 + unsigned long PID0 :1; // Bit 29 unsigned long :1; // Bit 30 unsigned long :1; // Bit 31 @@ -176,8 +176,11 @@ typedef union unsigned long :1; // Bit 20 unsigned long DAC0 :1; // Bit 21 unsigned long CMP :1; // Bit 22 + #if defined(USE_HT32F66242) || defined(USE_HT32F66246) + unsigned long PGA :1; // Bit 23 + #else unsigned long OPA :1; // Bit 23 - + #endif unsigned long ADC0 :1; // Bit 24 unsigned long ADC1 :1; // Bit 25 unsigned long :1; // Bit 26 diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h index 0677ae6717..3544ae3744 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_rtc.h - * @version $Rev:: 7278 $ - * @date $Date:: 2023-10-04 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the RTC library. ************************************************************************************************************* * @attention @@ -60,6 +60,8 @@ typedef enum RTC_SRC_LSE /*!< Low speed external 32768 Hz clock */ #endif } RTC_SRC_Enum; + +#if (LIBCFG_LSE) /** * @brief Selection of RTC LSE startup mode */ @@ -68,6 +70,7 @@ typedef enum RTC_LSESM_NORMAL = 0, /*!< Little power consumption but longer startup time. */ RTC_LSESM_FAST /*!< Shortly startup time but higher power consumption. */ } RTC_LSESM_Enum; +#endif /** * @brief Selection of RTC prescaler */ @@ -107,7 +110,7 @@ typedef enum RTC_ROWM_LEVEL /*!< Level mode. */ } RTC_ROWM_Enum; /** - * @brief Waveform mode of RTC output + * @brief Event selection of RTC output */ typedef enum { @@ -166,10 +169,13 @@ typedef enum #define IS_RTC_SRC_LSE(x) (0) #endif #define IS_RTC_SRC(x) ((x == RTC_SRC_LSI) || IS_RTC_SRC_LSE(x)) + +#if (LIBCFG_LSE) /** * @brief Used to check RTC_LSESM_Enum parameter */ #define IS_RTC_LSESM(x) ((x == RTC_LSESM_NORMAL) || (x == RTC_LSESM_FAST)) +#endif /** * @brief Used to check RTC_RPRE_Enum parameter */ @@ -220,7 +226,9 @@ void RTC_ClockSourceConfig(RTC_SRC_Enum Source); #if (LIBCFG_RTC_LSI_LOAD_TRIM) void RTC_LSILoadTrimData(void); #endif +#if (LIBCFG_LSE) void RTC_LSESMConfig(RTC_LSESM_Enum Mode); +#endif void RTC_LSECmd(ControlStatus NewState); void RTC_CMPCLRCmd(ControlStatus NewState); void RTC_SetPrescaler(RTC_RPRE_Enum Psc); diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h index eb0d814f23..a94a2118f2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_tm.h - * @version $Rev:: 7319 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the TM library. ************************************************************************************************************* * @attention @@ -103,7 +103,7 @@ typedef enum TM_CHPSC_4 = 0x00080000, /*!< TM channel capture is done once every 4 event */ TM_CHPSC_8 = 0x000C0000 /*!< TM channel capture is done once every 8 event */ } TM_CHPSC_Enum; -#if (LIBCFG_TM_652XX_V1) +#if (LIBCFG_TM_65X_66X_V1) /** * @brief Enumeration of TM channel Filter (Fsampling) Clock Divider. */ @@ -176,7 +176,7 @@ typedef enum TM_CKDIV_OFF = 0x0000, /*!< fDTS = fCLKIN */ TM_CKDIV_2 = 0x0100, /*!< fDTS = fCLKIN / 2 */ TM_CKDIV_4 = 0x0200, /*!< fDTS = fCLKIN / 4 */ - #if (LIBCFG_TM_652XX_V1 || LIBCFG_TM_CKDIV_8) + #if (LIBCFG_TM_65X_66X_V1 || LIBCFG_TM_CKDIV_8) TM_CKDIV_8 = 0x0300, /*!< fDTS = fCLKIN / 8 */ #endif } TM_CKDIV_Enum; @@ -237,7 +237,7 @@ typedef enum TM_SMSEL_PAUSE = 0x0500, /*!< Slave pause mode */ TM_SMSEL_TRIGGER = 0x0600, /*!< Slave trigger mode */ TM_SMSEL_STIED = 0x0700, /*!< Rising edge of the selected trigger(STI) clock the counter */ - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) TM_SMSEL_DECODER4 = 0x0800, /*!< Pluse/Direction mode(Counter counts on Ch0, Count up/down on Ch1 */ #endif } TM_SMSEL_Enum; @@ -254,7 +254,7 @@ typedef enum TM_MMSEL_CH1OREF = 0x00050000, /*!< The CH1OREF signal is used as trigger output. */ TM_MMSEL_CH2OREF = 0x00060000, /*!< The CH2OREF signal is used as trigger output. */ TM_MMSEL_CH3OREF = 0x00070000, /*!< The CH3OREF signal is used as trigger output. */ - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) TM_MMSEL_VCLK = 0x000C0000 /*!< The VCLK signal is used as trigger output. */ #endif #if (LIBCFG_PWM_8_CHANNEL) @@ -314,7 +314,7 @@ typedef struct TM_CHP_Enum Polarity; /*!< Channel input polarity refer to \ref TM_CHP_Enum */ TM_CHCCS_Enum Selection; /*!< Channel capture source selection refer to \ref TM_CHCCS_Enum */ TM_CHPSC_Enum Prescaler; /*!< Channel Capture prescaler refer to \ref TM_CHPSC_Enum */ - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) TM_CHFDIV_Enum Fsampling; /*!< Digital filter Fsampling Frequency, it must fDTS/1 ~ fDTS/64 */ #if (LIBCFG_TM_TIFN_5BIT) u8 Event; /*!< Digital filter N-event counter Setting, it must be 0 ~ 31 */ @@ -352,7 +352,7 @@ typedef struct #define TM_INT_TEV 0x0400 /*!< Trigger interrupt */ #define TM_INT_BRKEV 0x0800 /*!< Break interrupt */ -#if (LIBCFG_TM_652XX_V1) +#if (LIBCFG_TM_65X_66X_V1) #define MCTM_INT_CH0CD 0x100000 /*!< Channel 0 Count-Down compare interrupt */ #define MCTM_INT_CH1CD 0x200000 /*!< Channel 1 Count-Down compare interrupt */ #define MCTM_INT_CH2CD 0x400000 /*!< Channel 2 Count-Down compare interrupt */ @@ -365,7 +365,7 @@ typedef struct #define MCTM_INT_OVER 0x2000 /*!< Counter overflow interrupt */ #define MCTM_INT_UNDER 0x4000 /*!< Counter underflow Interrupt */ -#if (LIBCFG_TM_65232) +#if (LIBCFG_TM_RECCDI) #define MCTM_INT_RECCDIF 0x8000 /*!< CCIF or CDIF Interrupt flag control by REPR */ #endif @@ -512,11 +512,11 @@ typedef struct * @brief Used to check parameter of the output compare mode. */ #define IS_TM_OM_CMP(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ - ((x) == TM_OM_MATCH_INACTIVE) || \ - ((x) == TM_OM_MATCH_ACTIVE) || \ - ((x) == TM_OM_MATCH_TOGGLE) || \ - ((x) == TM_OM_PWM1) || \ - ((x) == TM_OM_PWM2)) + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2)) /** * @brief Used to check parameter of the output mode. */ @@ -586,7 +586,7 @@ typedef struct /** * @brief Used to check parameter of the counter mode. */ -#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ +#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ (x == TM_CNT_MODE_CA1) || \ (x == TM_CNT_MODE_CA2) || \ (x == TM_CNT_MODE_CA3) || \ @@ -606,24 +606,24 @@ typedef struct /** * @brief Used to check parameter of the channel input selection. */ -#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ - (x == TM_CHCCS_INDIRECT) || \ - (x == TM_CHCCS_TRCED)) +#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ + (x == TM_CHCCS_INDIRECT) || \ + (x == TM_CHCCS_TRCED)) /** * @brief Used to check parameter of the channel capture prescaler. */ #define IS_TM_CHPSC(x) ((x == TM_CHPSC_OFF) || \ - (x == TM_CHPSC_2) || \ - (x == TM_CHPSC_4) || \ - (x == TM_CHPSC_8)) + (x == TM_CHPSC_2) || \ + (x == TM_CHPSC_4) || \ + (x == TM_CHPSC_8)) #if 0 /** * @brief Used to check parameter of the ETI prescaler. */ #define IS_TM_ETIPSC(x) ((x == TM_ETIPSC_OFF) || \ - (x == TM_ETIPSC_2) || \ - (x == TM_ETIPSC_4) || \ - (x == TM_ETIPSC_8)) + (x == TM_ETIPSC_2) || \ + (x == TM_ETIPSC_4) || \ + (x == TM_ETIPSC_8)) #endif /** * @brief Used to check parameter of the TM interrupt. @@ -804,7 +804,7 @@ typedef struct /** * @brief Used to check value of TM digital filter. */ -#if (LIBCFG_TM_652XX_V1) +#if (LIBCFG_TM_65X_66X_V1) #define IS_TM_FILTER(x) (x <= 0xFF) #else #define IS_TM_FILTER(x) (x <= 0xF) @@ -886,7 +886,9 @@ void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction); void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +#if 0 // M0+ not supported void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +#endif void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h index ae5fdd1c5e..ed96545ac7 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_wdt.h - * @version $Rev:: 1704 $ - * @date $Date:: 2017-08-17 #$ + * @version $Rev:: 7779 $ + * @date $Date:: 2024-06-24 #$ * @brief The header file of the WDT library. ************************************************************************************************************* * @attention @@ -72,14 +72,17 @@ /* WDT runs or halts in sleep and deep sleep1 mode */ /* WDT WDTSHLT mask */ -#define MODE0_WDTSHLT_BOTH ((u32)0x00000000) -#define MODE0_WDTSHLT_SLEEP ((u32)0x00004000) -#define MODE0_WDTSHLT_HALT ((u32)0x00008000) +#define WDT_SLEEP_HALT_NONE ((u32)0x00000000) +#define WDT_SLEEP_HALT_DEEPSLEEP ((u32)0x00004000) +#define WDT_SLEEP_HALT_ALL ((u32)0x00008000) -#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == MODE0_WDTSHLT_BOTH) || \ - (WDT_Mode == MODE0_WDTSHLT_SLEEP) || \ - (WDT_Mode == MODE0_WDTSHLT_HALT)) +#define MODE0_WDTSHLT_BOTH WDT_SLEEP_HALT_NONE +#define MODE0_WDTSHLT_SLEEP WDT_SLEEP_HALT_DEEPSLEEP +#define MODE0_WDTSHLT_HALT WDT_SLEEP_HALT_ALL +#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == WDT_SLEEP_HALT_NONE) || \ + (WDT_Mode == WDT_SLEEP_HALT_DEEPSLEEP) || \ + (WDT_Mode == WDT_SLEEP_HALT_ALL)) /* WDT Flag */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h index bbf4192d74..df5f4dfa9f 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f65230_40_libcfg.h - * @version $Rev:: 7184 $ - * @date $Date:: 2023-08-31 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -56,12 +56,13 @@ #define LIBCFG_BFTM1 (1) #define LIBCFG_CKCU_ATM_V01 (1) #define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_LPCR (1) #define LIBCFG_CKCU_PLLSRCDIV (1) #define LIBCFG_CKCU_SYS_CK_60M (1) #define LIBCFG_CMP (1) #define LIBCFG_CMP2 (1) #define LIBCFG_CMP_NOSCALER_SRC (1) -#define LIBCFG_CMP_65x_VER (1) +#define LIBCFG_CMP_65x_66x_VER (1) #define LIBCFG_CRC (1) #define LIBCFG_DIV (1) #define LIBCFG_EXTI_4_9_GROUP (1) @@ -75,6 +76,7 @@ #define LIBCFG_MCTM_UEV1DIS (1) #define LIBCFG_PWRCU_NO_PD_MODE (1) #define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_DS2_MODE (1) #define LIBCFG_PWRCU_NO_VDDPORF (1) #define LIBCFG_NO_PWRCU_TEST_REG (1) #define LIBCFG_OPA (1) @@ -85,7 +87,7 @@ #define LIBCFG_SCTM1 (1) #define LIBCFG_SCTM2 (1) #define LIBCFG_SCTM3 (1) -#define LIBCFG_TM_652XX_V1 (1) +#define LIBCFG_TM_65X_66X_V1 (1) #define LIBCFG_PWRCU_VDD_5V (1) #define LIBCFG_PWRCU_NO_PORF (1) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h index 8787c99413..6909553bc4 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f65232_libcfg.h - * @version $Rev:: 6932 $ - * @date $Date:: 2023-05-11 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -52,11 +52,12 @@ #define LIBCFG_BFTM1 (1) #define LIBCFG_CKCU_ATM_V01 (1) #define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_LPCR (1) #define LIBCFG_CKCU_PLLSRCDIV (1) #define LIBCFG_CKCU_SYS_CK_60M (1) #define LIBCFG_CMP (1) #define LIBCFG_CMP_NOSCALER_SRC (1) -#define LIBCFG_CMP_65x_VER (1) +#define LIBCFG_CMP_65x_66x_VER (1) #define LIBCFG_CMP_POS_INPUT_SEL_V2 (1) #define LIBCFG_CMP_CO (1) #define LIBCFG_CMP_SCALER_8BIT (1) @@ -72,6 +73,7 @@ #define LIBCFG_MCTM_UEV1DIS (1) #define LIBCFG_PWRCU_NO_PD_MODE (1) #define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_DS2_MODE (1) #define LIBCFG_PWRCU_NO_VDDPORF (1) #define LIBCFG_NO_PWRCU_TEST_REG (1) #define LIBCFG_OPA (1) @@ -81,10 +83,9 @@ #define LIBCFG_SCTM1 (1) #define LIBCFG_SCTM2 (1) #define LIBCFG_SCTM3 (1) -#define LIBCFG_TM_652XX_V1 (1) -#define LIBCFG_TM_65232 (1) +#define LIBCFG_TM_65X_66X_V1 (1) +#define LIBCFG_TM_BK_FROM_CMP (1) #define LIBCFG_TM_TIFN_5BIT (1) #define LIBCFG_PWRCU_VDD_5V (1) -#define LIBCFG_PWRCU_NO_PORF (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h index 0b0313fc40..35f8689af8 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f65xxx_66xxx_adc.h - * @version $Rev:: 7058 $ - * @date $Date:: 2023-07-27 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the ADC library. ************************************************************************************************************* * @attention @@ -67,6 +67,7 @@ ((HP_MODE) == CONTINUOUS_MODE) || \ ((HP_MODE) == DISCONTINUOUS_MODE)) +#if (LIBCFG_ADC1) #define DUAL_INDEPENDENT (0x00000000) #define DUAL_CASCADE_REGULAR (0x00000001) #define DUAL_CASCADE_REGULAR_H_PRIORITY (0x00000003) @@ -74,6 +75,7 @@ #define IS_ADC_DUAL_MODE(DUAL_MODE) (((DUAL_MODE) == DUAL_INDEPENDENT) || \ ((DUAL_MODE) == DUAL_CASCADE_REGULAR) || \ ((DUAL_MODE) == DUAL_CASCADE_REGULAR_H_PRIORITY)) +#endif #if (LIBCFG_ADC_CH_65232) #define ADC_CH_0 (0) @@ -106,6 +108,44 @@ ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ ((CHANNEL) == ADC_CH_OPA0)) +#elif (LIBCFG_ADC_CH_66XXX_V1) +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#define ADC_CH_PGA0O (12) +#define ADC_CH_PGA1O (13) +#define ADC_CH_PGA2O (14) +#define ADC_CH_PGA3O (15) +#define ADC_CH_BANDGAP (16) +#define ADC_CH_MVDDA (17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + ((CHANNEL) == ADC_CH_PGA0O) || ((CHANNEL) == ADC_CH_PGA1O) || \ + ((CHANNEL) == ADC_CH_PGA2O) || ((CHANNEL) == ADC_CH_PGA3O) || \ + ((CHANNEL) == ADC_CH_BANDGAP) || ((CHANNEL) == ADC_CH_MVDDA)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + ((CHANNEL) == ADC_CH_PGA0O) || ((CHANNEL) == ADC_CH_PGA1O) || \ + ((CHANNEL) == ADC_CH_PGA2O) || ((CHANNEL) == ADC_CH_PGA3O)) #else #define ADC_CH_0 (0) #define ADC_CH_1 (1) @@ -170,8 +210,14 @@ #define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) #define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#if (LIBCFG_CMP2) #define ADC_TRIG_CMP2 ((1UL << 4) | (2UL << 20)) +#define IS_ADC_TRIG_CMP2(REGTRIG) ((REGTRIG == ADC_TRIG_CMP2)) +#else +#define IS_ADC_TRIG_CMP2(REGTRIG) (0) +#endif + #define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) #define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) @@ -225,7 +271,7 @@ ((REGTRIG) == ADC_TRIG_BFTM1) || \ ((REGTRIG) == ADC_TRIG_CMP0) || \ ((REGTRIG) == ADC_TRIG_CMP1) || \ - ((REGTRIG) == ADC_TRIG_CMP2) || \ + (IS_ADC_TRIG_CMP2(REGTRIG)) || \ ((REGTRIG) == ADC_TRIG_EXTI_0) || \ ((REGTRIG) == ADC_TRIG_EXTI_1) || \ ((REGTRIG) == ADC_TRIG_EXTI_2) || \ @@ -256,7 +302,7 @@ #define ADC_INT_DATA_OVERWRITE (0x01000000) #define ADC_INT_HP_DATA_OVERWRITE (0x02000000) -#define IS_ADC_INT(INT) ((((INT) & 0xFCFCFF88) == 0) && ((INT) != 0)) +#define IS_ADC_INT(INT) ((((INT) & 0xFCFCF8F8) == 0) && ((INT) != 0)) #define ADC_FLAG_SINGLE_EOC (0x00000001) @@ -270,7 +316,7 @@ #define ADC_FLAG_DATA_OVERWRITE (0x01000000) #define ADC_FLAG_HP_DATA_OVERWRITE (0x02000000) -#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCFF88) == 0) && ((FLAG) != 0)) +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCF8F8) == 0) && ((FLAG) != 0)) #define ADC_REGULAR_DATA0 (0) @@ -289,8 +335,22 @@ #define ADC_HP_DATA1 (1) #define ADC_HP_DATA2 (2) #define ADC_HP_DATA3 (3) +#if (LIBCFG_ADC_HDR_4_11) +#define ADC_HP_DATA4 (4) +#define ADC_HP_DATA5 (5) +#define ADC_HP_DATA6 (6) +#define ADC_HP_DATA7 (7) +#define ADC_HP_DATA8 (8) +#define ADC_HP_DATA9 (9) +#define ADC_HP_DATA10 (10) +#define ADC_HP_DATA11 (11) +#endif +#if (LIBCFG_ADC_HDR_4_11) +#define IS_ADC_HP_DATA(DATA) ((DATA) < 12) +#else #define IS_ADC_HP_DATA(DATA) ((DATA) < 4) +#endif #define ADC_AWD_DISABLE (u8)0x00 @@ -329,20 +389,34 @@ #define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) +#if (!LIBCFG_ADC_NO_OFFSET_REG) #define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) +#endif #define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 8) +#if (LIBCFG_ADC_HDR_4_11) +#define IS_ADC_HP_RANK(RANK) ((RANK) < 12) +#else #define IS_ADC_HP_RANK(RANK) ((RANK) < 4) +#endif #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) #define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) +#if (LIBCFG_ADC_HCONV_LENGTH_V2) +#define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) +#define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) +#else #define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) #define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 4)) +#endif +#if (LIBCFG_ADC_TRIG_DELAY) #define IS_ADC_TRIG_DELAY(DELAY) ((DELAY) < 256) +#endif +#if (!LIBCFG_ADC_NO_OFFSET_REG) typedef enum { ADC_ALIGN_RIGHT = (0 << 14), @@ -350,6 +424,7 @@ typedef enum } ADC_ALIGN_Enum; #define IS_ADC_ALIGN(ALIGN) (((ALIGN) == ADC_ALIGN_RIGHT) || ((ALIGN) == ADC_ALIGN_LEFT)) +#endif /** * @} */ @@ -373,9 +448,11 @@ void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 Sampl void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); +#if (!LIBCFG_ADC_NO_OFFSET_REG) void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x); void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue); void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState); +#endif #if (LIBCFG_ADC_TRIG_DELAY) void ADC_TrigDelayConfig(HT_ADC_TypeDef* HT_ADCn, u8 HDelayTime, u8 DelayTime); @@ -397,6 +474,14 @@ void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); + +#if (LIBCFG_ADC_IVREF) +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#endif + +#if (LIBCFG_ADC_MVDDA) +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#endif /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h index f8cfc6cca8..495ca58923 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f65xxx_66xxx_opa.h - * @version $Rev:: 6911 $ - * @date $Date:: 2023-05-10 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The header file of the OPA library. ************************************************************************************************************* * @attention @@ -57,11 +57,6 @@ typedef struct { u32 OPA_ScalerEnable; u32 OPA_ExternalPinEnable; - #if (LIBCFG_OPA_PGA) - u32 OPA_PGAEnable; - u32 OPA_UnitGainEnable; - u32 OPA_PGAGain; - #endif } OPA_InitTypeDef; /** * @brief Enumeration of OPA PGA Gain. @@ -115,14 +110,6 @@ typedef enum #define OPA_ExternalPin_ENABLE ((u32)0x00000008) #define OPA_ExternalPin_DISABLE ((u32)0x00000000) -/* Definitions of OPA PGA Enable Bit */ -#define OPA_PGA_ENABLE ((u32)0x00000004) -#define OPA_PGA_DISABLE ((u32)0x00000000) - -/* Definitions of OPA UnitGain Enable Bit */ -#define OPA_UNITGAIN_ENABLE ((u32)0x00000002) -#define OPA_UNITGAIN_DISABLE ((u32)0x00000000) - /* Definitions of OPA Output Status */ #define OPA_OUTPUT_HIGH ((u32)0x00000080) #define OPA_OUTPUT_LOW ((u32)0x00000000) @@ -140,19 +127,6 @@ typedef enum #define IS_OPA_ExtPinEnable(x) ((x == OPA_ExternalPin_ENABLE) || (x == OPA_ExternalPin_DISABLE)) -#define IS_OPA_PGAEnable(x) ((x == OPA_PGA_ENABLE) || (x == OPA_PGA_DISABLE)) - -#define IS_OPA_UnitGainEnable(x) ((x == OPA_UNITGAIN_ENABLE) || (x == OPA_UNITGAIN_DISABLE)) - -#define IS_OPA_PGA_SEL(SEL) ((SEL == PGA_GAIN_5) || (SEL == PGA_GAIN_6) || \ - (SEL == PGA_GAIN_7) || (SEL == PGA_GAIN_8) || \ - (SEL == PGA_GAIN_11) || (SEL == PGA_GAIN_12) || \ - (SEL == PGA_GAIN_15) || (SEL == PGA_GAIN_16) || \ - (SEL == PGA_GAIN_23) || (SEL == PGA_GAIN_24) || \ - (SEL == PGA_GAIN_31) || (SEL == PGA_GAIN_32) || \ - (SEL == PGA_GAIN_47) || (SEL == PGA_GAIN_48) || \ - (SEL == PGA_GAIN_63) || (SEL == PGA_GAIN_64)) - #define IS_OPA_OFMMODE(MODE) ((MODE == OPA_OFFSET_CALIBRATION_MODE) || \ (MODE == OPA_NORMAL_MODE)) @@ -183,11 +157,6 @@ void OPA_UnprotectConfig(HT_OPA_TypeDef* HT_OPAn); void OPA_Init(HT_OPA_TypeDef* HT_OPAn, OPA_InitTypeDef* OPA_InitStruct); void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); void OPA_ExternalInputCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); -#if (LIBCFG_OPA_PGA) -void OPA_UnitGainCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); -void OPA_PGACmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); -void OPA_PGAGain(HT_OPA_TypeDef* HT_OPAn, u8 bGAIN_SEL); -#endif void OPA_ScalerCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); void OPA_SetScalerValue(HT_OPA_TypeDef* HT_OPAn, u32 Scaler_Value); FlagStatus OPA_GetOutputStatus(HT_OPA_TypeDef* HT_OPAn); diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h index c72336c2fa..740ae8da56 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f65xxx_66xxx_pga.h - * @version $Rev:: 6915 $ - * @date $Date:: 2023-05-10 #$ - * @brief The header file of the PGA library (temporary file, not finish/support yet). + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ + * @brief The header file of the PGA library. ************************************************************************************************************* * @attention * @@ -44,8 +44,109 @@ * @{ */ +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PGA_Exported_Types PGA exported types + * @{ + */ +#define PGA_GAIN_LEVEL_0 (0x0) +#define PGA_GAIN_LEVEL_1 (0x1) +#define PGA_GAIN_LEVEL_2 (0x2) +#define PGA_GAIN_LEVEL_3 (0x3) +#define PGA_GAIN_LEVEL_4 (0x4) +#define PGA_GAIN_LEVEL_5 (0x5) +/** + * @brief Enumeration of PGA Gain Type 1. + */ +typedef enum +{ + /* PGAnPGA = 1, PGAnHVDDAEN[1:0] = b0x, PGAnNUG = 0 */ + PGA_GAIN_6 = PGA_GAIN_LEVEL_0, + PGA_GAIN_8 = PGA_GAIN_LEVEL_1, + PGA_GAIN_12 = PGA_GAIN_LEVEL_2, + PGA_GAIN_16 = PGA_GAIN_LEVEL_3, + PGA_GAIN_24 = PGA_GAIN_LEVEL_4, + PGA_GAIN_32 = PGA_GAIN_LEVEL_5, +} PGA_GAIN_TYPE1_Enum; +/** + * @brief Enumeration of PGA Gain Type 2. + */ +typedef enum +{ + /* PGAnPGA = 1, PGAnHVDDAEN[1:0] = b10, PGAnNUG = 0 */ + PGA_GAIN_5 = PGA_GAIN_LEVEL_0, + PGA_GAIN_7 = PGA_GAIN_LEVEL_1, + PGA_GAIN_11 = PGA_GAIN_LEVEL_2, + PGA_GAIN_15 = PGA_GAIN_LEVEL_3, + PGA_GAIN_23 = PGA_GAIN_LEVEL_4, + PGA_GAIN_31 = PGA_GAIN_LEVEL_5, +} PGA_GAIN_TYPE2_Enum; +/** + * @brief Enumeration of Calibration Reference Input. + */ +typedef enum +{ + PGA_CALIBRATION_INPUT_NEGATIVE = 0, + PGA_CALIBRATION_INPUT_POSITIVE = 1, +} PGA_CALIBRATION_INPUT_Enum; +/** + * @brief Definition of PGA init structure. + */ +typedef struct +{ + u8 PGA_REF; + u8 PGA_NUG; + u8 PGA_NE; + u8 PGA_PGA; + u8 PGA_HVDDA; +} PGA_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PGA_Exported_Constants PGA exported constants + * @{ + */ +#define PGA_UNPROTECT_KEY (0x9C3A) + +#define PGA_HVDDA_DISABLE (0x0) +#define PGA_HVDDA_RESISTOR (0x2) +#define PGA_HVDDA_POS_INPUT (0x3) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PGA_Exported_Functions PGA exported functions + * @{ + */ +void PGA_DeInit(void); +void PGA_Cmd(HT_PGA0_X_TypeDef* HT_PGAn, ControlStatus NewState); +void PGA_SetUnProtectKey(u32 uUnProtectKey); +void PGA_ProtectConfig(HT_PGA0_X_TypeDef* HT_PGAn); +void PGA_UnprotectConfig(HT_PGA0_X_TypeDef* HT_PGAn); +void PGA_Init(HT_PGA0_X_TypeDef* HT_PGAn, PGA_InitTypeDef* PGA_InitStruct); +void PGA_StructInit(PGA_InitTypeDef* PGA_InitStruct); +void PGA_GainConfig(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x); +void PGA_HVDDACmd(ControlStatus NewState); +void PGA_CalibrationCmd(HT_PGA0_X_TypeDef* HT_PGAn, ControlStatus NewState); +void PGA_SetCalibrationInput(HT_PGA0_X_TypeDef* HT_PGAn, PGA_CALIBRATION_INPUT_Enum PGA_INPUT_x); +void PGA_SetCalibrationValue(HT_PGA0_X_TypeDef* HT_PGAn, u32 Value); +FlagStatus PGA_ReadOutputBit(HT_PGA0_X_TypeDef* HT_PGAn); +void PGA_SetModeInverting(HT_PGA0_X_TypeDef* HT_PGAn, PGA_GAIN_TYPE1_Enum PGA_GAIN_x); +void PGA_SetModeDifferentiator(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x); +void PGA_SetModeNonInverting(HT_PGA0_X_TypeDef* HT_PGAn, PGA_GAIN_TYPE1_Enum PGA_GAIN_x); +void PGA_SetModeInvertingAdder(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x); +void PGA_SetModeExponent(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x); +void PGA_SetModeManual(HT_PGA0_X_TypeDef* HT_PGAn); +void PGA_SetModeNonInvertingAdder(HT_PGA0_X_TypeDef* HT_PGAn, PGA_GAIN_TYPE1_Enum PGA_GAIN_x); +void PGA_SetModeComparator(HT_PGA0_X_TypeDef* HT_PGAn); + +/** + * @} + */ /** * @} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h index 953106da19..8a64ca1567 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f66242_libcfg.h - * @version $Rev:: 7184 $ - * @date $Date:: 2023-08-31 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -44,9 +44,65 @@ #define LIBCFG_CHIPNAME (0x66242) #endif +#define LIBCFG_ADC_SAMPLE_TIME_BY_CH (1) #define LIBCFG_ADC_NO_OFFSET_REG (1) +#define LIBCFG_ADC_CH_66XXX_V1 (1) +#define LIBCFG_ADC_TRIG_SRC_V2 (1) +#define LIBCFG_ADC_TRIG_DELAY (1) +#define LIBCFG_ADC_HCONV_LENGTH_V2 (1) +#define LIBCFG_ADC_HDR_4_11 (1) +#define LIBCFG_ADC_STR_16_17 (1) +#define LIBCFG_ADC_HLST_0_2 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AFIO_SCTM_MODE9 (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_LPCR (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_SYS_CK_80M (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP_65x_66x_VER (1) +#define LIBCFG_CMP_CO (1) +#define LIBCFG_CMP_NOSCALER_SRC (1) +#define LIBCFG_CMP_POS_INPUT_SEL_V3 (1) +#define LIBCFG_CMP_SCALER_8BIT (1) +#define LIBCFG_CRC (1) +#define LIBCFG_CORDIC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_MCTM_UEV1DIS (1) #define LIBCFG_GPIOC (1) -#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_GPTM_GIRQ (1) #define LIBCFG_PDMA (1) +#define LIBCFG_PGA (1) +#define LIBCFG_PGA1 (1) +#define LIBCFG_PGA2 (1) +#define LIBCFG_PGA3 (1) +#define LIBCFG_PID (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_NO_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_DS2_MODE (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_TM_65X_66X_V1 (1) +#define LIBCFG_TM_BK_FROM_CMP (1) +#define LIBCFG_TM_RECCDI (1) +#define LIBCFG_TM_TIFN_5BIT (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h index 90a37a1703..ef490dac1c 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f66246_libcfg.h - * @version $Rev:: 7184 $ - * @date $Date:: 2023-08-31 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief The library configuration file. ************************************************************************************************************* * @attention @@ -44,9 +44,66 @@ #define LIBCFG_CHIPNAME (0x66246) #endif +#define LIBCFG_ADC_SAMPLE_TIME_BY_CH (1) #define LIBCFG_ADC_NO_OFFSET_REG (1) +#define LIBCFG_ADC_CH_66XXX_V1 (1) +#define LIBCFG_ADC_TRIG_SRC_V2 (1) +#define LIBCFG_ADC_TRIG_DELAY (1) +#define LIBCFG_ADC_HCONV_LENGTH_V2 (1) +#define LIBCFG_ADC_HDR_4_11 (1) +#define LIBCFG_ADC_STR_16_17 (1) +#define LIBCFG_ADC_HLST_0_2 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AFIO_SCTM_MODE9 (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CAN0 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_LPCR (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_SYS_CK_80M (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP_65x_66x_VER (1) +#define LIBCFG_CMP_CO (1) +#define LIBCFG_CMP_NOSCALER_SRC (1) +#define LIBCFG_CMP_POS_INPUT_SEL_V3 (1) +#define LIBCFG_CMP_SCALER_8BIT (1) +#define LIBCFG_CRC (1) +#define LIBCFG_CORDIC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_MCTM_UEV1DIS (1) #define LIBCFG_GPIOC (1) -#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_GPTM_GIRQ (1) #define LIBCFG_PDMA (1) +#define LIBCFG_PGA (1) +#define LIBCFG_PGA1 (1) +#define LIBCFG_PGA2 (1) +#define LIBCFG_PGA3 (1) +#define LIBCFG_PID (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_NO_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_DS2_MODE (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_TM_65X_66X_V1 (1) +#define LIBCFG_TM_BK_FROM_CMP (1) +#define LIBCFG_TM_RECCDI (1) +#define LIBCFG_TM_TIFN_5BIT (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) #endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h index 1c25b4c036..24e7abaf07 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f66xxx_cordic.h - * @version $Rev:: 6915 $ - * @date $Date:: 2023-05-10 #$ - * @brief The header file of the CORDIC library (temporary file, not finish/support yet). + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ + * @brief The header file of the CORDIC library. ************************************************************************************************************* * @attention * @@ -44,7 +44,243 @@ * @{ */ +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Types CORDIC exported types + * @{ + */ +typedef struct +{ + u32 Function; + u32 Scale; + u32 InSize; + u32 OutSize; + u32 NbWrite; + u32 NbRead; + u32 Precision; +} CORDIC_InitTypeDef; +/** + * @} + */ +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Constants CORDIC exported constants + * @{ + */ +/************************ Bit definition for CORDIC_CSR register **********************/ +#define CORDIC_CSR_FUNC_POS (0U) +#define CORDIC_CSR_FUNC_MASK (0xFUL << CORDIC_CSR_FUNC_POS) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_MASK /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_POS) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_POS) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_POS) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_POS) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_POS (4U) +#define CORDIC_CSR_PRECISION_MASK (0xFUL << CORDIC_CSR_PRECISION_POS) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_MASK /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_POS) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_POS) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_POS) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_POS) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_POS (8U) +#define CORDIC_CSR_SCALE_MASK (0x7UL << CORDIC_CSR_SCALE_POS) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_MASK /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_POS) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_POS) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_POS) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_POS (16U) +#define CORDIC_CSR_IEN_MASK (0x1UL << CORDIC_CSR_IEN_POS) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_MASK /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_POS (17U) +#define CORDIC_CSR_DMAREN_MASK (0x1UL << CORDIC_CSR_DMAREN_POS) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_MASK /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_POS (18U) +#define CORDIC_CSR_DMAWEN_MASK (0x1UL << CORDIC_CSR_DMAWEN_POS) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_MASK /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_POS (19U) +#define CORDIC_CSR_NRES_MASK (0x1UL << CORDIC_CSR_NRES_POS) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_MASK /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_POS (20U) +#define CORDIC_CSR_NARGS_MASK (0x3UL << CORDIC_CSR_NARGS_POS) /*!< 0x00300000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_MASK /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_NARGS_0 (0x1UL << CORDIC_CSR_NARGS_POS) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS_1 (0x2UL << CORDIC_CSR_NARGS_POS) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE_POS (22U) +#define CORDIC_CSR_RESSIZE_MASK (0x1UL << CORDIC_CSR_RESSIZE_POS) /*!< 0x00400000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_MASK /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_POS (23U) +#define CORDIC_CSR_ARGSIZE_MASK (0x1UL << CORDIC_CSR_ARGSIZE_POS) /*!< 0x00800000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_MASK /*!< Width of input data */ +#define CORDIC_CSR_RRDY_POS (31U) +#define CORDIC_CSR_RRDY_MASK (0x1UL << CORDIC_CSR_RRDY_POS) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_MASK /*!< Result Ready Flag */ + +/************************ Bit definition for CORDIC_WDATA register ********************/ +#define CORDIC_WDATA_ARG_POS (0U) +#define CORDIC_WDATA_ARG_MASK (0xFFFFFFFFUL << CORDIC_WDATA_ARG_POS) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_MASK /*!< Input Argument */ + +/************************ Bit definition for CORDIC_RDATA register ********************/ +#define CORDIC_RDATA_RES_POS (0U) +#define CORDIC_RDATA_RES_MASK (0xFFFFFFFFUL << CORDIC_RDATA_RES_POS) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_MASK /*!< Output Result */ + +/** @defgroup CORDIC_Function CORDIC Function + * @{ + */ +#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */ +#define CORDIC_FUNCTION_SINE ((u32)(CORDIC_CSR_FUNC_0)) /*!< Sine */ +#define CORDIC_FUNCTION_PHASE ((u32)(CORDIC_CSR_FUNC_1)) /*!< Phase */ +#define CORDIC_FUNCTION_MODULUS ((u32)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */ +#define CORDIC_FUNCTION_ARCTANGENT ((u32)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */ +#define CORDIC_FUNCTION_HCOSINE ((u32)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */ +#define CORDIC_FUNCTION_HSINE ((u32)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */ +#define CORDIC_FUNCTION_HARCTANGENT ((u32)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ +#define CORDIC_FUNCTION_NATURALLOG ((u32)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ +#define CORDIC_FUNCTION_SQUAREROOT ((u32)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ +#define CORDIC_FUNCTION_ROTATIONMATRIX ((u32)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_1)) /*!< Rotation Matrix */ +#define CORDIC_FUNCTION_INTEGERMODULUS ((u32)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Integer Modulus */ +#define CORDIC_FUNCTION_INTEGERSQUAREROOT ((u32)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_2)) /*!< Integer Square Root */ +/** + * @} + */ + +/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number + * @{ + */ +/* Note: 1 cycle corresponds to 4 algorithm iterations */ +#define CORDIC_PRECISION_1CYCLE ((u32)(CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_2CYCLES ((u32)(CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_3CYCLES ((u32)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_4CYCLES ((u32)(CORDIC_CSR_PRECISION_2)) +#define CORDIC_PRECISION_5CYCLES ((u32)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_6CYCLES ((u32)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_7CYCLES ((u32)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_8CYCLES ((u32)(CORDIC_CSR_PRECISION_3)) +#define CORDIC_PRECISION_9CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_10CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_11CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_12CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) +#define CORDIC_PRECISION_13CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_14CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_15CYCLES ((u32)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 |CORDIC_CSR_PRECISION_0)) +/** + * @} + */ + +/** @defgroup CORDIC_Scale CORDIC Scaling factor + * @{ + */ +/* Scale factor value 'n' implies that the input data have been multiplied + by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */ +#define CORDIC_SCALE_0 (0x00000000U) +#define CORDIC_SCALE_1 ((u32)(CORDIC_CSR_SCALE_0)) +#define CORDIC_SCALE_2 ((u32)(CORDIC_CSR_SCALE_1)) +#define CORDIC_SCALE_3 ((u32)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) +#define CORDIC_SCALE_4 ((u32)(CORDIC_CSR_SCALE_2)) +#define CORDIC_SCALE_5 ((u32)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) +#define CORDIC_SCALE_6 ((u32)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) +#define CORDIC_SCALE_7 ((u32)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) +/** + * @} + */ + +/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit + * @{ + */ +#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ +/** + * @} + */ + +/** @defgroup CORDIC_DMAR DMA Read Request Enable bit + * @{ + */ +#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ +/** + * @} + */ + +/** @defgroup CORDIC_DMAW DMA Write Request Enable bit + * @{ + */ +#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ +/** + * @} + */ + +/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation + * @{ + */ +#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bit data input (Q1.31 format), or two 16-bit + data input (Q1.15 format) packed in one 32 bits + Data */ +#define CORDIC_NBWRITE_2 ((u32)(CORDIC_CSR_NARGS_0)) /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ +#define CORDIC_NBWRITE_3 ((u32)(CORDIC_CSR_NARGS_1)) /*!< Three 32-bit write containing three 32-bits data input + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation + * @{ + */ +#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bit data output (Q1.31 format), or two 16-bit + data output (Q1.15 format) packed in one 32 bits + Data */ +#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_In_Size CORDIC input data size + * @{ + */ +#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ +#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_Out_Size CORDIC Results Size + * @{ + */ +#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ +#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_Flags CORDIC status flags + * @{ + */ +#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Functions CORDIC exported functions + * @{ + */ +void CORDIC_DeInit(void); +void CORDIC_Init(CORDIC_InitTypeDef *CORDIC_InitStruct); +void CORDIC_IntCmd(ControlStatus NewState); +void CORDIC_PDMACmd(u32 CORDIC_DMA, ControlStatus NewState); +FlagStatus CORDIC_GetFlagStatus_RRDY(void); +void CORDIC_WriteData(u32 InData); +u32 CORDIC_ReadData(void); + +/** + * @} + */ /** diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h index c47671643c..56d3bbe830 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f66xxx_pid.h - * @version $Rev:: 6915 $ - * @date $Date:: 2023-05-10 #$ - * @brief The header file of the PID library (temporary file, not finish/support yet). + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ + * @brief The header file of the PID library. ************************************************************************************************************* * @attention * @@ -44,8 +44,105 @@ * @{ */ +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PID_Exported_Types PID exported types + * @{ + */ +/** + * @brief PID PID_Mode + */ +typedef enum +{ + PID_SPD_MODE = 0, + PID_IQ_MODE, + PID_ID_MODE, + PID_FWNK_MODE, + PID_PLL_MODE, + PID_USR_MODE, +} PID_Mode_Enum; +#define IS_PID_MODE(PID_MODE) (((PID_MODE) == PID_SPD_MODE) || \ + ((PID_MODE) == PID_IQ_MODE) || \ + ((PID_MODE) == PID_ID_MODE) || \ + ((PID_MODE) == PID_FWNK_MODE) || \ + ((PID_MODE) == PID_PLL_MODE) || \ + ((PID_MODE) == PID_USR_MODE)) + +/** + * @brief PID paramater init structure + */ +typedef struct +{ + s32 ERRn_1; + s32 UIn_1; + s32 KP; + s32 KI; + s32 KD; + s32 UI_MAX; + s32 UI_MIN; + s16 OUT_MAX; + s16 OUT_MIN; +} PID_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PID_Exported_Constants PID exported constants + * @{ + */ +#define IS_PID(x) IS_PID0(x) +#define IS_PID0(x) (x == HT_PID0) + +/** + * @brief PID CR Bit Field Definitions + */ +#define PID_CR_MODSEL_Pos 24 +#define PID_CR_MODSEL_Msk (0xFul << PID_CR_MODSEL_Pos) + +#define PID_CR_UIF (0x00000008) +#define PID_CR_PIDEN (0x00000001) + +#define PID_FLAG_OVF (0x00020000) +#define PID_FLAG_CMP (0x00000200) + +#define IS_PID_FLAG(FLAG) ((FLAG == PID_FLAG_OVF) || \ + (FLAG == PID_FLAG_CMP)) + +#define PID_INT_OVF (0x00010000) +#define PID_INT_CMP (0x00000100) + +#define IS_PID_INT(INT) ((INT == PID_INT_OVF) || \ + (INT == PID_INT_CMP)) + +#define PID_INT_Status_Pos 2 +#define PID_INT_Clear_Pos 3 + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PID_Exported_Functions PID exported functions + * @{ + */ +void PID_DeInit(HT_PID_TypeDef* HT_PIDn); +void PID_Init(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode, PID_InitTypeDef* PID_Para); +void PID_IntConfig(HT_PID_TypeDef* HT_PIDn, u32 PID_INT_x, ControlStatus NewState); +FlagStatus PID_GetIntStatus(HT_PID_TypeDef* HT_PIDn, u32 PID_INT_x); +void PID_ClearIntPendingBit(HT_PID_TypeDef* HT_PIDn, u32 PID_INT_x); +void PID_SetComPara_ERRn(HT_PID_TypeDef* HT_PIDn, s32 ERRn); +void PID_SetComPara_UI_Input(HT_PID_TypeDef* HT_PIDn, s32 UI_Input); +void PID_Compute(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode); +s16 PID_GetOutResult(HT_PID_TypeDef* HT_PIDn); +FlagStatus PID_GetFlagStatus(HT_PID_TypeDef* HT_PIDn, u32 PID_FLAG_x); +void PID_UI_InputCmd(HT_PID_TypeDef* HT_PIDn, ControlStatus NewState); +s32 PID_GetERRn_1(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode); +s32 PID_GetUIn_1(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode); +/** + * @} + */ /** * @} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c index 91fc97ab99..80a7b66eac 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32_cm0plus_misc.c - * @version $Rev:: 5377 $ - * @date $Date:: 2021-05-26 #$ + * @version $Rev:: 7888 $ + * @date $Date:: 2024-07-22 #$ * @brief This file provides all the miscellaneous firmware functions. ************************************************************************************************************* * @attention @@ -221,7 +221,7 @@ u32 RBIT(u32 in) u32 uRBIT = 0; s32 i; - for(i = 31; i >=0; i--) + for (i = 31; i >=0; i--) { uRBIT |= ((in & 0x1) << i); in = in >> 1; @@ -229,6 +229,99 @@ u32 RBIT(u32 in) return uRBIT; } + +#if 0 +// Copy the code below to the begin of the main(). +// START + + #if (HTCFG_STACK_USAGE_ANALYSIS == 1) + /* !!! NOTICE !!! + Please update the Keil HT32 PACK and HT32 Firmware Library to the latest version to make sure the + Stack Usage Analysis function works properly. + */ + /* + Set HTCFG_STACK_USAGE_ANALYSIS as 1 in the "ht32xxxxxx_conf.h" to enable Stack Usage Analysis feature. + This feature is only applicable to the Keil MDK-ARM. Please call the "StackUsageAnalysisInit()" function + in the begin of the "main()". + The "StackUsageAnalysisInit()" parameter shall be the start address of the vector table. + Under Keil Debug mode, tick "View > Watch Window > HT32 Stack Usage Analysis" to show the stack usage + information. Those information is only valid after calling "StackUsageAnalysisInit()" function. + */ + StackUsageAnalysisInit(0x00000000); + #endif + +// END +#endif + +#if (HTCFG_STACK_USAGE_ANALYSIS == 1) +#if defined (__CC_ARM) +#define STACKLIMITADDR 0x20000010 +#define STACKSTART 0x20000014 +u32 _StackLimit __attribute__((at(STACKLIMITADDR)))= HT_SRAM_BASE + LIBCFG_RAM_SIZE; +u32 _StackStart __attribute__((at(STACKSTART)))= HT_SRAM_BASE; +/*********************************************************************************************************//** + * @brief Stack Usage Analysis Init + * @retval None + ***********************************************************************************************************/ +__ASM void StackUsageAnalysisInit(u32 addr) +{ + extern _StackLimit; + extern __HT_check_sp; + extern _StackStart; + LDR R0, [r0] + LDR R1, =_StackLimit + STR R0, [r1] + + LDR R0, =__HT_check_sp + LDR R1, =_StackStart + STR R0, [r1] + MOV R1, SP + LDR R2, =0xCDCDCDCD + LDR R3, =0xABABABAB + STR R3, [ R0 ] + B Loop_Check +Loop + STR R2, [ R0 ] +Loop_Check + ADDS R0, R0, #0x04 + CMP R0, R1 + BLT Loop + BX LR + ALIGN +} +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define STACKLIMITADDR "0x20000010" +#define STACKSTART "0x20000014" +u32 _StackLimit __attribute__((section(".ARM.__at_"STACKLIMITADDR))) = HT_SRAM_BASE + LIBCFG_RAM_SIZE; +u32 _StackStart __attribute__((section(".ARM.__at_"STACKSTART))) = HT_SRAM_BASE; +/*********************************************************************************************************//** + * @brief Stack Usage Analysis Init + * @retval None + ***********************************************************************************************************/ +__attribute__((noinline)) void StackUsageAnalysisInit(u32 addr) +{ + __ASM volatile (" LDR R0, [r0]"); + __ASM volatile (" LDR R1, =_StackLimit"); + __ASM volatile (" STR R0, [r1]"); + + __ASM volatile (" LDR R0, =__HT_check_sp"); + __ASM volatile (" LDR R1, =_StackStart"); + __ASM volatile (" STR R0, [r1]"); + __ASM volatile (" MOV R1, SP"); + __ASM volatile (" LDR R2, =0xCDCDCDCD"); + __ASM volatile (" LDR R3, =0xABABABAB"); + __ASM volatile (" STR R3, [ R0 ]"); + __ASM volatile (" B Loop_Check"); + __ASM volatile ("Loop:"); + __ASM volatile (" STR R2, [ R0 ]"); + __ASM volatile ("Loop_Check:"); + __ASM volatile (" ADDS R0, R0, #0x04"); + __ASM volatile (" CMP R0, R1"); + __ASM volatile (" BLT Loop"); + __ASM volatile (" BX LR"); +} +#endif +#endif /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c index d244507c11..af11e3bd48 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_adc.c - * @version $Rev:: 7366 $ - * @date $Date:: 2023-12-06 #$ + * @version $Rev:: 7691 $ + * @date $Date:: 2024-04-02 #$ * @brief This file provides all the ADC firmware functions. ************************************************************************************************************* * @attention @@ -90,6 +90,7 @@ void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) Assert_Param(IS_ADC(HT_ADCn)); HT_ADCn->CR |= ADC_SOFTWARE_RESET; + while ((HT_ADCn->CR & ADC_SOFTWARE_RESET) != 0); } /*********************************************************************************************************//** @@ -107,6 +108,7 @@ void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) if (NewState != DISABLE) { HT_ADCn->CR |= ADC_ENABLE_BIT; + ADC_Reset(HT_ADCn); } else { @@ -539,12 +541,13 @@ void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x) #if (LIBCFG_ADC_VREFBUF) /*********************************************************************************************************//** - * @brief Enable or Disable the VREF output. When enable, the VREF provides a stable voltage output to the ADVREFP pin (ADC reference positive voltage). + * @brief Enable or Disable the VREF output. When enable, the VREF provides a stable voltage output to the + ADVREFP pin (ADC reference positive voltage). * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. * @param NewState: This parameter can be ENABLE or DISABLE. * @retval None ************************************************************************************************************/ -void ADC_VREFOutputCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +void ADC_VREFOutputADVREFPCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) { /* !!! NOTICE !!! The ADCREFP pin should not be connected to an external voltage when the VREF output is enabled. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c index 133889a258..cce69677ec 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_aes.c - * @version $Rev:: 7390 $ - * @date $Date:: 2023-12-12 #$ - * @brief This file provides all the ADC firmware functions. + * @version $Rev:: 8205 $ + * @date $Date:: 2024-10-15 #$ + * @brief This file provides all the AES firmware functions. ************************************************************************************************************* * @attention * @@ -355,12 +355,12 @@ void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize) } HT_AESn->CR = uCRTemp; - for (i = 0; i < keySize; i += 4) + for (i = 0; i < (keySize / 4); i++) { #if (LIBCFG_AES_SWAP) - HT_AESn->KEYR[i >> 2] = __REV(*&Key[i]); + HT_AESn->KEYR[i] = __REV(*&Key[i]); #else - HT_AESn->KEYR[i >> 2] = *&Key[i]; + HT_AESn->KEYR[i] = *&Key[i]; #endif } @@ -378,12 +378,12 @@ void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector) int i; Assert_Param(IS_AES(HT_AESn)); - for (i = 0; i < 16; i += 4) + for (i = 0; i < 4; i++) { #if (LIBCFG_AES_SWAP) - HT_AESn->IVR[i >> 2] = __REV(*&Vector[i]); + HT_AESn->IVR[i] = __REV(*&Vector[i]); #else - HT_AESn->IVR[i >> 2] = *&Vector[i]; + HT_AESn->IVR[i] = *&Vector[i]; #endif } } diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c index 22fca5ab02..0287f0469a 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_can.c - * @version $Rev:: 7187 $ - * @date $Date:: 2023-08-31 #$ + * @version $Rev:: 8284 $ + * @date $Date:: 2024-11-22 #$ * @brief This file provides all the CAN firmware functions. ************************************************************************************************************* * @attention @@ -37,6 +37,7 @@ * @{ */ + /* Private types -------------------------------------------------------------------------------------------*/ typedef enum { @@ -45,9 +46,18 @@ typedef enum IF_TOTAL_NUM } CANIF_NUMBER_Enum; - /* Private function prototypes -----------------------------------------------------------------------------*/ -static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx); +static HT_CANIF_TypeDef *_GetFreeIF(HT_CAN_TypeDef *CANx); +static void _CAN_EnterInitMode(HT_CAN_TypeDef *CANx); +static void _CAN_LeaveInitMode(HT_CAN_TypeDef *CANx); +static void _CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgNum, CAN_MSG_TypeDef* pCanMsg, u32 uSingleOrFifoLast); +static s32 _CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 MsgNum, u32 Release, CAN_MSG_TypeDef* pCanMsg, u8* data, u32* len); +static ErrStatus _CAN_SetTxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); +static int _CAN_GetValidMsg(HT_CAN_TypeDef *CANx); +static bool _CAN_GetNewData(HT_CAN_TypeDef *CANx, u32 MsgNum); +static bool _CAN_CheckMsgIsValid(HT_CAN_TypeDef *CANx, u32 MsgNum); +static void _CAN_ClearMsgPendingFlag(HT_CAN_TypeDef *CANx, u32 MsgNum); +static volatile bool gIsBusOff = FALSE; /* Global functions ----------------------------------------------------------------------------------------*/ /** @defgroup CAN_Exported_Functions CAN exported functions @@ -73,943 +83,1049 @@ void CAN_DeInit(HT_CAN_TypeDef* CANx) } /*********************************************************************************************************//** - * @brief This function is used to set CAN to enter initialization mode and enable access bit timing - * register.After bit timing configuration ready, user must call CAN_LeaveInitMode() - * to leave initialization mode and lock bit timing register to let new configuration - * take effect. - * @param CANx: The pointer to CAN module base address. + * @brief Set CAN operation mode and target baud-rate. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure. * @retval None ***********************************************************************************************************/ -void CAN_EnterInitMode(HT_CAN_TypeDef *CANx) +void CAN_Init(HT_CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) { - CANx->CR |= CAN_CR_INIT_Msk; - CANx->CR |= CAN_CR_CCE_Msk; -} + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); -/*********************************************************************************************************//** - * @brief Leave initialization mode - * @param CANx: The pointer to CAN module base address. - * @retval None - ***********************************************************************************************************/ -void CAN_LeaveInitMode(HT_CAN_TypeDef *CANx) -{ - CANx->CR &= (~(CAN_CR_INIT_Msk | CAN_CR_CCE_Msk)); + _CAN_EnterInitMode(CANx); - while(CANx->CR & CAN_CR_INIT_Msk); /* Check INIT bit is released */ -} + CANx->BTR = (((u32)(CAN_InitStruct->CAN_TSEG1 - 1) << CAN_BTR_TSEG1_Pos) & CAN_BTR_TSEG1_Msk)| + (((u32)(CAN_InitStruct->CAN_TSEG0 -1) << CAN_BTR_TSEG0_Pos) & CAN_BTR_TSEG0_Msk)| + (((u32)(CAN_InitStruct->CAN_BRPrescaler -1) << CAN_BTR_BRP_Pos) & CAN_BTR_BRP_Msk) | + (((u32)(CAN_InitStruct->CAN_SJW -1) << CAN_BTR_SJW_Pos) & CAN_BTR_SJW_Msk); -/*********************************************************************************************************//** - * @brief This function is used to Wait message into message buffer in basic mode. Please notice the - * function is polling NEWDAT bit of MCR register by while loop and it is used in basic mode. - * @param CANx: The pointer to CAN module base address. - * @retval None - ***********************************************************************************************************/ -void CAN_WaitMsg(HT_CAN_TypeDef *CANx) -{ - CANx->SR = 0x0; /* clr status */ + CANx->BRPER = (CAN_InitStruct->CAN_BRPrescaler >> 6) & CAN_BRPE_BRPE_Msk; + _CAN_LeaveInitMode(CANx); - while(1) + if (CAN_InitStruct->CAN_NART) + HT_CAN0->CR |= CAN_CR_DAR; + + if (CAN_InitStruct->CAN_Mode) { - if(CANx->IF1.MCR & CAN_IF_MCR_NEWDAT_Msk) /* check new data */ - { - /*DEBUG_PRINTF("New Data IN\n");*/ - break; - } - if(CANx->SR & CAN_SR_RXOK_Msk) - { - /*DEBUG_PRINTF("Rx OK\n");*/ - } - if(CANx->SR & CAN_SR_LEC_Msk) - { - /*DEBUG_PRINTF("Error\n");*/ - } + CAN_EnterTestMode(CANx, CAN_InitStruct->CAN_Mode); + } + CAN_IntConfig(CANx, CAN_INT_EIE | CAN_INT_IE , ENABLE); + + return; +} + +/**********************************************************************************************************//** + * @brief Enable or Disable the specified CAN interrupt. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param CAN_Int: specify if the CAN interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CAN_INT_IE : Module interrupt enable. + * @arg CAN_INT_SIE : Status change interrupt enable. + * @arg CAN_INT_EIE : Error interrupt enable. + * @arg CAN_INT_ALL : All CAN interrupt + * @param NewState: this parameter can be ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CAN_IntConfig(HT_CAN_TypeDef *CANx, u32 CAN_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + CAN_Int = CAN_Int & CAN_INT_ALL; + + _CAN_EnterInitMode(CANx); + if (NewState != DISABLE) + { + CANx->CR |= CAN_Int; + } + else + { + CANx->CR = CANx->CR & ~(CAN_Int); + } + _CAN_LeaveInitMode(CANx); +} + +/**********************************************************************************************************//** + * @brief Get the specified CAN INT status. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param CAN_Int: the CAN interrupt source. + * This parameter can be one of the following values: + * @arg CAN_INT_IE : Module interrupt enable. + * @arg CAN_INT_SIE : Status change interrupt enable. + * @arg CAN_INT_EIE : Error interrupt enable. + * @retval SET or RESET + ***********************************************************************************************************/ +FlagStatus CAN_GetIntStatus(HT_CAN_TypeDef* CANx, u32 CAN_Int) +{ + FlagStatus Status; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + if ((CANx->CR & CAN_Int) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + return Status; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CAN flag has been set. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param CAN_Flag: specify the flag to be check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_BOFF : Busoff Status + * @arg CAN_FLAG_EWARN : Warning Status + * @arg CAN_FLAG_EPASS : Error Passive + * @arg CAN_FLAG_RXOK : Received a Message Successfully + * @arg CAN_FLAG_TXOK : Transmitted a Message Successfully + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CAN_GetFlagStatus(HT_CAN_TypeDef* CANx, uint32_t CAN_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if (CANx->SR & CAN_Flag) + { + return SET; + } + else + { + return RESET; } } -/*********************************************************************************************************//** - * @brief Get current bit rate - * @param CANx: The pointer to CAN module base address. - * @retval Current Bit-Rate (kilo bit per second) +/**********************************************************************************************************//** + * @brief Clear the interrupt flag of the specified CAN. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param CAN_Flag: specify the flag that is to be cleared. + * @arg CAN_FLAG_RXOK : Received a Message Successfully + * @arg CAN_FLAG_TXOK : Transmitted a Message Successfully + * @retval None ***********************************************************************************************************/ -u32 CAN_GetCANBitRate(HT_CAN_TypeDef *CANx) +void CAN_ClearFlag(HT_CAN_TypeDef* CANx, uint32_t CAN_Flag) { - u32 wTseg1, wTseg2; - u32 wBpr; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); - wTseg1 = (CANx->BTR & CAN_BTR_TSEG0_Msk) >> CAN_BTR_TSEG0_Pos; - wTseg2 = (CANx->BTR & CAN_BTR_TSEG1_Msk) >> CAN_BTR_TSEG1_Pos; - wBpr = CANx->BTR & CAN_BTR_BRP_Msk; - wBpr |= CANx->BRPER << 6; + CANx->SR &= ~CAN_Flag; +} - return (SystemCoreClock / (wBpr + 1) / (wTseg1 + wTseg2 + 3)); +/**********************************************************************************************************//** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval This function will return the CAN_ErrorCode following values: + * - NO_ERROR : No Error + * - STUFF_ERROR : Stuff Error + * - FORM_ERROR : Form Error + * - ACK_ERROR : Acknowledgment Error + * - BIT1_EROR : Bit Recessive Error + * - BIT0_ERROR : Bit Dominant Error + * - CRC_ERROR : CRC Error + * - NO_CHANGE : Software Set Error + ***********************************************************************************************************/ +CAN_LastErrorCode_TypeDef CAN_GetLastErrorCode(HT_CAN_TypeDef* CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + return (CAN_LastErrorCode_TypeDef)(CANx->SR & CAN_LEC_Msk); +} + +/**********************************************************************************************************//** + * @brief Returns the CANx Receive Error Counter (REC). + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval CAN Receive Error Counter. + ***********************************************************************************************************/ +u32 CAN_GetReceiveErrorCounter(HT_CAN_TypeDef* CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + return ((CANx->ECR & CAN_ECR_REC_MsK) >> CAN_ECR_REC_Pos); +} + +/*********************************************************************************************************//** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + ***********************************************************************************************************/ +u32 CAN_GetLSBTransmitErrorCounter(HT_CAN_TypeDef* CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + return (CANx->ECR & CAN_ECR_TEC_MsK); +} + +/*********************************************************************************************************//** + * @brief Monitor CAN BusOff status. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval None + ***********************************************************************************************************/ +void CAN_BusOffRecovery(HT_CAN_TypeDef *CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + /* Get BusOff Flag */ + if (CANx->SR & CAN_FLAG_BOFF) + { + _CAN_LeaveInitMode(CANx); + } + return; } /**********************************************************************************************************//** * @brief Switch the CAN into test mode. - * @param CANx: The pointer to CAN module base address. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. * @param u8TestMask Specifies the configuration in test modes - * @arg CAN_TEST_BASIC_Msk : Enable basic mode of test mode - * @arg CAN_TEST_SILENT_Msk : Enable silent mode of test mode - * @arg CAN_TEST_LBACK_Msk : Enable Loop Back Mode of test mode - * @arg CAN_TEST_TX0_Msk/CAN_TEST_TX1_Msk: Control CAN_TX pin bit field + * @arg CAN_MODE_BASIC : Enable basic mode of test mode + * @arg CAN_MODE_SILENT : Enable silent mode of test mode + * @arg CAN_MODE_LBACK : Enable Loop Back Mode of test mode + * @arg CAN_MODE_MONITORER : Sample Point can be monitored at CAN_TX pin. + * @arg CAN_MODE_TX_DOMINANT : CAN_TX pin drives a dominant ('0') value + * @arg CAN_MODE_TX_RECESSIVE : CAN_TX pin drives a recessive ('1') value * @retval None ***********************************************************************************************************/ void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask) { - CANx->CR |= CAN_CR_TEST_Msk; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + CANx->CR |= CAN_CR_TEST; CANx->TR = u8TestMask; } /*********************************************************************************************************//** * @brief Leave the test mode - * @param CANx: The pointer to CAN module base address. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. * @retval None ***********************************************************************************************************/ void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx) { - CANx->CR |= CAN_CR_TEST_Msk; - CANx->TR &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); - CANx->CR &= (~CAN_CR_TEST_Msk); -} + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); -/*********************************************************************************************************//** - * @brief Get the waiting status of a received message. - * @param CANx: The pointer to CAN module base address. - * @param MsgObj: Specifies the Message object number, from 0 to 31. 0 No message object has new data. - ***********************************************************************************************************/ -u32 CAN_IsNewDataReceived(HT_CAN_TypeDef *CANx, u32 MsgObj) -{ - MsgObj--; - return (MsgObj < 16 ? CANx->NDR0 & (1 << MsgObj) : CANx->NDR1 & (1 << (MsgObj - 16))); + CANx->CR |= CAN_CR_TEST; + CANx->TR &= ~(CAN_MODE_LBACK | CAN_MODE_SILENT | CAN_MODE_BASIC | CAN_MODE_TX_RECESSIVE); + CANx->CR &= (~CAN_CR_TEST); } /*********************************************************************************************************//** * @brief The function is used to Send CAN message in BASIC mode of test mode. Before call the API, * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter * basic mode of test mode. Please notice IF0 Registers used as Tx Buffer in basic mode. - * @param CANx: The pointer to CAN module base address. - * @param pCanMsg: Pointer to the message structure containing data to transmit. - * @retval TRUE: Transmission OK, FALSE: Check busy flag of interface 0 is timeout + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the data buffer to be transmitted. + * @param len: Length of the data to be transmitted. + * @retval SUCCESS or ERROR ***********************************************************************************************************/ -s32 CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg) +ErrStatus CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len) { - u32 i = 0; - while(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk); - - CANx->SR &= (~CAN_SR_TXOK_Msk); - - if(pCanMsg->IdType == CAN_STD_ID) + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + if (CANx->SR & CAN_FLAG_BOFF) { - /* standard ID*/ + return ERROR; + } + while (CANx->IF0.CREQ & CAN_FLAG_IF_BUSY) + { + } + + CANx->SR &= (~CAN_FLAG_TXOK); + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID */ CANx->IF0.ARB0 = 0; - CANx->IF0.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) ; + CANx->IF0.ARB1 = (((pCanMsg->Id) & CAN_STD_FRAME_Msk) << 2); } else { - /* extended ID*/ - CANx->IF0.ARB0 = (pCanMsg->Id) & 0xFFFF; - CANx->IF0.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_XTD_Msk; + /* extended ID */ + CANx->IF0.ARB0 = (pCanMsg->Id) & CAN_EXT_FRAME_LSB_Msk; + CANx->IF0.ARB1 = (((pCanMsg->Id) >> 16) & CAN_EXT_FRAME_MSB_Msk) | CAN_IF_ARB1_XTD; } - if(pCanMsg->FrameType) - CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR_Msk; + if (pCanMsg->FrameType) + CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR; else - CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR); - CANx->IF0.MCR = (CANx->IF0.MCR & (~CAN_IF_MCR_DLC_Msk)) | pCanMsg->DLC; - CANx->IF0.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; - CANx->IF0.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; - CANx->IF0.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; - CANx->IF0.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + CANx->IF0.MCR = (CANx->IF0.MCR & (~CAN_IF_MCR_DLC_Msk)) | len; + CANx->IF0.DA0R = ((u16)data[1] << 8) | data[0]; + CANx->IF0.DA1R = ((u16)data[3] << 8) | data[2]; + CANx->IF0.DB0R = ((u16)data[5] << 8) | data[4]; + CANx->IF0.DB1R = ((u16)data[7] << 8) | data[6]; - /* request transmission*/ - CANx->IF0.CREQ &= (~CAN_IF_CREQ_BUSY_Msk); - if(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) + /* request transmission */ + CANx->IF0.CREQ &= (~CAN_FLAG_IF_BUSY); + if (CANx->IF0.CREQ & CAN_FLAG_IF_BUSY) { - return FALSE; + return ERROR; } - CANx->IF0.CREQ |= CAN_IF_CREQ_BUSY_Msk; /* Sending */ + CANx->IF0.CREQ |= CAN_FLAG_IF_BUSY; /* Sending */ - for(i = 0; i < 0xFFFFF; i++) - { - if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) - break; - } - - if(i >= 0xFFFFFFF) - { - return FALSE; - } - return TRUE; + return SUCCESS; } /*********************************************************************************************************//** * @brief Get a message information in BASIC mode. - * @param CANx: The pointer to CAN module base address. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @retval FALSE: No any message received, TRUE: Receive a message success. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the buffer where received data will be stored. + * @param len: Pointer to a variable that will store the length of the received data. + * @retval SUCCESS or ERROR ***********************************************************************************************************/ -s32 CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg) +ErrStatus CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8* len) { - if((CANx->IF1.MCR & CAN_IF_MCR_NEWDAT_Msk) == 0) /* In basic mode, receive data always save in IF1 */ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if ((CANx->IF1.MCR & CAN_IF_MCR_NEWDAT) == 0) /* In basic mode, receive data always save in IF1 */ { - return FALSE; + return ERROR; } - CANx->SR &= (~CAN_SR_RXOK_Msk); + CANx->SR &= (~CAN_FLAG_RXOK); - CANx->IF1.CMASK = CAN_IF_CMASK_ARB_Msk - | CAN_IF_CMASK_CONTROL_Msk - | CAN_IF_CMASK_DATAA_Msk - | CAN_IF_CMASK_DATAB_Msk; + CANx->IF1.CMASK = CAN_IF_CMASK_ARB + | CAN_IF_CMASK_CONTROL + | CAN_IF_CMASK_DATAA + | CAN_IF_CMASK_DATAB; - if((CANx->IF1.MASK1 & CAN_IF_ARB1_XTD_Msk) == 0) + if ((CANx->IF1.MASK1 & CAN_IF_ARB1_XTD) == 0) { - /* standard ID*/ + /* standard ID */ pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CANx->IF1.MASK1 >> 2) & 0x07FF; + pCanMsg->Id = (CANx->IF1.MASK1 >> 2) & CAN_STD_FRAME_Msk; } else { - /* extended ID*/ + /* extended ID */ pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = (CANx->IF1.ARB1 & 0x1FFF) << 16; - pCanMsg->Id |= (u32)CANx->IF1.ARB0; + pCanMsg->Id = (CANx->IF1.ARB1 & CAN_EXT_FRAME_MSB_Msk) << 16; + pCanMsg->Id |= (u32)CANx->IF1.ARB0; } - pCanMsg->FrameType = !((CANx->IF1.ARB1 & CAN_IF_ARB1_DIR_Msk) >> CAN_IF_ARB1_DIR_Pos); - - pCanMsg->DLC = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; - pCanMsg->Data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; - pCanMsg->Data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; - pCanMsg->Data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; - pCanMsg->Data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; - pCanMsg->Data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; - pCanMsg->Data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; - pCanMsg->Data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; - pCanMsg->Data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; - - return TRUE; -} - -/*********************************************************************************************************//** - * @brief Set Rx message object - * @param CANx: The pointer to CAN module base address. - * @param MsgObj: Specifies the Message object number, from 0 to 31. - * @arg CAN_STD_ID (standard ID, 11-bit) - * @arg CAN_EXT_ID (extended ID, 29-bit) - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @retval TRUE: SUCCESS, FALSE: No useful interface. - ***********************************************************************************************************/ -s32 CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* pCanMsg) -{ - u32 u8MsgIfNum = 0; - - if((u8MsgIfNum = GetFreeIF(CANx)) == 2) /* Check Free Interface for configure */ - { - return FALSE; - } - - if (u8MsgIfNum == 1) - { - /* Command Setting */ - CANx->IF1.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | - CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; - - if(pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ - { - CANx->IF1.ARB0 = 0; - CANx->IF1.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | (pCanMsg->Id & 0x7FF) << 2; - CANx->IF1.MASK0 = pCanMsg->MASK0; - CANx->IF1.MASK1 = pCanMsg->MASK1; - } - else - { - CANx->IF1.ARB0 = pCanMsg->Id & 0xFFFF; - CANx->IF1.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | CAN_IF_ARB1_XTD_Msk | (pCanMsg->Id & 0x1FFF0000) >> 16; - } - - CANx->IF1.MCR |= CAN_IF_MCR_RXIE_Msk | pCanMsg->MCR ; - - if(pCanMsg->UMASK) - { - CANx->IF1.MCR |= CAN_IF_MCR_UMASK_Msk; - CANx->IF1.MASK0 = pCanMsg->MASK0; - CANx->IF1.MASK1 = pCanMsg->MASK1; - } - - if(pCanMsg->RMTEN) - CANx->IF1.MCR |= CAN_IF_MCR_RMTEN_Msk; - else - CANx->IF1.MCR &= (~CAN_IF_MCR_RMTEN_Msk); - - if(pCanMsg->EOB) - CANx->IF1.MCR |= CAN_IF_MCR_EOB_Msk; - else - CANx->IF1.MCR &= (~CAN_IF_MCR_EOB_Msk); - - CANx->IF1.MCR &= (~CAN_IF_MCR_INTPND_Msk); - CANx->IF1.MCR &= (~CAN_IF_MCR_NEWDAT_Msk); - CANx->IF1.DA0R = 0; - CANx->IF1.DA1R = 0; - CANx->IF1.DB0R = 0; - CANx->IF1.DB1R = 0; - CANx->IF1.CREQ = MsgObj+1; - } - else - { - /* Command Setting */ - CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | - CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; - - if(pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ - { - CANx->IF0.ARB0 = 0; - CANx->IF0.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | (pCanMsg->Id & 0x7FF) << 2; - CANx->IF0.MASK0 = pCanMsg->MASK0; - CANx->IF0.MASK1 = pCanMsg->MASK1; - } - else - { - CANx->IF0.ARB0 = pCanMsg->Id & 0xFFFF; - CANx->IF0.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | CAN_IF_ARB1_XTD_Msk | (pCanMsg->Id & 0x1FFF0000) >> 16; - } - - CANx->IF0.MCR |= CAN_IF_MCR_RXIE_Msk | pCanMsg->MCR ; - - if(pCanMsg->UMASK) - { - CANx->IF0.MCR |= CAN_IF_MCR_UMASK_Msk; - CANx->IF0.MASK0 = pCanMsg->MASK0; - CANx->IF0.MASK1 = pCanMsg->MASK1; - } - - if(pCanMsg->RMTEN) - CANx->IF0.MCR |= CAN_IF_MCR_RMTEN_Msk; - else - CANx->IF0.MCR &= (~CAN_IF_MCR_RMTEN_Msk); - - if(pCanMsg->EOB) - CANx->IF0.MCR |= CAN_IF_MCR_EOB_Msk; - else - CANx->IF0.MCR &= (~CAN_IF_MCR_EOB_Msk); - - CANx->IF0.MCR &= (~CAN_IF_MCR_INTPND_Msk); - CANx->IF0.MCR &= (~CAN_IF_MCR_NEWDAT_Msk); - CANx->IF0.DA0R = 0; - CANx->IF0.DA1R = 0; - CANx->IF0.DB0R = 0; - CANx->IF0.DB1R = 0; - CANx->IF0.CREQ = MsgObj+1; - } - return TRUE; -} - -/*********************************************************************************************************//** - * @brief Gets the message - * @param CANx: The pointer to CAN module base address. - * @param MsgObj: Specifies the Message object number, from 0 to 31. - * @param Release: Specifies the message release indicator. - * @arg TRUE : the message object is released when getting the data. - * @arg FALSE: the message object is not released. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @retval TRUE Success, FALSE No any message received - ***********************************************************************************************************/ -s32 CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, u32 Release, STR_CANMSG_T_TypeDef* pCanMsg) -{ - u32 u8MsgIfNum = 0; - - if(!CAN_IsNewDataReceived(CANx, MsgObj)) - { - return FALSE; - } - - if((u8MsgIfNum = GetFreeIF(CANx)) == 2) /* Check Free Interface for configure */ - { - return FALSE; - } - - CANx->SR &= (~CAN_SR_RXOK_Msk); - - if (u8MsgIfNum == 1) - { - /* read the message contents*/ - CANx->IF1.CMASK = CAN_IF_CMASK_MASK_Msk - | CAN_IF_CMASK_ARB_Msk - | CAN_IF_CMASK_CONTROL_Msk - | CAN_IF_CMASK_CLRINTPND_Msk - | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0) - | CAN_IF_CMASK_DATAA_Msk - | CAN_IF_CMASK_DATAB_Msk; - - CANx->IF1.CREQ = MsgObj; - - while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) - { - /*Wait*/ - } - - if((CANx->IF1.ARB1 & CAN_IF_ARB1_XTD_Msk) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CANx->IF1.ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = (CANx->IF1.ARB1 & 0x1FFF) << 16 ; - pCanMsg->Id |= CANx->IF1.ARB0; - } - pCanMsg->MCR = CANx->IF1.MCR; - pCanMsg->DLC = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; - pCanMsg->EOB = CANx->IF1.MCR & CAN_IF_MCR_EOB_Msk; - pCanMsg->Data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; - pCanMsg->Data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; - pCanMsg->Data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; - pCanMsg->Data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; - pCanMsg->Data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; - pCanMsg->Data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; - pCanMsg->Data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; - pCanMsg->Data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; - } - else - { - /* read the message contents*/ - CANx->IF0.CMASK = CAN_IF_CMASK_MASK_Msk - | CAN_IF_CMASK_ARB_Msk - | CAN_IF_CMASK_CONTROL_Msk - | CAN_IF_CMASK_CLRINTPND_Msk - | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0) - | CAN_IF_CMASK_DATAA_Msk - | CAN_IF_CMASK_DATAB_Msk; - - CANx->IF0.CREQ = MsgObj; - - while(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) - { - /*Wait*/ - } - - if((CANx->IF0.ARB1 & CAN_IF_ARB1_XTD_Msk) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CANx->IF0.ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = (CANx->IF0.ARB1 & 0x1FFF) << 16; - pCanMsg->Id |= CANx->IF0.ARB0; - } - - pCanMsg->MCR = CANx->IF0.MCR; - pCanMsg->DLC = CANx->IF0.MCR & CAN_IF_MCR_DLC_Msk; - pCanMsg->EOB = CANx->IF0.MCR & CAN_IF_MCR_EOB_Msk; - pCanMsg->Data[0] = CANx->IF0.DA0R & CAN_IF_DAT_A0_DATA0_Msk; - pCanMsg->Data[1] = (CANx->IF0.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; - pCanMsg->Data[2] = CANx->IF0.DA1R & CAN_IF_DAT_A1_DATA2_Msk; - pCanMsg->Data[3] = (CANx->IF0.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; - pCanMsg->Data[4] = CANx->IF0.DB0R & CAN_IF_DAT_B0_DATA4_Msk; - pCanMsg->Data[5] = (CANx->IF0.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; - pCanMsg->Data[6] = CANx->IF0.DB1R & CAN_IF_DAT_B1_DATA6_Msk; - pCanMsg->Data[7] = (CANx->IF0.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; - } - return TRUE; -} - -/*********************************************************************************************************//** - * @brief Set bus baud-rate. - * @param CANx: The pointer to CAN module base address. - * @param wBaudRate: The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. - * @retval CurrentBitRate: Real baud-rate value. - ***********************************************************************************************************/ -u32 CAN_SetBaudRate(HT_CAN_TypeDef *CANx, u32 wBaudRate) -{ - u32 wTseg0, wTseg1; - u32 wBrp; - u32 wValue; - - CAN_EnterInitMode(CANx); - - SystemCoreClockUpdate(); - - wTseg0 = 2; - wTseg1 = 1; - - wValue = SystemCoreClock / wBaudRate; - - while(1) - { - if(((wValue % (wTseg0 + wTseg1 + 3)) == 0)) - break; - if(wTseg1 < 7) - wTseg1++; - - if((wValue % (wTseg0 + wTseg1 + 3)) == 0) - break; - if(wTseg0 < 15) - wTseg0++; - else - { - wTseg0 = 2; - wTseg1 = 1; - break; - } - } - - wBrp = SystemCoreClock / (wBaudRate) / (wTseg0 + wTseg1 + 3) - 1; - - wValue = ((u32)wTseg1 << CAN_BTR_TSEG1_Pos) | ((u32)wTseg0 << CAN_BTR_TSEG0_Pos) | - (wBrp & CAN_BTR_BRP_Msk) | (CANx->BTR & CAN_BTR_SJW_Msk); - CANx->BTR = wValue; - CANx->BRPER = (wBrp >> 6) & 0x0F; - - CAN_LeaveInitMode(CANx); - - return (CAN_GetCANBitRate(CANx)); -} - -/*********************************************************************************************************//** - * @brief The function is used to disable all CAN interrupt. - * @param CANx: The pointer to CAN module base address. - * @retval None - ***********************************************************************************************************/ -void CAN_Close(HT_CAN_TypeDef *CANx) -{ - CAN_DisableInt(CANx, (CAN_CR_IE_Msk | CAN_CR_SIE_Msk | CAN_CR_EIE_Msk)); -} - -/*********************************************************************************************************//** - * @brief Set CAN operation mode and target baud-rate. - * @param CANx: The pointer to CAN module base address. - * @param wBaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. - * @param wMode The CAN operation mode. - * @arg CAN_NORMAL_MODE : Normal operation. - * @arg CAN_BASIC_MODE : Basic operation. - * @arg CAN_SILENT_MODE : Silent operation. - * @arg CAN_LBACK_MODE : Loop Back operation. - * @arg CAN_LBS_MODE : Loop Back combined with Silent operation. - * @retval u32CurrentBitRate Real baud-rate value. - ***********************************************************************************************************/ -u32 CAN_Open(HT_CAN_TypeDef *CANx, u32 wBaudRate, u32 wMode) -{ - u32 CurrentBitRate; - - CurrentBitRate = CAN_SetBaudRate(CANx, wBaudRate); - - if(wMode) - CAN_EnterTestMode(CANx, wMode); - - return CurrentBitRate; -} - -/*********************************************************************************************************//** - * @brief The function is used to configure a transmit object. - * @param CANx: The pointer to CAN module base address. - * @param MsgNum: Specifies the Message object number, from 0 to 31. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @retval FALSE No useful interface, TRUE Config message object success. - ***********************************************************************************************************/ -s32 CAN_SetTxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) -{ - u32 MsgIfNum = 0; - u32 i = 0; - - while((MsgIfNum = GetFreeIF(CANx)) == 2) - { - i++; - if(i > 0x10000000) - return FALSE; - } - - /* update the contents needed for transmission*/ - if(MsgIfNum ==0) - { - CANx->IF0.CMASK = 0xF3; /* CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk - | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */ - - if(pCanMsg->IdType == CAN_STD_ID) - { - /* standard ID*/ - CANx->IF0.ARB0 = 0; - CANx->IF0.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_DIR_Msk | CAN_IF_ARB1_MSGVAL_Msk; - } - else - { - /* extended ID*/ - CANx->IF0.ARB0 = (pCanMsg->Id) & 0xFFFF; - CANx->IF0.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk - | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; - } - - if(pCanMsg->FrameType) - CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR_Msk; - else - CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); - - CANx->IF0.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; - CANx->IF0.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; - CANx->IF0.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; - CANx->IF0.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; - CANx->IF0.MCR = 0; - if(pCanMsg->RMTEN) - CANx->IF0.MCR |= CAN_IF_MCR_RMTEN_Msk; - else - CANx->IF0.MCR &= (~CAN_IF_MCR_RMTEN_Msk); - if(pCanMsg->EOB) - CANx->IF0.MCR |= CAN_IF_MCR_EOB_Msk; - else - CANx->IF0.MCR &= (~CAN_IF_MCR_EOB_Msk); - - CANx->IF0.MCR |= CAN_IF_MCR_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCR_TXIE_Msk ; - CANx->IF0.CREQ = MsgNum +1; - } - else - { - CANx->IF1.CMASK = 0xF3; /* CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk - | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */ - - if(pCanMsg->IdType == CAN_STD_ID) - { - /* standard ID*/ - CANx->IF1.ARB0 = 0; - CANx->IF1.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_DIR_Msk | CAN_IF_ARB1_MSGVAL_Msk; - } - else - { - /* extended ID*/ - CANx->IF1.ARB0 = (pCanMsg->Id) & 0xFFFF; - CANx->IF1.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk - | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; - } - - if(pCanMsg->FrameType) - CANx->IF1.ARB1 |= CAN_IF_ARB1_DIR_Msk; - else - CANx->IF1.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); - - CANx->IF1.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; - CANx->IF1.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; - CANx->IF1.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; - CANx->IF1.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; - - CANx->IF1.MCR = 0; - - if(pCanMsg->RMTEN) - CANx->IF1.MCR |= CAN_IF_MCR_RMTEN_Msk; - else - CANx->IF1.MCR &= (~CAN_IF_MCR_RMTEN_Msk); - - if(pCanMsg->EOB) - CANx->IF1.MCR |= CAN_IF_MCR_EOB_Msk; - else - CANx->IF1.MCR &= (~CAN_IF_MCR_EOB_Msk); - - CANx->IF1.MCR |= CAN_IF_MCR_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCR_TXIE_Msk ; - CANx->IF1.CREQ = MsgNum +1; - } - return TRUE; -} - -/*********************************************************************************************************//** - * @brief Set transmit request bit. - * If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst - * (IFn_MCON[8]) will be ignored. - * @param CANx: The pointer to CAN module base address. - * @param u32MsgNum: Specifies the Message object number, from 0 to 31. - * @retval TRUE: Start transmit message. - ***********************************************************************************************************/ -s32 CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum) -{ - CANx->SR &= (~CAN_SR_TXOK_Msk); - - /* read the message contents*/ - CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk - | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; - - CANx->IF1.CREQ = u32MsgNum+1; - - while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) - { - /*Wait*/ - } - CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; - CANx->IF0.CREQ = u32MsgNum+1; - - return TRUE; -} - -/*********************************************************************************************************//** - * @brief Enable CAN interrupt. - * The application software has two possibilities to follow the source of a message interrupt. - * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. - * @param CANx: The pointer to CAN module base address. - * @param u32Mask: Interrupt Mask. - * @arg CAN_CR_IE_Msk : Module interrupt enable. - * @arg CAN_CR_SIE_Msk: Status change interrupt enable. - * @arg CAN_CR_EIE_Msk: Error interrupt enable. - * @retval None - ***********************************************************************************************************/ -void CAN_EnableInt(HT_CAN_TypeDef *CANx, u32 u32Mask) -{ - CAN_EnterInitMode(CANx); - - CANx->CR = (CANx->CR & 0xF1) | ((u32Mask & CAN_CR_IE_Msk) ? CAN_CR_IE_Msk : 0) - | ((u32Mask & CAN_CR_SIE_Msk) ? CAN_CR_SIE_Msk : 0) - | ((u32Mask & CAN_CR_EIE_Msk) ? CAN_CR_EIE_Msk : 0); - - - CAN_LeaveInitMode(CANx); -} - -/*********************************************************************************************************//** - * @brief Disable CAN interrupt. - * @param CANx: The pointer to CAN module base address. - * @param Mask: Interrupt Mask. (CAN_CR_IE_Msk / CAN_CR_SIE_Msk / CAN_CR_EIE_Msk). - * @retval None - ***********************************************************************************************************/ -void CAN_DisableInt(HT_CAN_TypeDef *CANx, u32 Mask) -{ - CAN_EnterInitMode(CANx); - - CANx->CR = CANx->CR & ~(CAN_CR_IE_Msk | ((Mask & CAN_CR_SIE_Msk) ? CAN_CR_SIE_Msk : 0) - | ((Mask & CAN_CR_EIE_Msk) ? CAN_CR_EIE_Msk : 0)); - - CAN_LeaveInitMode(CANx); -} - - -/*********************************************************************************************************//** - * @brief The function is used to configure a receive message object. - * @param CANx: The pointer to CAN module base address. - * @param MsgNum: Specifies the Message object number, from 0 to 31. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @arg CAN_STD_ID: The 11-bit identifier. - * @arg CAN_EXT_ID: The 29-bit identifier. - * @retval FALSE No useful interface, TRUE Configure a receive message object success. - ***********************************************************************************************************/ -s32 CAN_SetRxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_R_TypeDef* pCanMsg) -{ - u32 TimeOutCount = 0; - - while(CAN_SetRxMsgObj(CANx, MsgNum, pCanMsg) == FALSE) - { - TimeOutCount++; - - if(TimeOutCount >= 0x10000000) return FALSE; - } - - return TRUE; -} - -/*********************************************************************************************************//** - * @brief The function is used to configure several receive message objects. - * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message - * reception and transmission by buffering the data to be transferred. - * @param CANx: The pointer to CAN module base address. - * @param MsgNum: The starting MSG RAM number(0 ~ 31). - * @param MsgCount: the number of MSG RAM of the FIFO. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @arg CAN_STD_ID: The 11-bit identifier. - * @arg CAN_EXT_ID: The 29-bit identifier. - * @retval FALSE No useful interface, TRUE Configure receive message objects success. - ***********************************************************************************************************/ -s32 CAN_SetMultiRxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , u32 MsgCount, STR_CANMSG_R_TypeDef* pCanMsg) -{ - u32 i = 0; - u32 TimeOutCount; - - for(i = 1; i < MsgCount+1; i++) - { - TimeOutCount = 0; - pCanMsg->EOB = 0; - - if(i == MsgCount) - pCanMsg->EOB=1; - - while(CAN_SetRxMsgObj(CANx, MsgNum, pCanMsg) == FALSE) - { - TimeOutCount++; - - if(TimeOutCount >= 0x10000000) - return FALSE; - } - MsgNum ++; - } - - return TRUE; + *len = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; + data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + + return SUCCESS; } /*********************************************************************************************************//** * @brief Send CAN message. - * @param CANx: The pointer to CAN module base address. - * @param MsgNum: Specifies the Message object number, from 0 to 31. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @retval FALSE: 1. When operation in basic mode: Transmit message time out. - * 2. When operation in normal mode: No useful interface. - * TRUE: Transmit Message success. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the data buffer to be transmitted. + * @param len: Length of the data to be transmitted. + * @retval SUCCESS or ERROR ***********************************************************************************************************/ -s32 CAN_Transmit(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +ErrStatus CAN_Transmit(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len) { - if((CANx->CR & CAN_CR_TEST_Msk) && (CANx->TR & CAN_TEST_BASIC_Msk)) + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + if (_CAN_SetTxMsg(CANx, pCanMsg, data, len) == ERROR) { - return (CAN_BasicSendMsg(CANx, pCanMsg)); + return ERROR; } - else - { - if(CAN_SetTxMsg(CANx, MsgNum, pCanMsg) == FALSE) - return FALSE; - - CANx->SR &= (~CAN_SR_TXOK_Msk); - - /* read the message contents*/ - CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk - | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; - - CANx->IF1.CREQ = MsgNum+1; - - while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) - { - /*Wait*/ - } - CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; - CANx->IF0.CREQ = MsgNum+1; - } - - return TRUE; + return (CAN_TriggerTxMsg(CANx, pCanMsg)); } /*********************************************************************************************************//** * @brief Gets the message, if received. * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message * reception and transmission by buffering the data to be transferred. - * @param CANx: The pointer to CAN module base address. - * @param MsgNum: Specifies the Message object number, from 0 to 31. - * @param pCanMsg: Pointer to the message structure where received data is copied. - * @retval FALSE: No any message received, TRUE: Receive Message success. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the buffer where received data will be stored. + * @param len: Pointer to a variable that will store the length of the received data. + * @retval RxStatus_TypeDef: Returns the status of the message reception. Possible values are: + * - MSG_OBJ_NOT_SET + * - MSG_NOT_RECEIVED + * - MSG_OVER_RUN ***********************************************************************************************************/ -s32 CAN_Receive(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +CAN_RxStatus_TypeDef CAN_Receive(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u32* len) { - if((CANx->CR & CAN_CR_TEST_Msk) && (CANx->TR & CAN_TEST_BASIC_Msk)) + u32 _MsgNum = pCanMsg->MsgNum; + CAN_RxStatus_TypeDef status = MSG_OBJ_NOT_SET; + bool firstMsg = TRUE; + *len = 0; + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) != FALSE) { - return (CAN_BasicReceiveMsg(CANx, pCanMsg)); + while (1) + { + s32 ReadMsgStatus; + if (_CAN_GetNewData(CANx, _MsgNum) == FALSE) + { + if (firstMsg == TRUE) + status = MSG_NOT_RECEIVED; + else + status = MSG_RX_FINISH; + break; + } + firstMsg = FALSE; + ReadMsgStatus = _CAN_ReadMsgObj(CANx, _MsgNum, TRUE, pCanMsg, &data[*len], len); + if (ReadMsgStatus != 0) + { + if (ReadMsgStatus == 2) + { + status = MSG_OVER_RUN; + break; + } + status = MSG_RX_FINISH; + break; + } + _MsgNum++; + } + } + return status; +} + +/*********************************************************************************************************//** + * @brief Cancels a transmit request. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval SUCCESS or ERROR + ***********************************************************************************************************/ +ErrStatus CAN_CancelTransmit(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg) +{ + HT_CANIF_TypeDef *IFx = NULL; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) + { + return ERROR; + } + + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + if ((IFx->CREQ & CAN_FLAG_IF_BUSY) == 0) + { + IFx->CMASK = CAN_IF_CMASK_WRRD | CAN_IF_CMASK_CLRINTPND; + IFx->MCR = 0; + IFx->CREQ = pCanMsg->MsgNum; + } + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Discard the specified FIFO. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval SUCCESS or ERROR + ***********************************************************************************************************/ +ErrStatus CAN_DiscardRxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) + { + return ERROR; + } + while (1) + { + HT_CANIF_TypeDef *IFx = NULL; + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + IFx->CMASK = CAN_IF_CMASK_TXRQSTNEWDAT | CAN_IF_CMASK_CONTROL; + IFx->CREQ = pCanMsg->MsgNum; + if (IFx->MCR & CAN_IF_MCR_EOB) + { + break; + } + } + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief The function is used to configure several receive message objects. + * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message + * reception and transmission by buffering the data to be transferred. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param FifoDepth: the number of MSG RAM of the FIFO. + * @retval SUCCESS or ERROR + ***********************************************************************************************************/ +ErrStatus CAN_SetRxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u32 FifoDepth) +{ + s32 i = 0; + u32 _MsgNum; + + u32 eob; + if (pCanMsg->MsgNum == 0) + { + _MsgNum = _CAN_GetValidMsg(CANx); } else { - return CAN_ReadMsgObj(CANx, MsgNum, TRUE, pCanMsg); + _MsgNum = pCanMsg->MsgNum; } + if ((_MsgNum + FifoDepth) > MSG_OBJ_TOTAL_NUM) + { + return ERROR; + } + pCanMsg->MsgNum = _MsgNum; + eob = 0; + for (i = _MsgNum; i < FifoDepth + _MsgNum + 1; i++) + { + if (i == FifoDepth + _MsgNum) + { + eob = 1; + } + _CAN_SetRxMsgObj(CANx, i, pCanMsg, eob); + } + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Get the waiting status of a received message. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval TRUE: The corresponding message object has a new data bit is set, FALSE otherwise. + ***********************************************************************************************************/ +bool CAN_NewDataReceived(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg) +{ + + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) + { + return FALSE; + } + return _CAN_GetNewData(CANx, pCanMsg->MsgNum); +} + +/*********************************************************************************************************//** + * @brief Get the interrupt pending status of a message object. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval TRUE: The corresponding message object has a interrupt pending bit is set, FALSE otherwise. + ***********************************************************************************************************/ +bool CAN_GetMsgPending(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg) +{ + u32 Pending = CANx->IPR0; + Pending |= CANx->IPR1 << 16; + + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) + { + return FALSE; + } + + if ((Pending & 1 << (pCanMsg->MsgNum - 1)) == 0) + { + return FALSE; + } + return TRUE; } /*********************************************************************************************************//** * @brief Clear interrupt pending bit. - * @param CANx: The pointer to CAN module base address. - * @param MsgNum: Specifies the Message object number, from 0 to 31. - * @retval None + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval SUCCESS or ERROR ***********************************************************************************************************/ -void CAN_CLR_INT_PENDING_BIT(HT_CAN_TypeDef *CANx, u32 MsgNum) +ErrStatus CAN_ClearMsgPendingFlag(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg) { - u32 u32IFBusyCount = 0; - - while(u32IFBusyCount < 0x10000000) + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) { - if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) - { - CANx->IF0.CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; - CANx->IF0.CREQ = MsgNum+1; - break; - } - else if((CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) - { - CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; - CANx->IF1.CREQ = MsgNum+1; - break; - } - - u32IFBusyCount++; + return ERROR; } + _CAN_ClearMsgPendingFlag(CANx, pCanMsg->MsgNum); + + return SUCCESS; } /*********************************************************************************************************//** - * @brief The function is used to configure Mask as the message object. - * @param CANx: The pointer to CAN module base address. - * @param MsgObj: Specifies the Message object number, from 0 to 31. - * @param MaskMsg: Pointer to the message structure where received data is copied. - * @arg CAN_STD_ID: The 11-bit identifier. - * @arg CAN_EXT_ID: The 29-bit identifier. - * @retval FALSE No useful interface, TRUE Configure a receive message object success. + * @brief Checks the transmission of a message object. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval 0: Transmitting, 1: Transmission successful, -1: Transmission failed. ***********************************************************************************************************/ -s32 CAN_MsgObjMaskConfig(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* MaskMsg) +s32 CAN_TransmitStatus(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg) { - if(MaskMsg->IdType == CAN_STD_ID) - { - /* standard ID*/ - CANx->IF0.ARB0 = 0; - CANx->IF0.ARB1 = (((MaskMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_MSGVAL_Msk ; + s32 TxStatus = 0; + u32 u32Reg; + s32 MsgNum = pCanMsg->MsgNum -1; - /* Set the Mask Standard ID(11-bit) for IFn Mask Register is used for acceptance filtering*/ - CANx->IF0.MASK0 = 0; - CANx->IF0.MASK1 = ((MaskMsg->Id & 0x7FF) << 2) ; - } - else + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) { - /* extended ID*/ - CANx->IF0.ARB0 = (MaskMsg->Id) & 0xFFFF; - CANx->IF0.ARB1 = ((MaskMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk - | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; - /* Set the Mask Extended ID(29-bit) for IFn Mask Register is used for acceptance filtering*/ - CANx->IF0.MASK0 = (MaskMsg->Id) & 0xFFFF; - CANx->IF0.MASK1 = ((MaskMsg->Id) & 0x1FFF0000) >> 16 ; + return -1; } - if(MaskMsg->u8Xtd) - CANx->IF0.MASK1 |= CAN_IF_MASK1_MXTD_Msk; /* The extended identifier bit (IDE) is used for acceptance filtering */ - else - CANx->IF0.MASK1 &= (~CAN_IF_MASK1_MXTD_Msk); /* The extended identifier bit (IDE) has no effect on the acceptance filtering */ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); - if(MaskMsg->u8Dir) - CANx->IF0.MASK1 |= CAN_IF_MASK1_MDIR_Msk; /* The message direction bit (Dir) is used for acceptance filtering */ - else - CANx->IF0.MASK1 &= (~CAN_IF_MASK1_MDIR_Msk); /* The message direction bit (Dir) has no effect on the acceptance filtering */ + u32Reg = CANx->TRR0; + u32Reg |= (CANx->TRR1 << 16); + MsgNum = 1 << (MsgNum); + if ((u32Reg & (MsgNum)) == 0) + { + TxStatus = 1; + } - CANx->IF0.MCR |= CAN_IF_MCR_UMASK_Msk; /* Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering */ - - /* Update the contents needed for transmission*/ - CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk /* Transfer data from the selected Message Buffer Registers to the Message Object addressed */ - | CAN_IF_CMASK_MASK_Msk; /* Transfer Identifier Mask + MDir + MXtd to Message Object */ - - CANx->IF0.DA0R = 0; - CANx->IF0.DA1R = 0; - CANx->IF0.DB0R = 0; - CANx->IF0.DB1R = 0; - - /* Set the Message Object in the Message RAM is selected for data transfer */ - CANx->IF0.CREQ = 1 + MsgObj; - - return TRUE; + u32Reg = CANx->NDR0; + u32Reg |= (CANx->NDR1 << 16); + if ((u32Reg & (MsgNum)) > 0) + { + TxStatus = -1; + } + return TxStatus; } -/* Private functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Updates the data of a specified CAN message object. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the data array. + * @param len: Length of the data to be sent, in bytes (maximum 8 bytes). + * @retval SUCCESS or ERROR + ***********************************************************************************************************/ +ErrStatus CAN_UpdateTxMsgData(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len) +{ + HT_CANIF_TypeDef *IFx = NULL; + + len &= CAN_IF_MCR_DLC_Msk; + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) + { + return ERROR; + } + + IFx->CMASK = CAN_IF_CMASK_WRRD | CAN_IF_CMASK_DATAA | CAN_IF_CMASK_DATAB | CAN_IF_CMASK_CONTROL; + + IFx->MCR &= (~CAN_IF_MCR_DLC_Msk); + IFx->MCR |= (len & CAN_IF_MCR_DLC_Msk); + IFx->DA0R = ((u16)(data[1] << 8) | data[0]); + IFx->DA1R = ((u16)(data[3] << 8) | data[2]); + IFx->DB0R = ((u16)(data[5] << 8) | data[4]); + IFx->DB1R = ((u16)(data[7] << 8) | data[6]); + + IFx->CREQ = pCanMsg->MsgNum; + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Set transmit request bit. + * If a transmission is requested by programming bit TxRqst/NewDat, the TxRqst will be ignored. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @retval SUCCESS or ERROR + ***********************************************************************************************************/ +ErrStatus CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg) +{ + HT_CANIF_TypeDef *IFx = NULL; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if (CANx->SR & CAN_FLAG_BOFF) + { + return ERROR; + } + + if (_CAN_CheckMsgIsValid(CANx, pCanMsg->MsgNum) == FALSE) + { + return ERROR; + } + + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + + IFx->CMASK = CAN_IF_CMASK_WRRD | CAN_IF_CMASK_CONTROL; + IFx->MCR |= CAN_IF_MCR_NEWDAT | CAN_IF_MCR_TXRQST; + IFx->CREQ = pCanMsg->MsgNum; + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Clears all pending message flags. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval None + ***********************************************************************************************************/ +void CAN_ClearAllMsgPendingFlag(HT_CAN_TypeDef *CANx) +{ + int i; + u32 Pending = CANx->IPR0; + Pending |= CANx->IPR1 << 16; + for (i = 0 ; i < MSG_OBJ_TOTAL_NUM ; i++) + { + if ((Pending & 1) == 1) + { + _CAN_ClearMsgPendingFlag(CANx, i + 1); + } + + Pending = Pending >> 1; + if (Pending == 0) + { + break; + } + } +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ /** @defgroup CAN_Private_Functions CAN private functions * @{ */ /*********************************************************************************************************//** - * @brief Check if SmartCard slot is presented. - * @param CANx: The pointer to CAN module base address. -* @retval Free IF number. IF0_NUM or IF1_NUM or IF_TOTAL_NUM (No IF is free) + * @brief The function is used to configure a transmit object. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the data buffer to be transmitted. + * @param len: Length of the data to be transmitted. + * @retval SUCCESS or ERROR ***********************************************************************************************************/ -static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx) +ErrStatus _CAN_SetTxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len) { - if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) - return IF0_NUM; - else if((CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) - return IF1_NUM; + HT_CANIF_TypeDef *IFx = NULL; + if (pCanMsg->MsgNum == 0) + { + pCanMsg->MsgNum = _CAN_GetValidMsg(CANx); + } + if (pCanMsg->MsgNum > MSG_OBJ_TOTAL_NUM) + { + return ERROR; + } + + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + + /* update the contents needed for transmission */ + IFx->CMASK = CAN_IF_CMASK_WRRD | CAN_IF_CMASK_MASK | CAN_IF_CMASK_ARB + | CAN_IF_CMASK_CONTROL | CAN_IF_CMASK_DATAA | CAN_IF_CMASK_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID */ + IFx->ARB0 = 0; + IFx->ARB1 = (((pCanMsg->Id) & CAN_STD_FRAME_Msk) << 2) | CAN_IF_ARB1_DIR | CAN_IF_ARB1_MSGVAL; + } else - return IF_TOTAL_NUM; + { + /* extended ID */ + IFx->ARB0 = (pCanMsg->Id) & CAN_EXT_FRAME_LSB_Msk; + IFx->ARB1 = (((pCanMsg->Id) >> 16) & CAN_EXT_FRAME_MSB_Msk) + | CAN_IF_ARB1_DIR | CAN_IF_ARB1_XTD | CAN_IF_ARB1_MSGVAL; + } + + if (pCanMsg->FrameType) + IFx->ARB1 |= CAN_IF_ARB1_DIR; + else + IFx->ARB1 &= (~CAN_IF_ARB1_DIR); + + IFx->DA0R = ((u16)data[1] << 8) | data[0]; + IFx->DA1R = ((u16)data[3] << 8) | data[2]; + IFx->DB0R = ((u16)data[5] << 8) | data[4]; + IFx->DB1R = ((u16)data[7] << 8) | data[6]; + + IFx->MCR = 0; + + IFx->MCR &= (~CAN_IF_MCR_RMTEN); + + IFx->MCR |= CAN_IF_MCR_NEWDAT | len | CAN_IF_MCR_TXIE; + IFx->CREQ = pCanMsg->MsgNum; + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Get the waiting status of a received message. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param MsgNum: Specifies the Message object number, from 1 to 32. + * @retval TRUE: The corresponding message object has a new data bit is set, FALSE otherwise. + ***********************************************************************************************************/ +bool _CAN_GetNewData(HT_CAN_TypeDef *CANx, u32 MsgNum) +{ + u32 NewData = CANx->NDR0; + NewData |= CANx->NDR1 << 16; + + if ((NewData & 1 << (MsgNum - 1)) == 0) + { + return FALSE; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Get free interface. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval Free IF pointer. NULL: No IF is free + ***********************************************************************************************************/ +static HT_CANIF_TypeDef *_GetFreeIF(HT_CAN_TypeDef *CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if ((CANx->IF0.CREQ & CAN_FLAG_IF_BUSY) == 0) + { + return &CANx->IF0; + } + else if ((CANx->IF1.CREQ & CAN_FLAG_IF_BUSY) == 0) + { + return &CANx->IF1; + } + else + { + return NULL; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to set CAN to enter initialization mode and enable access bit timing + * register.After bit timing configuration ready, user must call CAN_LeaveInitMode() to leave + * initialization mode and lock bit timing register to let new configuration take effect. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval None + ***********************************************************************************************************/ +static void _CAN_EnterInitMode(HT_CAN_TypeDef *CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + CANx->CR |= CAN_CR_INIT; + CANx->CR |= CAN_CR_CCE; +} + +/*********************************************************************************************************//** + * @brief Leave initialization mode + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval None + ***********************************************************************************************************/ +static void _CAN_LeaveInitMode(HT_CAN_TypeDef *CANx) +{ + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + CANx->CR &= (~(CAN_CR_INIT | CAN_CR_CCE)); + + while (CANx->CR & CAN_CR_INIT); /* Check INIT bit is released */ +} + +/*********************************************************************************************************//** + * @brief Set Rx message object + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param MsgNum: Specifies the Message object number, from 1 to 32. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param uSingleOrFifoLast: Specifies the end-of-buffer indicator. + * @retval None + ***********************************************************************************************************/ +static void _CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgNum, CAN_MSG_TypeDef* pCanMsg, u32 uSingleOrFifoLast) +{ + HT_CANIF_TypeDef *IFx = NULL; + + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + /* Command Setting */ + IFx->CMASK = CAN_IF_CMASK_WRRD | CAN_IF_CMASK_MASK | CAN_IF_CMASK_ARB | + CAN_IF_CMASK_CONTROL | CAN_IF_CMASK_DATAA | CAN_IF_CMASK_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format, Configure Mask and Arbitration register */ + { + /* Standard Mask.(bit28..bit18). */ + IFx->ARB0 = 0; + IFx->ARB1 = CAN_IF_ARB1_MSGVAL | (pCanMsg->Id & CAN_STD_FRAME_Msk) << 2; + IFx->MASK0 = 0; + IFx->MASK1 = CAN_IF_MASK1_MDIR | (pCanMsg->IdMask & CAN_STD_FRAME_Msk) << 2; + } + else + { + IFx->ARB0 = pCanMsg->Id & CAN_EXT_FRAME_LSB_Msk; + IFx->ARB1 = CAN_IF_ARB1_MSGVAL | CAN_IF_ARB1_XTD | ((pCanMsg->Id >> 16) & CAN_EXT_FRAME_MSB_Msk); + IFx->MASK0 = pCanMsg->IdMask & CAN_EXT_FRAME_LSB_Msk; + IFx->MASK1 = CAN_IF_MASK1_MXTD | CAN_IF_MASK1_MDIR | ((pCanMsg->IdMask>> 16) & CAN_EXT_FRAME_MSB_Msk); + } + + IFx->MCR = CAN_IF_MCR_RXIE | CAN_IF_MCR_UMASK; + + if (pCanMsg->FrameType == CAN_REMOTE_FRAME) + { + + IFx->ARB1 |= CAN_IF_ARB1_DIR; + IFx->MCR |= CAN_IF_MCR_RMTEN; + } + + if (uSingleOrFifoLast) + IFx->MCR |= CAN_IF_MCR_EOB; + + IFx->MCR &= (~CAN_IF_MCR_INTPND); + IFx->MCR &= (~CAN_IF_MCR_NEWDAT); + IFx->CREQ = MsgNum; +} + +/*********************************************************************************************************//** + * @brief Gets the message + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param MsgNum: Specifies the Message object number, from 1 to 32. + * @param Release: Specifies the message release indicator. + * @arg TRUE : the message object is released when getting the data. + * @arg FALSE: the message object is not released. + * @param pCanMsg: Pointer to the message structure for transmitting or receiving data. + * @param data: Pointer to the buffer where received data will be stored. + * @param len: Pointer to a variable that will store the length of the received data. +* @retval 0: Data not empty, 1: Finish, 2: data over run + ***********************************************************************************************************/ +static s32 _CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 MsgNum, u32 Release, CAN_MSG_TypeDef* pCanMsg, u8* data, u32* len) +{ + HT_CANIF_TypeDef *IFx = NULL; + + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + + /* read the message contents */ + IFx->CMASK = CAN_IF_CMASK_MASK + | CAN_IF_CMASK_ARB + | CAN_IF_CMASK_CONTROL + | CAN_IF_CMASK_CLRINTPND + | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT : 0) + | CAN_IF_CMASK_DATAA + | CAN_IF_CMASK_DATAB; + + IFx->CREQ = MsgNum; + + while (IFx->CREQ & CAN_FLAG_IF_BUSY) + { + /*Wait */ + } + + if ((IFx->ARB1 & CAN_IF_ARB1_XTD) == 0) + { + /* standard ID */ + pCanMsg->Id = (IFx->ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; + } + else + { + /* extended ID */ + pCanMsg->Id = (IFx->ARB1 & CAN_EXT_FRAME_MSB_Msk) << 16; + pCanMsg->Id |= IFx->ARB0; + } + if ((IFx->MCR & CAN_IF_MCR_RMTEN) == 0) + { + pCanMsg->FrameType = CAN_DATA_FRAME; + } + else + { + pCanMsg->FrameType = CAN_REMOTE_FRAME; + } + + *len += IFx->MCR & CAN_IF_MCR_DLC_Msk; + data[0] = IFx->DA0R & CAN_IF_DAT_A0_DATA0_Msk; + data[1] = (IFx->DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + data[2] = IFx->DA1R & CAN_IF_DAT_A1_DATA2_Msk; + data[3] = (IFx->DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + data[4] = IFx->DB0R & CAN_IF_DAT_B0_DATA4_Msk; + data[5] = (IFx->DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + data[6] = IFx->DB1R & CAN_IF_DAT_B1_DATA6_Msk; + data[7] = (IFx->DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + if ((IFx->MCR & CAN_IF_MCR_MSGLST) > 0) + { + IFx->CMASK =CAN_IF_CMASK_WRRD | CAN_IF_CMASK_CONTROL; + IFx->MCR &= ~CAN_IF_MCR_MSGLST; + IFx->CREQ = MsgNum; + IFx->CMASK = CAN_IF_CMASK_TXRQSTNEWDAT; + IFx->CREQ = MsgNum; + return 2; + } + if ((IFx->MCR & CAN_IF_MCR_EOB) > 0) + { + return 1; + } + else + { + return 0; + } +} + +/*********************************************************************************************************//** + * @brief Gets the first valid message object number from the CAN message valid registers (MVR0 and MVR1). + * This function scans through the message object table to find the first valid message object that is + * not set (i.e., where the corresponding bit in the message valid register is 0). + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval The index of the first valid message object that is not set. + ***********************************************************************************************************/ +static int _CAN_GetValidMsg(HT_CAN_TypeDef *CANx) +{ + s32 _MsgNum; + u32 msgNumTable = CANx->MVR0; + msgNumTable |= CANx->MVR1 << 16; + for (_MsgNum = 0 ; _MsgNum < MSG_OBJ_TOTAL_NUM ; _MsgNum++) + { + if ((msgNumTable & 1) == 0) + { + break; + } + msgNumTable = msgNumTable >> 1; + } + return _MsgNum + 1; +} + +/*********************************************************************************************************//** + * @brief Checks if the specified message number is valid. + * @param CANx: Pointer to the CAN peripheral. + * @param MsgNum: The message number. + * @retval TRUE if the message number is valid, FALSE otherwise. + ***********************************************************************************************************/ +static bool _CAN_CheckMsgIsValid(HT_CAN_TypeDef *CANx, u32 MsgNum) +{ + if ((MsgNum == 0) || (MsgNum > MSG_OBJ_TOTAL_NUM)) + { + return FALSE; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Clears the pending flag for a specific CAN message object. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @param MsgNum: The message number. + * @retval None. + ***********************************************************************************************************/ +static void _CAN_ClearMsgPendingFlag(HT_CAN_TypeDef *CANx, u32 MsgNum) +{ + HT_CANIF_TypeDef *IFx = NULL; + while (IFx == NULL) + { + IFx = _GetFreeIF(CANx); + } + IFx->CMASK = CAN_IF_CMASK_CLRINTPND; + IFx->CREQ = MsgNum; } /** * @} @@ -1023,7 +1139,3 @@ static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx) /** * @} */ - -/** - * @} - */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c index 9238830a04..8cfac0313b 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_ckcu.c - * @version $Rev:: 7322 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the Clock Control Unit firmware functions. ************************************************************************************************************* * @attention @@ -90,7 +90,7 @@ #define CKCU_MASK_POTD ((u32)0x3 << CKCU_POS_POTD) #define CKCU_POS_PFBD 23 -#define CKCU_MASK_PFBD ((u32)0x0F << CKCU_POS_PFBD) +#define CKCU_MASK_PFBD ((u32)0x1F << CKCU_POS_PFBD) /* PLLCR bit field definition */ #define CKCU_POS_PLLBYPASS 31 @@ -139,8 +139,10 @@ #define CKCU_MASK_CKSWST ((u32)0x7 << CKCU_POS_CKSWST) /* LPCR bit field definition */ +#if (!LIBCFG_CKCU_NO_LPCR) #define CKCU_POS_BKISO 0 #define CKCU_MASK_BKISO ((u32)0x1 << CKCU_POS_BKISO) +#endif /* HSICR bit field definition */ #define CKCU_POS_TRIMEN (0) @@ -152,6 +154,7 @@ #define CKCU_POS_REFCLKSEL (5) #define CKCU_MASK_REFCLKSEL ((u32)0x3 << CKCU_POS_REFCLKSEL) + /** * @} */ @@ -521,12 +524,12 @@ void CKCU_SetLCDPrescaler(CKCU_LCDPRE_TypeDef LCDPRE) /*********************************************************************************************************//** * @brief Configure the CK_MIDI prescaler. * @param MIDIPRE: specify the value of divider. - * This parameter can be: - * @arg CKCU_MIDIPRE_DIV8 : CK_MIDI = HCLK / 8 - * @arg CKCU_MIDIPRE_DIV9 : CK_MIDI = HCLK / 9 - * @arg CKCU_MIDIPRE_DIV11 : CK_MIDI = HCLK / 11 - * @arg CKCU_MIDIPRE_DIV13 : CK_MIDI = HCLK / 13 - * @arg CKCU_MIDIPRE_DIV16 : CK_MIDI = HCLK / 16 + * This parameter can be: + * @arg CKCU_MIDIPRE_DIV8 : CK_MIDI = HCLK / 8 + * @arg CKCU_MIDIPRE_DIV9 : CK_MIDI = HCLK / 9 + * @arg CKCU_MIDIPRE_DIV11 : CK_MIDI = HCLK / 11 + * @arg CKCU_MIDIPRE_DIV13 : CK_MIDI = HCLK / 13 + * @arg CKCU_MIDIPRE_DIV16 : CK_MIDI = HCLK / 16 * @retval None ************************************************************************************************************/ void CKCU_SetMIDIPrescaler(CKCU_MIDIPRE_TypeDef MIDIPRE) @@ -637,31 +640,31 @@ u32 CKCU_GetPLLFrequency(void) /*********************************************************************************************************//** * @brief Configure the APB peripheral prescaler. * @param Perip: specify the APB peripheral. - * This parameter can be: - * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, - * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, - * CKCU_PCLK_CAN0, - * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, - * CKCU_PCLK_MCTM0, - * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, - * CKCU_PCLK_USART0, CKCU_PCLK_USART1, - * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 - * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, CKCU_PCLK_OPA - * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, - * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, - * CKCU_PCLK_I2S, - * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, CKCU_PCLK_SCTM2, CKCU_PCLK_SCTM3 - * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 - * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI - * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_CAN0, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, CKCU_PCLK_OPA, CKCU_PCLK_PGA + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, CKCU_PCLK_SCTM2, CKCU_PCLK_SCTM3 + * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 + * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI + * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY * @param PCLKPrescaler: specify the value of prescaler. - * This parameter can be: - * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) - * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) - * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 - * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 - * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) - * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) + * This parameter can be: + * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 + * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 + * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) + * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) * @retval None ************************************************************************************************************/ void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPrescaler) @@ -673,29 +676,29 @@ void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_Ty Prescaler -= 2; } Perip &= 0x0000001F; - CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, Prescaler); + CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, (Prescaler & 0x3)); } #endif /*********************************************************************************************************//** * @brief Return the operating frequency of the specific APB peripheral. * @param Perip: specify the APB peripheral. - * This parameter can be: - * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, - * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, - * CKCU_PCLK_CAN0, - * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, - * CKCU_PCLK_MCTM0, - * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, - * CKCU_PCLK_USART0, CKCU_PCLK_USART1, - * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 - * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC0, CKCU_PCLK_ADC1, CKCU_PCLK_CMP, CKCU_PCLK_OPA - * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, - * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, - * CKCU_PCLK_I2S, - * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 - * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI - * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_CAN0, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC0, CKCU_PCLK_ADC1, CKCU_PCLK_CMP, CKCU_PCLK_OPA, CKCU_PCLK_PGA + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 + * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI + * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY * @retval Frequency in Hz ************************************************************************************************************/ u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip) @@ -993,14 +996,14 @@ void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cm HT_CKCU->APBCCR1 = uAPBCCR1; } -#if (((LIBCFG_LSE) || (LIBCFG_USBD)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +#if (((LIBCFG_LSE) || (LIBCFG_USBD) || (LIBCFG_CKCU_REFCLK_EXT_PIN)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) /*********************************************************************************************************//** * @brief Configure the reference clock of HSI auto-trim function. * @param CLKSRC: specify the clock source. - * This parameter can be: - * @arg CKCU_ATC_LSE: LSE is selected as reference clock - * @arg CKCU_ATC_USB: USB is selected as reference clock - * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock + * This parameter can be: + * @arg CKCU_ATC_LSE: LSE is selected as reference clock + * @arg CKCU_ATC_USB: USB is selected as reference clock + * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock * @retval None ************************************************************************************************************/ void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC) @@ -1083,7 +1086,7 @@ bool CKCU_HSIAutoTrimIsReady(void) * @param Value: 0x0~0x1F. * @retval None ************************************************************************************************************/ -void CKCU_Set_HSIReadyCounter(u8 Value) +void CKCU_SetHSIReadyCounter(u8 Value) { /* Check the parameters */ Assert_Param(IS_COUNTER_VALUE(Value)); @@ -1091,6 +1094,23 @@ void CKCU_Set_HSIReadyCounter(u8 Value) HT_CKCU->HSIRDYCR = ((HT_CKCU->HSIRDYCR) & (~(0x1F))) | Value; } #endif + +/*********************************************************************************************************//** + * @brief Set HSE Gain Mode. + * @param GanMode: Specify the gain mode of HSE. + * This parameter can be: + * @arg CKCU_HSE_LOW_GAIN_MODE : HSE low gain mode + * @arg CKCU_HSE_HIGH_GAIN_MODE : HSE high gain mode + * @retval None + ************************************************************************************************************/ +void CKCU_SetHSEGainMode(u32 GanMode) +{ + /* Check the parameters */ + Assert_Param(IS_GAINMODE(GanMode)); + + HT_CKCU->GCCR = (HT_CKCU->GCCR & ~(0x100)) | GanMode; +} + /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c index 10f4b9dded..fff32e0549 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_cmp.c - * @version $Rev:: 6932 $ - * @date $Date:: 2023-05-11 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the CMP firmware functions. ************************************************************************************************************* * @attention @@ -90,7 +90,7 @@ void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct) Assert_Param(IS_CMP_ScalerEnable(CMP_InitStruct->CMP_ScalerEnable)); Assert_Param(IS_CMP_CoutSynchronized(CMP_InitStruct->CMP_CoutSync)); Assert_Param(IS_CMP_OutputPol_Set(CMP_InitStruct->CMP_OutputPol)); - #if (LIBCFG_CMP_65x_VER) + #if (LIBCFG_CMP_65x_66x_VER) Assert_Param(IS_CMP_InputSelection(CMP_InitStruct->CMP_InputSelection)); #endif Assert_Param(IS_CMP_InvInputSelection(CMP_InitStruct->CMP_InvInputSelection)); @@ -102,7 +102,7 @@ void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct) CMP_InitStruct->CMP_OutputPol | CMP_InitStruct->CMP_InvInputSelection | CMP_InitStruct->CMP_Hysteresis | \ CMP_InitStruct->CMP_Speed; - #if (LIBCFG_CMP_65x_VER) + #if (LIBCFG_CMP_65x_66x_VER) HT_CMPn->CI = CMP_InitStruct->CMP_InputSelection; #endif } diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c index e209d4c1a0..97e58529f6 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_dac.c - * @version $Rev:: 7081 $ - * @date $Date:: 2023-08-01 #$ + * @version $Rev:: 7904 $ + * @date $Date:: 2024-07-26 #$ * @brief This file provides all the DAC firmware functions. ************************************************************************************************************* * @attention @@ -38,6 +38,15 @@ */ +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Private_Define DAC private definitions + * @{ + */ +#define DAC_ENABLE_BIT (0x00000001) +/** + * @} + */ + /* Global functions ----------------------------------------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC exported functions * @{ @@ -185,11 +194,11 @@ void DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) if (NewState != DISABLE) { - SetBit_BB((u32)&DACnCH->CR, 0); + DACnCH->CR |= DAC_ENABLE_BIT; } else { - ResetBit_BB((u32)&DACnCH->CR, 0); + DACnCH->CR &= ~(DAC_ENABLE_BIT); } } diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c index 18e04c04fa..936ef0896d 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_flash.c - * @version $Rev:: 6657 $ - * @date $Date:: 2023-01-16 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the FLASH firmware functions. ************************************************************************************************************* * @attention @@ -92,9 +92,16 @@ #define IS_WAIT_STATE2(x) (0) #endif +#if (LIBCFG_FMC_WAIT_STATE_3) +#define IS_WAIT_STATE3(x) (x == FLASH_WAITSTATE_3) +#else +#define IS_WAIT_STATE3(x) (0) +#endif + #define IS_FLASH_WAITSTATE(WAIT) ((WAIT == FLASH_WAITSTATE_0) || \ (WAIT == FLASH_WAITSTATE_1) || \ - (IS_WAIT_STATE2(WAIT))) + (IS_WAIT_STATE2(WAIT)) || \ + (IS_WAIT_STATE3(WAIT))) #endif /** * @brief Check parameter of the FLASH vector mapping. @@ -137,6 +144,7 @@ * @arg \ref FLASH_WAITSTATE_0 : zero wait state * @arg \ref FLASH_WAITSTATE_1 : one wait state * @arg \ref FLASH_WAITSTATE_2 : two wait state + * @arg \ref FLASH_WAITSTATE_3 : three wait state * @retval None ************************************************************************************************************/ void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n) diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c index 4f778467de..ed29369ffb 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_gpio.c - * @version $Rev:: 6398 $ - * @date $Date:: 2022-10-27 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the GPIO and AFIO firmware functions. ************************************************************************************************************* * @attention @@ -293,7 +293,7 @@ void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, Contr GPIO_CK_OFF(); } -#if LIBCFG_GPIO_SINK_CURRENT_ENHANCED +#if (LIBCFG_GPIO_SINK_CURRENT_ENHANCED) /*********************************************************************************************************//** * @brief Select the sink current of specified GPIO pins. * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c index 0ab83cf919..d659df0830 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_pwrcu.c - * @version $Rev:: 6386 $ - * @date $Date:: 2022-10-27 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the Power Control Unit firmware functions. ************************************************************************************************************* * @attention @@ -68,9 +68,11 @@ #define Reset_V15RDYSC ResetBit_BB((u32)&HT_PWRCU->CR, 12) #endif +#if (!LIBCFG_PWRCU_NO_DS2_MODE) #define Set_DMOSSTS SetBit_BB((u32)&HT_PWRCU->CR, 15) #define Reset_DMOSSTS ResetBit_BB((u32)&HT_PWRCU->CR, 15) #define Get_DMOSSTS GetBit_BB((u32)&HT_PWRCU->CR, 15) +#endif #define Set_BODEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 0) #define Reset_BODEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 0) @@ -105,7 +107,6 @@ #define LVDS_MASK 0xFFB9FFFF #define VREG_V_MASK 0xF3FFFFFF #define VREG_M_MASK 0xFCFFFFFF -#define PWRRST_SET 0x1 /** * @} */ @@ -266,6 +267,7 @@ void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry) SCB->SCR &= ~(u32)SLEEPDEEP_SET; } +#if (!LIBCFG_PWRCU_NO_DS2_MODE) /*********************************************************************************************************//** * @brief Enter DEEP-SLEEP Mode 2. * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. @@ -385,6 +387,7 @@ void PWRCU_DeepSleep2Ex(PWRCU_SLEEP_ENTRY_Enum SleepEntry) } } #endif +#endif #if (!LIBCFG_PWRCU_NO_PD_MODE) /*********************************************************************************************************//** @@ -561,6 +564,7 @@ FlagStatus PWRCU_GetBODFlagStatus(void) return (FlagStatus)Get_BODF; } +#if (!LIBCFG_PWRCU_NO_DS2_MODE) /*********************************************************************************************************//** * @brief Return the DMOS status. * @retval This function will return one of the following values: @@ -610,6 +614,7 @@ void PWRCU_DMOSCmd(ControlStatus NewState) Reset_DMOSON; } } +#endif /*********************************************************************************************************//** * @brief Configure the LDO operation mode. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c index 5515859641..ffc160adf9 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_spi.c - * @version $Rev:: 7322 $ - * @date $Date:: 2023-10-28 #$ + * @version $Rev:: 7674 $ + * @date $Date:: 2024-03-28 #$ * @brief This file provides all the SPI firmware functions. ************************************************************************************************************* * @attention @@ -364,6 +364,11 @@ void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL) } else { + /* Inactive SEL pin needs to ensure the transmission has ended. If the program flow cannot guarantee */ + /* SPI transmission completion, you can enable the procedure below. */ + #if 0 + while (SPIx->SR & SPI_FLAG_BUSY); /* Wait until SPI NOT BUSY */ + #endif SPIx->CR0 &= SPI_SEL_INACTIVE; } } @@ -602,6 +607,8 @@ void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) Assert_Param(IS_SPI(SPIx)); Assert_Param(IS_CONTROL_STATUS(NewState)); + while (SPIx->SR & SPI_FLAG_BUSY); /* Wait until SPI NOT BUSY */ + (NewState == ENABLE)?(SPIx->CR0 |= CR0_DUALEN_SET):(SPIx->CR0 &= CR0_DUALEN_RESET); } #endif @@ -619,6 +626,8 @@ void QSPI_QuadCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) Assert_Param(IS_QSPI(SPIx)); Assert_Param(IS_CONTROL_STATUS(NewState)); + while (SPIx->SR & SPI_FLAG_BUSY); /* Wait until SPI NOT BUSY */ + if (NewState == DISABLE) { QSPI_DirectionConfig(SPIx, SIO_DIR_IN); @@ -645,6 +654,8 @@ void QSPI_DirectionConfig(HT_SPI_TypeDef* SPIx, SIO_DIR_Enum SIO_DIR_INorOUT) Assert_Param(IS_QSPI(SPIx)); Assert_Param(IS_SIO_DIR(SIO_DIR_INorOUT)); + while (SPIx->SR & SPI_FLAG_BUSY); /* Wait until SPI NOT BUSY */ + if (SIO_DIR_INorOUT != SIO_DIR_IN) SPIx->CR0 |= CR0_QDIODIR_OUT; else diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c index 1e4a2fe15d..dbc66535b2 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_tm.c - * @version $Rev:: 7059 $ - * @date $Date:: 2023-07-27 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the TM firmware functions. ************************************************************************************************************* * @attention @@ -67,7 +67,8 @@ #define CTR_CHCCDS 0x00010000ul #define CH0ICFR_CH0SRC 0x80000000ul -#define CHICFR_CHF_MASK ~0x000000FFul +#define CHICFR_CHF_MASK ~0x000000FFul /* CHF Mask for CHICFR, varies by model. + Using ~0x000000FFul for all model. */ #define CHICFR_CHCCS_MASK ~0x00030000ul #define CHICFR_CHPSC_MASK ~0x000C0000ul @@ -335,12 +336,12 @@ void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) Assert_Param(IS_TM_CHP(CapInit->Polarity)); Assert_Param(IS_TM_CHCCS(CapInit->Selection)); Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) #else Assert_Param(IS_TM_FILTER(CapInit->Filter)); #endif - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) Filter = FILTER_PROCESS(CapInit); #else Filter = CapInit->Filter; @@ -373,7 +374,7 @@ void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) Assert_Param(IS_TM_CHP(CapInit->Polarity)); Assert_Param(IS_TM_CHCCS(CapInit->Selection)); Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) #else Assert_Param(IS_TM_FILTER(CapInit->Filter)); #endif @@ -409,7 +410,7 @@ void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) OppositeChannel = TM_CH_0; } - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) Filter = FILTER_PROCESS(CapInit); #else Filter = CapInit->Filter; @@ -479,7 +480,7 @@ void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit) CapInit->Polarity = TM_CHP_NONINVERTED; CapInit->Selection = TM_CHCCS_DIRECT; CapInit->Prescaler = TM_CHPSC_OFF; - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) CapInit->Fsampling = TM_CHFDIV_1; CapInit->Event = TM_CHFEV_OFF; #else @@ -559,7 +560,7 @@ void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Assert_Param(IS_TM(TMx)); Assert_Param(IS_TM_TRSEL_CH(Sel)); Assert_Param(IS_TM_CHP(Pol)); - #if (LIBCFG_TM_652XX_V1) + #if (LIBCFG_TM_65X_66X_V1) #else Assert_Param(IS_TM_FILTER(Filter)); #endif @@ -903,6 +904,7 @@ void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus } } +#if 0 /*********************************************************************************************************//** * @brief Clear or Safeguard the CHxOREF signal when ETI is active. * @param TMx: where TMx is the selected TM from the TM peripheral. @@ -934,6 +936,7 @@ void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus Ne *pOcfr &= ~CHOCFR_REFCE; } } +#endif /*********************************************************************************************************//** * @brief Configure polarity of the TMx channel N. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c index c0dd366f36..b5ec97acf6 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_usart.c - * @version $Rev:: 7054 $ - * @date $Date:: 2023-07-24 #$ + * @version $Rev:: 7698 $ + * @date $Date:: 2024-04-15 #$ * @brief This file provides all the USART firmware functions. ************************************************************************************************************* * @attention @@ -366,7 +366,7 @@ void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag) * @arg USART_INT_RSADD : * @arg USART_INT_TOUT : * @arg USART_INT_CTS : -* @arg USART_INT_LBD : + * @arg USART_INT_LBD : * @param NewState: This parameter can be ENABLE or DISABLE. * @retval None ************************************************************************************************************/ @@ -871,11 +871,10 @@ void USART_LIN_SendBreak(HT_USART_TypeDef* USARTx) USARTx->CR |= USART_LINSENDBREAK; } - /*********************************************************************************************************//** * @brief Configure the break detection length in LIN mode. * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. - * @param length: data length in byte. + * @param USART_LIN_Length: data length in byte. * This parameter can be one of the following values: * @arg USART_LINLENGTH_11BIT * @arg USART_LINLENGTH_10BIT diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c index b90f5b1fac..13d5064e60 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f5xxxx_wdt.c - * @version $Rev:: 2772 $ - * @date $Date:: 2018-05-15 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the WDT firmware functions. ************************************************************************************************************* * @attention @@ -55,8 +55,8 @@ #define MODE0_WDTFIEN_RESET ((u32)0xFFFFEFFF) /* WDT WDTRSTEN mask */ -#define MODE0_WDTRETEN_SET ((u32)0x00002000) -#define MODE0_WDTRETEN_RESET ((u32)0xFFFFDFFF) +#define MODE0_WDTRSTEN_SET ((u32)0x00002000) +#define MODE0_WDTRSTEN_RESET ((u32)0xFFFFDFFF) /* WDT WDTEN mask */ #define MODE0_WDTEN_SET ((u32)0x00010000) @@ -109,9 +109,9 @@ void WDT_Cmd(ControlStatus NewState) * @brief Configure the WDT to run or halt in sleep and deep sleep1 mode. * @param WDT_Mode: * This parameter can be one of the following values: - * @arg MODE0_WDTSHLT_BOTH : WDT runs in sleep and deep sleep1 mode - * @arg MODE0_WDTSHLT_SLEEP : WDT runs in sleep mode - * @arg MODE0_WDTSHLT_HALT : WDT halts in sleep and deep sleep1 mode + * @arg WDT_SLEEP_HALT_NONE : WDT no halt + * @arg WDT_SLEEP_HALT_DEEPSLEEP : WDT halts in deep sleep1 mode + * @arg WDT_SLEEP_HALT_ALL : WDT halts in sleep and deep sleep1 mode * @retval None ************************************************************************************************************/ void WDT_HaltConfig(u32 WDT_Mode) @@ -134,11 +134,11 @@ void WDT_ResetCmd(ControlStatus NewState) if (NewState != DISABLE) { - HT_WDT->MR0 |= MODE0_WDTRETEN_SET; + HT_WDT->MR0 |= MODE0_WDTRSTEN_SET; } else { - HT_WDT->MR0 &= MODE0_WDTRETEN_RESET; + HT_WDT->MR0 &= MODE0_WDTRSTEN_RESET; } } diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c index 88c5d8aced..c624ee0289 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f65xxx_66xxx_adc.c - * @version $Rev:: 7367 $ - * @date $Date:: 2023-12-06 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the ADC firmware functions. ************************************************************************************************************* * @attention @@ -43,7 +43,11 @@ * @{ */ #define ADC_ENABLE_BIT (0x00000080) + +#if (LIBCFG_ADC1) #define DUAL_MODE_MASK (0x00000003) +#endif + #define ADC_SOFTWARE_RESET (0x00000001) #define LST_SEQ_SET (0x0000001F) #define TCR_SC_SET (0x00000001) @@ -51,9 +55,15 @@ #define HLST_SEQ_SET (0x0000001F) #define HTCR_SC_SET (0x00000001) +#if (!LIBCFG_ADC_NO_OFFSET_REG) #define OFR_ADOF_MASK (0x00000FFF) #define OFR_ADAL (1 << 14) #define OFR_ADOFE (1 << 15) +#endif + +#if (LIBCFG_ADC_MVDDA) +#define ADC_VREF_MVDDAEN (0x00000100) +#endif /** * @} */ @@ -162,8 +172,8 @@ void ADC_DualModeConfig(HT_ADC_TypeDef* HT_ADCn, u32 DUAL_X, u8 HDelayTime, u8 D * @arg ONE_SHOT_MODE : * @arg CONTINUOUS_MODE : * @arg DISCONTINUOUS_MODE : - * @param Length: must between 1 ~ 16 - * @param SubLength: must between 1 ~ 16, only valid for DISCONTINUOUS_MODE. + * @param Length: must between 1 ~ 8 + * @param SubLength: must between 1 ~ 8, only valid for DISCONTINUOUS_MODE. * @retval None ************************************************************************************************************/ void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) @@ -189,8 +199,8 @@ void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 * @arg ONE_SHOT_MODE : * @arg CONTINUOUS_MODE : * @arg DISCONTINUOUS_MODE : - * @param Length: must between 1 ~ 4 - * @param SubLength: must between 1 ~ 4 + * @param Length: must between 1 ~ 8 (5 ~ 8 only for specific model) + * @param SubLength: must between 1 ~ 8 (5 ~ 8 only for specific model) * @retval None ************************************************************************************************************/ void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) @@ -211,8 +221,16 @@ void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLe * @param ADC_CH_n: the ADC channel to configure * This parameter can be one of the following values: * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 7 + * @arg ADC_CH_OPA0 : ADC OPA0O selected + * @arg ADC_CH_OPA1 : ADC OPA1O selected + * @arg ADC_CH_PGA0O : ADC PGA0O selected + * @arg ADC_CH_PGA1O : ADC PGA1O selected + * @arg ADC_CH_PGA2O : ADC PGA2O selected + * @arg ADC_CH_PGA3O : ADC PGA3O selected * @arg ADC_CH_GND_VREF : ADC GND VREF selected * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @arg ADC_CH_BANDGAP : ADC BANDGAP selected + * @arg ADC_CH_MVDDA : ADC MVDDA selected * @param Rank: The rank in the regular group sequencer. * This parameter must be between 0 to 7. * @param SampleClock: Number of sampling clocks. @@ -230,7 +248,18 @@ void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); /* config sampling clock of correspond ADC input channel */ + #if (LIBCFG_ADC_STR_16_17) + if (ADC_CH_n < 16) + { + HT_ADCn->STR[ADC_CH_n] = SampleClock; + } + else + { + HT_ADCn->STR16[ADC_CH_n - 16] = SampleClock; + } + #else HT_ADCn->STR[ADC_CH_n] = SampleClock; + #endif /* Get the old register value */ tmpreg1 = HT_ADCn->LST[Rank >> 2]; @@ -252,10 +281,18 @@ void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 * @param ADC_CH_n: the ADC channel to configure * This parameter can be one of the following values: * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 7 + * @arg ADC_CH_OPA0 : ADC OPA0O selected + * @arg ADC_CH_OPA1 : ADC OPA1O selected + * @arg ADC_CH_PGA0O : ADC PGA0O selected + * @arg ADC_CH_PGA1O : ADC PGA1O selected + * @arg ADC_CH_PGA2O : ADC PGA2O selected + * @arg ADC_CH_PGA3O : ADC PGA3O selected * @arg ADC_CH_GND_VREF : ADC GND VREF selected * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @arg ADC_CH_BANDGAP : ADC BANDGAP selected + * @arg ADC_CH_MVDDA : ADC MVDDA selected * @param Rank: The rank in the high priority group sequencer. - * This parameter must be between 0 to 3. + * This parameter must be between 0 to 11. (4 ~ 11 only for specific model) * @param SampleClock: Number of sampling clocks. * This parameter must be between 0x00 to 0xFF. * @retval None @@ -271,10 +308,25 @@ void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 Sampl Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); /* config sampling clock of correspond ADC input channel */ + #if (LIBCFG_ADC_STR_16_17) + if (ADC_CH_n < 16) + { + HT_ADCn->STR[ADC_CH_n] = SampleClock; + } + else + { + HT_ADCn->STR16[ADC_CH_n - 16] = SampleClock; + } + #else HT_ADCn->STR[ADC_CH_n] = SampleClock; + #endif /* Get the old register value */ + #if (LIBCFG_ADC_HLST_0_2) + tmpreg1 = HT_ADCn->HLST[Rank >> 2]; + #else tmpreg1 = HT_ADCn->HLST; + #endif /* Calculate the mask to clear */ tmpreg2 = HLST_SEQ_SET << (8 * (Rank & 0x3)); /* Clear the old SEQx bits for the selected rank */ @@ -284,7 +336,11 @@ void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 Sampl /* Set the SEQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ + #if (LIBCFG_ADC_HLST_0_2) + HT_ADCn->HLST[Rank >> 2] = tmpreg1; + #else HT_ADCn->HLST = tmpreg1; + #endif } /*********************************************************************************************************//** @@ -537,7 +593,7 @@ u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) /*********************************************************************************************************//** * @brief Return the result of ADC high priority channel conversion. * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. - * @param ADC_HP_DATAn: where x can be 0 ~ 3 + * @param ADC_HP_DATAn: where x can be 0 ~ 11, (4 ~ 11 only for specific model) * @retval The Value of data conversion. ************************************************************************************************************/ u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn) @@ -546,7 +602,18 @@ u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn) Assert_Param(IS_ADC(HT_ADCn)); Assert_Param(IS_ADC_HP_DATA(ADC_HP_DATAn)); + #if (LIBCFG_ADC_HDR_4_11) + if (ADC_HP_DATAn < 4) + { + return ((u16)HT_ADCn->HDR[ADC_HP_DATAn]); + } + else + { + return ((u16)HT_ADCn->HDR4[ADC_HP_DATAn - 4]); + } + #else return ((u16)HT_ADCn->HDR[ADC_HP_DATAn]); + #endif } /*********************************************************************************************************//** @@ -770,6 +837,54 @@ void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewSt HT_ADCn->PDMAR &= ~ADC_PDMA_x; } } + +#if (LIBCFG_ADC_IVREF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000001; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000001); + } +} +#endif + +#if (LIBCFG_ADC_MVDDA) +/*********************************************************************************************************//** + * @brief Enable or Disable the power of MVDDA (VDDA/2) + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= ADC_VREF_MVDDAEN; + } + else + { + HT_ADCn->VREFCR &= ~(ADC_VREF_MVDDAEN); + } +} +#endif /** * @} */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c index 6df13c0c01..69a13d106e 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c @@ -1,7 +1,7 @@ /*********************************************************************************************************//** * @file ht32f65xxx_66xxx_opa.c - * @version $Rev:: 6932 $ - * @date $Date:: 2023-05-11 #$ + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ * @brief This file provides all the OPA firmware functions. ************************************************************************************************************* * @attention @@ -113,7 +113,7 @@ void OPA_ProtectConfig(HT_OPA_TypeDef* HT_OPAn) /* Check the parameters */ Assert_Param(IS_OPA(HT_OPAn)); - /* Write any value to bit 16 ~ 31 (PROTECT) and keep the other control bir */ + /* Write any value to bit 16 ~ 31 (PROTECT) and keep the other control bit */ HT_OPAn->CR = HT_OPAn->CR; } @@ -153,28 +153,9 @@ void OPA_Init(HT_OPA_TypeDef* HT_OPAn, OPA_InitTypeDef* OPA_InitStruct) Assert_Param(IS_OPA(HT_OPAn)); Assert_Param(IS_OPA_ScalerEnable(OPA_InitStruct->OPA_ScalerEnable)); Assert_Param(IS_OPA_ExtPinEnable(OPA_InitStruct->OPA_ExternalPinEnable)); - #if (LIBCFG_OPA_PGA) - Assert_Param(IS_OPA_PGAEnable(OPA_InitStruct->OPA_PGAEnable)); - Assert_Param(IS_OPA_UnitGainEnable(OPA_InitStruct->OPA_UnitGainEnable)); - Assert_Param(IS_OPA_PGA_SEL(OPA_InitStruct->OPA_PGAGain)); - #endif - #if (LIBCFG_OPA_PGA) - /* avoid both PGA and unit gain active at the same time */ - if (OPA_InitStruct->OPA_UnitGainEnable == OPA_UNITGAIN_ENABLE) - { - OPA_InitStruct->OPA_PGAEnable = OPA_PGA_DISABLE; - } - #endif - - #if (LIBCFG_OPA_PGA) - HT_OPAn->CR = OPA_InitStruct->OPA_ScalerEnable | OPA_InitStruct->OPA_PGAGain | \ - OPA_InitStruct->OPA_ExternalPinEnable | OPA_InitStruct->OPA_PGAEnable | \ - OPA_InitStruct->OPA_UnitGainEnable; - #else HT_OPAn->CR = OPA_InitStruct->OPA_ScalerEnable | \ OPA_InitStruct->OPA_ExternalPinEnable; - #endif } /*********************************************************************************************************//** @@ -187,11 +168,6 @@ void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct) /* OPA_InitStruct members default value */ OPA_InitStruct->OPA_ScalerEnable = OPA_SCALER_DISABLE; OPA_InitStruct->OPA_ExternalPinEnable = OPA_ExternalPin_DISABLE; - #if (LIBCFG_OPA_PGA) - OPA_InitStruct->OPA_PGAEnable = OPA_PGA_DISABLE; - OPA_InitStruct->OPA_UnitGainEnable = OPA_UNITGAIN_DISABLE; - OPA_InitStruct->OPA_PGAGain = PGA_GAIN_6; - #endif } /*********************************************************************************************************//** @@ -220,98 +196,6 @@ void OPA_ExternalInputCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) } } -#if (LIBCFG_OPA_PGA) -/*********************************************************************************************************//** - * @brief Enable or Disable the Unit Gain. - * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. - * @param NewState: This parameter can be ENABLE or DISABLE. - * @retval None - ************************************************************************************************************/ -void OPA_UnitGainCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) -{ - u32 OPA_CR = (u32)(&HT_OPAn->CR); - u32 CRValue; - - /* Check the parameters */ - Assert_Param(IS_OPA(HT_OPAn)); - Assert_Param(IS_CONTROL_STATUS(NewState)); - - CRValue = HT_OPAn->CR & (~(0x06UL)); // reset unit gain & PGA - - if (NewState == ENABLE) - { - CRValue |= 0x2; - } - - HT_OPAn->CR = gOPAUnProtectKey; - HT_OPAn->CR = CRValue; -} - -/*********************************************************************************************************//** - * @brief Enable or Disable the PGA. - * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. - * @param NewState: This parameter can be ENABLE or DISABLE. - * @retval None - ************************************************************************************************************/ -void OPA_PGACmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) -{ - u32 OPA_CR = (u32)(&HT_OPAn->CR); - u32 CRValue; - - /* Check the parameters */ - Assert_Param(IS_OPA(HT_OPAn)); - Assert_Param(IS_CONTROL_STATUS(NewState)); - - CRValue = HT_OPAn->CR & (~(0x06UL)); // reset unit gain & PGA - - if (NewState == ENABLE) - { - CRValue |= 0x4; // set PGA - } - - HT_OPAn->CR = gOPAUnProtectKey; - HT_OPAn->CR = CRValue; -} - -/*********************************************************************************************************//** - * @brief Configure the Gain Selection for the PGA. - * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. - * @param GAIN_SEL : - * This parameter can be one of the following value: - * @arg PGA_GAIN_6 : - * @arg PGA_GAIN_8 : - * @arg PGA_GAIN_12 : - * @arg PGA_GAIN_16 : - * @arg PGA_GAIN_24 : - * @arg PGA_GAIN_32 : - * @arg PGA_GAIN_48 : - * @arg PGA_GAIN_64 : - * @arg PGA_GAIN_5 : - * @arg PGA_GAIN_7 : - * @arg PGA_GAIN_11 : - * @arg PGA_GAIN_15 : - * @arg PGA_GAIN_23 : - * @arg PGA_GAIN_31 : - * @arg PGA_GAIN_47 : - * @arg PGA_GAIN_63 : - * @retval None - ************************************************************************************************************/ -void OPA_PGAGain(HT_OPA_TypeDef* HT_OPAn, u8 bGAIN_SEL) -{ - u32 CRValue; - - /* Check the parameters */ - Assert_Param(IS_OPA(HT_OPAn)); - Assert_Param(IS_OPA_PGA_SEL(bGAIN_SEL)); - - CRValue = HT_OPAn->CR & (~0x70UL); - CRValue |= (u32)bGAIN_SEL << 4; - - HT_OPAn->CR = gOPAUnProtectKey; - HT_OPAn->CR = CRValue; -} -#endif - /*********************************************************************************************************//** * @brief Enable or Disable the 10bit Scaler. * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c index 6dacca7f49..41b1b509e7 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f65xxx_66xxx_pga.c - * @version $Rev:: 6914 $ - * @date $Date:: 2023-05-10 #$ - * @brief This file provides all the PGA firmware functions. (temporary file, not finish/support yet). + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ + * @brief This file provides all the PGA firmware functions. ************************************************************************************************************* * @attention * @@ -37,8 +37,654 @@ * @{ */ +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup PGA_Private_Define PGA private definitions + * @{ + */ +#define PGA_ENABLE (0x00000001ul) +#define CR_REF_POS 10 +#define CR_HVDDA_POS 8 +#define CR_OUTPUT_HIGH (1) +#define CR_OUTPUT_POS 7 + +#define CR_GAIN_POS 4 +#define CR_GAIN_MASK (0x7ul << CR_GAIN_POS) + +#define CR_NE_POS 3 + +#define CR_PGA_POS 2 + +#define CR_NUG_POS 1 + +#define VOS_OFM_CALIBRATION_MODE (1) +#define VOS_OFM_POS 7 + +#define VOS_RSP_POS 6 + +#define VOS_OF_DEFAULT_VALUE (0x10) +#define VOS_OF_POS 0 +#define VOS_OF_MASK (0x1Ful << VOS_OF_POS) + +#define VR_VFEN_SET ((u32)0x00000001) +#define VR_VFEN_RESET ((u32)0xFFFFFFFE) + +#define PGA0_OF_WITH_CALIBRATION 0x1 +#define PGA1_OF_WITH_CALIBRATION 0x2 +#define PGA2_OF_WITH_CALIBRATION 0x4 +#define PGA3_OF_WITH_CALIBRATION 0x8 +/** + * @} + */ +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup PGA_Private_Macro PGA private macros + * @{ + */ +#define IS_PGA0(x) (x == HT_PGA0) +#if (LIBCFG_PGA1) +#define IS_PGA1(x) (x == HT_PGA1) +#else +#define IS_PGA1(x) (0) +#endif +#if (LIBCFG_PGA2) +#define IS_PGA2(x) (x == HT_PGA2) +#else +#define IS_PGA2(x) (0) +#endif +#if (LIBCFG_PGA3) +#define IS_PGA3(x) (x == HT_PGA3) +#else +#define IS_PGA3(x) (0) +#endif +#define IS_PGA(x) (IS_PGA0(x) || \ + IS_PGA1(x) || \ + IS_PGA2(x) || \ + IS_PGA3(x)) + +#define IS_PGA_HVDDA_OPTION(x) ((x == PGA_HVDDA_DISABLE) || \ + (x == PGA_HVDDA_RESISTOR) || \ + (x == PGA_HVDDA_POS_INPUT)) + +#define IS_PGA_GAIN(x) ((x == PGA_GAIN_LEVEL_0) || \ + (x == PGA_GAIN_LEVEL_1) || \ + (x == PGA_GAIN_LEVEL_2) || \ + (x == PGA_GAIN_LEVEL_3) || \ + (x == PGA_GAIN_LEVEL_4) || \ + (x == PGA_GAIN_LEVEL_5)) + +#define IS_PGA_INPUT(x) ((x == PGA_INPUT_NEGATIVE) || \ + (x == PGA_INPUT_POSITIVE)) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +static u32 gPGAUnProtectKey = 0; +static vu32 gPGACaliValInit = 0; + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PGA_Exported_Functions PGA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the PGA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void PGA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.PGA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); + + gPGACaliValInit = 0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PGA peripheral. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None +*************************************************************************************************************/ +void PGA_Cmd(HT_PGA0_X_TypeDef* HT_PGAn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_PGAn->CR = gPGAUnProtectKey; + + if (NewState != DISABLE) + { + /* Enable the selected HT_PGAn peripheral */ + HT_PGAn->CR |= PGA_ENABLE; + } + else + { + /* Disable the selected HT_PGAn peripheral */ + HT_PGAn->CR &= ~(u32)PGA_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Set the unprotect key. + * @param uUnProtectKey: protect key, shall be PGA_UNPROTECT_KEY + * @retval None + ************************************************************************************************************/ +void PGA_SetUnProtectKey(u32 uUnProtectKey) +{ + gPGAUnProtectKey = uUnProtectKey << 16; +} + +/*********************************************************************************************************//** + * @brief Protect the selected PGA before setting the PGA Control Register. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @retval None + ************************************************************************************************************/ +void PGA_ProtectConfig(HT_PGA0_X_TypeDef* HT_PGAn) +{ + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + + /* Write any value to bit 16 ~ 31 (PROTECT) and keep the other control bit */ + HT_PGAn->CR = HT_PGAn->CR; +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected PGA before setting the PGA Control Register. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @retval None + ************************************************************************************************************/ +void PGA_UnprotectConfig(HT_PGA0_X_TypeDef* HT_PGAn) +{ + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + + /* Set the unlock code corresponding to selected PGA */ + CRValue = HT_PGAn->CR & 0x0000FFFF; + HT_PGAn->CR = gPGAUnProtectKey | CRValue; +} + +/*********************************************************************************************************//** + * @brief Initialize the PGA peripheral according to the specified parameters in the PGA_InitStruct. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_InitStruct: pointer to a PGA_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void PGA_Init(HT_PGA0_X_TypeDef* HT_PGAn, PGA_InitTypeDef* PGA_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_HVDDA_OPTION(PGA_InitStruct->PGA_HVDDA)); + + /* According to the HT_PGAn calibration value flag, initialize the calibration value to 0x10 if needed. */ + if((HT_PGAn == HT_PGA0) && !(gPGACaliValInit & PGA0_OF_WITH_CALIBRATION)) + { + HT_PGA0->VOS = 0x00000090; + HT_PGA0->VOS &= 0xFFFFFF7F; + } + #if (LIBCFG_PGA1) + else if((HT_PGAn == HT_PGA1) && !(gPGACaliValInit & PGA1_OF_WITH_CALIBRATION)) + { + HT_PGA1->VOS = 0x00000090; + HT_PGA1->VOS &= 0xFFFFFF7F; + } + #endif + #if (LIBCFG_PGA2) + else if((HT_PGAn == HT_PGA2) && !(gPGACaliValInit & PGA2_OF_WITH_CALIBRATION)) + { + HT_PGA2->VOS = 0x00000090; + HT_PGA2->VOS &= 0xFFFFFF7F; + } + #endif + #if (LIBCFG_PGA3) + else if((HT_PGAn == HT_PGA3) && !(gPGACaliValInit & PGA3_OF_WITH_CALIBRATION)) + { + HT_PGA3->VOS = 0x00000090; + HT_PGA3->VOS &= 0xFFFFFF7F; + } + #endif + + HT_PGAn->CR = gPGAUnProtectKey; + + HT_PGAn->CR = (u32)PGA_InitStruct->PGA_REF << CR_REF_POS | \ + (u32)PGA_InitStruct->PGA_NUG << CR_NUG_POS | \ + (u32)PGA_InitStruct->PGA_NE << CR_NE_POS | \ + (u32)PGA_InitStruct->PGA_PGA << CR_PGA_POS | \ + (u32)PGA_InitStruct->PGA_HVDDA << CR_HVDDA_POS; +} + +/*********************************************************************************************************//** + * @brief Fill each PGA_InitStruct member with its default value. + * @param PGA_InitStruct: pointer to an PGA_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void PGA_StructInit(PGA_InitTypeDef* PGA_InitStruct) +{ + /* PGA_InitStruct members default value */ + PGA_InitStruct->PGA_REF = DISABLE; + PGA_InitStruct->PGA_NUG = DISABLE; + PGA_InitStruct->PGA_NE = DISABLE; + PGA_InitStruct->PGA_PGA = DISABLE; + PGA_InitStruct->PGA_HVDDA = PGA_HVDDA_DISABLE; +} + +/*********************************************************************************************************//** + * @brief Configure the Gain for the selected PGA Control Register. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_LEVEL_x: Where PGA_GAIN_LEVEL_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_LEVEL_0 + * @arg PGA_GAIN_LEVEL_1 + * @arg PGA_GAIN_LEVEL_2 + * @arg PGA_GAIN_LEVEL_3 + * @arg PGA_GAIN_LEVEL_4 + * @arg PGA_GAIN_LEVEL_5 + * @retval None + ************************************************************************************************************/ +void PGA_GainConfig(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x) +{ + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_LEVEL_x)); + + CRValue = HT_PGAn->CR & 0x0000FFFF; + CRValue &= ~CR_GAIN_MASK; + + HT_PGAn->CR = gPGAUnProtectKey; + HT_PGAn->CR = ((u32)PGA_GAIN_LEVEL_x << CR_GAIN_POS) | CRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the PGAHVDDA Voltage Follower. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None +*************************************************************************************************************/ +void PGA_HVDDACmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if(NewState != DISABLE) + { + /* Enable the selected HT_PGAn peripheral */ + HT_PGA->VR |= (u32)VR_VFEN_SET; + } + else + { + /* Disable the selected HT_PGAn peripheral */ + HT_PGA->VR &= (u32)VR_VFEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Calibration mode. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None +*************************************************************************************************************/ +void PGA_CalibrationCmd(HT_PGA0_X_TypeDef* HT_PGAn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if(NewState != DISABLE) + { + HT_PGAn->VOS |= (u32)VOS_OFM_CALIBRATION_MODE << VOS_OFM_POS; + /* + Set the HT_PGAn calibration value flag to true to ensure that the calibration value does not change + after executing calibration. + */ + if(HT_PGAn == HT_PGA0) + { + gPGACaliValInit |= PGA0_OF_WITH_CALIBRATION; + } + #if (LIBCFG_PGA1) + else if(HT_PGAn == HT_PGA1) + { + gPGACaliValInit |= PGA1_OF_WITH_CALIBRATION; + } + #endif + #if (LIBCFG_PGA2) + else if(HT_PGAn == HT_PGA2) + { + gPGACaliValInit |= PGA2_OF_WITH_CALIBRATION; + } + #endif + #if (LIBCFG_PGA3) + else if(HT_PGAn == HT_PGA3) + { + gPGACaliValInit |= PGA3_OF_WITH_CALIBRATION; + } + #endif + } + else + { + HT_PGAn->VOS &= ~((u32)VOS_OFM_CALIBRATION_MODE << VOS_OFM_POS); + } +} + +/*********************************************************************************************************//** + * @brief Configure the direction of Calibration reference pins. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_INPUT_x: where PGA_INPUT_x is the calibration reference. + * This parameter can be one of the following values: + * @arg PGA_INPUT_NEGATIVE + * @arg PGA_INPUT_POSITIVE + * @retval None +*************************************************************************************************************/ +void PGA_SetCalibrationInput(HT_PGA0_X_TypeDef* HT_PGAn, PGA_CALIBRATION_INPUT_Enum PGA_INPUT_x) +{ + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_INPUT(PGA_INPUT_x)); + + if(PGA_INPUT_x == PGA_CALIBRATION_INPUT_NEGATIVE) + { + PGA_UnprotectConfig(HT_PGAn); + HT_PGAn->CR |= (u32)ENABLE << CR_NE_POS; + HT_PGAn->VOS &= ~((u32)ENABLE << VOS_RSP_POS); + } + else + { + HT_PGAn->VOS |= (u32)ENABLE << VOS_RSP_POS; + } +} + +/*********************************************************************************************************//** + * @brief Configure the calibration value. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param Value: the calibration value. + * @retval None +*************************************************************************************************************/ +void PGA_SetCalibrationValue(HT_PGA0_X_TypeDef* HT_PGAn, u32 Value) +{ + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + + HT_PGAn->VOS = (HT_PGAn->VOS & ~(u32)(VOS_OF_MASK)) | Value; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified PID flag has been set. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @retval None +*************************************************************************************************************/ +FlagStatus PGA_ReadOutputBit(HT_PGA0_X_TypeDef* HT_PGAn) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + + if ((HT_PGAn->CR & ((u32)CR_OUTPUT_HIGH << CR_OUTPUT_POS)) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Set Inverting Amplifier Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_x: Where PGA_GAIN_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_6 + * @arg PGA_GAIN_8 + * @arg PGA_GAIN_12 + * @arg PGA_GAIN_16 + * @arg PGA_GAIN_24 + * @arg PGA_GAIN_32 + * @retval None + * @note Model configuration must follow the rules below: + * Inverting Amplifier Mode : The positive input must be grounded. + ************************************************************************************************************/ +void PGA_SetModeInverting(HT_PGA0_X_TypeDef* HT_PGAn, PGA_GAIN_TYPE1_Enum PGA_GAIN_x) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_x)); + + PGA_InitStruct.PGA_REF = ENABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = DISABLE; + PGA_InitStruct.PGA_PGA = ENABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); + PGA_GainConfig(HT_PGAn, PGA_GAIN_x); +} + +/*********************************************************************************************************//** + * @brief Set the Differentiator Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_LEVEL_x: Where PGA_GAIN_LEVEL_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_LEVEL_0 + * @arg PGA_GAIN_LEVEL_1 + * @arg PGA_GAIN_LEVEL_2 + * @arg PGA_GAIN_LEVEL_3 + * @arg PGA_GAIN_LEVEL_4 + * @arg PGA_GAIN_LEVEL_5 + * @retval None + * @note Model configuration must follow the rules below: + * Differentiator : The positive input must have an external capacitor and be grounded. + ************************************************************************************************************/ +void PGA_SetModeDifferentiator(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_LEVEL_x)); + + PGA_InitStruct.PGA_REF = ENABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = DISABLE; + PGA_InitStruct.PGA_PGA = ENABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); + PGA_GainConfig(HT_PGAn, PGA_GAIN_LEVEL_x); +} + +/*********************************************************************************************************//** + * @brief Set the Non-Inverting Amplifier Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_x: Where PGA_GAIN_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_6 + * @arg PGA_GAIN_8 + * @arg PGA_GAIN_12 + * @arg PGA_GAIN_16 + * @arg PGA_GAIN_24 + * @arg PGA_GAIN_32 + * @retval None + ************************************************************************************************************/ +void PGA_SetModeNonInverting(HT_PGA0_X_TypeDef* HT_PGAn, PGA_GAIN_TYPE1_Enum PGA_GAIN_x) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_x)); + + PGA_InitStruct.PGA_REF = DISABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = DISABLE; + PGA_InitStruct.PGA_PGA = ENABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); + PGA_GainConfig(HT_PGAn, PGA_GAIN_x); +} + +/*********************************************************************************************************//** + * @brief Set the Inverting Adder Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_LEVEL_x: Where PGA_GAIN_LEVEL_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_LEVEL_0 + * @arg PGA_GAIN_LEVEL_1 + * @arg PGA_GAIN_LEVEL_2 + * @arg PGA_GAIN_LEVEL_3 + * @arg PGA_GAIN_LEVEL_4 + * @arg PGA_GAIN_LEVEL_5 + * @retval None + * @note Model configuration must follow the rules below: + * Inverting Adder Mode : The positive input must be grounded. + * The negative input must be voltage divider. + ************************************************************************************************************/ +void PGA_SetModeInvertingAdder(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_LEVEL_x)); + + PGA_InitStruct.PGA_REF = ENABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = ENABLE; + PGA_InitStruct.PGA_PGA = ENABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); + PGA_GainConfig(HT_PGAn, PGA_GAIN_LEVEL_x); +} + +/*********************************************************************************************************//** + * @brief Set the Exponent Amplifier Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_LEVEL_x: Where PGA_GAIN_LEVEL_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_LEVEL_0 + * @arg PGA_GAIN_LEVEL_1 + * @arg PGA_GAIN_LEVEL_2 + * @arg PGA_GAIN_LEVEL_3 + * @arg PGA_GAIN_LEVEL_4 + * @arg PGA_GAIN_LEVEL_5 + * @retval None + * @note Model configuration must follow the rules below: + * Exponent Amplifier Mode : The positive input must be grounded. + * The negative input must have an external diode. + ************************************************************************************************************/ +void PGA_SetModeExponent(HT_PGA0_X_TypeDef* HT_PGAn, u32 PGA_GAIN_LEVEL_x) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_LEVEL_x)); + + PGA_InitStruct.PGA_REF = ENABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = ENABLE; + PGA_InitStruct.PGA_PGA = ENABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); + PGA_GainConfig(HT_PGAn, PGA_GAIN_LEVEL_x); +} + +/*********************************************************************************************************//** + * @brief Set the Manual Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @retval None + * @note This mode prototype is a voltage follower, and the following modes can be used + * with external components: + * Peak Detector + * Active Filter + * R-2R D/A conversion circuit (+) + ************************************************************************************************************/ +void PGA_SetModeManual(HT_PGA0_X_TypeDef* HT_PGAn) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + + PGA_InitStruct.PGA_REF = ENABLE; + PGA_InitStruct.PGA_NUG = ENABLE; + PGA_InitStruct.PGA_NE = DISABLE; + PGA_InitStruct.PGA_PGA = DISABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); +} + +/*********************************************************************************************************//** + * @brief Set the Non-Inverting Adder Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @param PGA_GAIN_x: Where PGA_GAIN_x is the Gain for PGA resistor. + * This parameter can be one of the following values: + * @arg PGA_GAIN_6 + * @arg PGA_GAIN_8 + * @arg PGA_GAIN_12 + * @arg PGA_GAIN_16 + * @arg PGA_GAIN_24 + * @arg PGA_GAIN_32 + * @retval None + * @note Model configuration must follow the rules below: + * Non-Inverting Adder : The positive input must be voltage divider. + * The negative input must be grounded. + ************************************************************************************************************/ +void PGA_SetModeNonInvertingAdder(HT_PGA0_X_TypeDef* HT_PGAn, PGA_GAIN_TYPE1_Enum PGA_GAIN_x) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + Assert_Param(IS_PGA_GAIN(PGA_GAIN_x)); + + PGA_InitStruct.PGA_REF = DISABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = DISABLE; + PGA_InitStruct.PGA_PGA = ENABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); + PGA_GainConfig(HT_PGAn, PGA_GAIN_x); +} + +/*********************************************************************************************************//** + * @brief Set the Comparator Mode of the specified HT_PGAn. + * @param HT_PGAn: where HT_PGAn is the selected PGA from the PGA peripherals. + * @retval None + ************************************************************************************************************/ +void PGA_SetModeComparator(HT_PGA0_X_TypeDef* HT_PGAn) +{ + PGA_InitTypeDef PGA_InitStruct; + + /* Check the parameters */ + Assert_Param(IS_PGA(HT_PGAn)); + + PGA_InitStruct.PGA_REF = DISABLE; + PGA_InitStruct.PGA_NUG = DISABLE; + PGA_InitStruct.PGA_NE = ENABLE; + PGA_InitStruct.PGA_PGA = DISABLE; + PGA_InitStruct.PGA_HVDDA = PGA_HVDDA_DISABLE; + + PGA_Init(HT_PGAn, &PGA_InitStruct); +} + +/** + * @} + */ /** * @} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c index 724e166fbe..ab3b316067 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f66xxx_cordic.c - * @version $Rev:: 6914 $ - * @date $Date:: 2023-05-10 #$ - * @brief This file provides all the CORDIC firmware functions. (temporary file, not finish/support yet). + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ + * @brief This file provides all the CORDIC firmware functions. ************************************************************************************************************* * @attention * @@ -38,7 +38,189 @@ */ +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CORDIC_Private_Define CORDIC private definitions + * @{ + */ +#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_ROTATIONMATRIX) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_INTEGERMODULUS) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_INTEGERSQUAREROOT)) +#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \ + ((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_15CYCLES)) + + +#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \ + ((__SCALE__) == CORDIC_SCALE_1) || \ + ((__SCALE__) == CORDIC_SCALE_2) || \ + ((__SCALE__) == CORDIC_SCALE_3) || \ + ((__SCALE__) == CORDIC_SCALE_4) || \ + ((__SCALE__) == CORDIC_SCALE_5) || \ + ((__SCALE__) == CORDIC_SCALE_6) || \ + ((__SCALE__) == CORDIC_SCALE_7)) + +#define IS_CORDIC_PDMA_REQ(REQ) (((REQ & 0xFFF9FFFF) == 0x0) && (REQ != 0x0)) + +#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \ + ((__NBWRITE__) == CORDIC_NBWRITE_2) || \ + ((__NBWRITE__) == CORDIC_NBWRITE_3)) + +#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \ + ((__NBREAD__) == CORDIC_NBREAD_2)) + +#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \ + ((__INSIZE__) == CORDIC_INSIZE_16BITS)) + +#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \ + ((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS)) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Functions CORDIC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CORDIC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void CORDIC_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.CORDIC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the CORDIC peripheral according to the specified parameters in the CORDIC_InitStruct. + * @param CORDIC_InitStruct: pointer to a CORDIC_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CORDIC_Init(CORDIC_InitTypeDef *CORDIC_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CORDIC_FUNCTION(CORDIC_InitStruct->Function)); + Assert_Param(IS_CORDIC_PRECISION(CORDIC_InitStruct->Precision)); + Assert_Param(IS_CORDIC_SCALE(CORDIC_InitStruct->Scale)); + Assert_Param(IS_CORDIC_NBWRITE(CORDIC_InitStruct->NbWrite)); + Assert_Param(IS_CORDIC_NBREAD(CORDIC_InitStruct->NbRead)); + Assert_Param(IS_CORDIC_INSIZE(CORDIC_InitStruct->InSize)); + Assert_Param(IS_CORDIC_OUTSIZE(CORDIC_InitStruct->OutSize)); + + HT_CORDIC->CSR &= ~(CORDIC_CSR_FUNC_MASK | CORDIC_CSR_PRECISION_MASK | CORDIC_CSR_SCALE_MASK | \ + CORDIC_CSR_NRES_MASK | CORDIC_CSR_NARGS_MASK | CORDIC_CSR_RESSIZE_MASK | CORDIC_CSR_ARGSIZE_MASK); + + HT_CORDIC->CSR |= (CORDIC_InitStruct->Function | CORDIC_InitStruct->Precision | CORDIC_InitStruct->Scale | \ + CORDIC_InitStruct->NbWrite | CORDIC_InitStruct->NbRead | CORDIC_InitStruct->InSize | CORDIC_InitStruct->OutSize); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable CORDIC result ready interrupt. (RRDY) + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CORDIC_IntCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CORDIC->CSR |= CORDIC_CSR_IEN; + } + else + { + HT_CORDIC->CSR &= ~CORDIC_CSR_IEN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the CORDIC PDMA interface. + * @param CORDIC_DMA: specify the CORDIC PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CORDIC_DMA_REN: Read PDMA transfer request + * @arg CORDIC_DMA_WEN: Write PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CORDIC_PDMACmd(u32 CORDIC_DMA, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CORDIC_PDMA_REQ(CORDIC_DMA)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CORDIC->CSR |= CORDIC_DMA; + } + else + { + HT_CORDIC->CSR &= ~CORDIC_DMA; + } +} + +/*********************************************************************************************************//** + * @brief Check CORDIC result ready flag state. (RRDY) + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CORDIC_GetFlagStatus_RRDY(void) +{ + if ((HT_CORDIC->CSR & CORDIC_FLAG_RRDY) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Write 32-bit input data for the CORDIC processing. + * @param InData: 32-bit value to be provided as input data for CORDIC processing. + * @retval None + ************************************************************************************************************/ +void CORDIC_WriteData(u32 InData) +{ + HT_CORDIC->WDATA = InData; +} + +/*********************************************************************************************************//** + * @brief Return 32-bit output data of CORDIC processing. + * @retval 32-bit output data of CORDIC processing. + ************************************************************************************************************/ +u32 CORDIC_ReadData(void) +{ + return (u32)HT_CORDIC->RDATA; +} +/** + * @} + */ /** * @} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c index d956f5fcf9..ad68960888 100644 --- a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c @@ -1,8 +1,8 @@ /*********************************************************************************************************//** * @file ht32f66xxx_pid.c - * @version $Rev:: 6914 $ - * @date $Date:: 2023-05-10 #$ - * @brief This file provides all the PID firmware functions. (temporary file, not finish/support yet). + * @version $Rev:: 8260 $ + * @date $Date:: 2024-11-05 #$ + * @brief This file provides all the PID firmware functions. ************************************************************************************************************* * @attention * @@ -37,8 +37,301 @@ * @{ */ +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup PID_Exported_Functions PID exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_PIDn peripheral registers to their default reset values. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @retval None + ************************************************************************************************************/ +void PID_DeInit(HT_PID_TypeDef* HT_PIDn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + if (HT_PIDn == HT_PID0) + { + RSTCUReset.Bit.PID0 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the HT_PIDn PID_Mode peripheral according to the specified parameters in the PID_InitTypeDef. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_Mode: where PID_Mode is the selected PID mode. + * This parameter can be one of the following values: + * @arg PID_SPD_MODE + * @arg PID_IQ_MODE + * @arg PID_ID_MODE + * @arg PID_FWNK_MODE + * @arg PID_PLL_MODE + * @arg PID_USR_MODE + * @param PID_Para: where PID_Para is PID paramater structure. + * @retval None + ************************************************************************************************************/ +void PID_Init(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode, PID_InitTypeDef* PID_Para) +{ + HT_PIDPARA_TypeDef * gPID_ModePara = &(HT_PIDn->SPD); + + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_MODE(PID_Mode)); + + (gPID_ModePara + PID_Mode)->KPIR = PID_Para->KP; + (gPID_ModePara + PID_Mode)->KIIR = PID_Para->KI; + (gPID_ModePara + PID_Mode)->KDIR = PID_Para->KD; + (gPID_ModePara + PID_Mode)->IFVMAXLR = PID_Para->UI_MAX; + (gPID_ModePara + PID_Mode)->IFVMINLR = PID_Para->UI_MIN; + (gPID_ModePara + PID_Mode)->PIDORLR = (u32)((PID_Para->OUT_MAX << 16) | ((u16)PID_Para->OUT_MIN)); + (gPID_ModePara + PID_Mode)->LEIR = PID_Para->ERRn_1; + (gPID_ModePara + PID_Mode)->LIFVR = PID_Para->UIn_1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PID interrupts. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_INT_x: Specify the PID interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg PID_INT_CMP : + * @arg PID_INT_OVF : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PID_IntConfig(HT_PID_TypeDef* HT_PIDn, u32 PID_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_INT(PID_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_PIDn->CR |= PID_INT_x; + } + else + { + HT_PIDn->CR &= ~PID_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified PID interrupt has occurred. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_INT_x: Specify the PID interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg PID_INT_CMP : + * @arg PID_INT_OVF : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PID_GetIntStatus(HT_PID_TypeDef* HT_PIDn, u32 PID_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_INT(PID_INT_x)); + + if ((HT_PIDn->CR & (PID_INT_x << PID_INT_Status_Pos)) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the PID interrupt pending bits. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_INT_x: Specify the PID interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg PID_INT_CMP : + * @arg PID_INT_OVF : + * @retval None + ************************************************************************************************************/ +void PID_ClearIntPendingBit(HT_PID_TypeDef* HT_PIDn, u32 PID_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_INT(PID_INT_x)); + + HT_PIDn->CR |= (PID_INT_x << PID_INT_Clear_Pos); +} + +/*********************************************************************************************************//** + * @brief Set the PID ERR(n) value of the common parameters. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param ERRn: where ERRn is PID Controller Error Input Value. + * @retval None + ************************************************************************************************************/ +void PID_SetComPara_ERRn(HT_PID_TypeDef* HT_PIDn, s32 ERRn) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + + HT_PIDn->EIVR = ERRn; +} + +/*********************************************************************************************************//** + * @brief Set the PID UI_input(n) value of the common parameters. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param UI_Input: where UI_Input is PID Controller integrator accumulation selection. + * @retval None + ************************************************************************************************************/ +void PID_SetComPara_UI_Input(HT_PID_TypeDef* HT_PIDn, s32 UI_Input) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + + HT_PIDn->IFIVR = UI_Input; +} + +/*********************************************************************************************************//** + * @brief Enable compute the PID calculation. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_Mode: where PID_Mode is the selected PID mode. + * This parameter can be one of the following values: + * @arg PID_SPD_MODE + * @arg PID_IQ_MODE + * @arg PID_ID_MODE + * @arg PID_FWNK_MODE + * @arg PID_PLL_MODE + * @arg PID_USR_MODE + * @retval None + ************************************************************************************************************/ +void PID_Compute(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_MODE(PID_Mode)); + + HT_PIDn->CR &= ~(u32)PID_CR_MODSEL_Msk; + HT_PIDn->CR |= (PID_Mode << PID_CR_MODSEL_Pos) | (PID_CR_PIDEN); +} + +/*********************************************************************************************************//** + * @brief Return the PID ouput result value. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @retval The Value of PID result. + ************************************************************************************************************/ +s16 PID_GetOutResult(HT_PID_TypeDef* HT_PIDn) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + + return HT_PIDn->ORR; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified PID flag has been set. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg PID_FLAG_CMP : + * @arg PID_FLAG_OVF : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PID_GetFlagStatus(HT_PID_TypeDef* HT_PIDn, u32 PID_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_FLAG(PID_FLAG_x)); + + if ((HT_PIDn->CR & PID_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the integrator accumulation value set by UI_input(n). + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PID_UI_InputCmd(HT_PID_TypeDef* HT_PIDn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_PIDn->CR |= PID_CR_UIF; + } + else + { + HT_PIDn->CR &= ~(u32)PID_CR_UIF; + } +} + +/*********************************************************************************************************//** + * @brief Return the PID last error input value (ERRn_1) for the selected PID mode. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_Mode: where PID_Mode is the selected PID mode. + * This parameter can be one of the following values: + * @arg PID_SPD_MODE + * @arg PID_IQ_MODE + * @arg PID_ID_MODE + * @arg PID_FWNK_MODE + * @arg PID_PLL_MODE + * @arg PID_USR_MODE + * @retval The Value of ERRn_1 for the selected PID mode. + ************************************************************************************************************/ +s32 PID_GetERRn_1(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode) +{ + HT_PIDPARA_TypeDef * gPID_ModePara = &(HT_PIDn->SPD); + + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_MODE(PID_Mode)); + + return (gPID_ModePara + PID_Mode)->LEIR; +} + +/*********************************************************************************************************//** + * @brief Return the PID last integral function value (UIn_1) for the selected PID mode. + * @param HT_PIDn: where HT_PIDn is the selected PID from the PID peripherals. + * @param PID_Mode: where PID_Mode is the selected PID mode. + * This parameter can be one of the following values: + * @arg PID_SPD_MODE + * @arg PID_IQ_MODE + * @arg PID_ID_MODE + * @arg PID_FWNK_MODE + * @arg PID_PLL_MODE + * @arg PID_USR_MODE + * @retval The Value of UIn_1 for the selected PID mode. + ************************************************************************************************************/ +s32 PID_GetUIn_1(HT_PID_TypeDef* HT_PIDn, PID_Mode_Enum PID_Mode) +{ + HT_PIDPARA_TypeDef * gPID_ModePara = &(HT_PIDn->SPD); + + /* Check the parameters */ + Assert_Param(IS_PID(HT_PIDn)); + Assert_Param(IS_PID_MODE(PID_Mode)); + return (gPID_ModePara + PID_Mode)->LIFVR; +} + +/** + * @} + */ /** * @} diff --git a/bsp/ht32/libraries/ht32_drivers/SConscript b/bsp/ht32/libraries/ht32_drivers/SConscript index f3c00c8aab..86ba719ad9 100644 --- a/bsp/ht32/libraries/ht32_drivers/SConscript +++ b/bsp/ht32/libraries/ht32_drivers/SConscript @@ -34,6 +34,15 @@ if GetDepend(['BSP_USING_ADC']): if GetDepend(['BSP_USING_WDT']): src += ['drv_wdt.c'] + +if GetDepend(['BSP_USING_CAN']): + src += ['drv_can.c'] + +if GetDepend(['BSP_USING_SDIO']): + src += ['drv_sdio.c'] + +if GetDepend(['BSP_USING_USBD']): + src += ['drv_usbd.c'] #创建一个列表，用于保存需要包含的H文件路径 path = [cwd] diff --git a/bsp/ht32/libraries/ht32_drivers/cpuport.h b/bsp/ht32/libraries/ht32_drivers/cpuport.h new file mode 100644 index 0000000000..05bb12cf2f --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/cpuport.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#ifdef RT_USING_SMP +typedef union { + unsigned long slock; + struct __arch_tickets { + unsigned short owner; + unsigned short next; + } tickets; +} rt_hw_spinlock_t; +#endif + +#endif /*CPUPORT_H__*/ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_can.c b/bsp/ht32/libraries/ht32_drivers/drv_can.c new file mode 100644 index 0000000000..2c6db98f73 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_can.c @@ -0,0 +1,673 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-22 QT-one first version + */ + +#include +#include "drv_can.h" +#include "ht32_can_config.h" + +#ifdef BSP_USING_CAN +#if !defined(BSP_USING_CAN) + #error "Please define at least one BSP_USING_CAN" +#endif + +#define CAN_UMASK_MODE 0 +#define CAN_MASK_MODE 1 + +struct ht32_can_msg_type +{ + CAN_MSG_TypeDef cfg_msg; + uint32_t data_len; + uint8_t data[8]; +}; + +/* Baud rate mapping structure */ +struct ht32_baud_rate +{ + enum CANBAUD rt_baud_rate; + uint32_t us_baus_rate; +}; +/* CAN Filter Table Configuration Structure */ +struct ht32_can_filter_config +{ + /* Each bit represents a message;1: the message is occupied;0: the message is not occupied */ + uint32_t filter_flag; + /* Filter table configuration information */ + CAN_MSG_TypeDef filter_mag[MSG_OBJ_TOTAL_NUM]; +}; +/* CAN Object Structures */ +struct ht32_can +{ + char *name; /* Equipment name */ + HT_CAN_TypeDef *can_x; /* peripheral base address */ + struct can_configure cfg; /* CAN Configuration Structure */ + struct rt_can_device device; /* Inherited device options */ + struct ht32_can_filter_config filter_cfg; /* Filter Table Configuration */ +}; +/* CAN Baud Rate Mapping Table */ +static const struct ht32_baud_rate can_baud_rate_tab[] = +{ + {CAN1MBaud, 1000000}, + {CAN800kBaud, 800000}, + {CAN500kBaud, 500000}, + {CAN250kBaud, 250000}, + {CAN125kBaud, 125000}, + {CAN100kBaud, 100000}, + {CAN50kBaud, 50000}, + {CAN20kBaud, 20000}, + {CAN10kBaud, 10000}, +}; +/* CAN Object Information */ +static struct ht32_can ht32_can_config = +{ + .name = BSP_USING_CAN_NAME, + .can_x = HT_CAN0, + .cfg = {0}, + .device = RT_NULL, + .filter_cfg = {0}, +}; +/** + * @brief Default Filter Table Configuration + * @param can_instance:CAN object + * @retval + */ +static rt_uint32_t cfg_can_default_filter(struct ht32_can *can_instance) +{ + uint8_t filter_num = BSP_USING_CAN_MSG_NUM; + can_instance->filter_cfg.filter_flag |= 1 << filter_num; + can_instance->filter_cfg.filter_mag[filter_num].MsgNum = filter_num + 1; + can_instance->filter_cfg.filter_mag[filter_num].IdType = (CAN_IdType_Enum)BSP_USING_CAN_ID_MODE; + can_instance->filter_cfg.filter_mag[filter_num].IdMask = BSP_USING_CAN_MASK; + can_instance->filter_cfg.filter_mag[filter_num].FrameType = (CAN_FrameType_Enum)BSP_USING_CAN_FRAME_MODE; + can_instance->filter_cfg.filter_mag[filter_num].Id = BSP_USING_CAN_ID; + CAN_SetRxMsg(can_instance->can_x, &can_instance->filter_cfg.filter_mag[filter_num], 1); + return RT_EOK; +} +/** + * @brief Get baud rate mapping parameters for CAN + * @info This function is mainly used to convert the baud rate of RTT format to HT32 format baud rate + * @param baud:CAN baud rate in RTT format + * @retval Returns the CAN baud rate in HT32 format. + */ +static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +{ + rt_uint32_t len, index; + + len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + for (index = 0; index < len; index++) + { + if (can_baud_rate_tab[index].rt_baud_rate == baud) + return can_baud_rate_tab[index].us_baus_rate; + } + return 0; +} +/** + * @brief Configuring CAN Structures + * @info This function depends on the ht32_can_config.h file + * @param can_ck:System clock for CAN + * @param can_buad:CAN baud rate to be configured + * @param mode:Modes of CAN + * @param nart:enable or disable the no automatic retransmission + * @param CAN_InitStruct:Structures to be configured + * @retval 1:success;0:error + */ +static rt_uint32_t config_can_struct(uint32_t can_ck, + uint32_t can_buad, + uint8_t mode, + ControlStatus nart, + CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t cf0_nbt = 0; + uint32_t nominal_bit_time = 0; + + for (cf0_nbt = 25; cf0_nbt > 8; cf0_nbt--) + { + if ((can_ck / can_buad / cf0_nbt) > 0) + { + if (((can_ck / (can_ck / can_buad / cf0_nbt)) / cf0_nbt) <= can_buad) + { + nominal_bit_time = cf0_nbt; + break; + } + } + } + if (cf0_nbt < 8) + { + return 0; + } + CAN_InitStruct->CAN_BRPrescaler = (can_ck / (can_buad * nominal_bit_time)); + CAN_InitStruct->CAN_SJW = HTCFG_CAN_CF0_BIT_TIME_SJW; + CAN_InitStruct->CAN_TSEG1 = (nominal_bit_time - (nominal_bit_time * HTCFG_CAN_CF0_SAMPLE_POINT) / 100); + CAN_InitStruct->CAN_TSEG0 = (nominal_bit_time - 1 - CAN_InitStruct->CAN_TSEG1); + CAN_InitStruct->CAN_NART = nart; + CAN_InitStruct->CAN_Mode = mode; + return 1; +} +/** + * @brief CAN Configuration Functions + * @param + * @retval + */ +static rt_err_t ht32_can_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + struct ht32_can *can_instance = RT_NULL; + rt_uint32_t can_baud = 0; + rt_uint8_t can_mode = 0; + CAN_InitTypeDef CAN_InitStruct = {0}; + + RT_ASSERT(can); + RT_ASSERT(cfg); + can_instance = (struct ht32_can *)can->parent.user_data; + RT_ASSERT(can_instance != RT_NULL); + + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.CAN0 = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + ht32_can_gpio_init(can_instance->can_x); + + /* Get baud rate */ + can_baud = get_can_baud_index(cfg->baud_rate); + if (can_baud == 0) + { + return -RT_ERROR; + } + + can_instance->cfg.baud_rate = cfg->baud_rate; + can_instance->cfg.mode = cfg->mode; + + /* Configuring the operating mode of CAN */ + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + can_mode = CAN_MODE_NORMAL; + break; + case RT_CAN_MODE_LISTEN: + can_mode = CAN_MODE_SILENT; + break; + case RT_CAN_MODE_LOOPBACK: + can_mode = CAN_MODE_LBACK; + break; + case RT_CAN_MODE_LOOPBACKANLISTEN: + can_mode = CAN_MODE_SILENT | CAN_MODE_LBACK; + break; + default: + return -RT_ERROR; + } + + if (0 == (config_can_struct(_HTCFG_CF0_CK_CAN, can_baud, can_mode, DISABLE, &CAN_InitStruct))) + { + return -RT_ERROR; + } + /* Reset CAN */ + CAN_DeInit(can_instance->can_x); + /* Initialising CAN */ + CAN_Init(can_instance->can_x, &CAN_InitStruct); + + /* Configuring the Default Filter for CAN */ + cfg_can_default_filter(can_instance); + + return RT_EOK; +} +/** + * @brief CAN Control Functions + * @param + * @retval + */ +rt_err_t ht32_can_control(struct rt_can_device *can, int cmd, void *arg) +{ + rt_uint32_t argval; + struct ht32_can *can_instance; + struct rt_can_filter_config *filter_cfg; + + RT_ASSERT(can != RT_NULL); + can_instance = (struct ht32_can *)can->parent.user_data; + RT_ASSERT(can_instance != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT:/* Clear Interrupt */ + { + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) /* receive interruptions */ + { + if (CAN_GetFlagStatus(can_instance->can_x, CAN_FLAG_RXOK)) + { + /* Clear RXOK Flag */ + CAN_ClearFlag(can_instance->can_x, CAN_FLAG_RXOK); + } + } + else if (argval == RT_DEVICE_FLAG_INT_TX) /* Send Interrupt */ + { + if (CAN_GetFlagStatus(can_instance->can_x, CAN_FLAG_TXOK)) + { + /* Clear TXOK flag*/ + CAN_ClearFlag(can_instance->can_x, CAN_FLAG_TXOK); + } + } + else if (argval == RT_DEVICE_CAN_INT_ERR) /* false interruption */ + { + /* Error Process*/ + CAN_LastErrorCode_TypeDef lec = CAN_GetLastErrorCode(can_instance->can_x); + if (lec != NO_ERROR) + { + LOG_W("LEC: %d\r\n", lec); + } + if (CAN_GetFlagStatus(can_instance->can_x, CAN_FLAG_BOFF)) + { + /* Recover from Bus off state.*/ + CAN_BusOffRecovery(can_instance->can_x); + } + } + break; + } + case RT_DEVICE_CTRL_SET_INT:/* Setting Up Interruptions */ + { + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) /* interrupt receive mode */ + { + LOG_W("Configuring Receive Interrupts!\r\n"); + CAN_IntConfig(can_instance->can_x, CAN_INT_EIE | CAN_INT_SIE | CAN_INT_IE, ENABLE); + NVIC_EnableIRQ(CAN0_IRQn); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) /* interrupt transmission mode */ + { + LOG_W("Configuring Transmit Interrupts!\r\n"); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) /* false interruption */ + { + LOG_W("Configuration error interrupt!\r\n"); + } + break; + } + case RT_CAN_CMD_SET_FILTER:/* Configuring the Hardware Filter Table */ + { + int i = 0; + uint8_t filter_num = 0; + uint32_t idmask = 0; + if (RT_NULL == arg) + { + /* default filter config */ + cfg_can_default_filter(can_instance); + } + else + { + filter_cfg = (struct rt_can_filter_config *)arg; + if (filter_cfg->count > MSG_OBJ_TOTAL_NUM) + { + LOG_W("Filter list length exceeds the limit(max 32)!"); + return -RT_ERROR; + } + for (i = 0; i < filter_cfg->count; i++) + { + /* Specify the filter table number or no */ + if (filter_cfg->items[i].hdr_bank == -1) + { + filter_num = i; + } + else + { + if (filter_cfg->items[i].hdr_bank > MSG_OBJ_TOTAL_NUM) + { + LOG_W("Filter List Number Out of Limits(1-32)!"); + return -RT_ERROR; + } + else + { + filter_num = filter_cfg->items[i].hdr_bank; + } + } + if (can_instance->filter_cfg.filter_flag & (1 << filter_num)) + { + LOG_W("This filter channel will be changed(num:%d)!", filter_num); + rt_kprintf("This filter channel will be changed(num:%d)!", filter_num); + } + can_instance->filter_cfg.filter_flag |= 1 << filter_num; + can_instance->filter_cfg.filter_mag[filter_num].MsgNum = filter_num + 1; + + /* Standard or Extended Frames */ + if (filter_cfg->items[i].ide == RT_CAN_STDID) + { + can_instance->filter_cfg.filter_mag[filter_num].IdType = CAN_STD_ID; + idmask = 0x7FF; + } + else if (filter_cfg->items[i].ide == RT_CAN_EXTID) + { + can_instance->filter_cfg.filter_mag[filter_num].IdType = CAN_EXT_ID; + idmask = 0x1FFFFFFF; + } + else + { + LOG_W("Frame pattern error(CAN_STD_ID/CAN_EXT_ID)!"); + return -RT_ERROR; + } + /* Whether to use MASK mode */ + if (filter_cfg->items[i].mode == CAN_UMASK_MODE) + { + can_instance->filter_cfg.filter_mag[filter_num].IdMask = idmask; + } + else if (filter_cfg->items[i].mode == CAN_MASK_MODE) + { + can_instance->filter_cfg.filter_mag[filter_num].IdMask = filter_cfg->items[i].mask; + } + else + { + LOG_W("MASK mode error(CAN_UMASK_MODE/CAN_MASK_MODE)!"); + return -RT_ERROR; + } + + /* Remote frames or data frames */ + if (filter_cfg->items[i].rtr == RT_CAN_RTR) + { + can_instance->filter_cfg.filter_mag[filter_num].FrameType = CAN_REMOTE_FRAME; + } + else if (filter_cfg->items[i].rtr == RT_CAN_DTR) + { + can_instance->filter_cfg.filter_mag[filter_num].FrameType = CAN_DATA_FRAME; + } + /* Setting ID */ + can_instance->filter_cfg.filter_mag[filter_num].Id = filter_cfg->items[i].id; + /* Setting up the CAN filter table */ + CAN_SetRxMsg(can_instance->can_x, &can_instance->filter_cfg.filter_mag[filter_num], 1); + } + } + break; + } + case RT_CAN_CMD_SET_BAUD:/* Setting the baud rate */ + { + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + if (argval != can_instance->cfg.baud_rate) + { + can_instance->cfg.baud_rate = argval; + return ht32_can_configure(&can_instance->device, &can_instance->cfg); + } + break; + } + case RT_CAN_CMD_SET_MODE:/* Setting the CAN Operating Mode */ + { + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISTEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISTEN) + { + return -RT_ERROR; + } + if (argval != can_instance->cfg.mode) + { + can_instance->cfg.mode = argval; + return ht32_can_configure(&can_instance->device, &can_instance->cfg); + } + break; + } + case RT_CAN_CMD_GET_STATUS:/* Get CAN device status */ + { + rt_uint32_t errtype; + + errtype = can_instance->can_x->ECR; + can_instance->device.status.rcverrcnt = ((errtype >> 8) & 0x7f); + can_instance->device.status.snderrcnt = (errtype & 0xff); + + errtype = can_instance->can_x->SR; + can_instance->device.status.lasterrtype = (errtype & 0x07); + can_instance->device.status.errcode = ((errtype >> 5) & 0x07); + + rt_memcpy(arg, &can_instance->device.status, sizeof(can_instance->device.status)); + break; + } + default: + return -RT_ERROR; + } + return RT_EOK; +} +/** + * @brief CAN sends data + * @param + * @retval + */ +rt_ssize_t ht32_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + struct ht32_can *can_instance = RT_NULL; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + struct ht32_can_msg_type tx_msg = {0}; + + RT_ASSERT(can != RT_NULL); + can_instance = (struct ht32_can *)can->parent.user_data; + RT_ASSERT(can_instance != RT_NULL); + + /* Standard and Extended Frames */ + if (CAN_STD_ID == pmsg->ide) + { + tx_msg.cfg_msg.IdType = CAN_STD_ID; + tx_msg.cfg_msg.Id = pmsg->id; + } + else if (CAN_EXT_ID == pmsg->ide) + { + tx_msg.cfg_msg.IdType = CAN_EXT_ID; + tx_msg.cfg_msg.Id = pmsg->id; + } + else + { + LOG_W("Frame pattern error(CAN_STD_ID/CAN_EXT_ID)!"); + return -RT_ERROR; + } + + /* Teleframes and data frames */ + if (RT_CAN_RTR == pmsg->rtr) + { + tx_msg.cfg_msg.FrameType = CAN_REMOTE_FRAME; + } + else if (RT_CAN_DTR == pmsg->rtr) + { + tx_msg.cfg_msg.FrameType = CAN_DATA_FRAME; + } + else + { + LOG_W("Remote frame setting error(CAN_REMOTE_FRAME/CAN_DATA_FRAME)!"); + return -RT_ERROR; + } + + /* Length of sent data */ + tx_msg.data_len = pmsg->len & 0x0FU; + /* data being sent */ + tx_msg.data[0] = pmsg->data[0]; + tx_msg.data[1] = pmsg->data[1]; + tx_msg.data[2] = pmsg->data[2]; + tx_msg.data[3] = pmsg->data[3]; + tx_msg.data[4] = pmsg->data[4]; + tx_msg.data[5] = pmsg->data[5]; + tx_msg.data[6] = pmsg->data[6]; + tx_msg.data[7] = pmsg->data[7]; + + /* Waiting tx Msg idle */ + while (CAN_TransmitStatus(can_instance->can_x, &tx_msg.cfg_msg) == 0); + /* Loopback data */ + CAN_Transmit(can_instance->can_x, &tx_msg.cfg_msg, tx_msg.data, tx_msg.data_len); + + return RT_EOK; +} +/** + * @brief CAN receive data + * @param + * @retval + */ +rt_ssize_t ht32_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + uint8_t i = 0; + uint32_t msgnum = 0; + CAN_RxStatus_TypeDef rx_status; + struct ht32_can_msg_type rx_msg = {0}; + struct ht32_can *can_instance = RT_NULL; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + + RT_ASSERT(can != RT_NULL); + RT_ASSERT(pmsg != RT_NULL); + can_instance = (struct ht32_can *)can->parent.user_data; + RT_ASSERT(can_instance != RT_NULL); + + msgnum = can_instance->filter_cfg.filter_flag; + for (i = 0; i < MSG_OBJ_TOTAL_NUM; i++) + { + if ((msgnum & 1) == 1) + { + rx_status = CAN_Receive(can_instance->can_x, &can_instance->filter_cfg.filter_mag[i], rx_msg.data, &rx_msg.data_len); + if (rx_status == MSG_OVER_RUN) + { + LOG_W("ID[%X] rx message over run\r\n", can_instance->filter_cfg.filter_mag[i].Id); + } + else if (rx_status == MSG_OBJ_NOT_SET) + { + LOG_W("rx message not set \r\n"); + } + else if (rx_status == MSG_RX_FINISH) + { + LOG_W("rx ok \r\n"); + pmsg->data[0] = rx_msg.data[0]; + pmsg->data[1] = rx_msg.data[1]; + pmsg->data[2] = rx_msg.data[2]; + pmsg->data[3] = rx_msg.data[3]; + pmsg->data[4] = rx_msg.data[4]; + pmsg->data[5] = rx_msg.data[5]; + pmsg->data[6] = rx_msg.data[6]; + pmsg->data[7] = rx_msg.data[7]; + pmsg->len = rx_msg.data_len; + + if (can_instance->filter_cfg.filter_mag[i].IdType == CAN_EXT_ID) + { + pmsg->id = can_instance->filter_cfg.filter_mag[i].Id; + pmsg->ide = RT_CAN_EXTID; + } + else if (can_instance->filter_cfg.filter_mag[i].IdType == CAN_STD_ID) + { + pmsg->id = can_instance->filter_cfg.filter_mag[i].Id; + pmsg->ide = RT_CAN_EXTID; + } + + if (can_instance->filter_cfg.filter_mag[i].FrameType == CAN_DATA_FRAME) + { + pmsg->rtr = RT_CAN_DTR; + } + else if (can_instance->filter_cfg.filter_mag[i].FrameType == CAN_REMOTE_FRAME) + { + pmsg->rtr = RT_CAN_RTR; + } + return RT_EOK; + } + } + msgnum = msgnum >> 1; + if (msgnum == 0) + { + return -1; + } + } + return -1; +} +/* Mapping CAN interfaces */ +static const struct rt_can_ops ht32_can_ops = +{ + .configure = ht32_can_configure, /* CAN Configuration Functions */ + .control = ht32_can_control, /* CAN Control Functions */ + .sendmsg = ht32_can_sendmsg, /* CAN Transmit Data */ + .recvmsg = ht32_can_recvmsg, /* CAN Receive Data */ +}; + +int rt_hw_can_init(void) +{ + + struct can_configure config = CANDEFAULTCONFIG; + config.mode = BSP_USING_CAN_MODE; + config.baud_rate = BSP_USING_CAN_BAUD; + config.privmode = RT_CAN_MODE_NOPRIV; + config.ticks = 50; + +#ifdef RT_CAN_USING_HDR + config.maxhdr = 14; +#endif + ht32_can_config.device.config = config; + /* Registration of CAN devices */ + rt_hw_can_register(&ht32_can_config.device, + ht32_can_config.name, + &ht32_can_ops, + &ht32_can_config); + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_can_init); + +void CAN0_IRQHandler(void) +{ + CAN_LastErrorCode_TypeDef lec; + rt_interrupt_enter(); + /* Recover from Bus off state. */ + if (CAN_GetFlagStatus(ht32_can_config.can_x, CAN_FLAG_BOFF)) + { + CAN_BusOffRecovery(ht32_can_config.can_x); + } + /* Transmit message finished */ + if (CAN_GetFlagStatus(ht32_can_config.can_x, CAN_FLAG_TXOK)) + { + rt_hw_can_isr(&ht32_can_config.device, RT_CAN_EVENT_TX_DONE); + CAN_ClearFlag(ht32_can_config.can_x, CAN_FLAG_TXOK); + } + /* Message received. */ + if (CAN_GetFlagStatus(ht32_can_config.can_x, CAN_FLAG_RXOK)) + { + /* Clear all message objects' interrupt pending flag */ + CAN_ClearAllMsgPendingFlag(ht32_can_config.can_x); + rt_hw_can_isr(&ht32_can_config.device, RT_CAN_EVENT_RX_IND); + CAN_ClearFlag(ht32_can_config.can_x, CAN_FLAG_RXOK); + } + lec = CAN_GetLastErrorCode(ht32_can_config.can_x); + if (lec != NO_ERROR) + { + switch (lec) + { + case NO_ERROR: + break; + case STUFF_ERROR: + ht32_can_config.device.status.bitpaderrcnt++; + break; + case FORM_ERROR: + ht32_can_config.device.status.formaterrcnt++; + break; + case ACK_ERROR: + ht32_can_config.device.status.ackerrcnt++; + break; + case BIT1_EROR: + case BIT0_ERROR: + ht32_can_config.device.status.biterrcnt++; + break; + case CRC_ERROR: + ht32_can_config.device.status.crcerrcnt++; + break; + case NO_CHANGE: + break; + } + ht32_can_config.device.status.lasterrtype = lec; + ht32_can_config.device.status.rcverrcnt = CAN_GetReceiveErrorCounter(ht32_can_config.can_x); + ht32_can_config.device.status.snderrcnt = CAN_GetLSBTransmitErrorCounter(ht32_can_config.can_x); + ht32_can_config.device.status.errcode = lec; + } + + rt_interrupt_leave(); +} + +#endif /* BSP_USING_CAN */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_can.h b/bsp/ht32/libraries/ht32_drivers/drv_can.h new file mode 100644 index 0000000000..4b5c63cecf --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_can.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-22 QT-one first version + */ + +#ifndef __DRV_CAN_H__ +#define __DRV_CAN_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_CAN_H__ */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_common.c b/bsp/ht32/libraries/ht32_drivers/drv_common.c index 1bdb6a36e1..fe689d4728 100644 --- a/bsp/ht32/libraries/ht32_drivers/drv_common.c +++ b/bsp/ht32/libraries/ht32_drivers/drv_common.c @@ -27,7 +27,7 @@ MSH_CMD_EXPORT(reboot, Reboot System); void rt_hw_systick_init(void) { SYSTICK_ClockSourceConfig(SYSTICK_SRC_STCLK); - SYSTICK_SetReloadValue(SystemCoreClock / 8 / RT_TICK_PER_SECOND); + SYSTICK_SetReloadValue(SystemCoreClock / 10 / RT_TICK_PER_SECOND); SYSTICK_IntConfig(ENABLE); SYSTICK_CounterCmd(SYSTICK_COUNTER_CLEAR); SYSTICK_CounterCmd(SYSTICK_COUNTER_ENABLE); diff --git a/bsp/ht32/libraries/ht32_drivers/drv_sdio.c b/bsp/ht32/libraries/ht32_drivers/drv_sdio.c new file mode 100644 index 0000000000..d9ea9e6954 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_sdio.c @@ -0,0 +1,747 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-11-06 QT-one first version + */ + +#include +#include "drv_sdio.h" + +#ifdef BSP_USING_SDIO +#if !defined (BSP_USING_SDIO) + #error "Please define at least one SDIOx" +#endif + +#define RT_HW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RT_HW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_uint32_t (*sdio_clk_get)(HT_SDIO_TypeDef *hw_sdio); + +struct ht32_sdio_config +{ + SDIO_InitTypeDef sdio_cfg; /* SDIO Configuration Structure */ + PDMACH_InitTypeDef dma_tx_cfg; /* TX DMA Configuration Structure */ + PDMACH_InitTypeDef dma_rx_cfg; /* RX DMA Configuration Structure */ +}; + +struct ht32_sdio_des +{ + HT_SDIO_TypeDef *hw_sdio; /* Pointer to sdio hardware structure */ + dma_txconfig txconfig; /* Pointer to the configuration function for the TX DMA */ + dma_rxconfig rxconfig; /* Pointer to the configuration function for the RX DMA */ + sdio_clk_get clk_get; /* Pointer to get sdio clock function */ +}; + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; /* RTT-defined mmcsd command structure */ + void *buff; /* Pointer to hold data */ + SDIO_CmdInitTypeDef sdio_cmd_str; /* Send Command Configuration */ + SDIO_DataInitTypeDef sdio_dat_str; /* Send Data Configuration */ +}; + +struct rt_hw_sdio +{ + struct rt_mmcsd_host *host; /* mmcsd host structure */ + struct ht32_sdio_des sdio_des; /* Configuration information for sdio */ + struct rt_event dat_event; /* data event variable */ + struct rt_event cmd_event; /* command event variable */ + struct rt_mutex mutex; /* mutually exclusive variable */ + struct sdio_pkg *pkg; /* package structure */ +}; + +rt_align(SDIO_ALIGN_LEN) /* Ensure data alignment */ +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; /* Buff caches allocated to SDIOs */ + +static struct rt_mmcsd_host *host; +static struct ht32_sdio_config sdio_cfg; + +static void sdio_delay(rt_uint32_t ms) +{ + while (ms > 0) + ms--; +} + +static rt_uint32_t ht32_sdio_clk_get(HT_SDIO_TypeDef *hw_sdio) +{ + return SDIO_CLOCK_FREQ; +} +/** + * @brief this function transfer data by dma. + * @param sdio rt_hw_sdio + * @param pkg sdio package + * @retval none + */ +static void rt_hw_sdio_transfer_by_dma(struct rt_hw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_data *data; + void *buff; + HT_SDIO_TypeDef *hw_sdio; + if ((RT_NULL == pkg) || (RT_NULL == sdio)) + { + LOG_E("rt_hw_sdio_transfer_by_dma invalid args"); + return; + } + + data = pkg->cmd->data; + if (RT_NULL == data) + { + LOG_E("rt_hw_sdio_transfer_by_dma invalid args"); + return; + } + + buff = pkg->buff; + if (RT_NULL == buff) + { + LOG_E("rt_hw_sdio_transfer_by_dma invalid args"); + return; + } + + hw_sdio = sdio->sdio_des.hw_sdio; + if (data->flags & DATA_DIR_WRITE) + { + LOG_D("SDIO write!"); + sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->DR, (data->blks * data->blksize)); + } + else if (data->flags & DATA_DIR_READ) + { + LOG_D("SDIO read!"); + sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->DR, (rt_uint32_t *)buff, (data->blks * data->blksize)); + } +} +/** + * @brief this function send command. + * @param sdio rt_hw_sdio + * @param pkg sdio package + * @retval none + */ +static void rt_hw_sdio_send_command(struct rt_hw_sdio *sdio, struct sdio_pkg *pkg) +{ + rt_uint32_t status = 0; + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + HT_SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + + /* config cmd reg */ + pkg->sdio_cmd_str.SDIO_DatPresent = SDIO_Data_Present_No; + + /* config data reg */ + if (data != RT_NULL) + { + rt_uint32_t dir = 0; + dir = (data->flags & DATA_DIR_READ) ? SDIO_TransferDir_ToSDIO : SDIO_TransferDir_ToCard; + if (SDIO_TransferDir_ToSDIO == dir) /* read */ + SDIO_FlagConfig(SDIO_FLAG_BUF_OVERFLOW | SDIO_FLAG_DATA_CRCERR | SDIO_FLAG_DATA_TIMEOUT | SDIO_FLAG_TRANS_END, ENABLE); + else if (SDIO_TransferDir_ToCard == dir) /* write */ + SDIO_FlagConfig(SDIO_FLAG_BUF_UNDERFLOW | SDIO_FLAG_DATA_CRCERR | SDIO_FLAG_DATA_TIMEOUT | SDIO_FLAG_TRANS_END, ENABLE); + if (data->blksize > 2048) + LOG_E("Block length out of range!"); + pkg->sdio_dat_str.SDIO_DataBlockCount = data->blks; /* Specify the number of data blocks to be transferred 1~65535 */ + pkg->sdio_dat_str.SDIO_DataBlockSize = data->blksize; /* Specify the size of the data block to be transferred 1~2048 */ + pkg->sdio_dat_str.SDIO_DataTimeOut = HW_SDIO_DATATIMEOUT; /* Specify the data timeout period 0x1 ~ 0x00ffffff */ + pkg->sdio_dat_str.SDIO_TransferDir = dir; /* Specify the direction of data transmission r/w */ + if (data->blks > 1) + pkg->sdio_dat_str.SDIO_TransferMode = SDIO_MultiBlock_DMA_Transfer; /* multiblock transfer mode */ + else + pkg->sdio_dat_str.SDIO_TransferMode = SDIO_SingleBlock_DMA_Transfer; /* single-block transfer mode */ + SDIO_DataConfig(&pkg->sdio_dat_str); + + pkg->sdio_cmd_str.SDIO_DatPresent = SDIO_Data_Present_Yes; + + rt_hw_sdio_transfer_by_dma(sdio, pkg); + } + + /* Configuring Response Mode */ + if (resp_type(cmd) == RESP_NONE) + pkg->sdio_cmd_str.SDIO_Response = SDIO_Response_No; + else if (resp_type(cmd) == RESP_R2) + pkg->sdio_cmd_str.SDIO_Response = SDIO_Response_Long; + else + pkg->sdio_cmd_str.SDIO_Response = SDIO_Response_Short; + + if (resp_type(cmd) & (RESP_R1 | RESP_R6)) + pkg->sdio_cmd_str.SDIO_CmdIdxChk = SDIO_CmdIdxChk_Yes; + else + pkg->sdio_cmd_str.SDIO_CmdIdxChk = SDIO_Data_Present_No; + + if (resp_type(cmd) & (RESP_R3)) + pkg->sdio_cmd_str.SDIO_CmdCrcChk = SDIO_CmdCrcChk_No; + else + pkg->sdio_cmd_str.SDIO_CmdCrcChk = SDIO_CmdCrcChk_Yes; + /* send cmd */ + pkg->sdio_cmd_str.SDIO_Argument = cmd->arg; /* sdio Command Parameters */ + pkg->sdio_cmd_str.SDIO_CmdIndex = (cmd->cmd_code << 8); /* Index of sdio commands 0x01 ~ 0x40*/ + /* open irq */ + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, ENABLE); + SDIO_IntConfig(HW_SDIO_CMD_FLAG, ENABLE); + SDIO_SendCommand(&pkg->sdio_cmd_str); + /* wait completed */ + if (rt_event_recv(&sdio->cmd_event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + SDIO_IntConfig(HW_SDIO_CMD_FLAG, DISABLE); + if (cmd->err != RT_EOK) + LOG_D("cmd err!"); + + /* waiting for data to be sent to completion */ + if (data != RT_NULL) + { + status = 0; + SDIO_IntConfig(SDIO_INT_BUF_OVERFLOW | SDIO_INT_DATA_CRCERR | SDIO_INT_DATA_TIMEOUT | SDIO_INT_TRANS_END, ENABLE); + if (rt_event_recv(&sdio->dat_event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + data->err = -RT_ETIMEOUT; + return; + } + SDIO_IntConfig(SDIO_INT_BUF_OVERFLOW | SDIO_INT_DATA_CRCERR | SDIO_INT_DATA_TIMEOUT | SDIO_INT_TRANS_END, DISABLE); + if (data->err != RT_EOK) + LOG_D("data err!"); + } + /* close irq, keep sdio irq */ + hw_sdio->IER = 0x00; + /* clear pkg */ + sdio->pkg = RT_NULL; +} +/** + * @brief this function send sdio request. + * @param sdio rt_hw_sdio + * @param req request + * @retval none + */ +static void rt_hw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rt_hw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RT_HW_SDIO_LOCK(sdio); + /* Send commands and data */ + if (req->cmd != RT_NULL) + { + memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + RT_ASSERT(size <= SDIO_BUFF_SIZE); + pkg.buff = data->buf; + if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) + { + pkg.buff = cache_buf; + if (data->flags & DATA_DIR_WRITE) + { + memcpy(cache_buf, data->buf, size); + } + } + } + rt_hw_sdio_send_command(sdio, &pkg); + if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) + { + memcpy(data->buf, cache_buf, data->blksize * data->blks); + } + } + /* Send stop command */ + if (req->stop != RT_NULL) + { + memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rt_hw_sdio_send_command(sdio, &pkg); + } + RT_HW_SDIO_UNLOCK(sdio); + mmcsd_req_complete(sdio->host); +} +/** + * @brief this function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval none + */ +static void rt_hw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rt_hw_sdio *sdio = host->private_data; + /* SDIO Clock Acquisition and Limiting */ + clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); + if (clk_src < 400 * 1000) + { + LOG_E("Chip clock frequency too low! fre:%d", clk_src); + return; + } + if (clk > host->freq_max) clk = host->freq_max; + if (clk > clk_src) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = clk_src; + } + + LOG_D("clk:%d width:%s%s%s power:%s%s%s", + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "" + ); + + RT_HW_SDIO_LOCK(sdio); + /* SDIO Clock Division Configuration */ + div = clk_src / clk; + if ((clk == 0) || (div == 0)) + { + div = 1; + } + else + { + if (div < 1) + { + div = 1; + } + else if (div > 0xff) + { + div = 0xff; + } + } + sdio_cfg.sdio_cfg.SDIO_ClockDiv = div; + if (div % 2) + sdio_cfg.sdio_cfg.SDIO_ClockPeriod = SDIO_Clock_LowPeriod_Longer; + else + sdio_cfg.sdio_cfg.SDIO_ClockPeriod = SDIO_Clock_LowPeriod_Shorter; + + /* Data bus mode configuration */ + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + LOG_E("8-bit data width not supported!"); + return; + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + sdio_cfg.sdio_cfg.SDIO_BusWide = SDIO_BusWide_4b; + sdio_cfg.sdio_cfg.SDIO_BusMode = SDIO_BusMode_HighSpeed; + } + else + { + sdio_cfg.sdio_cfg.SDIO_BusWide = SDIO_BusWide_1b; + sdio_cfg.sdio_cfg.SDIO_BusMode = SDIO_BusMode_NormalSpeed; + } + /* Power Mode Configuration */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + sdio_cfg.sdio_cfg.SDIO_ClockPowerSave = SDIO_Clock_PowerSave_Disable; + break; + case MMCSD_POWER_UP: + sdio_cfg.sdio_cfg.SDIO_ClockPowerSave = SDIO_Clock_PowerSave_StopHigh; + break; + case MMCSD_POWER_ON: + sdio_cfg.sdio_cfg.SDIO_ClockPowerSave = SDIO_Clock_PowerSave_StopLow; + break; + default: + LOG_W("unknown power_mode %d", io_cfg->power_mode); + break; + } + SDIO_Init(&sdio_cfg.sdio_cfg); + RT_HW_SDIO_UNLOCK(sdio); +} +/** + * @brief this function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval none + */ +void rt_hw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + if (enable) + { + LOG_D("enable sdio irq"); + NVIC_EnableIRQ(SDIO_IRQn); + } + else + { + LOG_D("disable sdio irq"); + NVIC_DisableIRQ(SDIO_IRQn); + } +} +/** + * @brief this function delect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rt_hw_sd_delect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} +/** + * @brief this function interrupt process function. + * @param host rt_mmcsd_host + * @retval none + */ +void rt_hw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + rt_uint8_t cmd_flag = 0; + rt_uint8_t data_flag = 0; + struct rt_hw_sdio *sdio = host->private_data; + HT_SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->SR; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + if (sdio->pkg == NULL) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(HW_SDIO_CMD_FLAG); + SDIO_FlagConfig(HW_SDIO_DATA_FLAG, DISABLE); + SDIO_ClearFlag(HW_SDIO_DATA_FLAG); + return; + } + /* Command Response Processing */ + if (cmd != NULL) + { + if (intstatus != 0x00000001) + sdio_delay(10000); + cmd->resp[0] = hw_sdio->RESP0; + cmd->resp[1] = hw_sdio->RESP1; + cmd->resp[2] = hw_sdio->RESP2; + cmd->resp[3] = hw_sdio->RESP3; + cmd->err = RT_EOK; + if (SDIO_GetFlagStatus(SDIO_FLAG_CMD_SEND)) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_CMD_SEND); + cmd_flag = 1; + } + if (SDIO_GetFlagStatus(SDIO_FLAG_CMD_TIMEOUT)) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_CMD_TIMEOUT); + RESET_CPSM(); + cmd->err = -RT_ETIMEOUT; + cmd_flag = 1; + } + if ((SDIO_GetFlagStatus(SDIO_FLAG_CMD_CRCERR)) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_CMD_CRCERR); + cmd->err = RT_EOK; + cmd_flag = 1; + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_CMD_CRCERR)) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_CMD_CRCERR); + cmd->err = -RT_ERROR; + cmd_flag = 1; + } + if ((SDIO_GetFlagStatus(SDIO_FLAG_CMD_IDXERR)) && (resp_type(cmd) & (RESP_R1 | RESP_R6)) && (cmd->err == RT_EOK)) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_CMD_IDXERR); + cmd->err = RT_EOK; + cmd_flag = 1; + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_CMD_IDXERR)) + { + SDIO_FlagConfig(HW_SDIO_CMD_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_CMD_IDXERR); + cmd->err = -RT_ERROR; + cmd_flag = 1; + } + if (cmd_flag) + { + rt_event_send(&sdio->cmd_event, intstatus); + } + } + /* Data response processing */ + if (data != NULL) + { + data->err = RT_EOK; + if (SDIO_GetFlagStatus(SDIO_FLAG_TRANS_END)) + { + SDIO_FlagConfig(HW_SDIO_DATA_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_TRANS_END); + data_flag = 1; + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DATA_TIMEOUT)) + { + SDIO_FlagConfig(HW_SDIO_DATA_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_DATA_TIMEOUT); + data->err = -RT_ETIMEOUT; + data_flag = 1; + } + if (SDIO_GetFlagStatus(SDIO_FLAG_DATA_CRCERR)) + { + SDIO_FlagConfig(HW_SDIO_DATA_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_DATA_CRCERR); + data->err = -RT_ERROR; + data_flag = 1; + } + if (SDIO_GetFlagStatus(SDIO_FLAG_BUF_OVERFLOW)) + { + SDIO_FlagConfig(HW_SDIO_DATA_FLAG, DISABLE); + SDIO_ClearFlag(SDIO_FLAG_BUF_OVERFLOW); + data->err = -RT_ERROR; + data_flag = 1; + } + /* 如果操作完成 */ + if (data_flag) + { + rt_event_send(&sdio->dat_event, intstatus); /* 发送事件，通知操作完成 */ + } + } + + +} +static const struct rt_mmcsd_host_ops ops = +{ + .request = rt_hw_sdio_request, + .set_iocfg = rt_hw_sdio_iocfg, + .get_card_status = rt_hw_sd_delect, + .enable_sdio_irq = rt_hw_sdio_irq_update, +}; +/** + * @brief this function create mmcsd host. + * @param sdio_des at32_sdio_des + * @retval rt_mmcsd_host + */ +struct rt_mmcsd_host *sdio_host_create(struct ht32_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rt_hw_sdio *sdio = RT_NULL; + /* effective parameter */ + if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + { + LOG_E("L:%d F:%s %s %s %s", + (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), + (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "") + ); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rt_hw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rt_hw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rt_hw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct ht32_sdio_des)); + sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (HT_SDIO_TypeDef *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio); + sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? ht32_sdio_clk_get : sdio_des->clk_get); + /* Initialising events and mutexes */ + rt_event_init(&sdio->dat_event, "sdio", RT_IPC_FLAG_FIFO); + rt_event_init(&sdio->cmd_event, "sdio_cmd", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO); + + /* set host defautl attributes */ + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80; +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rt_hw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +/** + * @brief this function configures the dmatx. + * @param src: pointer to the source buffer + * @param dst: pointer to the destination buffer + * @param buffer_size: size of tx buffer + * @retval none + */ +void sd_lowlevel_dmatx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size) +{ + PDMACH_InitTypeDef PDMACH_InitStruct; + /* Configure */ + PDMACH_InitStruct.PDMACH_SrcAddr = (u32)src; + PDMACH_InitStruct.PDMACH_DstAddr = (u32)dst; + PDMACH_InitStruct.PDMACH_AdrMod = SRC_ADR_LIN_INC | DST_ADR_FIX; + PDMACH_InitStruct.PDMACH_BlkCnt = buffer_size; + PDMACH_InitStruct.PDMACH_BlkLen = 1; + PDMACH_InitStruct.PDMACH_DataSize = WIDTH_32BIT; + PDMACH_InitStruct.PDMACH_Priority = H_PRIO; + PDMA_Config(PDMA_SDIO_TX, &PDMACH_InitStruct); + PDMA_IntConfig(PDMA_SDIO_TX, (PDMA_INT_GE | PDMA_INT_TC | PDMA_INT_TE), ENABLE); + NVIC_EnableIRQ(PDMACH7_IRQn); + PDMA_EnaCmd(PDMA_SDIO_TX, ENABLE); +} + +/** + * @brief this function configures the dmarx. + * @param src: pointer to the source buffer + * @param dst: pointer to the destination buffer + * @param buffer_size: size of rx buffer + * @retval none + */ +void sd_lowlevel_dmarx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size) +{ + PDMACH_InitTypeDef PDMACH_InitStruct; + /* Configure */ + PDMACH_InitStruct.PDMACH_SrcAddr = (u32)src; + PDMACH_InitStruct.PDMACH_DstAddr = (u32)dst; + PDMACH_InitStruct.PDMACH_AdrMod = SRC_ADR_FIX | DST_ADR_LIN_INC; + PDMACH_InitStruct.PDMACH_BlkCnt = buffer_size; + PDMACH_InitStruct.PDMACH_BlkLen = 1; + PDMACH_InitStruct.PDMACH_DataSize = WIDTH_32BIT; + PDMACH_InitStruct.PDMACH_Priority = H_PRIO; + PDMA_Config(PDMA_SDIO_RX, &PDMACH_InitStruct); + PDMA_IntConfig(PDMA_SDIO_RX, (PDMA_INT_GE | PDMA_INT_TC | PDMA_INT_TE), ENABLE); + NVIC_EnableIRQ(PDMACH6_IRQn); + PDMA_EnaCmd(PDMA_SDIO_RX, ENABLE); +} + + +/** + * @brief this function get at32 sdio clock. + * @param hw_sdio: at32_sdio + * @retval ahb frequency + */ +static rt_uint32_t ht32_sdio_clock_get(HT_SDIO_TypeDef *hw_sdio) +{ + return SystemCoreClock; +} +static rt_err_t dma_tx_config(rt_uint32_t *src, rt_uint32_t *dst, int size) +{ + sd_lowlevel_dmatx_config((uint32_t *)src, (uint32_t *)dst, size / 4); + return RT_EOK; +} +static rt_err_t dma_rx_config(rt_uint32_t *src, rt_uint32_t *dst, int size) +{ + sd_lowlevel_dmarx_config((uint32_t *)src, (uint32_t *)dst, size / 4); + return RT_EOK; +} + +int rt_hw_sdio_init(void) +{ + struct ht32_sdio_des sdio_des; + + ht32_sdio_gpio_init((void *)(HT_SDIO)); + sdio_des.clk_get = ht32_sdio_clock_get; + sdio_des.hw_sdio = (HT_SDIO_TypeDef *)HT_SDIO; + sdio_des.rxconfig = dma_rx_config; + sdio_des.txconfig = dma_tx_config; + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return -1; + } + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +/*********************************************************************************************************//** + * @brief This function handles PDMA_CH6 interrupt. + * @retval None + ************************************************************************************************************/ +void PDMA_CH6_IRQHandler(void) +{ + if (HT_PDMA->ISR1 & (PDMA_FLAG_TE << ((PDMA_CH6 - 6) * 5))) + { + LOG_E(" TE6"); + while (1); + } + + HT_PDMA->ISCR1 = PDMA_FLAG_TC << ((PDMA_CH6 - 6) * 5); + PDMA_EnaCmd(PDMA_SDIO_RX, DISABLE); +} + +/*********************************************************************************************************//** + * @brief This function handles PDMA_CH7 interrupt. + * @retval None + ************************************************************************************************************/ +void PDMA_CH7_IRQHandler(void) +{ + if (HT_PDMA->ISR1 & (PDMA_FLAG_TE << ((PDMA_CH7 - 6) * 5))) + { + LOG_E(" TE7"); + while (1); + } + + HT_PDMA->ISCR1 = PDMA_FLAG_TC << ((PDMA_CH7 - 6) * 5); + PDMA_EnaCmd(PDMA_SDIO_TX, DISABLE); +} + +/*********************************************************************************************************//** + * @brief This function handles SDIO interrupt. + * @retval None + ************************************************************************************************************/ +void SDIO_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_sdio_irq_process(host); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void ht32_mmcsd_change(void) +{ + mmcsd_change(host); +} + +#endif /* BSP_USING_SDIO */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_sdio.h b/bsp/ht32/libraries/ht32_drivers/drv_sdio.h new file mode 100644 index 0000000000..a66c96ef23 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_sdio.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-11-06 QT-one first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include +#include + +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef SDIO_BASE_ADDRESS +#define SDIO_BASE_ADDRESS HT_SDIO +#endif + +#ifndef SDIO_CLOCK_FREQ +#define SDIO_CLOCK_FREQ (48U * 1000 * 1000) +#endif + +#ifndef SDIO_BUFF_SIZE +#define SDIO_BUFF_SIZE (4096) +#endif + +#ifndef SDIO_ALIGN_LEN +#define SDIO_ALIGN_LEN (32) +#endif + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (24 * 1000 * 1000) +#endif + +#define HW_SDIO_CMD_FLAG \ + (SDIO_INT_CMD_SEND | SDIO_FLAG_CMD_TIMEOUT | SDIO_FLAG_CMD_CRCERR | SDIO_FLAG_CMD_IDXERR) + +#define HW_SDIO_DATA_FLAG \ + (SDIO_FLAG_BUF_OVERFLOW | SDIO_FLAG_BUF_UNDERFLOW | SDIO_FLAG_DATA_CRCERR | SDIO_FLAG_DATA_TIMEOUT | SDIO_FLAG_TRANS_END) + +#define HW_SDIO_DATATIMEOUT (0x000FFFFF) + +void ht32_mmcsd_change(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SDIO_H__ */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usart.c b/bsp/ht32/libraries/ht32_drivers/drv_usart.c index bc19b0409e..6616b5b860 100644 --- a/bsp/ht32/libraries/ht32_drivers/drv_usart.c +++ b/bsp/ht32/libraries/ht32_drivers/drv_usart.c @@ -261,11 +261,11 @@ static rt_ssize_t ht32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t static const struct rt_uart_ops ht32_usart_ops = { - .configure = ht32_configure, - .control = ht32_control, - .putc = ht32_putc, - .getc = ht32_getc, - .dma_transmit = ht32_dma_transmit, + .configure = ht32_configure, + .control = ht32_control, + .putc = ht32_putc, + .getc = ht32_getc, + .dma_transmit = ht32_dma_transmit, }; int rt_hw_usart_init(void) diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usbd.c b/bsp/ht32/libraries/ht32_drivers/drv_usbd.c new file mode 100644 index 0000000000..ecae47c3e6 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_usbd.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-09 QT-one first version + */ + +#include "drv_usbd.h" + +#ifdef RT_USING_USB_DEVICE +#if !defined(BSP_USING_USBD) + #error "Please define at least one BSP_USING_USBD" +#endif + +#if defined(BSP_USING_USBD) + #include "usb_port.h" +#endif + +struct ht32_usbd +{ + char *name; + USBDCore_TypeDef *p_usbd_code; + IRQn_Type irq; +}; + +__ALIGN4 USBDCore_TypeDef p_usbd; +/* internal mount point */ +static struct ht32_usbd *p_usbd_instance = RT_NULL; + +/* Endpoint Function List */ +static struct ep_id endpoint_pool[] = +{ + {0x00, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x01, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x02, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x03, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x04, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x05, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x06, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x07, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 64, ID_UNASSIGNED}, +}; + +/* usbd Peripheral List */ +static struct ht32_usbd usbd_config[] = +{ +#ifdef BSP_USING_USBD + { + .name = BSP_USING_USBD_NAME, + .p_usbd_code = NULL, + .irq = USB_IRQn, + }, +#endif +}; + +/* Start of Frame (SOF) interrupt callbacks */ +void usbd_sof_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_sof_handler(udcd); +} +/* USB reset interrupt */ +void usbd_reset_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_reset_handler(udcd); +} + +/* USB Suspend (Disconnect) Interrupt */ +void usbd_suspend_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_disconnect_handler(udcd); +} + +/* USB recovery (reconnect) interrupt */ +void usbd_resume_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_connect_handler(udcd); +} + +/* USB endpoint 0 interrupt */ +void usbd_setup_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep0_setup_handler(udcd, (struct urequest *)&pCore->Device.Request); +} + +/* Endpoint 0 input interrupt£¨Can be classified as other endpoint input interrupt£© */ +void usbd_ep0_in_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep0_in_handler(udcd); +} + +/* Endpoint 0 output interrupt£¨Can be classified as other endpoint input interrupt£© */ +void usbd_ep0_out_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + pCore->Device.Transfer.sByteLength = pCore->Device.Request.wLength; + rt_usbd_ep0_out_handler(udcd, pCore->Device.Transfer.sByteLength); +} + +/* Other endpoint input interrupt */ +void usbd_ep_in_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + pCore->Device.Transfer.sByteLength = 0; + rt_usbd_ep_in_handler(udcd, EPTn | 0x80, pCore->Device.Transfer.sByteLength); +} + +/* Other Endpoint Output Interrupt */ +void usbd_ep_out_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep_out_handler(udcd, EPTn, pCore->ept_io->trans_len); +} + +/* Setting the address */ +static rt_err_t ht32_set_address(rt_uint8_t address) +{ + /* Setting the device address */ + p_usbd_instance->p_usbd_code->Info.CurrentStatus = USER_USB_STATE_ADDRESS; + API_USB_SET_ADDR(address); + return RT_EOK; +} +/* Configuration settings */ +static rt_err_t ht32_set_config(rt_uint8_t address) +{ + return RT_EOK; +} +/* endpoint pause */ +static rt_err_t ht32_ep_set_stall(rt_uint8_t address) +{ + if (0 == (address & 0x7f)) + API_USB_EPTn_SEND_STALL((USBD_EPTn_Enum)(address & 0x7f)); + else + API_USB_EPTn_SET_HALT((USBD_EPTn_Enum)(address & 0x7f)); + return RT_EOK; +} +/* Endpoint reboot*/ +static rt_err_t ht32_ep_clear_stall(rt_uint8_t address) +{ + if (0 != (address & 0x7f)) + { + API_USB_EPTn_CLR_HALT((USBD_EPTn_Enum)(address & 0x7f)); + API_USB_EPTn_CLR_DTG((USBD_EPTn_Enum)(address & 0x7f)); + } + return RT_EOK; +} +/* endpoint enable */ +static rt_err_t ht32_ep_enable(struct uendpoint *ep) +{ + /* Functions not found in the firmware library at the moment */ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + usbd_ep_enable(p_usbd_instance->p_usbd_code, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} +/* endpoint incapacity */ +static rt_err_t ht32_ep_disable(struct uendpoint *ep) +{ + /* Functions not found in the firmware library at the moment */ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + usbd_ep_disable(p_usbd_instance->p_usbd_code, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} +/* Endpoint Receive Data Preparation */ +static rt_ssize_t ht32_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USBDCore_EPTReadOUTData((USBD_EPTn_Enum)(address & 0x7f), (uint32_t *)buffer, size); + return size; +} +/* Endpoint reading data */ +static rt_ssize_t ht32_ep_read(rt_uint8_t address, void *buffer) +{ + /* Do not read data from this function */ + rt_size_t size = 0; + RT_ASSERT(buffer != RT_NULL); + return size; +} +/* Endpoint Write Data */ +static rt_ssize_t ht32_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + /* Use this function to write data to a USB endpoint */ + return USBDCore_EPTWriteINData((USBD_EPTn_Enum)(address & 0x7f), (uint32_t *)buffer, size); +} +/* Endpoint 0 transmit status */ +static rt_err_t ht32_ep0_send_status(void) +{ + uint8_t Date = 0; + /* State of send endpoint 0 */ + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32*)&Date, 0); + return RT_EOK; +} +/* USB pause */ +static rt_err_t ht32_suspend(void) +{ + return RT_EOK; +} +/* USB awakens */ +static rt_err_t ht32_wakeup(void) +{ + return RT_EOK; +} + +/* USB device interface function */ +const static struct udcd_ops _udc_ops = +{ + .set_address = ht32_set_address, + .set_config = ht32_set_config, + .ep_set_stall = ht32_ep_set_stall, + .ep_clear_stall = ht32_ep_clear_stall, + .ep_enable = ht32_ep_enable, + .ep_disable = ht32_ep_disable, + .ep_read_prepare = ht32_ep_read_prepare, + .ep_read = ht32_ep_read, + .ep_write = ht32_ep_write, + .ep0_send_status = ht32_ep0_send_status, + .suspend = ht32_suspend, + .wakeup = ht32_wakeup, +}; + +static void usbd_mainroutine(void) +{ + USBDCore_MainRoutine(p_usbd_instance->p_usbd_code); +} +/* USB Device Initialisation Functions */ +static rt_err_t ht32_dcd_init(rt_device_t device) +{ + /* USB object and interface initialisation, and turning on USB interrupts */ + USB_Configuration(p_usbd_instance->p_usbd_code); + rt_thread_idle_sethook(usbd_mainroutine); + return RT_EOK; +} + +/* USB device registration function */ +int ht32_usbd_register(void) +{ + rt_size_t obj_num; + rt_err_t result = 0; + int index; + USBDCore_TypeDef *p_usbd_core = &p_usbd; + /* Calculate how many USB devices */ + obj_num = sizeof(usbd_config) / sizeof(struct ht32_usbd); + + for (index = 0; index < obj_num; index++) + { + /* Request a udcd object memory and clear it. */ + udcd_t udcd = (udcd_t)rt_malloc(sizeof(struct udcd)); + if (udcd == RT_NULL) + { + rt_kprintf("udcd malloc failed\r\n"); + return -RT_ERROR; + } + rt_memset((void *)udcd, 0, sizeof(struct udcd)); + + /* Assigning a value to the requested udcd object */ + udcd->parent.type = RT_Device_Class_USBDevice; + udcd->parent.init = ht32_dcd_init; + udcd->parent.user_data = p_usbd_core; + udcd->ops = &_udc_ops; + + p_usbd_core->pdata = udcd; + usbd_config[index].p_usbd_code = p_usbd_core; + + /* register endpoint infomation */ + udcd->ep_pool = endpoint_pool; + udcd->ep0.id = &endpoint_pool[0]; + + result = rt_device_register((rt_device_t)udcd, usbd_config[index].name, 0); + RT_ASSERT(result == RT_EOK); + + p_usbd_instance = &usbd_config[index]; + + result = rt_usb_device_init(); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_DEVICE_EXPORT(ht32_usbd_register); + + +void USB_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* interrupt callback function */ + usbd_irq_handler(p_usbd_instance->p_usbd_code); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_USB_DEVICE */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usbd.h b/bsp/ht32/libraries/ht32_drivers/drv_usbd.h new file mode 100644 index 0000000000..9c2f652ba6 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_usbd.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-09 QT-one first version + */ + +#ifndef __DRV_USBD_H__ +#define __DRV_USBD_H__ + +#include +#include +#include "drv_common.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USBD_H__ */ diff --git a/bsp/ht32/libraries/usbd_library/SConscript b/bsp/ht32/libraries/usbd_library/SConscript new file mode 100644 index 0000000000..7c3921200b --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/SConscript @@ -0,0 +1,22 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +# The set of source files associated with this SConscript file. +if GetDepend(['BSP_USING_USBD']): +# src += ['src/ht32_usbd_core.c'] +# src += ['src/ht32_usbd_int.c'] + src += ['src/usbd_code.c'] + src += ['src/usb_port.c'] + +path = [cwd + '/inc'] + +group = DefineGroup('usbd_library', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/ht32/libraries/usbd_library/checkout.py b/bsp/ht32/libraries/usbd_library/checkout.py new file mode 100644 index 0000000000..19fc0ca9fc --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/checkout.py @@ -0,0 +1,39 @@ +# 假设我们有一个名为'example.txt'的文件，我们想要修改它 +header_file_path = 'inc/ht32_usbd_core.h' +source_file_path = 'src/ht32_usbd_core.c' + +def modification(file_path): + # 打开文件 + with open(file_path, 'r+') as file: # 'r+'模式允许读写 + # 读取文件内容 + content = file.read() + print("文件打开成功！") + + # 假设我们要将所有的'old_string'替换为'new_string' + # updated_content = content.replace('old_string', 'new_string') + content = content.replace('USB_STATE_UNCONNECTED', 'USER_USB_STATE_UNCONNECTED') + content = content.replace('USB_STATE_ATTACHED', 'USER_USB_STATE_ATTACHED') + content = content.replace('USB_STATE_POWERED', 'USER_USB_STATE_POWERED') + content = content.replace('USB_STATE_SUSPENDED', 'USER_USB_STATE_SUSPENDED') + content = content.replace('USB_STATE_DEFAULT', 'USER_USB_STATE_DEFAULT') + content = content.replace('USB_STATE_ADDRESS', 'USER_USB_STATE_ADDRESS') + content = content.replace('USB_STATE_CONFIGURED', 'USER_USB_STATE_CONFIGURED') + + # 移动文件指针到文件开头，准备写入 + file.seek(0) + + # 写入更新后的内容 + file.write(content) + + # 截断文件，删除旧内容（如果更新后的内容比原内容短） + file.truncate() + + +# 文件现在已经被关闭，并且更改被保存 +if __name__ == '__main__': + modification(header_file_path) + print('头文件已修改！\r\n') + modification(source_file_path) + print('源文件已修改！\r\n') + print('请输入退出：') + diff --git a/bsp/ht32/libraries/usbd_library/inc/ht32_usbd_core.h b/bsp/ht32/libraries/usbd_library/inc/ht32_usbd_core.h new file mode 100644 index 0000000000..1ba2309d4f --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/inc/ht32_usbd_core.h @@ -0,0 +1,437 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.h + * @version $Rev:: 2555 $ + * @date $Date:: 2022-03-15 #$ + * @brief The header file of standard protocol related function for HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CORE_H +#define __HT32_USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library + * @{ + */ + +/** @addtogroup USBDCore + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Settings USB Device Core settings + * @{ + */ +/* USBD Debug mode */ +// Enable USB Debug mode +// Dump USB Debug data +#ifndef USBDCORE_DEBUG + #define USBDCORE_DEBUG (0) /*!< Enable USB Debug mode */ + #define USBDCORE_DEBUG_DATA (0) /*!< Dump USB Debug data */ +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Type USB Device Core exported types + * @{ + */ +/** + * @brief USB Device Request. + */ +typedef __PACKED_H struct +{ + uc8 bmRequestType; + uc8 bRequest; + uc8 wValueL; + uc8 wValueH; + uc16 wIndex; + uc16 wLength; +} __PACKED_F USBDCore_Request_TypeDef; + +/** + * @brief USB Descriptor. + */ +typedef struct +{ + uc8 *pDeviceDesc; /*!< Device Descriptor */ + uc8 *pConfnDesc; /*!< Configuration Descriptor */ + uc8 **ppStringDesc; /*!< String Descriptor */ + u32 uStringDescNumber; /*!< Count of String Descriptor */ +} USBDCore_Desc_TypeDef; + +/** + * @brief STALL, control IN or control OUT. + */ +typedef enum +{ + USB_ACTION_STALL = 0, + USB_ACTION_DATAIN = 1, + USB_ACTION_DATAOUT = 2, +} USBDCore_Action_Enum; + +/** + * @brief Call back function. + */ +typedef struct +{ + void (*func) (u32 uPara); /*!< Call back function pointer */ + u32 uPara; /*!< Parameter of call back function */ +} USBDCore_CallBack_TypeDef; + +/** + * @brief Parameter for control IN/OUT Transfer. + */ +typedef struct +{ + u8 uBuffer[2]; /*!< Temporary buffer */ + uc8 *pData; /*!< Pointer of control IN/OUT Data */ + s32 sByteLength; /*!< Total length for control IN/OUT Transfer */ + USBDCore_Action_Enum Action; /*!< STALL, control IN or control OUT */ + USBDCore_CallBack_TypeDef CallBack_OUT; /*!< Call back function pointer for Control OUT */ +} USBDCore_Transfer_TypeDef; + +/** + * @brief USB Device. + */ +typedef struct +{ + USBDCore_Request_TypeDef Request; /*!< USB Device Request */ + USBDCore_Desc_TypeDef Desc; /*!< USB Descriptor */ + USBDCore_Transfer_TypeDef Transfer; /*!< Parameter for control IN/OUT Transfer */ +} USBDCore_Device_TypeDef; + +/** + * @brief Bit access for CurrentFeature. + */ +typedef __PACKED_H struct _FEATURE_TYPEBIT +{ + unsigned bSelfPowered :1; /*!< Remote Wakeup feature */ + unsigned bRemoteWakeup :1; /*!< Self Powered */ +} __PACKED_F USBDCore_Feature_TypeBit; + +/** + * @brief For Set/ClearFeature and GetStatus request. + */ +typedef __PACKED_H union _FEATURE_TYPEDEF +{ + u8 uByte; /*!< Byte access for CurrentFeature */ + USBDCore_Feature_TypeBit Bits; /*!< Bit access for CurrentFeature */ +} __PACKED_F USBDCore_Feature_TypeDef; + +/** + * @brief Device State. + */ +typedef enum +{ + USER_USER_USB_STATE_UNCONNECTED = 0, + USER_USER_USB_STATE_ATTACHED = 1, + USER_USER_USB_STATE_POWERED = 2, + USER_USER_USB_STATE_SUSPENDED = 3, + USER_USER_USB_STATE_DEFAULT = 4, + USER_USER_USB_STATE_ADDRESS = 5, + USER_USER_USB_STATE_CONFIGURED = 6, +} USBDCore_Status_Enum; + +/** + * @brief USB Device information. + */ +typedef struct +{ + u8 uCurrentConfiguration; /*!< For Set/GetConfiguration request */ + u8 uCurrentInterface; /*!< For Set/GetInterface request */ + volatile USBDCore_Status_Enum CurrentStatus; /*!< Device State */ + USBDCore_Status_Enum LastStatus; /*!< Device State before SUSPEND */ + USBDCore_Feature_TypeDef CurrentFeature; /*!< For Set/ClearFeature and GetStatus request */ + u32 uIsDiscardClearFeature; /*!< Discard ClearFeature flag for Mass Storage */ +} USBDCore_Info_TypeDef; + +typedef void (*USBDCore_CallBackClass_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackVendor_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackEPTn_Typedef) (USBD_EPTn_Enum EPTn); + +/** + * @brief USB Class call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_MainRoutine; /*!< Class main routine call back function */ + USBDCore_CallBack_TypeDef CallBack_Reset; /*!< Class RESET call back function */ + USBDCore_CallBack_TypeDef CallBack_StartOfFrame; /*!< Class SOF call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetDescriptor; /*!< Class Get Descriptor call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassSetInterface; /*!< Set Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetInterface; /*!< Get Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassRequest; /*!< Class Request call back function */ + USBDCore_CallBackVendor_Typedef CallBack_VendorRequest; /*!< Vendor Request call back function */ + USBDCore_CallBackEPTn_Typedef CallBack_EPTn[MAX_EP_NUM]; /*!< Endpoint n call back function */ +} USBDCore_Class_TypeDef; + +/** + * @brief USB Device Power related call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_Suspend; +} USBDCore_Power_TypeDef; + +/** + * @brief Major structure of USB Library. + */ +typedef struct +{ + USBDCore_Device_TypeDef Device; /*!< USB Device */ + USBDCore_Info_TypeDef Info; /*!< USB Device information */ + USBDCore_Class_TypeDef Class; /*!< USB Class call back function */ + u32 *pDriver; /*!< USB Device Driver initialization structure */ + USBDCore_Power_TypeDef Power; /*!< USB Device Power related call back function */ + + void *pdata; /*!< USB User private pointer */ +} USBDCore_TypeDef; + +/*----------------------------------------------------------------------------------------------------------*/ +/* Variable architecture of USB Library */ +/*----------------------------------------------------------------------------------------------------------*/ +/* USBCore - USBDCore_TypeDef Major structure of USB Library */ +/* USBCore.Device - USBDCore_Device_TypeDef USB Device */ +/* USBCore.Device.Request - USBDCore_Request_TypeDef USB Device Request */ +/* USBCore.Device.Request.bmRequestType */ +/* USBCore.Device.Request.bRequest */ +/* USBCore.Device.Request.wValueL */ +/* USBCore.Device.Request.wValueH */ +/* USBCore.Device.Request.wIndex */ +/* USBCore.Device.Request.wLength */ +/* USBCore.Device.Desc - USBDCore_Desc_TypeDef USB Descriptor */ +/* USBCore.Device.Desc.pDeviceDesc Device Descriptor */ +/* USBCore.Device.Desc.pConfnDesc Configuration Descriptor */ +/* USBCore.Device.Desc.pStringDesc[DESC_NUM_STRING] String Descriptor */ +/* USBCore.Device.Desc.uStringDescNumber Count of String Descriptor */ +/* USBCore.Device.Transfer - USBDCore_Transfer_TypeDef Parameter for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.uBuffer[2] Temporary buffer */ +/* USBCore.Device.Transfer.pData Pointer of control IN/OUT Data */ +/* USBCore.Device.Transfer.sByteLength Total length for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.Action - USBDCore_Action_Enum STALL, control IN or control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.func(uPara) Call back function pointer for Control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.uPara Parameter of Control OUT call back function */ +/* */ +/* USBCore.Info - USBDCore_Info_TypeDef USB Device information */ +/* USBCore.Info.uCurrentConfiguration For Set/GetConfiguration request */ +/* USBCore.Info.uCurrentInterface For Set/GetInterface request */ +/* USBCore.Info.CurrentStatus - USBDCore_Status_Enum Device State */ +/* USBCore.Info.LastStatus - USBDCore_Status_Enum Device State before SUSPEND */ +/* USBCore.Info.CurrentFeature - USBDCore_Feature_TypeDef For Set/ClearFeature and GetStatus request */ +/* USBCore.Info.CurrentFeature.uByte Byte access for CurrentFeature */ +/* USBCore.Info.CurrentFeature.Bits.bRemoteWakeup Remote Wakeup feature */ +/* USBCore.Info.CurrentFeature.Bits.bSelfPowered Self Powered */ +/* USBCore.Info.uIsDiscardClearFeature Discard ClearFeature flag for Mass Storage */ +/* */ +/* USBCore.Class - USBDCore_Class_TypeDef USB Class call back function */ +/* USBCore.Class.CallBack_MainRoutine.func(uPara) Class main routine call back function */ +/* USBCore.Class.CallBack_MainRoutine.uPara Parameter of class main routine */ +/* USBCore.Class.CallBack_Reset.func(uPara) Class RESET call back function */ +/* USBCore.Class.CallBack_Reset.uPara Parameter of RESET call back function */ +/* USBCore.Class.CallBack_StartOfFrame.func(uPara) Class SOF call back function */ +/* USBCore.Class.CallBack_StartOfFrame.uPara Parameter of SOF call back function */ +/* USBCore.Class.CallBack_ClassGetDescriptor(pDev) Class Get Descriptor call back function */ +/* USBCore.Class.CallBack_ClassSetInterface(pDev) Set Interface call back function */ +/* USBCore.Class.CallBack_ClassGetInterface(pDev) Get Interface call back function */ +/* USBCore.Class.CallBack_ClassRequest(pDev) Class Request call back function */ +/* USBCore.Class.CallBack_EPTn[MAX_EP_NUM](EPTn) Endpoint n call back function */ +/* */ +/* USBCore.pDriver USB Device Driver initialization structure */ +/* */ +/* USBCore.Power - USBDCore_Power_TypeDef USB Device Power related call back function */ +/* USBCore.Power.CallBack_Suspend.func(uPara) System low power function for SUSPEND */ +/* USBCore.Power.CallBack_Suspend.uPara Parameter of system low power function */ +/*----------------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Constant USB Device Core exported constants + * @{ + */ + +/** @defgroup USBDCore_Descriptor Definitions for USB descriptor + * @{ + */ +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define DESC_TYPE_04_INF (0x4) +#define DESC_TYPE_05_EPT (0x5) +#define DESC_TYPE_06_DEV_QLF (0x6) +#define DESC_TYPE_08_INF_PWR (0x8) + +#define DESC_CLASS_00_BY_INF (0x00) +#define DESC_CLASS_01_AUDIO (0x01) +#define DESC_CLASS_02_CDC_CTRL (0x02) +#define DESC_CLASS_03_HID (0x03) +#define DESC_CLASS_05_PHY (0x05) +#define DESC_CLASS_06_STILL_IMG (0x06) +#define DESC_CLASS_07_PRINTER (0x07) +#define DESC_CLASS_08_MASS_STORAGE (0x08) +#define DESC_CLASS_09_HUB (0x09) +#define DESC_CLASS_0A_CDC_DATA (0x0A) +#define DESC_CLASS_0B_SMART_CARD (0x0B) +#define DESC_CLASS_0E_VIDEO (0x0E) +#define DESC_CLASS_0F_PHD (0x0F) +#define DESC_CLASS_FF_VENDOR (0xFF) + +#define DESC_LEN_DEV ((u32)(18)) +#define DESC_LEN_CONFN ((u32)(9)) +#define DESC_LEN_INF ((u32)(9)) +#define DESC_LEN_EPT ((u32)(7)) +/** + * @} + */ + +/** @defgroup USBDCore_Request Definitions for USB Request + * @{ + */ +#define REQ_DIR_00_H2D (0 << 7) +#define REQ_DIR_01_D2H (1 << 7) + +#define REQ_TYPE_00_STD (0 << 5) +#define REQ_TYPE_01_CLS (1 << 5) +#define REQ_TYPE_02_VND (2 << 5) + +#define REQ_REC_00_DEV (0) +#define REQ_REC_01_INF (1) +#define REQ_REC_02_EPT (2) +/** + * @} + */ + +/** + * @brief For USBDCore_EPTReadOUTData function. + */ +#define USB_DISCARD_OUT_DATA (0) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Macro USB Device Core exported macros + * @{ + */ +#define __DBG_USBPrintf(...) +#define __DBG_USBDump(a, b) + +#if (USBDCORE_DEBUG == 1) + #ifndef RETARGET_IS_USB + extern u32 __DBG_USBCount; + #undef __DBG_USBPrintf + #define __DBG_USBPrintf printf + #if (USBDCORE_DEBUG_DATA == 1) + #undef __DBG_USBDump + void __DBG_USBDump(uc8 *memory, u32 len); + #endif + #endif +#endif + +/** + * @brief Convert Half-Word to Byte for descriptor. + */ +#define DESC_H2B(Val) ((u8)(Val & 0x00FF)), ((u8)((Val & 0xFF00) >> 8)) + +/** + * @brief Padding 0 automatically for String descriptor. + */ +#define DESC_CHAR(c) (c), (0) + +/** + * @brief Calculate String length for String descriptor. + */ +#define DESC_STRLEN(n) (n * 2 + 2) + +/** + * @brief Calculate power for Configuration descriptor. + */ +#define DESC_POWER(mA) (mA / 2) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +#define USBDCore_DeInit API_USB_DEINIT +#define USBDCore_EPTReset API_USB_EPTn_RESET +#define USBDCore_EPTGetBufferLen API_USB_EPTn_GET_BUFFLEN +#define USBDCore_EPTGetTransferCount API_USB_EPTn_GET_CNT +#define USBDCore_EPTSetSTALL API_USB_EPTn_SET_HALT +#define USBDCore_EPTWaitSTALLSent API_USB_EPTn_WAIT_STALL_SENT +#define USBDCore_EPTClearDataToggle API_USB_EPTn_CLR_DTG + +#define USBDCore_EPTWriteINData API_USB_EPTn_WRITE_IN +#define USBDCore_EPTReadOUTData API_USB_EPTn_READ_OUT +#define USBDCore_EPTReadMemory API_USB_EPTn_READ_MEM + +void USBDCore_Init(USBDCore_TypeDef *pCore); +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore); +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore); +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore); +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore); +void USBDCore_TriggerRemoteWakeup(void); +USBDCore_Status_Enum USBDCore_GetStatus(void); + +void USBDCore_EPTReset(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum type); +void USBDCore_EPTSetSTALL(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTClearDataToggle(USBD_EPTn_Enum USBD_EPTn); + +u32 USBDCore_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBDCore_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBDCore_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_USBD_CORE_H -------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/usbd_library/inc/ht32_usbd_int.h b/bsp/ht32/libraries/usbd_library/inc/ht32_usbd_int.h new file mode 100644 index 0000000000..87e4bd2ebd --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/inc/ht32_usbd_int.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-11 QT-one first version + */ + +#ifndef __HT32_USBD_INT_H__ +#define __HT32_USBD_INT_H__ + +#include +#include +#include "drv_common.h" + +#include "ht32_usbd_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + + + + + /* º¯ÊýÉùÃ÷ */ + void usbd_sof_callback(USBDCore_TypeDef *pCore); + void usbd_reset_callback(USBDCore_TypeDef *pCore); + void usbd_suspend_callback(USBDCore_TypeDef *pCore); + void usbd_resume_callback(USBDCore_TypeDef *pCore); + + void usbd_setup_callback(USBDCore_TypeDef *pCore); + void usbd_ep0_in_callback(USBDCore_TypeDef *pCore); + void usbd_ep0_out_callback(USBDCore_TypeDef *pCore); + + void usbd_ep_in_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn); + void usbd_ep_out_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn); + +// void USB_Configuration(USBDCore_TypeDef *pCore); + + + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_USBD_INT_H__ */ diff --git a/bsp/ht32/libraries/usbd_library/inc/usb_port.h b/bsp/ht32/libraries/usbd_library/inc/usb_port.h new file mode 100644 index 0000000000..de96b24b04 --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/inc/usb_port.h @@ -0,0 +1,29 @@ + +#ifndef _USB_PORT_H +#define _USB_PORT_H + +#include "ht32.h" +//#include "ht32_usbd_core.h" +#include "usbd_code.h" + + +#define HT32F_DVB_USBConnect() USBD_DPpullupCmd(ENABLE) +#define HT32F_DVB_USBDisConnect() USBD_DPpullupCmd(DISABLE) + + +/* º¯ÊýÉùÃ÷ */ +void usbd_sof_callback(USBDCore_TypeDef *pCore); +void usbd_reset_callback(USBDCore_TypeDef *pCore); +void usbd_suspend_callback(USBDCore_TypeDef *pCore); +void usbd_resume_callback(USBDCore_TypeDef *pCore); + +void usbd_setup_callback(USBDCore_TypeDef *pCore); +void usbd_ep0_in_callback(USBDCore_TypeDef *pCore); +void usbd_ep0_out_callback(USBDCore_TypeDef *pCore); + +void usbd_ep_in_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn); +void usbd_ep_out_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn); + +void USB_Configuration(USBDCore_TypeDef *pCore); + +#endif /* _USB_PORT_H */ diff --git a/bsp/ht32/libraries/usbd_library/inc/usbd_code.h b/bsp/ht32/libraries/usbd_library/inc/usbd_code.h new file mode 100644 index 0000000000..fe27279b89 --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/inc/usbd_code.h @@ -0,0 +1,434 @@ + + + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __USBD_CODE_H +#define __USBD_CODE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +/** @addtogroup HT32_USBD_Library + * @{ + */ + +/** @addtogroup USBDCore + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Settings USB Device Core settings + * @{ + */ +/* USBD Debug mode */ +// Enable USB Debug mode +// Dump USB Debug data +#ifndef USBDCORE_DEBUG + #define USBDCORE_DEBUG (0) /*!< Enable USB Debug mode */ + #define USBDCORE_DEBUG_DATA (0) /*!< Dump USB Debug data */ +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Type USB Device Core exported types + * @{ + */ +/** + * @brief USB Device Request. + */ +typedef __PACKED_H struct +{ + uc8 bmRequestType; + uc8 bRequest; + uc8 wValueL; + uc8 wValueH; + uc16 wIndex; + uc16 wLength; +} __PACKED_F USBDCore_Request_TypeDef; + +/** + * @brief USB Descriptor. + */ +typedef struct +{ + uc8 *pDeviceDesc; /*!< Device Descriptor */ + uc8 *pConfnDesc; /*!< Configuration Descriptor */ + uc8 **ppStringDesc; /*!< String Descriptor */ + u32 uStringDescNumber; /*!< Count of String Descriptor */ +} USBDCore_Desc_TypeDef; + +/** + * @brief STALL, control IN or control OUT. + */ +typedef enum +{ + USB_ACTION_STALL = 0, + USB_ACTION_DATAIN = 1, + USB_ACTION_DATAOUT = 2, +} USBDCore_Action_Enum; + +/** + * @brief Call back function. + */ +typedef struct +{ + void (*func) (u32 uPara); /*!< Call back function pointer */ + u32 uPara; /*!< Parameter of call back function */ +} USBDCore_CallBack_TypeDef; + +/** + * @brief Parameter for control IN/OUT Transfer. + */ +typedef struct +{ + u8 uBuffer[2]; /*!< Temporary buffer */ + uc8 *pData; /*!< Pointer of control IN/OUT Data */ + s32 sByteLength; /*!< Total length for control IN/OUT Transfer */ + USBDCore_Action_Enum Action; /*!< STALL, control IN or control OUT */ + USBDCore_CallBack_TypeDef CallBack_OUT; /*!< Call back function pointer for Control OUT */ +} USBDCore_Transfer_TypeDef; + +/** + * @brief USB Device. + */ +typedef struct +{ + USBDCore_Request_TypeDef Request; /*!< USB Device Request */ + USBDCore_Desc_TypeDef Desc; /*!< USB Descriptor */ + USBDCore_Transfer_TypeDef Transfer; /*!< Parameter for control IN/OUT Transfer */ +} USBDCore_Device_TypeDef; + +/** + * @brief Bit access for CurrentFeature. + */ +typedef __PACKED_H struct _FEATURE_TYPEBIT +{ + unsigned bSelfPowered :1; /*!< Remote Wakeup feature */ + unsigned bRemoteWakeup :1; /*!< Self Powered */ +} __PACKED_F USBDCore_Feature_TypeBit; + +/** + * @brief For Set/ClearFeature and GetStatus request. + */ +typedef __PACKED_H union _FEATURE_TYPEDEF +{ + u8 uByte; /*!< Byte access for CurrentFeature */ + USBDCore_Feature_TypeBit Bits; /*!< Bit access for CurrentFeature */ +} __PACKED_F USBDCore_Feature_TypeDef; + +/** + * @brief Device State. + */ +typedef enum +{ + USER_USB_STATE_UNCONNECTED = 0, + USER_USB_STATE_ATTACHED = 1, + USER_USB_STATE_POWERED = 2, + USER_USB_STATE_SUSPENDED = 3, + USER_USB_STATE_DEFAULT = 4, + USER_USB_STATE_ADDRESS = 5, + USER_USB_STATE_CONFIGURED = 6, +} USBDCore_Status_Enum; + +/** + * @brief USB Device information. + */ +typedef struct +{ + u8 uCurrentConfiguration; /*!< For Set/GetConfiguration request */ + u8 uCurrentInterface; /*!< For Set/GetInterface request */ + volatile USBDCore_Status_Enum CurrentStatus; /*!< Device State */ + USBDCore_Status_Enum LastStatus; /*!< Device State before SUSPEND */ + USBDCore_Feature_TypeDef CurrentFeature; /*!< For Set/ClearFeature and GetStatus request */ + u32 uIsDiscardClearFeature; /*!< Discard ClearFeature flag for Mass Storage */ +} USBDCore_Info_TypeDef; + +typedef void (*USBDCore_CallBackClass_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackVendor_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackEPTn_Typedef) (USBD_EPTn_Enum EPTn); + +/** + * @brief USB Class call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_MainRoutine; /*!< Class main routine call back function */ + USBDCore_CallBack_TypeDef CallBack_Reset; /*!< Class RESET call back function */ + USBDCore_CallBack_TypeDef CallBack_StartOfFrame; /*!< Class SOF call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetDescriptor; /*!< Class Get Descriptor call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassSetInterface; /*!< Set Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetInterface; /*!< Get Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassRequest; /*!< Class Request call back function */ + USBDCore_CallBackVendor_Typedef CallBack_VendorRequest; /*!< Vendor Request call back function */ + USBDCore_CallBackEPTn_Typedef CallBack_EPTn[MAX_EP_NUM]; /*!< Endpoint n call back function */ +} USBDCore_Class_TypeDef; + +/** + * @brief USB Device Power related call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_Suspend; +} USBDCore_Power_TypeDef; + +/** + * @brief USB EP TypeDef. + */ +typedef struct +{ + uint16_t maxpacket; /*!< endpoint max packet*/ + uint16_t status; /*!< endpoint status */ + /* transmission buffer and count */ + uint16_t total_len; /*!< endpoint transmission total length */ + uint16_t trans_len; /*!< endpoint transmission length*/ + uint8_t *trans_buf; /*!< endpoint transmission buffer */ +} usb_ept_info; + + + +/** + * @brief Major structure of USB Library. + */ +typedef struct +{ + USBDCore_Device_TypeDef Device; /*!< USB Device */ + USBDCore_Info_TypeDef Info; /*!< USB Device information */ + USBDCore_Class_TypeDef Class; /*!< USB Class call back function */ + u32 *pDriver; /*!< USB Device Driver initialization structure */ + USBDCore_Power_TypeDef Power; /*!< USB Device Power related call back function */ + + usb_ept_info ept_io[8]; /*!< */ + void *pdata; /*!< USB User private pointer */ +} USBDCore_TypeDef; + +/*----------------------------------------------------------------------------------------------------------*/ +/* Variable architecture of USB Library */ +/*----------------------------------------------------------------------------------------------------------*/ +/* USBCore - USBDCore_TypeDef Major structure of USB Library */ +/* USBCore.Device - USBDCore_Device_TypeDef USB Device */ +/* USBCore.Device.Request - USBDCore_Request_TypeDef USB Device Request */ +/* USBCore.Device.Request.bmRequestType */ +/* USBCore.Device.Request.bRequest */ +/* USBCore.Device.Request.wValueL */ +/* USBCore.Device.Request.wValueH */ +/* USBCore.Device.Request.wIndex */ +/* USBCore.Device.Request.wLength */ +/* USBCore.Device.Desc - USBDCore_Desc_TypeDef USB Descriptor */ +/* USBCore.Device.Desc.pDeviceDesc Device Descriptor */ +/* USBCore.Device.Desc.pConfnDesc Configuration Descriptor */ +/* USBCore.Device.Desc.pStringDesc[DESC_NUM_STRING] String Descriptor */ +/* USBCore.Device.Desc.uStringDescNumber Count of String Descriptor */ +/* USBCore.Device.Transfer - USBDCore_Transfer_TypeDef Parameter for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.uBuffer[2] Temporary buffer */ +/* USBCore.Device.Transfer.pData Pointer of control IN/OUT Data */ +/* USBCore.Device.Transfer.sByteLength Total length for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.Action - USBDCore_Action_Enum STALL, control IN or control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.func(uPara) Call back function pointer for Control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.uPara Parameter of Control OUT call back function */ +/* */ +/* USBCore.Info - USBDCore_Info_TypeDef USB Device information */ +/* USBCore.Info.uCurrentConfiguration For Set/GetConfiguration request */ +/* USBCore.Info.uCurrentInterface For Set/GetInterface request */ +/* USBCore.Info.CurrentStatus - USBDCore_Status_Enum Device State */ +/* USBCore.Info.LastStatus - USBDCore_Status_Enum Device State before SUSPEND */ +/* USBCore.Info.CurrentFeature - USBDCore_Feature_TypeDef For Set/ClearFeature and GetStatus request */ +/* USBCore.Info.CurrentFeature.uByte Byte access for CurrentFeature */ +/* USBCore.Info.CurrentFeature.Bits.bRemoteWakeup Remote Wakeup feature */ +/* USBCore.Info.CurrentFeature.Bits.bSelfPowered Self Powered */ +/* USBCore.Info.uIsDiscardClearFeature Discard ClearFeature flag for Mass Storage */ +/* */ +/* USBCore.Class - USBDCore_Class_TypeDef USB Class call back function */ +/* USBCore.Class.CallBack_MainRoutine.func(uPara) Class main routine call back function */ +/* USBCore.Class.CallBack_MainRoutine.uPara Parameter of class main routine */ +/* USBCore.Class.CallBack_Reset.func(uPara) Class RESET call back function */ +/* USBCore.Class.CallBack_Reset.uPara Parameter of RESET call back function */ +/* USBCore.Class.CallBack_StartOfFrame.func(uPara) Class SOF call back function */ +/* USBCore.Class.CallBack_StartOfFrame.uPara Parameter of SOF call back function */ +/* USBCore.Class.CallBack_ClassGetDescriptor(pDev) Class Get Descriptor call back function */ +/* USBCore.Class.CallBack_ClassSetInterface(pDev) Set Interface call back function */ +/* USBCore.Class.CallBack_ClassGetInterface(pDev) Get Interface call back function */ +/* USBCore.Class.CallBack_ClassRequest(pDev) Class Request call back function */ +/* USBCore.Class.CallBack_EPTn[MAX_EP_NUM](EPTn) Endpoint n call back function */ +/* */ +/* USBCore.pDriver USB Device Driver initialization structure */ +/* */ +/* USBCore.Power - USBDCore_Power_TypeDef USB Device Power related call back function */ +/* USBCore.Power.CallBack_Suspend.func(uPara) System low power function for SUSPEND */ +/* USBCore.Power.CallBack_Suspend.uPara Parameter of system low power function */ +/*----------------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Constant USB Device Core exported constants + * @{ + */ + +/** @defgroup USBDCore_Descriptor Definitions for USB descriptor + * @{ + */ +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define DESC_TYPE_04_INF (0x4) +#define DESC_TYPE_05_EPT (0x5) +#define DESC_TYPE_06_DEV_QLF (0x6) +#define DESC_TYPE_08_INF_PWR (0x8) + +#define DESC_CLASS_00_BY_INF (0x00) +#define DESC_CLASS_01_AUDIO (0x01) +#define DESC_CLASS_02_CDC_CTRL (0x02) +#define DESC_CLASS_03_HID (0x03) +#define DESC_CLASS_05_PHY (0x05) +#define DESC_CLASS_06_STILL_IMG (0x06) +#define DESC_CLASS_07_PRINTER (0x07) +#define DESC_CLASS_08_MASS_STORAGE (0x08) +#define DESC_CLASS_09_HUB (0x09) +#define DESC_CLASS_0A_CDC_DATA (0x0A) +#define DESC_CLASS_0B_SMART_CARD (0x0B) +#define DESC_CLASS_0E_VIDEO (0x0E) +#define DESC_CLASS_0F_PHD (0x0F) +#define DESC_CLASS_FF_VENDOR (0xFF) + +#define DESC_LEN_DEV ((u32)(18)) +#define DESC_LEN_CONFN ((u32)(9)) +#define DESC_LEN_INF ((u32)(9)) +#define DESC_LEN_EPT ((u32)(7)) +/** + * @} + */ + +/** @defgroup USBDCore_Request Definitions for USB Request + * @{ + */ +#define REQ_DIR_00_H2D (0 << 7) +#define REQ_DIR_01_D2H (1 << 7) + +#define REQ_TYPE_00_STD (0 << 5) +#define REQ_TYPE_01_CLS (1 << 5) +#define REQ_TYPE_02_VND (2 << 5) + +#define REQ_REC_00_DEV (0) +#define REQ_REC_01_INF (1) +#define REQ_REC_02_EPT (2) +/** + * @} + */ + +/** + * @brief For USBDCore_EPTReadOUTData function. + */ +#define USB_DISCARD_OUT_DATA (0) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Macro USB Device Core exported macros + * @{ + */ +#define __DBG_USBPrintf(...) +#define __DBG_USBDump(a, b) + +#if (USBDCORE_DEBUG == 1) + #ifndef RETARGET_IS_USB + extern u32 __DBG_USBCount; + #undef __DBG_USBPrintf + #define __DBG_USBPrintf printf + #if (USBDCORE_DEBUG_DATA == 1) + #undef __DBG_USBDump + void __DBG_USBDump(uc8 *memory, u32 len); + #endif + #endif +#endif + +/** + * @brief Convert Half-Word to Byte for descriptor. + */ +#define DESC_H2B(Val) ((u8)(Val & 0x00FF)), ((u8)((Val & 0xFF00) >> 8)) + +/** + * @brief Padding 0 automatically for String descriptor. + */ +#define DESC_CHAR(c) (c), (0) + +/** + * @brief Calculate String length for String descriptor. + */ +#define DESC_STRLEN(n) (n * 2 + 2) + +/** + * @brief Calculate power for Configuration descriptor. + */ +#define DESC_POWER(mA) (mA / 2) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +#define USBDCore_DeInit API_USB_DEINIT +#define USBDCore_EPTReset API_USB_EPTn_RESET +#define USBDCore_EPTGetBufferLen API_USB_EPTn_GET_BUFFLEN +#define USBDCore_EPTGetTransferCount API_USB_EPTn_GET_CNT +#define USBDCore_EPTSetSTALL API_USB_EPTn_SET_HALT +#define USBDCore_EPTWaitSTALLSent API_USB_EPTn_WAIT_STALL_SENT +#define USBDCore_EPTClearDataToggle API_USB_EPTn_CLR_DTG + +#define USBDCore_EPTWriteINData API_USB_EPTn_WRITE_IN +#define USBDCore_EPTReadOUTData API_USB_EPTn_READ_OUT +#define USBDCore_EPTReadMemory API_USB_EPTn_READ_MEM + + +void usbd_irq_handler(USBDCore_TypeDef *pCore); +void USBDCore_Init(USBDCore_TypeDef *pCore); +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore); + +void usbd_ep_enable(USBDCore_TypeDef *pCore, uint8_t ept_addr); +void usbd_ep_disable(USBDCore_TypeDef *pCore, uint8_t ept_addr); +void usbd_ept_recv(USBDCore_TypeDef *udev, uint8_t ept_addr, uint8_t *buffer, uint16_t len); +//u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore); +//u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore); +//void USBDCore_TriggerRemoteWakeup(void); +//USBDCore_Status_Enum USBDCore_GetStatus(void); + +void USBDCore_EPTReset(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum type); +void USBDCore_EPTSetSTALL(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTClearDataToggle(USBD_EPTn_Enum USBD_EPTn); + +u32 USBDCore_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBDCore_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBDCore_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CODE_H -------------------------------------------------------------------------------*/ + diff --git a/bsp/ht32/libraries/usbd_library/src/ht32_usbd_core.c b/bsp/ht32/libraries/usbd_library/src/ht32_usbd_core.c new file mode 100644 index 0000000000..e7a488ce2e --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/src/ht32_usbd_core.c @@ -0,0 +1,1069 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.c + * @version $Rev:: 1684 $ + * @date $Date:: 2019-05-07 #$ + * @brief The standard protocol related function of HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "usb_port.h" + + +#ifdef USBD_VENDOR_SUPPORT + #include "ht32_usbd_vendor.c" +#endif + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDCore USB Device Core + * @brief USB Device Core standard protocol related function + * @{ + */ + + +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_TypesDefinitions USB Device Core private types definitions + * @{ + */ +typedef enum +{ + Device = 0, + Interface = 1, + Endpoint = 2, + Other = 3, +} USBDCore_Recipient_Enum; + +typedef enum +{ + ClearFeature = 0, + SetFeature = 1, +} USBDCore_SetClearFeature_Enum; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Define USB Device Core private definitions + * @{ + */ +/* USBD Debug mode */ +#if (USBDCORE_DEBUG == 1) + #ifdef RETARGET_IS_USB + #warning "USB debug mode can not work when retaget to USB Virtual COM. Turn off automatically." + #undef USBDCORE_DEBUG + #define USBDCORE_DEBUG 0 + #else + u32 __DBG_USBCount; + #warning "USB debug mode has been enabled which degrade the performance." + #warning "After the debug operation, please remember to turn off USB debug mode." + #endif +#endif + +/** @defgroup USBDCore_STD Definition for standard request + * @{ + */ +#define REQ_00_GET_STAT ((u16)(0 << 8)) +#define REQ_01_CLR_FETU ((u16)(1 << 8)) +#define REQ_03_SET_FETU ((u16)(3 << 8)) +#define REQ_05_SET_ADDR ((u16)(5 << 8)) +#define REQ_06_GET_DESC ((u16)(6 << 8)) +#define REQ_07_SET_DESC ((u16)(7 << 8)) +#define REQ_08_GET_CONF ((u16)(8 << 8)) +#define REQ_09_SET_CONF ((u16)(9 << 8)) +#define REQ_10_GET_INF ((u16)(10 << 8)) +#define REQ_11_SET_INF ((u16)(11 << 8)) +#define REQ_12_SYN_FRME ((u16)(12 << 8)) +/** + * @} + */ + +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define USB_NO_DATA (-1) /*!< For Device.Transfer.sByteLength */ +#define BMREQUEST_TYPE_MASK (0x6 << 4) /*!< bmRequestType[6:5] */ +#define USB_FEATURE_REMOTE_WAKEUP (1) + +#define MAX_CONTROL_OUT_SIZE (64) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore); +static void _USBDCore_Reset(USBDCore_TypeDef *pCore); +static void _USBDCore_Resume(USBDCore_TypeDef *pCore); +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore); +static void _USBDCore_Setup(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient); +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient, USBDCore_SetClearFeature_Enum type); +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Macro USB Device Core private macros + * @{ + */ +/** + * @brief Get self powered bit from Device descriptor + */ +#define _GET_SELFPOWERED_FROM_DESC() (((pCore->Device.Desc.pConfnDesc[7]) >> 6) & 0x01) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Variable USB Device Core private variables + * @{ + */ +USBDCore_TypeDef *pUSBCore; +/** + * @} + */ + + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core initialization. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_Init(USBDCore_TypeDef *pCore) +{ + pUSBCore = pCore; + pCore->Info.CurrentStatus = USER_USER_USB_STATE_POWERED; + API_USB_INIT(pCore->pDriver); + __DBG_USBPrintf("\r\n%06ld \r\n", ++__DBG_USBCount); + return; +} + +/*********************************************************************************************************//** + * @brief USB Interrupt Service Routine. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore) +{ + u32 USBISRFlag = API_USB_GET_INT(); + u32 USBEPTISRFlag; + USBD_EPTn_Enum EPTn; + +#if (USBDCORE_DEBUG == 1) + u32 USBAddr = HT_USB->DEVAR; +#endif + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SOF Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SOF_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SOF[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + if (pCore->Class.CallBack_StartOfFrame.func != NULL) + { + pCore->Class.CallBack_StartOfFrame.func(pCore->Class.CallBack_StartOfFrame.uPara); + } + + usbd_sof_callback(pCore); + + API_USB_CLR_SOF_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SUSPEND Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SUSPEND_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SUSPEND[%02d]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus); + API_USB_CLR_SUSPEND_INT(); + _USBDCore_Suspend(pCore); + +// usbd_suspend_callback(pCore); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESET Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESET_INT(USBISRFlag)) + { + if (API_USB_IS_FRES_INT(USBISRFlag)) + { + API_USB_CLR_FRES_INT(); + } + else + { + __DBG_USBPrintf("%06ld RESET[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + _USBDCore_Reset(pCore); + if (pCore->Class.CallBack_Reset.func != NULL) + { + pCore->Class.CallBack_Reset.func(pCore->Class.CallBack_Reset.uPara); + } + + usbd_reset_callback(pCore); + } + API_USB_CLR_RESET_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESUME Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESUME_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld RESUME\r\n", ++__DBG_USBCount); + _USBDCore_Resume(pCore); + +// usbd_resume_callback(pCore); + + API_USB_CLR_RESUME_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint 0 interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_EPTn_INT(USBISRFlag, USBD_EPT0)) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT(USBD_EPT0); + + /*------------------------------------------------------------------------------------------------------*/ + /* Control SETUP Stage */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SETUP_INT(USBEPTISRFlag)) + { + API_USB_READ_SETUP(&(pCore->Device.Request)); /* Read SETUP Command data from USB Buffer*/ + + __DBG_USBPrintf("%06ld SETUP\t[08]\r\n", ++__DBG_USBCount); + __DBG_USBDump((uc8 *) & (pCore->Device.Request), 8); + +// _USBDCore_Setup(pCore); + + usbd_setup_callback(pCore); + + API_USB_CLR_SETUP_INT(); /* Clear SETUP Interrupt */ + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 IN */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_IN_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + +// _USBDCore_ControlIN(pCore); + + usbd_ep0_in_callback(pCore); + + API_USB_EPTn_CLR_IN_INT(USBD_EPT0); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 OUT */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_OUT_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0OUT\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + /*----------------------------------------------------------------------------------------------------*/ + /* Clear interrupt flag before USBDCore_ControlOUT is meaning since USBDCore_ControlOUT clear NAKRX */ + /* bit which will cause another interrupt occur. */ + /*----------------------------------------------------------------------------------------------------*/ + API_USB_EPTn_CLR_OUT_INT(USBD_EPT0); +// _USBDCore_ControlOUT(pCore); + + usbd_ep0_out_callback(pCore); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Clear Control Endpoint 0 global interrupt */ + /*------------------------------------------------------------------------------------------------------*/ + API_USB_CLR_EPTn_INT(USBD_EPT0); + + } /* if (API_USB_IS_EP_INT(USBISRFlag, USBD_EPT0)) */ + + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint n call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + while ((EPTn = API_USB_GET_EPT_NUM(API_USB_GET_INT())) != USBD_NOEPT) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT((USBD_EPTn_Enum)EPTn); + + if (API_USB_EPTn_IS_INT(USBEPTISRFlag)) + { + API_USB_EPTn_CLR_INT(EPTn); + API_USB_CLR_EPTn_INT(EPTn); + + if (pCore->Class.CallBack_EPTn[EPTn] != NULL) + { + pCore->Class.CallBack_EPTn[EPTn](EPTn); + } + /* 在此处调用端点输入输出回调函数*/ + if (USBEPTISRFlag & IDTXIF) + { + /* 在此处调用端点输入函数 */ + usbd_ep_in_callback(pCore, (USBD_EPTn_Enum)EPTn); + } + else + { + /* 在此处调用端点输出函数 */ + usbd_ep_out_callback(pCore, (USBD_EPTn_Enum)EPTn); + } + + } + } /* while ((EPTn = API_USB_GET_EPTn_NUM(API_USB_GET_INT())) != USBD_NOEPT) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Core Main Routine for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore) +{ + _USBDCore_PowerHandler(pCore); + + /*--------------------------------------------------------------------------------------------------------*/ + /* Class main routine call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + if ((pCore->Class.CallBack_MainRoutine.func != NULL) && (pCore->Info.CurrentStatus == USER_USER_USB_STATE_CONFIGURED)) + { + pCore->Class.CallBack_MainRoutine.func(pCore->Class.CallBack_MainRoutine.uPara); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Return Suspend status + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore) +{ + return ((pCore->Info.CurrentStatus == USER_USER_USB_STATE_SUSPENDED) ? TRUE : FALSE); +} + +/*********************************************************************************************************//** + * @brief Return remote wake status which set by SET FEATURE standard command + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore) +{ + return (pCore->Info.CurrentFeature.Bits.bRemoteWakeup); +} + +/*********************************************************************************************************//** + * @brief Turn on USB power and remote wakeup the Host + * @retval None + ***********************************************************************************************************/ +void USBDCore_TriggerRemoteWakeup(void) +{ + API_USB_POWER_ON(); /* Turn on USB Power */ + API_USB_REMOTE_WAKEUP(); /* Generate Remote Wakeup request to Host (RESUME) */ + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Device status + * @retval USBDCore_Status_Enum + ***********************************************************************************************************/ +USBDCore_Status_Enum USBDCore_GetStatus(void) +{ + return pUSBCore->Info.CurrentStatus; +} + +/*********************************************************************************************************//** + * @brief Dump memory data for debug purpose. + * @param memory: buffer pointer to dump + * @param len: dump length + * @retval None + ***********************************************************************************************************/ +#if (USBDCORE_DEBUG == 1 && USBDCORE_DEBUG_DATA == 1) +void __DBG_USBDump(uc8 *memory, u32 len) +{ + u32 i; + for (i = 0; i < len; i++) + { + if (i % 8 == 0) + { + if (i != 0) + { + __DBG_USBPrintf("\r\n"); + } + __DBG_USBPrintf("\t\t"); + } + __DBG_USBPrintf("%02X ", *((u8 *)(memory + i))); + } + __DBG_USBPrintf("\r\n"); + + return; +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Function USB Device Core private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core Power handler for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_UP(pCore->pDriver, pCore->Info.CurrentFeature.Bits.bSelfPowered); + + if (pCore->Info.CurrentStatus == USER_USER_USB_STATE_SUSPENDED) + { + /*------------------------------------------------------------------------------------------------------*/ + /* System Low Power call back function */ + /*------------------------------------------------------------------------------------------------------*/ + if (pCore->Power.CallBack_Suspend.func != NULL) + { + __DBG_USBPrintf("%06ld >LOWPOWER\r\n", ++__DBG_USBCount); + + pCore->Power.CallBack_Suspend.func(pCore->Power.CallBack_Suspend.uPara); + + __DBG_USBPrintf("%06ld pDriver; + + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Info.uCurrentConfiguration = 0; + pCore->Info.uCurrentInterface = 0; + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = 0; + pCore->Info.CurrentStatus = USER_USER_USB_STATE_DEFAULT; + pCore->Info.uIsDiscardClearFeature = FALSE; + + API_USB_DEINIT(); + + API_USB_POWER_ON(); + + /* Endpoint 0 initialization */ + API_USB_EPTn_INIT(USBD_EPT0, pCore->pDriver); // To be modify, init from desc + + /* Enable USB interrupt */ + API_USB_ENABLE_INT(pDrv->uInterruptMask); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Resume + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Resume(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_ON(); + pCore->Info.CurrentStatus = pCore->Info.LastStatus; + return; +} + +/*********************************************************************************************************//** + * @brief USB Suspend + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore) +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* When Device has been suspended, Change CurrentStatus as SUSPEND and then USBDCore_PowerHandler will */ + /* turn off chip power. */ + /*--------------------------------------------------------------------------------------------------------*/ + if (pCore->Info.CurrentStatus >= USER_USER_USB_STATE_POWERED) + { + API_USB_POWER_OFF(); + pCore->Info.LastStatus = pCore->Info.CurrentStatus; + pCore->Info.CurrentStatus = USER_USER_USB_STATE_SUSPENDED; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Setup Stage + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Setup(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.Action = USB_ACTION_STALL; + pCore->Device.Transfer.sByteLength = 0; + + switch (pCore->Device.Request.bmRequestType & BMREQUEST_TYPE_MASK) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Standard requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_00_STD: + { + _USBDCore_Standard_Request(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Class requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_01_CLS: + { + if (pCore->Class.CallBack_ClassRequest != NULL) + { + pCore->Class.CallBack_ClassRequest(&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Vendor requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_02_VND: + { + if (pCore->Class.CallBack_VendorRequest != NULL) + { + pCore->Class.CallBack_VendorRequest(&(pCore->Device)); + } + /* Add Vendor requests handler here.... */ +#ifdef USBD_VENDOR_SUPPORT + USBDVendor_Request(pCore); +#endif + break; + } + } /* switch (gUSBReq.bmRequestType.byte) */ + + switch (pCore->Device.Transfer.Action) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Control IN */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAIN: + { + /*----------------------------------------------------------------------------------------------------*/ + /* When the Control IN length is large than the Host required, transfer the length which specified */ + /* by SETUP Data Packet. */ + /*----------------------------------------------------------------------------------------------------*/ + if (pCore->Device.Transfer.sByteLength > pCore->Device.Request.wLength) + { + pCore->Device.Transfer.sByteLength = pCore->Device.Request.wLength; + } + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", __DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Control OUT */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAOUT: + { + if (pCore->Device.Transfer.sByteLength == 0) + { + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); /* Prepare ZLP ack for Control OUT */ + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* STALL */ + /*------------------------------------------------------------------------------------------------------*/ + default: + { + __DBG_USBPrintf("%06ld EP0 STALL\r\n", __DBG_USBCount); + + API_USB_EPTn_SEND_STALL(USBD_EPT0); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Stand Request. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore) +{ + u16 USBCmd = *((u16 *)(&(pCore->Device.Request))); + + switch (USBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 0_Device | 0080h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DST\t[%02d]\r\n", __DBG_USBCount, pCore->Info.CurrentFeature.uByte); + _USBDCore_Standard_GetStatus(pCore, Device); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0081h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IST\t[%02d]\r\n", __DBG_USBCount, 0); + _USBDCore_Standard_GetStatus(pCore, Interface); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 2_Endpoint | 0082h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld GET EST\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_GetStatus(pCore, Endpoint); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0100h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld CLR DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0102h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld CLR EFEA\t[0x%02x]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0300h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0302h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld SET EFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 05_Set Address | 00_Host-to-Device | 00_Standard Request | 0_Device | 0500h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_05_SET_ADDR | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET ADDR\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetAddress(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 0_Device | 0680h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + _USBDCore_Standard_GetDescriptor(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0681h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + if (pCore->Class.CallBack_ClassGetDescriptor != NULL) + { + pCore->Class.CallBack_ClassGetDescriptor((USBDCore_Device_TypeDef *) & (pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 08_Get Configuration | 80_Host-to-Device | 00_Standard Request | 0_Device | 0880h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_08_GET_CONF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Info.uCurrentConfiguration); + _USBDCore_Standard_GetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 09_Set Configuration | 00_Host-to-Device | 00_Standard Request | 0_Device | 0900h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_09_SET_CONF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 11_Set Interface | 00_Host-to-Device | 00_Standard Request | 1_Interface | 0B01h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_11_SET_INF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld SET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassSetInterface != NULL) + { + pCore->Class.CallBack_ClassSetInterface((USBDCore_Device_TypeDef *) & (pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 10_Get Interface | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0A81h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_10_GET_INF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassGetInterface != NULL) + { + pCore->Class.CallBack_ClassGetInterface((USBDCore_Device_TypeDef *) & (pCore->Device)); + } + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_STATUS. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient) +{ + pCore->Device.Transfer.uBuffer[1] = 0; + switch (recipient) + { + case Device: + { + pCore->Device.Transfer.uBuffer[0] = pCore->Info.CurrentFeature.uByte; + break; + } + case Interface: + { + pCore->Device.Transfer.uBuffer[0] = 0; + break; + } + case Endpoint: + { + pCore->Device.Transfer.uBuffer[0] = API_USB_EPTn_GET_HALT((USBD_EPTn_Enum)(pCore->Device.Request.wIndex & 0xF)); + break; + } + default: + { + return; + } + } + + pCore->Device.Transfer.pData = (uc8 *) & (pCore->Device.Transfer.uBuffer); + pCore->Device.Transfer.sByteLength = 2; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_FEATURE / CLEAR_FEATURE. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @param type: + * @arg ClearFeature: 0 + @arg SerFeature: 1 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, + USBDCore_Recipient_Enum recipient, + USBDCore_SetClearFeature_Enum type) +{ + u32 i; + switch (recipient) + { + case Device: + { + if (pCore->Device.Request.wValueL == USB_FEATURE_REMOTE_WAKEUP) + { + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = type; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + break; + } + case Endpoint: + { + i = pCore->Device.Request.wIndex & 0xF; + if (i != 0) + { + if (type == ClearFeature) + { + if (pCore->Info.uIsDiscardClearFeature == FALSE) + { + API_USB_EPTn_CLR_HALT((USBD_EPTn_Enum)i); + API_USB_EPTn_CLR_DTG((USBD_EPTn_Enum)i); + } + } + else + { + API_USB_EPTn_SET_HALT((USBD_EPTn_Enum)i); + } + } + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + default: + { + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_ADDRESS. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore) +{ + API_USB_SET_ADDR(pCore->Device.Request.wValueL); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + pCore->Info.CurrentStatus = USER_USER_USB_STATE_ADDRESS; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_DESCRIPTOR. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore) +{ + u32 value = pCore->Device.Request.wValueH; + uc8 *pTemp; + + switch (value) + { + case DESC_TYPE_01_DEV: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pDeviceDesc; + pCore->Device.Transfer.sByteLength = *(pCore->Device.Desc.pDeviceDesc); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_CONFN: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pConfnDesc; + pCore->Device.Transfer.sByteLength = *(u16 *)((pCore->Device.Desc.pConfnDesc) + 2); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_03_STR: + { + value = pCore->Device.Request.wValueL; + if (value < pCore->Device.Desc.uStringDescNumber) + { + if (*(pCore->Device.Desc.ppStringDesc + value) != NULL) + { + pTemp = *(pCore->Device.Desc.ppStringDesc + value); + pCore->Device.Transfer.pData = (uc8 *)(pTemp); + pCore->Device.Transfer.sByteLength = *(pTemp); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + } + break; + } + } + +#ifdef USBD_VENDOR_SUPPORT + USBDVendor_StandardGetDescriptor(pCore); +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.pData = &(pCore->Info.uCurrentConfiguration); + pCore->Device.Transfer.sByteLength = 1; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore) +{ + u32 i; + + pCore->Info.uCurrentConfiguration = pCore->Device.Request.wValueL; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + /* Endpoint n settings */ + for (i = 1; i < MAX_EP_NUM; i++) + { + API_USB_EPTn_INIT((USBD_EPTn_Enum)i, pCore->pDriver); // To be modify, init from desc + } + + pCore->Info.CurrentStatus = USER_USER_USB_STATE_CONFIGURED; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control IN transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore) +{ + s32 EP0INLen = API_USB_GET_CTRL_IN_LEN(); + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAIN) + { + if (pCore->Device.Transfer.sByteLength >= EP0INLen) + { + len = EP0INLen; + pCore->Device.Transfer.sByteLength -= len; + } + else + { + len = pCore->Device.Transfer.sByteLength; + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Device.Transfer.Action = USB_ACTION_DATAOUT; + } + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, len); + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control OUT transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore) +{ + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAOUT) + { + len = API_USB_EPTn_READ_OUT(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, MAX_CONTROL_OUT_SIZE); + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + pCore->Device.Transfer.sByteLength -= len; + + if (pCore->Device.Transfer.sByteLength == 0) + { + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + if (pCore->Device.Transfer.CallBack_OUT.func != NULL) + { + pCore->Device.Transfer.CallBack_OUT.func(pCore->Device.Transfer.CallBack_OUT.uPara); + pCore->Device.Transfer.CallBack_OUT.func = NULL; + } + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); + } + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/usbd_library/src/ht32_usbd_int.c b/bsp/ht32/libraries/usbd_library/src/ht32_usbd_int.c new file mode 100644 index 0000000000..8999a00c52 --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/src/ht32_usbd_int.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-11 QT-one first version + */ + +#include "ht32_usbd_int.h" + +#ifdef RT_USING_USB_DEVICE +//#include "ht32_usbd_core.h" + + + +static void USBPLL_Configuration(void); +static void USBVRG_Configuration(void); +static void Suspend(u32 uPara); + + +static USBDCore_TypeDef *int_p_usbd_code; +static USBD_Driver_TypeDef gUSBDriver; +static u32 gIsLowPowerAllowed = TRUE; + +/* + 为了不破坏原本的usb_code文件中的USB中断回调函数 + 此处重构USB中断回调函数 + 除了重构USB的中断回调函数以外，还需要重写一些中断回调功能函数 +*/ +/* + RTT的USB中断回调过程如下 + USB中断函数 -> USB中断回调函数 -> USB相关功能回调函数 + -> RTT的USB相关功能回调函数 -> 结束USB中断 + + RTT的USB程序运行流程（RTT的USB线程运行流程） + USB线程阻塞等待USB获取到消息队列中的消息 + -> USB中断通过回调函数将接收到的消息传给USB的消息队列 + -> RTT的USB相关功能回调函数获取到USB中断的消息，并设置USB消息队列的状态 + -> USB退出中断，USB获取到消息后，线程阻塞被解除 + -> USB线程根据获取的状态执行对应的功能 + -> USB线程通过USB操作接口实现对应的功能 + +*/ +/* + 根据RTT的USB中断回调过程和RTT的USB线程执行过程 + 得出完成USB驱动需要实现的两个重要部分 + 1、USB线程实现功能所需要的调用到的USB操作接口函数 + 2、USB中断回调过程使用到的RTT的USB驱动的函数的相关衔接部分 + + 除了以上两个比较重要的功能外，还需要完成以下的一些必要部分 + 1、USB初始化函数 + 2、USB设备注册函数 + + 完成以上功能主要涉及到两个文件为： + 1、drv_usbd.c + 2、ht32_usbd_int.c + + 对两个文件的内容分配以及文件依赖如下： + drv_usbd.c + 主要负责实现USB的操作接口的实现 + 以及初始化函数和USB设备注册函数 + 由于自定义的USB内核挂载点在该文件中 + 所以USB的中断函数也会写在该文件中 + 依赖： + ht32_usbd_core.c + ht32_usbd_int.c + 以及RTT的相关文件 + + ht32_usbd_int.c + 主要负责实现USB中断回调以及回调函数 + 中和RTT的USB驱动函数相关衔接部分 + 该文件还会包含USB的初始配置函数以及 + USB的休眠与唤醒的相关函数 + 依赖： + ht32_usbd_core.c + 以及RTT的相关文件 +*/ + +/* 帧起始（SOF）中断回调 */ +void usbd_sof_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_sof_handler(udcd); +} +/* USB复位中断 */ +void usbd_reset_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_reset_handler(udcd); +} + +/* USB暂停(断开连接)中断 */ +void usbd_suspend_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_disconnect_handler(udcd); +} + +/* USB恢复（重新连接）中断 */ +void usbd_resume_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_connect_handler(udcd); +} + +/* USB端点0中断 */ +/* 端点0控制中断 */ +void usbd_setup_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep0_setup_handler(udcd, (struct urequest *)&pCore->Device.Request); +} + +/* 端点0输入中断（可以归入其他端点输入中断） */ +void usbd_ep0_in_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep0_in_handler(udcd); +} + +/* 端点0输出中断（可以归入其他端点输出中断） */ +void usbd_ep0_out_callback(USBDCore_TypeDef *pCore) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep0_out_handler(udcd, pCore->Device.Transfer.sByteLength); +} + +/* USB其他端点中断 */ +/* 其他端点输入中断 */ +void usbd_ep_in_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep_in_handler(udcd, EPTn | 0x80, pCore->Device.Transfer.sByteLength); +} + +/* 其他端点输出中断 */ +void usbd_ep_out_callback(USBDCore_TypeDef *pCore, USBD_EPTn_Enum EPTn) +{ + udcd_t udcd = (udcd_t)pCore->pdata; + rt_usbd_ep_out_handler(udcd, EPTn, pCore->Device.Transfer.sByteLength); +} + + + + +//rt_err_t rt_usbd_set_feature(udevice_t device, rt_uint16_t value, rt_uint16_t index); +//rt_err_t rt_usbd_clear_feature(udevice_t device, rt_uint16_t value, rt_uint16_t index); +//rt_err_t rt_usbd_ep_set_stall(udevice_t device, uep_t ep); +//rt_err_t rt_usbd_ep_clear_stall(udevice_t device, uep_t ep); +//rt_err_t rt_usbd_ep0_set_stall(udevice_t device); +//rt_err_t rt_usbd_ep0_clear_stall(udevice_t device); + + +/*********************************************************************************************************//** + * @brief Configure USB. + * @retval None + ***********************************************************************************************************/ +static void USB_Configuration(USBDCore_TypeDef *pCore) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.USBD = 1; + CKCUClock.Bit.EXTI = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + int_p_usbd_code = pCore; + +#if (LIBCFG_CKCU_USB_PLL) + USBPLL_Configuration(); +#endif + +#if (LIBCFG_PWRCU_VREG) + USBVRG_Configuration(); /* Voltage of USB setting */ +#endif + + pCore->pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ + pCore->Power.CallBack_Suspend.func = Suspend; /* Install suspend call back function into USB core */ + +// gUSBCore.pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ +// gUSBCore.Power.CallBack_Suspend.func = Suspend; /* Install suspend call back function into USB core */ + //gUSBCore.Power.CallBack_Suspend.uPara = (u32)NULL; + + /* 描述符初始化 */ +// USBDDesc_Init(&pCore->Device.Desc); /* Initiate memory pointer of descriptor */ + /* USB类初始化 */ +// USBDClass_Init(&(pCore->Class)); /* Initiate USB Class layer */ + /* USB内核初始化 */ + USBDCore_Init(pCore); /* Initiate USB Core layer */ + + /* !!! NOTICE !!! + Must turn on if the USB clock source is from HSI (PLL clock Source) + */ +#if 0 + { + /* Turn on HSI auto trim function */ + CKCU_HSIAutoTrimClkConfig(CKCU_ATC_USB); + CKCU_HSIAutoTrimCmd(ENABLE); + } +#endif + + NVIC_EnableIRQ(USB_IRQn); /* Enable USB device interrupt */ +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Configure USB PLL + * @retval None + ************************************************************************************************************/ +static void USBPLL_Configuration(void) +{ + { + /* USB PLL configuration */ + + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + CKCU_PLLInitTypeDef PLLInit; + + PLLInit.ClockSource = CKCU_PLLSRC_HSE; // CKCU_PLLSRC_HSE or CKCU_PLLSRC_HSI +#if (LIBCFG_CKCU_USB_PLL_96M) + PLLInit.CFG = CKCU_USBPLL_8M_96M; +#else + PLLInit.CFG = CKCU_USBPLL_8M_48M; +#endif + PLLInit.BYPASSCmd = DISABLE; + CKCU_USBPLLInit(&PLLInit); + } + + CKCU_USBPLLCmd(ENABLE); + + while (CKCU_GetClockReadyStatus(CKCU_FLAG_USBPLLRDY) == RESET); + CKCU_USBClockConfig(CKCU_CKUSBPLL); +} +#endif + +#if (LIBCFG_PWRCU_VREG) +/*********************************************************************************************************//** + * @brief Configure USB Voltage + * @retval None + ************************************************************************************************************/ +static void USBVRG_Configuration(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.BKP = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + PWRCU_SetVREG(PWRCU_VREG_3V3); + + /* !!! NOTICE !!! + USB LDO should be enabled (PWRCU_VREG_ENABLE) if the MCU VDD > 3.6 V. + */ + PWRCU_VREGConfig(PWRCU_VREG_BYPASS); +} +#endif + +#define REMOTE_WAKEUP (0) +/*********************************************************************************************************//** + * @brief Suspend call back function which enter DeepSleep1 + * @param uPara: Parameter for Call back function + * @retval None + ***********************************************************************************************************/ +static void Suspend(u32 uPara) +{ +#if (REMOTE_WAKEUP == 1) + u32 IsRemoteWakeupAllowed; +#endif + + if (gIsLowPowerAllowed) + { + +#if (REMOTE_WAKEUP == 1) + /* Disable EXTI interrupt to prevent interrupt occurred after wakeup */ + EXTI_IntConfig(KEY1_BUTTON_EXTI_CHANNEL, DISABLE); + IsRemoteWakeupAllowed = USBDCore_GetRemoteWakeUpFeature(&gUSBCore); + + if (IsRemoteWakeupAllowed == TRUE) + { + /* Enable EXTI wake event and clear wakeup flag */ + EXTI_WakeupEventConfig(KEY1_BUTTON_EXTI_CHANNEL, EXTI_WAKEUP_LOW_LEVEL, ENABLE); + EXTI_ClearWakeupFlag(KEY1_BUTTON_EXTI_CHANNEL); + } +#endif + + __DBG_USBPrintf("%06ld >DEEPSLEEP\r\n", ++__DBG_USBCount); + + // Add your procedure here which disable related IO to reduce power consumption + // .................. + // + + if ((int_p_usbd_code->Info.CurrentStatus == USB_STATE_SUSPENDED) && ((HT_USB->CSR & 0xC0) == 0x40)) // D+ = 1, D- = 0 + { + /* For Bus powered device, you must enter DeepSleep1 when device has been suspended. For self-powered */ + /* device, you may decide to enter DeepSleep1 or not depended on your application. */ + + /* For the convenient during debugging and evaluation stage, the USBDCore_LowPower() is map to a null */ + /* function by default. In the real product, you must map this function to the low power function of */ + /* firmware library by setting USBDCORE_ENABLE_LOW_POWER as 1 (in the ht32fxxxx_usbdconf.h file). */ + USBDCore_LowPower(); + } + + // Add your procedure here which recovery related IO for application + // .................. + // + + __DBG_USBPrintf("%06ld 3.6 V. + */ + PWRCU_VREGConfig(PWRCU_VREG_BYPASS); +} +#endif + +#define REMOTE_WAKEUP (0) +/*********************************************************************************************************//** + * @brief Suspend call back function which enter DeepSleep1 + * @param uPara: Parameter for Call back function + * @retval None + ***********************************************************************************************************/ +static void Suspend(u32 uPara) +{ +#if (REMOTE_WAKEUP == 1) + u32 IsRemoteWakeupAllowed; +#endif + + if (gIsLowPowerAllowed) + { + +#if (REMOTE_WAKEUP == 1) + /* Disable EXTI interrupt to prevent interrupt occurred after wakeup */ + EXTI_IntConfig(KEY1_BUTTON_EXTI_CHANNEL, DISABLE); + IsRemoteWakeupAllowed = USBDCore_GetRemoteWakeUpFeature(&gUSBCore); + + if (IsRemoteWakeupAllowed == TRUE) + { + /* Enable EXTI wake event and clear wakeup flag */ + EXTI_WakeupEventConfig(KEY1_BUTTON_EXTI_CHANNEL, EXTI_WAKEUP_LOW_LEVEL, ENABLE); + EXTI_ClearWakeupFlag(KEY1_BUTTON_EXTI_CHANNEL); + } +#endif + + __DBG_USBPrintf("%06ld >DEEPSLEEP\r\n", ++__DBG_USBCount); + + // Add your procedure here which disable related IO to reduce power consumption + // .................. + // + + if ((gUSBCore->Info.CurrentStatus == USER_USB_STATE_SUSPENDED) && ((HT_USB->CSR & 0xC0) == 0x40)) // D+ = 1, D- = 0 + { + /* For Bus powered device, you must enter DeepSleep1 when device has been suspended. For self-powered */ + /* device, you may decide to enter DeepSleep1 or not depended on your application. */ + + /* For the convenient during debugging and evaluation stage, the USBDCore_LowPower() is map to a null */ + /* function by default. In the real product, you must map this function to the low power function of */ + /* firmware library by setting USBDCORE_ENABLE_LOW_POWER as 1 (in the ht32fxxxx_usbdconf.h file). */ + USBDCore_LowPower(); + } + + // Add your procedure here which recovery related IO for application + // .................. + // + + __DBG_USBPrintf("%06ld pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ + gUSBCore->Power.CallBack_Suspend.func = Suspend; /* Install suspend call back function into USB core */ + +// USBDDesc_Init(&gUSBCore.Device.Desc); /* Initiate memory pointer of descriptor */ +// USBDClass_Init(&gUSBCore.Class); /* Initiate USB Class layer */ + USBDCore_Init(gUSBCore); /* Initiate USB Core layer */ + + NVIC_SetPriority(USB_IRQn,0); + NVIC_EnableIRQ(USB_IRQn); /* Enable USB device interrupt */ + + HT32F_DVB_USBConnect(); + +} + + + + + + + + diff --git a/bsp/ht32/libraries/usbd_library/src/usbd_code.c b/bsp/ht32/libraries/usbd_library/src/usbd_code.c new file mode 100644 index 0000000000..33040e57eb --- /dev/null +++ b/bsp/ht32/libraries/usbd_library/src/usbd_code.c @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-09 QT-one first version + */ + +#include "usbd_code.h" +#include "usb_port.h" + +#include +#include +#include "drv_common.h" + +#if 1 + +#define USB_NO_DATA (-1) /*!< For Device.Transfer.sByteLength */ +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore); +static void _USBDCore_Reset(USBDCore_TypeDef *pCore); +static void _USBDCore_Resume(USBDCore_TypeDef *pCore); + +static void usbd_ept_init(USBDCore_TypeDef *udev); +/*********************************************************************************************************//** + * @brief USB Interrupt Service Routine. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void usbd_irq_handler(USBDCore_TypeDef *pCore) +{ + u32 USBISRFlag = API_USB_GET_INT(); + u32 USBEPTISRFlag; + USBD_EPTn_Enum EPTn; + +#if (USBDCORE_DEBUG == 1) + u32 USBAddr = HT_USB->DEVAR; +#endif + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SOF Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SOF_INT(USBISRFlag)) + { + usbd_sof_callback(pCore); + API_USB_CLR_SOF_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SUSPEND Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SUSPEND_INT(USBISRFlag)) + { + API_USB_CLR_SUSPEND_INT(); + usbd_suspend_callback(pCore); + _USBDCore_Suspend(pCore); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESET Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESET_INT(USBISRFlag)) + { + if (API_USB_IS_FRES_INT(USBISRFlag)) + { + API_USB_CLR_FRES_INT(); + } + else + { + usbd_reset_callback(pCore); + _USBDCore_Reset(pCore); + } + API_USB_CLR_RESET_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESUME Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESUME_INT(USBISRFlag)) + { + usbd_resume_callback(pCore); + _USBDCore_Resume(pCore); + API_USB_CLR_RESUME_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint 0 interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_EPTn_INT(USBISRFlag, USBD_EPT0)) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT(USBD_EPT0); + + /*------------------------------------------------------------------------------------------------------*/ + /* Control SETUP Stage */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SETUP_INT(USBEPTISRFlag)) + { + API_USB_READ_SETUP(&(pCore->Device.Request)); /* Read SETUP Command data from USB Buffer*/ + usbd_setup_callback(pCore); + API_USB_CLR_SETUP_INT(); /* Clear SETUP Interrupt */ + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 IN */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_IN_INT(USBEPTISRFlag)) + { + usbd_ep0_in_callback(pCore); + API_USB_EPTn_CLR_IN_INT(USBD_EPT0); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 OUT */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_OUT_INT(USBEPTISRFlag)) + { + /*----------------------------------------------------------------------------------------------------*/ + /* Clear interrupt flag before USBDCore_ControlOUT is meaning since USBDCore_ControlOUT clear NAKRX */ + /* bit which will cause another interrupt occur. */ + /*----------------------------------------------------------------------------------------------------*/ + API_USB_EPTn_CLR_OUT_INT(USBD_EPT0); + usbd_ep0_out_callback(pCore); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Clear Control Endpoint 0 global interrupt */ + /*------------------------------------------------------------------------------------------------------*/ + API_USB_CLR_EPTn_INT(USBD_EPT0); + + } /* if (API_USB_IS_EP_INT(USBISRFlag, USBD_EPT0)) */ + + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint n call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + while ((EPTn = API_USB_GET_EPT_NUM(API_USB_GET_INT())) != USBD_NOEPT) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT((USBD_EPTn_Enum)EPTn); + + if (API_USB_EPTn_IS_INT(USBEPTISRFlag)) + { + API_USB_EPTn_CLR_INT(EPTn); + API_USB_CLR_EPTn_INT(EPTn); + + if (USBEPTISRFlag & IDTXIF) + { + usbd_ep_in_callback(pCore, (USBD_EPTn_Enum)EPTn); + } + else + { + usbd_ep_out_callback(pCore, (USBD_EPTn_Enum)EPTn); + } + + } + } /* while ((EPTn = API_USB_GET_EPTn_NUM(API_USB_GET_INT())) != USBD_NOEPT) */ + + return; +} +/*********************************************************************************************************//** + * @brief USB Core initialization. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_Init(USBDCore_TypeDef *pCore) +{ + pCore->Info.CurrentStatus = USER_USB_STATE_POWERED; + API_USB_INIT(pCore->pDriver); + + /* Endpoint information initialisation */ + usbd_ept_init(pCore); + + return; +} +/*********************************************************************************************************//** + * @brief USB Core Main Routine for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_UP(pCore->pDriver, pCore->Info.CurrentFeature.Bits.bSelfPowered); + + if (pCore->Info.CurrentStatus == USER_USB_STATE_SUSPENDED) + { + /*------------------------------------------------------------------------------------------------------*/ + /* System Low Power call back function */ + /*------------------------------------------------------------------------------------------------------*/ + if (pCore->Power.CallBack_Suspend.func != NULL) + { + __DBG_USBPrintf("%06ld >LOWPOWER\r\n", ++__DBG_USBCount); + + pCore->Power.CallBack_Suspend.func(pCore->Power.CallBack_Suspend.uPara); + + __DBG_USBPrintf("%06ld Info.CurrentStatus >= USER_USB_STATE_POWERED) + { + API_USB_POWER_OFF(); + pCore->Info.LastStatus = pCore->Info.CurrentStatus; + pCore->Info.CurrentStatus = USER_USB_STATE_SUSPENDED; + } + + return; +} +/*********************************************************************************************************//** + * @brief USB Reset + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Reset(USBDCore_TypeDef *pCore) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pCore->pDriver; + + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Info.uCurrentConfiguration = 0; + pCore->Info.uCurrentInterface = 0; + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = 0; + pCore->Info.CurrentStatus = USER_USB_STATE_DEFAULT; + pCore->Info.uIsDiscardClearFeature = FALSE; + + API_USB_DEINIT(); + + API_USB_POWER_ON(); + + /* Endpoint 0 initialization */ + API_USB_EPTn_INIT(USBD_EPT0, pCore->pDriver); // To be modify, init from desc + + /* Enable USB interrupt */ + API_USB_ENABLE_INT(pDrv->uInterruptMask); + + return; +} +/*********************************************************************************************************//** + * @brief USB Resume + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Resume(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_ON(); + pCore->Info.CurrentStatus = pCore->Info.LastStatus; + return; +} +/****************************************************************************************************************************/ +void usbd_ep_enable(USBDCore_TypeDef *pCore, uint8_t ept_addr) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pCore->pDriver; + pDrv->ept[ept_addr & 0x7f].CFGR.bits.EPEN = 1; + API_USB_EPTn_INIT((USBD_EPTn_Enum)(ept_addr & 0x7f), pCore->pDriver); // To be modify, init from desc +} +void usbd_ep_disable(USBDCore_TypeDef *pCore, uint8_t ept_addr) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pCore->pDriver; + pDrv->ept[ept_addr & 0x7f].CFGR.bits.EPEN = 0; + API_USB_EPTn_INIT((USBD_EPTn_Enum)(ept_addr & 0x7f), pCore->pDriver); // To be modify, init from desc +} + +static void usbd_ept_init(USBDCore_TypeDef *udev) +{ + uint8_t ept_num = 0; + usb_ept_info *ept_info; + for (ept_num = 0; ept_num < 8; ept_num++) + { + ept_info = &udev->ept_io[ept_num]; + + ept_info->maxpacket = 64; + + ept_info->status = 1; + + ept_info->total_len = 0; + ept_info->trans_len = 0; + ept_info->trans_buf = NULL; + } +} +/** + * @brief usb endpoint receive data + * @param udev: to the structure of usbd_core_type + * @param ept_addr: endpoint number + * @param buffer: receive data buffer + * @param len: receive data length + * @retval none + */ +void usbd_ept_recv(USBDCore_TypeDef *udev, uint8_t ept_addr, uint8_t *buffer, uint16_t len) +{ + /* get endpoint info struct and register */ + usb_ept_info *ept_info = &udev->ept_io[ept_addr & 0x7F]; + uint32_t trs_len = 0; + + /* set receive data buffer and length */ + ept_info->trans_buf = buffer; + ept_info->total_len = len; + ept_info->trans_len = 0; + + if (ept_info->total_len > ept_info->maxpacket) + { + trs_len = ept_info->maxpacket; + ept_info->total_len -= trs_len; + } + else + { + trs_len = len; + ept_info->total_len = 0; + } + + ept_info->trans_len = trs_len; + /* set rx status valid */ + ept_info->status = TRUE; +} + +#endif /* BSP_USING_USBD */ diff --git a/bsp/ht32/tools/sdk_dist.py b/bsp/ht32/tools/sdk_dist.py index 49b2c2872a..01540d7ec6 100644 --- a/bsp/ht32/tools/sdk_dist.py +++ b/bsp/ht32/tools/sdk_dist.py @@ -37,3 +37,27 @@ def dist_do_building(BSP_ROOT, dist_dir): bsp_update_kconfig_library(dist_dir) +def get_source(ic_model, file_path, system_path, base_path): + source_path = [] + files_list = [] + readafter = 0 + if not os.path.isfile(file_path): + return + + with open(file_path, 'r') as file: + # content = file.read() + for line in file: + if readafter == 2 and line.find('>') != -1: + break + if readafter == 2: + files_list.append(line.strip()) + if line.find(ic_model) != -1: + readafter = 1 + if readafter == 1 and line.find('<') != -1: + readafter = 2 + for line in files_list: + if line.find('system') != -1: + source_path.append(os.path.join(system_path, line.strip())) + else: + source_path.append(os.path.join(base_path, line.strip())) + return source_path

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