Merge branch 'master' of https://github.com/RT-Thread/rt-thread into imx1050

2026-09-28 16:14:20 +08:00 · 2018-05-02 09:47:57 +08:00
parent aa86f7f7bb 795f9873cc
commit 313920126b
178 changed files with 13648 additions and 8669 deletions
@@ -28,6 +28,7 @@ env:
  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt1052-evk' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
 #  - RTT_BSP='bf533' # no scons
  - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' 
@@ -1,5 +1,7 @@
 # RT-Thread #

+[中文页](README_zh.md) |
+
 [![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
 [![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)

@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
        
    AFLAGS = ''
@@ -120,5 +120,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --semihosting' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -14,3 +14,24 @@ config TINA_USING_UART2
    bool "Using UART2"
    select RT_USING_SERIAL
    default y
+
+config TINA_USING_SDIO0
+    bool "Using SDIO0"
+    select RT_USING_SDIO
+    default y
+
+config TINA_USING_SPI0
+    bool "Using spi0"
+    select RT_USING_SPI
+    default y
+
+config TINA_USING_SPI1
+    bool "Using spi1"
+    select RT_USING_SPI
+    default y
+
+config TINA_USING_SPI_FLASH
+    bool "Using flash"
+    select TINA_USING_SPI0
+    select RT_USING_SFUD
+    default y
@@ -525,3 +525,89 @@ rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
    return RT_EOK;
 }

+rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
+{
+    unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+    volatile rt_uint32_t *mmc_clk = (clk_id == SDMMC0) ? \
+        (&CCU->sdmmc0_clk) : (&CCU->sdmmc1_clk);
+
+    if (hz < 0)
+    {
+        return RT_EINVAL;
+    }
+
+    if (hz == 0)
+    {
+        *mmc_clk &= ~(0x1 << 31);
+        return RT_EOK;
+    }
+    
+    if (hz <= 24000000)
+    {
+        pll = (0x0 << 24);
+        pll_hz = 24000000;
+    }
+    else
+    {
+        pll = (0x1 << 24);
+        pll_hz = periph_get_pll_clk();
+    }
+
+    div = pll_hz / hz;
+    if (pll_hz % hz)
+    {
+        div++;
+    }
+
+    n = 0;
+    while (div > 16)
+    {
+        n++;
+        div = (div + 1) / 2;
+    }
+
+    if (n > 3)
+    {
+        return -1;
+    }
+
+    /* determine delays */
+    if (hz <= 400000)
+    {
+        oclk_dly = 0;
+        sclk_dly = 0;
+    }
+    else if (hz <= 25000000)
+    {
+        oclk_dly = 0;
+        sclk_dly = 5;
+    }
+    else if (hz <= 50000000)
+    {
+        oclk_dly = 3;
+        sclk_dly = 4;
+    }
+    else
+    {
+        /* hz > 50000000 */
+        oclk_dly = 1;
+        sclk_dly = 4;
+    }
+    
+    *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
+           (n << 16) | (oclk_dly << 8) | (div - 1);
+
+    return RT_EOK;
+}
+
+rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate)
+{
+    CCU->dram_gating |= (0x01 << dram_gate);
+    return RT_EOK;
+}
+
+rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate)
+{
+    CCU->dram_gating &= ~(0x01 << dram_gate);
+    return RT_EOK;
+}
@@ -34,13 +34,6 @@
 #define CLK_PLL_SRC             (0x02)
 #define PRE_DIV_SRC             (0x03)

-/*  */
-#define BE_GATING_DRAM          (0x1<<26)
-#define FE_GATING_DRAM          (0x1<<24)
-#define TVD_GATING_DRAM         (0x1<<3)
-#define DEINTERLACE_GATING_DRAM (0x1<<2)
-#define CSI_GATING_DRAM         (0x1<<1)
-#define VE_GATING_DRAM          (0x1<<0)

 /*  */
 #define TCON_PLL_VIDEO_X1       (0x000)
@@ -142,6 +135,21 @@ enum bus_gate
    AUDIO_CODEC_GATING = (0x00 | (0x2 << BUS_GATE_OFFSET_BIT)),
 };

+enum dram_gate
+{
+    BE_GATING_DRAM          = 26,
+    FE_GATING_DRAM          = 24,
+    TVD_GATING_DRAM         = 3,
+    DEINTERLACE_GATING_DRAM = 2,
+    CSI_GATING_DRAM         = 1,
+    VE_GATING_DRAM          = 0
+};
+enum mmc_clk_id
+{
+    SDMMC0,
+    SDMMC1,
+};
+
 struct tina_ccu
 {
    volatile rt_uint32_t pll_cpu_ctrl;         /* 0x000 */
@@ -240,4 +248,8 @@ rt_err_t bus_gate_clk_disalbe(enum bus_gate bus);
 rt_err_t bus_software_reset_enalbe(enum bus_gate bus);
 rt_err_t bus_software_reset_disalbe(enum bus_gate bus);

+rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
+rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
+
+rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
 #endif
@@ -0,0 +1,180 @@
+/*
+ * File      : drv_sdio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+
+#define MMC0_BASE_ADDR     0x01C0F000
+#define MMC1_BASE_ADDR     0x01C10000
+
+struct tina_mmc
+{
+    volatile rt_uint32_t gctl_reg;            /* (0x000) */
+    volatile rt_uint32_t ckcr_reg;            /* (0x004) */
+    volatile rt_uint32_t tmor_reg;            /* (0x008) */
+    volatile rt_uint32_t bwdr_reg;            /* (0x00C) */
+    volatile rt_uint32_t bksr_reg;            /* (0x010) */
+    volatile rt_uint32_t bycr_reg;            /* (0x014) */
+    volatile rt_uint32_t cmdr_reg;            /* (0x018) */
+    volatile rt_uint32_t cagr_reg;            /* (0x01C) */
+    volatile rt_uint32_t resp0_reg;           /* (0x020) */
+    volatile rt_uint32_t resp1_reg;           /* (0x024) */
+    volatile rt_uint32_t resp2_reg;           /* (0x028) */
+    volatile rt_uint32_t resp3_reg;           /* (0x02C) */
+    volatile rt_uint32_t imkr_reg;            /* (0x030) */
+    volatile rt_uint32_t misr_reg;            /* (0x034) */
+    volatile rt_uint32_t risr_reg;            /* (0x038) */
+    volatile rt_uint32_t star_reg;            /* (0x03C) */
+    volatile rt_uint32_t fwlr_reg;            /* (0x040) */
+    volatile rt_uint32_t funs_reg;            /* (0x044) */
+    volatile rt_uint32_t cbcr_reg;            /* (0x048) */
+    volatile rt_uint32_t bbcr_reg;            /* (0x04C) */
+    volatile rt_uint32_t dbgc_reg;            /* (0x050) */
+    volatile rt_uint32_t reserved0;
+    volatile rt_uint32_t a12a_reg;            /* (0x058) */
+    volatile rt_uint32_t reserved1[7];
+    volatile rt_uint32_t hwrst_reg;           /* (0x078) */
+    volatile rt_uint32_t reserved2;
+    volatile rt_uint32_t dmac_reg;            /* (0x080) */
+    volatile rt_uint32_t dlba_reg;            /* (0x084) */
+    volatile rt_uint32_t idst_reg;            /* (0x088) */
+    volatile rt_uint32_t idie_reg;            /* (0x08C) */
+    volatile rt_uint32_t chda_reg;            /* (0x090) */
+    volatile rt_uint32_t cbda_reg;            /* (0x094) */
+    volatile rt_uint32_t reserved3[26];
+    volatile rt_uint32_t card_thldc_reg;      /* (0x100) */
+    volatile rt_uint32_t reserved4[2];
+    volatile rt_uint32_t emmc_dsbd_reg;       /* (0x10c) */
+    volatile rt_uint32_t reserved5[12];
+    volatile rt_uint32_t reserved6[48];
+    volatile rt_uint32_t fifo_reg;            /* (0x200) */
+};
+
+typedef struct tina_mmc *tina_mmc_t;
+
+#define MMC0    ((tina_mmc_t)MMC0_BASE_ADDR)
+#define MMC1    ((tina_mmc_t)MMC1_BASE_ADDR)
+
+
+#define BIT(x)              (1<<(x))
+/* Struct for Intrrrupt Information */
+#define SDXC_RespErr        BIT(1)  //0x2
+#define SDXC_CmdDone        BIT(2)  //0x4
+#define SDXC_DataOver       BIT(3)  //0x8
+#define SDXC_TxDataReq      BIT(4)  //0x10
+#define SDXC_RxDataReq      BIT(5)  //0x20
+#define SDXC_RespCRCErr     BIT(6)  //0x40
+#define SDXC_DataCRCErr     BIT(7)  //0x80
+#define SDXC_RespTimeout    BIT(8)  //0x100
+#define SDXC_ACKRcv         BIT(8)  //0x100
+#define SDXC_DataTimeout    BIT(9)  //0x200
+#define SDXC_BootStart      BIT(9)  //0x200
+#define SDXC_DataStarve     BIT(10) //0x400
+#define SDXC_VolChgDone     BIT(10) //0x400
+#define SDXC_FIFORunErr     BIT(11) //0x800
+#define SDXC_HardWLocked    BIT(12) //0x1000
+#define SDXC_StartBitErr    BIT(13) //0x2000
+#define SDXC_AutoCMDDone    BIT(14) //0x4000
+#define SDXC_EndBitErr      BIT(15) //0x8000
+#define SDXC_SDIOInt        BIT(16) //0x10000
+#define SDXC_CardInsert     BIT(30) //0x40000000
+#define SDXC_CardRemove     BIT(31) //0x80000000
+#define SDXC_IntErrBit      (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr \
+                            | SDXC_RespTimeout | SDXC_DataTimeout | SDXC_FIFORunErr \
+                            | SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr)  //0xbfc2
+
+/*
+    SD CMD reg
+REG[0-5] : Cmd ID
+REG[6]   : Has response
+REG[7]   : Long response
+REG[8]   : Check response CRC
+REG[9]   : Has data
+REG[10]  : Write
+REG[11]  : Steam mode
+REG[12]  : Auto stop
+REG[13]  : Wait previous over
+REG[14]  : About cmd
+REG[15]  : Send initialization
+REG[21]  : Update clock
+REG[31]  : Load cmd
+*/
+#define SDXC_RESPONSE_CMD        BIT(6)
+#define SDXC_LONG_RESPONSE_CMD   BIT(7)
+#define SDXC_CHECK_CRC_CMD       BIT(8)
+#define SDXC_HAS_DATA_CMD        BIT(9)
+#define SDXC_WRITE_CMD           BIT(10)
+#define SDXC_STEAM_CMD           BIT(11)
+#define SDXC_AUTO_STOP_CMD       BIT(12)
+#define SDXC_WAIT_OVER_CMD       BIT(13)
+#define SDXC_ABOUT_CMD           BIT(14)
+#define SDXC_SEND_INIT_CMD       BIT(15)
+#define SDXC_UPDATE_CLOCK_CMD    BIT(21)
+#define SDXC_LOAD_CMD            BIT(31)
+
+/* 
+    SD status reg 
+REG[0]   : FIFO_RX_LEVEL
+REG[1]   : FIFO_TX_LEVEL
+REG[2]   : FIFO_EMPTY
+REG[3]   : FIFO_FULL
+REG[4-7] : FSM_STA
+REG[8]   : CARD_PRESENT
+REG[9]   : CARD_BUSY
+REG[10]  : FSM_BUSY
+REG[11-16]: RESP_IDX 
+REG[17-21]: FIFO_LEVEL
+REG[31]   : DMA_REQ
+*/
+
+#define SDXC_FIFO_RX_LEVEL    BIT(0)
+#define SDXC_FIFO_TX_LEVEL    BIT(1)
+#define SDXC_FIFO_EMPTY       BIT(2)
+#define SDXC_FIFO_FULL        BIT(3)
+#define SDXC_CARD_PRESENT     BIT(8)
+#define SDXC_CARD_BUSY        BIT(9)
+#define SDXC_FSM_BUSY         BIT(10)
+#define SDXC_DMA_REQ          BIT(31)
+
+struct mmc_des_v4p1
+{
+    rt_uint32_t                         : 1,
+                    dic                 : 1, /* disable interrupt on completion                                    */
+                    last_des            : 1, /* 1-this data buffer is the last buffer                              */
+                    first_des           : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer        */
+                    des_chain           : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */
+                    end_of_ring         : 1, /* 1-last descriptor flag when using dual data buffer in descriptor   */
+                                        : 24,
+                    card_err_sum        : 1, /* transfer error flag                                                */
+                    own                 : 1; /* des owner:1-idma owns it, 0-host owns it                           */
+
+#define SDXC_DES_NUM_SHIFT 12  /* smhc2!! */
+#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
+    rt_uint32_t data_buf1_sz  : 16,
+                data_buf2_sz     : 16;
+    rt_uint32_t buf_addr_ptr1;
+    rt_uint32_t buf_addr_ptr2;
+};
+
+#endif
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('spi', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,80 @@
+/*
+ * File      : drv_spi_flash.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[FLASH]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define SPI_FLASH_DEVICE_NAME       "spi00"
+#define SPI_FLASH_CHIP              "gd25qxx"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
+#else
+#define DEBUG_PRINTF(...)
+#endif
+
+#ifdef TINA_USING_SPI_FLASH
+
+#include "spi_flash.h"
+
+#if defined(RT_USING_SFUD)
+#include "spi_flash_sfud.h"
+rt_spi_flash_device_t spi_device;
+int rt_hw_spi_flash_with_sfud_init(void)
+{
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    spi_device = rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME);
+    if (spi_device == NULL)
+    {
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+        return RT_ERROR;
+    };
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    return RT_EOK;
+}
+INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init);
+
+#elif defined(RT_USING_W25QXX)
+#include "spi_flash_w25qxx.h"
+
+int rt_hw_spi_flash_init(void)
+{
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    return w25qxx_init(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME);
+}
+INIT_DEVICE_EXPORT(rt_hw_spi_flash_init);
+
+#endif
+
+#endif
@@ -17,7 +17,7 @@ elif CROSS_TOOL == 'keil':
    EXEC_PATH   = 'C:/Keil_v5'
 elif CROSS_TOOL == 'iar':
    PLATFORM    = 'iar'
-    IAR_PATH    = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
+    EXEC_PATH    = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'

 if os.getenv('RTT_EXEC_PATH'):
    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -113,7 +113,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --endian=little'
    CFLAGS += ' -e'
    CFLAGS += ' --fpu=none'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
    CFLAGS += ' --silent'

    AFLAGS = '--cpu '+ DEVICE
@@ -135,5 +135,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --map ' + MAP_FILE
    LFLAGS += ' --silent'

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = 'ielftool  --silent --bin $TARGET ' + TARGET_NAME
@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil_v5'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -111,7 +111,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --endian=little'
    CFLAGS += ' -e'
    CFLAGS += ' --fpu=none'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
    CFLAGS += ' --silent'

    AFLAGS = '--cpu '+ DEVICE
@@ -133,5 +133,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --map ' + MAP_FILE
    LFLAGS += ' --silent'

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = 'ielftool  --silent --bin $TARGET ' + TARGET_NAME
@@ -8,15 +8,12 @@ CROSS_TOOL='gcc'
 if os.getenv('RTT_CC'):
    CROSS_TOOL = os.getenv('RTT_CC')

-if  CROSS_TOOL == 'gcc':
-    PLATFORM 	= 'gcc'
-    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
-elif CROSS_TOOL == 'keil':
-    PLATFORM 	= 'armcc'
-    EXEC_PATH 	= 'C:/Keil'
+# only support GNU GCC compiler.
+PLATFORM  = 'gcc'
+EXEC_PATH = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'

 if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')

 BUILD = 'debug'

@@ -54,48 +51,3 @@ if PLATFORM == 'gcc':

    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
                  SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    CXX = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMP'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imx6.map --scatter imx6.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
-
-elif PLATFORM == 'iar':
-    # toolchains
-    CC = 'iccarm'
-    AS = 'iasmarm'
-    AR = 'iarchive'
-    LINK = 'ilinkarm'
-    TARGET_EXT = 'out'
-
-    DEVICE = ' --cpu DARMP'
-
-    CFLAGS = ''
-    AFLAGS = ''
-    LFLAGS = ' --config imx6.icf'
-
-    EXEC_PATH += '/arm/bin/'
-    RT_USING_MINILIBC = False
-    POST_ACTION = ''
@@ -76,6 +76,7 @@ CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_CMD_SIZE=80
@@ -134,7 +135,13 @@ CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_W25QXX is not set
+# CONFIG_RT_USING_GD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_WIFI is not set

@@ -297,6 +304,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # tools packages
 #
 # CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_IPERF is not set
@@ -307,12 +315,82 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_SAMPLES is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set

 #
 # example package: hello
 #
 # CONFIG_PKG_USING_HELLO is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
 CONFIG_SOC_IMXRT1052=y
+CONFIG_BOARD_RT1050_EVK=y
+# CONFIG_BOARD_RT1050_FIRE is not set
+
+#
+# RT1050 Bsp Config
+#
+
+#
+# Select uart drivers
+#
 CONFIG_RT_USING_UART1=y
-CONFIG_RT_USING_HP_RTC=y
+# CONFIG_RT_USING_UART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+# CONFIG_RT_USING_UART4 is not set
+# CONFIG_RT_USING_UART5 is not set
+# CONFIG_RT_USING_UART6 is not set
+# CONFIG_RT_USING_UART7 is not set
+# CONFIG_RT_USING_UART8 is not set
+
+#
+# Select spi bus and dev drivers
+#
+CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y
+# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set
+# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set
+# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set
+CONFIG_LPSPI_CLK_SOURCE=0
+CONFIG_LPSPI_CLK_SOURCE_DIVIDER=8
+# CONFIG_RT_USING_SPIBUS1 is not set
+# CONFIG_RT_USING_SPIBUS2 is not set
+# CONFIG_RT_USING_SPIBUS3 is not set
+CONFIG_RT_USING_SPIBUS4=y
+CONFIG_LPSPI4_SCK_GPIO_1=y
+# CONFIG_LPSPI4_SCK_GPIO_2 is not set
+CONFIG_LPSPI4_SDO_GPIO_1=y
+# CONFIG_LPSPI4_SDO_GPIO_2 is not set
+CONFIG_LPSPI4_SDI_GPIO_1=y
+# CONFIG_LPSPI4_SDI_GPIO_2 is not set
+# CONFIG_RT_USING_SPI_FLASH is not set
+
+#
+# Select i2c bus drivers
+#
+CONFIG_LPI2C_CLOCK_SOURCE_DIVIDER=4
+CONFIG_RT_USING_I2C1=y
+# CONFIG_RT_USING_I2C1_BITOPS is not set
+# CONFIG_RT_USING_I2C2 is not set
+# CONFIG_RT_USING_I2C3 is not set
+# CONFIG_RT_USING_I2C4 is not set
+
+#
+# Select lcd driver
+#
+
+#
+# Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45
+#
+CONFIG_RT_USING_LCD=y
+CONFIG_LCD_WIDTH=480
+CONFIG_LCD_HEIGHT=272
+CONFIG_LCD_HFP=4
+CONFIG_LCD_VFP=4
+CONFIG_LCD_HBP=8
+CONFIG_LCD_VBP=2
+CONFIG_LCD_HSW=40
+CONFIG_LCD_VSW=10
+CONFIG_LCD_BL_PIN=106
+CONFIG_LCD_RST_PIN=45
+CONFIG_RT_USING_SDRAM=y
+CONFIG_RT_USING_RTC_HP=y
@@ -5,7 +5,11 @@ Import('RTT_ROOT')
 from building import *

 cwd = GetCurrentDir()
-src  = Glob('drivers/*.c')
+src = Glob('drivers/*.c')
+
+if GetDepend('BOARD_RT1050_FIRE'): 
+    SrcRemove(src, r'drivers\fsl_enet.c')
+
 SrcRemove(src, 'drivers/dataqueue.c')
 src += Glob('common/chip/*.c')
 src += [cwd + '/system_MIMXRT1052.c']
@@ -1345,7 +1345,13 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
 #else
        address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-        memcpy((void *)address, data, length);
+        
+        {
+            // Change SDK to reduce memory copy
+            extern void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len);
+            pbuf2mem(data, (void *)address, length);
+        }
+        //memcpy((void *)address, data, length);
        /* Set data length. */
        curBuffDescrip->length = length;
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -0,0 +1,77 @@
+#  i.MX RT1050
+
+## 1. 简介
+
+i.MX RT 1050系列芯片，是由 NXP 半导体公司推出的跨界处理器芯片。它基于应用处理器的芯片架构，采用了微控制器的内核Cortex-M7，从而具有应用处理器的高性能及丰富的功能，又具备传统微控制器的易用、实时及低功耗的特性。
+
+BSP默认支持的i.MX RT1052处理器具备以下简要的特性：
+
+| 介绍 | 描述 |
+| ---- | ---- |
+| 主CPU平台 | ARM Cortex-M7 |
+| 最高频率 | 600MHz |
+| 内部存储器 | 512KB  SRAM |
+| 外部存储器接口 | NAND、eMMC、QuadSPI NOR Flash 和 Parallel NOR Flash |
+
+## 2. 编译说明
+
+i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本 |
+| ---------- | --------- |
+| MDK5 | MDK525 |
+| IAR | IAR 8.11.3.13984 |
+| GCC | GCC 5.4.1 20160919 (release) |
+
+## 3.BSP使用
+
+### 3.1 配置工程
+
+i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野火的i.MX RT1052开发板。如果不是基于官方开发板，那么重新配置并生成工程：
+
+- 在bsp下打开env工具
+- 输入`menuconfig`命令，`RT1052 Board select (***)-->`选择正确的开发板。
+- 输入`scons --target=mdk5 -s`或`scons --target=iar`来生成需要的工程
+
+### 3.2 下载和仿真
+
+#### 3.2.1 MIMXRT1050-EVK
+
+EVK开发板有板载OpenSDA仿真器，仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28)，就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口就可以看到shell输出
+
+#### 3.2.2 野火开发板
+
+### 3.3 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上（PuTTY）看到RT-Thread的启动logo信息：
+
+TODO
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  | 备注 |
+| ------ | ----  | ------ |
+| UART | 支持 | UART 1~8 |
+| GPIO | 支持 |  |
+| IIC | 支持 | IIC 1~4 |
+| SPI | 支持 | SPI 1~4 |
+| ETH | 支持 | 野火开发板的ETH还没支持 |
+| LCD | 支持 |  |
+| RTC | 支持 |  |
+| SDIO | 支持 | 暂时仅仅支持一个SDIO，还不支持中断方式 |
+| SDRAM | 支持 | 32M SDRAM，后面2M作为Non Cache区域 |
+
+## 5. 联系人信息
+
+维护人：
+
+- [tanek](https://github.com/TanekLiang)
+- [liu2guang](https://github.com/liu2guang)
+
+## 6. 参考
+
+- [MIMXRT1050-EVK: i.MX RT1050评估套件概述](https://www.nxp.com/cn/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK)
+- [MIMXRT1050 EVK Board Hardware User’s Guide ](https://www.nxp.com/docs/en/user-guide/MIMXRT1050EVKHUG.pdf)
+- [i.MX RT Series Crossover Processor Quick Start Guide](https://www.nxp.com/docs/en/user-guide/IMXRT1050EVKQSG.pdf)
+- [i.MX RT Series Crossover Processor Fact Sheet](https://www.nxp.com/docs/en/fact-sheet/IMXRTSERIESFS.pdf)
+- [Evaluation Kit Based on i.MX RT1050 Crossover Processors](https://www.nxp.com/docs/en/fact-sheet/IMXRT1050EVKFS.pdf)
@@ -46,3 +46,26 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)

 # make a building
 DoBuilding(TARGET, objs)
+
+def Update_MDKFlashProgrammingAlgorithm(flash_dict):
+    import xml.etree.ElementTree as etree
+    from utils import xml_indent
+
+    project_tree = etree.parse('project.uvoptx')
+    root = project_tree.getroot()
+    out = file('project.uvoptx', 'wb')
+
+    for elem in project_tree.iterfind('.//Target/TargetOption/TargetDriverDllRegistry/SetRegEntry'):
+        Key = elem.find('Key')
+        if Key.text in flash_dict.keys():
+            elem.find('Name').text = flash_dict[Key.text]
+
+    xml_indent(root)
+    out.write(etree.tostring(root, encoding='utf-8'))
+    out.close()
+
+if GetOption('target') and GetDepend('BOARD_RT1050_FIRE'):
+    Update_MDKFlashProgrammingAlgorithm({
+        "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000',
+        "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000',
+    })
@@ -38,29 +38,29 @@

 void dump_clock(void)
 {
-    rt_kprintf("CPU clock: %d\n",                   CLOCK_GetFreq(kCLOCK_CpuClk));
-	rt_kprintf("AHB clock : %d\n",                  CLOCK_GetFreq(kCLOCK_AhbClk));
-	rt_kprintf("SEMC clock : %d\n",                 CLOCK_GetFreq(kCLOCK_SemcClk));
-	rt_kprintf("IPG clock : %d\n",                  CLOCK_GetFreq(kCLOCK_IpgClk));
-	rt_kprintf("OSC clock selected : %d\n",         CLOCK_GetFreq(kCLOCK_OscClk));
-	rt_kprintf("RTC clock: %d\n",                   CLOCK_GetFreq(kCLOCK_RtcClk));
-	rt_kprintf("ARMPLLCLK : %d\n",                  CLOCK_GetFreq(kCLOCK_ArmPllClk));
-	rt_kprintf("USB1PLLCLK : %d\n",                 CLOCK_GetFreq(kCLOCK_Usb1PllClk));
-	rt_kprintf("USB1PLLPDF0CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
-	rt_kprintf("USB1PLLPFD1CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
-	rt_kprintf("USB1PLLPFD2CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
-	rt_kprintf("USB1PLLPFD3CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
-	rt_kprintf("USB2PLLCLK : %d\n",                 CLOCK_GetFreq(kCLOCK_Usb2PllClk));
-	rt_kprintf("SYSPLLCLK : %d\n",                  CLOCK_GetFreq(kCLOCK_SysPllClk));
-	rt_kprintf("SYSPLLPDF0CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
-	rt_kprintf("SYSPLLPFD1CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
-	rt_kprintf("SYSPLLPFD2CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
-	rt_kprintf("SYSPLLPFD3CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
-	rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
-	rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
-	rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll2Clk));
-	rt_kprintf("Audio PLLCLK : %d\n",               CLOCK_GetFreq(kCLOCK_AudioPllClk));
-	rt_kprintf("Video PLLCLK : %d\n",               CLOCK_GetFreq(kCLOCK_VideoPllClk));
+    rt_kprintf("OSC clock : %d\n",                  CLOCK_GetFreq(kCLOCK_OscClk));
+    rt_kprintf("RTC clock : %d\n",                  CLOCK_GetFreq(kCLOCK_RtcClk));
+    rt_kprintf("CPU clock: %d\n",                   CLOCK_GetFreq(kCLOCK_CpuClk)); 
+    rt_kprintf("AHB clock : %d\n",                  CLOCK_GetFreq(kCLOCK_AhbClk)); 
+    rt_kprintf("SEMC clock : %d\n",                 CLOCK_GetFreq(kCLOCK_SemcClk)); 
+    rt_kprintf("IPG clock : %d\n",                  CLOCK_GetFreq(kCLOCK_IpgClk));
+    rt_kprintf("ARMPLLCLK(PLL1) : %d\n",            CLOCK_GetFreq(kCLOCK_ArmPllClk));
+    rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n",    CLOCK_GetFreq(kCLOCK_SysPllClk));
+    rt_kprintf("SYSPLLPDF0CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
+    rt_kprintf("SYSPLLPFD1CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
+    rt_kprintf("SYSPLLPFD2CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
+    rt_kprintf("SYSPLLPFD3CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
+    rt_kprintf("USB1PLLCLK(PLL3) : %d\n",           CLOCK_GetFreq(kCLOCK_Usb1PllClk));
+    rt_kprintf("USB1PLLPDF0CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
+    rt_kprintf("USB1PLLPFD1CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
+    rt_kprintf("USB1PLLPFD2CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
+    rt_kprintf("USB1PLLPFD3CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
+    rt_kprintf("Audio PLLCLK(PLL4) : %d\n",         CLOCK_GetFreq(kCLOCK_AudioPllClk));
+    rt_kprintf("Video PLLCLK(PLL5) : %d\n",         CLOCK_GetFreq(kCLOCK_VideoPllClk));
+    rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
+    rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
+    rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll2Clk));
+    rt_kprintf("USB2PLLCLK(PLL7) : %d\n",           CLOCK_GetFreq(kCLOCK_Usb2PllClk));
 }

 void dump_cc_info(void)
@@ -2,41 +2,65 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *

-cwd     = os.path.join(str(Dir('#')), 'drivers')
+cwd = os.path.join(str(Dir('#')), 'drivers')

 # add the general drivers.
 src = Split("""
 board.c
 drv_uart.c
-hyper_flash_boot.c
-drv_sdram.c
+drv_cache.c
 """)

 CPPPATH = [cwd]
 CPPDEFINES = []

+# add sdram driver code
+if GetDepend('RT_USING_SDRAM'):
+    src = src + ['drv_sdram.c'] 
+
+# add pin driver code
 if GetDepend('RT_USING_PIN'):
    src += ['drv_pin.c']

-if GetDepend('RT_USING_HP_RTC'):
-    src += ['drv_hp_rtc.c']
+# add rtc driver code
+if GetDepend('RT_USING_RTC_HP'):
+    src = src + ['drv_rtc.c'] 

-if GetDepend('RT_USING_LWIP'):
-    src += ['drv_eth.c', 'fsl_phy.c']
-    CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']
-    
+# add spibus driver code
+if GetDepend('RT_USING_SPI'):
+    src += ['drv_spi_bus.c']
+
+# add spi flash driver code
+if GetDepend('RT_USING_SPI_FLASH'):
+    src += ['drv_spi_flash.c']
+
+# add i2cbus driver code
+if GetDepend('RT_USING_I2C'):
+    src += ['drv_i2c.c']
+
+# add lcd driver code
+if GetDepend('RT_USING_LCD'):
+    src += ['drv_lcd.c']
+
+# add sdio driver code
 if GetDepend('RT_USING_SDIO'):
    src += ['drv_sdio.c']
-if GetDepend('RT_USING_USB_DEVICE'):
-    src += Glob('usb/phy/*.c')
-    CPPDEFINES += ['ENDIANNESS']
-    
+
+# add usb device driver code
 if GetDepend('RT_USING_USB_DEVICE'):
    src += ['drv_usbd.c']
    src += Glob('usb/device/*.c')
-    
-if GetDepend('RT_USING_RTGUI') or GetDepend('PKG_USING_GUIENGINE'):
-    src += ['drv_lcd.c', 'drv_ft5406.c', 'drv_i2c.c']
+# add usb phy driver code
+if GetDepend('RT_USING_USB_DEVICE'):
+    src += Glob('usb/phy/*.c')
+    CPPDEFINES += ['ENDIANNESS']
+
+if GetDepend('BOARD_RT1050_EVK'):
+    src += ['hyper_flash_boot.c']
+
+    if GetDepend('RT_USING_LWIP'):
+        src += ['drv_eth.c', 'fsl_phy.c']
+        CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']

 if GetDepend('RT_USING_AUDIO'):
    src += ['drv_codec.c', 'fsl_wm8960.c']
@@ -18,7 +18,9 @@
 #include "board.h"
 #include "drv_uart.h"

+#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
 static struct rt_memheap system_heap;
+#endif

 /* ARM PLL configuration for RUN mode */
 const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U };
@@ -46,40 +48,39 @@ static void BOARD_BootClockRUN(void)
    /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
    CLOCK_SetXtalFreq(24000000U);
    CLOCK_SetRtcXtalFreq(32768U);
-    
+
    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
-    CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */   
-    
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+
    /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */
    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
-    
+
    CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
 #ifndef SKIP_SYSCLK_INIT
    CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
 #endif
-#ifndef SKIP_USB_PLL_INIT    
+#ifndef SKIP_USB_PLL_INIT
    CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
-#endif    
+#endif
    CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
-    CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ 
-    CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ 
-    
-    CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */    
-    CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */       
-    
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
+
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
+
    /* Disable unused clock */
-    BOARD_BootClockGate();    
-    
-    /* Power down all unused PLL */    
+    BOARD_BootClockGate();
+
+    /* Power down all unused PLL */
    CLOCK_DeinitAudioPll();
    CLOCK_DeinitVideoPll();
    CLOCK_DeinitEnetPll();
    CLOCK_DeinitUsb2Pll();

-    /* Configure UART divider to default */
-    CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
-    CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */    
-    
+    /* iomuxc clock (iomuxc_clk_enable): 0x03u */
+    CLOCK_EnableClock(kCLOCK_Iomuxc);
+
    /* Update core clock */
    SystemCoreClockUpdate();
 }
@@ -162,54 +163,43 @@ void rt_lowlevel_init(void)
 {
    BOARD_ConfigMPU();

+#if defined(RT_USING_SDRAM)
    extern int imxrt_sdram_init(void);
    imxrt_sdram_init();
+#endif
 }

 /**
- * This function will initial LPC8XX board.
+ * This function will initial rt1050 board.
 */
 void rt_hw_board_init()
 {
    BOARD_BootClockRUN();

    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
-    
+
 #ifdef RT_USING_COMPONENTS_INIT
    rt_components_board_init();
 #endif
-    
+
 #ifdef RT_USING_CONSOLE
    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-    
+
 #ifdef RT_USING_HEAP
+
+#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
    rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
-    rt_system_heap_init((void*)SDRAM_BEGIN, (void*)SDRAM_END);
+    rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END);

    rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
    rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
+#else
+    rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
 #endif
 }

-#ifdef PKG_USING_GUIENGINE
-#include <rtgui/driver.h>
-#include "drv_lcd.h"
-
-/* initialize for gui driver */
-int rtgui_lcd_init(void)
-{
-    rt_device_t device;
-
-    imxrt_hw_lcd_init();
-
-    device = rt_device_find("lcd");
-    /* set graphic device */
-    rtgui_graphic_set_device(device);
-
-    return 0;
-}
-INIT_DEVICE_EXPORT(rtgui_lcd_init);
-#endif
-
 /*@}*/
@@ -0,0 +1,75 @@
+/*
+ * File      : drv_cache.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     tanek        first implementation
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <fsl_cache.h>
+
+void rt_hw_cpu_icache_enable(void)
+{
+    SCB_EnableICache();
+}
+
+void rt_hw_cpu_icache_disable(void)
+{
+    SCB_DisableICache();
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
+{
+    if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        ICACHE_InvalidateByRange((uint32_t)addr, size);
+    }
+}
+
+void rt_hw_cpu_dcache_enable(void)
+{
+    SCB_EnableDCache();
+}
+
+void rt_hw_cpu_dcache_disable(void)
+{
+    SCB_DisableDCache();
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
+{
+    if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
+    {
+        DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
+    }
+    else if (ops & RT_HW_CACHE_FLUSH)
+    {
+        DCACHE_CleanByRange((uint32_t)addr, size);
+    }
+    else if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        DCACHE_InvalidateByRange((uint32_t)addr, size);
+    }
+    else
+    {
+        RT_ASSERT(0);
+    }
+}
@@ -40,7 +40,7 @@

 #define BSP_TOUCH_SAMPLE_HZ     30

-#define I2CBUS_NAME  "i2c0"
+#define I2CBUS_NAME  "i2c1"

 #if 0
 #define FTDEBUG      rt_kprintf
@@ -0,0 +1,189 @@
+/*
+* File      : drv_hwtimer.c
+* This file is part of RT-Thread RTOS
+* COPYRIGHT (C) 2017, RT-Thread Development Team
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, write to the Free Software Foundation, Inc.,
+*  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*
+* Change Logs:
+* Date           Author       Notes
+* 2018-04-17     WangBing     the first version.
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "drv_hwtimer.h"
+
+#include "fsl_common.h"
+#include "fsl_gpt.h"
+
+#ifdef RT_USING_HWTIMER
+
+#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#endif
+
+/* Select IPG Clock as PERCLK_CLK clock source */
+#define EXAMPLE_GPT_CLOCK_SOURCE_SELECT (0U)
+/* Clock divider for PERCLK_CLK clock source */
+#define EXAMPLE_GPT_CLOCK_DIVIDER_SELECT (5U)
+/* Get source clock for GPT driver (GPT prescaler = 6) */
+#define EXAMPLE_GPT_CLK_FREQ (CLOCK_GetFreq(kCLOCK_IpgClk) / (EXAMPLE_GPT_CLOCK_DIVIDER_SELECT + 1U))
+
+static void NVIC_Configuration(void)
+{
+    EnableIRQ(GPT1_IRQn);
+}
+
+static rt_err_t rt1052_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
+{
+    rt_err_t err = RT_EOK;
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        uint32_t clk;
+        uint32_t pre;
+        clk = EXAMPLE_GPT_CLK_FREQ;
+        pre = clk / *((uint32_t *)args) - 1;
+        GPT_SetClockDivider(hwtimer_dev, pre);
+    }
+    break;
+    default:
+        err = -RT_ENOSYS;
+        break;
+    }
+    return err;
+}
+
+static rt_uint32_t rt1052_hwtimer_count_get(rt_hwtimer_t *timer)
+{
+    rt_uint32_t CurrentTimer_Count;
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    CurrentTimer_Count = GPT_GetCurrentTimerCount(hwtimer_dev);
+
+    return CurrentTimer_Count;
+}
+
+static void rt1052_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    GPT_Type *hwtimer_dev;
+    gpt_config_t gptConfig;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    GPT_Deinit(hwtimer_dev);
+
+    if (state == 1)
+    {
+        /*Clock setting for GPT*/
+        CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
+        CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
+
+        /* Initialize GPT module by default config */
+        GPT_GetDefaultConfig(&gptConfig);
+        GPT_Init(hwtimer_dev, &gptConfig);
+    }
+}
+
+static rt_err_t rt1052_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
+{
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    hwtimer_dev->CR |= (mode == HWTIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U;
+
+    GPT_SetOutputCompareValue(hwtimer_dev, kGPT_OutputCompare_Channel1, cnt);
+
+    GPT_EnableInterrupts(hwtimer_dev, kGPT_OutputCompare1InterruptEnable);
+
+    NVIC_Configuration();
+
+    GPT_StartTimer(hwtimer_dev);
+
+    return RT_EOK;
+}
+
+static void rt1052_hwtimer_stop(rt_hwtimer_t *timer)
+{
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    GPT_StopTimer(hwtimer_dev);
+}
+
+static const struct rt_hwtimer_ops rt1052_hwtimer_ops =
+{
+    rt1052_hwtimer_init,
+    rt1052_hwtimer_start,
+    rt1052_hwtimer_stop,
+    rt1052_hwtimer_count_get,
+    rt1052_hwtimer_control,
+};
+
+static const struct rt_hwtimer_info rt1052_hwtimer_info =
+{
+    25000000,           /* the maximum count frequency can be set */
+    6103,               /* the minimum count frequency can be set */
+    0xFFFFFFFF,
+    HWTIMER_CNTMODE_UP,
+};
+
+static rt_hwtimer_t GPT_timer1;
+
+int rt1052_hw_hwtimer_init(void)
+{
+    int ret = RT_EOK;
+
+    GPT_timer1.info = &rt1052_hwtimer_info;
+    GPT_timer1.ops  = &rt1052_hwtimer_ops;
+
+    rt_device_hwtimer_register(&GPT_timer1, "_timer", GPT1);
+
+    return ret;
+}
+
+void GPT1_IRQHandler(void)
+{
+    if (GPT_GetStatusFlags(GPT1, kGPT_OutputCompare1Flag) != 0)
+    {
+        GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag);
+        rt_device_hwtimer_isr(&GPT_timer1);
+    }
+
+    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
+      exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U)
+    __DSB();
+#endif
+}
+
+INIT_DEVICE_EXPORT(rt1052_hw_hwtimer_init);
+
+#endif /*RT_USING_HWTIMER*/
@@ -0,0 +1,34 @@
+/*
+* File      : drv_hwtimer.h
+* This file is part of RT-Thread RTOS
+* COPYRIGHT (C) 2017, RT-Thread Development Team
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, write to the Free Software Foundation, Inc.,
+*  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*
+* Change Logs:
+* Date           Author       Notes
+* 2018-04-17     WangBing     the first version.
+*/
+ 
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt1052_hw_hwtimer_init(void);
+
+#endif
+
@@ -0,0 +1,34 @@
+/*
+ * File      : drv_i2c.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-24     LaiYiKeTang  the first version
+ */
+
+#ifndef __DRVI2C_H__
+#define __DRVI2C_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+struct rt1052_i2c_bus
+{
+    struct rt_i2c_bus_device parent;
+    LPI2C_Type *I2C;
+    struct rt_i2c_msg *msg;
+    rt_uint32_t msg_cnt;
+    volatile rt_uint32_t msg_ptr;
+    volatile rt_uint32_t dptr;
+    char *device_name;
+};
+
+#endif
+
@@ -1,29 +1,23 @@
 /*
- * File      : drv_i2c.c
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * File      : drv_lcd2.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
 *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
 *
 * Change Logs:
 * Date           Author       Notes
- * 2017-12-15     Tanek        the first version
+ * 2018-04-05     Liuguang     the first version.
 */
 
 #ifndef __DRV_LCD_H__
 #define __DRV_LCD_H__

-extern int imxrt_hw_lcd_init(void);
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_lcd_init(void);

 #endif
@@ -392,7 +392,6 @@ void GPIO5_Combined_0_15_IRQHandler(void)
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
    __DSB();
 #endif
-    
    rt_interrupt_leave();
 }

@@ -473,13 +472,13 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
    {
        CLOCK_EnableClock(kCLOCK_Iomuxc); 
        
-        IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); 
+        IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1); 
    }
    else
    {
        CLOCK_EnableClock(kCLOCK_IomuxcSnvs); 
        
-        IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); 
+        IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1); 
    }
    
    gpio.outputLogic = 0; 
@@ -530,7 +529,7 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)

 static int rt1052_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    return GPIO_PinRead(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
+    return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
 }

 static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
@@ -1,5 +1,5 @@
 /*
- * File      : drv_hp_rtc.c
+ * File      : drv_rtc.c
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
 *
@@ -11,11 +11,12 @@
 * Date           Author       Notes
 * 2018-03-15     Liuguang     the first version.
 */
-#include "drv_hp_rtc.h" 
-#include <time.h>
+#include "drv_rtc.h" 
+
 #include "fsl_common.h" 
 #include "fsl_snvs_hp.h"
 #include "fsl_snvs_lp.h"
+#include <time.h>

 #ifdef RT_USING_RTC

@@ -35,7 +36,7 @@ static time_t get_timestamp(void)
    tm_new.tm_hour = rtcDate.hour;
    
    tm_new.tm_mday = rtcDate.day; 
-    tm_new.tm_mon  = rtcDate.month - 1;  
+    tm_new.tm_mon  = rtcDate.month - 1; 
    tm_new.tm_year = rtcDate.year - 1900; 

    return mktime(&tm_new);
@@ -1,5 +1,5 @@
 /*
- * File      : drv_hp_rtc.h
+ * File      : drv_rtc.h
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
 *
@@ -56,7 +56,7 @@ static int enable_log = 1;

 #define USDHC_ADMA_TABLE_WORDS      (8U)        /* define the ADMA descriptor table length */
 #define USDHC_ADMA2_ADDR_ALIGN      (4U)        /* define the ADMA2 descriptor table addr align size */
-#define IMXRT_MAX_FREQ              (400 * 1000u)
+#define IMXRT_MAX_FREQ              (50UL * 1000UL * 1000UL)
    
 #define USDHC_ADMA_TABLE_WORDS      (8U)        /* define the ADMA descriptor table length */
 #define USDHC_ADMA2_ADDR_ALIGN      (4U)        /* define the ADMA2 descriptor table addr align size */
@@ -357,7 +357,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
            if (buf)
            {
                MMCSD_DGB(" write(data->buf to buf) ");
-                memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
+                rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
                fsl_data.txData = (uint32_t const *)buf;
            }
            else
@@ -401,7 +401,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
        if (fsl_data.rxData)
        {
            MMCSD_DGB("read copy buf to data->buf ");
-            memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
+            rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
        }
    
        rt_free_align(buf);
@@ -0,0 +1,24 @@
+/*
+ * File      : drv_spi_bus.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-27     Liuguang     the first version.
+ */
+ 
+#ifndef __DRV_SPI_BUS_H__ 
+#define __DRV_SPI_BUS_H__ 
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_spi_bus_init(void);
+rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); 
+
+#endif
@@ -0,0 +1,51 @@
+/*
+ * File      : drv_spi_flash.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     Liuguang     the first version.
+ */
+ 
+#include "drv_spi_flash.h" 
+
+#include "spi_flash.h" 
+#include "spi_flash_sfud.h" 
+
+#ifndef SPI_FLASH_USING_SPIBUS_NAME 
+#define SPI_FLASH_USING_SPIBUS_NAME "spi4" 
+#endif
+#ifndef SPI_FLASH_NAME 
+#define SPI_FLASH_NAME "flash0" 
+#endif
+#ifndef SPI_FLASH_USING_CS_PIN 
+#define SPI_FLASH_USING_CS_PIN (79) 
+#endif
+
+int rt_hw_spi_flash_init(void)
+{
+    rt_err_t ret; 
+    
+    extern rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, 
+        const char *device_name, rt_uint32_t pin); 
+    
+    ret = rt1050_spi_bus_attach_device(SPI_FLASH_USING_SPIBUS_NAME, 
+        SPI_FLASH_USING_SPIBUS_NAME "0", SPI_FLASH_USING_CS_PIN); 
+    if(ret != RT_EOK) 
+    {
+        return ret; 
+    }
+    
+    if(rt_sfud_flash_probe(SPI_FLASH_NAME, SPI_FLASH_USING_SPIBUS_NAME "0") == RT_NULL) 
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK; 
+}
+INIT_DEVICE_EXPORT(rt_hw_spi_flash_init); 
@@ -0,0 +1,23 @@
+/*
+ * File      : drv_spi_flash.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     Liuguang     the first version.
+ */
+ 
+#ifndef __DRV_SPI_FLASH_H_ 
+#define __DRV_SPI_FLASH_H_ 
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_spi_flash_init(void); 
+
+#endif /* __DRV_SPI_FLASH_H_ */ 
@@ -21,7 +21,6 @@

 #ifdef RT_USING_SERIAL

-/* GPIO外设时钟会在LPUART_Init中自动配置, 如果定义了以下宏则不会自动配置 */
 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
 #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
@@ -41,10 +40,10 @@
 /* imxrt uart driver */
 struct imxrt_uart
 {
-    LPUART_Type * uart_base;
+    LPUART_Type *uart_base;
    IRQn_Type irqn;

-    struct rt_serial_device * serial;
+    struct rt_serial_device *serial;
    char *device_name;
 };

@@ -129,7 +128,8 @@ void LPUART8_IRQHandler(void)

 #endif /* RT_USING_UART8 */

-static const struct imxrt_uart uarts[] = {
+static const struct imxrt_uart uarts[] =
+{
 #ifdef RT_USING_UART1
    {
        LPUART1,
@@ -198,7 +198,7 @@ static const struct imxrt_uart uarts[] = {
 };

 /* Get debug console frequency. */
-uint32_t BOARD_DebugConsoleSrcFreq(void)
+uint32_t GetUartSrcFreq(void)
 {
    uint32_t freq;

@@ -231,7 +231,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
    if (uart->uart_base != RT_NULL)
    {
 #ifdef RT_USING_UART1
-        CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03u */

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
@@ -261,7 +260,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
                                                     Hyst. Enable Field: Hysteresis Disabled */
 #endif
 #ifdef RT_USING_UART2
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
@@ -272,15 +270,12 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
            0x10B0u);
-
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
            0x10B0u);

 #endif
 #ifdef RT_USING_UART3
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
@@ -291,13 +286,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
            0x10B0u);
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
            0x10B0u);
 #endif
 #ifdef RT_USING_UART4
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_B1_00_LPUART4_TX,
@@ -308,13 +301,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_B1_00_LPUART4_TX,
            0x10B0u);
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_B1_01_LPUART4_RX,
            0x10B0u);
 #endif
 #ifdef RT_USING_UART5
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_B1_12_LPUART5_TX,
@@ -325,13 +316,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_B1_12_LPUART5_TX,
            0x10B0u);
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_B1_13_LPUART5_RX,
            0x10B0u);
 #endif
 #ifdef RT_USING_UART6
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
@@ -342,13 +331,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
            0x10B0u);
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
            0x10B0u);
 #endif
 #ifdef RT_USING_UART7
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_EMC_31_LPUART7_TX,
@@ -359,13 +346,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_EMC_31_LPUART7_TX,
            0x10B0u);
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_EMC_32_LPUART7_RX,
            0x10B0u);
 #endif
 #ifdef RT_USING_UART8
-        CLOCK_EnableClock(kCLOCK_Iomuxc);

        IOMUXC_SetPinMux(
            IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
@@ -376,7 +361,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
            0x10B0u);
-
        IOMUXC_SetPinConfig(
            IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
            0x10B0u);
@@ -440,8 +424,7 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c
    config.enableTx = true;
    config.enableRx = true;

-    LPUART_Init(uart->uart_base, &config, BOARD_DebugConsoleSrcFreq());
-
+    LPUART_Init(uart->uart_base, &config, GetUartSrcFreq());

    return RT_EOK;
 }
@@ -481,7 +464,7 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch)
    uart = (struct imxrt_uart *)serial->parent.user_data;

    LPUART_WriteByte(uart->uart_base, ch);
-    while(!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
+    while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));

    return 1;
 }
@@ -546,16 +529,21 @@ static const struct rt_uart_ops imxrt_uart_ops =
    imxrt_getc,
 };

-int imxrt_hw_usart_init(void)
+int imxrt_hw_uart_init(void)
 {
    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
    int i;
+
+    /* Configure UART divider to default */
+    CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
+
    for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
    {
        uarts[i].serial->ops    = &imxrt_uart_ops;
        uarts[i].serial->config = config;

-        /* register UART1 device */
+        /* register UART device */
        rt_hw_serial_register(uarts[i].serial,
                              uarts[i].device_name,
                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
@@ -564,6 +552,6 @@ int imxrt_hw_usart_init(void)

    return 0;
 }
-INIT_BOARD_EXPORT(imxrt_hw_usart_init);
+INIT_BOARD_EXPORT(imxrt_hw_uart_init);

 #endif /*RT_USING_SERIAL */
@@ -12,12 +12,11 @@
 * 2017-10-10     Tanek        the first version
 */

-#ifndef __DRV_USART_H__
-#define __DRV_USART_H__
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__

 #include <rthw.h>
 #include <rtthread.h>

-int rt_hw_usart_init(void);

 #endif
@@ -23,7 +23,7 @@
 #error Can not using 2 controller as usb device
 #endif
 #endif
-
+#define FSL_USB_HS

 /* USB PHY condfiguration */
 #define BOARD_USB_PHY_D_CAL (0x0CU)
@@ -81,6 +81,27 @@ void USB_DeviceClockInit(uint8_t controllerId)
 #endif
 }
 #ifdef RT_USING_EHCI0_AS_DEVICE
+#ifdef FSL_USB_HS
+static struct ep_id _ehci0_ep_pool[] =
+{
+    {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
+};
+#else
 static struct ep_id _ehci0_ep_pool[] =
 {
    {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
@@ -100,6 +121,7 @@ static struct ep_id _ehci0_ep_pool[] =
    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    64, ID_UNASSIGNED},
    {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
 };
+#endif
 void USB_OTG1_IRQHandler(void)
 {
    /* enter interrupt */
@@ -133,6 +155,7 @@ static rt_err_t _ehci0_ep_enable(uep_t ep)
 {
    usb_device_endpoint_init_struct_t ep_init;
    usb_device_endpoint_callback_struct_t ep_callback;
+    rt_uint32_t param = ep->ep_desc->bEndpointAddress;
    RT_ASSERT(ep != RT_NULL);
    RT_ASSERT(ep->ep_desc != RT_NULL);
    ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize;
@@ -140,7 +163,7 @@ static rt_err_t _ehci0_ep_enable(uep_t ep)
    ep_init.transferType = ep->ep_desc->bmAttributes;
    ep_init.zlt = 0;
    ep_callback.callbackFn = usb_device_endpoint_callback;
-    ep_callback.callbackParam = (void *)ep_init.endpointAddress;
+    ep_callback.callbackParam = (void *)param;
    ep_callback.isBusy = 0;
    USB_DeviceInitEndpoint(ehci0_handle,&ep_init,&ep_callback);
    return RT_EOK;
@@ -220,6 +243,27 @@ static rt_err_t drv_ehci0_usbd_init(rt_device_t device)
 }
 #endif
 #ifdef RT_USING_EHCI1_AS_DEVICE
+#ifdef FSL_USB_HS
+static struct ep_id _ehci1_ep_pool[] =
+{
+    {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
+};
+#else
 static struct ep_id _ehci1_ep_pool[] =
 {
    {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
@@ -239,6 +283,7 @@ static struct ep_id _ehci1_ep_pool[] =
    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    64, ID_UNASSIGNED},
    {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
 };
+#endif
 void USB_OTG2_IRQHandler(void)
 {
    /* enter interrupt */
@@ -373,6 +418,11 @@ static int rt_usbd_init(void)
    /* Register endpoint infomation */
    _fsl_udc_0.ep_pool = _ehci0_ep_pool;
    _fsl_udc_0.ep0.id = &_ehci0_ep_pool[0];
+    #ifdef FSL_USB_HS
+    _fsl_udc_0.device_is_hs = RT_TRUE;
+    #else
+    _fsl_udc_0.device_is_hs = RT_FALSE;
+    #endif
    rt_device_register((rt_device_t)&_fsl_udc_0, "usbd", 0);
    rt_usb_device_init();
    #endif
@@ -384,6 +434,11 @@ static int rt_usbd_init(void)
    /* Register endpoint infomation */
    _fsl_udc_1.ep_pool = _ehci1_ep_pool;
    _fsl_udc_1.ep0.id = &_ehci1_ep_pool[0];
+    #ifdef FSL_USB_HS
+    _fsl_udc_1.device_is_hs = RT_TRUE;
+    #else
+    _fsl_udc_1.device_is_hs = RT_FALSE;
+    #endif
    rt_device_register((rt_device_t)&_fsl_udc_1, "usbd", 0);
    rt_usb_device_init();
    #endif
@@ -410,6 +465,7 @@ static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_d
    }
    if(message->isSetup)
    {
+        //rt_kprintf("1udcd:%#08X\n",udcd);
        rt_usbd_ep0_setup_handler(udcd, (struct urequest*)message->buffer);
    }
    else if(ep_addr == 0x00)
@@ -423,6 +479,7 @@ static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_d
                USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
            }
        }
+        //rt_kprintf("2udcd:%#08X\n",udcd);
        rt_usbd_ep0_out_handler(udcd,message->length);
    }
    else if(ep_addr == 0x80)
@@ -436,6 +493,7 @@ static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_d
                USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
            }
        }
+        //rt_kprintf("3udcd:%#08X\n",udcd);
        rt_usbd_ep0_in_handler(udcd);
    }
    else if(ep_addr&0x80)
@@ -308,7 +308,7 @@
          <state>$PROJ_DIR$\Libraries\drivers</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
+          <state>$PROJ_DIR$\drivers</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
          <state>$PROJ_DIR$\.</state>
          <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
@@ -316,10 +316,11 @@
          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
          <state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
          <state>$PROJ_DIR$\Libraries\utilities</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi</state>
          <state>$PROJ_DIR$\applications</state>
          <state>$PROJ_DIR$\..\..\components\finsh</state>
          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
-          <state>$PROJ_DIR$\drivers</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
        </option>
        <option>
@@ -1247,7 +1248,7 @@
          <state>$PROJ_DIR$\Libraries\drivers</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
+          <state>$PROJ_DIR$\drivers</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
          <state>$PROJ_DIR$\.</state>
          <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
@@ -1255,10 +1256,11 @@
          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
          <state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
          <state>$PROJ_DIR$\Libraries\utilities</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi</state>
          <state>$PROJ_DIR$\applications</state>
          <state>$PROJ_DIR$\..\..\components\finsh</state>
          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
-          <state>$PROJ_DIR$\drivers</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
        </option>
        <option>
@@ -1898,7 +1900,7 @@
      <name>$PROJ_DIR$\drivers\drv_uart.c</name>
    </file>
    <file>
-      <name>$PROJ_DIR$\drivers\hyper_flash_boot.c</name>
+      <name>$PROJ_DIR$\drivers\drv_cache.c</name>
    </file>
    <file>
      <name>$PROJ_DIR$\drivers\drv_sdram.c</name>
@@ -1907,7 +1909,13 @@
      <name>$PROJ_DIR$\drivers\drv_pin.c</name>
    </file>
    <file>
-      <name>$PROJ_DIR$\drivers\drv_hp_rtc.c</name>
+      <name>$PROJ_DIR$\drivers\drv_rtc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_spi_bus.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\hyper_flash_boot.c</name>
    </file>
    <file>
      <name>$PROJ_DIR$\drivers\drv_eth.c</name>
@@ -2227,6 +2235,12 @@
    <file>
      <name>$PROJ_DIR$\..\..\components\drivers\serial\serial.c</name>
    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_dev.c</name>
+    </file>
    <file>
      <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
    </file>
@@ -18,7 +18,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil_v5'
 elif CROSS_TOOL == 'iar':
    PLATFORM 	= 'iar'
-    IAR_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+    EXEC_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -43,7 +43,7 @@ if PLATFORM == 'gcc':
    DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
    CFLAGS = DEVICE + ' -std=c99 -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_PRESENT -eentry'
    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld'
+    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld'

    CPATH = ''
    LPATH = ''
@@ -55,7 +55,7 @@ if PLATFORM == 'gcc':
    else:
        CFLAGS += ' -O2 -Os'

-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+    POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

    # module setting 
    CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
@@ -77,7 +77,7 @@ elif PLATFORM == 'armcc':
    DEVICE = ' --cpu Cortex-M7.fp.sp'
    CFLAGS = DEVICE + ' --apcs=interwork'
    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf'
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf'

    CFLAGS += ' --diag_suppress=66,1296,186'
    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
@@ -121,7 +121,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M7'
    CFLAGS += ' -e'
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
    CFLAGS += ' -Ol'
    CFLAGS += ' --use_c++_inline'

@@ -137,5 +137,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
    LFLAGS += ' --entry __iar_program_start'

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -120,6 +120,6 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --semihosting' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    RT_USING_MINILIBC = False
    POST_ACTION = ''
@@ -25,7 +25,7 @@ elif CROSS_TOOL == 'keil':
    EXEC_PATH = r'D:/Keil'
 elif CROSS_TOOL == 'iar':
    PLATFORM = 'iar'
-    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+    EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'

 if os.getenv('RTT_EXEC_PATH'):
        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -113,7 +113,7 @@ elif PLATFORM == 'iar':
    else:
        CFLAGS += ' --cpu=Cortex-M0'
    CFLAGS += ' -e' 
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -132,5 +132,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -29,7 +29,7 @@ elif CROSS_TOOL == 'keil':
    EXEC_PATH = r'D:/Keil'
 elif CROSS_TOOL == 'iar':
    PLATFORM = 'iar'
-    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+    EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'

 if os.getenv('RTT_EXEC_PATH'):
        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -117,7 +117,7 @@ elif PLATFORM == 'iar':
    else:
        CFLAGS += ' --cpu=Cortex-M0'
    CFLAGS += ' -e' 
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -136,5 +136,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
    EXEC_PATH 	= 'C:/keil_v5'
 elif CROSS_TOOL == 'iar':
    PLATFORM 	= 'iar'
-    IAR_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+    EXEC_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M0'
    CFLAGS += ' -e'
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
    CFLAGS += ' -Ol'
    CFLAGS += ' --use_c++_inline'

@@ -121,5 +121,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
    LFLAGS += ' --entry __iar_program_start'

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -14,7 +14,7 @@ if  CROSS_TOOL == 'gcc':
 	EXEC_PATH 	= 'C:/Program Files/Renesas/Hew/Tools/KPIT Cummins/GNUM16CM32C-ELF/v11.01/m32c-elf/bin'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0'
+	EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0'
 #	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0'
 elif CROSS_TOOL == 'keil':
    print('================ERROR============================')
@@ -65,16 +65,14 @@ elif PLATFORM == 'iar':
    
    DEVICE = '--cpu M16C'
    
-    EXEC_PATH = IAR_PATH + '/m16c/bin'
-    
    AFLAGS = '-s+'
 #    AFLAGS += ' -M<>' 
    AFLAGS += ' -w+' 
    AFLAGS += ' -r' 
-    AFLAGS += ' -I"' + IAR_PATH + '/m16c/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC"'
        
    LFLAGS = '-xms'
-    LFLAGS += ' -I"' + IAR_PATH + '/m16c/LIB"' 
+    LFLAGS += ' -I"' + EXEC_PATH + '/m16c/LIB"' 
    LFLAGS += ' -rt' 
    LFLAGS += ' -s __program_start' 
    LFLAGS += ' -D_CSTACK_SIZE=80' 
@@ -82,7 +80,7 @@ elif PLATFORM == 'iar':
    LFLAGS += ' -D_DATA16_HEAP_SIZE=1000' 
    LFLAGS += ' -D_FAR_HEAP_SIZE=400'
    LFLAGS += ' -D_DATA20_HEAP_SIZE=400'
-    LFLAGS += ' "' + IAR_PATH + '/m16c/LIB/CLIB/clm16cfnffwc.r34"' 
+    LFLAGS += ' "' + EXEC_PATH + '/m16c/LIB/CLIB/clm16cfnffwc.r34"' 
    LFLAGS += ' -e_small_write=_formatted_write' 
    LFLAGS += ' -e_medium_read=_formatted_read'
    
@@ -95,13 +93,15 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --debug' 
    CFLAGS += ' -e' 
    CFLAGS += ' --align_func 1' 
-    CFLAGS += ' -I"' + IAR_PATH + '/m16c/INC"'
-    CFLAGS += ' -I"' + IAR_PATH + '/m16c/INC/CLIB"' 
+    CFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC"'
+    CFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC/CLIB"' 
    CFLAGS += ' -Ol' 
    CFLAGS += ' --no_cse' 
    CFLAGS += ' --no_unroll' 
    CFLAGS += ' --no_inline' 
    CFLAGS += ' --no_code_motion' 
    CFLAGS += ' --no_tbaa'    
+	
+	EXEC_PATH = EXEC_PATH + '/m16c/bin'
   
    POST_ACTION = ''
@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -102,7 +102,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'    
        
@@ -112,11 +112,11 @@ elif PLATFORM == 'iar':
    AFLAGS += ' -r' 
    AFLAGS += ' --cpu Cortex-M3' 
    AFLAGS += ' --fpu None' 
-    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"'

    LFLAGS = ' --config mb9bf500r.icf'
    LFLAGS += ' --semihosting' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec'
@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -101,7 +101,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'    
        
@@ -111,11 +111,11 @@ elif PLATFORM == 'iar':
    AFLAGS += ' -r' 
    AFLAGS += ' --cpu Cortex-M3' 
    AFLAGS += ' --fpu None' 
-    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"'

    LFLAGS = ' --config rtthread-mb9bf506.icf'
    LFLAGS += ' --semihosting' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' 
@@ -24,7 +24,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= r'E:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'    
        
@@ -116,11 +116,11 @@ elif PLATFORM == 'iar':
    AFLAGS += ' -r' 
    AFLAGS += ' --cpu Cortex-M3' 
    AFLAGS += ' --fpu None' 
-    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"'

    LFLAGS = ' --config rtthread-fm3.icf'
    LFLAGS += ' --semihosting' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' 
@@ -103,7 +103,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M0' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -119,5 +119,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M4' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -121,5 +121,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -150,9 +150,9 @@ extern unsigned char  _sdata;
 // End address for the .data section// defined in linker script
 extern unsigned char  _edata;
 // Begin address for the .bss section// defined in linker script
-extern unsigned char  __bss_start__;
+extern unsigned char  __bss_start;
 // End address for the .bss section// defined in linker script
-extern unsigned char  __bss_end__;
+extern unsigned char  __bss_end;

 extern int entry(void);

@@ -333,7 +333,7 @@ pHandler g_pfnVectors[] =
 void _start()
 {
    memcpy(&_sdata, &_sidata, &_edata - &_sdata);
-    memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
+    memset(&__bss_start, 0, &__bss_end - &__bss_start);
 }

 static void Reset_Handler(void)
@@ -3,7 +3,7 @@
    NuTiny-EVB-NUC472

 ## note:
-    support the GCC MDK5 IAR
+    support the GCC MDK4 MDK5 IAR

 **TODO**

@@ -22,7 +22,7 @@ extern int Image$$RW_IRAM1$$ZI$$Limit;
 #elif __ICCARM__
 #pragma section="HEAP"
 #else
-extern int __bss_end__;
+extern int __bss_end;
 #endif

 /**
@@ -80,7 +80,7 @@ void rt_hw_board_init(void)
    rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
 #else
    /* init memory system */
-    rt_system_heap_init((void*)&__bss_end__, (void*)SRAM_END);
+    rt_system_heap_init((void*)&__bss_end, (void*)SRAM_END);
 #endif
 #endif /* RT_USING_HEAP */

@@ -181,7 +181,7 @@ static void init_rx_desc(rt_nuc472_emac_t emac)
        emac->rx_desc[i].status1 = OWNERSHIP_EMAC;
        emac->rx_desc[i].buf = &emac->rx_buf[i][0];
        emac->rx_desc[i].status2 = 0;
-        emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
+        emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % RX_DESCRIPTOR_NUM];
    }
    emac_base->RXDSA = (unsigned int)&emac->rx_desc[0];
    return;
@@ -205,8 +205,8 @@ static void set_mac_addr(rt_nuc472_emac_t emac, rt_uint8_t *addr)

 void EMAC_init(rt_nuc472_emac_t emac, rt_uint8_t *mac_addr)
 {
+    EMAC_T *emac_base = emac->emac_base;  
    RT_ASSERT(emac->dev_addr != RT_NULL);
-    EMAC_T *emac_base = emac->emac_base;

    CLK_EnableModuleClock(EMAC_MODULE);

@@ -445,12 +445,12 @@ rt_err_t rt_nuc472_emac_tx(rt_device_t dev, struct pbuf* p)
 struct pbuf *rt_nuc472_emac_rx(rt_device_t dev)
 {
    rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev;
+    unsigned int status;
    struct pbuf* p;

    /* init p pointer */
    p = RT_NULL;

-    unsigned int status;
    status = emac->cur_rx_desc_ptr->status1;

    if(status & OWNERSHIP_EMAC)
@@ -1,8 +0,0 @@
-
-/*
- * Placeholder to list other libraries required by the application.
- 
-GROUP(
-)
-
- */
@@ -1,25 +0,0 @@
-/*
- * Memory Spaces Definitions.
- *
- * Need modifying for a specific board. 
- *   FLASH.ORIGIN: starting address of flash
- *   FLASH.LENGTH: length of flash
- *   RAM.ORIGIN: starting address of RAM bank 0
- *   RAM.LENGTH: length of RAM bank 0
- *
- * The values below can be addressed in further linker scripts
- * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.
- */
-
-MEMORY
-{
-  RAM (xrw)  : ORIGIN = 0x20000000, LENGTH =  64K
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH =  512K /*4K*/
-}
-
-/*
- * For external ram use something like:
-
-  RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 8K
-
- */
@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:\Keil_v5'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M4' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -121,5 +121,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M0'
    CFLAGS += ' -e'
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
    CFLAGS += ' -Ol'
    CFLAGS += ' --use_c++_inline'

@@ -122,5 +122,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
    LFLAGS += ' --entry __iar_program_start'

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -8,12 +8,8 @@ CROSS_TOOL='gcc'
 if os.getenv('RTT_CC'):
    CROSS_TOOL = os.getenv('RTT_CC')

-if  CROSS_TOOL == 'gcc':
-    PLATFORM    = 'gcc'
-    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
-elif CROSS_TOOL == 'keil':
-    PLATFORM    = 'armcc'
-    EXEC_PATH   = 'C:/Keil'
+PLATFORM    = 'gcc'
+EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'

 if os.getenv('RTT_EXEC_PATH'):
    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -32,6 +28,7 @@ if PLATFORM == 'gcc':
    SIZE = PREFIX + 'size'
    OBJDUMP = PREFIX + 'objdump'
    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'

    DEVICE = ' -march=armv7-a -marm -msoft-float'
    CFLAGS = DEVICE + ' -Wall'
@@ -52,52 +49,13 @@ if PLATFORM == 'gcc':
    else:
        CFLAGS += ' -O2'

-    CXXFLAGS = CFLAGS
+    CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
+
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc'
+    M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'

    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
                  SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    CXX = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMP'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
-
-elif PLATFORM == 'iar':
-    # toolchains
-    CC = 'iccarm'
-    AS = 'iasmarm'
-    AR = 'iarchive'
-    LINK = 'ilinkarm'
-    TARGET_EXT = 'out'
-
-    DEVICE = ' --cpu DARMP'
-
-    CFLAGS = ''
-    AFLAGS = ''
-    LFLAGS = ' --config rtthread.icf'
-
-    EXEC_PATH += '/arm/bin/'
-    RT_USING_MINILIBC = False
-    POST_ACTION = ''
@@ -7,7 +7,7 @@ src = Glob('*.c')
 if GetDepend('RT_USING_LWIP') == False:
    SrcRemove(src, 'sam7x_emac.c')
 if GetDepend('RT_USING_DFS') == False:
-    SrcRemove(src, 'ssd.c')
+    SrcRemove(src, 'sd.c')

 CPPPATH = [cwd]

@@ -107,7 +107,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M0' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -123,5 +123,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
        
    AFLAGS = ''
@@ -118,5 +118,5 @@ elif PLATFORM == 'iar':
    LFLAGS = ' --config stm32_rom.icf'
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -15,6 +15,6 @@

 int main(void)
 {
-  /* user app entry */
-  return 0;
+    /* user app entry */
+    return 0;
 }
@@ -24,12 +24,9 @@

 /*@{*/

-
 void HAL_MspInit(void)
 {
-
    HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
    /* System interrupt init*/
    __HAL_RCC_AFIO_CLK_ENABLE();
    /* MemoryManagement_IRQn interrupt configuration */
@@ -46,16 +43,14 @@ void HAL_MspInit(void)
    HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
    /* SysTick_IRQn interrupt configuration */
    HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
-
    /**DISABLE: JTAG-DP Disabled and SW-DP Disabled**/
    __HAL_AFIO_REMAP_SWJ_NOJTAG();
 }
+
 void SystemClock_Config(void)
 {
-
    RCC_OscInitTypeDef RCC_OscInitStruct;
    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-
    /**Initializes the CPU, AHB and APB busses clocks
      */
    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
@@ -73,22 +68,17 @@ void SystemClock_Config(void)
    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
    RT_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
-
    /**Configure the Systick interrupt time
      */
    HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
-
    /**Configure the Systick
      */
    HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-
    /* SysTick_IRQn interrupt configuration */
    HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
 }

-
 /**
 * This is the timer interrupt service routine.
 *
@@ -97,10 +87,8 @@ void SysTick_Handler(void)
 {
    /* enter interrupt */
    rt_interrupt_enter();
-
    HAL_IncTick();
    rt_tick_increase();
-
    /* leave interrupt */
    rt_interrupt_leave();
 }
@@ -115,15 +103,10 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_HEAP
    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-
 #ifdef RT_USING_COMPONENTS_INIT
    rt_components_board_init();
 #endif
-
 #ifdef RT_USING_CONSOLE
    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-
 }
-
-/*@}*/
@@ -197,7 +197,6 @@
 #define STM32_SRAM_SIZE 64
 //#define STM32F107xC
 #endif
-
 /* whether use board external SRAM memory */
 // <e>Use external SRAM memory on the board
 // 	<i>Enable External SRAM memory
@@ -209,10 +208,8 @@
 //		<i>Default: 0x68080000
 #define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */
 // </e>
-
 // <o> Internal SRAM memory size[Kbytes] <8-64>
 //	<i>Default: 64
-
 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
 #ifdef __CC_ARM
 extern int Image$$RW_IRAM1$$ZI$$Limit;
@@ -14,18 +14,12 @@
 */
 #ifndef GPIO_H__
 #define GPIO_H__
-
-
 struct stm32_hw_pin_userdata
 {
    int pin;
    uint32_t mode;
 };
-
 #define PIN_USERDATA_END {-1,0}
-
 extern struct stm32_hw_pin_userdata stm32_pins[];
-
 int rt_hw_pin_init(void);
-
 #endif
@@ -22,9 +22,9 @@
 * 2018-01-13     Liu2guang      the first version.
 */

-#ifndef __DRV_SDCARD_H_ 
-#define __DRV_SDCARD_H_ 
+#ifndef __DRV_SDCARD_H_
+#define __DRV_SDCARD_H_

-int rt_hw_sdcard_init(void); 
+int rt_hw_sdcard_init(void);

 #endif
@@ -16,30 +16,25 @@
 #include <board.h>
 #include <drv_spi.h>
 #ifdef RT_USING_SPI
-
 #define SPIRXEVENT 0x01
 #define SPITXEVENT 0x02
 #define SPITIMEOUT 2
 #define SPICRCEN 0
-
 struct stm32_hw_spi_cs
 {
    rt_uint32_t pin;
 };

-
 struct stm32_spi
 {
    SPI_TypeDef *Instance;
    struct rt_spi_configuration *cfg;
 };

-
 static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *cfg)
 {
    SPI_HandleTypeDef hspi;
    hspi.Instance = spix;
-
    if (cfg->mode & RT_SPI_SLAVE)
    {
        hspi.Init.Mode = SPI_MODE_SLAVE;
@@ -145,6 +140,7 @@ static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *c
    __HAL_SPI_ENABLE(&hspi);
    return RT_EOK;
 }
+
 #define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
 #define SPISEND_1(reg, ptr, datalen)       \
    do                                     \
@@ -195,6 +191,7 @@ static rt_err_t spitxrx1b(struct stm32_spi *hspi, void *rcvb, const void *sndb)
    SPIRECV_1(hspi->Instance->DR, rcvb, hspi->cfg->data_width);
    return RT_EOK;
 }
+
 static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
    rt_err_t res;
@@ -203,7 +200,6 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
    struct stm32_spi *hspi = (struct stm32_spi *)device->bus->parent.user_data;
    struct stm32_hw_spi_cs *cs = device->parent.user_data;
-
    if (message->cs_take)
    {
        rt_pin_write(cs->pin, 0);
@@ -238,7 +234,6 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
    return message->length - length;
 }

-
 rt_err_t spi_configure(struct rt_spi_device *device,
                       struct rt_spi_configuration *configuration)
 {
@@ -378,34 +373,3 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *spiHandle)
    }
 }
 #endif /*RT_USING_SPI*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -18,21 +18,7 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include <rtdevice.h>
-
-
-
-extern int stm32_spi_register_bus(SPI_TypeDef * SPIx,const char * name);
-extern rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin,const char * bus_name,const char * device_name);
+extern int stm32_spi_register_bus(SPI_TypeDef *SPIx, const char *name);
+extern rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin, const char *bus_name, const char *device_name);
 extern int stm32_hw_spi_init(void);
-
-
-
 #endif
-
-
-
-
-
-
-
-
@@ -11,12 +11,9 @@
 * Date           Author       Notes
 * 2009-01-05     Bernard      the first version
 */
-
 #ifndef __USART_H__
 #define __USART_H__
-
 #include <rthw.h>
 #include <rtthread.h>
 int rt_hw_usart_init(void);
-
 #endif
@@ -16,9 +16,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "board.h"
-
-#define USB_DISCONNECT_PIN                  30		//PA9
-
+#define USB_DISCONNECT_PIN                  30      //PA9
 static PCD_HandleTypeDef _stm_pcd;
 static struct udcd _stm_udc;
 static struct ep_id _ep_pool[] =
@@ -35,9 +33,7 @@ static struct ep_id _ep_pool[] =
 void USB_LP_CAN1_RX0_IRQHandler(void)
 {
    rt_interrupt_enter();
-
    HAL_PCD_IRQHandler(&_stm_pcd);
-
    rt_interrupt_leave();
 }

@@ -51,10 +47,9 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *pcd)

 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
 {
-    rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest*)hpcd->Setup);
+    rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest *)hpcd->Setup);
 }

-
 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
    if (epnum == 0)
@@ -63,7 +58,7 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
    }
    else
    {
-        rt_usbd_ep_in_handler(&_stm_udc, 0x80|epnum,hpcd->IN_ep[epnum].xfer_count);
+        rt_usbd_ep_in_handler(&_stm_udc, 0x80 | epnum, hpcd->IN_ep[epnum].xfer_count);
    }
 }

@@ -90,46 +85,43 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
    }
    else
    {
-        rt_usbd_ep0_out_handler(&_stm_udc,hpcd->OUT_ep[0].xfer_count);
+        rt_usbd_ep0_out_handler(&_stm_udc, hpcd->OUT_ep[0].xfer_count);
    }
 }

-
 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
 {
-    if(state == 1)
+    if (state == 1)
    {
-        rt_pin_write(USB_DISCONNECT_PIN,PIN_HIGH);
+        rt_pin_write(USB_DISCONNECT_PIN, PIN_HIGH);
    }
    else
    {
-        rt_pin_write(USB_DISCONNECT_PIN,PIN_LOW);
-    }  
+        rt_pin_write(USB_DISCONNECT_PIN, PIN_LOW);
+    }
 }

-void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+void HAL_PCD_MspInit(PCD_HandleTypeDef *pcdHandle)
 {
-    if(pcdHandle->Instance==USB)
+    if (pcdHandle->Instance == USB)
    {
        __HAL_RCC_GPIOA_CLK_ENABLE();
-        rt_pin_mode(USB_DISCONNECT_PIN,PIN_MODE_OUTPUT);
-        rt_pin_write(USB_DISCONNECT_PIN,PIN_LOW);
+        rt_pin_mode(USB_DISCONNECT_PIN, PIN_MODE_OUTPUT);
+        rt_pin_write(USB_DISCONNECT_PIN, PIN_LOW);
        /* Peripheral clock enable */
        __HAL_RCC_USB_CLK_ENABLE();
-
        /* Peripheral interrupt init */
        HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 5, 0);
        HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
    }
 }

-void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *pcdHandle)
 {
-    if(pcdHandle->Instance==USB)
+    if (pcdHandle->Instance == USB)
    {
        /* Peripheral clock disable */
        __HAL_RCC_USB_CLK_DISABLE();
-
        /* Peripheral interrupt Deinit*/
        HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
    }
@@ -143,7 +135,7 @@ static rt_err_t _ep_set_stall(rt_uint8_t address)

 static rt_err_t _ep_clear_stall(rt_uint8_t address)
 {
-    HAL_PCD_EP_ClrStall(&_stm_pcd, address);  
+    HAL_PCD_EP_ClrStall(&_stm_pcd, address);
    return RT_EOK;
 }

@@ -164,7 +156,6 @@ static rt_err_t _ep_enable(uep_t ep)
    RT_ASSERT(ep->ep_desc != RT_NULL);
    HAL_PCD_EP_Open(&_stm_pcd, ep->ep_desc->bEndpointAddress,
                    ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes);
-
    return RT_EOK;
 }

@@ -196,7 +187,7 @@ static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
 }

 static rt_err_t _ep0_send_status(void)
-{	
+{
    HAL_PCD_EP_Transmit(&_stm_pcd, 0x00, NULL, 0);
    return RT_EOK;
 }
@@ -214,10 +205,8 @@ static rt_err_t _wakeup(void)
 static rt_err_t _init(rt_device_t device)
 {
    PCD_HandleTypeDef *pcd;
-
    /* Set LL Driver parameters */
-    pcd = (PCD_HandleTypeDef*)device->user_data;
-
+    pcd = (PCD_HandleTypeDef *)device->user_data;
    pcd->Instance = USB;
    pcd->Init.dev_endpoints = 8;
    pcd->Init.speed = PCD_SPEED_FULL;
@@ -225,19 +214,16 @@ static rt_err_t _init(rt_device_t device)
    pcd->Init.low_power_enable = DISABLE;
    pcd->Init.lpm_enable = DISABLE;
    pcd->Init.battery_charging_enable = DISABLE;
-
    /* Initialize LL Driver */
    HAL_PCD_Init(pcd);
-  
-    HAL_PCDEx_PMAConfig(pcd , 0x00 , PCD_SNG_BUF, 0x18);
-    HAL_PCDEx_PMAConfig(pcd , 0x80 , PCD_SNG_BUF, 0x58);
-    HAL_PCDEx_PMAConfig(pcd , 0x81 , PCD_SNG_BUF, 0x98);    
-    HAL_PCDEx_PMAConfig(pcd , 0x01 , PCD_SNG_BUF, 0x118);
-    HAL_PCDEx_PMAConfig(pcd , 0x82 , PCD_SNG_BUF, 0xD8);   
-    HAL_PCDEx_PMAConfig(pcd , 0x02 , PCD_SNG_BUF, 0x158);
-    HAL_PCDEx_PMAConfig(pcd , 0x83 , PCD_SNG_BUF, 0x198);
+    HAL_PCDEx_PMAConfig(pcd, 0x00, PCD_SNG_BUF, 0x18);
+    HAL_PCDEx_PMAConfig(pcd, 0x80, PCD_SNG_BUF, 0x58);
+    HAL_PCDEx_PMAConfig(pcd, 0x81, PCD_SNG_BUF, 0x98);
+    HAL_PCDEx_PMAConfig(pcd, 0x01, PCD_SNG_BUF, 0x118);
+    HAL_PCDEx_PMAConfig(pcd, 0x82, PCD_SNG_BUF, 0xD8);
+    HAL_PCDEx_PMAConfig(pcd, 0x02, PCD_SNG_BUF, 0x158);
+    HAL_PCDEx_PMAConfig(pcd, 0x83, PCD_SNG_BUF, 0x198);
    HAL_PCD_Start(pcd);
-
    return RT_EOK;
 }

@@ -257,11 +243,9 @@ const static struct udcd_ops _udc_ops =
    _wakeup,
 };

-
 int stm_usbd_register(void)
 {
    rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd));
-
    _stm_udc.parent.type = RT_Device_Class_USBDevice;
    _stm_udc.parent.init = _init;
    _stm_udc.parent.user_data = &_stm_pcd;
@@ -269,10 +253,9 @@ int stm_usbd_register(void)
    /* Register endpoint infomation */
    _stm_udc.ep_pool = _ep_pool;
    _stm_udc.ep0.id = &_ep_pool[0];
-
    rt_device_register((rt_device_t)&_stm_udc, "usbd", 0);
    rt_usb_device_init();
    return 0;
 }
+
 INIT_DEVICE_EXPORT(stm_usbd_register);
- 
@@ -14,7 +14,5 @@
 #ifndef __STM32_USB_H__
 #define __STM32_USB_H__
 #include <rtthread.h>
-
 int stm_usbd_register(void);
-
 #endif
@@ -36,8 +36,8 @@
 #define __STM32F1xx_IT_H

 #ifdef __cplusplus
- extern "C" {
-#endif 
+extern "C" {
+#endif

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f1xx_hal.h"
@@ -20,7 +20,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keilv5'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -122,5 +122,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -212,7 +212,7 @@
            <hadIRAM2>0</hadIRAM2>
            <hadIROM2>0</hadIROM2>
            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
+            <useUlib>0</useUlib>
            <EndSel>0</EndSel>
            <uLtcg>0</uLtcg>
            <RoSelD>3</RoSelD>
@@ -31,7 +31,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -117,7 +117,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
    CFLAGS += ' --use_c++_inline'
        
@@ -133,5 +133,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -215,7 +215,7 @@
            <hadIRAM2>0</hadIRAM2>
            <hadIROM2>0</hadIROM2>
            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
+            <useUlib>0</useUlib>
            <EndSel>0</EndSel>
            <uLtcg>0</uLtcg>
            <RoSelD>3</RoSelD>
@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -101,7 +101,7 @@ elif PLATFORM == 'iar':
    CFLAGS += ' --cpu=Cortex-M3' 
    CFLAGS += ' -e' 
    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
    CFLAGS += ' -Ol'    
        
    AFLAGS = ''
@@ -115,5 +115,5 @@ elif PLATFORM == 'iar':
    LFLAGS += ' --semihosting' 
    LFLAGS += ' --entry __iar_program_start'    

-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
    POST_ACTION = ''
@@ -58,7 +58,8 @@ CONFIG_ARCH_ARM_CORTEX_M4=y
 #
 # RT-Thread Components
 #
-# CONFIG_RT_USING_COMPONENTS_INIT is not set
+CONFIG_RT_USING_COMPONENTS_INIT=y
+# CONFIG_RT_USING_USER_MAIN is not set

 #
 # C++ features
@@ -74,6 +75,7 @@ CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_CMD_SIZE=80
@@ -302,12 +304,12 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set

 #
 # example package: hello
 #
 # CONFIG_PKG_USING_HELLO is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
 CONFIG_SOC_STM32F4=y
 CONFIG_RT_USING_UART1=y
 CONFIG_RT_USING_UART2=y
@@ -34,32 +34,14 @@

 void rt_init_thread_entry(void* parameter)
 {
+    /* initialization RT-Thread Components */
+    rt_components_init();
+	
    /* GDB STUB */
 #ifdef RT_USING_GDB
    gdb_set_device("uart6");
    gdb_start();
 #endif
-
-    /* LwIP Initialization */
-#ifdef RT_USING_LWIP
-    {
-        extern void lwip_sys_init(void);
-
-        /* register ethernetif device */
-        eth_system_device_init();
-
-        rt_hw_stm32_eth_init();
-
-        /* init lwip system */
-        lwip_sys_init();
-        rt_kprintf("TCP/IP initialized!\n");
-    }
-#endif
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-#endif
 }

 int rt_application_init()
@@ -93,12 +93,11 @@ void rt_hw_board_init()
    /* Configure the SysTick */
    SysTick_Configuration();

-    stm32_hw_usart_init();
-    stm32_hw_pin_init();
-    
+    rt_components_board_init();
+ 
 #ifdef RT_USING_CONSOLE
    rt_console_set_device(CONSOLE_DEVICE);
-#endif
+#endif	
 }

 /*@}*/
@@ -4156,3 +4156,4 @@ void rt_hw_stm32_eth_init(void)
            rt_thread_startup(tid);
    }
 }
+INIT_PREV_EXPORT(rt_hw_stm32_eth_init);
--- a/Show More
+++ b/Show More