From 5b31545970ab395fcada828a71f7b67e5c39e9a3 Mon Sep 17 00:00:00 2001 From: tangyuxin <462747508@qq.com> Date: Sun, 25 Mar 2018 07:54:25 +0800 Subject: [PATCH 01/67] [drivers]Fix put_force bug --- components/drivers/src/ringbuffer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/components/drivers/src/ringbuffer.c b/components/drivers/src/ringbuffer.c index baeeea0e50..48bf590f8c 100644 --- a/components/drivers/src/ringbuffer.c +++ b/components/drivers/src/ringbuffer.c @@ -119,8 +119,11 @@ rt_size_t rt_ringbuffer_put_force(struct rt_ringbuffer *rb, space_length = rt_ringbuffer_space_len(rb); - if (length > space_length) + if (length > rb->buffer_size) + { + ptr = &ptr[length - rb->buffer_size]; length = rb->buffer_size; + } if (rb->buffer_size - rb->write_index > length) { From 045500ce2c1d159ca7433392eae94ae81984fed0 Mon Sep 17 00:00:00 2001 From: liuguang <1004383796@qq.com> Date: Mon, 26 Mar 2018 11:38:20 +0800 Subject: [PATCH 02/67] =?UTF-8?q?[BSP]=20add=20fire=20board=20support=20an?= =?UTF-8?q?d=20optimize=20bsp.|=E6=B7=BB=E5=8A=A0=E9=87=8E=E7=81=AB?= =?UTF-8?q?=E5=BC=80=E5=8F=91=E6=9D=BF=E6=94=AF=E6=8C=81=E5=B9=B6=E4=BC=98?= =?UTF-8?q?=E5=8C=96bsp.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. 添加env menuconfig可以选择nxp官方或者野火开发板. 2. 修改drv_hp_rtc名称为drv_rtc. --- bsp/imxrt1052-evk/.config | 24 +- bsp/imxrt1052-evk/Kconfig | 124 +- bsp/imxrt1052-evk/applications/main.c | 46 +- bsp/imxrt1052-evk/drivers/SConscript | 47 +- bsp/imxrt1052-evk/drivers/board.c | 21 +- .../drivers/{drv_hp_rtc.c => drv_rtc.c} | 9 +- .../drivers/{drv_hp_rtc.h => drv_rtc.h} | 2 +- bsp/imxrt1052-evk/project.uvoptx | 2199 ++++++++++++++++- bsp/imxrt1052-evk/project.uvprojx | 448 +--- bsp/imxrt1052-evk/rtconfig.h | 97 +- 10 files changed, 2464 insertions(+), 553 deletions(-) rename bsp/imxrt1052-evk/drivers/{drv_hp_rtc.c => drv_rtc.c} (97%) rename bsp/imxrt1052-evk/drivers/{drv_hp_rtc.h => drv_rtc.h} (94%) diff --git a/bsp/imxrt1052-evk/.config b/bsp/imxrt1052-evk/.config index badc996951..74720d8a9a 100644 --- a/bsp/imxrt1052-evk/.config +++ b/bsp/imxrt1052-evk/.config @@ -76,6 +76,7 @@ CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 @@ -297,6 +298,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set # CONFIG_PKG_USING_IPERF is not set @@ -307,12 +309,30 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set # # example package: hello # # CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set CONFIG_SOC_IMXRT1052=y +CONFIG_BOARD_RT1050_EVK=y +# CONFIG_BOARD_RT1050_FIRE is not set + +# +# RT1050_EVK Bsp Config +# + +# +# Select uart device +# CONFIG_RT_USING_UART1=y -CONFIG_RT_USING_HP_RTC=y +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART4 is not set +# CONFIG_RT_USING_UART5 is not set +# CONFIG_RT_USING_UART6 is not set +# CONFIG_RT_USING_UART7 is not set +# CONFIG_RT_USING_UART8 is not set +CONFIG_RT_USING_SDRAM=y +CONFIG_RT_USING_RTC_HP=y diff --git a/bsp/imxrt1052-evk/Kconfig b/bsp/imxrt1052-evk/Kconfig index a5c48884a7..372696b8f4 100644 --- a/bsp/imxrt1052-evk/Kconfig +++ b/bsp/imxrt1052-evk/Kconfig @@ -23,17 +23,66 @@ config SOC_IMXRT1052 select ARCH_ARM_CORTEX_M7 default y -if RT_USING_SERIAL -config RT_USING_UART1 - bool "Using RT_USING_UART1" - default y -endif +# RT1050 board select! +choice + prompt "RT1050 Board select" + default BOARD_RT1050_EVK + config BOARD_RT1050_EVK + bool "RT1050_EVK" + config BOARD_RT1050_FIRE + bool "RT1050_FIRE" +endchoice -if RT_USING_RTC -config RT_USING_HP_RTC - bool "Using RT_USING_HP_RTC" - default n -endif +if BOARD_RT1050_EVK +menu "RT1050_EVK Bsp Config" + +menu "Select uart device" + config RT_USING_UART1 + bool "Using uart1" + select RT_USING_SERIAL + default y + config RT_USING_UART2 + bool "Using uart2" + select RT_USING_SERIAL + default n + config RT_USING_UART3 + bool "Using uart3" + select RT_USING_SERIAL + default n + config RT_USING_UART4 + bool "Using uart4" + select RT_USING_SERIAL + default n + config RT_USING_UART5 + bool "Using uart5" + select RT_USING_SERIAL + default n + config RT_USING_UART6 + bool "Using uart6" + select RT_USING_SERIAL + default n + config RT_USING_UART7 + bool "Using uart7" + select RT_USING_SERIAL + default n + config RT_USING_UART8 + bool "Using uart8" + select RT_USING_SERIAL + default n +endmenu + +#menu "SDRAM drive support" + config RT_USING_SDRAM + bool "Using sdram" + default y +#endmenu + +#menu "RTC drive support" + config RT_USING_RTC_HP + bool "Using hp rtc" + select RT_USING_RTC + default n +#endmenu if RT_USING_USB_DEVICE choice @@ -47,4 +96,59 @@ if RT_USING_USB_DEVICE endchoice endif +endmenu +endif +if BOARD_RT1050_FIRE +menu "RT1050_FIRE Bsp Config" + +menu "Select uart device" + config RT_USING_UART1 + bool "Using uart1" + select RT_USING_SERIAL + default y + config RT_USING_UART2 + bool "Using uart2" + select RT_USING_SERIAL + default n + config RT_USING_UART3 + bool "Using uart3" + select RT_USING_SERIAL + default n + config RT_USING_UART4 + bool "Using uart4" + select RT_USING_SERIAL + default n + config RT_USING_UART5 + bool "Using uart5" + select RT_USING_SERIAL + default n + config RT_USING_UART6 + bool "Using uart6" + select RT_USING_SERIAL + default n + config RT_USING_UART7 + bool "Using uart7" + select RT_USING_SERIAL + default n + config RT_USING_UART8 + bool "Using uart8" + select RT_USING_SERIAL + default n +endmenu + +#menu "SDRAM drive support" + config RT_USING_SDRAM + bool "Using sdram" + default y +#endmenu + +#menu "RTC drive support" + config RT_USING_RTC_HP + bool "Using hp rtc" + select RT_USING_RTC + default n +#endmenu + +endmenu +endif diff --git a/bsp/imxrt1052-evk/applications/main.c b/bsp/imxrt1052-evk/applications/main.c index e6082cf4d9..b820aad5fe 100644 --- a/bsp/imxrt1052-evk/applications/main.c +++ b/bsp/imxrt1052-evk/applications/main.c @@ -38,29 +38,29 @@ void dump_clock(void) { - rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk)); - rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk)); - rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk)); - rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk)); - rt_kprintf("OSC clock selected : %d\n", CLOCK_GetFreq(kCLOCK_OscClk)); - rt_kprintf("RTC clock: %d\n", CLOCK_GetFreq(kCLOCK_RtcClk)); - rt_kprintf("ARMPLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); - rt_kprintf("USB1PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); - rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); - rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); - rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); - rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); - rt_kprintf("USB2PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); - rt_kprintf("SYSPLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); - rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); - rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); - rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); - rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); - rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); - rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); - rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll2Clk)); - rt_kprintf("Audio PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); - rt_kprintf("Video PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); + rt_kprintf("OSC clock : %d\n", CLOCK_GetFreq(kCLOCK_OscClk)); + rt_kprintf("RTC clock : %d\n", CLOCK_GetFreq(kCLOCK_RtcClk)); + rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk)); + rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk)); + rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk)); + rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk)); + rt_kprintf("ARMPLLCLK(PLL1) : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); + rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); + rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); + rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); + rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); + rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); + rt_kprintf("USB1PLLCLK(PLL3) : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); + rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); + rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); + rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); + rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); + rt_kprintf("Audio PLLCLK(PLL4) : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); + rt_kprintf("Video PLLCLK(PLL5) : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); + rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); + rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); + rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll2Clk)); + rt_kprintf("USB2PLLCLK(PLL7) : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); } void dump_cc_info(void) diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript index 6ca466f3c8..4c5a6e8ef3 100644 --- a/bsp/imxrt1052-evk/drivers/SConscript +++ b/bsp/imxrt1052-evk/drivers/SConscript @@ -8,35 +8,42 @@ cwd = os.path.join(str(Dir('#')), 'drivers') src = Split(""" board.c drv_uart.c -hyper_flash_boot.c -drv_sdram.c """) CPPPATH = [cwd] CPPDEFINES = [] +# add sdram driver code +if GetDepend('RT_USING_SDRAM'): + src = src + ['./drv_sdram.c'] + if GetDepend('RT_USING_PIN'): src += ['drv_pin.c'] -if GetDepend('RT_USING_HP_RTC'): - src += ['drv_hp_rtc.c'] +# add rtc driver code +if GetDepend('RT_USING_RTC_HP'): + src = src + ['./drv_rtc.c'] -if GetDepend('RT_USING_LWIP'): - src += ['drv_eth.c', 'fsl_phy.c'] - CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE'] - -if GetDepend('RT_USING_SDIO'): - src += ['drv_sdio.c'] -if GetDepend('RT_USING_USB_DEVICE'): - src += Glob('usb/phy/*.c') - CPPDEFINES += ['ENDIANNESS'] - -if GetDepend('RT_USING_USB_DEVICE'): - src += ['drv_usbd.c'] - src += Glob('usb/device/*.c') - -if GetDepend('RT_USING_RTGUI') or GetDepend('PKG_USING_GUIENGINE'): - src += ['drv_lcd.c', 'drv_ft5406.c', 'drv_i2c.c'] +if GetDepend('BOARD_RT1050_EVK'): + src += ['hyper_flash_boot.c'] + + if GetDepend('RT_USING_LWIP'): + src += ['drv_eth.c', 'fsl_phy.c'] + CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE'] + + if GetDepend('RT_USING_SDIO'): + src += ['drv_sdio.c'] + + if GetDepend('RT_USING_USB_DEVICE'): + src += Glob('usb/phy/*.c') + CPPDEFINES += ['ENDIANNESS'] + + if GetDepend('RT_USING_USB_DEVICE'): + src += ['drv_usbd.c'] + src += Glob('usb/device/*.c') + + if GetDepend('RT_USING_RTGUI') or GetDepend('PKG_USING_GUIENGINE'): + src += ['drv_lcd.c', 'drv_ft5406.c', 'drv_i2c.c'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) diff --git a/bsp/imxrt1052-evk/drivers/board.c b/bsp/imxrt1052-evk/drivers/board.c index b182ed58e0..df518fbf0f 100644 --- a/bsp/imxrt1052-evk/drivers/board.c +++ b/bsp/imxrt1052-evk/drivers/board.c @@ -18,7 +18,9 @@ #include "board.h" #include "drv_uart.h" +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) static struct rt_memheap system_heap; +#endif /* ARM PLL configuration for RUN mode */ const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U }; @@ -162,12 +164,14 @@ void rt_lowlevel_init(void) { BOARD_ConfigMPU(); +#if defined(RT_USING_SDRAM) extern int imxrt_sdram_init(void); imxrt_sdram_init(); +#endif } /** - * This function will initial LPC8XX board. + * This function will initial rt1050 board. */ void rt_hw_board_init() { @@ -184,11 +188,18 @@ void rt_hw_board_init() #endif #ifdef RT_USING_HEAP - rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); - rt_system_heap_init((void*)SDRAM_BEGIN, (void*)SDRAM_END); - rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); - rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); + rt_system_heap_init((void *)SDRAM_BEGIN, (void*)SDRAM_END); + + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#else + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void*)HEAP_END); +#endif + #endif } diff --git a/bsp/imxrt1052-evk/drivers/drv_hp_rtc.c b/bsp/imxrt1052-evk/drivers/drv_rtc.c similarity index 97% rename from bsp/imxrt1052-evk/drivers/drv_hp_rtc.c rename to bsp/imxrt1052-evk/drivers/drv_rtc.c index 42448ae737..0c1dea21eb 100644 --- a/bsp/imxrt1052-evk/drivers/drv_hp_rtc.c +++ b/bsp/imxrt1052-evk/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * File : drv_hp_rtc.c + * File : drv_rtc.c * This file is part of RT-Thread RTOS * COPYRIGHT (C) 2006-2013, RT-Thread Development Team * @@ -11,11 +11,12 @@ * Date Author Notes * 2018-03-15 Liuguang the first version. */ -#include "drv_hp_rtc.h" -#include +#include "drv_rtc.h" + #include "fsl_common.h" #include "fsl_snvs_hp.h" #include "fsl_snvs_lp.h" +#include #ifdef RT_USING_RTC @@ -35,7 +36,7 @@ static time_t get_timestamp(void) tm_new.tm_hour = rtcDate.hour; tm_new.tm_mday = rtcDate.day; - tm_new.tm_mon = rtcDate.month - 1; + tm_new.tm_mon = rtcDate.month - 1; tm_new.tm_year = rtcDate.year - 1900; return mktime(&tm_new); diff --git a/bsp/imxrt1052-evk/drivers/drv_hp_rtc.h b/bsp/imxrt1052-evk/drivers/drv_rtc.h similarity index 94% rename from bsp/imxrt1052-evk/drivers/drv_hp_rtc.h rename to bsp/imxrt1052-evk/drivers/drv_rtc.h index e191e4714c..e7cf53902c 100644 --- a/bsp/imxrt1052-evk/drivers/drv_hp_rtc.h +++ b/bsp/imxrt1052-evk/drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * File : drv_hp_rtc.h + * File : drv_rtc.h * This file is part of RT-Thread RTOS * COPYRIGHT (C) 2006-2013, RT-Thread Development Team * diff --git a/bsp/imxrt1052-evk/project.uvoptx b/bsp/imxrt1052-evk/project.uvoptx index deca1cf444..a97f733fce 100644 --- a/bsp/imxrt1052-evk/project.uvoptx +++ b/bsp/imxrt1052-evk/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -101,9 +101,7 @@ 0 0 1 - 0 - 0 - 3 + 2 @@ -166,19 +164,2194 @@ 0 + + + 0 0 - 0 - - - - - - - - + 0 + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\device_test.c + device_test.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + applications\mem_dump.c + mem_dump.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + applications\mem_test.c + mem_test.c + 0 + 0 + + + + + Drivers + 1 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + drivers\drv_sdram.c + drv_sdram.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + drivers\drv_pin.c + drv_pin.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + drivers\drv_rtc.c + drv_rtc.c + 0 + 0 + + + 2 + 10 + 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Libraries\drivers\fsl_common.c + fsl_common.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_csi.c + fsl_csi.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_dcdc.c + fsl_dcdc.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_dcp.c + fsl_dcp.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_dmamux.c + fsl_dmamux.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_edma.c + fsl_edma.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_elcdif.c + fsl_elcdif.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_enc.c + fsl_enc.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_enet.c + fsl_enet.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_ewm.c + fsl_ewm.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_flexcan.c + fsl_flexcan.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + Libraries\drivers\fsl_flexio.c + fsl_flexio.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + 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..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + ip4_addr.c + 0 + 0 + + + 10 + 175 + 1 + 0 + 0 + 0 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + ip4_frag.c + 0 + 0 + + + ::CMSIS 0 diff --git a/bsp/imxrt1052-evk/project.uvprojx b/bsp/imxrt1052-evk/project.uvprojx index 2c067820c8..9efc66c679 100644 --- a/bsp/imxrt1052-evk/project.uvprojx +++ b/bsp/imxrt1052-evk/project.uvprojx @@ -1,43 +1,44 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ RT-Thread IMXRT1052 0x4 ARM-ADS - 5060528::V5.06 update 5 (build 528)::ARMCC - 0 + 5060422::V5.06 update 4 (build 422)::ARMCC MIMXRT1052:M7 NXP - NXP.iMXRT_DFP.1.0.2 - http://mcuxpresso.nxp.com/cmsis_pack/repo/ + NXP.iMXRT_DFP.1.0.1 IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) 0 $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h - - - - - - - - - + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +60,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +70,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +81,14 @@ 1 0 fromelf --bin !L --output rtthread-mdk.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +102,8 @@ 0 0 3 - - + + 1 @@ -135,11 +136,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -172,7 +173,7 @@ 0 0 "Cortex-M7" - + 0 0 0 @@ -304,7 +305,7 @@ 0x20000 - + 1 @@ -332,7 +333,7 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 SKIP_SYSCLK_INIT, CPU_MIMXRT1052DVL6A, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, RT_USING_ARM_LIBC - + applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix @@ -348,10 +349,10 @@ 0 0 - - - - + + + + @@ -363,13 +364,13 @@ 0 0x00000000 0x10000000 - + .\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + @@ -382,22 +383,16 @@ 1 applications\device_test.c - - main.c 1 applications\main.c - - mem_dump.c 1 applications\mem_dump.c - - mem_test.c 1 @@ -413,57 +408,41 @@ 1 drivers\board.c - - drv_uart.c 1 drivers\drv_uart.c - - - - hyper_flash_boot.c - 1 - drivers\hyper_flash_boot.c - - - drv_sdram.c 1 drivers\drv_sdram.c - - drv_pin.c 1 drivers\drv_pin.c - - - drv_hp_rtc.c + drv_rtc.c 1 - drivers\drv_hp_rtc.c + drivers\drv_rtc.c + + + hyper_flash_boot.c + 1 + drivers\hyper_flash_boot.c - - drv_eth.c 1 drivers\drv_eth.c - - fsl_phy.c 1 drivers\fsl_phy.c - - drv_sdio.c 1 @@ -479,421 +458,301 @@ 1 Libraries\drivers\fsl_adc.c - - fsl_adc_etc.c 1 Libraries\drivers\fsl_adc_etc.c - - fsl_aipstz.c 1 Libraries\drivers\fsl_aipstz.c - - fsl_aoi.c 1 Libraries\drivers\fsl_aoi.c - - fsl_bee.c 1 Libraries\drivers\fsl_bee.c - - fsl_cache.c 1 Libraries\drivers\fsl_cache.c - - fsl_clock.c 1 Libraries\drivers\fsl_clock.c - - fsl_cmp.c 1 Libraries\drivers\fsl_cmp.c - - fsl_common.c 1 Libraries\drivers\fsl_common.c - - fsl_csi.c 1 Libraries\drivers\fsl_csi.c - - fsl_dcdc.c 1 Libraries\drivers\fsl_dcdc.c - - fsl_dcp.c 1 Libraries\drivers\fsl_dcp.c - - fsl_dmamux.c 1 Libraries\drivers\fsl_dmamux.c - - fsl_edma.c 1 Libraries\drivers\fsl_edma.c - - fsl_elcdif.c 1 Libraries\drivers\fsl_elcdif.c - - fsl_enc.c 1 Libraries\drivers\fsl_enc.c - - fsl_enet.c 1 Libraries\drivers\fsl_enet.c - - fsl_ewm.c 1 Libraries\drivers\fsl_ewm.c - - fsl_flexcan.c 1 Libraries\drivers\fsl_flexcan.c - - fsl_flexio.c 1 Libraries\drivers\fsl_flexio.c - - fsl_flexio_i2c_master.c 1 Libraries\drivers\fsl_flexio_i2c_master.c - - fsl_flexio_i2s.c 1 Libraries\drivers\fsl_flexio_i2s.c - - fsl_flexio_i2s_edma.c 1 Libraries\drivers\fsl_flexio_i2s_edma.c - - fsl_flexio_spi.c 1 Libraries\drivers\fsl_flexio_spi.c - - fsl_flexio_spi_edma.c 1 Libraries\drivers\fsl_flexio_spi_edma.c - - fsl_flexio_uart.c 1 Libraries\drivers\fsl_flexio_uart.c - - fsl_flexio_uart_edma.c 1 Libraries\drivers\fsl_flexio_uart_edma.c - - fsl_flexram.c 1 Libraries\drivers\fsl_flexram.c - - fsl_flexspi.c 1 Libraries\drivers\fsl_flexspi.c - - fsl_gpc.c 1 Libraries\drivers\fsl_gpc.c - - fsl_gpio.c 1 Libraries\drivers\fsl_gpio.c - - fsl_gpt.c 1 Libraries\drivers\fsl_gpt.c - - fsl_kpp.c 1 Libraries\drivers\fsl_kpp.c - - fsl_lpi2c.c 1 Libraries\drivers\fsl_lpi2c.c - - fsl_lpi2c_edma.c 1 Libraries\drivers\fsl_lpi2c_edma.c - - fsl_lpspi.c 1 Libraries\drivers\fsl_lpspi.c - - fsl_lpspi_edma.c 1 Libraries\drivers\fsl_lpspi_edma.c - - fsl_lpuart.c 1 Libraries\drivers\fsl_lpuart.c - - fsl_lpuart_edma.c 1 Libraries\drivers\fsl_lpuart_edma.c - - fsl_pit.c 1 Libraries\drivers\fsl_pit.c - - fsl_pmu.c 1 Libraries\drivers\fsl_pmu.c - - fsl_pwm.c 1 Libraries\drivers\fsl_pwm.c - - fsl_pxp.c 1 Libraries\drivers\fsl_pxp.c - - fsl_qtmr.c 1 Libraries\drivers\fsl_qtmr.c - - fsl_rtwdog.c 1 Libraries\drivers\fsl_rtwdog.c - - fsl_sai.c 1 Libraries\drivers\fsl_sai.c - - fsl_sai_edma.c 1 Libraries\drivers\fsl_sai_edma.c - - fsl_semc.c 1 Libraries\drivers\fsl_semc.c - - fsl_snvs_hp.c 1 Libraries\drivers\fsl_snvs_hp.c - - fsl_snvs_lp.c 1 Libraries\drivers\fsl_snvs_lp.c - - fsl_spdif.c 1 Libraries\drivers\fsl_spdif.c - - fsl_spdif_edma.c 1 Libraries\drivers\fsl_spdif_edma.c - - fsl_src.c 1 Libraries\drivers\fsl_src.c - - fsl_trng.c 1 Libraries\drivers\fsl_trng.c - - fsl_tsc.c 1 Libraries\drivers\fsl_tsc.c - - fsl_usdhc.c 1 Libraries\drivers\fsl_usdhc.c - - fsl_wdog.c 1 Libraries\drivers\fsl_wdog.c - - fsl_xbara.c 1 Libraries\drivers\fsl_xbara.c - - fsl_xbarb.c 1 Libraries\drivers\fsl_xbarb.c - - system_MIMXRT1052.c 1 Libraries\system_MIMXRT1052.c - - startup_MIMXRT1052.s 2 @@ -909,85 +768,61 @@ 1 ..\..\src\clock.c - - components.c 1 ..\..\src\components.c - - device.c 1 ..\..\src\device.c - - idle.c 1 ..\..\src\idle.c - - ipc.c 1 ..\..\src\ipc.c - - irq.c 1 ..\..\src\irq.c - - kservice.c 1 ..\..\src\kservice.c - - memheap.c 1 ..\..\src\memheap.c - - object.c 1 ..\..\src\object.c - - scheduler.c 1 ..\..\src\scheduler.c - - signal.c 1 ..\..\src\signal.c - - thread.c 1 ..\..\src\thread.c - - timer.c 1 @@ -1003,29 +838,21 @@ 1 ..\..\libcpu\arm\cortex-m7\cpuport.c - - context_rvds.S 2 ..\..\libcpu\arm\cortex-m7\context_rvds.S - - backtrace.c 1 ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\libcpu\arm\common\div0.c - - showmem.c 1 @@ -1041,50 +868,36 @@ 1 ..\..\components\dfs\src\dfs.c - - dfs_file.c 1 ..\..\components\dfs\src\dfs_file.c - - dfs_fs.c 1 ..\..\components\dfs\src\dfs_fs.c - - dfs_posix.c 1 ..\..\components\dfs\src\dfs_posix.c - - devfs.c 1 ..\..\components\dfs\filesystems\devfs\devfs.c - - dfs_elm.c 1 ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - ff.c 1 ..\..\components\dfs\filesystems\elmfat\ff.c - - ccsbcs.c 1 @@ -1100,113 +913,81 @@ 1 ..\..\components\drivers\i2c\i2c_core.c - - i2c_dev.c 1 ..\..\components\drivers\i2c\i2c_dev.c - - i2c-bit-ops.c 1 ..\..\components\drivers\i2c\i2c-bit-ops.c - - pin.c 1 ..\..\components\drivers\misc\pin.c - - rtc.c 1 ..\..\components\drivers\rtc\rtc.c - - block_dev.c 1 ..\..\components\drivers\sdio\block_dev.c - - mmcsd_core.c 1 ..\..\components\drivers\sdio\mmcsd_core.c - - sd.c 1 ..\..\components\drivers\sdio\sd.c - - sdio.c 1 ..\..\components\drivers\sdio\sdio.c - - mmc.c 1 ..\..\components\drivers\sdio\mmc.c - - serial.c 1 ..\..\components\drivers\serial\serial.c - - completion.c 1 ..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\components\drivers\src\pipe.c - - ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 @@ -1222,106 +1003,76 @@ 1 ..\..\components\finsh\shell.c - - symbol.c 1 ..\..\components\finsh\symbol.c - - cmd.c 1 ..\..\components\finsh\cmd.c - - msh.c 1 ..\..\components\finsh\msh.c - - msh_cmd.c 1 ..\..\components\finsh\msh_cmd.c - - msh_file.c 1 ..\..\components\finsh\msh_file.c - - finsh_compiler.c 1 ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 @@ -1337,36 +1088,26 @@ 1 ..\..\components\libc\compilers\armlibc\libc.c - - libc_syms.c 1 ..\..\components\libc\compilers\armlibc\libc_syms.c - - mem_std.c 1 ..\..\components\libc\compilers\armlibc\mem_std.c - - stdio.c 1 ..\..\components\libc\compilers\armlibc\stdio.c - - stubs.c 1 ..\..\components\libc\compilers\armlibc\stubs.c - - time.c 1 @@ -1382,246 +1123,176 @@ 1 ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - api_lib.c 1 ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - api_msg.c 1 ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - err.c 1 ..\..\components\net\lwip-2.0.2\src\api\err.c - - netbuf.c 1 ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - netdb.c 1 ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - netifapi.c 1 ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - sockets.c 1 ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - tcpip.c 1 ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - def.c 1 ..\..\components\net\lwip-2.0.2\src\core\def.c - - dns.c 1 ..\..\components\net\lwip-2.0.2\src\core\dns.c - - inet_chksum.c 1 ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - init.c 1 ..\..\components\net\lwip-2.0.2\src\core\init.c - - ip.c 1 ..\..\components\net\lwip-2.0.2\src\core\ip.c - - memp.c 1 ..\..\components\net\lwip-2.0.2\src\core\memp.c - - netif.c 1 ..\..\components\net\lwip-2.0.2\src\core\netif.c - - pbuf.c 1 ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - raw.c 1 ..\..\components\net\lwip-2.0.2\src\core\raw.c - - stats.c 1 ..\..\components\net\lwip-2.0.2\src\core\stats.c - - sys.c 1 ..\..\components\net\lwip-2.0.2\src\core\sys.c - - tcp.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - tcp_in.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - tcp_out.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - timeouts.c 1 ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - udp.c 1 ..\..\components\net\lwip-2.0.2\src\core\udp.c - - ethernet.c 1 ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - ethernetif.c 1 ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - lowpan6.c 1 ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - autoip.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - dhcp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - etharp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - icmp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - igmp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - ip4.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - ip4_addr.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - ip4_frag.c 1 @@ -1629,19 +1300,24 @@ + + ::CMSIS + + - + - + - + - + + diff --git a/bsp/imxrt1052-evk/rtconfig.h b/bsp/imxrt1052-evk/rtconfig.h index 664aeb5458..79c7553e99 100644 --- a/bsp/imxrt1052-evk/rtconfig.h +++ b/bsp/imxrt1052-evk/rtconfig.h @@ -8,9 +8,7 @@ #define RT_NAME_MAX 8 #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 #define RT_DEBUG @@ -19,7 +17,6 @@ #define RT_DEBUG_THREAD 0 #define RT_USING_HOOK #define IDLE_THREAD_STACK_SIZE 256 -/* RT_USING_TIMER_SOFT is not set */ /* Inter-Thread communication */ @@ -28,26 +25,19 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ -/* RT_USING_MEMPOOL is not set */ #define RT_USING_MEMHEAP -/* RT_USING_NOHEAP is not set */ -/* RT_USING_SMALL_MEM is not set */ -/* RT_USING_SLAB is not set */ #define RT_USING_MEMHEAP_AS_HEAP #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE -/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -/* RT_USING_MODULE is not set */ #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -60,7 +50,6 @@ /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -73,10 +62,8 @@ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ /* Device virtual file system */ @@ -91,67 +78,38 @@ #define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS -/* RT_DFS_ELM_USE_LFN_0 is not set */ -/* RT_DFS_ELM_USE_LFN_1 is not set */ -/* RT_DFS_ELM_USE_LFN_2 is not set */ #define RT_DFS_ELM_USE_LFN_3 #define RT_DFS_ELM_USE_LFN 3 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -/* RT_DFS_ELM_USE_ERASE is not set */ #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_NET is not set */ -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ -/* RT_USING_DFS_JFFS2 is not set */ -/* RT_USING_DFS_NFS is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ #define RT_USING_RTC -/* RT_USING_SOFT_RTC is not set */ -/* RTC_SYNC_USING_NTP is not set */ #define RT_USING_SDIO -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_WIFI is not set */ /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ -/* RT_USING_POSIX is not set */ -/* HAVE_SYS_SIGNALS is not set */ /* Network stack */ /* light weight TCP/IP stack */ #define RT_USING_LWIP -/* RT_USING_LWIP141 is not set */ #define RT_USING_LWIP202 -/* RT_USING_LWIP_IPV6 is not set */ -/* RT_LWIP_IGMP is not set */ #define RT_LWIP_ICMP -/* RT_LWIP_SNMP is not set */ #define RT_LWIP_DNS #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 @@ -164,8 +122,6 @@ #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP -/* RT_LWIP_RAW is not set */ -/* RT_LWIP_PPP is not set */ #define RT_MEMP_NUM_NETCONN 8 #define RT_LWIP_PBUF_NUM 16 #define RT_LWIP_RAW_PCB_NUM 4 @@ -180,33 +136,24 @@ #define RT_LWIP_ETHTHREAD_PRIORITY 12 #define RT_LWIP_ETHTHREAD_STACKSIZE 1024 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -/* RT_LWIP_REASSEMBLY_FRAG is not set */ #define LWIP_NETIF_STATUS_CALLBACK 1 #define SO_REUSE 1 #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 -/* RT_LWIP_NETIF_LOOPBACK is not set */ #define LWIP_NETIF_LOOPBACK 0 /* Modbus master and slave stack */ -/* RT_USING_MODBUS is not set */ -/* LWIP_USING_DHCPD is not set */ /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_LOGTRACE is not set */ -/* RT_USING_RYM is not set */ /* ARM CMSIS */ -/* RT_USING_CMSIS_OS is not set */ -/* RT_USING_RTT_CMSIS is not set */ /* RT-Thread online packages */ @@ -214,72 +161,44 @@ /* RT-Thread GUI Engine */ -/* PKG_USING_GUIENGINE is not set */ -/* PKG_USING_PERSIMMON is not set */ -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ -/* PKG_USING_NETUTILS is not set */ /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_IPERF is not set */ /* miscellaneous packages */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* PKG_USING_QUICKLZ is not set */ /* example package: hello */ -/* PKG_USING_HELLO is not set */ -/* PKG_USING_MULTIBUTTON is not set */ #define SOC_IMXRT1052 +#define BOARD_RT1050_EVK + +/* RT1050_EVK Bsp Config */ + +/* Select uart device */ + #define RT_USING_UART1 -#define RT_USING_HP_RTC +#define RT_USING_SDRAM +#define RT_USING_RTC_HP #endif From e04c3cecc8f43d892fca33669f566abff7e455af Mon Sep 17 00:00:00 2001 From: ZYH Date: Wed, 28 Mar 2018 10:10:31 +0800 Subject: [PATCH 03/67] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E9=BB=98=E8=AE=A4?= =?UTF-8?q?=E5=B7=A5=E7=A8=8B=E4=B8=8Emenuconfig=E5=90=8C=E6=AD=A5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32f4xx-HAL/project.uvoptx | 1589 ++++++++++++++++++++++++++++- bsp/stm32f4xx-HAL/project.uvprojx | 359 ++----- 2 files changed, 1644 insertions(+), 304 deletions(-) diff --git a/bsp/stm32f4xx-HAL/project.uvoptx b/bsp/stm32f4xx-HAL/project.uvoptx index 3ef0a82752..737a535dc0 100644 --- a/bsp/stm32f4xx-HAL/project.uvoptx +++ b/bsp/stm32f4xx-HAL/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -101,7 +101,7 @@ 0 0 1 - 5 + 0 @@ -112,18 +112,13 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL - - 0 - ST-LINKIII-KEIL_SWO - -U0664FF545449677267026033 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_256.FLM -FS08000000 -FL040000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM) - 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_256 -FL040000 -FS08000000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM) @@ -178,4 +173,1580 @@ + + Drivers + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + drivers/board.c + board.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + drivers/stm32f4xx_it.c + stm32f4xx_it.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + drivers/drv_gpio.c + drv_gpio.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + drivers/drv_usart.c + drv_usart.c + 0 + 0 + + + + + Applications + 0 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + applications/main.c + main.c + 0 + 0 + + + + + STM32F4xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + stm32f4xx_hal.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c + stm32f4xx_hal_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c + stm32f4xx_hal_adc_ex.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c + stm32f4xx_hal_can.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c + stm32f4xx_hal_cec.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + stm32f4xx_hal_cortex.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c + stm32f4xx_hal_crc.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c + stm32f4xx_hal_cryp.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c + stm32f4xx_hal_cryp_ex.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c + stm32f4xx_hal_dac.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c + stm32f4xx_hal_dac_ex.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c + stm32f4xx_hal_dcmi.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c + stm32f4xx_hal_dcmi_ex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c + stm32f4xx_hal_dfsdm.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + stm32f4xx_hal_dma.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c + stm32f4xx_hal_dma2d.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + stm32f4xx_hal_dma_ex.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c + stm32f4xx_hal_dsi.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c + stm32f4xx_hal_eth.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + stm32f4xx_hal_flash.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + stm32f4xx_hal_flash_ex.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + stm32f4xx_hal_flash_ramfunc.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c + stm32f4xx_hal_fmpi2c.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c + stm32f4xx_hal_fmpi2c_ex.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + stm32f4xx_hal_gpio.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c + stm32f4xx_hal_hash.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c + stm32f4xx_hal_hash_ex.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c + stm32f4xx_hal_hcd.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + stm32f4xx_hal_i2c.c + 0 + 0 + + + 3 + 35 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + stm32f4xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 36 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c + stm32f4xx_hal_i2s.c + 0 + 0 + + + 3 + 37 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c + stm32f4xx_hal_i2s_ex.c + 0 + 0 + + + 3 + 38 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c + stm32f4xx_hal_irda.c + 0 + 0 + + + 3 + 39 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c + stm32f4xx_hal_iwdg.c + 0 + 0 + + + 3 + 40 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c + stm32f4xx_hal_lptim.c + 0 + 0 + + + 3 + 41 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c + stm32f4xx_hal_ltdc.c + 0 + 0 + + + 3 + 42 + 1 + 0 + 0 + 0 + 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Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + stm32f4xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 51 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c + stm32f4xx_hal_qspi.c + 0 + 0 + + + 3 + 52 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + stm32f4xx_hal_rcc.c + 0 + 0 + + + 3 + 53 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + stm32f4xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 54 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c + stm32f4xx_hal_rng.c + 0 + 0 + + + 3 + 55 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c + stm32f4xx_hal_rtc.c + 0 + 0 + + + 3 + 56 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c + stm32f4xx_hal_rtc_ex.c + 0 + 0 + + + 3 + 57 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c + stm32f4xx_hal_sai.c + 0 + 0 + + + 3 + 58 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c + stm32f4xx_hal_sai_ex.c + 0 + 0 + + + 3 + 59 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c + stm32f4xx_hal_sd.c + 0 + 0 + + + 3 + 60 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c + stm32f4xx_hal_sdram.c + 0 + 0 + + + 3 + 61 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c + stm32f4xx_hal_smartcard.c + 0 + 0 + + + 3 + 62 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c + stm32f4xx_hal_spdifrx.c + 0 + 0 + + + 3 + 63 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + stm32f4xx_hal_spi.c + 0 + 0 + + + 3 + 64 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c + stm32f4xx_hal_sram.c + 0 + 0 + + + 3 + 65 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + stm32f4xx_hal_tim.c + 0 + 0 + + + 3 + 66 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + stm32f4xx_hal_tim_ex.c + 0 + 0 + + + 3 + 67 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + stm32f4xx_hal_uart.c + 0 + 0 + + + 3 + 68 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c + stm32f4xx_hal_usart.c + 0 + 0 + + + 3 + 69 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c + stm32f4xx_hal_wwdg.c + 0 + 0 + + + 3 + 70 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c + stm32f4xx_ll_adc.c + 0 + 0 + + + 3 + 71 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c + stm32f4xx_ll_crc.c + 0 + 0 + + + 3 + 72 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c + stm32f4xx_ll_dac.c + 0 + 0 + + + 3 + 73 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c + stm32f4xx_ll_dma.c + 0 + 0 + + + 3 + 74 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma2d.c + stm32f4xx_ll_dma2d.c + 0 + 0 + + + 3 + 75 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c + stm32f4xx_ll_exti.c + 0 + 0 + + + 3 + 76 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c + stm32f4xx_ll_fmc.c + 0 + 0 + + + 3 + 77 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c + stm32f4xx_ll_fsmc.c + 0 + 0 + + + 3 + 78 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c + stm32f4xx_ll_gpio.c + 0 + 0 + + + 3 + 79 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c + stm32f4xx_ll_i2c.c + 0 + 0 + + + 3 + 80 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c + stm32f4xx_ll_lptim.c + 0 + 0 + + + 3 + 81 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c + stm32f4xx_ll_pwr.c + 0 + 0 + + + 3 + 82 + 1 + 0 + 0 + 0 + Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c + stm32f4xx_ll_rcc.c + 0 + 0 + + + 3 + 83 + 1 + 0 + 0 + 0 + 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../../src/object.c + object.c + 0 + 0 + + + 5 + 104 + 1 + 0 + 0 + 0 + ../../src/scheduler.c + scheduler.c + 0 + 0 + + + 5 + 105 + 1 + 0 + 0 + 0 + ../../src/signal.c + signal.c + 0 + 0 + + + 5 + 106 + 1 + 0 + 0 + 0 + ../../src/thread.c + thread.c + 0 + 0 + + + 5 + 107 + 1 + 0 + 0 + 0 + ../../src/timer.c + timer.c + 0 + 0 + + + + + CORTEX-M4 + 0 + 0 + 0 + 0 + + 6 + 108 + 1 + 0 + 0 + 0 + ../../libcpu/arm/cortex-m4/cpuport.c + cpuport.c + 0 + 0 + + + 6 + 109 + 2 + 0 + 0 + 0 + ../../libcpu/arm/cortex-m4/context_rvds.S + context_rvds.S + 0 + 0 + + + 6 + 110 + 1 + 0 + 0 + 0 + ../../libcpu/arm/common/backtrace.c + backtrace.c + 0 + 0 + + + 6 + 111 + 1 + 0 + 0 + 0 + ../../libcpu/arm/common/div0.c + div0.c + 0 + 0 + + + 6 + 112 + 1 + 0 + 0 + 0 + ../../libcpu/arm/common/showmem.c + showmem.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 7 + 113 + 1 + 0 + 0 + 0 + ../../components/drivers/misc/pin.c + pin.c + 0 + 0 + + + 7 + 114 + 1 + 0 + 0 + 0 + ../../components/drivers/serial/serial.c + serial.c + 0 + 0 + + + 7 + 115 + 1 + 0 + 0 + 0 + ../../components/drivers/src/completion.c + completion.c + 0 + 0 + + + 7 + 116 + 1 + 0 + 0 + 0 + ../../components/drivers/src/dataqueue.c + dataqueue.c + 0 + 0 + + + 7 + 117 + 1 + 0 + 0 + 0 + ../../components/drivers/src/pipe.c + pipe.c + 0 + 0 + + + 7 + 118 + 1 + 0 + 0 + 0 + ../../components/drivers/src/ringbuffer.c + ringbuffer.c + 0 + 0 + + + 7 + 119 + 1 + 0 + 0 + 0 + ../../components/drivers/src/waitqueue.c + waitqueue.c + 0 + 0 + + + 7 + 120 + 1 + 0 + 0 + 0 + ../../components/drivers/src/workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 8 + 121 + 1 + 0 + 0 + 0 + ../../components/finsh/shell.c + shell.c + 0 + 0 + + + 8 + 122 + 1 + 0 + 0 + 0 + ../../components/finsh/symbol.c + symbol.c + 0 + 0 + + + 8 + 123 + 1 + 0 + 0 + 0 + ../../components/finsh/cmd.c + cmd.c + 0 + 0 + + + 8 + 124 + 1 + 0 + 0 + 0 + ../../components/finsh/msh.c + msh.c + 0 + 0 + + + 8 + 125 + 1 + 0 + 0 + 0 + ../../components/finsh/msh_cmd.c + msh_cmd.c + 0 + 0 + + + 8 + 126 + 1 + 0 + 0 + 0 + ../../components/finsh/msh_file.c + msh_file.c + 0 + 0 + + + diff --git a/bsp/stm32f4xx-HAL/project.uvprojx b/bsp/stm32f4xx-HAL/project.uvprojx index 829333228e..f7d6ea872a 100644 --- a/bsp/stm32f4xx-HAL/project.uvprojx +++ b/bsp/stm32f4xx-HAL/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread_stm32f4xx @@ -11,33 +14,33 @@ 0 - STM32F401RCTx + STM32F407VGTx STMicroelectronics - Keil.STM32F4xx_DFP.2.11.0 + Keil.STM32F4xx_DFP.2.12.0 http://www.keil.com/pack - IRAM(0x20000000,0x10000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32F401RCTx$CMSIS\Flash\STM32F4xx_256.FLM)) + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) 0 - $$Device:STM32F401RCTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - - - - $$Device:STM32F401RCTx$CMSIS\SVD\STM32F401x.svd + $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output @H.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - "" () - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -181,7 +184,7 @@ 0 0 2 - 0 + 1 0 8 0 @@ -189,7 +192,7 @@ 0 0 3 - 3 + 4 0 0 0 @@ -241,12 +244,12 @@ 0 0x20000000 - 0x10000 + 0x20000 1 0x8000000 - 0x40000 + 0x100000 0 @@ -271,7 +274,7 @@ 1 0x8000000 - 0x40000 + 0x100000 1 @@ -296,15 +299,15 @@ 0 0x20000000 - 0x10000 + 0x20000 0 - 0x0 - 0x0 + 0x10000000 + 0x10000 - + 1 @@ -330,9 +333,9 @@ 0 0 - + USE_HAL_DRIVER, STM32F407xx - + drivers;applications;.;Libraries/STM32F4xx_HAL_Driver/Inc;Libraries/CMSIS/Device/ST/STM32F4xx/Include;Libraries/CMSIS/Include;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/finsh @@ -348,10 +351,10 @@ 0 0 - - - - + + + + @@ -363,13 +366,13 @@ 0 0x08000000 0x20000000 - + .\stm32_rom.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + @@ -382,22 +385,16 @@ 1 drivers/board.c - - stm32f4xx_it.c 1 drivers/stm32f4xx_it.c - - drv_gpio.c 1 drivers/drv_gpio.c - - drv_usart.c 1 @@ -423,589 +420,421 @@ 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c - - stm32f4xx_hal_adc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c - - stm32f4xx_hal_adc_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c - - stm32f4xx_hal_can.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c - - stm32f4xx_hal_cec.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c - - stm32f4xx_hal_cortex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c - - stm32f4xx_hal_crc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c - - stm32f4xx_hal_cryp.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c - - stm32f4xx_hal_cryp_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c - - stm32f4xx_hal_dac.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c - - stm32f4xx_hal_dac_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c - - stm32f4xx_hal_dcmi.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c - - stm32f4xx_hal_dcmi_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c - - stm32f4xx_hal_dfsdm.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c - - stm32f4xx_hal_dma.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c - - stm32f4xx_hal_dma2d.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c - - stm32f4xx_hal_dma_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c - - stm32f4xx_hal_dsi.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c - - stm32f4xx_hal_eth.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c - - stm32f4xx_hal_flash.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c - - stm32f4xx_hal_flash_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c - - stm32f4xx_hal_flash_ramfunc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c - - stm32f4xx_hal_fmpi2c.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c - - stm32f4xx_hal_fmpi2c_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c - - stm32f4xx_hal_gpio.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c - - stm32f4xx_hal_hash.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c - - stm32f4xx_hal_hash_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c - - stm32f4xx_hal_hcd.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c - - stm32f4xx_hal_i2c.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c - - stm32f4xx_hal_i2c_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c - - stm32f4xx_hal_i2s.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c - - stm32f4xx_hal_i2s_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c - - stm32f4xx_hal_irda.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c - - stm32f4xx_hal_iwdg.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c - - stm32f4xx_hal_lptim.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c - - stm32f4xx_hal_ltdc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c - - stm32f4xx_hal_ltdc_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c - - stm32f4xx_hal_mmc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c - - stm32f4xx_hal_nand.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c - - stm32f4xx_hal_nor.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c - - stm32f4xx_hal_pccard.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c - - stm32f4xx_hal_pcd.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c - - stm32f4xx_hal_pcd_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c - - stm32f4xx_hal_pwr.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c - - stm32f4xx_hal_pwr_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c - - stm32f4xx_hal_qspi.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c - - stm32f4xx_hal_rcc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c - - stm32f4xx_hal_rcc_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c - - stm32f4xx_hal_rng.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c - - stm32f4xx_hal_rtc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c - - stm32f4xx_hal_rtc_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c - - stm32f4xx_hal_sai.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c - - stm32f4xx_hal_sai_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c - - stm32f4xx_hal_sd.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c - - stm32f4xx_hal_sdram.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c - - stm32f4xx_hal_smartcard.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c - - stm32f4xx_hal_spdifrx.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c - - stm32f4xx_hal_spi.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c - - stm32f4xx_hal_sram.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c - - stm32f4xx_hal_tim.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c - - stm32f4xx_hal_tim_ex.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c - - stm32f4xx_hal_uart.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c - - stm32f4xx_hal_usart.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c - - stm32f4xx_hal_wwdg.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c - - stm32f4xx_ll_adc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c - - stm32f4xx_ll_crc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c - - stm32f4xx_ll_dac.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c - - stm32f4xx_ll_dma.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c - - stm32f4xx_ll_dma2d.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma2d.c - - stm32f4xx_ll_exti.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c - - stm32f4xx_ll_fmc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c - - stm32f4xx_ll_fsmc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c - - stm32f4xx_ll_gpio.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c - - stm32f4xx_ll_i2c.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c - - stm32f4xx_ll_lptim.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c - - stm32f4xx_ll_pwr.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c - - stm32f4xx_ll_rcc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c - - stm32f4xx_ll_rng.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c - - stm32f4xx_ll_rtc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c - - stm32f4xx_ll_sdmmc.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c - - stm32f4xx_ll_spi.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c - - stm32f4xx_ll_tim.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c - - stm32f4xx_ll_usart.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c - - stm32f4xx_ll_usb.c 1 Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c - - stm32f4xx_ll_utils.c 1 @@ -1021,8 +850,6 @@ 1 Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c - - startup_stm32f407xx.s 2 @@ -1038,99 +865,71 @@ 1 ../../src/clock.c - - components.c 1 ../../src/components.c - - device.c 1 ../../src/device.c - - idle.c 1 ../../src/idle.c - - ipc.c 1 ../../src/ipc.c - - irq.c 1 ../../src/irq.c - - kservice.c 1 ../../src/kservice.c - - mem.c 1 ../../src/mem.c - - memheap.c 1 ../../src/memheap.c - - mempool.c 1 ../../src/mempool.c - - object.c 1 ../../src/object.c - - scheduler.c 1 ../../src/scheduler.c - - signal.c 1 ../../src/signal.c - - thread.c 1 ../../src/thread.c - - timer.c 1 @@ -1146,29 +945,21 @@ 1 ../../libcpu/arm/cortex-m4/cpuport.c - - context_rvds.S 2 ../../libcpu/arm/cortex-m4/context_rvds.S - - backtrace.c 1 ../../libcpu/arm/common/backtrace.c - - div0.c 1 ../../libcpu/arm/common/div0.c - - showmem.c 1 @@ -1184,50 +975,36 @@ 1 ../../components/drivers/misc/pin.c - - serial.c 1 ../../components/drivers/serial/serial.c - - completion.c 1 ../../components/drivers/src/completion.c - - dataqueue.c 1 ../../components/drivers/src/dataqueue.c - - pipe.c 1 ../../components/drivers/src/pipe.c - - ringbuffer.c 1 ../../components/drivers/src/ringbuffer.c - - waitqueue.c 1 ../../components/drivers/src/waitqueue.c - - workqueue.c 1 @@ -1243,36 +1020,26 @@ 1 ../../components/finsh/shell.c - - symbol.c 1 ../../components/finsh/symbol.c - - cmd.c 1 ../../components/finsh/cmd.c - - msh.c 1 ../../components/finsh/msh.c - - msh_cmd.c 1 ../../components/finsh/msh_cmd.c - - msh_file.c 1 @@ -1283,9 +1050,11 @@ + - - - + + + + From b09445cbfe1e8105b244a9e1819c2826d1be14e9 Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Wed, 28 Mar 2018 10:17:24 +0800 Subject: [PATCH 04/67] [Kernel][memheap] fix rt_realloc bugs - missing free old memory after malloc new - free memory when new size is zero --- src/memheap.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/memheap.c b/src/memheap.c index dcd9114620..7317ebdbab 100644 --- a/src/memheap.c +++ b/src/memheap.c @@ -659,6 +659,12 @@ void *rt_realloc(void *rmem, rt_size_t newsize) if (rmem == RT_NULL) return rt_malloc(newsize); + if (newsize == 0) + { + rt_free(rmem); + return RT_NULL; + } + /* get old memory item */ header_ptr = (struct rt_memheap_item *) ((rt_uint8_t *)rmem - RT_MEMHEAP_SIZE); @@ -678,6 +684,8 @@ void *rt_realloc(void *rmem, rt_size_t newsize) rt_memcpy(new_ptr, rmem, oldsize); else rt_memcpy(new_ptr, rmem, newsize); + + rt_free(rmem); } } From 342f883acbde330afd39f7456ac632b36f5dcc24 Mon Sep 17 00:00:00 2001 From: lzp <417350690@qq.com> Date: Wed, 28 Mar 2018 14:40:05 +0800 Subject: [PATCH 05/67] [BSP]NUC472 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.增加MDK4工程 2.修复GCC的链接文件 栈内存与动态内存地址重复 3.修复EMAC驱动宏错误 --- .../Nuvoton/NUC472_442/Source/GCC/startup.c | 6 +- bsp/nuvoton_nuc472/README.md | 2 +- bsp/nuvoton_nuc472/drivers/board.c | 4 +- bsp/nuvoton_nuc472/drivers/nuc472_eth.c | 6 +- bsp/nuvoton_nuc472/ldscripts/libs.ld | 8 - bsp/nuvoton_nuc472/ldscripts/mem.ld | 25 - bsp/nuvoton_nuc472/ldscripts/sections.ld | 392 ++---- bsp/nuvoton_nuc472/project.uvproj | 1153 +++++++++++++++++ bsp/nuvoton_nuc472/template.uvproj | 407 ++++++ 9 files changed, 1643 insertions(+), 360 deletions(-) delete mode 100644 bsp/nuvoton_nuc472/ldscripts/libs.ld delete mode 100644 bsp/nuvoton_nuc472/ldscripts/mem.ld create mode 100644 bsp/nuvoton_nuc472/project.uvproj create mode 100644 bsp/nuvoton_nuc472/template.uvproj diff --git a/bsp/nuvoton_nuc472/Libraries/Device/Nuvoton/NUC472_442/Source/GCC/startup.c b/bsp/nuvoton_nuc472/Libraries/Device/Nuvoton/NUC472_442/Source/GCC/startup.c index c4bc353cf6..388f88671f 100644 --- a/bsp/nuvoton_nuc472/Libraries/Device/Nuvoton/NUC472_442/Source/GCC/startup.c +++ b/bsp/nuvoton_nuc472/Libraries/Device/Nuvoton/NUC472_442/Source/GCC/startup.c @@ -150,9 +150,9 @@ extern unsigned char _sdata; // End address for the .data section// defined in linker script extern unsigned char _edata; // Begin address for the .bss section// defined in linker script -extern unsigned char __bss_start__; +extern unsigned char __bss_start; // End address for the .bss section// defined in linker script -extern unsigned char __bss_end__; +extern unsigned char __bss_end; extern int entry(void); @@ -333,7 +333,7 @@ pHandler g_pfnVectors[] = void _start() { memcpy(&_sdata, &_sidata, &_edata - &_sdata); - memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__); + memset(&__bss_start, 0, &__bss_end - &__bss_start); } static void Reset_Handler(void) diff --git a/bsp/nuvoton_nuc472/README.md b/bsp/nuvoton_nuc472/README.md index a3febd4e36..5bc4e9c7b3 100644 --- a/bsp/nuvoton_nuc472/README.md +++ b/bsp/nuvoton_nuc472/README.md @@ -3,7 +3,7 @@ NuTiny-EVB-NUC472 ## note: - support the GCC MDK5 IAR + support the GCC MDK4 MDK5 IAR **TODO** diff --git a/bsp/nuvoton_nuc472/drivers/board.c b/bsp/nuvoton_nuc472/drivers/board.c index f8135a795e..3184e138f9 100644 --- a/bsp/nuvoton_nuc472/drivers/board.c +++ b/bsp/nuvoton_nuc472/drivers/board.c @@ -22,7 +22,7 @@ extern int Image$$RW_IRAM1$$ZI$$Limit; #elif __ICCARM__ #pragma section="HEAP" #else -extern int __bss_end__; +extern int __bss_end; #endif /** @@ -80,7 +80,7 @@ void rt_hw_board_init(void) rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END); #else /* init memory system */ - rt_system_heap_init((void*)&__bss_end__, (void*)SRAM_END); + rt_system_heap_init((void*)&__bss_end, (void*)SRAM_END); #endif #endif /* RT_USING_HEAP */ diff --git a/bsp/nuvoton_nuc472/drivers/nuc472_eth.c b/bsp/nuvoton_nuc472/drivers/nuc472_eth.c index de9f32eedd..e082669ca8 100644 --- a/bsp/nuvoton_nuc472/drivers/nuc472_eth.c +++ b/bsp/nuvoton_nuc472/drivers/nuc472_eth.c @@ -181,7 +181,7 @@ static void init_rx_desc(rt_nuc472_emac_t emac) emac->rx_desc[i].status1 = OWNERSHIP_EMAC; emac->rx_desc[i].buf = &emac->rx_buf[i][0]; emac->rx_desc[i].status2 = 0; - emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % TX_DESCRIPTOR_NUM]; + emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % RX_DESCRIPTOR_NUM]; } emac_base->RXDSA = (unsigned int)&emac->rx_desc[0]; return; @@ -205,8 +205,8 @@ static void set_mac_addr(rt_nuc472_emac_t emac, rt_uint8_t *addr) void EMAC_init(rt_nuc472_emac_t emac, rt_uint8_t *mac_addr) { + EMAC_T *emac_base = emac->emac_base; RT_ASSERT(emac->dev_addr != RT_NULL); - EMAC_T *emac_base = emac->emac_base; CLK_EnableModuleClock(EMAC_MODULE); @@ -445,12 +445,12 @@ rt_err_t rt_nuc472_emac_tx(rt_device_t dev, struct pbuf* p) struct pbuf *rt_nuc472_emac_rx(rt_device_t dev) { rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev; + unsigned int status; struct pbuf* p; /* init p pointer */ p = RT_NULL; - unsigned int status; status = emac->cur_rx_desc_ptr->status1; if(status & OWNERSHIP_EMAC) diff --git a/bsp/nuvoton_nuc472/ldscripts/libs.ld b/bsp/nuvoton_nuc472/ldscripts/libs.ld deleted file mode 100644 index 70fea89265..0000000000 --- a/bsp/nuvoton_nuc472/ldscripts/libs.ld +++ /dev/null @@ -1,8 +0,0 @@ - -/* - * Placeholder to list other libraries required by the application. - -GROUP( -) - - */ diff --git a/bsp/nuvoton_nuc472/ldscripts/mem.ld b/bsp/nuvoton_nuc472/ldscripts/mem.ld deleted file mode 100644 index 351c8f767a..0000000000 --- a/bsp/nuvoton_nuc472/ldscripts/mem.ld +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Memory Spaces Definitions. - * - * Need modifying for a specific board. - * FLASH.ORIGIN: starting address of flash - * FLASH.LENGTH: length of flash - * RAM.ORIGIN: starting address of RAM bank 0 - * RAM.LENGTH: length of RAM bank 0 - * - * The values below can be addressed in further linker scripts - * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'. - */ - -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K /*4K*/ -} - -/* - * For external ram use something like: - - RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 8K - - */ diff --git a/bsp/nuvoton_nuc472/ldscripts/sections.ld b/bsp/nuvoton_nuc472/ldscripts/sections.ld index d7989ad7f9..9e7ed857ca 100644 --- a/bsp/nuvoton_nuc472/ldscripts/sections.ld +++ b/bsp/nuvoton_nuc472/ldscripts/sections.ld @@ -1,129 +1,32 @@ /* - * Default linker script for Cortex-M - * - * To make use of the multi-region initialisations, define - * OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.c file. + * linker script for STM32F10x with GNU ld + * bernard.xiong 2009-10-14 */ -/* - * The '__stack' definition is required by crt0, do not remove it. - */ -__stack = ORIGIN(RAM) + LENGTH(RAM); - -_estack = __stack; /* STM specific definition */ - -/* - * Default stack sizes. - * These are used by the startup in order to allocate stacks - * for the different modes. - */ - -__Main_Stack_Size = 1024 ; - -PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ; - -__Main_Stack_Limit = __stack - __Main_Stack_Size ; - -/* "PROVIDE" allows to easily override these values from an - * object file or the command line. */ -PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ; - -/* - * There will be a link error if there is not this amount of - * RAM free at the end. - */ -_Minimum_Stack_Size = 256 ; - -/* - * Default heap definitions. - * The heap start immediately after the last statically allocated - * .sbss/.noinit section, and extends up to the main stack limit. - */ -PROVIDE ( _Heap_Begin = _end_noinit ) ; -PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ; - -/* - * The entry point is informative, for debuggers and simulators, - * since the Cortex-M vector points to it anyway. - */ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 128K sram */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 512KB flash */ +} ENTRY(_start) - - -/* Sections Definitions */ +_system_stack_size = 0x400; SECTIONS { - /* - * For Cortex-M devices, the beginning of the startup code is stored in - * the .isr_vector section, which goes to FLASH. - */ - .isr_vector : ALIGN(4) + .text : { - FILL(0xFF) - - __vectors_start = ABSOLUTE(.) ; - __vectors_start__ = ABSOLUTE(.) ; /* STM specific definition */ - KEEP(*(.isr_vector)) /* Interrupt vectors */ - - KEEP(*(.cfmconfig)) /* Freescale configuration words */ - - /* - * This section is here for convenience, to store the - * startup code at the beginning of the flash area, hoping that - * this will increase the readability of the listing. - */ - *(.after_vectors .after_vectors.*) /* Startup code and ISR */ - - } >FLASH - - .inits : ALIGN(4) - { - /* - * Memory regions initialisation arrays. - * - * Thee are two kinds of arrays for each RAM region, one for - * data and one for bss. Each is iterrated at startup and the - * region initialisation is performed. - * - * The data array includes: - * - from (LOADADDR()) - * - region_begin (ADDR()) - * - region_end (ADDR()+SIZEOF()) - * - * The bss array includes: - * - region_begin (ADDR()) - * - region_end (ADDR()+SIZEOF()) - * - * WARNING: It is mandatory that the regions are word aligned, - * since the initialisation code works only on words. - */ - - __data_regions_array_start = .; - - LONG(LOADADDR(.data)); - LONG(ADDR(.data)); - LONG(ADDR(.data)+SIZEOF(.data)); - - __data_regions_array_end = .; - - __bss_regions_array_start = .; - - LONG(ADDR(.bss)); - LONG(ADDR(.bss)+SIZEOF(.bss)); - - - __bss_regions_array_end = .; - - /* End of memory regions initialisation arrays. */ - - /* - * These are the old initialisation sections, intended to contain - * naked code, with the prologue/epilogue added by crti.o/crtn.o - * when linking with startup files. The standalone startup code - * currently does not run these, better use the init arrays below. - */ - KEEP(*(.init)) - KEEP(*(.fini)) + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) /* section information for finsh shell */ . = ALIGN(4); @@ -135,7 +38,7 @@ SECTIONS KEEP(*(VSymTab)) __vsymtab_end = .; . = ALIGN(4); - + /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; @@ -143,212 +46,67 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); + . = ALIGN(4); + _etext = .; + } > CODE = 0 - /* - * The preinit code, i.e. an array of pointers to initialisation - * functions to be performed before constructors. - */ - PROVIDE_HIDDEN (__preinit_array_start = .); - - /* - * Used to run the SystemInit() before anything else. - */ - KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*)) - - /* - * Used for other platform inits. - */ - KEEP(*(.preinit_array_platform .preinit_array_platform.*)) - - /* - * The application inits. If you need to enforce some order in - * execution, create new sections, as before. - */ - KEEP(*(.preinit_array .preinit_array.*)) - - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - - /* - * The init code, i.e. an array of pointers to static constructors. - */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - - /* - * The fini code, i.e. an array of pointers to static destructors. - */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - } >FLASH - - /* - * For some STRx devices, the beginning of the startup code - * is stored in the .flashtext section, which goes to FLASH. - */ - .flashtext : ALIGN(4) + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : { - *(.flashtext .flashtext.*) /* Startup code */ - } >FLASH - - - /* - * The program code is stored in the .text section, - * which goes to FLASH. - */ - .text : ALIGN(4) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) { - *(.text .text.*) /* all remaining code */ - - /* read-only data (constants) */ - *(.rodata .rodata.* .constdata .constdata.*) + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; - *(vtable) /* C++ virtual tables */ + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) - KEEP(*(.eh_frame*)) + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA - /* - * Stub sections generated by the linker, to glue together - * ARM and Thumb code. .glue_7 is used for ARM code calling - * Thumb code, and .glue_7t is used for Thumb code calling - * ARM code. Apparently always generated by the linker, for some - * architectures, so better leave them here. - */ - *(.glue_7) - *(.glue_7t) - - KEEP (*(.init)) - KEEP (*(.fini)) - - } >FLASH - - /* ARM magic sections */ - .ARM.extab : ALIGN(4) - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - . = ALIGN(4); - __exidx_start = .; - .ARM.exidx : ALIGN(4) - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - . = ALIGN(4); - _etext = .; - __etext = .; - - /* MEMORY_ARRAY */ - /* - .ROarraySection : + .stack : { - *(.ROarraySection .ROarraySection.*) - } >MEMORY_ARRAY - */ - - /* - * This address is used by the startup code to - * initialise the .data section. - */ - _sidata = LOADADDR(.data); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA - /* - * The initialised data section. - * - * The program executes knowing that the data is in the RAM - * but the loader puts the initial values in the FLASH (inidata). - * It is one task of the startup to copy the initial values from - * FLASH to RAM. - */ - .data : ALIGN(4) + __bss_start = .; + .bss : { - FILL(0xFF) - /* This is used by the startup code to initialise the .data section */ - _sdata = . ; /* STM specific definition */ - __data_start__ = . ; - *(.data_begin .data_begin.*) + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; - *(.data .data.*) - - *(.data_end .data_end.*) - . = ALIGN(4); - - /* This is used by the startup code to initialise the .data section */ - _edata = . ; /* STM specific definition */ - __data_end__ = . ; - - } >RAM AT>FLASH - - /* - * The uninitialised data sections. NOLOAD is used to avoid - * the "section `.bss' type changed to PROGBITS" warning - */ - - /* The primary uninitialised data section. */ - .bss (NOLOAD) : ALIGN(4) - { - __bss_start__ = .; /* standard newlib definition */ - _sbss = .; /* STM specific definition */ - *(.bss_begin .bss_begin.*) - - *(.bss .bss.*) + *(.bss) + *(.bss.*) *(COMMON) - - *(.bss_end .bss_end.*) - . = ALIGN(4); - __bss_end__ = .; /* standard newlib definition */ - _ebss = . ; /* STM specific definition */ - } >RAM - - .noinit (NOLOAD) : ALIGN(4) - { - _noinit = .; - - *(.noinit .noinit.*) - - . = ALIGN(4) ; - _end_noinit = .; - } > RAM - - /* Mandatory to be word aligned, _sbrk assumes this */ - PROVIDE ( end = _end_noinit ); /* was _ebss */ - PROVIDE ( _end = _end_noinit ); - PROVIDE ( __end = _end_noinit ); - PROVIDE ( __end__ = _end_noinit ); - - /* - * Used for validation only, do not allocate anything here! - * - * This is just to check that there is enough RAM left for the Main - * stack. It should generate an error if it's full. - */ - ._check_stack : ALIGN(4) - { - . = . + _Minimum_Stack_Size ; - } >RAM - /* After that there are only debugging sections. */ - - /* This can remove the debugging information from the standard libraries */ - /* - DISCARD : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - */ - + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } @@ -357,11 +115,9 @@ SECTIONS .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } - /* - * DWARF debug sections. + /* DWARF debug sections. * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. - */ + * of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } @@ -383,5 +139,5 @@ SECTIONS .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } + .debug_varnames 0 : { *(.debug_varnames) } } diff --git a/bsp/nuvoton_nuc472/project.uvproj b/bsp/nuvoton_nuc472/project.uvproj new file mode 100644 index 0000000000..0888eb8df9 --- /dev/null +++ b/bsp/nuvoton_nuc472/project.uvproj @@ -0,0 +1,1153 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread-nuc472 + 0x4 + ARM-ADS + + + NUC472HI8AE + Nuvoton + IRAM(0x20000000-0x2000FFFF) IROM(0-0x7FFFF) CLOCK(84000000) CPUTYPE("Cortex-M4") FPU2 + + undefined + + 0 + + + + + + + + + + + SFD\Nuvoton\NUC400_v1.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + applications;.;drivers;Libraries\CMSIS\Include;Libraries\Device\Nuvoton\NUC472_442\Include;Libraries\StdDriver\inc;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + application.c + 1 + applications\application.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + + + nuc472_eth.c + 1 + drivers\nuc472_eth.c + + + + + usart.c + 1 + drivers\usart.c + + + + + CMSIS + + + system_NUC472_442.c + 1 + Libraries\Device\Nuvoton\NUC472_442\Source\system_NUC472_442.c + + + + + startup_NUC472_442.s + 2 + Libraries\Device\Nuvoton\NUC472_442\Source\ARM\startup_NUC472_442.s + + + + + NUC472_StdPeriph + + + acmp.c + 1 + Libraries\StdDriver\src\acmp.c + + + + + adc.c + 1 + Libraries\StdDriver\src\adc.c + + + + + can.c + 1 + Libraries\StdDriver\src\can.c + + + + + cap.c + 1 + Libraries\StdDriver\src\cap.c + + + + + clk.c + 1 + Libraries\StdDriver\src\clk.c + + + + + crc.c + 1 + Libraries\StdDriver\src\crc.c + + + + + crypto.c + 1 + Libraries\StdDriver\src\crypto.c + + + + + eadc.c + 1 + Libraries\StdDriver\src\eadc.c + + + + + ebi.c + 1 + Libraries\StdDriver\src\ebi.c + + + + + emac.c + 1 + Libraries\StdDriver\src\emac.c + + + + + epwm.c + 1 + Libraries\StdDriver\src\epwm.c + + + + + fmc.c + 1 + Libraries\StdDriver\src\fmc.c + + + + + gpio.c + 1 + Libraries\StdDriver\src\gpio.c + + + + + i2c.c + 1 + Libraries\StdDriver\src\i2c.c + + + + + i2s.c + 1 + Libraries\StdDriver\src\i2s.c + + + + + pdma.c + 1 + Libraries\StdDriver\src\pdma.c + + + + + ps2.c + 1 + Libraries\StdDriver\src\ps2.c + + + + + pwm.c + 1 + Libraries\StdDriver\src\pwm.c + + + + + rtc.c + 1 + Libraries\StdDriver\src\rtc.c + + + + + sc.c + 1 + Libraries\StdDriver\src\sc.c + + + + + scuart.c + 1 + Libraries\StdDriver\src\scuart.c + + + + + sd.c + 1 + Libraries\StdDriver\src\sd.c + + + + + spi.c + 1 + Libraries\StdDriver\src\spi.c + + + + + sys_.c + 1 + Libraries\StdDriver\src\sys_.c + + + + + timer_.c + 1 + Libraries\StdDriver\src\timer_.c + + + + + uart.c + 1 + Libraries\StdDriver\src\uart.c + + + + + usbd.c + 1 + Libraries\StdDriver\src\usbd.c + + + + + wdt.c + 1 + Libraries\StdDriver\src\wdt.c + + + + + wwdt.c + 1 + Libraries\StdDriver\src\wwdt.c + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\src\signal.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + lwIP + + + sys_arch.c + 1 + ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c + + + + + api_lib.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\api_lib.c + + + + + api_msg.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\api_msg.c + + + + + err.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\err.c + + + + + netbuf.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\netbuf.c + + + + + netdb.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\netdb.c + + + + + netifapi.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\netifapi.c + + + + + sockets.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\sockets.c + + + + + tcpip.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\tcpip.c + + + + + def.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\def.c + + + + + dns.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\dns.c + + + + + inet_chksum.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c + + + + + init.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\init.c + + + + + ip.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ip.c + + + + + memp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\memp.c + + + + + netif.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\netif.c + + + + + pbuf.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\pbuf.c + + + + + raw.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\raw.c + + + + + stats.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\stats.c + + + + + sys.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\sys.c + + + + + tcp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\tcp.c + + + + + tcp_in.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c + + + + + tcp_out.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c + + + + + timeouts.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + + + + udp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\udp.c + + + + + ethernet.c + 1 + ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + + + + ethernetif.c + 1 + ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + + + + lowpan6.c + 1 + ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + + + + autoip.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + + + + dhcp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + + + + etharp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + + + + icmp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + + + + igmp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + + + + ip4.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + + + + ip4_addr.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + + + + ip4_frag.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + + + + + + + diff --git a/bsp/nuvoton_nuc472/template.uvproj b/bsp/nuvoton_nuc472/template.uvproj new file mode 100644 index 0000000000..61af4cfa37 --- /dev/null +++ b/bsp/nuvoton_nuc472/template.uvproj @@ -0,0 +1,407 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-nuc472 + 0x4 + ARM-ADS + + + NUC472HI8AE + Nuvoton + IRAM(0x20000000-0x2000FFFF) IROM(0-0x7FFFF) CLOCK(84000000) CPUTYPE("Cortex-M4") FPU2 + + undefined + + 0 + + + + + + + + + + + SFD\Nuvoton\NUC400_v1.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + + From f596c5ad88bd6cd968433c7273c2621e77439b0f Mon Sep 17 00:00:00 2001 From: SummerGift <459994202@qq.com> Date: Wed, 28 Mar 2018 15:15:09 +0800 Subject: [PATCH 06/67] [bsp] Add pin equipment for stm32f429-apollo --- bsp/stm32f429-apollo/drivers/SConscript | 2 +- bsp/stm32f429-apollo/drivers/board.h | 2 + bsp/stm32f429-apollo/drivers/drv_gpio.c | 1882 +++++++++++++++++++++++ bsp/stm32f429-apollo/drivers/drv_gpio.h | 30 + 4 files changed, 1915 insertions(+), 1 deletion(-) create mode 100644 bsp/stm32f429-apollo/drivers/drv_gpio.c create mode 100644 bsp/stm32f429-apollo/drivers/drv_gpio.h diff --git a/bsp/stm32f429-apollo/drivers/SConscript b/bsp/stm32f429-apollo/drivers/SConscript index f41b8a0957..3c05f05d71 100644 --- a/bsp/stm32f429-apollo/drivers/SConscript +++ b/bsp/stm32f429-apollo/drivers/SConscript @@ -29,7 +29,7 @@ if GetDepend(['RT_USING_I2C']) or GetDepend('RT_USING_LWIP'): # add gpio drivers. if GetDepend('RT_USING_PIN'): - src += ['gpio.c'] + src += ['drv_gpio.c'] # add spi drivers. if GetDepend('RT_USING_SPI'): diff --git a/bsp/stm32f429-apollo/drivers/board.h b/bsp/stm32f429-apollo/drivers/board.h index 5090d04f1f..b6dd87b44f 100644 --- a/bsp/stm32f429-apollo/drivers/board.h +++ b/bsp/stm32f429-apollo/drivers/board.h @@ -77,6 +77,8 @@ void rt_hw_board_init(void); #define FINSH_DEVICE_NAME CONSOLE_DEVICE +#define STM32F4xx_PIN_NUMBERS 176 + void Error_Handler(void); #endif diff --git a/bsp/stm32f429-apollo/drivers/drv_gpio.c b/bsp/stm32f429-apollo/drivers/drv_gpio.c new file mode 100644 index 0000000000..a5158eeade --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/drv_gpio.c @@ -0,0 +1,1882 @@ +/* + * File : drv_gpio.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2017-10-20 ZYH the first version + */ + +#include +#include +#include + +#ifdef RT_USING_PIN + +#define __STM32_PIN(index, gpio, gpio_index) {index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __STM32_PIN_DEFAULT {-1, 0, 0, 0} + +static void GPIOA_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOA_CLK_ENABLE + __HAL_RCC_GPIOA_CLK_ENABLE(); +#endif +} +static void GPIOB_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOB_CLK_ENABLE + __HAL_RCC_GPIOB_CLK_ENABLE(); +#endif +} +static void GPIOC_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOC_CLK_ENABLE + __HAL_RCC_GPIOC_CLK_ENABLE(); +#endif +} +#if (STM32F4xx_PIN_NUMBERS > 48) + + static void GPIOD_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOD_CLK_ENABLE + __HAL_RCC_GPIOD_CLK_ENABLE(); + #endif + } + #if (STM32F4xx_PIN_NUMBERS > 64) + static void GPIOE_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOE_CLK_ENABLE + __HAL_RCC_GPIOE_CLK_ENABLE(); + #endif + } + #if (STM32F4xx_PIN_NUMBERS > 100) + static void GPIOF_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOF_CLK_ENABLE + __HAL_RCC_GPIOF_CLK_ENABLE(); + #endif + } + static void GPIOG_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOG_CLK_ENABLE + __HAL_RCC_GPIOG_CLK_ENABLE(); + #endif + } + #if (STM32F4xx_PIN_NUMBERS > 144) + static void GPIOH_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOH_CLK_ENABLE + __HAL_RCC_GPIOH_CLK_ENABLE(); + #endif + } + static void GPIOI_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOI_CLK_ENABLE + __HAL_RCC_GPIOI_CLK_ENABLE(); + #endif + } + #if (STM32F4xx_PIN_NUMBERS > 176) + static void GPIOJ_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOJ_CLK_ENABLE + __HAL_RCC_GPIOJ_CLK_ENABLE(); + #endif + } + static void GPIOK_CLK_ENABLE(void) + { + #ifdef __HAL_RCC_GPIOK_CLK_ENABLE + __HAL_RCC_GPIOK_CLK_ENABLE(); + #endif + } + #endif + #endif + #endif + #endif +#endif +/* STM32 GPIO driver */ +struct pin_index +{ + int index; + void (*rcc)(void); + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ +#if (STM32F4xx_PIN_NUMBERS == 36) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, A, 15), + __STM32_PIN(3, B, 5), + __STM32_PIN(4, B, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(8, A, 14), + __STM32_PIN(9, B, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(13, C, 14), + __STM32_PIN(13, A, 13), + __STM32_PIN(14, B, 3), + __STM32_PIN(15, B, 7), + __STM32_PIN(16, C, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN(18, C, 15), + __STM32_PIN(19, A, 8), + __STM32_PIN(20, A, 12), + __STM32_PIN(21, B, 4), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(25, B, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN(27, B, 10), + __STM32_PIN(28, A, 2), + __STM32_PIN(29, A, 0), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(33, B, 2), + __STM32_PIN(34, B, 5), + __STM32_PIN(35, A, 3), + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 48) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, C, 13), + __STM32_PIN(3, C, 14), + __STM32_PIN(4, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(10, A, 0), + __STM32_PIN(11, A, 1), + __STM32_PIN(12, A, 2), + __STM32_PIN(13, A, 3), + __STM32_PIN(14, A, 4), + __STM32_PIN(15, A, 5), + __STM32_PIN(16, A, 6), + __STM32_PIN(17, A, 7), + __STM32_PIN(18, B, 0), + __STM32_PIN(19, B, 1), + __STM32_PIN(20, B, 2), + __STM32_PIN(21, B, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(25, B, 12), + __STM32_PIN(26, B, 13), + __STM32_PIN(27, B, 14), + __STM32_PIN(28, B, 15), + __STM32_PIN(29, A, 8), + __STM32_PIN(30, A, 9), + __STM32_PIN(31, A, 10), + __STM32_PIN(32, A, 11), + __STM32_PIN(33, A, 12), + __STM32_PIN(34, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(37, A, 14), + __STM32_PIN(38, A, 15), + __STM32_PIN(39, B, 3), + __STM32_PIN(40, B, 4), + __STM32_PIN(41, B, 5), + __STM32_PIN(42, B, 6), + __STM32_PIN(43, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(45, B, 8), + __STM32_PIN(46, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 64) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, C, 13), + __STM32_PIN(3, C, 14), + __STM32_PIN(4, C, 15), + __STM32_PIN(5, D, 0), + __STM32_PIN(6, D, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(8, C, 0), + __STM32_PIN(9, C, 1), + __STM32_PIN(10, C, 2), + __STM32_PIN(11, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(14, A, 0), + __STM32_PIN(15, A, 1), + __STM32_PIN(16, A, 2), + __STM32_PIN(17, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(20, A, 4), + __STM32_PIN(21, A, 5), + __STM32_PIN(22, A, 6), + __STM32_PIN(23, A, 7), + __STM32_PIN(24, C, 4), + __STM32_PIN(25, C, 5), + __STM32_PIN(26, B, 0), + __STM32_PIN(27, B, 1), + __STM32_PIN(28, B, 2), + __STM32_PIN(29, B, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(33, B, 12), + __STM32_PIN(34, B, 13), + __STM32_PIN(35, B, 14), + __STM32_PIN(36, B, 15), + __STM32_PIN(37, C, 6), + __STM32_PIN(38, C, 7), + __STM32_PIN(39, C, 8), + __STM32_PIN(40, C, 9), + __STM32_PIN(41, A, 8), + __STM32_PIN(42, A, 9), + __STM32_PIN(43, A, 10), + __STM32_PIN(44, A, 11), + __STM32_PIN(45, A, 12), + __STM32_PIN(46, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(49, A, 14), + __STM32_PIN(50, A, 15), + __STM32_PIN(51, C, 10), + __STM32_PIN(52, C, 11), + __STM32_PIN(53, C, 12), + __STM32_PIN(54, D, 2), + __STM32_PIN(55, B, 3), + __STM32_PIN(56, B, 4), + __STM32_PIN(57, B, 5), + __STM32_PIN(58, B, 6), + __STM32_PIN(59, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(61, B, 8), + __STM32_PIN(62, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 81) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, C, 10), + __STM32_PIN(3, A, 15), + __STM32_PIN(4, D, 0), + __STM32_PIN(5, B, 3), + __STM32_PIN(6, B, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(11, A, 14), + __STM32_PIN(12, A, 12), + __STM32_PIN(13, C, 12), + __STM32_PIN(14, B, 4), + __STM32_PIN(15, B, 6), + __STM32_PIN(16, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(20, A, 13), + __STM32_PIN(21, A, 11), + __STM32_PIN(22, C, 11), + __STM32_PIN(23, D, 2), + __STM32_PIN(24, B, 8), + __STM32_PIN(25, C, 1), + __STM32_PIN(26, C, 13), + __STM32_PIN(27, C, 14), + __STM32_PIN(28, A, 10), + __STM32_PIN(29, A, 9), + __STM32_PIN(30, A, 8), + __STM32_PIN(31, C, 7), + __STM32_PIN(32, C, 6), + __STM32_PIN(33, B, 9), + __STM32_PIN(34, C, 2), + __STM32_PIN_DEFAULT, + __STM32_PIN(36, C, 15), + __STM32_PIN(37, C, 8), + __STM32_PIN(38, C, 9), + __STM32_PIN(39, B, 14), + __STM32_PIN(40, B, 0), + __STM32_PIN(41, A, 4), + __STM32_PIN(42, A, 3), + __STM32_PIN(43, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(47, D, 9), + __STM32_PIN(48, B, 12), + __STM32_PIN(49, E, 13), + __STM32_PIN(50, A, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, C, 0), + __STM32_PIN_DEFAULT, + __STM32_PIN(55, D, 10), + __STM32_PIN(56, B, 13), + __STM32_PIN(57, E, 14), + __STM32_PIN(58, E, 10), + __STM32_PIN(59, B, 1), + __STM32_PIN(59, A, 5), + __STM32_PIN(61, A, 0), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(64, B, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN(66, B, 10), + __STM32_PIN(67, E, 11), + __STM32_PIN(68, B, 2), + __STM32_PIN(69, C, 4), + __STM32_PIN_DEFAULT, + __STM32_PIN(71, A, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(75, E, 15), + __STM32_PIN(76, E, 12), + __STM32_PIN(77, E, 9), + __STM32_PIN(78, C, 5), + __STM32_PIN(80, A, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(81, A, 2), +#endif +#if (STM32F4xx_PIN_NUMBERS == 100 && !defined(STM32F469xx) && !defined(STM32F479xx)) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, C, 13), + __STM32_PIN(8, C, 14), + __STM32_PIN(9, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(15, C, 0), + __STM32_PIN(16, C, 1), + __STM32_PIN(17, C, 2), + __STM32_PIN(18, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(23, A, 0), + __STM32_PIN(24, A, 1), + __STM32_PIN(25, A, 2), + __STM32_PIN(26, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(29, A, 4), + __STM32_PIN(30, A, 5), + __STM32_PIN(31, A, 6), + __STM32_PIN(32, A, 7), + __STM32_PIN(33, C, 4), + __STM32_PIN(34, C, 5), + __STM32_PIN(35, B, 0), + __STM32_PIN(36, B, 1), + __STM32_PIN(37, B, 2), + __STM32_PIN(38, E, 7), + __STM32_PIN(39, E, 8), + __STM32_PIN(40, E, 9), + __STM32_PIN(41, E, 10), + __STM32_PIN(42, E, 11), + __STM32_PIN(43, E, 12), + __STM32_PIN(44, E, 13), + __STM32_PIN(45, E, 14), + __STM32_PIN(46, E, 15), + __STM32_PIN(47, B, 10), + #if defined(STM32F405xx)||defined(STM32F415xx)||defined(STM32F407xx)||defined(STM32F417xx)||defined(STM32F427xx)||defined(STM32F437xx)||defined(STM32F429xx) + __STM32_PIN(48, B, 11), + #else + __STM32_PIN_DEFAULT, + #endif + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(51, B, 12), + __STM32_PIN(52, B, 13), + __STM32_PIN(53, B, 14), + __STM32_PIN(54, B, 15), + __STM32_PIN(55, D, 8), + __STM32_PIN(56, D, 9), + __STM32_PIN(57, D, 10), + __STM32_PIN(58, D, 11), + __STM32_PIN(59, D, 12), + __STM32_PIN(60, D, 13), + __STM32_PIN(61, D, 14), + __STM32_PIN(62, D, 15), + __STM32_PIN(63, C, 6), + __STM32_PIN(64, C, 7), + __STM32_PIN(65, C, 8), + __STM32_PIN(66, C, 9), + __STM32_PIN(67, A, 8), + __STM32_PIN(68, A, 9), + __STM32_PIN(69, A, 10), + __STM32_PIN(70, A, 11), + __STM32_PIN(71, A, 12), + __STM32_PIN(72, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(76, A, 14), + __STM32_PIN(77, A, 15), + __STM32_PIN(78, C, 10), + __STM32_PIN(79, C, 11), + __STM32_PIN(80, C, 12), + __STM32_PIN(81, D, 0), + __STM32_PIN(82, D, 1), + __STM32_PIN(83, D, 2), + __STM32_PIN(84, D, 3), + __STM32_PIN(85, D, 4), + __STM32_PIN(86, D, 5), + __STM32_PIN(87, D, 6), + __STM32_PIN(88, D, 7), + __STM32_PIN(89, B, 3), + __STM32_PIN(90, B, 4), + __STM32_PIN(91, B, 5), + __STM32_PIN(92, B, 6), + __STM32_PIN(93, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(95, B, 8), + __STM32_PIN(96, B, 9), + __STM32_PIN(97, E, 0), + __STM32_PIN(98, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 100 && (defined(STM32F469xx) || defined(STM32F479xx))) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(4, C, 13), + __STM32_PIN(5, C, 14), + __STM32_PIN(6, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(12, C, 0), + __STM32_PIN(13, C, 1), + __STM32_PIN(14, C, 2), + __STM32_PIN(15, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(19, A, 0), + __STM32_PIN(20, A, 1), + __STM32_PIN(21, A, 2), + __STM32_PIN(22, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(25, A, 4), + __STM32_PIN(26, A, 5), + __STM32_PIN(27, A, 6), + __STM32_PIN(28, A, 7), + __STM32_PIN(29, B, 0), + __STM32_PIN(30, B, 1), + __STM32_PIN(31, B, 2), + __STM32_PIN(32, E, 7), + __STM32_PIN(33, E, 8), + __STM32_PIN(34, E, 9), + __STM32_PIN(35, E, 10), + __STM32_PIN(36, E, 11), + __STM32_PIN(37, E, 12), + __STM32_PIN(38, E, 13), + __STM32_PIN(39, E, 14), + __STM32_PIN(40, E, 15), + __STM32_PIN(41, B, 10), + __STM32_PIN(42, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(46, B, 12), + __STM32_PIN(47, B, 13), + __STM32_PIN(48, B, 14), + __STM32_PIN(49, B, 15), + __STM32_PIN(50, D, 8), + __STM32_PIN(51, D, 9), + __STM32_PIN(52, D, 10), + __STM32_PIN(53, D, 14), + __STM32_PIN(54, D, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(66, C, 6), + __STM32_PIN(67, C, 7), + __STM32_PIN(68, C, 8), + __STM32_PIN(69, C, 9), + __STM32_PIN(70, A, 8), + __STM32_PIN(71, A, 9), + __STM32_PIN(72, A, 10), + __STM32_PIN(73, A, 11), + __STM32_PIN(74, A, 12), + __STM32_PIN(75, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(79, A, 14), + __STM32_PIN(80, A, 15), + __STM32_PIN(81, C, 10), + __STM32_PIN(82, C, 11), + __STM32_PIN(83, C, 12), + __STM32_PIN(84, D, 0), + __STM32_PIN(85, D, 1), + __STM32_PIN(86, D, 2), + __STM32_PIN(87, D, 3), + __STM32_PIN(88, D, 4), + __STM32_PIN(89, D, 5), + __STM32_PIN(90, D, 6), + __STM32_PIN(91, D, 7), + __STM32_PIN(92, B, 3), + __STM32_PIN(93, B, 4), + __STM32_PIN(94, B, 5), + __STM32_PIN(95, B, 6), + __STM32_PIN(96, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(98, B, 8), + __STM32_PIN(99, B, 9), + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 144) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, C, 13), + __STM32_PIN(8, C, 14), + __STM32_PIN(9, C, 15), + __STM32_PIN(10, F, 0), + __STM32_PIN(11, F, 1), + __STM32_PIN(12, F, 2), + __STM32_PIN(13, F, 3), + __STM32_PIN(14, F, 4), + __STM32_PIN(15, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(18, F, 6), + __STM32_PIN(19, F, 7), + __STM32_PIN(20, F, 8), + __STM32_PIN(21, F, 9), + __STM32_PIN(22, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(26, C, 0), + __STM32_PIN(27, C, 1), + __STM32_PIN(28, C, 2), + __STM32_PIN(29, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(34, A, 0), + __STM32_PIN(35, A, 1), + __STM32_PIN(36, A, 2), + __STM32_PIN(37, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(40, A, 4), + __STM32_PIN(41, A, 5), + __STM32_PIN(42, A, 6), + __STM32_PIN(43, A, 7), + __STM32_PIN(44, C, 4), + __STM32_PIN(45, C, 5), + __STM32_PIN(46, B, 0), + __STM32_PIN(47, B, 1), + __STM32_PIN(48, B, 2), + __STM32_PIN(49, F, 11), + __STM32_PIN(50, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, F, 13), + __STM32_PIN(54, F, 14), + __STM32_PIN(55, F, 15), + __STM32_PIN(56, G, 0), + __STM32_PIN(57, G, 1), + __STM32_PIN(58, E, 7), + __STM32_PIN(59, E, 8), + __STM32_PIN(60, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(63, E, 10), + __STM32_PIN(64, E, 11), + __STM32_PIN(65, E, 12), + __STM32_PIN(66, E, 13), + __STM32_PIN(67, E, 14), + __STM32_PIN(68, E, 15), + __STM32_PIN(69, B, 10), + __STM32_PIN(70, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(73, B, 12), + __STM32_PIN(74, B, 13), + __STM32_PIN(75, B, 14), + __STM32_PIN(76, B, 15), + __STM32_PIN(77, D, 8), + __STM32_PIN(78, D, 9), + __STM32_PIN(79, D, 10), + __STM32_PIN(80, D, 11), + __STM32_PIN(81, D, 12), + __STM32_PIN(82, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(85, D, 14), + __STM32_PIN(86, D, 15), + __STM32_PIN(87, G, 2), + __STM32_PIN(88, G, 3), + __STM32_PIN(89, G, 4), + __STM32_PIN(90, G, 5), + __STM32_PIN(91, G, 6), + __STM32_PIN(92, G, 7), + __STM32_PIN(93, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(96, C, 6), + __STM32_PIN(97, C, 7), + __STM32_PIN(98, C, 8), + __STM32_PIN(99, C, 9), + __STM32_PIN(100, A, 8), + __STM32_PIN(101, A, 9), + __STM32_PIN(102, A, 10), + __STM32_PIN(103, A, 11), + __STM32_PIN(104, A, 12), + __STM32_PIN(105, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(109, A, 14), + __STM32_PIN(110, A, 15), + __STM32_PIN(111, C, 10), + __STM32_PIN(112, C, 11), + __STM32_PIN(113, C, 12), + __STM32_PIN(114, D, 0), + __STM32_PIN(115, D, 1), + __STM32_PIN(116, D, 2), + __STM32_PIN(117, D, 3), + __STM32_PIN(118, D, 4), + __STM32_PIN(119, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(122, D, 6), + __STM32_PIN(123, D, 7), + __STM32_PIN(124, G, 9), + __STM32_PIN(125, G, 10), + __STM32_PIN(126, G, 11), + __STM32_PIN(127, G, 12), + __STM32_PIN(128, G, 13), + __STM32_PIN(129, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(132, G, 15), + __STM32_PIN(133, B, 3), + __STM32_PIN(134, B, 4), + __STM32_PIN(135, B, 5), + __STM32_PIN(136, B, 6), + __STM32_PIN(137, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(139, B, 8), + __STM32_PIN(140, B, 9), + __STM32_PIN(141, E, 0), + __STM32_PIN(142, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 169) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, I, 6), + __STM32_PIN(3, I, 5), + __STM32_PIN(4, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(6, B, 4), + __STM32_PIN(7, G, 12), + __STM32_PIN(8, D, 7), + __STM32_PIN(9, D, 3), + __STM32_PIN(10, C, 12), + __STM32_PIN(11, A, 14), + __STM32_PIN(12, I, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN(14, I, 7), + __STM32_PIN(15, E, 2), + __STM32_PIN(16, I, 4), + __STM32_PIN(17, E, 0), + __STM32_PIN(18, B, 7), + __STM32_PIN(19, B, 3), + __STM32_PIN(20, G, 11), + __STM32_PIN(21, D, 6), + __STM32_PIN(22, D, 2), + __STM32_PIN(23, C, 11), + __STM32_PIN(24, A, 15), + __STM32_PIN(25, I, 2), + __STM32_PIN(26, I, 0), + __STM32_PIN(27, E, 3), + __STM32_PIN(28, E, 4), + __STM32_PIN_DEFAULT, + __STM32_PIN(30, B, 9), + __STM32_PIN(31, B, 6), + __STM32_PIN(32, G, 15), + __STM32_PIN(33, G, 10), + __STM32_PIN(34, D, 5), + __STM32_PIN(35, D, 1), + __STM32_PIN(36, C, 10), + __STM32_PIN(37, I, 1), + __STM32_PIN(38, H, 15), + __STM32_PIN(39, H, 14), + __STM32_PIN(40, E, 5), + __STM32_PIN(41, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(43, B, 8), + __STM32_PIN(44, B, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(47, D, 4), + __STM32_PIN(48, D, 0), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(52, H, 13), + __STM32_PIN(53, C, 14), + __STM32_PIN(54, I, 9), + __STM32_PIN(55, I, 10), + __STM32_PIN(56, C, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(60, A, 9), + __STM32_PIN(61, A, 10), + __STM32_PIN(62, A, 11), + __STM32_PIN(63, A, 12), + __STM32_PIN(64, A, 13), + __STM32_PIN(65, A, 8), + __STM32_PIN(66, C, 15), + __STM32_PIN(67, F, 0), + __STM32_PIN(68, F, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(74, C, 6), + __STM32_PIN(75, C, 7), + __STM32_PIN(76, C, 8), + __STM32_PIN(77, C, 9), + __STM32_PIN(78, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(81, F, 4), + __STM32_PIN(82, F, 3), + __STM32_PIN(83, F, 2), + __STM32_PIN(84, C, 0), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(89, G, 6), + __STM32_PIN(90, G, 7), + __STM32_PIN(91, G, 5), + __STM32_PIN(92, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN(94, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN(96, C, 1), + __STM32_PIN(97, C, 2), + __STM32_PIN(98, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN(100, E, 13), + __STM32_PIN(101, D, 11), + __STM32_PIN(102, D, 14), + __STM32_PIN(103, G, 4), + __STM32_PIN(104, G, 2), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(109, A, 0), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(112, E, 8), + __STM32_PIN(113, E, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(116, D, 15), + __STM32_PIN(117, D, 12), + __STM32_PIN(118, A, 1), + __STM32_PIN(119, A, 2), + __STM32_PIN(120, A, 3), + __STM32_PIN(121, A, 7), + __STM32_PIN(122, B, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(124, F, 14), + __STM32_PIN(125, E, 9), + __STM32_PIN(126, E, 15), + __STM32_PIN(127, H, 9), + __STM32_PIN(128, D, 10), + __STM32_PIN(129, D, 13), + __STM32_PIN(130, D, 9), + __STM32_PIN(131, H, 3), + __STM32_PIN(132, H, 2), + __STM32_PIN(133, H, 5), + __STM32_PIN(134, C, 4), + __STM32_PIN(135, B, 2), + __STM32_PIN_DEFAULT, + __STM32_PIN(137, F, 15), + __STM32_PIN(138, E, 10), + __STM32_PIN(139, B, 10), + __STM32_PIN(140, H, 8), + __STM32_PIN(141, H, 12), + __STM32_PIN(142, D, 8), + __STM32_PIN(143, B, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN(145, H, 4), + __STM32_PIN(146, A, 5), + __STM32_PIN(147, C, 5), + __STM32_PIN(148, F, 11), + __STM32_PIN(149, F, 13), + __STM32_PIN(150, G, 1), + __STM32_PIN(151, E, 11), + __STM32_PIN(152, B, 11), + __STM32_PIN(153, H, 7), + __STM32_PIN(154, H, 11), + __STM32_PIN(155, B, 13), + __STM32_PIN(156, B, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN(158, A, 4), + __STM32_PIN(159, A, 6), + __STM32_PIN(160, B, 0), + __STM32_PIN(161, F, 12), + __STM32_PIN(162, G, 0), + __STM32_PIN(163, E, 7), + __STM32_PIN(164, E, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN(166, E, 12), + __STM32_PIN(167, H, 10), + __STM32_PIN(168, B, 12), + __STM32_PIN_DEFAULT, +#endif +#if (STM32F4xx_PIN_NUMBERS == 176) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, I, 8), + __STM32_PIN(8, C, 13), + __STM32_PIN(9, C, 14), + __STM32_PIN(10, C, 15), + __STM32_PIN(11, I, 9), + __STM32_PIN(12, I, 10), + __STM32_PIN(13, I, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(16, F, 0), + __STM32_PIN(17, F, 1), + __STM32_PIN(18, F, 2), + __STM32_PIN(19, F, 3), + __STM32_PIN(20, F, 4), + __STM32_PIN(21, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(24, F, 6), + __STM32_PIN(25, F, 7), + __STM32_PIN(26, F, 8), + __STM32_PIN(27, F, 9), + __STM32_PIN(28, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(32, C, 0), + __STM32_PIN(33, C, 1), + __STM32_PIN(34, C, 2), + __STM32_PIN(35, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(40, A, 0), + __STM32_PIN(41, A, 1), + __STM32_PIN(42, A, 2), + __STM32_PIN(43, H, 2), + __STM32_PIN(44, H, 3), + __STM32_PIN(45, H, 4), + __STM32_PIN(46, H, 5), + __STM32_PIN(47, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(50, A, 4), + __STM32_PIN(51, A, 5), + __STM32_PIN(52, A, 6), + __STM32_PIN(53, A, 7), + __STM32_PIN(54, C, 4), + __STM32_PIN(55, C, 5), + __STM32_PIN(56, B, 0), + __STM32_PIN(57, B, 1), + __STM32_PIN(58, B, 2), + __STM32_PIN(59, F, 11), + __STM32_PIN(60, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(63, F, 13), + __STM32_PIN(64, F, 14), + __STM32_PIN(65, F, 15), + __STM32_PIN(66, G, 0), + __STM32_PIN(67, G, 1), + __STM32_PIN(68, E, 7), + __STM32_PIN(69, E, 8), + __STM32_PIN(70, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(73, E, 10), + __STM32_PIN(74, E, 11), + __STM32_PIN(75, E, 12), + __STM32_PIN(76, E, 13), + __STM32_PIN(77, E, 14), + __STM32_PIN(78, E, 15), + __STM32_PIN(79, B, 10), + __STM32_PIN(80, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(83, H, 6), + __STM32_PIN(84, H, 7), + __STM32_PIN(85, H, 8), + __STM32_PIN(86, H, 9), + __STM32_PIN(87, H, 10), + __STM32_PIN(88, H, 11), + __STM32_PIN(89, H, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(92, B, 12), + __STM32_PIN(93, B, 13), + __STM32_PIN(94, B, 14), + __STM32_PIN(95, B, 15), + __STM32_PIN(96, D, 8), + __STM32_PIN(97, D, 9), + __STM32_PIN(98, D, 10), + __STM32_PIN(99, D, 11), + __STM32_PIN(100, D, 12), + __STM32_PIN(101, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(104, D, 14), + __STM32_PIN(105, D, 15), + __STM32_PIN(106, G, 2), + __STM32_PIN(107, G, 3), + __STM32_PIN(108, G, 4), + __STM32_PIN(109, G, 5), + __STM32_PIN(110, G, 6), + __STM32_PIN(111, G, 7), + __STM32_PIN(112, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(115, C, 6), + __STM32_PIN(116, C, 7), + __STM32_PIN(117, C, 8), + __STM32_PIN(118, C, 9), + __STM32_PIN(119, A, 8), + __STM32_PIN(120, A, 9), + __STM32_PIN(121, A, 10), + __STM32_PIN(122, A, 11), + __STM32_PIN(123, A, 12), + __STM32_PIN(124, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(128, H, 13), + __STM32_PIN(129, H, 14), + __STM32_PIN(130, H, 15), + __STM32_PIN(131, I, 0), + __STM32_PIN(132, I, 1), + __STM32_PIN(133, I, 2), + __STM32_PIN(134, I, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(137, A, 14), + __STM32_PIN(138, A, 15), + __STM32_PIN(139, C, 10), + __STM32_PIN(140, C, 11), + __STM32_PIN(141, C, 12), + __STM32_PIN(142, D, 0), + __STM32_PIN(143, D, 1), + __STM32_PIN(144, D, 2), + __STM32_PIN(145, D, 3), + __STM32_PIN(146, D, 4), + __STM32_PIN(147, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(150, D, 6), + __STM32_PIN(151, D, 7), + __STM32_PIN(152, G, 9), + __STM32_PIN(153, G, 10), + __STM32_PIN(154, G, 11), + __STM32_PIN(155, G, 12), + __STM32_PIN(156, G, 13), + __STM32_PIN(157, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(160, G, 15), + __STM32_PIN(161, B, 3), + __STM32_PIN(162, B, 4), + __STM32_PIN(163, B, 5), + __STM32_PIN(164, B, 6), + __STM32_PIN(165, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(167, B, 8), + __STM32_PIN(168, B, 9), + __STM32_PIN(169, E, 0), + __STM32_PIN(170, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(173, I, 4), + __STM32_PIN(174, I, 5), + __STM32_PIN(175, I, 6), + __STM32_PIN(176, I, 7), +#endif +#if (STM32F4xx_PIN_NUMBERS == 208) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, I, 8), + __STM32_PIN(8, C, 13), + __STM32_PIN(9, C, 14), + __STM32_PIN(10, C, 15), + __STM32_PIN(11, I, 9), + __STM32_PIN(12, I, 10), + __STM32_PIN(13, I, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(16, F, 0), + __STM32_PIN(17, F, 1), + __STM32_PIN(18, F, 2), + __STM32_PIN(19, I, 12), + __STM32_PIN(20, I, 13), + __STM32_PIN(21, I, 14), + __STM32_PIN(22, F, 3), + __STM32_PIN(23, F, 4), + __STM32_PIN(24, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(27, F, 6), + __STM32_PIN(28, F, 7), + __STM32_PIN(29, F, 8), + __STM32_PIN(30, F, 9), + __STM32_PIN(31, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(35, C, 0), + __STM32_PIN(36, C, 1), + __STM32_PIN(37, C, 2), + __STM32_PIN(38, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(43, A, 0), + __STM32_PIN(44, A, 1), + __STM32_PIN(45, A, 2), + __STM32_PIN(46, H, 2), + __STM32_PIN(47, H, 3), + __STM32_PIN(48, H, 4), + __STM32_PIN(49, H, 5), + __STM32_PIN(50, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, A, 4), + __STM32_PIN(54, A, 5), + __STM32_PIN(55, A, 6), + __STM32_PIN(56, A, 7), + __STM32_PIN(57, C, 4), + __STM32_PIN(58, C, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(61, B, 0), + __STM32_PIN(62, B, 1), + __STM32_PIN(63, B, 2), + __STM32_PIN(64, I, 15), + __STM32_PIN(65, J, 0), + __STM32_PIN(66, J, 1), + __STM32_PIN(67, J, 2), + __STM32_PIN(68, J, 3), + __STM32_PIN(69, J, 4), + __STM32_PIN(70, F, 11), + __STM32_PIN(71, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(74, F, 13), + __STM32_PIN(75, F, 14), + __STM32_PIN(76, F, 15), + __STM32_PIN(77, G, 0), + __STM32_PIN(78, G, 1), + __STM32_PIN(79, E, 7), + __STM32_PIN(80, E, 8), + __STM32_PIN(81, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(84, E, 10), + __STM32_PIN(85, E, 11), + __STM32_PIN(86, E, 12), + __STM32_PIN(87, E, 13), + __STM32_PIN(88, E, 14), + __STM32_PIN(89, E, 15), + __STM32_PIN(90, B, 10), + __STM32_PIN(91, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(95, J, 5), + __STM32_PIN(96, H, 6), + __STM32_PIN(97, H, 7), + __STM32_PIN(98, H, 8), + __STM32_PIN(99, H, 9), + __STM32_PIN(100, H, 10), + __STM32_PIN(101, H, 11), + __STM32_PIN(102, H, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN(104, B, 12), + __STM32_PIN(105, B, 13), + __STM32_PIN(106, B, 14), + __STM32_PIN(107, B, 15), + __STM32_PIN(108, D, 8), + __STM32_PIN(109, D, 9), + __STM32_PIN(110, D, 10), + __STM32_PIN(111, D, 11), + __STM32_PIN(112, D, 12), + __STM32_PIN(113, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(104, D, 14), + __STM32_PIN(105, D, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(129, G, 2), + __STM32_PIN(130, G, 3), + __STM32_PIN(131, G, 4), + __STM32_PIN(132, G, 5), + __STM32_PIN(133, G, 6), + __STM32_PIN(134, G, 7), + __STM32_PIN(135, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(138, C, 6), + __STM32_PIN(139, C, 7), + __STM32_PIN(140, C, 8), + __STM32_PIN(141, C, 9), + __STM32_PIN(142, A, 8), + __STM32_PIN(143, A, 9), + __STM32_PIN(144, A, 10), + __STM32_PIN(145, A, 11), + __STM32_PIN(146, A, 12), + __STM32_PIN(147, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(151, H, 13), + __STM32_PIN(152, H, 14), + __STM32_PIN(153, H, 15), + __STM32_PIN(154, I, 0), + __STM32_PIN(155, I, 1), + __STM32_PIN(156, I, 2), + __STM32_PIN(157, I, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN(159, A, 14), + __STM32_PIN(160, A, 15), + __STM32_PIN(161, C, 10), + __STM32_PIN(162, C, 11), + __STM32_PIN(163, C, 12), + __STM32_PIN(164, D, 0), + __STM32_PIN(165, D, 1), + __STM32_PIN(166, D, 2), + __STM32_PIN(167, D, 3), + __STM32_PIN(168, D, 4), + __STM32_PIN(169, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(172, D, 6), + __STM32_PIN(173, D, 7), + __STM32_PIN(174, J, 12), + __STM32_PIN(175, J, 13), + __STM32_PIN(176, J, 14), + __STM32_PIN(177, J, 15), + __STM32_PIN(178, G, 9), + __STM32_PIN(179, G, 10), + __STM32_PIN(180, G, 11), + __STM32_PIN(181, G, 12), + __STM32_PIN(182, G, 13), + __STM32_PIN(183, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(186, K, 3), + __STM32_PIN(187, K, 4), + __STM32_PIN(188, K, 5), + __STM32_PIN(189, K, 6), + __STM32_PIN(190, K, 7), + __STM32_PIN(191, G, 15), + __STM32_PIN(192, B, 3), + __STM32_PIN(193, B, 4), + __STM32_PIN(194, B, 5), + __STM32_PIN(195, B, 6), + __STM32_PIN(196, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(198, B, 8), + __STM32_PIN(199, B, 9), + __STM32_PIN(200, E, 0), + __STM32_PIN(201, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(205, I, 4), + __STM32_PIN(206, I, 5), + __STM32_PIN(207, I, 6), + __STM32_PIN(208, I, 7), +#endif +#if (STM32F4xx_PIN_NUMBERS == 216) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(9, I, 8), + __STM32_PIN(10, C, 13), + __STM32_PIN(11, C, 14), + __STM32_PIN(12, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN(14, I, 9), + __STM32_PIN(15, I, 10), + __STM32_PIN(16, I, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(19, F, 0), + __STM32_PIN(20, F, 1), + __STM32_PIN(21, F, 2), + __STM32_PIN(22, I, 12), + __STM32_PIN(23, I, 13), + __STM32_PIN(24, I, 14), + __STM32_PIN(25, F, 3), + __STM32_PIN(26, F, 4), + __STM32_PIN(27, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(30, F, 6), + __STM32_PIN(31, F, 7), + __STM32_PIN(32, F, 8), + __STM32_PIN(33, F, 9), + __STM32_PIN(34, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(38, C, 0), + __STM32_PIN(39, C, 1), + __STM32_PIN(40, C, 2), + __STM32_PIN(41, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(48, A, 0), + __STM32_PIN(49, A, 1), + __STM32_PIN(50, A, 2), + __STM32_PIN(51, H, 2), + __STM32_PIN(52, H, 3), + __STM32_PIN(53, H, 4), + __STM32_PIN(54, H, 5), + __STM32_PIN(55, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(59, A, 4), + __STM32_PIN(60, A, 5), + __STM32_PIN(61, A, 6), + __STM32_PIN(62, A, 7), + __STM32_PIN(63, C, 4), + __STM32_PIN(64, C, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(67, B, 0), + __STM32_PIN(68, B, 1), + __STM32_PIN(69, B, 2), + __STM32_PIN(70, I, 15), + __STM32_PIN(71, J, 0), + __STM32_PIN(72, J, 1), + __STM32_PIN(73, J, 2), + __STM32_PIN(74, J, 3), + __STM32_PIN(75, J, 4), + __STM32_PIN(76, F, 11), + __STM32_PIN(77, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(80, F, 13), + __STM32_PIN(81, F, 14), + __STM32_PIN(82, F, 15), + __STM32_PIN(83, G, 0), + __STM32_PIN(84, G, 1), + __STM32_PIN(85, E, 7), + __STM32_PIN(86, E, 8), + __STM32_PIN(87, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(90, E, 10), + __STM32_PIN(91, E, 11), + __STM32_PIN(92, E, 12), + __STM32_PIN(93, E, 13), + __STM32_PIN(94, E, 14), + __STM32_PIN(95, E, 15), + __STM32_PIN(96, B, 10), + __STM32_PIN(97, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(101, J, 5), + __STM32_PIN(102, H, 6), + __STM32_PIN(103, H, 7), + __STM32_PIN(104, H, 8), + __STM32_PIN(105, H, 9), + __STM32_PIN(106, H, 10), + __STM32_PIN(107, H, 11), + __STM32_PIN(108, H, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(111, B, 12), + __STM32_PIN(112, B, 13), + __STM32_PIN(113, B, 14), + __STM32_PIN(114, B, 15), + __STM32_PIN(115, D, 8), + __STM32_PIN(116, D, 9), + __STM32_PIN(117, D, 10), + __STM32_PIN(118, D, 11), + __STM32_PIN(119, D, 12), + __STM32_PIN(120, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(123, D, 14), + __STM32_PIN(124, D, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(136, G, 2), + __STM32_PIN(137, G, 3), + __STM32_PIN(138, G, 4), + __STM32_PIN(139, G, 5), + __STM32_PIN(140, G, 6), + __STM32_PIN(141, G, 7), + __STM32_PIN(142, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(145, C, 6), + __STM32_PIN(146, C, 7), + __STM32_PIN(147, C, 8), + __STM32_PIN(148, C, 9), + __STM32_PIN(149, A, 8), + __STM32_PIN(150, A, 9), + __STM32_PIN(151, A, 10), + __STM32_PIN(152, A, 11), + __STM32_PIN(153, A, 12), + __STM32_PIN(154, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(158, H, 13), + __STM32_PIN(159, H, 14), + __STM32_PIN(160, H, 15), + __STM32_PIN(161, I, 0), + __STM32_PIN(162, I, 1), + __STM32_PIN(163, I, 2), + __STM32_PIN(164, I, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(167, A, 14), + __STM32_PIN(168, A, 15), + __STM32_PIN(169, C, 10), + __STM32_PIN(170, C, 11), + __STM32_PIN(171, C, 12), + __STM32_PIN(172, D, 0), + __STM32_PIN(173, D, 1), + __STM32_PIN(174, D, 2), + __STM32_PIN(175, D, 3), + __STM32_PIN(176, D, 4), + __STM32_PIN(177, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(180, D, 6), + __STM32_PIN(181, D, 7), + __STM32_PIN(182, J, 12), + __STM32_PIN(183, J, 13), + __STM32_PIN(184, J, 14), + __STM32_PIN(185, J, 15), + __STM32_PIN(186, G, 9), + __STM32_PIN(187, G, 10), + __STM32_PIN(188, G, 11), + __STM32_PIN(189, G, 12), + __STM32_PIN(190, G, 13), + __STM32_PIN(191, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(194, K, 3), + __STM32_PIN(195, K, 4), + __STM32_PIN(196, K, 5), + __STM32_PIN(197, K, 6), + __STM32_PIN(198, K, 7), + __STM32_PIN(199, G, 15), + __STM32_PIN(200, B, 3), + __STM32_PIN(201, B, 4), + __STM32_PIN(202, B, 5), + __STM32_PIN(203, B, 6), + __STM32_PIN(204, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(206, B, 8), + __STM32_PIN(207, B, 9), + __STM32_PIN(208, E, 0), + __STM32_PIN(209, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(213, I, 4), + __STM32_PIN(214, I, 5), + __STM32_PIN(215, I, 6), + __STM32_PIN(216, I, 7), +#endif +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +}; +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value); +} + +int stm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = HAL_GPIO_ReadPin(index->gpio, index->pin); + + return value; +} + +void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + index->rcc(); + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); +} +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; +rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ + index->rcc(); + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; + break; + } + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); + HAL_NVIC_SetPriority(irqmap->irqno, 5, 0); + HAL_NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _stm32_pin_ops = + { + stm32_pin_mode, + stm32_pin_write, + stm32_pin_read, + stm32_pin_attach_irq, + stm32_pin_dettach_irq, + stm32_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0); + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2); + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4); + rt_interrupt_leave(); +} +void EXTI9_5_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); + rt_interrupt_leave(); +} +void EXTI15_10_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/stm32f429-apollo/drivers/drv_gpio.h b/bsp/stm32f429-apollo/drivers/drv_gpio.h new file mode 100644 index 0000000000..f263a87c2d --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/drv_gpio.h @@ -0,0 +1,30 @@ +/* + * File : drv_gpio.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2015-01-05 Bernard the first version + */ +#ifndef GPIO_H__ +#define GPIO_H__ + + +struct stm32_hw_pin_userdata +{ + int pin; + uint32_t mode; +}; + +#define PIN_USERDATA_END {-1,0} + +extern struct stm32_hw_pin_userdata stm32_pins[]; + +int rt_hw_pin_init(void); + +#endif From 852714c1c2d724ea15f4f2f421ed4a54dbdf3891 Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Wed, 28 Mar 2018 19:50:06 +0800 Subject: [PATCH 07/67] [bps][imxrt1052] fixed gcc output bin file error --- bsp/imxrt1052-evk/rtconfig.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bsp/imxrt1052-evk/rtconfig.py b/bsp/imxrt1052-evk/rtconfig.py index 8df0ecb78a..ac2a0df885 100644 --- a/bsp/imxrt1052-evk/rtconfig.py +++ b/bsp/imxrt1052-evk/rtconfig.py @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -std=c99 -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_PRESENT -eentry' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld' CPATH = '' LPATH = '' @@ -55,7 +55,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2 -Os' - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' # module setting CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' @@ -77,7 +77,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = DEVICE + ' --apcs=interwork' AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf' CFLAGS += ' --diag_suppress=66,1296,186' CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' From 739bc6a259818f761ea7c2f59616352465a42235 Mon Sep 17 00:00:00 2001 From: SummerGift <459994202@qq.com> Date: Thu, 29 Mar 2018 10:16:21 +0800 Subject: [PATCH 08/67] [bsp][imxrt1052-evk]: fix parameter type incompatible error --- bsp/imxrt1052-evk/drivers/drv_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/imxrt1052-evk/drivers/drv_i2c.c b/bsp/imxrt1052-evk/drivers/drv_i2c.c index 38a3c45482..4d23ea36cc 100644 --- a/bsp/imxrt1052-evk/drivers/drv_i2c.c +++ b/bsp/imxrt1052-evk/drivers/drv_i2c.c @@ -234,7 +234,7 @@ static void _search_i2c_device(rt_device_t dev, uint8_t cmd) msgs[0].addr = i; msgs[1].addr = i; - len = rt_i2c_transfer(dev, msgs, 2); + len = rt_i2c_transfer((struct rt_i2c_bus_device *)dev, msgs, 2); if (len == 2) { count++; From db081c517f9dce3781b8bf27ef68971251416da2 Mon Sep 17 00:00:00 2001 From: ZYH Date: Thu, 29 Mar 2018 11:44:20 +0800 Subject: [PATCH 09/67] [Bsp][STM32f4xx-HAL]fix pin index --- bsp/stm32f4xx-HAL/drivers/drv_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/stm32f4xx-HAL/drivers/drv_gpio.c b/bsp/stm32f4xx-HAL/drivers/drv_gpio.c index a5158eeade..ea3382ea09 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_gpio.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_gpio.c @@ -122,7 +122,7 @@ static const struct pin_index pins[] = __STM32_PIN(9, B, 6), __STM32_PIN_DEFAULT, __STM32_PIN_DEFAULT, - __STM32_PIN(13, C, 14), + __STM32_PIN(12, C, 14), __STM32_PIN(13, A, 13), __STM32_PIN(14, B, 3), __STM32_PIN(15, B, 7), From 144bfdbd18d913c02ca68fb591b45e27ff630f63 Mon Sep 17 00:00:00 2001 From: balanceTWK Date: Thu, 29 Mar 2018 18:19:40 +0800 Subject: [PATCH 10/67] [BSP][i.mxrt1052] fix uart --- bsp/imxrt1052-evk/drivers/board.c | 59 ++++++++++++++-------------- bsp/imxrt1052-evk/drivers/drv_uart.c | 42 +++++++------------- bsp/imxrt1052-evk/drivers/drv_uart.h | 5 +-- 3 files changed, 46 insertions(+), 60 deletions(-) diff --git a/bsp/imxrt1052-evk/drivers/board.c b/bsp/imxrt1052-evk/drivers/board.c index df518fbf0f..ecb30dd9be 100644 --- a/bsp/imxrt1052-evk/drivers/board.c +++ b/bsp/imxrt1052-evk/drivers/board.c @@ -48,40 +48,39 @@ static void BOARD_BootClockRUN(void) /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ CLOCK_SetXtalFreq(24000000U); CLOCK_SetRtcXtalFreq(32768U); - + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - + CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - + CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ #ifndef SKIP_SYSCLK_INIT CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */ #endif -#ifndef SKIP_USB_PLL_INIT +#ifndef SKIP_USB_PLL_INIT CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ -#endif +#endif CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ - - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ - + CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ + + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ + /* Disable unused clock */ - BOARD_BootClockGate(); - - /* Power down all unused PLL */ + BOARD_BootClockGate(); + + /* Power down all unused PLL */ CLOCK_DeinitAudioPll(); CLOCK_DeinitVideoPll(); CLOCK_DeinitEnetPll(); CLOCK_DeinitUsb2Pll(); - /* Configure UART divider to default */ - CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ - + /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + CLOCK_EnableClock(kCLOCK_Iomuxc); + /* Update core clock */ SystemCoreClockUpdate(); } @@ -164,7 +163,7 @@ void rt_lowlevel_init(void) { BOARD_ConfigMPU(); -#if defined(RT_USING_SDRAM) +#if defined(RT_USING_SDRAM) extern int imxrt_sdram_init(void); imxrt_sdram_init(); #endif @@ -178,28 +177,28 @@ void rt_hw_board_init() BOARD_BootClockRUN(); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - + #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - + #ifdef RT_USING_HEAP #if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); - rt_system_heap_init((void *)SDRAM_BEGIN, (void*)SDRAM_END); - - rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); - rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); + rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END); + + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); #else - rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); - rt_system_heap_init((void *)HEAP_BEGIN, (void*)HEAP_END); + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif - + #endif } diff --git a/bsp/imxrt1052-evk/drivers/drv_uart.c b/bsp/imxrt1052-evk/drivers/drv_uart.c index e4a303ef22..346dd66328 100644 --- a/bsp/imxrt1052-evk/drivers/drv_uart.c +++ b/bsp/imxrt1052-evk/drivers/drv_uart.c @@ -21,7 +21,6 @@ #ifdef RT_USING_SERIAL -/* GPIOʱӻLPUART_InitԶ, º򲻻Զ */ #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif @@ -41,10 +40,10 @@ /* imxrt uart driver */ struct imxrt_uart { - LPUART_Type * uart_base; + LPUART_Type *uart_base; IRQn_Type irqn; - struct rt_serial_device * serial; + struct rt_serial_device *serial; char *device_name; }; @@ -129,7 +128,8 @@ void LPUART8_IRQHandler(void) #endif /* RT_USING_UART8 */ -static const struct imxrt_uart uarts[] = { +static const struct imxrt_uart uarts[] = +{ #ifdef RT_USING_UART1 { LPUART1, @@ -198,7 +198,7 @@ static const struct imxrt_uart uarts[] = { }; /* Get debug console frequency. */ -uint32_t BOARD_DebugConsoleSrcFreq(void) +uint32_t GetUartSrcFreq(void) { uint32_t freq; @@ -231,7 +231,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) if (uart->uart_base != RT_NULL) { #ifdef RT_USING_UART1 - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ @@ -261,7 +260,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) Hyst. Enable Field: Hysteresis Disabled */ #endif #ifdef RT_USING_UART2 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B1_02_LPUART2_TX, @@ -272,15 +270,12 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0x10B0u); - - IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0x10B0u); #endif #ifdef RT_USING_UART3 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B1_06_LPUART3_TX, @@ -291,13 +286,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0x10B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0x10B0u); #endif #ifdef RT_USING_UART4 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_B1_00_LPUART4_TX, @@ -308,13 +301,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_B1_00_LPUART4_TX, 0x10B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_B1_01_LPUART4_RX, 0x10B0u); #endif #ifdef RT_USING_UART5 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_B1_12_LPUART5_TX, @@ -325,13 +316,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_B1_12_LPUART5_TX, 0x10B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_B1_13_LPUART5_RX, 0x10B0u); #endif #ifdef RT_USING_UART6 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_02_LPUART6_TX, @@ -342,13 +331,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B0_02_LPUART6_TX, 0x10B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B0_03_LPUART6_RX, 0x10B0u); #endif #ifdef RT_USING_UART7 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_EMC_31_LPUART7_TX, @@ -359,13 +346,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_EMC_31_LPUART7_TX, 0x10B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_EMC_32_LPUART7_RX, 0x10B0u); #endif #ifdef RT_USING_UART8 - CLOCK_EnableClock(kCLOCK_Iomuxc); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B1_10_LPUART8_TX, @@ -376,7 +361,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart) IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_10_LPUART8_TX, 0x10B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_11_LPUART8_RX, 0x10B0u); @@ -440,8 +424,7 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c config.enableTx = true; config.enableRx = true; - LPUART_Init(uart->uart_base, &config, BOARD_DebugConsoleSrcFreq()); - + LPUART_Init(uart->uart_base, &config, GetUartSrcFreq()); return RT_EOK; } @@ -481,7 +464,7 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch) uart = (struct imxrt_uart *)serial->parent.user_data; LPUART_WriteByte(uart->uart_base, ch); - while(!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)); + while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)); return 1; } @@ -546,16 +529,21 @@ static const struct rt_uart_ops imxrt_uart_ops = imxrt_getc, }; -int imxrt_hw_usart_init(void) +int imxrt_hw_uart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; int i; + + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { uarts[i].serial->ops = &imxrt_uart_ops; uarts[i].serial->config = config; - /* register UART1 device */ + /* register UART device */ rt_hw_serial_register(uarts[i].serial, uarts[i].device_name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -564,6 +552,6 @@ int imxrt_hw_usart_init(void) return 0; } -INIT_BOARD_EXPORT(imxrt_hw_usart_init); +INIT_BOARD_EXPORT(imxrt_hw_uart_init); #endif /*RT_USING_SERIAL */ diff --git a/bsp/imxrt1052-evk/drivers/drv_uart.h b/bsp/imxrt1052-evk/drivers/drv_uart.h index f5d3842b46..ca9fb423a1 100644 --- a/bsp/imxrt1052-evk/drivers/drv_uart.h +++ b/bsp/imxrt1052-evk/drivers/drv_uart.h @@ -12,12 +12,11 @@ * 2017-10-10 Tanek the first version */ -#ifndef __DRV_USART_H__ -#define __DRV_USART_H__ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ #include #include -int rt_hw_usart_init(void); #endif From 9826f07dfa66c96a76945c26bbb1c798f98f4016 Mon Sep 17 00:00:00 2001 From: liu2guang <1004383796@qq.com> Date: Fri, 30 Mar 2018 12:20:42 +0800 Subject: [PATCH 11/67] =?UTF-8?q?[BSP]=20add=20spi=20bus=20driver.=20|=20?= =?UTF-8?q?=E6=B7=BB=E5=8A=A0spi=E6=80=BB=E7=BA=BF=E9=A9=B1=E5=8A=A8.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/imxrt1052-evk/Kconfig | 50 +++- bsp/imxrt1052-evk/drivers/SConscript | 5 + bsp/imxrt1052-evk/drivers/drv_spi_bus.c | 336 ++++++++++++++++++++++++ bsp/imxrt1052-evk/drivers/drv_spi_bus.h | 24 ++ 4 files changed, 409 insertions(+), 6 deletions(-) create mode 100644 bsp/imxrt1052-evk/drivers/drv_spi_bus.c create mode 100644 bsp/imxrt1052-evk/drivers/drv_spi_bus.h diff --git a/bsp/imxrt1052-evk/Kconfig b/bsp/imxrt1052-evk/Kconfig index 372696b8f4..d55ce6e145 100644 --- a/bsp/imxrt1052-evk/Kconfig +++ b/bsp/imxrt1052-evk/Kconfig @@ -36,7 +36,7 @@ endchoice if BOARD_RT1050_EVK menu "RT1050_EVK Bsp Config" -menu "Select uart device" +menu "Select uart drivers" config RT_USING_UART1 bool "Using uart1" select RT_USING_SERIAL @@ -71,13 +71,32 @@ menu "Select uart device" default n endmenu -#menu "SDRAM drive support" +menu "Select spibus drivers" + config RT_USING_SPIBUS1 + bool "Using spi1 bus" + select RT_USING_SPI + default n + config RT_USING_SPIBUS2 + bool "Using spi2 bus" + select RT_USING_SPI + default n + config RT_USING_SPIBUS3 + bool "Using spi3 bus" + select RT_USING_SPI + default n + config RT_USING_SPIBUS4 + bool "Using spi4 bus" + select RT_USING_SPI + default y +endmenu + +#menu "SDRAM driver support" config RT_USING_SDRAM bool "Using sdram" default y #endmenu -#menu "RTC drive support" +#menu "RTC driver support" config RT_USING_RTC_HP bool "Using hp rtc" select RT_USING_RTC @@ -102,7 +121,7 @@ endif if BOARD_RT1050_FIRE menu "RT1050_FIRE Bsp Config" -menu "Select uart device" +menu "Select uart drivers" config RT_USING_UART1 bool "Using uart1" select RT_USING_SERIAL @@ -137,13 +156,32 @@ menu "Select uart device" default n endmenu -#menu "SDRAM drive support" +menu "Select spibus drivers" + config RT_USING_SPIBUS1 + bool "Using spi1 bus" + select RT_USING_SPI + default n + config RT_USING_SPIBUS2 + bool "Using spi2 bus" + select RT_USING_SPI + default n + config RT_USING_SPIBUS3 + bool "Using spi3 bus" + select RT_USING_SPI + default n + config RT_USING_SPIBUS4 + bool "Using spi4 bus" + select RT_USING_SPI + default y +endmenu + +#menu "SDRAM driver support" config RT_USING_SDRAM bool "Using sdram" default y #endmenu -#menu "RTC drive support" +#menu "RTC driver support" config RT_USING_RTC_HP bool "Using hp rtc" select RT_USING_RTC diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript index 4c5a6e8ef3..7133fea6fb 100644 --- a/bsp/imxrt1052-evk/drivers/SConscript +++ b/bsp/imxrt1052-evk/drivers/SConscript @@ -17,6 +17,7 @@ CPPDEFINES = [] if GetDepend('RT_USING_SDRAM'): src = src + ['./drv_sdram.c'] +# add pin driver code if GetDepend('RT_USING_PIN'): src += ['drv_pin.c'] @@ -24,6 +25,10 @@ if GetDepend('RT_USING_PIN'): if GetDepend('RT_USING_RTC_HP'): src = src + ['./drv_rtc.c'] +# add spibus driver code +if GetDepend('RT_USING_SPI'): + src += ['drv_spi_bus.c'] + if GetDepend('BOARD_RT1050_EVK'): src += ['hyper_flash_boot.c'] diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_bus.c b/bsp/imxrt1052-evk/drivers/drv_spi_bus.c new file mode 100644 index 0000000000..558d30c849 --- /dev/null +++ b/bsp/imxrt1052-evk/drivers/drv_spi_bus.c @@ -0,0 +1,336 @@ +/* + * File : drv_spi_bus.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2018-03-27 Liuguang the first version. + */ + +#include "drv_spi_bus.h" + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_lpspi.h" + +#ifdef RT_USING_SPI + +#define LPSPI_CLK_SOURCE (1U) +#define LPSPI_CLK_SOURCE_DIVIDER (7U) + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +struct rt1050_spi +{ + LPSPI_Type *base; + struct rt_spi_configuration *cfg; +}; + +struct rt1050_hw_spi_cs +{ + rt_uint32_t pin; +}; + +static uint32_t rt1050_get_lpspi_freq(void) +{ + uint32_t freq = 0; + + /* CLOCK_GetMux(kCLOCK_LpspiMux): + 00b: derive clock from PLL3 PFD1 720M + 01b: derive clock from PLL3 PFD0 720M + 10b: derive clock from PLL2 528M + 11b: derive clock from PLL2 PFD2 396M + */ + switch(CLOCK_GetMux(kCLOCK_LpspiMux)) + { + case 0: + freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); + break; + + case 1: + freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); + break; + + case 2: + freq = CLOCK_GetFreq(kCLOCK_SysPllClk); + break; + + case 3: + freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk); + break; + } + + freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); + + return freq; +} + +static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *cfg) +{ + lpspi_master_config_t masterConfig; + + if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) + { + return RT_EINVAL; + } + +#if defined(RT_USING_SPIBUS1) + if(base == LPSPI1) + { + IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_27_LPSPI1_SCK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_27_LPSPI1_SCK, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_28_LPSPI1_SDO, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_28_LPSPI1_SDO, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_29_LPSPI1_SDI, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_29_LPSPI1_SDI, 0x10B0u); + } +#endif + +#if defined(RT_USING_SPIBUS2) + if(base == LPSPI2) + { + IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI, 0x10B0u); + + /* Optional IO config */ + //IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_00_LPSPI2_SCK, 0U); + //IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_00_LPSPI2_SCK, 0x10B0u); + //IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_02_LPSPI2_SDO, 0U); + //IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_02_LPSPI2_SDO, 0x10B0u); + //IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_03_LPSPI2_SDI, 0U); + //IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_03_LPSPI2_SDI, 0x10B0u); + } +#endif + +#if defined(RT_USING_SPIBUS3) + if(base == LPSPI3) + { + IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0x10B0u); + } +#endif + +#if defined(RT_USING_SPIBUS4) + if(base == LPSPI4) + { + IOMUXC_SetPinMux (IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0x10B0u); + IOMUXC_SetPinMux (IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0x10B0u); + + /* Optional IO config */ + //IOMUXC_SetPinMux (IOMUXC_GPIO_B1_07_LPSPI4_SCK, 0U); + //IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_LPSPI4_SCK, 0x10B0u); + //IOMUXC_SetPinMux (IOMUXC_GPIO_B1_06_LPSPI4_SDO, 0U); + //IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_LPSPI4_SDO, 0x10B0u); + //IOMUXC_SetPinMux (IOMUXC_GPIO_B1_05_LPSPI4_SDI, 0U); + //IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_LPSPI4_SDI, 0x10B0u); + } +#endif + + LPSPI_MasterGetDefaultConfig(&masterConfig); + + masterConfig.baudRate = cfg->max_hz; + masterConfig.bitsPerFrame = cfg->data_width; + + if(cfg->mode & RT_SPI_MSB) + { + masterConfig.direction = kLPSPI_MsbFirst; + } + else + { + masterConfig.direction = kLPSPI_LsbFirst; + } + + if(cfg->mode & RT_SPI_CPHA) + { + masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + } + else + { + masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + } + + if(cfg->mode & RT_SPI_CPOL) + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; + } + else + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + } + + masterConfig.pinCfg = kLPSPI_SdiInSdoOut; + masterConfig.dataOutConfig = kLpspiDataOutTristate; + masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; + + LPSPI_MasterInit(base, &masterConfig, rt1050_get_lpspi_freq()); + base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; + + return RT_EOK; +} + +rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct rt1050_hw_spi_cs *cs_pin = (struct rt1050_hw_spi_cs *)rt_malloc(sizeof(struct rt1050_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + rt_err_t ret; + struct rt1050_spi *spi = RT_NULL; + + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + + spi = (struct rt1050_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = rt1050_spi_init(spi->base, cfg); + + return ret; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + lpspi_transfer_t transfer; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data); + struct rt1050_hw_spi_cs *cs = device->parent.user_data; + + if(message->cs_take) + { + rt_pin_write(cs->pin, PIN_LOW); + } + + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); + transfer.dataSize = message->length; + status_t stat = LPSPI_MasterTransferBlocking(spi->base, &transfer); + + if(message->cs_release) + { + rt_pin_write(cs->pin, PIN_HIGH); + } + + return message->length; +} + +#if defined(RT_USING_SPIBUS1) +static struct rt1050_spi spi1 = +{ + .base = LPSPI1 +}; +static struct rt_spi_bus spi1_bus = +{ + .parent.user_data = &spi1 +}; +#endif + +#if defined(RT_USING_SPIBUS2) +static struct rt1050_spi spi2 = +{ + .base = LPSPI2 +}; +static struct rt_spi_bus spi2_bus = +{ + .parent.user_data = &spi2 +}; +#endif + +#if defined(RT_USING_SPIBUS3) +static struct rt1050_spi spi3 = +{ + .base = LPSPI3 +}; +static struct rt_spi_bus spi3_bus = +{ + .parent.user_data = &spi3 +}; +#endif + +#if defined(RT_USING_SPIBUS4) +static struct rt1050_spi spi4 = +{ + .base = LPSPI4 +}; +static struct rt_spi_bus spi4_bus = +{ + .parent.user_data = &spi4 +}; +#endif + +static struct rt_spi_ops rt1050_spi_ops = +{ + .configure = spi_configure, + .xfer = spixfer +}; + +int rt_hw_spi_bus_init(void) +{ +#if defined(RT_USING_SPIBUS1) || defined(RT_USING_SPIBUS2) || \ + defined(RT_USING_SPIBUS3) || defined(RT_USING_SPIBUS4) + + CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI_CLK_SOURCE); + CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLK_SOURCE_DIVIDER); + + CLOCK_EnableClock(kCLOCK_Iomuxc); +#endif + +#if defined(RT_USING_SPIBUS1) + rt_spi_bus_register(&spi1_bus, "spibus1", &rt1050_spi_ops); +#endif + +#if defined(RT_USING_SPIBUS2) + rt_spi_bus_register(&spi2_bus, "spibus2", &rt1050_spi_ops); +#endif + +#if defined(RT_USING_SPIBUS3) + rt_spi_bus_register(&spi3_bus, "spibus3", &rt1050_spi_ops); +#endif + +#if defined(RT_USING_SPIBUS4) + rt_spi_bus_register(&spi4_bus, "spibus4", &rt1050_spi_ops); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_spi_bus_init); + +#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_bus.h b/bsp/imxrt1052-evk/drivers/drv_spi_bus.h new file mode 100644 index 0000000000..b5016a4ebf --- /dev/null +++ b/bsp/imxrt1052-evk/drivers/drv_spi_bus.h @@ -0,0 +1,24 @@ +/* + * File : drv_spi_bus.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2018-03-27 Liuguang the first version. + */ + +#ifndef __DRV_SPI_BUS_H__ +#define __DRV_SPI_BUS_H__ + +#include +#include + +int rt_hw_spi_bus_init(void); +rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); + +#endif From 0bbb349145acbead50d7e8581db31dd88dde5b96 Mon Sep 17 00:00:00 2001 From: liu2guang <1004383796@qq.com> Date: Sat, 31 Mar 2018 20:25:13 +0800 Subject: [PATCH 12/67] =?UTF-8?q?[BSP][RT1050]=20Optimized=20spi=20bus=20d?= =?UTF-8?q?river.=20|=20=E4=BC=98=E5=8C=96spi=E9=A9=B1=E5=8A=A8.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. menuconfig中导出spi总线IO选择配置. 2. menuconfig中导出spi总线时钟源配置. 3. 限制spibus总线速度最大为40MHz. --- bsp/imxrt1052-evk/.config | 33 +++- bsp/imxrt1052-evk/Kconfig | 215 +++++++++++++++--------- bsp/imxrt1052-evk/drivers/drv_spi_bus.c | 205 ++++++++++++++++------ bsp/imxrt1052-evk/project.uvprojx | 87 +++++++++- bsp/imxrt1052-evk/rtconfig.h | 15 +- 5 files changed, 417 insertions(+), 138 deletions(-) diff --git a/bsp/imxrt1052-evk/.config b/bsp/imxrt1052-evk/.config index 74720d8a9a..5b047f25fb 100644 --- a/bsp/imxrt1052-evk/.config +++ b/bsp/imxrt1052-evk/.config @@ -135,7 +135,13 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RTC_SYNC_USING_NTP is not set CONFIG_RT_USING_SDIO=y -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_WIFI is not set @@ -310,6 +316,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_SAMPLES is not set # # example package: hello @@ -320,11 +327,11 @@ CONFIG_BOARD_RT1050_EVK=y # CONFIG_BOARD_RT1050_FIRE is not set # -# RT1050_EVK Bsp Config +# RT1050 Bsp Config # # -# Select uart device +# Select uart drivers # CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set @@ -334,5 +341,25 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART6 is not set # CONFIG_RT_USING_UART7 is not set # CONFIG_RT_USING_UART8 is not set + +# +# Select spi bus drivers +# +CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set +CONFIG_LPSPI_CLK_SOURCE=0 +CONFIG_LPSPI_CLK_SOURCE_DIVIDER=7 +# CONFIG_RT_USING_SPIBUS1 is not set +# CONFIG_RT_USING_SPIBUS2 is not set +# CONFIG_RT_USING_SPIBUS3 is not set +CONFIG_RT_USING_SPIBUS4=y +CONFIG_LPSPI4_SCK_GPIO_1=y +# CONFIG_LPSPI4_SCK_GPIO_2 is not set +CONFIG_LPSPI4_SDO_GPIO_1=y +# CONFIG_LPSPI4_SDO_GPIO_2 is not set +CONFIG_LPSPI4_SDI_GPIO_1=y +# CONFIG_LPSPI4_SDI_GPIO_2 is not set CONFIG_RT_USING_SDRAM=y CONFIG_RT_USING_RTC_HP=y diff --git a/bsp/imxrt1052-evk/Kconfig b/bsp/imxrt1052-evk/Kconfig index d55ce6e145..0216ef30d6 100644 --- a/bsp/imxrt1052-evk/Kconfig +++ b/bsp/imxrt1052-evk/Kconfig @@ -33,8 +33,7 @@ choice bool "RT1050_FIRE" endchoice -if BOARD_RT1050_EVK -menu "RT1050_EVK Bsp Config" +menu "RT1050 Bsp Config" menu "Select uart drivers" config RT_USING_UART1 @@ -71,23 +70,159 @@ menu "Select uart drivers" default n endmenu -menu "Select spibus drivers" +menu "Select spi bus drivers" + choice + prompt "SPI bus clock source" + default LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + + config LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + bool "PLL3PFD1" + config LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + bool "PLL3PFD0" + config LPSPI_CLK_SOURCE_FROM_PLL2 + bool "PLL2" + config LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + bool "PLL2PFD2" + endchoice + config LPSPI_CLK_SOURCE + int + default 0 if LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + default 1 if LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + default 2 if LPSPI_CLK_SOURCE_FROM_PLL2 + default 3 if LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + + config LPSPI_CLK_SOURCE_DIVIDER + int "SPI bus clock source divider" + range 0 8 + default 7 + config RT_USING_SPIBUS1 bool "Using spi1 bus" select RT_USING_SPI default n + choice + prompt "spi1 bus sck io choice" + default LPSPI1_SCK_GPIO_1 + depends on RT_USING_SPIBUS1 + config LPSPI1_SCK_GPIO_1 + bool "GPIO_EMC_27" + config LPSPI1_SCK_GPIO_2 + bool "GPIO_SD_B0_00" + endchoice + choice + prompt "spi1 bus sdo io choice" + default LPSPI1_SDO_GPIO_1 + depends on RT_USING_SPIBUS1 + config LPSPI1_SDO_GPIO_1 + bool "GPIO_EMC_28" + config LPSPI1_SDO_GPIO_2 + bool "GPIO_SD_B0_02" + endchoice + choice + prompt "spi1 bus sdi io choice" + default LPSPI1_SDI_GPIO_1 + depends on RT_USING_SPIBUS1 + config LPSPI1_SDI_GPIO_1 + bool "GPIO_EMC_29" + config LPSPI1_SDI_GPIO_2 + bool "GPIO_SD_B0_03" + endchoice + config RT_USING_SPIBUS2 bool "Using spi2 bus" select RT_USING_SPI default n + choice + prompt "spi2 bus sck io choice" + default LPSPI2_SCK_GPIO_1 + depends on RT_USING_SPIBUS2 + config LPSPI2_SCK_GPIO_1 + bool "GPIO_SD_B1_07" + config LPSPI2_SCK_GPIO_2 + bool "GPIO_EMC_00" + endchoice + choice + prompt "spi2 bus sdo io choice" + default LPSPI2_SDO_GPIO_1 + depends on RT_USING_SPIBUS2 + config LPSPI2_SDO_GPIO_1 + bool "GPIO_SD_B1_08" + config LPSPI2_SDO_GPIO_2 + bool "GPIO_EMC_02" + endchoice + choice + prompt "spi2 bus sdi io choice" + default LPSPI2_SDI_GPIO_1 + depends on RT_USING_SPIBUS2 + config LPSPI2_SDI_GPIO_1 + bool "GPIO_SD_B1_09" + config LPSPI2_SDI_GPIO_2 + bool "GPIO_EMC_03" + endchoice + config RT_USING_SPIBUS3 bool "Using spi3 bus" select RT_USING_SPI default n + choice + prompt "spi3 bus sck io choice" + default LPSPI3_SCK_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SCK_GPIO_1 + bool "GPIO_AD_B1_15" + config LPSPI3_SCK_GPIO_2 + bool "GPIO_AD_B0_00" + endchoice + choice + prompt "spi3 bus sdo io choice" + default LPSPI3_SDO_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDO_GPIO_1 + bool "GPIO_AD_B1_14" + config LPSPI3_SDO_GPIO_2 + bool "GPIO_AD_B0_01" + endchoice + choice + prompt "spi3 bus sdi io choice" + default LPSPI3_SDI_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDI_GPIO_1 + bool "GPIO_AD_B1_13" + config LPSPI3_SDI_GPIO_2 + bool "GPIO_AD_B0_02" + endchoice + config RT_USING_SPIBUS4 bool "Using spi4 bus" select RT_USING_SPI default y + choice + prompt "spi4 bus sck io choice" + default LPSPI4_SCK_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SCK_GPIO_1 + bool "GPIO_B0_03" + config LPSPI4_SCK_GPIO_2 + bool "GPIO_B1_07" + endchoice + choice + prompt "spi4 bus sdo io choice" + default LPSPI4_SDO_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDO_GPIO_1 + bool "GPIO_B0_02" + config LPSPI4_SDO_GPIO_2 + bool "GPIO_B1_06" + endchoice + choice + prompt "spi4 bus sdi io choice" + default LPSPI4_SDI_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDI_GPIO_1 + bool "GPIO_B0_01" + config LPSPI4_SDI_GPIO_2 + bool "GPIO_B1_05" + endchoice endmenu #menu "SDRAM driver support" @@ -103,6 +238,7 @@ endmenu default n #endmenu +if BOARD_RT1050_EVK if RT_USING_USB_DEVICE choice prompt "select usb device controller" @@ -114,79 +250,6 @@ if RT_USING_USB_DEVICE bool "set EHCI1 as device" endchoice endif - -endmenu endif -if BOARD_RT1050_FIRE -menu "RT1050_FIRE Bsp Config" - -menu "Select uart drivers" - config RT_USING_UART1 - bool "Using uart1" - select RT_USING_SERIAL - default y - config RT_USING_UART2 - bool "Using uart2" - select RT_USING_SERIAL - default n - config RT_USING_UART3 - bool "Using uart3" - select RT_USING_SERIAL - default n - config RT_USING_UART4 - bool "Using uart4" - select RT_USING_SERIAL - default n - config RT_USING_UART5 - bool "Using uart5" - select RT_USING_SERIAL - default n - config RT_USING_UART6 - bool "Using uart6" - select RT_USING_SERIAL - default n - config RT_USING_UART7 - bool "Using uart7" - select RT_USING_SERIAL - default n - config RT_USING_UART8 - bool "Using uart8" - select RT_USING_SERIAL - default n endmenu - -menu "Select spibus drivers" - config RT_USING_SPIBUS1 - bool "Using spi1 bus" - select RT_USING_SPI - default n - config RT_USING_SPIBUS2 - bool "Using spi2 bus" - select RT_USING_SPI - default n - config RT_USING_SPIBUS3 - bool "Using spi3 bus" - select RT_USING_SPI - default n - config RT_USING_SPIBUS4 - bool "Using spi4 bus" - select RT_USING_SPI - default y -endmenu - -#menu "SDRAM driver support" - config RT_USING_SDRAM - bool "Using sdram" - default y -#endmenu - -#menu "RTC driver support" - config RT_USING_RTC_HP - bool "Using hp rtc" - select RT_USING_RTC - default n -#endmenu - -endmenu -endif diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_bus.c b/bsp/imxrt1052-evk/drivers/drv_spi_bus.c index 558d30c849..714dba95c6 100644 --- a/bsp/imxrt1052-evk/drivers/drv_spi_bus.c +++ b/bsp/imxrt1052-evk/drivers/drv_spi_bus.c @@ -20,20 +20,124 @@ #ifdef RT_USING_SPI -#define LPSPI_CLK_SOURCE (1U) -#define LPSPI_CLK_SOURCE_DIVIDER (7U) - #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif +#if !defined(LPSPI_CLK_SOURCE) +#define LPSPI_CLK_SOURCE (1U) /* PLL3 PFD0 */ +#endif +#if !defined(LPSPI_CLK_SOURCE_DIVIDER) +#define LPSPI_CLK_SOURCE_DIVIDER (7U) /* 8div */ +#endif + +/* LPSPI1 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI1_SCK_GPIO_1) +#define LPSPI1_SCK_GPIO IOMUXC_GPIO_EMC_27_LPSPI1_SCK +#elif defined(LPSPI1_SCK_GPIO_2) +#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK +#else +#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK +#endif + +#if defined(LPSPI1_SDO_GPIO_1) +#define LPSPI1_SDO_GPIO IOMUXC_GPIO_EMC_28_LPSPI1_SDO +#elif defined(LPSPI1_SDO_GPIO_2) +#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO +#else +#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO +#endif + +#if defined(LPSPI1_SDI_GPIO_1) +#define LPSPI1_SDI_GPIO IOMUXC_GPIO_EMC_29_LPSPI1_SDI +#elif defined(LPSPI1_SDI_GPIO_2) +#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI +#else +#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI +#endif + +/* LPSPI2 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI2_SCK_GPIO_1) +#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK +#elif defined(LPSPI2_SCK_GPIO_2) +#define LPSPI2_SCK_GPIO IOMUXC_GPIO_EMC_00_LPSPI2_SCK +#else +#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK +#endif + +#if defined(LPSPI2_SDO_GPIO_1) +#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 +#elif defined(LPSPI2_SDO_GPIO_2) +#define LPSPI2_SDO_GPIO IOMUXC_GPIO_EMC_02_LPSPI2_SDO +#else +#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 +#endif + +#if defined(LPSPI2_SDI_GPIO_1) +#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI +#elif defined(LPSPI2_SDI_GPIO_2) +#define LPSPI2_SDI_GPIO IOMUXC_GPIO_EMC_03_LPSPI2_SDI +#else +#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI +#endif + +/* LPSPI3 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI3_SCK_GPIO_1) +#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK +#elif defined(LPSPI3_SCK_GPIO_2) +#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK +#else +#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK +#endif + +#if defined(LPSPI3_SDO_GPIO_1) +#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO +#elif defined(LPSPI3_SDO_GPIO_2) +#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO +#else +#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO +#endif + +#if defined(LPSPI3_SDI_GPIO_1) +#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI +#elif defined(LPSPI3_SDI_GPIO_2) +#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI +#else +#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI +#endif + +/* LPSPI4 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI4_SCK_GPIO_1) +#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK +#elif defined(LPSPI4_SCK_GPIO_2) +#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B1_07_LPSPI4_SCK +#else +#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK +#endif + +#if defined(LPSPI4_SDO_GPIO_1) +#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO +#elif defined(LPSPI4_SDO_GPIO_2) +#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B1_06_LPSPI4_SDO +#else +#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO +#endif + +#if defined(LPSPI4_SDI_GPIO_1) +#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI +#elif defined(LPSPI4_SDI_GPIO_2) +#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B1_05_LPSPI4_SDI +#else +#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI +#endif + struct rt1050_spi { LPSPI_Type *base; struct rt_spi_configuration *cfg; }; -struct rt1050_hw_spi_cs +struct rt1050_sw_spi_cs { rt_uint32_t pin; }; @@ -76,6 +180,8 @@ static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *c { lpspi_master_config_t masterConfig; + RT_ASSERT(cfg != RT_NULL); + if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) { return RT_EINVAL; @@ -84,69 +190,57 @@ static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *c #if defined(RT_USING_SPIBUS1) if(base == LPSPI1) { - IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_27_LPSPI1_SCK, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_27_LPSPI1_SCK, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_28_LPSPI1_SDO, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_28_LPSPI1_SDO, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_29_LPSPI1_SDI, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_29_LPSPI1_SDI, 0x10B0u); + IOMUXC_SetPinMux (LPSPI1_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI1_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI1_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI1_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI1_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI1_SDI_GPIO, 0x10B0u); } #endif #if defined(RT_USING_SPIBUS2) if(base == LPSPI2) { - IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI, 0x10B0u); - - /* Optional IO config */ - //IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_00_LPSPI2_SCK, 0U); - //IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_00_LPSPI2_SCK, 0x10B0u); - //IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_02_LPSPI2_SDO, 0U); - //IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_02_LPSPI2_SDO, 0x10B0u); - //IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_03_LPSPI2_SDI, 0U); - //IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_03_LPSPI2_SDI, 0x10B0u); + IOMUXC_SetPinMux (LPSPI2_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI2_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI2_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI2_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI2_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI2_SDI_GPIO, 0x10B0u); } #endif #if defined(RT_USING_SPIBUS3) if(base == LPSPI3) { - IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0x10B0u); + IOMUXC_SetPinMux (LPSPI3_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI3_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI3_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI3_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI3_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI3_SDI_GPIO, 0x10B0u); } #endif #if defined(RT_USING_SPIBUS4) if(base == LPSPI4) { - IOMUXC_SetPinMux (IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0x10B0u); - IOMUXC_SetPinMux (IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0x10B0u); - - /* Optional IO config */ - //IOMUXC_SetPinMux (IOMUXC_GPIO_B1_07_LPSPI4_SCK, 0U); - //IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_LPSPI4_SCK, 0x10B0u); - //IOMUXC_SetPinMux (IOMUXC_GPIO_B1_06_LPSPI4_SDO, 0U); - //IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_LPSPI4_SDO, 0x10B0u); - //IOMUXC_SetPinMux (IOMUXC_GPIO_B1_05_LPSPI4_SDI, 0U); - //IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_LPSPI4_SDI, 0x10B0u); + IOMUXC_SetPinMux (LPSPI4_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI4_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI4_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI4_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI4_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI4_SDI_GPIO, 0x10B0u); } #endif LPSPI_MasterGetDefaultConfig(&masterConfig); + if(cfg->max_hz > 40*1000*1000) + { + cfg->max_hz = 40*1000*1000; + } masterConfig.baudRate = cfg->max_hz; masterConfig.bitsPerFrame = cfg->data_width; @@ -191,12 +285,12 @@ static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *c rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) { - rt_err_t ret; + rt_err_t ret = RT_EOK; struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); - struct rt1050_hw_spi_cs *cs_pin = (struct rt1050_hw_spi_cs *)rt_malloc(sizeof(struct rt1050_hw_spi_cs)); + struct rt1050_sw_spi_cs *cs_pin = (struct rt1050_sw_spi_cs *)rt_malloc(sizeof(struct rt1050_sw_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); cs_pin->pin = pin; @@ -210,7 +304,7 @@ rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_n static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { - rt_err_t ret; + rt_err_t ret = RT_EOK; struct rt1050_spi *spi = RT_NULL; RT_ASSERT(cfg != RT_NULL); @@ -232,17 +326,18 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * RT_ASSERT(device->bus->parent.user_data != RT_NULL); struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data); - struct rt1050_hw_spi_cs *cs = device->parent.user_data; + struct rt1050_sw_spi_cs *cs = device->parent.user_data; if(message->cs_take) { rt_pin_write(cs->pin, PIN_LOW); } - transfer.rxData = (uint8_t *)(message->recv_buf); - transfer.txData = (uint8_t *)(message->send_buf); transfer.dataSize = message->length; - status_t stat = LPSPI_MasterTransferBlocking(spi->base, &transfer); + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); + + LPSPI_MasterTransferBlocking(spi->base, &transfer); if(message->cs_release) { @@ -314,19 +409,19 @@ int rt_hw_spi_bus_init(void) #endif #if defined(RT_USING_SPIBUS1) - rt_spi_bus_register(&spi1_bus, "spibus1", &rt1050_spi_ops); + rt_spi_bus_register(&spi1_bus, "spi1", &rt1050_spi_ops); #endif #if defined(RT_USING_SPIBUS2) - rt_spi_bus_register(&spi2_bus, "spibus2", &rt1050_spi_ops); + rt_spi_bus_register(&spi2_bus, "spi2", &rt1050_spi_ops); #endif #if defined(RT_USING_SPIBUS3) - rt_spi_bus_register(&spi3_bus, "spibus3", &rt1050_spi_ops); + rt_spi_bus_register(&spi3_bus, "spi3", &rt1050_spi_ops); #endif #if defined(RT_USING_SPIBUS4) - rt_spi_bus_register(&spi4_bus, "spibus4", &rt1050_spi_ops); + rt_spi_bus_register(&spi4_bus, "spi4", &rt1050_spi_ops); #endif return RT_EOK; diff --git a/bsp/imxrt1052-evk/project.uvprojx b/bsp/imxrt1052-evk/project.uvprojx index 9efc66c679..9ab3526b19 100644 --- a/bsp/imxrt1052-evk/project.uvprojx +++ b/bsp/imxrt1052-evk/project.uvprojx @@ -10,7 +10,7 @@ RT-Thread IMXRT1052 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060528::V5.06 update 5 (build 528)::ARMCC MIMXRT1052:M7 @@ -334,7 +334,7 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 SKIP_SYSCLK_INIT, CPU_MIMXRT1052DVL6A, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, RT_USING_ARM_LIBC - applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix + applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix @@ -428,6 +428,11 @@ 1 drivers\drv_rtc.c + + drv_spi_bus.c + 1 + drivers\drv_spi_bus.c + hyper_flash_boot.c 1 @@ -907,6 +912,74 @@ DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + i2c_core.c @@ -963,6 +1036,16 @@ 1 ..\..\components\drivers\serial\serial.c + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + completion.c 1 diff --git a/bsp/imxrt1052-evk/rtconfig.h b/bsp/imxrt1052-evk/rtconfig.h index 79c7553e99..50a6fec9bf 100644 --- a/bsp/imxrt1052-evk/rtconfig.h +++ b/bsp/imxrt1052-evk/rtconfig.h @@ -95,6 +95,7 @@ #define RT_USING_PIN #define RT_USING_RTC #define RT_USING_SDIO +#define RT_USING_SPI /* Using USB */ @@ -193,11 +194,21 @@ #define SOC_IMXRT1052 #define BOARD_RT1050_EVK -/* RT1050_EVK Bsp Config */ +/* RT1050 Bsp Config */ -/* Select uart device */ +/* Select uart drivers */ #define RT_USING_UART1 + +/* Select spi bus drivers */ + +#define LPSPI_CLK_SOURCE_FROM_PLL3PFD1 +#define LPSPI_CLK_SOURCE 0 +#define LPSPI_CLK_SOURCE_DIVIDER 7 +#define RT_USING_SPIBUS4 +#define LPSPI4_SCK_GPIO_1 +#define LPSPI4_SDO_GPIO_1 +#define LPSPI4_SDI_GPIO_1 #define RT_USING_SDRAM #define RT_USING_RTC_HP From 80c2015c3af6db792c4a938cc28121791a89df2f Mon Sep 17 00:00:00 2001 From: armink Date: Sun, 1 Apr 2018 23:03:43 +0800 Subject: [PATCH 13/67] [DeviceDriver] Remove rt_memory api using on SFUD. --- components/drivers/spi/spi_flash_sfud.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/components/drivers/spi/spi_flash_sfud.c b/components/drivers/spi/spi_flash_sfud.c index d86179aaf8..2e97644fa4 100644 --- a/components/drivers/spi/spi_flash_sfud.c +++ b/components/drivers/spi/spi_flash_sfud.c @@ -510,14 +510,7 @@ static void sf(uint8_t argc, char **argv) { addr = 0; size = sfud_dev->chip.capacity; uint32_t start_time, time_cast; - rt_uint32_t total_mem, used_mem, max_uesd_mem; - rt_memory_info(&total_mem, &used_mem, &max_uesd_mem); - size_t write_size = SFUD_WRITE_MAX_PAGE_SIZE, read_size; - if ((total_mem - used_mem) / 2 < size) { - read_size = (total_mem - used_mem) / 2; - } else { - read_size = size; - } + size_t write_size = SFUD_WRITE_MAX_PAGE_SIZE, read_size = 4096; uint8_t *write_data = rt_malloc(write_size), *read_data = rt_malloc(read_size); if (write_data && read_data) { From c8a654ce9b6d872e9ab7cd238f57e8700fb72443 Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Mon, 2 Apr 2018 18:00:12 +0800 Subject: [PATCH 14/67] Update README.md --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 01a828711a..279ce96c23 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,7 @@ # RT-Thread # +[中文页](README_zh.md) | + [![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread) [![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) From aaf574f6fd16a1c4c0b00e361ae388ab8157351f Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Tue, 3 Apr 2018 11:40:11 +0800 Subject: [PATCH 15/67] [bsp][v2m-mps2] update project to remove mpython package default --- bsp/v2m-mps2/project.uvoptx | 2129 ++-------------------------------- bsp/v2m-mps2/project.uvprojx | 871 +------------- 2 files changed, 100 insertions(+), 2900 deletions(-) diff --git a/bsp/v2m-mps2/project.uvoptx b/bsp/v2m-mps2/project.uvoptx index 5a89df19a8..ec88cea752 100644 --- a/bsp/v2m-mps2/project.uvoptx +++ b/bsp/v2m-mps2/project.uvoptx @@ -148,24 +148,7 @@ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - - - 0 - 0 - 150 - 1 -
5262
- 0 - 0 - 0 - 0 - 0 - 1 - ..\..\src\components.c - - \\rtthread_v2m_mps2\../../src/components.c\150 - - + 0 @@ -219,7 +202,7 @@ Applications - 1 + 0 0 0 0 @@ -239,7 +222,7 @@ Drivers - 1 + 0 0 0 0 @@ -282,7 +265,7 @@ - MicroPython + Kernel 0 0 0 @@ -294,8 +277,8 @@ 0 0 0 - packages\micropython\py\argcheck.c - argcheck.c + ..\..\src\clock.c + clock.c 0 0 @@ -306,8 +289,8 @@ 0 0 0 - packages\micropython\py\asmarm.c - asmarm.c + ..\..\src\components.c + components.c 0 0 @@ -318,8 +301,8 @@ 0 0 0 - packages\micropython\py\asmbase.c - asmbase.c + ..\..\src\device.c + device.c 0 0 @@ -330,8 +313,8 @@ 0 0 0 - packages\micropython\py\asmthumb.c - asmthumb.c + ..\..\src\idle.c + idle.c 0 0 @@ -342,8 +325,8 @@ 0 0 0 - packages\micropython\py\asmx64.c - asmx64.c + ..\..\src\ipc.c + ipc.c 0 0 @@ -354,8 +337,8 @@ 0 0 0 - packages\micropython\py\asmx86.c - asmx86.c + ..\..\src\irq.c + irq.c 0 0 @@ -366,8 +349,8 @@ 0 0 0 - packages\micropython\py\asmxtensa.c - asmxtensa.c + ..\..\src\kservice.c + kservice.c 0 0 @@ -378,8 +361,8 @@ 0 0 0 - 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- - objint.c - 1 - packages\micropython\py\objint.c - - - objint_longlong.c - 1 - packages\micropython\py\objint_longlong.c - - - objint_mpz.c - 1 - packages\micropython\py\objint_mpz.c - - - objlist.c - 1 - packages\micropython\py\objlist.c - - - objmap.c - 1 - packages\micropython\py\objmap.c - - - objmodule.c - 1 - packages\micropython\py\objmodule.c - - - objnamedtuple.c - 1 - packages\micropython\py\objnamedtuple.c - - - objnone.c - 1 - packages\micropython\py\objnone.c - - - objobject.c - 1 - packages\micropython\py\objobject.c - - - objpolyiter.c - 1 - packages\micropython\py\objpolyiter.c - - - objproperty.c - 1 - packages\micropython\py\objproperty.c - - - objrange.c - 1 - packages\micropython\py\objrange.c - - - objreversed.c - 1 - packages\micropython\py\objreversed.c - - - objset.c - 1 - packages\micropython\py\objset.c - - - objsingleton.c - 1 - packages\micropython\py\objsingleton.c - - - objslice.c - 1 - packages\micropython\py\objslice.c - - - objstr.c - 1 - packages\micropython\py\objstr.c - - - objstringio.c - 1 - packages\micropython\py\objstringio.c - - - objstrunicode.c - 1 - packages\micropython\py\objstrunicode.c - - - objtuple.c - 1 - packages\micropython\py\objtuple.c - - - objtype.c - 1 - packages\micropython\py\objtype.c - - - objzip.c - 1 - packages\micropython\py\objzip.c - - - opmethods.c - 1 - packages\micropython\py\opmethods.c - - - parse.c - 1 - packages\micropython\py\parse.c - - - parsenum.c - 1 - packages\micropython\py\parsenum.c - - - parsenumbase.c - 1 - packages\micropython\py\parsenumbase.c - - - persistentcode.c - 1 - packages\micropython\py\persistentcode.c - - - pystack.c - 1 - packages\micropython\py\pystack.c - - - qstr.c - 1 - packages\micropython\py\qstr.c - - - reader.c - 1 - packages\micropython\py\reader.c - - - repl.c - 1 - packages\micropython\py\repl.c - - - runtime.c - 1 - packages\micropython\py\runtime.c - - - runtime_utils.c - 1 - packages\micropython\py\runtime_utils.c - - - scope.c - 1 - packages\micropython\py\scope.c - - - sequence.c - 1 - packages\micropython\py\sequence.c - - - showbc.c - 1 - packages\micropython\py\showbc.c - - - smallint.c - 1 - packages\micropython\py\smallint.c - - - stackctrl.c - 1 - packages\micropython\py\stackctrl.c - - - stream.c - 1 - packages\micropython\py\stream.c - - - unicode.c - 1 - packages\micropython\py\unicode.c - - - vm.c - 1 - packages\micropython\py\vm.c - - - vstr.c - 1 - packages\micropython\py\vstr.c - - - warning.c - 1 - packages\micropython\py\warning.c - - - readline.c - 1 - packages\micropython\lib\mp-readline\readline.c - - - interrupt_char.c - 1 - packages\micropython\lib\utils\interrupt_char.c - - - printf.c - 1 - packages\micropython\lib\utils\printf.c - - - pyexec.c - 1 - packages\micropython\lib\utils\pyexec.c - - - stdout_helpers.c - 1 - packages\micropython\lib\utils\stdout_helpers.c - - - machine_i2c.c - 1 - packages\micropython\extmod\machine_i2c.c - - - machine_mem.c - 1 - packages\micropython\extmod\machine_mem.c - - - machine_pinbase.c - 1 - packages\micropython\extmod\machine_pinbase.c - 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- - modutimeq.c - 1 - packages\micropython\extmod\modutimeq.c - - - moduzlib.c - 1 - packages\micropython\extmod\moduzlib.c - - - modwebrepl.c - 1 - packages\micropython\extmod\modwebrepl.c - - - modwebsocket.c - 1 - packages\micropython\extmod\modwebsocket.c - - - uos_dupterm.c - 1 - packages\micropython\extmod\uos_dupterm.c - - - utime_mphal.c - 1 - packages\micropython\extmod\utime_mphal.c - - - vfs.c - 1 - packages\micropython\extmod\vfs.c - - - vfs_fat.c - 1 - packages\micropython\extmod\vfs_fat.c - - - vfs_fat_diskio.c - 1 - packages\micropython\extmod\vfs_fat_diskio.c - - - vfs_fat_file.c - 1 - packages\micropython\extmod\vfs_fat_file.c - - - vfs_reader.c - 1 - packages\micropython\extmod\vfs_reader.c - - - virtpin.c - 1 - packages\micropython\extmod\virtpin.c - - - _frozen_mpy.c - 1 - packages\micropython\port\_frozen_mpy.c - - - file.c - 1 - packages\micropython\port\file.c - - - help.c - 1 - packages\micropython\port\help.c - - - machine_pin.c - 1 - packages\micropython\port\machine_pin.c - - - modmachine.c - 1 - packages\micropython\port\modmachine.c - - - modnetwork.c - 1 - packages\micropython\port\modnetwork.c - - - modpyb.c - 1 - packages\micropython\port\modpyb.c - - - modrtthread.c - 1 - packages\micropython\port\modrtthread.c - - - moduos.c - 1 - packages\micropython\port\moduos.c - - - moduos_file.c - 1 - packages\micropython\port\moduos_file.c - - - modusocket.c - 1 - packages\micropython\port\modusocket.c - - - modutime.c - 1 - packages\micropython\port\modutime.c - - - mpy_main.c - 1 - packages\micropython\port\mpy_main.c - - - rtt_getchar.c - 1 - packages\micropython\port\rtt_getchar.c - - - uart_core.c - 1 - packages\micropython\port\uart_core.c - - - netutils.c - 1 - packages\micropython\lib\netutils\netutils.c - - - Kernel From 327a6b6ff1cee83384c13abd3e1b64f6f8f5e8f7 Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Mon, 2 Apr 2018 22:02:10 +0800 Subject: [PATCH 16/67] [bsp][imxrt1052] add cache interface support --- bsp/imxrt1052-evk/drivers/SConscript | 1 + bsp/imxrt1052-evk/drivers/drv_cache.c | 75 + bsp/imxrt1052-evk/project.ewp | 26 +- bsp/imxrt1052-evk/project.uvoptx | 2199 +------------------------ bsp/imxrt1052-evk/project.uvprojx | 525 ++++-- 5 files changed, 512 insertions(+), 2314 deletions(-) create mode 100644 bsp/imxrt1052-evk/drivers/drv_cache.c diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript index 7133fea6fb..73bcec1fd6 100644 --- a/bsp/imxrt1052-evk/drivers/SConscript +++ b/bsp/imxrt1052-evk/drivers/SConscript @@ -8,6 +8,7 @@ cwd = os.path.join(str(Dir('#')), 'drivers') src = Split(""" board.c drv_uart.c +drv_cache.c """) CPPPATH = [cwd] diff --git a/bsp/imxrt1052-evk/drivers/drv_cache.c b/bsp/imxrt1052-evk/drivers/drv_cache.c new file mode 100644 index 0000000000..5cc68c50dc --- /dev/null +++ b/bsp/imxrt1052-evk/drivers/drv_cache.c @@ -0,0 +1,75 @@ +/* + * File : drv_cache.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2018-04-02 tanek first implementation + */ + +#include +#include +#include + +void rt_hw_cpu_icache_enable(void) +{ + SCB_EnableICache(); +} + +void rt_hw_cpu_icache_disable(void) +{ + SCB_DisableICache(); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +void rt_hw_cpu_icache_ops(int ops, void* addr, int size) +{ + if (ops & RT_HW_CACHE_INVALIDATE) + { + ICACHE_InvalidateByRange((uint32_t)addr, size); + } +} + +void rt_hw_cpu_dcache_enable(void) +{ + SCB_EnableDCache(); +} + +void rt_hw_cpu_dcache_disable(void) +{ + SCB_DisableDCache(); +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) +{ + if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) + { + DCACHE_CleanInvalidateByRange((uint32_t)addr, size); + } + else if (ops & RT_HW_CACHE_FLUSH) + { + DCACHE_CleanByRange((uint32_t)addr, size); + } + else if (ops & RT_HW_CACHE_INVALIDATE) + { + DCACHE_InvalidateByRange((uint32_t)addr, size); + } + else + { + RT_ASSERT(0); + } +} diff --git a/bsp/imxrt1052-evk/project.ewp b/bsp/imxrt1052-evk/project.ewp index 5443606ca3..d218142329 100644 --- a/bsp/imxrt1052-evk/project.ewp +++ b/bsp/imxrt1052-evk/project.ewp @@ -308,7 +308,7 @@ $PROJ_DIR$\Libraries\drivers $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src - $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix + $PROJ_DIR$\drivers $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4 $PROJ_DIR$\. $PROJ_DIR$\..\..\libcpu\arm\cortex-m7 @@ -316,10 +316,11 @@ $PROJ_DIR$\..\..\components\dfs\filesystems\devfs $PROJ_DIR$\Libraries\CMSIS\Include $PROJ_DIR$\Libraries\utilities + $PROJ_DIR$\..\..\components\drivers\spi $PROJ_DIR$\applications $PROJ_DIR$\..\..\components\finsh $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat - $PROJ_DIR$\drivers + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include - - Applications - 1 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - applications\device_test.c - device_test.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - applications\mem_dump.c - mem_dump.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - applications\mem_test.c - mem_test.c - 0 - 0 - - - - - Drivers - 1 - 0 - 0 - 0 - - 2 - 5 - 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ip4.c - 0 - 0 - - - 10 - 174 - 1 - 0 - 0 - 0 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - ip4_addr.c - 0 - 0 - - - 10 - 175 - 1 - 0 - 0 - 0 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - ip4_frag.c - 0 - 0 - - - ::CMSIS 0 diff --git a/bsp/imxrt1052-evk/project.uvprojx b/bsp/imxrt1052-evk/project.uvprojx index 9ab3526b19..57030f2377 100644 --- a/bsp/imxrt1052-evk/project.uvprojx +++ b/bsp/imxrt1052-evk/project.uvprojx @@ -1,44 +1,43 @@ - 2.1 -
### uVision Project, (C) Keil Software
- RT-Thread IMXRT1052 0x4 ARM-ADS 5060528::V5.06 update 5 (build 528)::ARMCC + 0 MIMXRT1052:M7 NXP - NXP.iMXRT_DFP.1.0.1 + NXP.iMXRT_DFP.1.0.2 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) 0 $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h - - - - - - - - - + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd 0 0 - - - - - + + + + + 0 0 @@ -60,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -70,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -81,14 +80,14 @@ 1 0 fromelf --bin !L --output rtthread-mdk.bin - + 0 0 0 0 0 - + 0 @@ -102,8 +101,8 @@ 0 0 3 - - + + 1 @@ -136,11 +135,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -173,7 +172,7 @@ 0 0 "Cortex-M7" - + 0 0 0 @@ -305,7 +304,7 @@ 0x20000 - + 1 @@ -333,7 +332,7 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 SKIP_SYSCLK_INIT, CPU_MIMXRT1052DVL6A, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, RT_USING_ARM_LIBC - + applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix @@ -349,10 +348,10 @@ 0 0 - - - - + + + + @@ -364,13 +363,13 @@ 0 0x00000000 0x10000000 - + .\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + @@ -383,16 +382,22 @@ 1 applications\device_test.c + + main.c 1 applications\main.c + + mem_dump.c 1 applications\mem_dump.c + + mem_test.c 1 @@ -408,46 +413,71 @@ 1 drivers\board.c + + drv_uart.c 1 drivers\drv_uart.c + + + + drv_cache.c + 1 + drivers\drv_cache.c + + + drv_sdram.c 1 drivers\drv_sdram.c + + drv_pin.c 1 drivers\drv_pin.c + + drv_rtc.c 1 drivers\drv_rtc.c + + drv_spi_bus.c 1 drivers\drv_spi_bus.c + + hyper_flash_boot.c 1 drivers\hyper_flash_boot.c + + drv_eth.c 1 drivers\drv_eth.c + + fsl_phy.c 1 drivers\fsl_phy.c + + drv_sdio.c 1 @@ -463,301 +493,421 @@ 1 Libraries\drivers\fsl_adc.c + + fsl_adc_etc.c 1 Libraries\drivers\fsl_adc_etc.c + + fsl_aipstz.c 1 Libraries\drivers\fsl_aipstz.c + + fsl_aoi.c 1 Libraries\drivers\fsl_aoi.c + + fsl_bee.c 1 Libraries\drivers\fsl_bee.c + + fsl_cache.c 1 Libraries\drivers\fsl_cache.c + + fsl_clock.c 1 Libraries\drivers\fsl_clock.c + + fsl_cmp.c 1 Libraries\drivers\fsl_cmp.c + + fsl_common.c 1 Libraries\drivers\fsl_common.c + + fsl_csi.c 1 Libraries\drivers\fsl_csi.c + + fsl_dcdc.c 1 Libraries\drivers\fsl_dcdc.c + + fsl_dcp.c 1 Libraries\drivers\fsl_dcp.c + + fsl_dmamux.c 1 Libraries\drivers\fsl_dmamux.c + + fsl_edma.c 1 Libraries\drivers\fsl_edma.c + + fsl_elcdif.c 1 Libraries\drivers\fsl_elcdif.c + + fsl_enc.c 1 Libraries\drivers\fsl_enc.c + + fsl_enet.c 1 Libraries\drivers\fsl_enet.c + + fsl_ewm.c 1 Libraries\drivers\fsl_ewm.c + + fsl_flexcan.c 1 Libraries\drivers\fsl_flexcan.c + + fsl_flexio.c 1 Libraries\drivers\fsl_flexio.c + + fsl_flexio_i2c_master.c 1 Libraries\drivers\fsl_flexio_i2c_master.c + + fsl_flexio_i2s.c 1 Libraries\drivers\fsl_flexio_i2s.c + + fsl_flexio_i2s_edma.c 1 Libraries\drivers\fsl_flexio_i2s_edma.c + + fsl_flexio_spi.c 1 Libraries\drivers\fsl_flexio_spi.c + + fsl_flexio_spi_edma.c 1 Libraries\drivers\fsl_flexio_spi_edma.c + + fsl_flexio_uart.c 1 Libraries\drivers\fsl_flexio_uart.c + + fsl_flexio_uart_edma.c 1 Libraries\drivers\fsl_flexio_uart_edma.c + + fsl_flexram.c 1 Libraries\drivers\fsl_flexram.c + + fsl_flexspi.c 1 Libraries\drivers\fsl_flexspi.c + + fsl_gpc.c 1 Libraries\drivers\fsl_gpc.c + + fsl_gpio.c 1 Libraries\drivers\fsl_gpio.c + + fsl_gpt.c 1 Libraries\drivers\fsl_gpt.c + + fsl_kpp.c 1 Libraries\drivers\fsl_kpp.c + + fsl_lpi2c.c 1 Libraries\drivers\fsl_lpi2c.c + + fsl_lpi2c_edma.c 1 Libraries\drivers\fsl_lpi2c_edma.c + + fsl_lpspi.c 1 Libraries\drivers\fsl_lpspi.c + + fsl_lpspi_edma.c 1 Libraries\drivers\fsl_lpspi_edma.c + + fsl_lpuart.c 1 Libraries\drivers\fsl_lpuart.c + + fsl_lpuart_edma.c 1 Libraries\drivers\fsl_lpuart_edma.c + + fsl_pit.c 1 Libraries\drivers\fsl_pit.c + + fsl_pmu.c 1 Libraries\drivers\fsl_pmu.c + + fsl_pwm.c 1 Libraries\drivers\fsl_pwm.c + + fsl_pxp.c 1 Libraries\drivers\fsl_pxp.c + + fsl_qtmr.c 1 Libraries\drivers\fsl_qtmr.c + + fsl_rtwdog.c 1 Libraries\drivers\fsl_rtwdog.c + + fsl_sai.c 1 Libraries\drivers\fsl_sai.c + + fsl_sai_edma.c 1 Libraries\drivers\fsl_sai_edma.c + + fsl_semc.c 1 Libraries\drivers\fsl_semc.c + + fsl_snvs_hp.c 1 Libraries\drivers\fsl_snvs_hp.c + + fsl_snvs_lp.c 1 Libraries\drivers\fsl_snvs_lp.c + + fsl_spdif.c 1 Libraries\drivers\fsl_spdif.c + + fsl_spdif_edma.c 1 Libraries\drivers\fsl_spdif_edma.c + + fsl_src.c 1 Libraries\drivers\fsl_src.c + + fsl_trng.c 1 Libraries\drivers\fsl_trng.c + + fsl_tsc.c 1 Libraries\drivers\fsl_tsc.c + + fsl_usdhc.c 1 Libraries\drivers\fsl_usdhc.c + + fsl_wdog.c 1 Libraries\drivers\fsl_wdog.c + + fsl_xbara.c 1 Libraries\drivers\fsl_xbara.c + + fsl_xbarb.c 1 Libraries\drivers\fsl_xbarb.c + + system_MIMXRT1052.c 1 Libraries\system_MIMXRT1052.c + + startup_MIMXRT1052.s 2 @@ -773,61 +923,85 @@ 1 ..\..\src\clock.c + + components.c 1 ..\..\src\components.c + + device.c 1 ..\..\src\device.c + + idle.c 1 ..\..\src\idle.c + + ipc.c 1 ..\..\src\ipc.c + + irq.c 1 ..\..\src\irq.c + + kservice.c 1 ..\..\src\kservice.c + + memheap.c 1 ..\..\src\memheap.c + + object.c 1 ..\..\src\object.c + + scheduler.c 1 ..\..\src\scheduler.c + + signal.c 1 ..\..\src\signal.c + + thread.c 1 ..\..\src\thread.c + + timer.c 1 @@ -843,21 +1017,29 @@ 1 ..\..\libcpu\arm\cortex-m7\cpuport.c + + context_rvds.S 2 ..\..\libcpu\arm\cortex-m7\context_rvds.S + + backtrace.c 1 ..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\libcpu\arm\common\div0.c + + showmem.c 1 @@ -873,36 +1055,50 @@ 1 ..\..\components\dfs\src\dfs.c + + dfs_file.c 1 ..\..\components\dfs\src\dfs_file.c + + dfs_fs.c 1 ..\..\components\dfs\src\dfs_fs.c + + dfs_posix.c 1 ..\..\components\dfs\src\dfs_posix.c + + devfs.c 1 ..\..\components\dfs\filesystems\devfs\devfs.c + + dfs_elm.c 1 ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + ff.c 1 ..\..\components\dfs\filesystems\elmfat\ff.c + + ccsbcs.c 1 @@ -912,171 +1108,151 @@ DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - i2c_core.c 1 ..\..\components\drivers\i2c\i2c_core.c + + i2c_dev.c 1 ..\..\components\drivers\i2c\i2c_dev.c + + i2c-bit-ops.c 1 ..\..\components\drivers\i2c\i2c-bit-ops.c + + pin.c 1 ..\..\components\drivers\misc\pin.c + + rtc.c 1 ..\..\components\drivers\rtc\rtc.c + + block_dev.c 1 ..\..\components\drivers\sdio\block_dev.c + + mmcsd_core.c 1 ..\..\components\drivers\sdio\mmcsd_core.c + + sd.c 1 ..\..\components\drivers\sdio\sd.c + + sdio.c 1 ..\..\components\drivers\sdio\sdio.c + + mmc.c 1 ..\..\components\drivers\sdio\mmc.c + + serial.c 1 ..\..\components\drivers\serial\serial.c + + spi_core.c 1 ..\..\components\drivers\spi\spi_core.c + + spi_dev.c 1 ..\..\components\drivers\spi\spi_dev.c + + completion.c 1 ..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\components\drivers\src\pipe.c + + ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 ..\..\components\drivers\src\workqueue.c + + + + + + + + + + + + finsh @@ -1086,76 +1262,106 @@ 1 ..\..\components\finsh\shell.c + + symbol.c 1 ..\..\components\finsh\symbol.c + + cmd.c 1 ..\..\components\finsh\cmd.c + + msh.c 1 ..\..\components\finsh\msh.c + + msh_cmd.c 1 ..\..\components\finsh\msh_cmd.c + + msh_file.c 1 ..\..\components\finsh\msh_file.c + + finsh_compiler.c 1 ..\..\components\finsh\finsh_compiler.c + + finsh_error.c 1 ..\..\components\finsh\finsh_error.c + + finsh_heap.c 1 ..\..\components\finsh\finsh_heap.c + + finsh_init.c 1 ..\..\components\finsh\finsh_init.c + + finsh_node.c 1 ..\..\components\finsh\finsh_node.c + + finsh_ops.c 1 ..\..\components\finsh\finsh_ops.c + + finsh_parser.c 1 ..\..\components\finsh\finsh_parser.c + + finsh_var.c 1 ..\..\components\finsh\finsh_var.c + + finsh_vm.c 1 ..\..\components\finsh\finsh_vm.c + + finsh_token.c 1 @@ -1171,26 +1377,36 @@ 1 ..\..\components\libc\compilers\armlibc\libc.c + + libc_syms.c 1 ..\..\components\libc\compilers\armlibc\libc_syms.c + + mem_std.c 1 ..\..\components\libc\compilers\armlibc\mem_std.c + + stdio.c 1 ..\..\components\libc\compilers\armlibc\stdio.c + + stubs.c 1 ..\..\components\libc\compilers\armlibc\stubs.c + + time.c 1 @@ -1206,176 +1422,246 @@ 1 ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c + + api_lib.c 1 ..\..\components\net\lwip-2.0.2\src\api\api_lib.c + + api_msg.c 1 ..\..\components\net\lwip-2.0.2\src\api\api_msg.c + + err.c 1 ..\..\components\net\lwip-2.0.2\src\api\err.c + + netbuf.c 1 ..\..\components\net\lwip-2.0.2\src\api\netbuf.c + + netdb.c 1 ..\..\components\net\lwip-2.0.2\src\api\netdb.c + + netifapi.c 1 ..\..\components\net\lwip-2.0.2\src\api\netifapi.c + + sockets.c 1 ..\..\components\net\lwip-2.0.2\src\api\sockets.c + + tcpip.c 1 ..\..\components\net\lwip-2.0.2\src\api\tcpip.c + + def.c 1 ..\..\components\net\lwip-2.0.2\src\core\def.c + + dns.c 1 ..\..\components\net\lwip-2.0.2\src\core\dns.c + + inet_chksum.c 1 ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c + + init.c 1 ..\..\components\net\lwip-2.0.2\src\core\init.c + + ip.c 1 ..\..\components\net\lwip-2.0.2\src\core\ip.c + + memp.c 1 ..\..\components\net\lwip-2.0.2\src\core\memp.c + + netif.c 1 ..\..\components\net\lwip-2.0.2\src\core\netif.c + + pbuf.c 1 ..\..\components\net\lwip-2.0.2\src\core\pbuf.c + + raw.c 1 ..\..\components\net\lwip-2.0.2\src\core\raw.c + + stats.c 1 ..\..\components\net\lwip-2.0.2\src\core\stats.c + + sys.c 1 ..\..\components\net\lwip-2.0.2\src\core\sys.c + + tcp.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp.c + + tcp_in.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c + + tcp_out.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c + + timeouts.c 1 ..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + udp.c 1 ..\..\components\net\lwip-2.0.2\src\core\udp.c + + ethernet.c 1 ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + ethernetif.c 1 ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + lowpan6.c 1 ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + autoip.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + dhcp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + etharp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + icmp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + igmp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + ip4.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + ip4_addr.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + ip4_frag.c 1 @@ -1383,24 +1669,19 @@ - - ::CMSIS - - - + - + - + - + - From 5fd9bd67a815b6811f7d1974f1c1509cc7950745 Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Thu, 5 Apr 2018 18:41:45 +0800 Subject: [PATCH 17/67] [bsp][imxrt1052] support auto update flash programming algorithm for wildfire board --- bsp/imxrt1052-evk/SConstruct | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/bsp/imxrt1052-evk/SConstruct b/bsp/imxrt1052-evk/SConstruct index 23d4762514..fc7e9d11a7 100644 --- a/bsp/imxrt1052-evk/SConstruct +++ b/bsp/imxrt1052-evk/SConstruct @@ -46,3 +46,26 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # make a building DoBuilding(TARGET, objs) + +def Update_MDKFlashProgrammingAlgorithm(flash_dict): + import xml.etree.ElementTree as etree + from utils import xml_indent + + project_tree = etree.parse('project.uvoptx') + root = project_tree.getroot() + out = file('project.uvoptx', 'wb') + + for elem in project_tree.iterfind('.//Target/TargetOption/TargetDriverDllRegistry/SetRegEntry'): + Key = elem.find('Key') + if Key.text in flash_dict.keys(): + elem.find('Name').text = flash_dict[Key.text] + + xml_indent(root) + out.write(etree.tostring(root, encoding='utf-8')) + out.close() + +if GetOption('target') and GetDepend('BOARD_RT1050_FIRE'): + Update_MDKFlashProgrammingAlgorithm({ + "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', + "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', + }) From 6d63451e38f59f0874b94d7ece3a706a8794c27b Mon Sep 17 00:00:00 2001 From: balanceTWK Date: Thu, 5 Apr 2018 11:44:25 +0800 Subject: [PATCH 18/67] [bsp][imxrt1052] add hardware i2c --- bsp/imxrt1052-evk/Kconfig | 54 ++- bsp/imxrt1052-evk/drivers/SConscript | 4 + bsp/imxrt1052-evk/drivers/drv_i2c.c | 538 ++++++++++++++++++++++----- bsp/imxrt1052-evk/drivers/drv_i2c.h | 34 ++ 4 files changed, 538 insertions(+), 92 deletions(-) create mode 100644 bsp/imxrt1052-evk/drivers/drv_i2c.h diff --git a/bsp/imxrt1052-evk/Kconfig b/bsp/imxrt1052-evk/Kconfig index 0216ef30d6..acfdff1a48 100644 --- a/bsp/imxrt1052-evk/Kconfig +++ b/bsp/imxrt1052-evk/Kconfig @@ -93,7 +93,7 @@ menu "Select spi bus drivers" config LPSPI_CLK_SOURCE_DIVIDER int "SPI bus clock source divider" - range 0 8 + range 1 8 default 7 config RT_USING_SPIBUS1 @@ -225,6 +225,58 @@ menu "Select spi bus drivers" endchoice endmenu +menu "Select iic drivers" + + config LPI2C_CLOCK_SOURCE_DIVIDER + int "lpi2c bus clock source divider" + range 1 64 + default 4 + + config RT_USING_I2C1 + bool "USING I2C1" + select RT_USING_I2C + default n + if RT_USING_I2C1 + config RT_USING_I2C1_BITOPS + select RT_USING_I2C_BITOPS + default n + bool "using simulate I2C1" + endif + + config RT_USING_I2C2 + bool "USING I2C2" + select RT_USING_I2C + default n + if RT_USING_I2C2 + config RT_USING_I2C2_BITOPS + select RT_USING_I2C_BITOPS + default n + bool "using simulate I2C2" + endif + + config RT_USING_I2C3 + bool "USING I2C3" + select RT_USING_I2C + default n + if RT_USING_I2C3 + config RT_USING_I2C3_BITOPS + select RT_USING_I2C_BITOPS + default n + bool "using simulate I2C3" + endif + + config RT_USING_I2C4 + bool "USING I2C4" + select RT_USING_I2C + default n + if RT_USING_I2C4 + config RT_USING_I2C4_BITOPS + select RT_USING_I2C_BITOPS + default n + bool "using simulate I2C4" + endif +endmenu + #menu "SDRAM driver support" config RT_USING_SDRAM bool "Using sdram" diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript index 73bcec1fd6..e19e0044bd 100644 --- a/bsp/imxrt1052-evk/drivers/SConscript +++ b/bsp/imxrt1052-evk/drivers/SConscript @@ -30,6 +30,10 @@ if GetDepend('RT_USING_RTC_HP'): if GetDepend('RT_USING_SPI'): src += ['drv_spi_bus.c'] +# add i2cbus driver code +if GetDepend('RT_USING_I2C'): + src += ['drv_i2c.c'] + if GetDepend('BOARD_RT1050_EVK'): src += ['hyper_flash_boot.c'] diff --git a/bsp/imxrt1052-evk/drivers/drv_i2c.c b/bsp/imxrt1052-evk/drivers/drv_i2c.c index 4d23ea36cc..efe33efa6e 100644 --- a/bsp/imxrt1052-evk/drivers/drv_i2c.c +++ b/bsp/imxrt1052-evk/drivers/drv_i2c.c @@ -19,23 +19,32 @@ * Change Logs: * Date Author Notes * 2017-08-08 Yang the first version + * 2018-03-24 LaiYiKeTang add hardware iic */ - + #include #include #include "board.h" #include "fsl_gpio.h" #include "fsl_lpi2c.h" +#include "drv_i2c.h" //#define DRV_I2C_DEBUG #ifdef RT_USING_I2C -#ifdef RT_USING_I2C_BITOPS +#define I2C1BUS_NAME "i2c1" +#define I2C2BUS_NAME "i2c2" +#define I2C3BUS_NAME "i2c3" +#define I2C4BUS_NAME "i2c4" -#define I2CBUS_NAME "i2c0" +/* Get frequency of lpi2c clock */ +#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U)) -struct stm32_i2c_bit_data +#if defined(RT_USING_I2C_BITOPS) && (defined(RT_USING_I2C1_BITOPS) || defined(RT_USING_I2C2_BITOPS) || \ + defined(RT_USING_I2C3_BITOPS) || defined(RT_USING_I2C4_BITOPS)) + +struct rt1052_i2c_bit_data { struct { @@ -49,24 +58,24 @@ static void gpio_udelay(rt_uint32_t us) volatile rt_int32_t i; for (; us > 0; us--) { - i = 1000; + i = 100; while (i--); } } -static void gpio_set_input(GPIO_Type* base, uint32_t pin) +static void gpio_set_input(GPIO_Type *base, uint32_t pin) { - if (base->GDIR & (1 << pin)) //output mode + if (base->GDIR & (1 << pin)) { base->GDIR &= ~(1 << pin); gpio_udelay(5); } } -static void gpio_set_output(GPIO_Type* base, uint32_t pin) +static void gpio_set_output(GPIO_Type *base, uint32_t pin) { - if (!(base->GDIR & (1 << pin))) //input mode - { + if (!(base->GDIR & (1 << pin))) + { base->GDIR |= (1 << pin); gpio_udelay(5); } @@ -74,26 +83,26 @@ static void gpio_set_output(GPIO_Type* base, uint32_t pin) static void gpio_set_sda(void *data, rt_int32_t state) { - struct stm32_i2c_bit_data *bd = data; - + struct rt1052_i2c_bit_data *bd = data; + gpio_set_output(bd->sda.base, bd->sda.pin); - + GPIO_PinWrite(bd->sda.base, bd->sda.pin, !!state); } static void gpio_set_scl(void *data, rt_int32_t state) { - struct stm32_i2c_bit_data *bd = data; - + struct rt1052_i2c_bit_data *bd = data; + gpio_set_output(bd->scl.base, bd->scl.pin); - + GPIO_PinWrite(bd->scl.base, bd->scl.pin, !!state); } static rt_int32_t gpio_get_sda(void *data) { - struct stm32_i2c_bit_data *bd = data; - + struct rt1052_i2c_bit_data *bd = data; + gpio_set_input(bd->sda.base, bd->sda.pin); return GPIO_ReadPinInput(bd->sda.base, bd->sda.pin); @@ -101,89 +110,434 @@ static rt_int32_t gpio_get_sda(void *data) static rt_int32_t gpio_get_scl(void *data) { - struct stm32_i2c_bit_data *bd = data; - + struct rt1052_i2c_bit_data *bd = data; + gpio_set_input(bd->scl.base, bd->scl.pin); return GPIO_ReadPinInput(bd->scl.base, bd->scl.pin); } +#endif -#else /* RT_USING_I2C_BITOPS */ - // todo : add hardware i2c -#endif /* RT_USING_I2C_BITOPS */ +#ifdef RT_USING_I2C1 +#ifdef RT_USING_I2C1_BITOPS + +#else +static struct rt1052_i2c_bus lpi2c1 = +{ + .I2C = LPI2C1, + .device_name = I2C1BUS_NAME, +}; +#endif /* RT_USING_I2C1_BITOPS */ +#endif /* RT_USING_I2C1 */ + +#ifdef RT_USING_I2C2 +#ifdef RT_USING_I2C2_BITOPS + +#else +static struct rt1052_i2c_bus lpi2c2 = +{ + .I2C = LPI2C2, + .device_name = I2C2BUS_NAME, +}; +#endif /* RT_USING_I2C2_BITOPS */ +#endif /* RT_USING_I2C2 */ + +#ifdef RT_USING_I2C3 +#ifdef RT_USING_I2C3_BITOPS + +#else +static struct rt1052_i2c_bus lpi2c3 = +{ + .I2C = LPI2C3, + .device_name = I2C3BUS_NAME, +}; + +#endif /* RT_USING_I2C3_BITOPS */ +#endif /* RT_USING_I2C3 */ + +#ifdef RT_USING_I2C4 + +#ifdef RT_USING_I2C4_BITOPS + +#else +static struct rt1052_i2c_bus lpi2c4 = +{ + .I2C = LPI2C4, + .device_name = I2C4BUS_NAME, +}; +#endif /* RT_USING_I2C1_BITOPS */ + +#endif /* RT_USING_I2C4 */ + +#if (defined(RT_USING_I2C1) || defined(RT_USING_I2C2) || \ + defined(RT_USING_I2C3) || defined(RT_USING_I2C4)) + +static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t, + rt_uint32_t); + +static const struct rt_i2c_bus_device_ops imxrt_i2c_ops = +{ + imxrt_i2c_mst_xfer, + imxrt_i2c_slv_xfer, + imxrt_i2c_bus_control, +}; + +#if !defined(RT_USING_I2C_BITOPS) || (!defined(RT_USING_I2C1_BITOPS) || !defined(RT_USING_I2C2_BITOPS) || \ + !defined(RT_USING_I2C3_BITOPS) || !defined(RT_USING_I2C4_BITOPS)) + +void imxrt_lpi2c_gpio_init(struct rt1052_i2c_bus *bus) +{ + if (bus->I2C == LPI2C1) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, + 0xD8B0u); + } + else if (bus->I2C == LPI2C2) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_04_LPI2C2_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_05_LPI2C2_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_04_LPI2C2_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_05_LPI2C2_SDA, + 0xD8B0u); + } + else if (bus->I2C == LPI2C3) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, + 0xD8B0u); + } + else if (bus->I2C == LPI2C4) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_12_LPI2C4_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_11_LPI2C4_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_12_LPI2C4_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_11_LPI2C4_SDA, + 0xD8B0u); + } + else + { + RT_ASSERT(RT_NULL); + } +} + +static rt_err_t imxrt_lpi2c_configure(struct rt1052_i2c_bus *bus, lpi2c_master_config_t *cfg) +{ + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + imxrt_lpi2c_gpio_init(bus); + bus->parent.ops = &imxrt_i2c_ops; + LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY); + return RT_EOK; +} + +#endif + +static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt1052_i2c_bus *rt1052_i2c; + rt_uint32_t numbak; + rt_uint16_t i; + RT_ASSERT(bus != RT_NULL); + rt1052_i2c = (struct rt1052_i2c_bus *) bus; + + rt1052_i2c->msg = msgs; + rt1052_i2c->msg_ptr = 0; + rt1052_i2c->msg_cnt = num; + rt1052_i2c->dptr = 0; + + for (i = 0; i < num; i++) + { + if (rt1052_i2c->msg[i].flags & RT_I2C_RD) + { + LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Read); + if (LPI2C_MasterReceive(rt1052_i2c->I2C, rt1052_i2c->msg->buf, rt1052_i2c->msg->len) == kStatus_LPI2C_Nak) + { + i = 0; + break; + } + } + else + { + LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Write); + if (LPI2C_MasterSend(rt1052_i2c->I2C, rt1052_i2c->msg->buf, rt1052_i2c->msg->len) == kStatus_LPI2C_Nak) + { + i = 0; + break; + } + } + } + + i2c_dbg("send stop condition\n"); + LPI2C_MasterStop(rt1052_i2c->I2C); + + numbak = i; + rt1052_i2c->msg = RT_NULL; + rt1052_i2c->msg_ptr = 0; + rt1052_i2c->msg_cnt = 0; + rt1052_i2c->dptr = 0; + return numbak; +} +static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + return 0; +} +static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t cmd, + rt_uint32_t arg) +{ + return RT_ERROR; +} + +#endif int rt_hw_i2c_init(void) { -#ifdef RT_USING_I2C_BITOPS - /* register I2C1: SCL/P0_20 SDA/P0_19 */ +#if !defined(RT_USING_I2C_BITOPS) || (!defined(RT_USING_I2C1_BITOPS) || !defined(RT_USING_I2C2_BITOPS) || \ + !defined(RT_USING_I2C3_BITOPS) || !defined(RT_USING_I2C4_BITOPS)) + + lpi2c_master_config_t masterConfig = {0}; + + /*Clock setting for LPI2C*/ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER); + +#endif + +#if defined(RT_USING_I2C_BITOPS) && (defined(RT_USING_I2C1_BITOPS) || defined(RT_USING_I2C2_BITOPS) || \ + defined(RT_USING_I2C3_BITOPS) || defined(RT_USING_I2C4_BITOPS)) + gpio_pin_config_t pin_config = { - static struct rt_i2c_bus_device i2c_device; + kGPIO_DigitalOutput, + 0, + }; +#endif /* RT_USING_I2C_BITOPS= RT_USING_I2C1_BITOPS RT_USING_I2C2_BITOPS RT_USING_I2C3_BITOPS RT_USING_I2C4_BITOPS */ +#if defined(RT_USING_I2C1) && defined(RT_USING_I2C1_BITOPS) - static const struct stm32_i2c_bit_data _i2c_bdata = - { - /* SCL */ {GPIO1, 16}, - /* SDA */ {GPIO1, 17}, - }; + static struct rt_i2c_bus_device i2c1_device; - static const struct rt_i2c_bit_ops _i2c_bit_ops = - { - (void*)&_i2c_bdata, - gpio_set_sda, - gpio_set_scl, - gpio_get_sda, - gpio_get_scl, + static const struct rt1052_i2c_bit_data _i2c1_bdata = + { + /* SCL */ {GPIO1, 16}, + /* SDA */ {GPIO1, 17}, + }; - gpio_udelay, + static const struct rt_i2c_bit_ops _i2c1_bit_ops = + { + (void *) &_i2c1_bdata, + gpio_set_sda, + gpio_set_scl, + gpio_get_sda, + gpio_get_scl, - 50, - 1000 - }; + gpio_udelay, - gpio_pin_config_t pin_config = { - kGPIO_DigitalOutput, 0, - }; - - CLOCK_EnableClock(kCLOCK_Iomuxc); + 50, + 1000 + }; - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_GPIO1_IO16, 1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_GPIO1_IO16, - 0xD8B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 22K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_GPIO1_IO17, 1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_GPIO1_IO17, - 0xD8B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 22K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - /* Enable touch panel controller */ - GPIO_PinInit(_i2c_bdata.sda.base, _i2c_bdata.sda.pin, &pin_config); - GPIO_PinInit(_i2c_bdata.scl.base, _i2c_bdata.scl.pin, &pin_config); - - GPIO_PortSet(_i2c_bdata.sda.base, _i2c_bdata.sda.pin); - GPIO_PortSet(_i2c_bdata.scl.base, _i2c_bdata.scl.pin); - - //RT_ASSERT(gpio_get_scl(&_i2c_bdata) != 0); - //RT_ASSERT(gpio_get_sda(&_i2c_bdata) != 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_GPIO1_IO16, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_GPIO1_IO16, 0xD8B0u); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_GPIO1_IO17, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_GPIO1_IO17, 0xD8B0u); - i2c_device.priv = (void *)&_i2c_bit_ops; - rt_i2c_bit_add_bus(&i2c_device, I2CBUS_NAME); - } /* register I2C */ + /* Enable touch panel controller */ + GPIO_PinInit(_i2c1_bdata.sda.base, _i2c1_bdata.sda.pin, &pin_config); + GPIO_PinInit(_i2c1_bdata.scl.base, _i2c1_bdata.scl.pin, &pin_config); + + GPIO_PortSet(_i2c1_bdata.sda.base, _i2c1_bdata.sda.pin); + GPIO_PortSet(_i2c1_bdata.scl.base, _i2c1_bdata.scl.pin); + + i2c1_device.priv = (void *) &_i2c1_bit_ops; + rt_i2c_bit_add_bus(&i2c1_device, I2C1BUS_NAME); + +#elif defined(RT_USING_I2C1) && !defined(RT_USING_I2C1_BITOPS) + LPI2C_MasterGetDefaultConfig(&masterConfig); + imxrt_lpi2c_configure(&lpi2c1, &masterConfig); + rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name); +#endif +#if defined(RT_USING_I2C2) && defined(RT_USING_I2C2_BITOPS) + + static struct rt_i2c_bus_device i2c2_device; + + static const struct rt1052_i2c_bit_data _i2c2_bdata = + { + /* SCL */ {GPIO2, 4}, + /* SDA */ {GPIO2, 5}, + }; + + static const struct rt_i2c_bit_ops _i2c2_bit_ops = + { + (void *) &_i2c2_bdata, + gpio_set_sda, + gpio_set_scl, + gpio_get_sda, + gpio_get_scl, + + gpio_udelay, + + 50, + 1000 + }; + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_GPIO2_IO04, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_GPIO2_IO04, 0xD8B0u); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_GPIO2_IO05, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_GPIO2_IO05, 0xD8B0u); + + /* Enable touch panel controller */ + GPIO_PinInit(_i2c2_bdata.sda.base, _i2c2_bdata.sda.pin, &pin_config); + GPIO_PinInit(_i2c2_bdata.scl.base, _i2c2_bdata.scl.pin, &pin_config); + + GPIO_PortSet(_i2c2_bdata.sda.base, _i2c2_bdata.sda.pin); + GPIO_PortSet(_i2c2_bdata.scl.base, _i2c2_bdata.scl.pin); + + + i2c2_device.priv = (void *) &_i2c2_bit_ops; + rt_i2c_bit_add_bus(&i2c2_device, I2C2BUS_NAME); + +#elif defined(RT_USING_I2C2) && !defined(RT_USING_I2C2_BITOPS) + LPI2C_MasterGetDefaultConfig(&masterConfig); + imxrt_lpi2c_configure(&lpi2c2, &masterConfig); + rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name); +#endif +#if defined(RT_USING_I2C3) && defined(RT_USING_I2C3_BITOPS) + + static struct rt_i2c_bus_device i2c3_device; + + static const struct rt1052_i2c_bit_data _i2c3_bdata = + { + /* SCL */ {GPIO1, 23}, + /* SDA */ {GPIO1, 22}, + }; + + static const struct rt_i2c_bit_ops _i2c3_bit_ops = + { + (void *) &_i2c3_bdata, + gpio_set_sda, + gpio_set_scl, + gpio_get_sda, + gpio_get_scl, + + gpio_udelay, + + 50, + 1000 + }; + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0xD8B0u); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xD8B0u); + + /* Enable touch panel controller */ + GPIO_PinInit(_i2c3_bdata.sda.base, _i2c3_bdata.sda.pin, &pin_config); + GPIO_PinInit(_i2c3_bdata.scl.base, _i2c3_bdata.scl.pin, &pin_config); + + GPIO_PortSet(_i2c3_bdata.sda.base, _i2c3_bdata.sda.pin); + GPIO_PortSet(_i2c3_bdata.scl.base, _i2c3_bdata.scl.pin); + + + i2c3_device.priv = (void *) &_i2c3_bit_ops; + rt_i2c_bit_add_bus(&i2c3_device, I2C3BUS_NAME); + +#elif defined(RT_USING_I2C3) && !defined(RT_USING_I2C3_BITOPS) + LPI2C_MasterGetDefaultConfig(&masterConfig); + imxrt_lpi2c_configure(&lpi2c3, &masterConfig); + rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name); +#endif +#if defined(RT_USING_I2C4) && defined(RT_USING_I2C4_BITOPS) + + static struct rt_i2c_bus_device i2c4_device; + + static const struct rt1052_i2c_bit_data _i2c4_bdata = + { + /* SCL */ {GPIO4, 12}, + /* SDA */ {GPIO4, 11}, + }; + + static const struct rt_i2c_bit_ops _i2c4_bit_ops = + { + (void *) &_i2c4_bdata, + gpio_set_sda, + gpio_set_scl, + gpio_get_sda, + gpio_get_scl, + + gpio_udelay, + + 50, + 1000 + }; + + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_GPIO4_IO12, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_12_GPIO4_IO12, 0xD8B0u); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_GPIO4_IO11, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_11_GPIO4_IO11, 0xD8B0u); + + /* Enable touch panel controller */ + GPIO_PinInit(_i2c4_bdata.sda.base, _i2c4_bdata.sda.pin, &pin_config); + GPIO_PinInit(_i2c4_bdata.scl.base, _i2c4_bdata.scl.pin, &pin_config); + + GPIO_PortSet(_i2c4_bdata.sda.base, _i2c4_bdata.sda.pin); + GPIO_PortSet(_i2c4_bdata.scl.base, _i2c4_bdata.scl.pin); + + + i2c4_device.priv = (void *) &_i2c4_bit_ops; + rt_i2c_bit_add_bus(&i2c4_device, I2C4BUS_NAME); + +#elif defined(RT_USING_I2C4) && !defined(RT_USING_I2C4_BITOPS) + LPI2C_MasterGetDefaultConfig(&masterConfig); + imxrt_lpi2c_configure(&lpi2c4, &masterConfig); + rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name); +#endif -#else /* RT_USING_I2C_BITOPS */ - // Todo : add hardware i2c -#endif /* RT_USING_I2C_BITOPS */ return 0; } @@ -197,7 +551,7 @@ static rt_device_t _i2c_find(const char *name) rt_device_t dev; dev = rt_device_find(name); - if (!dev) + if (!dev) { rt_kprintf("search device failed: %s\n", name); return RT_NULL; @@ -210,7 +564,7 @@ static rt_device_t _i2c_find(const char *name) } rt_kprintf("open i2c bus: %s\n", name); - + return dev; } @@ -231,7 +585,7 @@ static void _search_i2c_device(rt_device_t dev, uint8_t cmd) for (int i = 0; i <= 0x7f; i++) { int len; - + msgs[0].addr = i; msgs[1].addr = i; len = rt_i2c_transfer((struct rt_i2c_bus_device *)dev, msgs, 2); @@ -239,9 +593,9 @@ static void _search_i2c_device(rt_device_t dev, uint8_t cmd) { count++; rt_kprintf("add:%02X transfer success, id: %02X\n", i, buf); - } + } } - + rt_kprintf("i2c device: %d\n", count); } @@ -253,14 +607,16 @@ static int i2c_test(const char *name, uint8_t cmd) rt_kprintf("search i2c device faild\n"); return -1; } - + _search_i2c_device(dev, cmd); - + rt_device_close(dev); - + return 0; } -FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c0", 0xA3)); +FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c1", 0xA3)); #endif #endif /* RT_USING_I2C */ + + diff --git a/bsp/imxrt1052-evk/drivers/drv_i2c.h b/bsp/imxrt1052-evk/drivers/drv_i2c.h new file mode 100644 index 0000000000..4743225c37 --- /dev/null +++ b/bsp/imxrt1052-evk/drivers/drv_i2c.h @@ -0,0 +1,34 @@ +/* + * File : drv_i2c.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2018-03-24 LaiYiKeTang the first version + */ + +#ifndef __DRVI2C_H__ +#define __DRVI2C_H__ + +#include +#include +#include +#include "board.h" +struct rt1052_i2c_bus +{ + struct rt_i2c_bus_device parent; + LPI2C_Type *I2C; + struct rt_i2c_msg *msg; + rt_uint32_t msg_cnt; + volatile rt_uint32_t msg_ptr; + volatile rt_uint32_t dptr; + char *device_name; +}; + +#endif + From 2545c3854ea82b6d93dc8be7c1fffb4863b87498 Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Sat, 7 Apr 2018 00:37:44 +0800 Subject: [PATCH 19/67] [Tools] add IAR get version support --- tools/iar.py | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/tools/iar.py b/tools/iar.py index b5a012e4c5..09271ba4eb 100644 --- a/tools/iar.py +++ b/tools/iar.py @@ -156,3 +156,38 @@ def IARProject(target, script): out.close() IARWorkspace(target) + +def IARVersion(): + import subprocess + import re + + def IARPath(): + import rtconfig + + # set environ + old_environ = os.environ + os.environ['RTT_CC'] = 'iar' + reload(rtconfig) + + # get iar path + path = rtconfig.EXEC_PATH + + # restore environ + os.environ = old_environ + reload(rtconfig) + + return path + + path = IARPath(); + + if os.path.exists(path): + cmd = os.path.join(path, 'iccarm.exe') + else: + print('Get IAR version error. Please update IAR installation path in rtconfig.h!') + return "0.0" + + child = subprocess.Popen([cmd, '--version'], stdout=subprocess.PIPE, stderr=subprocess.PIPE, shell=True) + stdout, stderr = child.communicate() + + # example stdout: IAR ANSI C/C++ Compiler V8.20.1.14183/W32 for ARM + return re.search('[\d\.]+', stdout).group(0) \ No newline at end of file From 570627b72f75cb39fbb602143f8edc9146e0507c Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Sat, 7 Apr 2018 00:43:28 +0800 Subject: [PATCH 20/67] [Libc][dlib] Auto remove macro _DLIB_THREAD_SUPPORT when IAR version higher than 8.20.1 --- components/libc/compilers/dlib/SConscript | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/components/libc/compilers/dlib/SConscript b/components/libc/compilers/dlib/SConscript index 8ae7484894..47fa8de83d 100644 --- a/components/libc/compilers/dlib/SConscript +++ b/components/libc/compilers/dlib/SConscript @@ -1,4 +1,7 @@ from building import * +from distutils.version import LooseVersion +from iar import IARVersion + Import('rtconfig') src = Glob('*.c') @@ -11,7 +14,10 @@ CPPDEFINES = ['RT_USING_DLIBC'] if rtconfig.PLATFORM == 'iar': if GetDepend('RT_USING_DFS'): - CPPDEFINES = CPPDEFINES + ['_DLIB_FILE_DESCRIPTOR', '_DLIB_THREAD_SUPPORT'] + CPPDEFINES = CPPDEFINES + ['_DLIB_FILE_DESCRIPTOR'] + + if LooseVersion(IARVersion()) < LooseVersion("8.20.1"): + CPPDEFINES = CPPDEFINES + ['_DLIB_THREAD_SUPPORT'] group = DefineGroup('dlib', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) From cd39c2525a8e014d14bba71a526da69eefc2248a Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Sat, 7 Apr 2018 15:43:45 +0800 Subject: [PATCH 21/67] [bsp] support get compiler path by environment variables for IAR --- bsp/CME_M7/rtconfig.py | 6 +++--- bsp/asm9260t/rtconfig.py | 6 +++--- bsp/at91sam9260/rtconfig.py | 6 +++--- bsp/imxrt1052-evk/rtconfig.py | 6 +++--- bsp/lpc176x/rtconfig.py | 6 +++--- bsp/lpc43xx/M0/rtconfig.py | 6 +++--- bsp/lpc43xx/M4/rtconfig.py | 6 +++--- bsp/lpc824/rtconfig.py | 6 +++--- bsp/m16c62p/rtconfig.py | 16 ++++++++-------- bsp/mb9bf500r/rtconfig.py | 8 ++++---- bsp/mb9bf506r/rtconfig.py | 8 ++++---- bsp/mb9bf618s/rtconfig.py | 8 ++++---- bsp/nuvoton_m05x/rtconfig.py | 4 ++-- bsp/nuvoton_m451/rtconfig.py | 4 ++-- bsp/nuvoton_nuc472/rtconfig.py | 6 +++--- bsp/nv32f100x/rtconfig.py | 4 ++-- bsp/stm32f0x/rtconfig.py | 4 ++-- bsp/stm32f107/rtconfig.py | 6 +++--- bsp/stm32f10x-HAL/rtconfig.py | 6 +++--- bsp/stm32f10x/rtconfig.py | 6 +++--- bsp/stm32f20x/rtconfig.py | 6 +++--- bsp/stm32f40x/rtconfig.py | 4 ++-- bsp/stm32f411-nucleo/rtconfig.py | 6 +++--- bsp/stm32f429-armfly/rtconfig.py | 4 ++-- bsp/stm32f429-disco/rtconfig.py | 4 ++-- bsp/stm32f4xx-HAL/rtconfig.py | 6 +++--- bsp/stm32f7-disco/rtconfig.py | 6 +++--- bsp/stm32h743-nucleo/rtconfig.py | 6 +++--- bsp/stm32l072/rtconfig.py | 4 ++-- bsp/stm32l475-iot-disco/rtconfig.py | 4 ++-- bsp/stm32l476-nucleo/rtconfig.py | 4 ++-- bsp/upd70f3454/rtconfig.py | 18 +++++++++--------- bsp/xplorer4330/M0/rtconfig.py | 6 +++--- bsp/xplorer4330/M4/rtconfig.py | 6 +++--- 34 files changed, 106 insertions(+), 106 deletions(-) diff --git a/bsp/CME_M7/rtconfig.py b/bsp/CME_M7/rtconfig.py index ebaa7dc334..134ef61559 100644 --- a/bsp/CME_M7/rtconfig.py +++ b/bsp/CME_M7/rtconfig.py @@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -106,7 +106,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' AFLAGS = '' @@ -120,5 +120,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --semihosting' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/asm9260t/rtconfig.py b/bsp/asm9260t/rtconfig.py index 2a7b809133..5b58a675e3 100644 --- a/bsp/asm9260t/rtconfig.py +++ b/bsp/asm9260t/rtconfig.py @@ -17,7 +17,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -113,7 +113,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --endian=little' CFLAGS += ' -e' CFLAGS += ' --fpu=none' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' --silent' AFLAGS = '--cpu '+ DEVICE @@ -135,5 +135,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --map ' + MAP_FILE LFLAGS += ' --silent' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --silent --bin $TARGET ' + TARGET_NAME diff --git a/bsp/at91sam9260/rtconfig.py b/bsp/at91sam9260/rtconfig.py index fe64534a71..2ebf071443 100755 --- a/bsp/at91sam9260/rtconfig.py +++ b/bsp/at91sam9260/rtconfig.py @@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -111,7 +111,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --endian=little' CFLAGS += ' -e' CFLAGS += ' --fpu=none' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' --silent' AFLAGS = '--cpu '+ DEVICE @@ -133,5 +133,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --map ' + MAP_FILE LFLAGS += ' --silent' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --silent --bin $TARGET ' + TARGET_NAME diff --git a/bsp/imxrt1052-evk/rtconfig.py b/bsp/imxrt1052-evk/rtconfig.py index ac2a0df885..5b0695c67e 100644 --- a/bsp/imxrt1052-evk/rtconfig.py +++ b/bsp/imxrt1052-evk/rtconfig.py @@ -18,7 +18,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -121,7 +121,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M7' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -137,5 +137,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/lpc176x/rtconfig.py b/bsp/lpc176x/rtconfig.py index b999555a09..6ea5b5c8a4 100644 --- a/bsp/lpc176x/rtconfig.py +++ b/bsp/lpc176x/rtconfig.py @@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -105,7 +105,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -120,6 +120,6 @@ elif PLATFORM == 'iar': LFLAGS += ' --semihosting' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' RT_USING_MINILIBC = False POST_ACTION = '' diff --git a/bsp/lpc43xx/M0/rtconfig.py b/bsp/lpc43xx/M0/rtconfig.py index e998c27fe1..e577355e83 100644 --- a/bsp/lpc43xx/M0/rtconfig.py +++ b/bsp/lpc43xx/M0/rtconfig.py @@ -25,7 +25,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'D:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -113,7 +113,7 @@ elif PLATFORM == 'iar': else: CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -132,5 +132,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/lpc43xx/M4/rtconfig.py b/bsp/lpc43xx/M4/rtconfig.py index 6f35501fdc..226c6e2cc5 100644 --- a/bsp/lpc43xx/M4/rtconfig.py +++ b/bsp/lpc43xx/M4/rtconfig.py @@ -29,7 +29,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'D:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -117,7 +117,7 @@ elif PLATFORM == 'iar': else: CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -136,5 +136,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/lpc824/rtconfig.py b/bsp/lpc824/rtconfig.py index 70a75bffd7..1d130785ce 100644 --- a/bsp/lpc824/rtconfig.py +++ b/bsp/lpc824/rtconfig.py @@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -105,7 +105,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -121,5 +121,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/m16c62p/rtconfig.py b/bsp/m16c62p/rtconfig.py index 5fb198af6c..0e800d3532 100644 --- a/bsp/m16c62p/rtconfig.py +++ b/bsp/m16c62p/rtconfig.py @@ -14,7 +14,7 @@ if CROSS_TOOL == 'gcc': EXEC_PATH = 'C:/Program Files/Renesas/Hew/Tools/KPIT Cummins/GNUM16CM32C-ELF/v11.01/m32c-elf/bin' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0' # EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0' elif CROSS_TOOL == 'keil': print('================ERROR============================') @@ -65,16 +65,14 @@ elif PLATFORM == 'iar': DEVICE = '--cpu M16C' - EXEC_PATH = IAR_PATH + '/m16c/bin' - AFLAGS = '-s+' # AFLAGS += ' -M<>' AFLAGS += ' -w+' AFLAGS += ' -r' - AFLAGS += ' -I"' + IAR_PATH + '/m16c/INC"' + AFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC"' LFLAGS = '-xms' - LFLAGS += ' -I"' + IAR_PATH + '/m16c/LIB"' + LFLAGS += ' -I"' + EXEC_PATH + '/m16c/LIB"' LFLAGS += ' -rt' LFLAGS += ' -s __program_start' LFLAGS += ' -D_CSTACK_SIZE=80' @@ -82,7 +80,7 @@ elif PLATFORM == 'iar': LFLAGS += ' -D_DATA16_HEAP_SIZE=1000' LFLAGS += ' -D_FAR_HEAP_SIZE=400' LFLAGS += ' -D_DATA20_HEAP_SIZE=400' - LFLAGS += ' "' + IAR_PATH + '/m16c/LIB/CLIB/clm16cfnffwc.r34"' + LFLAGS += ' "' + EXEC_PATH + '/m16c/LIB/CLIB/clm16cfnffwc.r34"' LFLAGS += ' -e_small_write=_formatted_write' LFLAGS += ' -e_medium_read=_formatted_read' @@ -95,13 +93,15 @@ elif PLATFORM == 'iar': CFLAGS += ' --debug' CFLAGS += ' -e' CFLAGS += ' --align_func 1' - CFLAGS += ' -I"' + IAR_PATH + '/m16c/INC"' - CFLAGS += ' -I"' + IAR_PATH + '/m16c/INC/CLIB"' + CFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC"' + CFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC/CLIB"' CFLAGS += ' -Ol' CFLAGS += ' --no_cse' CFLAGS += ' --no_unroll' CFLAGS += ' --no_inline' CFLAGS += ' --no_code_motion' CFLAGS += ' --no_tbaa' + + EXEC_PATH = EXEC_PATH + '/m16c/bin' POST_ACTION = '' diff --git a/bsp/mb9bf500r/rtconfig.py b/bsp/mb9bf500r/rtconfig.py index f194c68386..8b325ab1fc 100644 --- a/bsp/mb9bf500r/rtconfig.py +++ b/bsp/mb9bf500r/rtconfig.py @@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -102,7 +102,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -112,11 +112,11 @@ elif PLATFORM == 'iar': AFLAGS += ' -r' AFLAGS += ' --cpu Cortex-M3' AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' + AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' LFLAGS = ' --config mb9bf500r.icf' LFLAGS += ' --semihosting' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf506r/rtconfig.py b/bsp/mb9bf506r/rtconfig.py index ac4859e91c..d8b525f291 100644 --- a/bsp/mb9bf506r/rtconfig.py +++ b/bsp/mb9bf506r/rtconfig.py @@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -101,7 +101,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -111,11 +111,11 @@ elif PLATFORM == 'iar': AFLAGS += ' -r' AFLAGS += ' --cpu Cortex-M3' AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' + AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' LFLAGS = ' --config rtthread-mb9bf506.icf' LFLAGS += ' --semihosting' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf618s/rtconfig.py b/bsp/mb9bf618s/rtconfig.py index 9bb51b95f9..474ff3dd57 100644 --- a/bsp/mb9bf618s/rtconfig.py +++ b/bsp/mb9bf618s/rtconfig.py @@ -24,7 +24,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'E:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' + EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -106,7 +106,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -116,11 +116,11 @@ elif PLATFORM == 'iar': AFLAGS += ' -r' AFLAGS += ' --cpu Cortex-M3' AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' + AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' LFLAGS = ' --config rtthread-fm3.icf' LFLAGS += ' --semihosting' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/nuvoton_m05x/rtconfig.py b/bsp/nuvoton_m05x/rtconfig.py index f136d42a93..bc4cad07d1 100644 --- a/bsp/nuvoton_m05x/rtconfig.py +++ b/bsp/nuvoton_m05x/rtconfig.py @@ -103,7 +103,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -119,5 +119,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/nuvoton_m451/rtconfig.py b/bsp/nuvoton_m451/rtconfig.py index 799aa803d4..de3eeb61d1 100644 --- a/bsp/nuvoton_m451/rtconfig.py +++ b/bsp/nuvoton_m451/rtconfig.py @@ -105,7 +105,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -121,5 +121,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/nuvoton_nuc472/rtconfig.py b/bsp/nuvoton_nuc472/rtconfig.py index 291a90f26b..f37ab79b7a 100644 --- a/bsp/nuvoton_nuc472/rtconfig.py +++ b/bsp/nuvoton_nuc472/rtconfig.py @@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:\Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -105,7 +105,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -121,5 +121,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/nv32f100x/rtconfig.py b/bsp/nv32f100x/rtconfig.py index 2306ae23f6..b2c7d0fdc6 100644 --- a/bsp/nv32f100x/rtconfig.py +++ b/bsp/nv32f100x/rtconfig.py @@ -106,7 +106,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -122,5 +122,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f0x/rtconfig.py b/bsp/stm32f0x/rtconfig.py index 9de2ab0f81..ca4bedb0c7 100644 --- a/bsp/stm32f0x/rtconfig.py +++ b/bsp/stm32f0x/rtconfig.py @@ -107,7 +107,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -123,5 +123,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f107/rtconfig.py b/bsp/stm32f107/rtconfig.py index 9fb35a9d8b..599152138e 100644 --- a/bsp/stm32f107/rtconfig.py +++ b/bsp/stm32f107/rtconfig.py @@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -105,7 +105,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' AFLAGS = '' @@ -118,5 +118,5 @@ elif PLATFORM == 'iar': LFLAGS = ' --config stm32_rom.icf' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f10x-HAL/rtconfig.py b/bsp/stm32f10x-HAL/rtconfig.py index ea15f07054..885eefe3fd 100644 --- a/bsp/stm32f10x-HAL/rtconfig.py +++ b/bsp/stm32f10x-HAL/rtconfig.py @@ -20,7 +20,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keilv5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -106,7 +106,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -122,5 +122,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f10x/rtconfig.py b/bsp/stm32f10x/rtconfig.py index f4d2a34a06..8801792087 100644 --- a/bsp/stm32f10x/rtconfig.py +++ b/bsp/stm32f10x/rtconfig.py @@ -31,7 +31,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -117,7 +117,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -133,5 +133,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f20x/rtconfig.py b/bsp/stm32f20x/rtconfig.py index 9d06b66a97..c0ec40f60e 100644 --- a/bsp/stm32f20x/rtconfig.py +++ b/bsp/stm32f20x/rtconfig.py @@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -101,7 +101,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M3' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' AFLAGS = '' @@ -115,5 +115,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --semihosting' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f40x/rtconfig.py b/bsp/stm32f40x/rtconfig.py index 67edfca299..4dd99457ce 100644 --- a/bsp/stm32f40x/rtconfig.py +++ b/bsp/stm32f40x/rtconfig.py @@ -106,7 +106,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -122,5 +122,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f411-nucleo/rtconfig.py b/bsp/stm32f411-nucleo/rtconfig.py index e9d8cc55f7..8bd3a4f62b 100644 --- a/bsp/stm32f411-nucleo/rtconfig.py +++ b/bsp/stm32f411-nucleo/rtconfig.py @@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -112,7 +112,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' --silent' AFLAGS = DEVICE @@ -133,5 +133,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --entry __iar_program_start' #LFLAGS += ' --silent' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' \ No newline at end of file diff --git a/bsp/stm32f429-armfly/rtconfig.py b/bsp/stm32f429-armfly/rtconfig.py index 769465e7a8..92312b2072 100644 --- a/bsp/stm32f429-armfly/rtconfig.py +++ b/bsp/stm32f429-armfly/rtconfig.py @@ -112,7 +112,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -128,5 +128,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f429-disco/rtconfig.py b/bsp/stm32f429-disco/rtconfig.py index ab2222b943..7a3c12641d 100644 --- a/bsp/stm32f429-disco/rtconfig.py +++ b/bsp/stm32f429-disco/rtconfig.py @@ -106,7 +106,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -122,5 +122,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32f4xx-HAL/rtconfig.py b/bsp/stm32f4xx-HAL/rtconfig.py index c036761317..d8de63dca7 100644 --- a/bsp/stm32f4xx-HAL/rtconfig.py +++ b/bsp/stm32f4xx-HAL/rtconfig.py @@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = 'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -112,7 +112,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' --silent' AFLAGS = DEVICE @@ -133,5 +133,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --entry __iar_program_start' #LFLAGS += ' --silent' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' \ No newline at end of file diff --git a/bsp/stm32f7-disco/rtconfig.py b/bsp/stm32f7-disco/rtconfig.py index 4fb5865f3d..94846be362 100644 --- a/bsp/stm32f7-disco/rtconfig.py +++ b/bsp/stm32f7-disco/rtconfig.py @@ -20,7 +20,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -119,7 +119,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M7' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' CFLAGS += ' --silent' @@ -140,5 +140,5 @@ elif PLATFORM == 'iar': CXXFLAGS = CFLAGS - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32h743-nucleo/rtconfig.py b/bsp/stm32h743-nucleo/rtconfig.py index ed5e8e9c25..8ef89a1258 100644 --- a/bsp/stm32h743-nucleo/rtconfig.py +++ b/bsp/stm32h743-nucleo/rtconfig.py @@ -20,7 +20,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -119,7 +119,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M7' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' CFLAGS += ' --silent' @@ -140,5 +140,5 @@ elif PLATFORM == 'iar': CXXFLAGS = CFLAGS - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32l072/rtconfig.py b/bsp/stm32l072/rtconfig.py index ca72477a93..96a398fc92 100644 --- a/bsp/stm32l072/rtconfig.py +++ b/bsp/stm32l072/rtconfig.py @@ -108,7 +108,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -124,5 +124,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32l475-iot-disco/rtconfig.py b/bsp/stm32l475-iot-disco/rtconfig.py index 769465e7a8..92312b2072 100644 --- a/bsp/stm32l475-iot-disco/rtconfig.py +++ b/bsp/stm32l475-iot-disco/rtconfig.py @@ -112,7 +112,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -128,5 +128,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/stm32l476-nucleo/rtconfig.py b/bsp/stm32l476-nucleo/rtconfig.py index b0c519ef3e..24b65fb7ce 100644 --- a/bsp/stm32l476-nucleo/rtconfig.py +++ b/bsp/stm32l476-nucleo/rtconfig.py @@ -112,7 +112,7 @@ elif PLATFORM == 'iar': CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -128,5 +128,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/upd70f3454/rtconfig.py b/bsp/upd70f3454/rtconfig.py index e25c81cfc7..2dec4b39ec 100644 --- a/bsp/upd70f3454/rtconfig.py +++ b/bsp/upd70f3454/rtconfig.py @@ -16,7 +16,7 @@ if CROSS_TOOL == 'gcc': exit(0) elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation_0' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation_0' elif CROSS_TOOL == 'keil': print('================ERROR============================') print('Not support keil yet!') @@ -66,8 +66,6 @@ elif PLATFORM == 'iar': DEVICE = '--cpu V850' - EXEC_PATH = IAR_PATH + '/v850/bin' - AFLAGS = '-s+' AFLAGS = ' -v1' # AFLAGS += ' -M<>' @@ -76,17 +74,17 @@ elif PLATFORM == 'iar': AFLAGS += ' -DDATA_MODEL_TINY' AFLAGS += ' -w+' AFLAGS += ' -r' - AFLAGS += ' -I"' + IAR_PATH + '/v850/INC"' + AFLAGS += ' -I"' + EXEC_PATH + '/v850/INC"' LFLAGS = '-xms' - LFLAGS += ' -I"' + IAR_PATH + '/v850/LIB"' + LFLAGS += ' -I"' + EXEC_PATH + '/v850/LIB"' LFLAGS += ' -rt' LFLAGS += ' -s __program_start' LFLAGS += ' -D_CSTACK_SIZE=1000' - LFLAGS += ' "' + IAR_PATH + '/v850/LIB/dl85nn1.r85"' + LFLAGS += ' "' + EXEC_PATH + '/v850/LIB/dl85nn1.r85"' LFLAGS += ' -D_HEAP_SIZE=0' -# LFLAGS += ' "' + IAR_PATH + '/v850/lib/CLIB/clm16cfnffwc.r34"' +# LFLAGS += ' "' + EXEC_PATH + '/v850/lib/CLIB/clm16cfnffwc.r34"' # LFLAGS += ' -e_small_write=_formatted_write' # LFLAGS += ' -e_medium_read=_formatted_read' @@ -99,13 +97,15 @@ elif PLATFORM == 'iar': CFLAGS += ' --no_unroll' CFLAGS += ' --no_inline' CFLAGS += ' --no_code_motion' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/v850/LIB/dl85nn1.h"' - CFLAGS += ' -I"' + IAR_PATH + '/v850/INC"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/v850/LIB/dl85nn1.h"' + CFLAGS += ' -I"' + EXEC_PATH + '/v850/INC"' CFLAGS += ' --no_tbaa' CFLAGS += ' --debug' CFLAGS += ' --lock_regs 0' CFLAGS += ' --migration_preprocessor_extensions' CFLAGS += ' -e' CFLAGS += ' -Ol' + + EXEC_PATH = EXEC_PATH + '/v850/bin' POST_ACTION = '' diff --git a/bsp/xplorer4330/M0/rtconfig.py b/bsp/xplorer4330/M0/rtconfig.py index 5eef1d3ab8..6902581132 100644 --- a/bsp/xplorer4330/M0/rtconfig.py +++ b/bsp/xplorer4330/M0/rtconfig.py @@ -29,7 +29,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'D:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -116,7 +116,7 @@ elif PLATFORM == 'iar': else: CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -135,5 +135,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' diff --git a/bsp/xplorer4330/M4/rtconfig.py b/bsp/xplorer4330/M4/rtconfig.py index b19c390160..465f12eb0a 100644 --- a/bsp/xplorer4330/M4/rtconfig.py +++ b/bsp/xplorer4330/M4/rtconfig.py @@ -29,7 +29,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'D:/Keil' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -116,7 +116,7 @@ elif PLATFORM == 'iar': else: CFLAGS += ' --cpu=Cortex-M0' CFLAGS += ' -e' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' -Ol' CFLAGS += ' --use_c++_inline' @@ -135,5 +135,5 @@ elif PLATFORM == 'iar': LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = IAR_PATH + '/arm/bin/' + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = '' From 0d1f75453bb42917841b7e741abe05403f4d4b89 Mon Sep 17 00:00:00 2001 From: aozima Date: Sat, 7 Apr 2018 17:14:12 +0800 Subject: [PATCH 22/67] update scons script: strict SrcRemove() match rule. --- tools/building.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tools/building.py b/tools/building.py index 42cb37dc4f..990e57edcd 100644 --- a/tools/building.py +++ b/tools/building.py @@ -743,11 +743,20 @@ def SrcRemove(src, remove): for item in src: if type(item) == type('str'): - if os.path.basename(item) in remove: + item_str = item + else: + item_str = item.rstr() + + if os.path.isabs(item_str): + item_str = os.path.relpath(item_str, GetCurrentDir()) + + if type(remove) == type('str'): + if item_str == remove: src.remove(item) else: - if os.path.basename(item.rstr()) in remove: - src.remove(item) + for remove_item in remove: + if item_str == str(remove_item): + src.remove(item) def GetVersion(): import SCons.cpp From 1ff8d7339bf468f2385de0c122df5a5bb27dda52 Mon Sep 17 00:00:00 2001 From: aozima Date: Sun, 8 Apr 2018 10:24:06 +0800 Subject: [PATCH 23/67] [bsp] [sam7x]: fix SConscript spelling error. --- bsp/sam7x/drivers/SConscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/sam7x/drivers/SConscript b/bsp/sam7x/drivers/SConscript index 466c472cd8..df0abc5435 100644 --- a/bsp/sam7x/drivers/SConscript +++ b/bsp/sam7x/drivers/SConscript @@ -7,7 +7,7 @@ src = Glob('*.c') if GetDepend('RT_USING_LWIP') == False: SrcRemove(src, 'sam7x_emac.c') if GetDepend('RT_USING_DFS') == False: - SrcRemove(src, 'ssd.c') + SrcRemove(src, 'sd.c') CPPPATH = [cwd] From ae1536b2a0bec188a95d1ed40d50a921ddfa29ea Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Sun, 8 Apr 2018 17:16:49 +0800 Subject: [PATCH 24/67] [bsp][imxrt1052-evk] update eth driver - fixed eth send frame bug - code clean --- .../Libraries/drivers/fsl_enet.c | 8 +- bsp/imxrt1052-evk/drivers/drv_eth.c | 629 +++++++++--------- 2 files changed, 331 insertions(+), 306 deletions(-) diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c index 2e7e002425..0ef887400a 100644 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c +++ b/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c @@ -1345,7 +1345,13 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d #else address = (uint32_t)curBuffDescrip->buffer; #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data, length); + + { + // Change SDK to reduce memory copy + extern void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len); + pbuf2mem(data, (void *)address, length); + } + //memcpy((void *)address, data, length); /* Set data length. */ curBuffDescrip->length = length; #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE diff --git a/bsp/imxrt1052-evk/drivers/drv_eth.c b/bsp/imxrt1052-evk/drivers/drv_eth.c index 3bd9cdcc72..812adbd748 100644 --- a/bsp/imxrt1052-evk/drivers/drv_eth.c +++ b/bsp/imxrt1052-evk/drivers/drv_eth.c @@ -16,7 +16,7 @@ #include #ifdef RT_USING_FINSH -#include + #include #endif #include "fsl_enet.h" @@ -50,13 +50,13 @@ struct rt_imxrt_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; enet_handle_t enet_handle; ENET_Type *enet_base; enet_data_error_stats_t error_statistic; - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ rt_bool_t tx_is_waiting; struct rt_semaphore tx_wait; @@ -73,18 +73,18 @@ ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_ static struct rt_imxrt_eth imxrt_eth_device; -void _enet_rx_callback(struct rt_imxrt_eth * eth) +void _enet_rx_callback(struct rt_imxrt_eth *eth) { rt_err_t result; ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt); result = eth_device_ready(&(eth->parent)); - if( result != RT_EOK ) - rt_kprintf("RX err =%d\n", result ); + if (result != RT_EOK) + rt_kprintf("RX err =%d\n", result); } -void _enet_tx_callback(struct rt_imxrt_eth * eth) +void _enet_tx_callback(struct rt_imxrt_eth *eth) { if (eth->tx_is_waiting == RT_TRUE) { @@ -95,7 +95,7 @@ void _enet_tx_callback(struct rt_imxrt_eth * eth) void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) { - switch(event) + switch (event) { case kENET_RxEvent: @@ -130,53 +130,53 @@ void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, static void _enet_io_init(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled @@ -184,9 +184,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled @@ -194,9 +194,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: R0/6 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled @@ -204,9 +204,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Keeper Pull Up / Down Config. Field: 100K Ohm Pull Down Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: R0/6 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled @@ -214,9 +214,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Keeper Pull Up / Down Config. Field: 100K Ohm Pull Down Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -224,9 +224,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -234,9 +234,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -244,9 +244,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -254,9 +254,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -264,9 +264,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -274,9 +274,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x31u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/6 Speed Field: low(50MHz) Open Drain Enable Field: Open Drain Disabled @@ -284,9 +284,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Keeper Pull Up / Down Config. Field: 100K Ohm Pull Down Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -294,9 +294,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -304,9 +304,9 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ - 0xB829u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: low(50MHz) Open Drain Enable Field: Open Drain Enabled @@ -314,8 +314,6 @@ static void _enet_io_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - - } static void _enet_clk_init(void) @@ -353,7 +351,8 @@ static void _enet_config(void) uint32_t sysClock; /* prepare the buffer configuration. */ - enet_buffer_config_t buffConfig = { + enet_buffer_config_t buffConfig = + { ENET_RXBD_NUM, ENET_TXBD_NUM, SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), @@ -390,6 +389,43 @@ static void _enet_config(void) ENET_ActiveRead(imxrt_eth_device.enet_base); } +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +static void packet_dump(const char *msg, const struct pbuf *p) +{ + const struct pbuf *q; + rt_uint32_t i, j; + rt_uint8_t *ptr; + + rt_kprintf("%s %d byte\n", msg, p->tot_len); + + i = 0; + for (q = p; q != RT_NULL; q = q->next) + { + ptr = q->payload; + + for (j = 0; j < q->len; j++) + { + if ((i % 8) == 0) + { + rt_kprintf(" "); + } + if ((i % 16) == 0) + { + rt_kprintf("\r\n"); + } + rt_kprintf("%02x ", *ptr); + + i++; + ptr++; + } + } + + rt_kprintf("\n\n"); +} +#else +#define packet_dump(...) +#endif /* dump */ + /* initialize the interface */ static rt_err_t rt_imxrt_eth_init(rt_device_t dev) { @@ -402,127 +438,112 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev) static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) { dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n"); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_imxrt_eth_close(rt_device_t dev) { dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n"); - return RT_EOK; + return RT_EOK; } -static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) { dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n"); - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } -static rt_size_t rt_imxrt_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n"); - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) { dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n"); - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /* ethernet device interface */ /* transmit packet. */ -rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p) +rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) { rt_err_t result = RT_EOK; enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; - RT_ASSERT(p != NULL); + RT_ASSERT(p != NULL); RT_ASSERT(enet_handle != RT_NULL); - dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len); + dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len); #ifdef ETH_TX_DUMP - { - int i; - uint8_t * buf; - buf = (uint8_t *)p->payload; - for (i = 0; i < p->len; i++) - { - dbg_log(DBG_LOG, "%02X ", buf[i]); - if (i % 16 == 15) - dbg_log(DBG_LOG, "\n"); - } - dbg_log(DBG_LOG, "\n"); - } + packet_dump("send", p); #endif - do - { - result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, p->payload, p->len); + do + { + result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len); - if (result == kStatus_ENET_TxFrameBusy) - { - rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); - } + if (result == kStatus_ENET_TxFrameBusy) + { + imxrt_eth_device.tx_is_waiting = RT_TRUE; + rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); + } - } while (result == kStatus_ENET_TxFrameBusy); + } + while (result == kStatus_ENET_TxFrameBusy); - return RT_EOK; + return RT_EOK; +} + +void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len) +{ + pbuf_copy_partial((const struct pbuf *)data, dataptr, len, 0); } /* reception packet. */ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) { - uint32_t length = 0; - status_t status; + uint32_t length = 0; + status_t status; - struct pbuf* p = RT_NULL; - enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; + struct pbuf *p = RT_NULL; + enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle; ENET_Type *enet_base = imxrt_eth_device.enet_base; enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; - /* Get the Frame size */ - status = ENET_GetRxFrameSize(enet_handle, &length); + /* Get the Frame size */ + status = ENET_GetRxFrameSize(enet_handle, &length); - /* Call ENET_ReadFrame when there is a received frame. */ - if (length != 0) - { - /* Received valid frame. Deliver the rx buffer with the size equal to length. */ - p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); + /* Call ENET_ReadFrame when there is a received frame. */ + if (length != 0) + { + /* Received valid frame. Deliver the rx buffer with the size equal to length. */ + p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); if (p != NULL) { status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); if (status == kStatus_Success) { - #ifdef ETH_RX_DUMP - uint8_t *buf; - int i; - - ETH_PRINTF("A frame received. the length:%d\n", p->len); - buf = (uint8_t *)p->payload; - for (i = 0; i < p->len; i++) - { - dbg_log(DBG_LOG, "%02X ", buf[i]); - if (i % 16 == 15) - dbg_log(DBG_LOG, "\n"); - } - dbg_log(DBG_LOG, "\n"); - #endif +#ifdef ETH_RX_DUMP + packet_dump("recv", p); +#endif return p; } else @@ -535,16 +556,16 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) { dbg_log(DBG_LOG, " pbuf_alloc faild\n"); } - } - else if (status == kStatus_ENET_RxFrameError) - { - dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); - /* Update the received buffer when error happened. */ - /* Get the error information of the received g_frame. */ - ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); - /* update the receive buffer. */ - ENET_ReadFrame(enet_base, enet_handle, NULL, 0); - } + } + else if (status == kStatus_ENET_RxFrameError) + { + dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); + /* Update the received buffer when error happened. */ + /* Get the error information of the received g_frame. */ + ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); + /* update the receive buffer. */ + ENET_ReadFrame(enet_base, enet_handle, NULL, 0); + } ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); return NULL; @@ -552,29 +573,28 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) static void phy_monitor_thread_entry(void *parameter) { - phy_speed_t speed; phy_duplex_t duplex; bool link = false; - + _enet_phy_reset_by_gpio(); PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); - + while (1) { bool new_link = false; status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); - + if ((status == kStatus_Success) && (link != new_link)) { link = new_link; - + if (link) // link up { - PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, + PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, PHY_ADDRESS, &speed, &duplex); - + if (kPHY_Speed10M == speed) { dbg_log(DBG_LOG, "10M\n"); @@ -583,7 +603,7 @@ static void phy_monitor_thread_entry(void *parameter) { dbg_log(DBG_LOG, "100M\n"); } - + if (kPHY_HalfDuplex == duplex) { dbg_log(DBG_LOG, "half dumplex\n"); @@ -592,13 +612,13 @@ static void phy_monitor_thread_entry(void *parameter) { dbg_log(DBG_LOG, "full dumplex\n"); } - - if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) - || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) + + if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) + || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) { - imxrt_eth_device.speed = (enet_mii_speed_t)speed; + imxrt_eth_device.speed = (enet_mii_speed_t)speed; imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; - + dbg_log(DBG_LOG, "link up, and update eth mode.\n"); rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); } @@ -615,7 +635,7 @@ static void phy_monitor_thread_entry(void *parameter) eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); } } - + rt_thread_delay(RT_TICK_PER_SECOND * 2); } } @@ -626,17 +646,17 @@ static int rt_hw_imxrt_eth_init(void) _enet_io_init(); _enet_clk_init(); - + /* OUI 00-80-E1 STMICROELECTRONICS. */ imxrt_eth_device.dev_addr[0] = 0x00; - imxrt_eth_device.dev_addr[1] = 0x80; - imxrt_eth_device.dev_addr[2] = 0xE1; + imxrt_eth_device.dev_addr[1] = 0x04; + imxrt_eth_device.dev_addr[2] = 0x9F; /* generate MAC addr from 96bit unique ID (only for test). */ - imxrt_eth_device.dev_addr[3] = 0x12; - imxrt_eth_device.dev_addr[4] = 0x34; - imxrt_eth_device.dev_addr[5] = 0x56; - - imxrt_eth_device.speed = kENET_MiiSpeed100M; + imxrt_eth_device.dev_addr[3] = 0x05; + imxrt_eth_device.dev_addr[4] = 0x44; + imxrt_eth_device.dev_addr[5] = 0xE5; + + imxrt_eth_device.speed = kENET_MiiSpeed100M; imxrt_eth_device.duplex = kENET_MiiFullDuplex; imxrt_eth_device.enet_base = ENET; @@ -667,9 +687,9 @@ static int rt_hw_imxrt_eth_init(void) { dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state); } - + eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); - + /* start phy monitor */ { rt_thread_t tid; @@ -682,7 +702,7 @@ static int rt_hw_imxrt_eth_init(void) if (tid != RT_NULL) rt_thread_startup(tid); } - + return state; } INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); @@ -756,102 +776,102 @@ void enet_reg_dump(void) #define DUMP_REG(__REG) \ rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG) - DUMP_REG(EIR); - DUMP_REG(EIMR); - DUMP_REG(RDAR); - DUMP_REG(TDAR); - DUMP_REG(ECR); - DUMP_REG(MMFR); - DUMP_REG(MSCR); - DUMP_REG(MIBC); - DUMP_REG(RCR); - DUMP_REG(TCR); - DUMP_REG(PALR); - DUMP_REG(PAUR); - DUMP_REG(OPD); - DUMP_REG(TXIC); - DUMP_REG(RXIC); - DUMP_REG(IAUR); - DUMP_REG(IALR); - DUMP_REG(GAUR); - DUMP_REG(GALR); - DUMP_REG(TFWR); - DUMP_REG(RDSR); - DUMP_REG(TDSR); - DUMP_REG(MRBR); - DUMP_REG(RSFL); - DUMP_REG(RSEM); - DUMP_REG(RAEM); - DUMP_REG(RAFL); - DUMP_REG(TSEM); - DUMP_REG(TAEM); - DUMP_REG(TAFL); - DUMP_REG(TIPG); - DUMP_REG(FTRL); - DUMP_REG(TACC); - DUMP_REG(RACC); - DUMP_REG(RMON_T_DROP); - DUMP_REG(RMON_T_PACKETS); - DUMP_REG(RMON_T_BC_PKT); - DUMP_REG(RMON_T_MC_PKT); - DUMP_REG(RMON_T_CRC_ALIGN); - DUMP_REG(RMON_T_UNDERSIZE); - DUMP_REG(RMON_T_OVERSIZE); - DUMP_REG(RMON_T_FRAG); - DUMP_REG(RMON_T_JAB); - DUMP_REG(RMON_T_COL); - DUMP_REG(RMON_T_P64); - DUMP_REG(RMON_T_P65TO127); - DUMP_REG(RMON_T_P128TO255); - DUMP_REG(RMON_T_P256TO511); - DUMP_REG(RMON_T_P512TO1023); - DUMP_REG(RMON_T_P1024TO2047); - DUMP_REG(RMON_T_P_GTE2048); - DUMP_REG(RMON_T_OCTETS); - DUMP_REG(IEEE_T_DROP); - DUMP_REG(IEEE_T_FRAME_OK); - DUMP_REG(IEEE_T_1COL); - DUMP_REG(IEEE_T_MCOL); - DUMP_REG(IEEE_T_DEF); - DUMP_REG(IEEE_T_LCOL); - DUMP_REG(IEEE_T_EXCOL); - DUMP_REG(IEEE_T_MACERR); - DUMP_REG(IEEE_T_CSERR); - DUMP_REG(IEEE_T_SQE); - DUMP_REG(IEEE_T_FDXFC); - DUMP_REG(IEEE_T_OCTETS_OK); - DUMP_REG(RMON_R_PACKETS); - DUMP_REG(RMON_R_BC_PKT); - DUMP_REG(RMON_R_MC_PKT); - DUMP_REG(RMON_R_CRC_ALIGN); - DUMP_REG(RMON_R_UNDERSIZE); - DUMP_REG(RMON_R_OVERSIZE); - DUMP_REG(RMON_R_FRAG); - DUMP_REG(RMON_R_JAB); - DUMP_REG(RMON_R_RESVD_0); - DUMP_REG(RMON_R_P64); - DUMP_REG(RMON_R_P65TO127); - DUMP_REG(RMON_R_P128TO255); - DUMP_REG(RMON_R_P256TO511); - DUMP_REG(RMON_R_P512TO1023); - DUMP_REG(RMON_R_P1024TO2047); - DUMP_REG(RMON_R_P_GTE2048); - DUMP_REG(RMON_R_OCTETS); - DUMP_REG(IEEE_R_DROP); - DUMP_REG(IEEE_R_FRAME_OK); - DUMP_REG(IEEE_R_CRC); - DUMP_REG(IEEE_R_ALIGN); - DUMP_REG(IEEE_R_MACERR); - DUMP_REG(IEEE_R_FDXFC); - DUMP_REG(IEEE_R_OCTETS_OK); - DUMP_REG(ATCR); - DUMP_REG(ATVR); - DUMP_REG(ATOFF); - DUMP_REG(ATPER); - DUMP_REG(ATCOR); - DUMP_REG(ATINC); - DUMP_REG(ATSTMP); - DUMP_REG(TGSR); + DUMP_REG(EIR); + DUMP_REG(EIMR); + DUMP_REG(RDAR); + DUMP_REG(TDAR); + DUMP_REG(ECR); + DUMP_REG(MMFR); + DUMP_REG(MSCR); + DUMP_REG(MIBC); + DUMP_REG(RCR); + DUMP_REG(TCR); + DUMP_REG(PALR); + DUMP_REG(PAUR); + DUMP_REG(OPD); + DUMP_REG(TXIC); + DUMP_REG(RXIC); + DUMP_REG(IAUR); + DUMP_REG(IALR); + DUMP_REG(GAUR); + DUMP_REG(GALR); + DUMP_REG(TFWR); + DUMP_REG(RDSR); + DUMP_REG(TDSR); + DUMP_REG(MRBR); + DUMP_REG(RSFL); + DUMP_REG(RSEM); + DUMP_REG(RAEM); + DUMP_REG(RAFL); + DUMP_REG(TSEM); + DUMP_REG(TAEM); + DUMP_REG(TAFL); + DUMP_REG(TIPG); + DUMP_REG(FTRL); + DUMP_REG(TACC); + DUMP_REG(RACC); + DUMP_REG(RMON_T_DROP); + DUMP_REG(RMON_T_PACKETS); + DUMP_REG(RMON_T_BC_PKT); + DUMP_REG(RMON_T_MC_PKT); + DUMP_REG(RMON_T_CRC_ALIGN); + DUMP_REG(RMON_T_UNDERSIZE); + DUMP_REG(RMON_T_OVERSIZE); + DUMP_REG(RMON_T_FRAG); + DUMP_REG(RMON_T_JAB); + DUMP_REG(RMON_T_COL); + DUMP_REG(RMON_T_P64); + DUMP_REG(RMON_T_P65TO127); + DUMP_REG(RMON_T_P128TO255); + DUMP_REG(RMON_T_P256TO511); + DUMP_REG(RMON_T_P512TO1023); + DUMP_REG(RMON_T_P1024TO2047); + DUMP_REG(RMON_T_P_GTE2048); + DUMP_REG(RMON_T_OCTETS); + DUMP_REG(IEEE_T_DROP); + DUMP_REG(IEEE_T_FRAME_OK); + DUMP_REG(IEEE_T_1COL); + DUMP_REG(IEEE_T_MCOL); + DUMP_REG(IEEE_T_DEF); + DUMP_REG(IEEE_T_LCOL); + DUMP_REG(IEEE_T_EXCOL); + DUMP_REG(IEEE_T_MACERR); + DUMP_REG(IEEE_T_CSERR); + DUMP_REG(IEEE_T_SQE); + DUMP_REG(IEEE_T_FDXFC); + DUMP_REG(IEEE_T_OCTETS_OK); + DUMP_REG(RMON_R_PACKETS); + DUMP_REG(RMON_R_BC_PKT); + DUMP_REG(RMON_R_MC_PKT); + DUMP_REG(RMON_R_CRC_ALIGN); + DUMP_REG(RMON_R_UNDERSIZE); + DUMP_REG(RMON_R_OVERSIZE); + DUMP_REG(RMON_R_FRAG); + DUMP_REG(RMON_R_JAB); + DUMP_REG(RMON_R_RESVD_0); + DUMP_REG(RMON_R_P64); + DUMP_REG(RMON_R_P65TO127); + DUMP_REG(RMON_R_P128TO255); + DUMP_REG(RMON_R_P256TO511); + DUMP_REG(RMON_R_P512TO1023); + DUMP_REG(RMON_R_P1024TO2047); + DUMP_REG(RMON_R_P_GTE2048); + DUMP_REG(RMON_R_OCTETS); + DUMP_REG(IEEE_R_DROP); + DUMP_REG(IEEE_R_FRAME_OK); + DUMP_REG(IEEE_R_CRC); + DUMP_REG(IEEE_R_ALIGN); + DUMP_REG(IEEE_R_MACERR); + DUMP_REG(IEEE_R_FDXFC); + DUMP_REG(IEEE_R_OCTETS_OK); + DUMP_REG(ATCR); + DUMP_REG(ATVR); + DUMP_REG(ATOFF); + DUMP_REG(ATPER); + DUMP_REG(ATCOR); + DUMP_REG(ATINC); + DUMP_REG(ATSTMP); + DUMP_REG(TGSR); } void enet_nvic_tog(void) @@ -891,24 +911,23 @@ void enet_rx_stat(void) void enet_buf_info(void) { - int i = 0; for (i = 0; i < ENET_RXBD_NUM; i++) { rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", - i, - g_rxBuffDescrip[i].length, - g_rxBuffDescrip[i].control, - g_rxBuffDescrip[i].buffer); + i, + g_rxBuffDescrip[i].length, + g_rxBuffDescrip[i].control, + g_rxBuffDescrip[i].buffer); } for (i = 0; i < ENET_TXBD_NUM; i++) { rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", - i, - g_txBuffDescrip[i].length, - g_txBuffDescrip[i].control, - g_txBuffDescrip[i].buffer); + i, + g_txBuffDescrip[i].length, + g_txBuffDescrip[i].control, + g_txBuffDescrip[i].buffer); } } From 2f5a9c37fa49dbe7fbdb7d67fa992b552cf0cf37 Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Fri, 6 Apr 2018 20:35:05 +0800 Subject: [PATCH 25/67] [DeviceDriver][RTC] fixed warning when only enable finsh shell: function "date" was declared but never referenced --- components/drivers/rtc/rtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/drivers/rtc/rtc.c b/components/drivers/rtc/rtc.c index f64a528ef0..48da802627 100644 --- a/components/drivers/rtc/rtc.c +++ b/components/drivers/rtc/rtc.c @@ -247,7 +247,7 @@ FINSH_FUNCTION_EXPORT(list_date, show date and time.) FINSH_FUNCTION_EXPORT(set_date, set date. e.g: set_date(2010,2,28)) FINSH_FUNCTION_EXPORT(set_time, set time. e.g: set_time(23,59,59)) -#if defined(RT_USING_FINSH) +#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) static void date(uint8_t argc, char **argv) { if (argc == 1) @@ -308,6 +308,6 @@ static void date(uint8_t argc, char **argv) } } MSH_CMD_EXPORT(date, get date and time or set [year month day hour min sec]); -#endif /* defined(RT_USING_FINSH) */ +#endif /* defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) */ #endif /* RT_USING_FINSH */ From 48058683ffabd109939bd09f26677549a7ad9ebc Mon Sep 17 00:00:00 2001 From: liang yongxiang Date: Fri, 6 Apr 2018 20:49:47 +0800 Subject: [PATCH 26/67] [bsp][gd32450z-eval] Update project building error because of GUI engine moved to package. --- bsp/gd32450z-eval/project.ewp | 776 ++++++++++++------------------ bsp/gd32450z-eval/project.uvproj | 764 +++++++++-------------------- bsp/gd32450z-eval/project.uvprojx | 516 +++++--------------- 3 files changed, 674 insertions(+), 1382 deletions(-) diff --git a/bsp/gd32450z-eval/project.ewp b/bsp/gd32450z-eval/project.ewp index 668bf4899e..b26015f8f6 100644 --- a/bsp/gd32450z-eval/project.ewp +++ b/bsp/gd32450z-eval/project.ewp @@ -298,32 +298,28 @@