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modify the coding style and add change logs

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LYH-ux committed 2020-07-01 23:44:57 +08:00
1 parent aebdcaccbb
commit 2aaeea751e
21 files changed
+720 -1010
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bsp/tm4c123bsp/board/board.c
+21 -47
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@@ -7,51 +7,37 @@
* Date Author Notes
* 2017-07-24 Tanek the first version
* 2018-11-12 Ernest Chen modify copyright
* 2020-06-27 AHTYDHD modify to adapt in TM4C123
*/
#include <stdint.h>
#include <stdbool.h>
#include "hw_ints.h"
#include "hw_sysctl.h"
#include "hw_memmap.h"
#include "hw_types.h"
#include "fpu.h"
#include "debug.h"
#include "pin_map.h"
#include "rom.h"
#include "sysctl.h"
#include "systick.h"
#include "hw_ints.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_memmap.h"
#include "driverlib/fpu.h"
#include "driverlib/sysctl.h"
#include "driverlib/systick.h"
#include "board.h"
// Holds the system core clock, which is the system clock
// frequency supplied to the SysTick timer and the processor
// core clock.
uint32_t SystemCoreClock;
/* this function set the system clock */
void SystemCoreClockUpdate(void)
{
FPULazyStackingEnable();
//
// Set the clocking to run directly from the crystal.
//
FPULazyStackingEnable();
/* Set the clocking to run directly from the crystal. 50MHz*/
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
SYSCTL_OSC_MAIN);
SystemCoreClock = SysCtlClockGet();
SYSCTL_OSC_MAIN);
SystemCoreClock = SysCtlClockGet();
}
/* this funtion set the Systick and enable systick int */
void SysTickConfig()
{
SysTickDisable();
SysTickPeriodSet(SystemCoreClock/RT_TICK_PER_SECOND);
SysTickDisable();
SysTickPeriodSet(SystemCoreClock / RT_TICK_PER_SECOND);
SysTickIntEnable();
SysTickEnable();
SysTickEnable();
}
/**
@@ -65,44 +51,32 @@ void rt_hw_board_init()
SysTickConfig();
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
rt_hw_usart_init();
#endif
#ifdef RT_USING_PIN
rt_hw_pin_init();
rt_hw_pin_init();
#endif
#ifdef RT_USING_PWM
rt_hw_pwm_init();
rt_hw_pwm_init();
#endif
/* Call components board initial (use INIT_BOARD_EXPORT()) */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
/* set the console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
bsp/tm4c123bsp/board/board.h
+21 -16
View File
@@ -1,32 +1,40 @@
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rthw.h>
#include <rtthread.h>
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
#define TM4C123_SRAM1_START (0x20000000)
#define TM4C123_SRAM1_START (0x20000000)
#define TM4C123_SRAM1_END (TM4C123_SRAM1_START + 32 * 1024) // end address = 0x20000000(base adddress) + 32K(RAM size)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM$$ZI$$Limit; // RW_IRAM
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int _ebss;
#define HEAP_BEGIN ((void *)&_ebss)
#endif
#define HEAP_END TM4C123_SRAM1_END
#endif
#ifdef RT_USING_PIN
#include "drv_gpio.h"
#endif /* RT_USING_PIN */
#ifdef RT_USING_SERIAL
#include "drv_uart.h"
#endif /* RT_USING_SERIAL */
@@ -39,9 +47,6 @@ extern int Image$$RW_IRAM$$ZI$$Limit; // RW_IRAM
#include "drv_spi.h"
#endif /* RT_USING_SPI*/
#endif /*__BOARD_H__*/
#endif /*_BOARD_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/board/tm4c123_config.c
+56 -45
View File
@@ -1,77 +1,88 @@
#include "stdbool.h"
#include "stdint.h"
#include "hw_memmap.h"
#include "pin_map.h"
#include "sysctl.h"
#include "pwm.h"
#include "gpio.h"
#include "uart.h"
#include "adc.h"
#include "ssi.h"
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#include <rtthread.h>
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_memmap.h"
#include "driverlib/pin_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/gpio.h"
#include "tm4c123_config.h"
#ifdef RT_USING_SERIAL
#include "driverlib/uart.h"
#endif /* RT_USING_SERIAL */
#ifdef RT_USING_ADC
#include "driverlib/adc.h"
#endif /* RT_USING_ADC */
#ifdef RT_USING_PWM
#include "driverlib/pwm.h"
#endif /* RT_USING_PWM */
#ifdef RT_USING_SPI
#include "driverlib/ssi.h"
#endif /* RT_USING_SPI */
#ifdef RT_USING_SERIAL
void uart_hw_config(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
/* UART0 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
/* UART1 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC5_U1TX);
GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
}
#endif /* RT_USING_SERIAL */
void pwm_hw_config(void)
{
SysCtlPWMClockSet(SYSCTL_PWMDIV_2);
//GPIO port D needs to be enabled so these pins can be used.
SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
// Configure the GPIO pin muxing to select PWM functions for these pins.
GPIOPinConfigure(GPIO_PF2_M1PWM6);
GPIOPinConfigure(GPIO_PF3_M1PWM7);
// Configure the GPIO pad for PWM function on pins PF2 and PF3
GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2|GPIO_PIN_3);
}
#ifdef RT_USING_ADC
void adc_hw_config(void)
{
// The ADC0 peripheral must be enabled for use.
//
/* ADC0 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
// GPIO port D needs to be enabled
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
// Select the analog ADC function for these pins.
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
}
#endif /* RT_USING_ADC */
#ifdef RT_USING_PWM
void pwm_hw_config(void)
{
/* PWM7 (PWM1 module,M1PWM6 and M1PWM7) */
SysCtlPWMClockSet(SYSCTL_PWMDIV_2);
SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinConfigure(GPIO_PF2_M1PWM6);
GPIOPinConfigure(GPIO_PF3_M1PWM7);
GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3);
}
#endif /* RT_USING_PWM */
#ifdef RT_USING_SPI
void spi_hw_config(void)
{
/* SPI0 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
//GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);
}
#endif /* RT_USING_SPI */
/************************** end of file ******************/
bsp/tm4c123bsp/board/tm4c123_config.h
+25 -10
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@@ -1,23 +1,38 @@
#ifndef _TM4C123GH6PZ_CONFIG_H_
#define _TM4C123GH6PZ_CONFIG_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __TM4C123GH6PZ_CONFIG_H__
#define __TM4C123GH6PZ_CONFIG_H__
#ifdef __cplusplus
extern "C" {
#endif
void uart_hw_config(void);
void pwm_hw_config(void);
#ifdef RT_USING_SERIAL
void uart_hw_config(void);
#endif /* RT_USING_SERIAL */
#ifdef RT_USING_ADC
void adc_hw_config(void);
void spi_hw_config(void);
#endif /* RT_USING_ADC */
#ifdef RT_USING_PWM
void pwm_hw_config(void);
#endif /* RT_USING_PWM */
#ifdef RT_USING_SPI
void spi_hw_config(void);
#endif /* RT_USING_SPI */
#ifdef __cplusplus
}
#endif
#endif /*__TM4C123GH6PZ_CONFIG_H__*/
#endif /*_TM4C123GH6PZ_CONFIG_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h
+13 -6
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@@ -1,13 +1,20 @@
#ifndef _ADC_CONFIG_H_
#define _ADC_CONFIG_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC0
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
@@ -36,10 +43,10 @@ extern "C" {
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef __cplusplus
}
#endif
#endif /*__ADC_CONFIG_H__*/
#endif /*_ADC_CONFIG_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h
+14 -8
View File
@@ -1,7 +1,15 @@
#ifndef _PWM_CONFIG_H_
#define _PWM_CONFIG_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#ifdef __cplusplus
extern "C" {
@@ -102,13 +110,11 @@ extern "C" {
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_PWM7 */
#ifdef __cplusplus
}
#endif
#endif /*__PWM_CONFIG_H__*/
#endif /*_PWM_CONFIG_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h
+12 -2
View File
@@ -1,3 +1,13 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
@@ -17,7 +27,6 @@ extern "C" {
#endif /* SPI0_BUS_CONFIG */
#endif /* BSP_USING_SPI0 */
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
@@ -38,7 +47,6 @@ extern "C" {
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
@@ -54,3 +62,5 @@ extern "C" {
#endif
#endif /*__SPI_CONFIG_H__ */
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h
+11 -2
View File
@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
@@ -6,7 +15,6 @@
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
@@ -63,5 +71,6 @@ extern "C" {
}
#endif
#endif
#endif /* __UART_CONFIG_H__ */
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/drv_adc.c
+51 -56
View File
@@ -1,19 +1,24 @@
#include "drv_adc.h"
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#include "drv_adc.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "adc.h"
#include "sysctl.h"
#include "inc/hw_memmap.h"
#include "driverlib/adc.h"
#include "driverlib/sysctl.h"
#ifdef RT_USING_ADC
#include "adc_config.h"
#include "tm4c123_config.h"
#include <string.h>
#define LOG_TAG "drv.adc"
#include <drv_log.h>
@@ -23,11 +28,9 @@ static struct tm4c123_adc_config adc_config[] =
#ifdef BSP_USING_ADC0
ADC0_CONFIG,
#endif
#ifdef BSP_USING_ADC1
ADC1_CONFIG,
#endif
};
struct tm4c123_adc
@@ -36,56 +39,46 @@ struct tm4c123_adc
struct rt_adc_device adc_device;
};
static struct tm4c123_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])]={0};
static struct tm4c123_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0};
static rt_err_t tm4c123_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
RT_ASSERT(device != RT_NULL);
//stm32_adc_handler = device->parent.user_data;
struct tm4c123_adc_config *config = (struct tm4c123_adc_config *)device->parent.user_data;
if (enabled)
{
ADCSequenceEnable(ADC0_BASE, 2);
ADCIntClear(ADC0_BASE, 2);
ADCSequenceEnable(config->adcbase, config->sequence);
ADCIntClear(config->adcbase, config->sequence);
}
else
{
ADCSequenceDisable(ADC0_BASE, 2);
ADCSequenceDisable(config->adcbase, config->sequence);
}
return RT_EOK;
}
static rt_err_t tm4c123_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
uint32_t pui32ADC0Value[4]={0};
// Trigger the ADC conversion.
//
ADCProcessorTrigger(ADC0_BASE, 2);
uint32_t pui32ADC0Value[4] = {0};
struct tm4c123_adc_config *config = (struct tm4c123_adc_config *)device->parent.user_data;
//
// Wait for conversion to be completed.
//
while(!ADCIntStatus(ADC0_BASE, 2, false))
/* Trigger the ADC conversion. */
ADCProcessorTrigger(config->adcbase, config->sequence);
while (!ADCIntStatus(config->adcbase, config->sequence, false))
{
}
//
// Clear the ADC interrupt flag.
//
ADCIntClear(ADC0_BASE, 2);
//
// Read ADC Value.
//
ADCSequenceDataGet(ADC0_BASE, 2, pui32ADC0Value);
/* Clear the ADC interrupt flag. */
ADCIntClear(config->adcbase, config->sequence);
/* Read ADC Value. */
ADCSequenceDataGet(config->adcbase, config->sequence, pui32ADC0Value);
/* get ADC value */
*value = (rt_uint32_t)pui32ADC0Value[channel];
@@ -102,39 +95,39 @@ static const struct rt_adc_ops tm4c123_adc_ops =
static rt_err_t tm4c123_hw_adc_init(struct tm4c123_adc *device)
{
uint32_t adcbase = device->config->adcbase;
uint32_t sequencenum = device->config->sequence;
ADCSequenceConfigure(adcbase, sequencenum,
device->config->trigermode, 0);
ADCSequenceConfigure(adcbase, sequencenum,
device->config->trigermode, 0);
ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH7 );
ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH6 | ADC_CTL_IE );
ADCSequenceStepConfigure(ADC0_BASE, 2, 2, ADC_CTL_CH5 );
//Tell the ADC logic
// that this is the last conversion on sequence 3 (ADC_CTL_END).
ADCSequenceStepConfigure(ADC0_BASE, 2, 3, ADC_CTL_CH4 | ADC_CTL_IE |
ADC_CTL_END);
return RT_EOK;
ADCSequenceStepConfigure(adcbase, sequencenum, 0, ADC_CTL_CH7);
ADCSequenceStepConfigure(adcbase, sequencenum, 1, ADC_CTL_CH6 | ADC_CTL_IE);
ADCSequenceStepConfigure(adcbase, sequencenum, 2, ADC_CTL_CH5);
/*Tell the ADC logic
that this is the last conversion on sequence 3 (ADC_CTL_END). */
ADCSequenceStepConfigure(adcbase, sequencenum, 3, ADC_CTL_CH4 | ADC_CTL_IE |
ADC_CTL_END);
return RT_EOK;
}
static int tm4c123_adc_init(void)
{
int i = 0;
rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct tm4c123_adc);
rt_err_t result = RT_EOK;
int i = 0;
rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct tm4c123_adc);
rt_err_t result = RT_EOK;
adc_hw_config();
adc_hw_config();
for (i = 0; i < obj_num; i++)
{
/* ADC init */
adc_obj[i].config = &adc_config[i];
if(tm4c123_hw_adc_init(&adc_obj[i])!= RT_EOK)
if (tm4c123_hw_adc_init(&adc_obj[i]) != RT_EOK)
{
LOG_E("%s init failed", adc_obj[i].config->name);
result = -RT_ERROR;
@@ -143,9 +136,9 @@ static int tm4c123_adc_init(void)
else
{
LOG_D("%s init success", adc_obj[i].config->name);
/* register adc device */
if (rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].config->name, &tm4c123_adc_ops,RT_NULL) == RT_EOK)
if (rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].config->name, &tm4c123_adc_ops, &adc_config[i]) == RT_EOK)
{
LOG_D("%s register success", adc_obj[i].config->name);
}
@@ -162,3 +155,5 @@ static int tm4c123_adc_init(void)
INIT_APP_EXPORT(tm4c123_adc_init);
#endif /*RT_UING_ADC*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/drv_adc.h
+18 -7
View File
@@ -1,6 +1,16 @@
#ifndef _DRV_ADC_H_
#define _DRV_ADC_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#include<stdint.h>
#include<rtthread.h>
#include<rtdevice.h>
@@ -8,13 +18,14 @@
struct tm4c123_adc_config
{
const char *name;
uint32_t adcbase;
uint32_t channel;
uint32_t sequence;
uint32_t trigermode;
uint32_t sequencepriority;
const char *name;
uint32_t adcbase;
uint32_t channel;
uint32_t sequence;
uint32_t trigermode;
uint32_t sequencepriority;
};
#endif /*_DRV_ADC_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/drv_flash/drv_flash.h
-31
View File
@@ -1,31 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int stm32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */
bsp/tm4c123bsp/libraries/Drivers/drv_flash/drv_flash_f1.c
-197
View File
@@ -1,197 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t addr)
{
uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
if ((end_addr) > STM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
while (addr < end_addr)
{
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
}
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
uint32_t PAGEError = 0;
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef EraseInitStruct;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
/* Fill EraseInit structure*/
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.PageAddress = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
{
result = -RT_ERROR;
goto __exit;
}
__exit:
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
#if defined(PKG_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */
bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c
+79 -111
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bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h
+20 -10
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@@ -1,19 +1,28 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef _DRV_GPIO_H_
#define _DRV_GPIO_H_
#include <stdint.h>
#include <rtthread.h>
#define _TM4C_PIN(index, gpioport, gpio_index) \
{ \
index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index \
}
#define _TM4C_PIN_RESERVE \
{ \
-1, 0, 0 \
}
#define _TM4C_PIN(index, gpioport, gpio_index) \
{ \
index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index \
}
#define _TM4C_PIN_RESERVE \
{ \
-1, 0, 0 \
}
/* TM4C123 GPIO driver*/
struct pin_index
@@ -27,3 +36,4 @@ extern int rt_hw_pin_init(void);
#endif /*_DRV_GPIO_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/drv_log.h
+4 -4
View File
@@ -13,15 +13,15 @@
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c
+203 -214
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bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h
+19 -11
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@@ -1,28 +1,36 @@
#ifndef _DRV_PWM_H_
#define _DRV_PWM_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include<rtdevice.h>
#include<rthw.h>
struct tm4c123_pwm
{
struct tm4c123_pwm_config *config;
struct rt_device_pwm pwm_device;
struct tm4c123_pwm_config *config;
struct rt_device_pwm pwm_device;
};
/* tm4c123 config class */
struct tm4c123_pwm_config
{
rt_uint8_t channel;
char *name;
uint32_t counterMode;
uint32_t syncMode;
rt_uint8_t channel;
char *name;
uint32_t counterMode;
uint32_t syncMode;
};
int rt_hw_pwm_init(void);
#endif /*__DRV_PWM_H__*/
#endif /*_DRV_PWM_H_*/
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/drv_spi.c
+54 -50
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bsp/tm4c123bsp/libraries/Drivers/drv_spi.h
+15 -11
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@@ -1,5 +1,15 @@
#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtdevice.h>
#include <rthw.h>
@@ -16,7 +26,7 @@ struct tm4c123_hw_spi_cs
struct tm4c123_spi_config
{
uint32_t base;
char * bus_name;
char *bus_name;
};
/* tm4c123 spi dirver class */
@@ -24,7 +34,6 @@ struct tm4c123_spi
{
struct tm4c123_spi_config *config;
struct rt_spi_configuration *cfg;
struct rt_spi_bus spi_bus;
};
@@ -35,11 +44,6 @@ struct tm4c123_spi_device
char *device_name;
};
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
#endif /*__DRV_SPI_H_ */
#endif /*__DRV_SPI_H__ */
/************************** end of file ******************/
bsp/tm4c123bsp/libraries/Drivers/drv_uart.c
+63 -160
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bsp/tm4c123bsp/libraries/Drivers/drv_uart.h
+21 -12
View File
@@ -1,5 +1,15 @@
#ifndef _DRV_UART_H_
#define _DRV_UART_H_
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-27 AHTYDHD the first version
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include <stdint.h>
#include <rthw.h>
@@ -10,29 +20,28 @@
struct tm4c123_uart_config
{
const char *name;
uint32_t uartbase;
uint32_t baudrate;
uint32_t mode;
uint32_t uartbase;
uint32_t baudrate;
uint32_t mode;
//struct dma_config *dma_rx;
//struct dma_config *dma_tx;
};
/* tm4c123 uart dirver class */
struct tm4c123_uart
{
{
struct tm4c123_uart_config *config;
uint32_t uartintbase;
uint32_t uartintbase;
#ifdef RT_SERIAL_USING_DMA
#endif
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
extern int rt_hw_usart_init(void);
#endif /*_DRV_UART_H_*/
#endif /*__DRV_UART_H__*/
/************************** end of file ******************/